[powerpc] Full merge of PowerPC disassembler PRs, including:

* Remove dependency on capstone for PowerPC disassembly #6292
* Add support for PowerPC VLE instruction set #6740
* Add support for paired-single instructions #6821
* Various post-merge fixes and tweaks to disassembly and lifting
* Removal of dependence on capstone for assembler's scoring mechanism (capstone currently disabled, but not removed from codebase yet)

1 files changed, 866 insertions, 1486 deletions

diff --git a/arch/powerpc/il.cpp b/arch/powerpc/il.cpp
index ad8e29a5..b288561a 100644
--- a/arch/powerpc/il.cpp
+++ b/arch/powerpc/il.cpp
@@ -1,23 +1,15 @@
 #include "lowlevelilinstruction.h"
-#include <binaryninjaapi.h>
+#include "binaryninjaapi.h"
 
 #include "disassembler.h"
 
+#include "decode/decode.h"
+
 using namespace BinaryNinja;
 
 #include "il.h"
 #include "util.h"
 
-#define OTI_SEXT32_REGS 1
-#define OTI_SEXT64_REGS 2
-#define OTI_ZEXT32_REGS 4
-#define OTI_ZEXT64_REGS 8
-#define OTI_SEXT32_IMMS 16
-#define OTI_SEXT64_IMMS 32
-#define OTI_ZEXT32_IMMS 64
-#define OTI_ZEXT64_IMMS 128
-#define OTI_IMM_CPTR 256
-#define OTI_IMM_REL_CPTR 512
 #define OTI_IMM_BIAS 1024
 #define OTI_GPR0_ZERO 2048
 
@@ -32,144 +24,107 @@ static uint32_t genMask(uint32_t mb, uint32_t me)
 	return (mb <= me) ? (maskBegin & maskEnd) : (maskBegin | maskEnd);
 }
 
+static uint64_t genMask64(uint32_t mb, uint32_t me)
+{
+	uint64_t maskBegin = ~0ull >> mb;
+	uint64_t maskEnd = ~0ull << (63 - me);
+
+	return (mb <= me) ? (maskBegin & maskEnd) : (maskBegin | maskEnd);
+}
+
 #define PPC_IL_OPTIONS_DEFAULT	0
 #define PPC_IL_EXTRA_DEFAULT	0
 #define RZF 4
 
-static ExprId operToIL(LowLevelILFunction &il, struct cs_ppc_op *op,
+static ExprId operToIL(LowLevelILFunction &il, Operand* op,
 	int options=PPC_IL_OPTIONS_DEFAULT, uint64_t extra=PPC_IL_EXTRA_DEFAULT, size_t regsz=4)
 {
 	ExprId res;
 
-	if(!op) {
+	if (!op)
+	{
 		MYLOG("ERROR: operToIL() got NULL operand\n");
 		return il.Unimplemented();
 	}
 
-	switch(op->type) {
-		case PPC_OP_REG:
-			//MYLOG("case PPC_OP_REG returning reg %d\n", op->reg);
-			if (options & OTI_GPR0_ZERO && op->reg == PPC_REG_R0)
+	switch (op->cls)
+	{
+		case PPC_OP_REG_RA:
+		case PPC_OP_REG_RB:
+		case PPC_OP_REG_RC:  // XXX: valid?
+		case PPC_OP_REG_RD:
+		case PPC_OP_REG_RS:
+		case PPC_OP_REG_FRA:
+		case PPC_OP_REG_FRB:
+		case PPC_OP_REG_FRC:
+		case PPC_OP_REG_FRD:
+		case PPC_OP_REG_FRS:
+			if (options & OTI_GPR0_ZERO && op->reg == PPC_REG_GPR0)
 				res = il.Const(regsz, 0);
 			else
 				res = il.Register(regsz, op->reg);
 			break;
-		case PPC_OP_IMM:
-			/* the immediate is a constant pointer (eg: absolute address) */
-			if(options & OTI_IMM_CPTR) {
-				res = il.ConstPointer(regsz, op->imm);
+
+		case PPC_OP_SIMM:
+			if (options & OTI_IMM_BIAS)
+			{
+				/* the immediate should be biased with given value */
+				res = il.Const(regsz, op->simm + extra);
 			}
-			/* the immediate is a displacement (eg: relative addressing) */
-			else if(options & OTI_IMM_REL_CPTR) {
-				res = il.ConstPointer(regsz, op->imm + extra);
+			else
+			{
+				/* the immediate is just a plain boring immediate */
+				res = il.Const(regsz, op->simm);
 			}
-			/* the immediate should be biased with given value */
-			else if(options & OTI_IMM_BIAS) {
-				res = il.Const(regsz, op->imm + extra);
+			break;
+
+		case PPC_OP_UIMM:
+			if (options & OTI_IMM_BIAS)
+			{
+				/* the immediate should be biased with given value */
+				res = il.Const(regsz, op->uimm + extra);
 			}
-			/* the immediate is just a plain boring immediate */
-			else {
-				res = il.Const(regsz, op->imm);
+			else
+			{
+				/* the immediate is just a plain boring immediate */
+				res = il.Const(regsz, op->uimm);
 			}
 			break;
 
-		case PPC_OP_MEM:
-			//MYLOG("case PPC_OP_MEM returning regs (%d,%d)\n", op->mem.base, op->mem.disp);
-
-			if (options & OTI_GPR0_ZERO && op->mem.base == PPC_REG_R0)
+		case PPC_OP_MEM_RA:
+			if (options & OTI_GPR0_ZERO && op->mem.reg == PPC_REG_GPR0)
 				res = il.Const(regsz, 0);
 			else
-				res = il.Register(regsz, op->mem.base);
+				res = il.Register(regsz, op->mem.reg);
 
 			if(options & OTI_IMM_BIAS)
-				res = il.Add(regsz, res, il.Const(4, op->mem.disp + extra));
+				res = il.Add(regsz, res, il.Const(regsz, op->mem.offset + extra));
 			else
-				res = il.Add(regsz, res, il.Const(4, op->mem.disp));
+				res = il.Add(regsz, res, il.Const(regsz, op->mem.offset));
 			break;
 
-		case PPC_OP_CRX:
-		case PPC_OP_INVALID:
+		case PPC_OP_NONE:
 		default:
 			MYLOG("ERROR: don't know how to convert operand to IL\n");
 			res = il.Unimplemented();
 	}
 
-	switch(options) {
-		case OTI_SEXT32_REGS:
-			if(op->type == PPC_OP_REG)
-				res = il.SignExtend(4, res);
-			break;
-		case OTI_SEXT64_REGS:
-			if(op->type == PPC_OP_REG)
-				res = il.SignExtend(8, res);
-			break;
-		case OTI_ZEXT32_REGS:
-			if(op->type == PPC_OP_REG)
-				res = il.ZeroExtend(4, res);
-			break;
-		case OTI_ZEXT64_REGS:
-			if(op->type == PPC_OP_REG)
-				res = il.ZeroExtend(8, res);
-			break;
-		case OTI_SEXT32_IMMS:
-			if(op->type == PPC_OP_REG)
-				res = il.SignExtend(4, res);
-			break;
-		case OTI_SEXT64_IMMS:
-			if(op->type == PPC_OP_REG)
-				res = il.SignExtend(8, res);
-			break;
-		case OTI_ZEXT32_IMMS:
-			if(op->type == PPC_OP_REG)
-				res = il.ZeroExtend(4, res);
-			break;
-		case OTI_ZEXT64_IMMS:
-			if(op->type == PPC_OP_REG)
-				res = il.ZeroExtend(8, res);
-			break;
-	}
-
 	return res;
 }
 
 #define operToIL_a(il, op, regSz) operToIL(il, op, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, regSz)
 
 /* map PPC_REG_CRX to an IL flagwrite type (a named set of written flags */
-int crxToFlagWriteType(int crx, bool signedComparison = true)
+int crxToFlagWriteType(Register reg, ppc_suf suf)
 {
-	// MYLOG("%s() crx:%d", __func__, crx);
-	int flag_out = 0;
-	int crx_local = 0;
-	int crx_type = 0;
-	int crx_index = 0;
-	int suf = 0;
-
-	crx_local = crx & PPC_CRX_REG_MASK;
-	crx_type = crx & PPC_CRX_FLOAT_MASK;
-	if ((crx_local < PPC_REG_CR0) || (crx_local > PPC_REG_CR7))
-	{
-		goto fail;
-	}
-
-	crx_index = crx_local - PPC_REG_CR0;
-
-	if (crx_type != 0)
-	{
-		suf = PPC_SUF_F;
-	}
-	else if (signedComparison == false)
-	{
-		suf = PPC_SUF_U;
-	}
+	if ((reg < PPC_REG_CRF0) || (reg > PPC_REG_CRF7))
+		return IL_FLAGWRITE_NONE;
 
 	/* when we have more flags... */
-	flag_out = (crx_index * PPC_SUF_SZ) + IL_FLAGWRITE_CR0_S + suf;
-	
-fail:
-	return flag_out;
+	int crx_index = reg - PPC_REG_CRF0;
+	return (crx_index * PPC_SUF_SZ) + IL_FLAGWRITE_CR0_S + suf;
 }
 
-
 static ExprId ExtractConditionClause(LowLevelILFunction& il, uint8_t crBit, bool negate = false)
 {
 	// MYLOG("%s() crbit:%x", __func__, crBit);
@@ -242,55 +197,34 @@ static bool LiftConditionalBranch(LowLevelILFunction& il, uint8_t bo, uint8_t bi
 	return isConditional;
 }
 
-static bool LiftBranches(Architecture* arch, LowLevelILFunction &il, const uint8_t* data, uint64_t addr, bool le)
+static bool LiftBranches(Architecture* arch, LowLevelILFunction &il, const Instruction *instruction, uint64_t addr)
 {
-	// MYLOG("%s() addr:0x%08llx\n", __func__, addr);
-	uint32_t insn = *(const uint32_t *) data;
-	bool lk;
 	size_t addressSize_l = arch->GetAddressSize();
-
-	if (!le)
-	{
-		insn = bswap32(insn);
-	}
-
-	lk = insn & 1;
-
-	switch (insn >> 26)
+	switch (instruction->id)
 	{
-		case PPC_INS_BCA: /* b (b, ba, bl, bla) */
+		case PPC_ID_Bx:
 		{
-			uint64_t target = insn & 0x03fffffc;
-
-			/* sign extend target */
-			target = sign_extend(addressSize_l, target, 25);
-
-			/* account for absolute addressing */
-			if (!(insn & 2))
-			{
-				target += addr;
-				ADDRMASK(addressSize_l, target);
-			}
+			uint64_t target = instruction->operands[0].label;
 
 			BNLowLevelILLabel* label = il.GetLabelForAddress(arch, target);
 
-			if (label && !(lk && (target != (addr+4))))
+			if (label && !(instruction->flags.lk && (target != (addr+instruction->numBytes))))
 			{
 				/* branch to an instruction within the same function -- take
 				 * 'lk' bit behavior into account, but don't emit as a call
 				 */
-				if (lk)
+				if (instruction->flags.lk)
 				{
-					il.AddInstruction(il.SetRegister(addressSize_l, PPC_REG_LR, il.ConstPointer(addressSize_l, addr + 4)));
+					il.AddInstruction(il.SetRegister(addressSize_l, PPC_REG_LR, il.ConstPointer(addressSize_l, addr + instruction->numBytes)));
 				}	
 
 				il.AddInstruction(il.Goto(*label));
 			}
 			else
 			{
-				ExprId dest = il.ConstPointer(4, target);
+				ExprId dest = il.ConstPointer(addressSize_l, target);
 
-				if (lk)
+				if (instruction->flags.lk)
 					il.AddInstruction(il.Call(dest));
 				else
 					il.AddInstruction(il.Jump(dest));
@@ -298,28 +232,51 @@ static bool LiftBranches(Architecture* arch, LowLevelILFunction &il, const uint8
 
 			break;
 		}
-		case PPC_INS_BA: /* bc */
+		case PPC_ID_BCx: /* bc */
+		case PPC_ID_VLE_E_BCx:
+		case PPC_ID_VLE_SE_BC:
 		{
-			uint64_t target = insn & 0xfffc;
-			uint8_t bo = (insn >> 21) & 0x1f;
-			uint8_t bi = (insn >> 16) & 0x1f;
-
-			/* sign extend target */
-			target = sign_extend(addressSize_l, target, 15);
+			uint8_t bo = instruction->operands[0].uimm;
+			uint8_t bi = instruction->operands[1].uimm;
+			uint64_t target = instruction->operands[2].label;
 
-			/* account for absolute addressing */
-			if (!(insn & 2))
+			if (instruction->id == PPC_ID_VLE_E_BCx)
+			{
+				// Table 2-5. BO32 Field Encodings in VLEPEM,
+				// mapped to their equivalent BO fields for
+				// normal BC instructions
+				//
+				// 0b00 -> branch if condition false    | 0b00100
+				// 0b01 -> branch if condition true     | 0b01100
+				// 0b10 -> dec CTR, branch if CTR != 0  | 0b10000
+				// 0b11 -> dec CTR, branch if CTR == 0  | 0b10010
+				switch (bo)
+				{
+					case 0: bo = 0x04; break;
+					case 1: bo = 0x0c; break;
+					case 2: bo = 0x10; break;
+					case 3: bo = 0x12; break;
+					default:
+						; // unreachable
+				}
+			}
+			else if (instruction->id == PPC_ID_VLE_SE_BC)
 			{
-				target += addr;
-				ADDRMASK(addressSize_l, target);
+				// Table 2-6. BO16 Field Encodings in VLEPEM,
+				// mapped to their equivalent BO fields for
+				// normal BC instructions
+				//
+				// 0b0 -> branch if condition false    | 0b00100
+				// 0b1 -> branch if condition true     | 0b01100
+				bo = (bo << 3) | 0x4;
 			}
 
 			BNLowLevelILLabel *existingTakenLabel = il.GetLabelForAddress(arch, target);
-			BNLowLevelILLabel *existingFalseLabel = il.GetLabelForAddress(arch, addr + 4);
+			BNLowLevelILLabel *existingFalseLabel = il.GetLabelForAddress(arch, addr + instruction->numBytes);
 
-			if (lk)
+			if (instruction->flags.lk)
 			{
-				il.AddInstruction(il.SetRegister(addressSize_l, PPC_REG_LR, il.ConstPointer(addressSize_l, addr + 4)));
+				il.AddInstruction(il.SetRegister(addressSize_l, PPC_REG_LR, il.ConstPointer(addressSize_l, addr + instruction->numBytes)));
 			}
 
 			LowLevelILLabel takenLabelManual, falseLabelManual;
@@ -343,9 +300,9 @@ static bool LiftBranches(Architecture* arch, LowLevelILFunction &il, const uint8
 			{
 				il.AddInstruction(il.Goto(*takenLabel));
 			}
-			else if (target != addr + 4)
+			else if (target != addr + instruction->numBytes)
 			{
-				if (lk)
+				if (instruction->flags.lk)
 				{
 					il.AddInstruction(il.Call(il.ConstPointer(addressSize_l, target)));
 					if (wasConditionalBranch)
@@ -364,29 +321,30 @@ static bool LiftBranches(Architecture* arch, LowLevelILFunction &il, const uint8
 
 			break;
 		}
-		case PPC_INS_BCCTR: /* bcctr, bclr */
+		case PPC_ID_BCCTRx: /* bcctr, bclr */
+		case PPC_ID_BCLRx:
 		{
-			uint8_t bo = (insn >> 21) & 0x1f;
-			uint8_t bi = (insn >> 16) & 0x1f;
+			uint8_t bo = instruction->operands[0].uimm;
+			uint8_t bi = instruction->operands[1].uimm;
 			bool blr = false;
 			ExprId expr;
-
-			switch ((insn >> 1) & 0x3ff)
+			switch (instruction->id)
 			{
-				case 16:
-					expr = il.Register(addressSize_l, PPC_REG_LR);
-					blr = true;
-					break;
-				case 528:
-					if (!(bo & 4))
+				case PPC_ID_BCCTRx:
+					if (!(bo & 0x4))
 						return false;
 					expr = il.Register(addressSize_l, PPC_REG_CTR);
+					blr = false;
+					break;
+				case PPC_ID_BCLRx:
+					expr = il.Register(addressSize_l, PPC_REG_LR);
+					blr = true;
 					break;
 				default:
 					return false;
 			}
 
-			BNLowLevelILLabel *existingFalseLabel = il.GetLabelForAddress(arch, addr + 4);
+			BNLowLevelILLabel *existingFalseLabel = il.GetLabelForAddress(arch, addr + instruction->numBytes);
 			BNLowLevelILLabel* falseLabel = existingFalseLabel;
 
 			LowLevelILLabel takenLabel, falseLabelManual;
@@ -399,7 +357,7 @@ static bool LiftBranches(Architecture* arch, LowLevelILFunction &il, const uint8
 			if (wasConditionalBranch)
 				il.MarkLabel(takenLabel);
 
-			if (lk)
+			if (instruction->flags.lk)
 			{
 				il.AddInstruction(il.Call(expr));
 				if (wasConditionalBranch)
@@ -415,6 +373,24 @@ static bool LiftBranches(Architecture* arch, LowLevelILFunction &il, const uint8
 
 			break;
 		}
+		case PPC_ID_VLE_SE_BLRx:
+		{
+			if (instruction->flags.lk)
+				il.AddInstruction(il.Call(il.Register(addressSize_l, PPC_REG_LR)));
+			else
+				il.AddInstruction(il.Return(il.Register(addressSize_l, PPC_REG_LR)));
+
+			break;
+		}
+		case PPC_ID_VLE_SE_BCTRx:
+		{
+			if (instruction->flags.lk)
+				il.AddInstruction(il.Call(il.Register(addressSize_l, PPC_REG_CTR)));
+			else
+				il.AddInstruction(il.Jump(il.Register(addressSize_l, PPC_REG_CTR)));
+
+			break;
+		}
 		default:
 			return false;
 	}
@@ -455,67 +431,67 @@ static ExprId ByteReverseRegister(LowLevelILFunction &il, uint32_t reg, size_t s
 }
 
 
-static void ByteReversedLoad(LowLevelILFunction &il, struct cs_ppc* ppc, size_t size, size_t addressSize_a=4)
+static void ByteReversedLoad(LowLevelILFunction &il, Instruction* instruction, size_t size, size_t address_size_a=4)
 {
-	ExprId addr = operToIL(il, &ppc->operands[1], OTI_GPR0_ZERO, PPC_IL_EXTRA_DEFAULT, addressSize_a);                  // (rA|0)
-	ExprId  val = il.Load(size, il.Add(addressSize_a, addr, operToIL_a(il, &ppc->operands[2], addressSize_a))); // [(rA|0) + (rB)]
+	ExprId addr = operToIL(il, &instruction->operands[1], OTI_GPR0_ZERO, PPC_IL_EXTRA_DEFAULT, address_size_a);          // (rA|0)
+	ExprId  val = il.Load(size, il.Add(address_size_a, addr, operToIL_a(il, &instruction->operands[2], address_size_a))); // [(rA|0) + (rB)]
 
-	if (size < addressSize_a)
+	if (size < address_size_a)
 	{
-		val = il.ZeroExtend(addressSize_a, val);
+		val = il.ZeroExtend(address_size_a, val);
 	}
 
 	/* set reg immediately; this will cause xrefs to be sized correctly,
 	 * we'll use this as the scratch while we calculate the swapped value */
-	il.AddInstruction(il.SetRegister(addressSize_a, ppc->operands[0].reg, val));               // rD = [(rA|0) + (rB)]
-	ExprId swap = ByteReverseRegister(il, ppc->operands[0].reg, size);
+	il.AddInstruction(il.SetRegister(address_size_a, instruction->operands[0].reg, val));               // rD = [(rA|0) + (rB)]
+	ExprId swap = ByteReverseRegister(il, instruction->operands[0].reg, size);
 
-	il.AddInstruction(il.SetRegister(addressSize_a, ppc->operands[0].reg, swap));              // rD = swap([(rA|0) + (rB)])
+	il.AddInstruction(il.SetRegister(address_size_a, instruction->operands[0].reg, swap));              // rD = swap([(rA|0) + (rB)])
 }
 
-static void ByteReversedStore(LowLevelILFunction &il, struct cs_ppc* ppc, size_t size, size_t addressSize_a=4)
+static void ByteReversedStore(LowLevelILFunction &il, Instruction* instruction, size_t size, size_t addressSize_a=4)
 {
-	ExprId addr = operToIL(il, &ppc->operands[1], OTI_GPR0_ZERO, PPC_IL_EXTRA_DEFAULT, addressSize_a);     // (rA|0)
-	addr = il.Add(addressSize_a, addr, operToIL_a(il, &ppc->operands[2], addressSize_a));          // (rA|0) + (rB)
-	ExprId val = ByteReverseRegister(il, ppc->operands[0].reg, size); // rS = swap(rS)
-	il.AddInstruction(il.Store(size, addr, val));                     // [(rA|0) + (rB)] = swap(rS)
+	ExprId addr = operToIL(il, &instruction->operands[1], OTI_GPR0_ZERO, PPC_IL_EXTRA_DEFAULT, addressSize_a);   // (rA|0)
+	addr = il.Add(addressSize_a, addr, operToIL_a(il, &instruction->operands[2], addressSize_a));          // (rA|0) + (rB)
+	ExprId val = ByteReverseRegister(il, instruction->operands[0].reg, size); // rS = swap(rS)
+	il.AddInstruction(il.Store(size, addr, val));                             // [(rA|0) + (rB)] = swap(rS)
 }
 
-static void loadstoreppcfs(LowLevelILFunction& il,
-	int load_store_sz,
-	cs_ppc_op* operand1, /* register that gets read/written */
-	cs_ppc_op* operand2, /* location the read/write occurs */
-	cs_ppc_op* operand3=0,
+static void load_float(LowLevelILFunction& il,
+	int load_sz,
+	Operand* operand1, /* register that gets read/written */
+	Operand* operand2, /* location the read/write occurs */
+	Operand* operand3=0,
 	bool update=false
 	)
 {
-	ExprId tmp = 0;
+	ExprId tmp = BN_INVALID_EXPR;
 	const int addrsz = 4;
 	// assume single
-	if (!load_store_sz)
-		load_store_sz = 4;
+	if (!load_sz)
+		load_sz = 4;
 
 	// operand1.reg = [operand2.reg + operand2.imm]
-	if (operand2->type == PPC_OP_MEM)
+	if (operand2->cls == PPC_OP_MEM_RA)
 	{
-		if (operand2->mem.disp == 0)
+		if (operand2->mem.reg == 0)
 		{
-			tmp = il.Register(4, operand2->mem.base);
+			tmp = il.Const(addrsz, operand2->mem.offset);
 		}
 		else
 		{
-			tmp = il.Add(addrsz, il.Register(addrsz, operand2->mem.base), il.Const(addrsz, operand2->mem.disp));
+			tmp = il.Add(addrsz, il.Register(addrsz, operand2->mem.reg), il.Const(addrsz, operand2->mem.offset));
 		}		
 	}
-	else if(operand2->type == PPC_OP_REG)
+	else if(operand2->cls == PPC_OP_REG_RA)
 	{
-		if ((operand3 != 0) && (operand3->type == PPC_OP_REG))
+		if ((operand3 != 0) && (operand3->cls == PPC_OP_REG_RB))
 		{
 			tmp = il.Add(4, il.Register(addrsz, operand2->reg), il.Register(addrsz, operand3->reg));
 		}
 	}
 
-	il.AddInstruction(il.SetRegister(load_store_sz, operand1->reg, il.FloatConvert(load_store_sz, il.Operand(1, il.Load(load_store_sz, tmp)))));
+	il.AddInstruction(il.SetRegister(load_sz, operand1->reg, il.FloatConvert(load_sz, il.Operand(1, il.Load(load_sz, tmp)))));
 	
 	if (update == true)
 	{
@@ -527,100 +503,43 @@ static void loadstoreppcfs(LowLevelILFunction& il,
 /* returns TRUE - if this IL continues
           FALSE - if this IL terminates a block */
 bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
-  const uint8_t* data, uint64_t addr, decomp_result *res, bool le)
+	Instruction* instruction, uint64_t addr)
 {
-	int i;
-	bool rc = true;
-	struct cs_insn *insn = 0;
-	struct cs_detail *detail = 0;
-	struct cs_ppc *ppc = 0;
-	size_t addressSize_l = 0;
-	int extend_l = 0;
-	uint32_t rawInsn = *(const uint32_t *) data;
-
-	// for ppc_ps
-	// ppc_reg_bn gqr_l = (ppc_reg_bn)0;
-	// int w_l = 0;
-
-	addressSize_l = arch->GetAddressSize();
-	if (!le)
-	{
-		rawInsn = bswap32(rawInsn);
-	}
-
-
-	/* bypass capstone path for *all* branching instructions; capstone
-	 * is too difficult to work with and is outright broken for some
-	 * branch instructions (bdnz, etc.)
-	 */
-	if (LiftBranches(arch, il, data, addr, le))
+	if (LiftBranches(arch, il, instruction, addr))
 		return true;
 
-	insn = &(res->insn);
-	detail = &(res->detail);
-	ppc = &(detail->ppc);
+	int i;
+	size_t addressSize_l = arch->GetAddressSize();
+	size_t opSize = 4;
 
-	/* There is a simplifying reduction available for:
-	 *   rlwinm <reg>, <reg>, <rol_amt>, <mask_begin>, <mask_end>
-	 * When <rol_amt> == <mask_begin> == 0, this can be translated to:
-	 *   clrwi <reg>, <reg>, 31-<mask_end>
-	 *
-	 * Unfortunately capstone screws this up, replacing just the instruction id with PPC_INSN_CLRWI.
-	 * The mnemonic ("rlwinm"), operands, etc. all stay the same.
-	 */
-	if (insn->id == PPC_INS_CLRLWI && insn->mnemonic[0] == 'r')
-	{
-		insn->id = PPC_INS_RLWINM;
-	}
+	bool rc = true;
 
 	/* create convenient access to instruction operands */
-	cs_ppc_op *oper0=NULL, *oper1=NULL, *oper2=NULL, *oper3=NULL, *oper4=NULL;
+	Operand *oper0=NULL, *oper1=NULL, *oper2=NULL, *oper3=NULL, *oper4=NULL;
 	#define REQUIRE1OP if(!oper0) goto ReturnUnimpl;
 	#define REQUIRE2OPS if(!oper0 || !oper1) goto ReturnUnimpl;
 	#define REQUIRE3OPS if(!oper0 || !oper1 || !oper2) goto ReturnUnimpl;
 	#define REQUIRE4OPS if(!oper0 || !oper1 || !oper2 || !oper3) goto ReturnUnimpl;
 	#define REQUIRE5OPS if(!oper0 || !oper1 || !oper2 || !oper3 || !oper4) goto ReturnUnimpl;
 
-	switch(ppc->op_count) {
+	switch (instruction->numOperands)
+	{
 		default:
-		case 5: oper4 = &(ppc->operands[4]); FALL_THROUGH
-		case 4: oper3 = &(ppc->operands[3]); FALL_THROUGH
-		case 3: oper2 = &(ppc->operands[2]); FALL_THROUGH
-		case 2: oper1 = &(ppc->operands[1]); FALL_THROUGH
-		case 1: oper0 = &(ppc->operands[0]); FALL_THROUGH
+		case 5: oper4 = &(instruction->operands[4]); FALL_THROUGH
+		case 4: oper3 = &(instruction->operands[3]); FALL_THROUGH
+		case 3: oper2 = &(instruction->operands[2]); FALL_THROUGH
+		case 2: oper1 = &(instruction->operands[1]); FALL_THROUGH
+		case 1: oper0 = &(instruction->operands[0]); FALL_THROUGH
 		case 0: while(0);
 	}
 
-	/* for conditionals that specify a crx, treat it special */
-	if(ppc->bc != PPC_BC_INVALID) {
-		if(oper0 && oper0->type == PPC_OP_REG && oper0->reg >= PPC_REG_CR0 &&
-		  ppc->operands[0].reg <= PPC_REG_CR7) {
-			oper0 = oper1;
-			oper1 = oper2;
-			oper2 = oper3;
-			oper3 = NULL;
-		}
-	}
+	ExprId ei0 = BN_INVALID_EXPR, ei1 = BN_INVALID_EXPR, ei2 = BN_INVALID_EXPR;
 
-	if(0 && insn->id == PPC_INS_CMPLWI) {
-		MYLOG("%s() %08llx: %02X %02X %02X %02X %s %s has %d operands\n",
-			__func__, addr, data[0], data[1], data[2], data[3],
-			insn->mnemonic, insn->op_str, ppc->op_count
-		);
-
-		//printInstructionVerbose(res);
-		//MYLOG("oper0: %p\n", oper0);
-		//MYLOG("oper1: %p\n", oper1);
-		//MYLOG("oper2: %p\n", oper2);
-		//MYLOG("oper3: %p\n", oper3);
-	}
-
-	ExprId ei0 = 0, ei1 = 0, ei2 = 0;
-
-	switch(insn->id) {
+	switch (instruction->id)
+	{
 		/* add
 			"add." also updates the CR0 bits */
-		case PPC_INS_ADD: /* add */
+		case PPC_ID_ADDx: /* add */
 			REQUIRE2OPS
 			ei0 = il.Add(
 				addressSize_l,
@@ -628,12 +547,12 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 				operToIL_a(il, oper2, addressSize_l)
 			);
 			ei0 = il.SetRegister(addressSize_l, oper0->reg, ei0,
-				(insn->id == PPC_INS_ADD && ppc->update_cr0) ? IL_FLAGWRITE_CR0_S : 0
+				instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_ADDE: /* add, extended (+ carry flag) */
+		case PPC_ID_ADDEx: /* add, extended (+ carry flag) */
 			REQUIRE3OPS
 			ei0 = il.AddCarry(
 				addressSize_l,
@@ -643,15 +562,15 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 				IL_FLAGWRITE_XER_CA
 			);
 			ei0 = il.SetRegister(addressSize_l, oper0->reg, ei0,
-			  ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+				instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_ADDME: /* add, extended (+ carry flag) minus one */
-		case PPC_INS_ADDZE:
+		case PPC_ID_ADDMEx: /* add, extended (+ carry flag) minus one */
+		case PPC_ID_ADDZEx:
 			REQUIRE2OPS
-			if (insn->id == PPC_INS_ADDME)
+			if (instruction->id == PPC_ID_ADDMEx)
 				ei0 = il.Const(addressSize_l, ADDRNEG1(addressSize_l));
 			else
 				ei0 = il.Const(addressSize_l, 0);
@@ -663,13 +582,13 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 				IL_FLAGWRITE_XER_CA
 			);
 			ei0 = il.SetRegister(addressSize_l, oper0->reg, ei0,
-				ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+				instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_ADDC: /* add, carrying */
-		case PPC_INS_ADDIC: /* add immediate, carrying */
+		case PPC_ID_ADDCx: /* add, carrying */
+		case PPC_ID_ADDICx: /* add immediate, carrying */
 			REQUIRE3OPS
 			ei0 = il.Add(
 				addressSize_l,
@@ -678,18 +597,18 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 				IL_FLAGWRITE_XER_CA
 			);
 			ei0 = il.SetRegister(addressSize_l, oper0->reg, ei0,
-				ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+				instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_ADDI: /* add immediate, eg: addi rD, rA, <imm> */
-		case PPC_INS_ADDIS: /* add immediate, shifted */
+		case PPC_ID_ADDIx: /* add immediate, eg: addi rD, rA, <imm> */
+		case PPC_ID_ADDIS: /* add immediate, shifted */
 			REQUIRE2OPS
-			if (insn->id == PPC_INS_ADDIS)
-				ei0 = il.Const(addressSize_l, oper2->imm << 16);
+			if (instruction->id == PPC_ID_ADDIS)
+				ei0 = il.Const(addressSize_l, oper2->simm << 16);
 			else
-				ei0 = il.Const(addressSize_l, oper2->imm);
+				ei0 = il.Const(addressSize_l, oper2->simm);
 			ei0 = il.Add(
 				addressSize_l,
 				operToIL(il, oper1, OTI_GPR0_ZERO, PPC_IL_EXTRA_DEFAULT, addressSize_l),
@@ -699,183 +618,179 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_LIS: /* load immediate, shifted */
+		case PPC_ID_LIS: /* load immediate, shifted */
 			REQUIRE2OPS
 			ei0 = il.SetRegister(
 				addressSize_l,
 				oper0->reg,
-				il.ConstPointer(addressSize_l, oper1->imm << 16)
+				il.ConstPointer(addressSize_l, oper1->simm << 16)
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_LI: /* load immediate */
-		case PPC_INS_LA: /* load displacement */
+		case PPC_ID_LI: /* load immediate */
 			REQUIRE2OPS
 			il.AddInstruction(il.SetRegister(addressSize_l, oper0->reg, operToIL_a(il, oper1, addressSize_l)));
 			break;
 
-		case PPC_INS_AND:
-		case PPC_INS_ANDC: // and [with complement]
-		case PPC_INS_NAND:
+		case PPC_ID_ANDx:
+		case PPC_ID_ANDCx: // and [with complement]
+		case PPC_ID_NANDx:
 			REQUIRE3OPS
-			ei0 = operToIL_a(il, oper2, addressSize_l);
-			if (insn->id == PPC_INS_ANDC)
+			ei0 = operToIL(il, oper2);
+			if (instruction->id == PPC_ID_ANDCx)
 				ei0 = il.Not(addressSize_l, ei0);
-			ei0 = il.And(addressSize_l, operToIL_a(il, oper1, addressSize_l), ei0);
-			if (insn->id == PPC_INS_NAND)
+			ei0 = il.And(addressSize_l, operToIL(il, oper1), ei0);
+			if (instruction->id == PPC_ID_NANDx)
 				ei0 = il.Not(addressSize_l, ei0);
 			ei0 = il.SetRegister(addressSize_l, oper0->reg, ei0,
-				ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+				instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_ANDIS:
-		case PPC_INS_ANDI:
+		case PPC_ID_ANDIx:
+		case PPC_ID_ANDIS:
 			REQUIRE3OPS
-			if (insn->id == PPC_INS_ANDIS)
-				ei0 = il.Const(addressSize_l, oper2->imm << 16);
+			if (instruction->id == PPC_ID_ANDIS)
+				ei0 = il.Const(addressSize_l, oper2->uimm << 16);
 			else
-				ei0 = il.Const(addressSize_l, oper2->imm);
-			ei0 = il.And(addressSize_l, operToIL_a(il, oper1, addressSize_l), ei0);
-			ei0 = il.SetRegister(addressSize_l, oper0->reg, ei0, IL_FLAGWRITE_CR0_S);
+				ei0 = il.Const(addressSize_l, oper2->uimm);
+			ei0 = il.And(addressSize_l, operToIL(il, oper1), ei0);
+
+			// VLE instructions that get translated to ANDIx may
+			// not have the rc bit set
+			if (instruction->flags.rc)
+				ei0 = il.SetRegister(addressSize_l, oper0->reg, ei0, IL_FLAGWRITE_CR0_S);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_CMP:
-		case PPC_INS_CMPW: /* compare (signed) word(32-bit) */
-			REQUIRE2OPS
-			ei0 = operToIL_a(il, oper2 ? oper1 : oper0, addressSize_l);
-			ei1 = operToIL_a(il, oper2 ? oper2 : oper1, addressSize_l);
-			ei2 = il.Sub(addressSize_l, ei0, ei1, crxToFlagWriteType(oper2 ? oper0->reg : PPC_REG_CR0));
+		case PPC_ID_CMPW: /* compare (signed) word(32-bit) */
+			REQUIRE3OPS
+			ei0 = operToIL(il, oper1);
+			ei1 = operToIL(il, oper2);
+			ei2 = il.Sub(addressSize_l, ei0, ei1, crxToFlagWriteType(oper0->reg, PPC_SUF_S));
 			il.AddInstruction(ei2);
 			break;
 
-		case PPC_INS_CMPL:
-		case PPC_INS_CMPLW: /* compare logical(unsigned) word(32-bit) */
-			REQUIRE2OPS
-			ei0 = operToIL_a(il, oper2 ? oper1 : oper0, addressSize_l);
-			ei1 = operToIL_a(il, oper2 ? oper2 : oper1, addressSize_l);
-			ei2 = il.Sub(addressSize_l, ei0, ei1, crxToFlagWriteType(oper2 ? oper0->reg : PPC_REG_CR0, false));
+		case PPC_ID_CMPLW: /* compare logical(unsigned) word(32-bit) */
+			REQUIRE3OPS
+			ei0 = operToIL(il, oper1);
+			ei1 = operToIL(il, oper2);
+			ei2 = il.Sub(addressSize_l, ei0, ei1, crxToFlagWriteType(oper0->reg, PPC_SUF_U));
 			il.AddInstruction(ei2);
 			break;
 
-		case PPC_INS_CMPI:
-		case PPC_INS_CMPWI: /* compare (signed) word(32-bit) immediate */
-		case PPC_INS_CMPDI:
-			REQUIRE2OPS
-			EXTOPTS(rawInsn, addressSize_l, extend_l);
-			ei0 = operToIL_a(il, oper2 ? oper1 : oper0, addressSize_l);
-			ei1 = operToIL(il, oper2 ? oper2 : oper1, extend_l, PPC_IL_EXTRA_DEFAULT, addressSize_l);
-			ei2 = il.Sub(addressSize_l, ei0, ei1, crxToFlagWriteType(oper2 ? oper0->reg : PPC_REG_CR0));
+		case PPC_ID_CMPWI: /* compare (signed) word(32-bit) immediate */
+			REQUIRE3OPS
+			ei0 = operToIL(il, oper1);
+			ei1 = operToIL_a(il, oper2, addressSize_l);
+			ei2 = il.Sub(addressSize_l, ei0, ei1, crxToFlagWriteType(oper0->reg, PPC_SUF_S));
 			il.AddInstruction(ei2);
 			break;
 
-		case PPC_INS_CMPLI:
-		case PPC_INS_CMPLWI: /* compare logical(unsigned) word(32-bit) immediate */
-			REQUIRE2OPS
-			EXTOPTZ(rawInsn, addressSize_l, extend_l);
-			ei0 = operToIL_a(il, oper2 ? oper1 : oper0, addressSize_l);
-			ei1 = operToIL(il, oper2 ? oper2 : oper1, extend_l, PPC_IL_EXTRA_DEFAULT, addressSize_l);
-			ei2 = il.Sub(addressSize_l, ei0, ei1, crxToFlagWriteType(oper2 ? oper0->reg : PPC_REG_CR0, false));
+		case PPC_ID_CMPLWI: /* compare logical(unsigned) word(32-bit) immediate */
+			REQUIRE3OPS
+			ei0 = operToIL(il, oper1);
+			ei1 = operToIL_a(il, oper2, addressSize_l);
+			ei2 = il.Sub(addressSize_l, ei0, ei1, crxToFlagWriteType(oper0->reg, PPC_SUF_U));
 			il.AddInstruction(ei2);
 			break;
 
-	//case PPC_INS_CMPD: /* compare (signed) d-word(64-bit) */
-	//	REQUIRE2OPS
-	//	ei0 = operToIL(il, oper0);
-	//	ei1 = operToIL(il, oper1, OTI_SEXT64_REGS);
-	//	ei2 = il.Sub(4, ei0, ei1, flagWriteType);
-	//	il.AddInstruction(ei2);
-	//	break;
+		case PPC_ID_CMPD: /* compare (signed) d-word(64-bit) */
+			REQUIRE2OPS
+			ei0 = operToIL_a(il, oper1, 8);
+			ei1 = operToIL_a(il, oper2, 8);
+			ei2 = il.Sub(addressSize_l, ei0, ei1, crxToFlagWriteType(oper0->reg, PPC_SUF_S));
+			il.AddInstruction(ei2);
+			break;
 
-	//case PPC_INS_CMPLD: /* compare logical(unsigned) d-word(64-bit) */
-	//	REQUIRE2OPS
-	//	ei0 = operToIL(il, oper0);
-	//	ei1 = operToIL(il, oper1, OTI_ZEXT64_REGS);
-	//	ei2 = il.Sub(4, ei0, ei1, flagWriteType);
-	//	il.AddInstruction(ei2);
-	//	break;
+		case PPC_ID_CMPLD: /* compare logical(unsigned) d-word(64-bit) */
+			REQUIRE2OPS
+			ei0 = operToIL_a(il, oper1, 8);
+			ei1 = operToIL_a(il, oper2, 8);
+			ei2 = il.Sub(addressSize_l, ei0, ei1, crxToFlagWriteType(oper0->reg, PPC_SUF_U));
+			il.AddInstruction(ei2);
+			break;
 
-	//case PPC_INS_CMPDI: /* compare (signed) d-word(64-bit) immediate */
-	//	REQUIRE2OPS
-	//	ei0 = operToIL(il, oper0);
-	//	ei1 = operToIL(il, oper1, OTI_SEXT64_IMMS);
-	//	ei2 = il.Sub(4, ei0, ei1, flagWriteType);
-	//	il.AddInstruction(ei2);
-	//	break;
+		case PPC_ID_CMPDI:
+			REQUIRE2OPS
+			ei0 = operToIL_a(il, oper1, 8);
+			ei1 = operToIL_a(il, oper2, 8);
+			ei2 = il.Sub(8, ei0, ei1, crxToFlagWriteType(oper0->reg, PPC_SUF_S));
+			il.AddInstruction(ei2);
+			break;
 
-	//case PPC_INS_CMPLDI: /* compare logical(unsigned) d-word(64-bit) immediate */
-	//	REQUIRE2OPS
-	//	ei0 = operToIL(il, oper0);
-	//	ei1 = operToIL(il, oper1, OTI_ZEXT64_IMMS);
-	//	ei2 = il.Sub(4, ei0, ei1, flagWriteType);
-	//	il.AddInstruction(ei2);
-	//	break;
+		case PPC_ID_CMPLDI:
+			REQUIRE2OPS
+			ei0 = operToIL_a(il, oper1, 8);
+			ei1 = operToIL_a(il, oper2, 8);
+			ei2 = il.Sub(8, ei0, ei1, crxToFlagWriteType(oper0->reg, PPC_SUF_U));
+			il.AddInstruction(ei2);
+			break;
 
-		case PPC_INS_CRAND:
-		case PPC_INS_CRANDC:
-		case PPC_INS_CRNAND:
+		case PPC_ID_CRAND:
+		case PPC_ID_CRANDC:
+		case PPC_ID_CRNAND:
 			REQUIRE3OPS
-			ei0 = il.Flag(oper1->reg - PPC_REG_R0);
-			ei1 = il.Flag(oper2->reg - PPC_REG_R0);
-			if (insn->id == PPC_INS_CRANDC)
+			ei0 = il.Flag(oper1->crbit);
+			ei1 = il.Flag(oper2->crbit);
+			if (instruction->id == PPC_ID_CRANDC)
 				ei1 = il.Not(0, ei1);
 			ei0 = il.And(0, ei0, ei1);
-			if (insn->id == PPC_INS_CRNAND)
+			if (instruction->id == PPC_ID_CRNAND)
 				ei0 = il.Not(0, ei0);
-			il.AddInstruction(il.SetFlag(oper0->reg - PPC_REG_R0, ei0));
+			il.AddInstruction(il.SetFlag(oper0->crbit, ei0));
 			break;
 
-		case PPC_INS_CROR:
-		case PPC_INS_CRORC:
-		case PPC_INS_CRNOR:
+		case PPC_ID_CROR:
+		case PPC_ID_CRORC:
+		case PPC_ID_CRNOR:
 			REQUIRE3OPS
-			ei0 = il.Flag(oper1->reg - PPC_REG_R0);
-			ei1 = il.Flag(oper2->reg - PPC_REG_R0);
-			if (insn->id == PPC_INS_CRORC)
+			ei0 = il.Flag(oper1->crbit);
+			ei1 = il.Flag(oper2->crbit);
+			if (instruction->id == PPC_ID_CRORC)
 				ei1 = il.Not(0, ei1);
 			ei0 = il.Or(0, ei0, ei1);
-			if (insn->id == PPC_INS_CRNOR)
+			if (instruction->id == PPC_ID_CRNOR)
 				ei0 = il.Not(0, ei0);
-			il.AddInstruction(il.SetFlag(oper0->reg - PPC_REG_R0, ei0));
+			il.AddInstruction(il.SetFlag(oper0->crbit, ei0));
 			break;
 
-		case PPC_INS_CREQV:
-		case PPC_INS_CRXOR:
+		case PPC_ID_CREQV:
+		case PPC_ID_CRXOR:
 			REQUIRE3OPS
-			ei0 = il.Flag(oper1->reg - PPC_REG_R0);
-			ei1 = il.Flag(oper2->reg - PPC_REG_R0);
+			ei0 = il.Flag(oper1->crbit);
+			ei1 = il.Flag(oper2->crbit);
 			ei0 = il.Xor(0, ei0, ei1);
-			if (insn->id == PPC_INS_CREQV)
+			if (instruction->id == PPC_ID_CREQV)
 				ei0 = il.Not(0, ei0);
-			il.AddInstruction(il.SetFlag(oper0->reg - PPC_REG_R0, ei0));
+			il.AddInstruction(il.SetFlag(oper0->crbit, ei0));
 			break;
 
-		case PPC_INS_CRSET:
+		case PPC_ID_CRSET:
 			REQUIRE1OP
-			ei0 = il.SetFlag(oper0->reg - PPC_REG_R0, il.Const(0, 1));
+			ei0 = il.SetFlag(oper0->crbit, il.Const(0, 1));
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_CRCLR:
+		case PPC_ID_CRCLR:
 			REQUIRE1OP
-			ei0 = il.SetFlag(oper0->reg - PPC_REG_R0, il.Const(0, 0));
+			ei0 = il.SetFlag(oper0->crbit, il.Const(0, 0));
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_CRNOT:
-		case PPC_INS_CRMOVE:
+		case PPC_ID_CRNOT:
+		case PPC_ID_CRMOVE:
 			REQUIRE2OPS
-			ei0 = il.Flag(oper1->reg - PPC_REG_R0);
-			if (insn->id == PPC_INS_CRNOT)
+			ei0 = il.Flag(oper1->crbit);
+			if (instruction->id == PPC_ID_CRNOT)
 				ei0 = il.Not(0, ei0);
-			ei0 = il.SetFlag(oper0->reg - PPC_REG_R0, ei0);
+			ei0 = il.SetFlag(oper0->crbit, ei0);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_MFCR:
+		case PPC_ID_MFCR:
 			REQUIRE1OP
 			il.AddInstruction(il.SetRegister(4, oper0->reg,
 				il.Or(4, il.FlagBit(4, IL_FLAG_LT, 31),
@@ -912,11 +827,26 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 				il.FlagBit(4, IL_FLAG_SO_7, 0))))))))))))))))))))))))))))))))));
 			break;
 
-		case PPC_INS_MTCRF:
+		case PPC_ID_MCRF:
+		{
+			REQUIRE2OPS
+			uint32_t from = oper1->reg - PPC_REG_CRF0;
+			uint32_t to = oper0->reg - PPC_REG_CRF0;
+
+			il.AddInstruction(il.SetFlag(4*to + IL_FLAG_LT, il.FlagBit(0, 4*from + IL_FLAG_LT, 31 - (4*from + IL_FLAG_LT))));
+			il.AddInstruction(il.SetFlag(4*to + IL_FLAG_GT, il.FlagBit(0, 4*from + IL_FLAG_GT, 31 - (4*from + IL_FLAG_GT))));
+			il.AddInstruction(il.SetFlag(4*to + IL_FLAG_EQ, il.FlagBit(0, 4*from + IL_FLAG_EQ, 31 - (4*from + IL_FLAG_EQ))));
+			il.AddInstruction(il.SetFlag(4*to + IL_FLAG_SO, il.FlagBit(0, 4*from + IL_FLAG_SO, 31 - (4*from + IL_FLAG_SO))));
+
+			break;
+
+		}
+
+		case PPC_ID_MTCRF:
 			REQUIRE2OPS
 			for (uint8_t test = 0x80, i = 0; test; test >>= 1, i++)
 			{
-				if (test & oper0->imm)
+				if (test & oper0->uimm)
 				{
 					ei0 = il.Or(4, il.Register(4, oper1->reg), il.Const(4, 0), IL_FLAGWRITE_MTCR0 + i);
 					il.AddInstruction(ei0);
@@ -924,11 +854,11 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			}
 			break;
 
-		case PPC_INS_EXTSB:
-		case PPC_INS_EXTSH:
+		case PPC_ID_EXTSBx:
+		case PPC_ID_EXTSHx:
 			REQUIRE2OPS
 			ei0 = il.Register(addressSize_l, oper1->reg);
-			if (insn->id == PPC_INS_EXTSB)
+			if (instruction->id == PPC_ID_EXTSBx)
 			{
 				ei0 = il.LowPart(1, ei0);
 			}
@@ -938,27 +868,27 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			}
 			ei0 = il.SignExtend(addressSize_l, ei0);
 			ei0 = il.SetRegister(addressSize_l, oper0->reg, ei0,
-				ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+				instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_EXTSW:
+		case PPC_ID_EXTSWx:
 			REQUIRE2OPS
 			ei0 = il.Register(8, oper1->reg);
 			ei0 = il.LowPart(4, ei0);
 			ei0 = il.SignExtend(8, ei0);
 			ei0 = il.SetRegister(8, oper0->reg, ei0,
-				ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+				instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_ISEL:
+		case PPC_ID_ISEL:
 			REQUIRE4OPS
 			{
 				LowLevelILLabel trueLabel, falseLabel, doneLabel;
-				uint32_t crBit = powerpc_crx_to_reg(oper3->reg);
+				uint32_t crBit = oper3->crbit;
 				uint32_t cr = crBit / 4;
 
 				switch (crBit % 4)
@@ -996,9 +926,10 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			}
 			break;
 
-		case PPC_INS_LMW:
+		case PPC_ID_LMW:
 			REQUIRE2OPS
-			for(i=oper0->reg; i<=PPC_REG_R31; ++i) {
+			for (i = oper0->reg; i <= PPC_REG_GPR31; ++i)
+			{
 				ei0 = il.SetRegister(4,
 					i,             // dest
 					il.Load(4,     // source
@@ -1014,28 +945,36 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 		/*
 			load byte and zero extend [and update]
 		*/
-		case PPC_INS_LBZ:
-		case PPC_INS_LBZU:
+		case PPC_ID_LBZ:
+		case PPC_ID_LBZU:
+		case PPC_ID_VLE_SE_LBZ:
+		{
+			// 16-bit VLE loads/stores treats r0 as a normal register
+			uint32_t options = OTI_GPR0_ZERO;
+			if (instruction->id == PPC_ID_VLE_SE_LBZ)
+				options = 0;
+
 			REQUIRE2OPS
-			ei0 = operToIL(il, oper1, OTI_GPR0_ZERO, PPC_IL_EXTRA_DEFAULT, addressSize_l); // d(rA) or 0
+			ei0 = operToIL(il, oper1, options, PPC_IL_EXTRA_DEFAULT, addressSize_l); // d(rA) or 0
 			ei0 = il.Load(1, ei0);                    // [d(rA)]
 			ei0 = il.ZeroExtend(addressSize_l, ei0);
 			ei0 = il.SetRegister(addressSize_l, oper0->reg, ei0); // rD = [d(rA)]
 			il.AddInstruction(ei0);
 
 			// if update, rA is set to effective address (d(rA))
-			if(insn->id == PPC_INS_LBZU) {
-				ei0 = il.SetRegister(addressSize_l, oper1->mem.base, operToIL_a(il, oper1, addressSize_l));
+			if(instruction->id == PPC_ID_LBZU) {
+				ei0 = il.SetRegister(addressSize_l, oper1->mem.reg, operToIL(il, oper1, addressSize_l));
 				il.AddInstruction(ei0);
 			}
 
 			break;
+		}
 
 		/*
 			load half word [and zero/sign extend] [and update]
 		*/
-		case PPC_INS_LBZX:
-		case PPC_INS_LBZUX:
+		case PPC_ID_LBZX:
+		case PPC_ID_LBZUX:
 			REQUIRE3OPS
 			ei0 = operToIL(il, oper1, OTI_GPR0_ZERO, PPC_IL_EXTRA_DEFAULT, addressSize_l);              // d(rA) or 0
 			ei0 = il.Load(1, il.Add(addressSize_l, ei0, operToIL_a(il, oper2, addressSize_l))); // [d(rA) + d(rB)]
@@ -1044,7 +983,8 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 
 			// if update, rA is set to effective address (d(rA))
-			if(insn->id == PPC_INS_LBZUX && oper1->reg != oper0->reg && oper1->reg != PPC_REG_R0) {
+			if (instruction->id == PPC_ID_LBZUX && oper1->reg != oper0->reg && oper1->reg != PPC_REG_GPR0)
+			{
 				ei0 = il.SetRegister(addressSize_l, oper1->reg, operToIL_a(il, oper1, addressSize_l));
 				il.AddInstruction(ei0);
 			}
@@ -1054,14 +994,21 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 		/*
 			load half word [and zero/sign extend] [and update]
 		*/
-		case PPC_INS_LHZ:
-		case PPC_INS_LHZU:
-		case PPC_INS_LHA:
-		case PPC_INS_LHAU:
+		case PPC_ID_LHZ:
+		case PPC_ID_LHZU:
+		case PPC_ID_LHA:
+		case PPC_ID_LHAU:
+		case PPC_ID_VLE_SE_LHZ:
+		{
+			// 16-bit VLE loads/stores treats r0 as a normal register
+			uint32_t options = OTI_GPR0_ZERO;
+			if (instruction->id == PPC_ID_VLE_SE_LHZ)
+				options = 0;
+
 			REQUIRE2OPS
-			ei0 = operToIL(il, oper1, OTI_GPR0_ZERO, PPC_IL_EXTRA_DEFAULT, addressSize_l); // d(rA) or 0
+			ei0 = operToIL(il, oper1, options, PPC_IL_EXTRA_DEFAULT, addressSize_l); // d(rA) or 0
 			ei0 = il.Load(2, ei0);                    // [d(rA)]
-			if(insn->id == PPC_INS_LHZ || insn->id == PPC_INS_LHZU)
+			if(instruction->id == PPC_ID_LHZ || instruction->id == PPC_ID_LHZU)
 				ei0 = il.ZeroExtend(addressSize_l, ei0);
 			else
 				ei0 = il.SignExtend(addressSize_l, ei0);
@@ -1069,24 +1016,26 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 
 			// if update, rA is set to effective address (d(rA))
-			if(insn->id == PPC_INS_LHZU || insn->id == PPC_INS_LHAU) {
-				ei0 = il.SetRegister(addressSize_l, oper1->mem.base, operToIL_a(il, oper1, addressSize_l));
+			if (instruction->id == PPC_ID_LHZU || instruction->id == PPC_ID_LHAU)
+			{
+				ei0 = il.SetRegister(addressSize_l, oper1->mem.reg, operToIL_a(il, oper1, addressSize_l));
 				il.AddInstruction(ei0);
 			}
 
 			break;
+		}
 
 		/*
 			load half word [and zero/sign extend] [and update]
 		*/
-		case PPC_INS_LHZX:
-		case PPC_INS_LHZUX:
-		case PPC_INS_LHAX:
-		case PPC_INS_LHAUX:
+		case PPC_ID_LHZX:
+		case PPC_ID_LHZUX:
+		case PPC_ID_LHAX:
+		case PPC_ID_LHAUX:
 			REQUIRE3OPS
 			ei0 = operToIL(il, oper1, OTI_GPR0_ZERO, PPC_IL_EXTRA_DEFAULT, addressSize_l);              // d(rA) or 0
 			ei0 = il.Load(2, il.Add(addressSize_l, ei0, operToIL_a(il, oper2, addressSize_l))); // [d(rA) + d(rB)]
-			if(insn->id == PPC_INS_LHZX || insn->id == PPC_INS_LHZUX)
+			if(instruction->id == PPC_ID_LHZX || instruction->id == PPC_ID_LHZUX)
 				ei0 = il.ZeroExtend(addressSize_l, ei0);
 			else
 				ei0 = il.SignExtend(addressSize_l, ei0);
@@ -1094,7 +1043,7 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 
 			// if update, rA is set to effective address (d(rA))
-			if((insn->id == PPC_INS_LHZUX || insn->id == PPC_INS_LHAUX) && oper1->reg != oper0->reg && oper1->reg != PPC_REG_R0) {
+			if((instruction->id == PPC_ID_LHZUX || instruction->id == PPC_ID_LHAUX) && oper1->reg != oper0->reg && oper1->reg != PPC_REG_GPR0) {
 				ei0 = il.SetRegister(addressSize_l, oper1->reg, operToIL_a(il, oper1, addressSize_l));
 				il.AddInstruction(ei0);
 			}
@@ -1104,10 +1053,17 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 		/*
 			load word [and zero] [and update]
 		*/
-		case PPC_INS_LWZ:
-		case PPC_INS_LWZU:
+		case PPC_ID_LWZ:
+		case PPC_ID_LWZU:
+		case PPC_ID_VLE_SE_LWZ:
+		{
+			// 16-bit VLE loads/stores treats r0 as a normal register
+			uint32_t options = OTI_GPR0_ZERO;
+			if (instruction->id == PPC_ID_VLE_SE_LWZ)
+				options = 0;
+
 			REQUIRE2OPS
-			ei0 = operToIL(il, oper1, OTI_GPR0_ZERO, PPC_IL_EXTRA_DEFAULT, addressSize_l); // d(rA) or 0
+			ei0 = operToIL(il, oper1, options, PPC_IL_EXTRA_DEFAULT, addressSize_l); // d(rA) or 0
 			ei0 = il.Load(4, ei0);                    // [d(rA)]
 			if(addressSize_l == 8)
 			{
@@ -1117,19 +1073,19 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 
 			// if update, rA is set to effective address (d(rA))
-			if(insn->id == PPC_INS_LWZU)
-			{
-				ei0 = il.SetRegister(addressSize_l, oper1->mem.base, operToIL_a(il, oper1, addressSize_l));
+			if(instruction->id == PPC_ID_LWZU) {
+				ei0 = il.SetRegister(addressSize_l, oper1->mem.reg, operToIL_a(il, oper1, addressSize_l));
 				il.AddInstruction(ei0);
 			}
 
 			break;
+		}
 
 		/*
 			load word [and zero] [and update]
 		*/
-		case PPC_INS_LWZX:
-		case PPC_INS_LWZUX:
+		case PPC_ID_LWZX:
+		case PPC_ID_LWZUX:
 			REQUIRE3OPS
 			ei0 = operToIL(il, oper1, OTI_GPR0_ZERO, PPC_IL_EXTRA_DEFAULT, addressSize_l);              // d(rA) or 0
 			ei0 = il.Load(4, il.Add(addressSize_l, ei0, operToIL_a(il, oper2, addressSize_l))); // [d(rA) + d(rB)]
@@ -1141,8 +1097,7 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 
 			// if update, rA is set to effective address (d(rA))
-			if(insn->id == PPC_INS_LWZUX && oper1->reg != oper0->reg && oper1->reg != PPC_REG_R0)
-			{
+			if(instruction->id == PPC_ID_LWZUX && oper1->reg != oper0->reg && oper1->reg != PPC_REG_GPR0) {
 				ei0 = il.SetRegister(addressSize_l, oper1->reg, operToIL_a(il, oper1, addressSize_l));
 				il.AddInstruction(ei0);
 			}
@@ -1152,8 +1107,8 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 		/*
 			load doubleword [and update]
 		*/
-		case PPC_INS_LD:
-		case PPC_INS_LDU:
+		case PPC_ID_LD:
+		case PPC_ID_LDU:
 			REQUIRE2OPS
 			ei0 = operToIL(il, oper1, OTI_GPR0_ZERO); // d(rA) or 0
 			ei0 = il.Load(8, ei0);                    // [d(rA)]
@@ -1161,8 +1116,8 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 
 			// if update, rA is set to effective address (d(rA))
-			if(insn->id == PPC_INS_LWZU) {
-				ei0 = il.SetRegister(8, oper1->mem.base, operToIL(il, oper1));
+			if(instruction->id == PPC_ID_LWZU) {
+				ei0 = il.SetRegister(8, oper1->mem.reg, operToIL(il, oper1));
 				il.AddInstruction(ei0);
 			}
 
@@ -1171,8 +1126,8 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 		/*
 			load doubleword [and update]
 		*/
-		case PPC_INS_LDX:
-		case PPC_INS_LDUX:
+		case PPC_ID_LDX:
+		case PPC_ID_LDUX:
 			REQUIRE3OPS
 			ei0 = operToIL(il, oper1, OTI_GPR0_ZERO);              // d(rA) or 0
 			ei0 = il.Load(8, il.Add(8, ei0, operToIL(il, oper2))); // [d(rA) + d(rB)]
@@ -1180,124 +1135,115 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 
 			// if update, rA is set to effective address (d(rA))
-			if(insn->id == PPC_INS_LWZUX && oper1->reg != oper0->reg && oper1->reg != PPC_REG_R0) {
+			if(instruction->id == PPC_ID_LWZUX && oper1->reg != oper0->reg && oper1->reg != PPC_REG_GPR0) {
 				ei0 = il.SetRegister(8, oper1->reg, operToIL(il, oper1));
 				il.AddInstruction(ei0);
 			}
 
 			break;
 
-		case PPC_INS_LHBRX:
+		case PPC_ID_LHBRX:
 			REQUIRE3OPS
-			ByteReversedLoad(il, ppc, 2, addressSize_l);
+			ByteReversedLoad(il, instruction, 2, addressSize_l);
 			break;
 
-		case PPC_INS_LWBRX:
+		case PPC_ID_LWBRX:
 			REQUIRE3OPS
-			ByteReversedLoad(il, ppc, 4, addressSize_l);
+			ByteReversedLoad(il, instruction, 4, addressSize_l);
 			break;
 
-		case PPC_INS_STHBRX:
+		case PPC_ID_STHBRX:
 			REQUIRE3OPS
-			ByteReversedStore(il, ppc, 2, addressSize_l);
+			ByteReversedStore(il, instruction, 2, addressSize_l);
 			break;
 
-		case PPC_INS_STWBRX:
+		case PPC_ID_STWBRX:
 			REQUIRE3OPS
-			ByteReversedStore(il, ppc, 4, addressSize_l);
+			ByteReversedStore(il, instruction, 4, addressSize_l);
 			break;
 
-		case PPC_INS_MFCTR: // move from ctr
+		case PPC_ID_MFCTR: // move from ctr
 			REQUIRE1OP
 			il.AddInstruction(il.SetRegister(addressSize_l, oper0->reg, il.Register(addressSize_l, PPC_REG_CTR)));
 			break;
 
-		case PPC_INS_MFLR: // move from link register
+		case PPC_ID_MFLR: // move from link register
 			REQUIRE1OP
 			il.AddInstruction(il.SetRegister(addressSize_l, oper0->reg, il.Register(addressSize_l, PPC_REG_LR)));
 			break;
 
-		case PPC_INS_MTCTR: // move to ctr
+		case PPC_ID_MTCTR: // move to ctr
 			REQUIRE1OP
 			il.AddInstruction(il.SetRegister(addressSize_l, PPC_REG_CTR, operToIL_a(il, oper0, addressSize_l)));
 			break;
 
-		case PPC_INS_MTLR: // move to link register
+		case PPC_ID_MTLR: // move to link register
 			REQUIRE1OP
 			il.AddInstruction(il.SetRegister(addressSize_l, PPC_REG_LR, operToIL_a(il, oper0, addressSize_l)));
 			break;
 
-		case PPC_INS_NEG:
+		case PPC_ID_NEGx:
 			REQUIRE2OPS
-			ei0 = il.Neg(addressSize_l, operToIL_a(il, oper1, addressSize_l));
+			ei0 = il.Neg(addressSize_l, operToIL(il, oper1));
 			il.AddInstruction(il.SetRegister(addressSize_l, oper0->reg, ei0,
-				ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+				instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			));
 			break;
 
-		case PPC_INS_NOP:
+		case PPC_ID_NOP:
 			il.AddInstruction(il.Nop());
 			break;
 
-		case PPC_INS_NOT:
-			REQUIRE2OPS
-			ei0 = il.Not(addressSize_l, operToIL_a(il, oper1, addressSize_l));
-			il.AddInstruction(il.SetRegister(addressSize_l, oper0->reg, ei0,
-				ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
-			));
-			break;
-
-		case PPC_INS_OR:
-		case PPC_INS_ORC:
-		case PPC_INS_NOR:
+		case PPC_ID_ORx:
+		case PPC_ID_ORCx:
+		case PPC_ID_NORx:
 			REQUIRE3OPS
 			ei0 = operToIL_a(il, oper2, addressSize_l);
-			if (insn->id == PPC_INS_ORC)
+			if (instruction->id == PPC_ID_ORCx)
 				ei0 = il.Not(addressSize_l, ei0);
 			ei0 = il.Or(addressSize_l, operToIL_a(il, oper1, addressSize_l), ei0);
-			if (insn->id == PPC_INS_NOR)
+			if (instruction->id == PPC_ID_NORx)
 				ei0 = il.Not(addressSize_l, ei0);
 			ei0 = il.SetRegister(addressSize_l, oper0->reg, ei0,
-				ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+				instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_ORI:
-		case PPC_INS_ORIS:
+		case PPC_ID_ORIx:
+		case PPC_ID_ORIS:
 			REQUIRE3OPS
-			if (insn->id == PPC_INS_ORIS)
-				ei0 = il.Const(addressSize_l, oper2->imm << 16);
+			if (instruction->id == PPC_ID_ORIS)
+				ei0 = il.Const(addressSize_l, oper2->uimm << 16);
 			else
-				ei0 = il.Const(addressSize_l, oper2->imm);
+				ei0 = il.Const(addressSize_l, oper2->uimm);
 			ei0 = il.Or(addressSize_l, operToIL_a(il, oper1, addressSize_l), ei0);
 			ei0 = il.SetRegister(addressSize_l, oper0->reg, ei0);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_XOR:
-		case PPC_INS_EQV:
+		case PPC_ID_XORx:
+		case PPC_ID_EQVx:
 			REQUIRE3OPS
 			ei0 = il.Xor(addressSize_l,
 				operToIL_a(il, oper1, addressSize_l),
 				operToIL_a(il, oper2, addressSize_l)
 			);
-			if (insn->id == PPC_INS_EQV)
+			if (instruction->id == PPC_ID_EQVx)
 				ei0 = il.Not(addressSize_l, ei0);
 			ei0 = il.SetRegister(addressSize_l, oper0->reg, ei0,
-				ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+				instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_XORI:
-		case PPC_BN_INS_XORI:
-		case PPC_INS_XORIS:
+		case PPC_ID_XORIx:
+		case PPC_ID_XORIS:
 			REQUIRE3OPS
-			if (insn->id == PPC_INS_XORIS)
-				ei0 = il.Const(addressSize_l, oper2->imm << 16);
+			if (instruction->id == PPC_ID_XORIS)
+				ei0 = il.Const(addressSize_l, oper2->uimm << 16);
 			else
-				ei0 = il.Const(addressSize_l, oper2->imm);
+				ei0 = il.Const(addressSize_l, oper2->uimm);
 			ei0 = il.SetRegister(
 				addressSize_l,
 				oper0->reg,
@@ -1309,23 +1255,23 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_SUBF:
-		case PPC_INS_SUBFC:
-		case PPC_INS_SUBFIC:
+		case PPC_ID_SUBFx:
+		case PPC_ID_SUBFCx:
+		case PPC_ID_SUBFICx:
 			REQUIRE3OPS
 			ei0 = il.Sub(
 				addressSize_l,
 				operToIL_a(il, oper2, addressSize_l),
 				operToIL_a(il, oper1, addressSize_l),
-				(insn->id != PPC_INS_SUBF) ? IL_FLAGWRITE_XER_CA : 0
+				(instruction->id != PPC_ID_SUBFx) ? IL_FLAGWRITE_XER_CA : 0
 			);
 			ei0 = il.SetRegister(addressSize_l, oper0->reg, ei0,
-				ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+				instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_SUBFE:
+		case PPC_ID_SUBFEx:
 			REQUIRE3OPS
 			ei0 = il.SubBorrow(
 				addressSize_l,
@@ -1335,15 +1281,15 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 				IL_FLAGWRITE_XER_CA
 			);
 			ei0 = il.SetRegister(addressSize_l, oper0->reg, ei0,
-				ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+				instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_SUBFME:
-		case PPC_INS_SUBFZE:
+		case PPC_ID_SUBFMEx:
+		case PPC_ID_SUBFZEx:
 			REQUIRE2OPS
-			if (insn->id == PPC_INS_SUBFME)
+			if (instruction->id == PPC_ID_SUBFMEx)
 				ei0 = il.Const(addressSize_l, ADDRNEG1(addressSize_l));
 			else
 				ei0 = il.Const(addressSize_l, 0);
@@ -1355,14 +1301,15 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 				IL_FLAGWRITE_XER_CA
 			);
 			ei0 = il.SetRegister(addressSize_l, oper0->reg, ei0,
-				ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+				instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_STMW:
+		case PPC_ID_STMW:
 			REQUIRE2OPS
-			for(i=oper0->reg; i<=PPC_REG_R31; ++i) {
+			for (i = oper0->reg; i <= PPC_REG_GPR31; ++i)
+			{
 				ei0 = il.Register(4, i); // source
 				ei1 = operToIL(il, oper1, OTI_IMM_BIAS, (i-(oper0->reg))*4, addressSize_l);
 				il.AddInstruction(
@@ -1376,26 +1323,34 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			break;
 
 		/* store half word [with update] */
-		case PPC_INS_STB:
-		case PPC_INS_STBU: /* store(size, addr, val) */
+		case PPC_ID_STB:
+		case PPC_ID_STBU: /* store(size, addr, val) */
+		case PPC_ID_VLE_SE_STB:
+		{
+			// 16-bit VLE loads/stores treats r0 as a normal register
+			uint32_t options = OTI_GPR0_ZERO;
+			if (instruction->id == PPC_ID_VLE_SE_STB)
+				options = 0;
+
 			REQUIRE2OPS
 			ei0 = il.Store(1,
-				operToIL(il, oper1, OTI_GPR0_ZERO, PPC_IL_EXTRA_DEFAULT, addressSize_l),
+				operToIL(il, oper1, options, PPC_IL_EXTRA_DEFAULT, addressSize_l),
 				il.LowPart(1, operToIL_a(il, oper0, addressSize_l))
 			);
 			il.AddInstruction(ei0);
 
 			// if update, then rA gets updated address
-			if(insn->id == PPC_INS_STBU) {
-				ei0 = il.SetRegister(addressSize_l, oper1->mem.base, operToIL_a(il, oper1, addressSize_l));
+			if(instruction->id == PPC_ID_STBU) {
+				ei0 = il.SetRegister(addressSize_l, oper1->mem.reg, operToIL_a(il, oper1, addressSize_l));
 				il.AddInstruction(ei0);
 			}
 
 			break;
+		}
 
 		/* store half word indexed [with update] */
-		case PPC_INS_STBX:
-		case PPC_INS_STBUX: /* store(size, addr, val) */
+		case PPC_ID_STBX:
+		case PPC_ID_STBUX: /* store(size, addr, val) */
 			REQUIRE3OPS
 			ei0 = il.Store(1,
 				il.Add(
@@ -1407,7 +1362,7 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 
 			// if update, then rA gets updated address
-			if(insn->id == PPC_INS_STBUX) {
+			if(instruction->id == PPC_ID_STBUX) {
 				ei0 = il.SetRegister(addressSize_l, oper1->reg,
 					il.Add(addressSize_l, operToIL_a(il, oper1, addressSize_l), operToIL_a(il, oper2, addressSize_l))
 				);
@@ -1417,26 +1372,34 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			break;
 
 		/* store half word [with update] */
-		case PPC_INS_STH:
-		case PPC_INS_STHU: /* store(size, addr, val) */
+		case PPC_ID_STH:
+		case PPC_ID_STHU: /* store(size, addr, val) */
+		case PPC_ID_VLE_SE_STH:
+		{
+			// 16-bit VLE loads/stores treats r0 as a normal register
+			uint32_t options = OTI_GPR0_ZERO;
+			if (instruction->id == PPC_ID_VLE_SE_STH)
+				options = 0;
+
 			REQUIRE2OPS
 			ei0 = il.Store(2,
-				operToIL(il, oper1, OTI_GPR0_ZERO, PPC_IL_EXTRA_DEFAULT, addressSize_l),
+				operToIL(il, oper1, options, PPC_IL_EXTRA_DEFAULT, addressSize_l),
 				il.LowPart(2, operToIL_a(il, oper0, addressSize_l))
 			);
 			il.AddInstruction(ei0);
 
 			// if update, then rA gets updated address
-			if(insn->id == PPC_INS_STHU) {
-				ei0 = il.SetRegister(addressSize_l, oper1->mem.base, operToIL_a(il, oper1, addressSize_l));
+			if(instruction->id == PPC_ID_STHU) {
+				ei0 = il.SetRegister(addressSize_l, oper1->mem.reg, operToIL_a(il, oper1, addressSize_l));
 				il.AddInstruction(ei0);
 			}
 
 			break;
+		}
 
 		/* store half word indexed [with update] */
-		case PPC_INS_STHX:
-		case PPC_INS_STHUX: /* store(size, addr, val) */
+		case PPC_ID_STHX:
+		case PPC_ID_STHUX: /* store(size, addr, val) */
 			REQUIRE3OPS
 			ei0 = il.Store(2,
 				il.Add(
@@ -1448,7 +1411,7 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 
 			// if update, then rA gets updated address
-			if(insn->id == PPC_INS_STHUX) {
+			if(instruction->id == PPC_ID_STHUX) {
 				ei0 = il.SetRegister(addressSize_l, oper1->reg,
 					il.Add(addressSize_l, operToIL_a(il, oper1, addressSize_l), operToIL_a(il, oper2, addressSize_l))
 				);
@@ -1458,8 +1421,15 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			break;
 
 		/* store word [with update] */
-		case PPC_INS_STW:
-		case PPC_INS_STWU: /* store(size, addr, val) */
+		case PPC_ID_STW:
+		case PPC_ID_STWU: /* store(size, addr, val) */
+		case PPC_ID_VLE_SE_STW:
+		{
+			// 16-bit VLE loads/stores treats r0 as a normal register
+			uint32_t options = OTI_GPR0_ZERO;
+			if (instruction->id == PPC_ID_VLE_SE_STW)
+				options = 0;
+
 			REQUIRE2OPS
 			if (addressSize_l == 8)
 			{
@@ -1469,23 +1439,25 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			{
 				ei0 = operToIL(il, oper0);
 			}
+
 			ei0 = il.Store(4,
-				operToIL(il, oper1, OTI_GPR0_ZERO, PPC_IL_EXTRA_DEFAULT, addressSize_l),
+				operToIL(il, oper1, options, PPC_IL_EXTRA_DEFAULT, addressSize_l),
 				ei0
 			);
 			il.AddInstruction(ei0);
 
 			// if update, then rA gets updated address
-			if(insn->id == PPC_INS_STWU) {
-				ei0 = il.SetRegister(addressSize_l, oper1->mem.base, operToIL_a(il, oper1, addressSize_l));
+			if(instruction->id == PPC_ID_STWU) {
+				ei0 = il.SetRegister(addressSize_l, oper1->mem.reg, operToIL_a(il, oper1, addressSize_l));
 				il.AddInstruction(ei0);
 			}
 
 			break;
+		}
 
 		/* store word indexed [with update] */
-		case PPC_INS_STWX:
-		case PPC_INS_STWUX: /* store(size, addr, val) */
+		case PPC_ID_STWX:
+		case PPC_ID_STWUX: /* store(size, addr, val) */
 			REQUIRE3OPS
 			if (addressSize_l == 8)
 			{
@@ -1505,7 +1477,7 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 
 			// if update, then rA gets updated address
-			if(insn->id == PPC_INS_STWUX) {
+			if(instruction->id == PPC_ID_STWUX) {
 				ei0 = il.SetRegister(addressSize_l, oper1->reg,
 					il.Add(addressSize_l, operToIL_a(il, oper1, addressSize_l), operToIL_a(il, oper2, addressSize_l))
 				);
@@ -1515,8 +1487,8 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			break;
 
 		/* store double word [with update] */
-		case PPC_INS_STD:
-		case PPC_INS_STDU: /* store(size, addr, val) */
+		case PPC_ID_STD:
+		case PPC_ID_STDU: /* store(size, addr, val) */
 			REQUIRE2OPS
 			ei0 = il.Store(8,
 				operToIL(il, oper1, OTI_GPR0_ZERO, PPC_IL_OPTIONS_DEFAULT, addressSize_l),
@@ -1525,16 +1497,16 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 
 			// if update, then rA gets updated address
-			if(insn->id == PPC_INS_STDU) {
-				ei0 = il.SetRegister(8, oper1->mem.base, operToIL_a(il, oper1, 8));
+			if(instruction->id == PPC_ID_STWU) {
+				ei0 = il.SetRegister(8, oper1->mem.reg, operToIL_a(il, oper1, 8));
 				il.AddInstruction(ei0);
 			}
 
 			break;
 
 		/* store word indexed [with update] */
-		case PPC_INS_STDX:
-		case PPC_INS_STDUX: /* store(size, addr, val) */
+		case PPC_ID_STDX:
+		case PPC_ID_STDUX: /* store(size, addr, val) */
 			REQUIRE3OPS
 			ei0 = il.Store(8,
 				il.Add(8, operToIL(il, oper1, OTI_GPR0_ZERO), operToIL_a(il, oper2, addressSize_l)),
@@ -1543,7 +1515,7 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 
 			// if update, then rA gets updated address
-			if(insn->id == PPC_INS_STDUX) {
+			if(instruction->id == PPC_ID_STDUX) {
 				ei0 = il.SetRegister(8, oper1->reg,
 					il.Add(8, operToIL_a(il, oper1, 8), operToIL_a(il, oper2, 8))
 				);
@@ -1552,21 +1524,21 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 
 			break;
 
-		case PPC_INS_RLWIMI:
+		case PPC_ID_RLWIMIx:
 			REQUIRE5OPS
 			{
-				uint32_t mask = genMask(oper3->imm, oper4->imm);
+				uint32_t mask = genMask(oper3->uimm, oper4->uimm);
 
 				ei0 = il.Register(4, oper1->reg);
 
-				if (oper2->imm != 0)
+				if (oper2->uimm != 0)
 				{
-					if ((mask & (~0u >> (32 - oper2->imm))) == 0)
-						ei0 = il.ShiftLeft(4, ei0, il.Const(4, oper2->imm));
-					else if ((mask & (~0u << oper2->imm)) == 0)
-						ei0 = il.LogicalShiftRight(4, ei0, il.Const(4, 32 - oper2->imm));
+					if ((mask & (~0u >> (32 - oper2->uimm))) == 0)
+						ei0 = il.ShiftLeft(4, ei0, il.Const(4, oper2->uimm));
+					else if ((mask & (~0u << oper2->uimm)) == 0)
+						ei0 = il.LogicalShiftRight(4, ei0, il.Const(4, 32 - oper2->uimm));
 					else
-						ei0 = il.RotateLeft(4, ei0, il.Const(4, oper2->imm));
+						ei0 = il.RotateLeft(4, ei0, il.Const(4, oper2->uimm));
 				}
 
 				ei0 = il.And(4, ei0, il.Const(4, mask));
@@ -1574,38 +1546,74 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 				ei0 = il.Or(4, il.And(4, il.Register(4, oper0->reg), il.Const(4, invertMask)), ei0);
 
 				ei0 = il.SetRegister(4, oper0->reg, ei0,
-						ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
+				);
+				il.AddInstruction(ei0);
+			}
+			break;
+
+		case PPC_ID_RLDIMIx:
+		case PPC_ID_RLDICx:
+			REQUIRE4OPS
+			{
+				uint64_t mask = 0;
+				uint64_t sh = oper2->uimm;
+				uint64_t mb = oper3 ? oper3->uimm : 0;
+				uint64_t me = 63 - sh;
+				mask = genMask64(mb, me);
+
+				ei0 = il.Register(8, oper1->reg);
+
+				if (sh != 0)
+				{
+					if ((mask & (~0ull >> (64 - sh))) == 0)
+						ei0 = il.ShiftLeft(8, ei0, il.Const(8, sh));
+					else if ((mask & (~0ull << sh)) == 0)
+						ei0 = il.LogicalShiftRight(8, ei0, il.Const(8, 64 - sh));
+					else
+						ei0 = il.RotateLeft(8, ei0, il.Const(8, sh));
+				}
+
+				ei0 = il.And(8, ei0, il.Const(8, mask));
+				if (instruction->id == PPC_ID_RLDIMIx)
+				{
+					uint64_t invertMask = ~mask;
+					ei0 = il.Or(8, il.And(8, il.Register(8, oper0->reg), il.Const(8, invertMask)), ei0);
+				}
+
+				ei0 = il.SetRegister(8, oper0->reg, ei0,
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 				);
 				il.AddInstruction(ei0);
 			}
 			break;
 
-		case PPC_INS_RLWINM:
+		case PPC_ID_RLWINMx:
 			REQUIRE5OPS
 			{
-				uint32_t mask = genMask(oper3->imm, oper4->imm);
+				uint32_t mask = genMask(oper3->uimm, oper4->uimm);
 
 				ei0 = il.Register(4, oper1->reg);
 
-				if (oper2->imm != 0)
+				if (oper2->uimm != 0)
 				{
-					if ((mask & (~0u >> (32 - oper2->imm))) == 0)
+					if ((mask & (~0u >> (32 - oper2->uimm))) == 0)
 					{
 						if (mask != 0xffffffff)
-							ei0 = il.And(4, ei0, il.Const(4, mask >> oper2->imm));
+							ei0 = il.And(4, ei0, il.Const(4, mask >> oper2->uimm));
 
-						ei0 = il.ShiftLeft(4, ei0, il.Const(4, oper2->imm));
+						ei0 = il.ShiftLeft(4, ei0, il.Const(4, oper2->uimm));
 					}
-					else if ((mask & (~0u << oper2->imm)) == 0)
+					else if ((mask & (~0u << oper2->uimm)) == 0)
 					{
 						if (mask != 0xffffffff)
-							ei0 = il.And(4, ei0, il.Const(4, mask << (32 - oper2->imm)));
+							ei0 = il.And(4, ei0, il.Const(4, mask << (32 - oper2->uimm)));
 
-						ei0 = il.LogicalShiftRight(4, ei0, il.Const(4, 32 - oper2->imm));
+						ei0 = il.LogicalShiftRight(4, ei0, il.Const(4, 32 - oper2->uimm));
 					}
 					else
 					{
-						ei0 = il.RotateLeft(4, ei0, il.Const(4, oper2->imm));
+						ei0 = il.RotateLeft(4, ei0, il.Const(4, oper2->uimm));
 
 						if (mask != 0xffffffff)
 							ei0 = il.And(4, ei0, il.Const(4, mask));
@@ -1617,64 +1625,204 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 				}
 
 				ei0 = il.SetRegister(4, oper0->reg, ei0,
-						ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+						instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 				);
 				il.AddInstruction(ei0);
 			}
 			break;
 
-		case PPC_INS_SLWI:
+		case PPC_ID_RLDICRx:
+		case PPC_ID_RLDICLx:
+		case PPC_ID_EXTLDIx:
+		case PPC_ID_EXTRDIx:
+			REQUIRE4OPS
+		case PPC_ID_CLRLDIx:
+		case PPC_ID_CLRRDIx:
+		// case PPC_ID_SLDIx:
+		// case PPC_ID_SRDIx:
+		case PPC_ID_ROTLDIx:
+		case PPC_ID_ROTRDIx:
 			REQUIRE3OPS
-			ei0 = il.Const(4, oper2->imm);           // amt: shift amount
-			ei1 = il.Register(4, oper1->reg);        //  rS: reg to be shifted
-			ei0 = il.ShiftLeft(4, ei1, ei0);         // (rS << amt)
-			ei0 = il.SetRegister(4, oper0->reg, ei0, // rD = (rs << amt)
-					ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+			{
+				uint64_t mask = 0;
+				uint64_t sh = oper2->uimm;
+				uint64_t mb = oper3 ? oper3->uimm : 0;
+				uint64_t me = oper3 ? oper3->uimm : 0;
+
+				switch (instruction->id)
+				{
+				case PPC_ID_CLRRDIx: me = 63 - sh; sh = 0;
+				// case PPC_ID_EXTLDIx:
+				case PPC_ID_RLDICRx: mb = 0; break;
+				case PPC_ID_EXTLDIx: sh = oper3->uimm; mb = 0; me = oper2->uimm - 1; break;
+
+				case PPC_ID_CLRLDIx: mb = sh; sh = 0;
+				// case PPC_ID_EXTRDIx:
+				case PPC_ID_RLDICLx: me = 63; break;
+				case PPC_ID_EXTRDIx: sh = oper2->uimm + oper3->uimm; mb = 64 - oper2->uimm; me = 63; break;
+
+				case PPC_ID_SLDIx:   mb = 0;  me = 63 - sh; break;
+				case PPC_ID_SRDIx:   mb = 64 - sh;  me = sh; break;
+
+				case PPC_ID_ROTLDIx: mb = 0; me = 63; break;
+				case PPC_ID_ROTRDIx: mb = 0; me = 63; sh = 64 - sh; break;
+					default: // Impossible
+					;
+				}
+				mask = genMask64(mb, me);
+
+				ei0 = il.Register(8, oper1->reg);
+
+				if (sh != 0)
+				{
+					if ((mask & (~0ull >> (64 - sh))) == 0)
+					{
+						if (mask != 0xffffffffffffffff)
+							ei0 = il.And(8, ei0, il.Const(8, mask >> sh));
+
+						ei0 = il.ShiftLeft(8, ei0, il.Const(8, sh));
+					}
+					else if ((mask & (~0ull << sh)) == 0)
+					{
+						if (mask != 0xffffffffffffffff)
+							ei0 = il.And(8, ei0, il.Const(8, mask << (64 - sh)));
+
+						ei0 = il.LogicalShiftRight(8, ei0, il.Const(8, 64 - sh));
+					}
+					else
+					{
+						ei0 = il.RotateLeft(8, ei0, il.Const(8, sh));
+
+						if (mask != 0xffffffffffffffff)
+							ei0 = il.And(8, ei0, il.Const(8, mask));
+					}
+				}
+				else if (mask != 0xffffffffffffffff)
+				{
+					ei0 = il.And(8, ei0, il.Const(8, mask));
+				}
+
+				ei0 = il.SetRegister(8, oper0->reg, ei0,
+						instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
+				);
+				il.AddInstruction(ei0);
+			}
+			break;
+
+		case PPC_ID_SLDIx:
+			opSize = 8;
+		case PPC_ID_SLWIx:
+			REQUIRE3OPS
+			ei0 = il.Const(opSize, oper2->uimm);           // amt: shift amount
+			ei1 = il.Register(opSize, oper1->reg);        //  rS: reg to be shifted
+			ei0 = il.ShiftLeft(opSize, ei1, ei0);         // (rS << amt)
+			ei0 = il.SetRegister(opSize, oper0->reg, ei0, // rD = (rs << amt)
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_SRWI:
+		case PPC_ID_SRDIx:
+			opSize = 8;
+		case PPC_ID_SRWIx:
 			REQUIRE3OPS
-			ei0 = il.Const(4, oper2->imm);           // amt: shift amount
-			ei1 = il.Register(4, oper1->reg);        //  rS: reg to be shifted
-			ei0 = il.LogicalShiftRight(4, ei1, ei0);        // (rS << amt)
-			ei0 = il.SetRegister(4, oper0->reg, ei0, // rD = (rs << amt)
-					ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+			ei0 = il.Const(opSize, oper2->uimm);           // amt: shift amount
+			ei1 = il.Register(opSize, oper1->reg);        //  rS: reg to be shifted
+			ei0 = il.LogicalShiftRight(opSize, ei1, ei0);        // (rS << amt)
+			ei0 = il.SetRegister(opSize, oper0->reg, ei0, // rD = (rs << amt)
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_CLRLWI:
+		case PPC_ID_CLRRWIx:
 			REQUIRE3OPS
-			ei0 = il.Const(4, (uint32_t) (0xffffffff >> oper2->imm));
-			ei1 = il.Register(4, oper1->reg);
-			ei0 = il.And(4, ei1, ei0);
-			ei0 = il.SetRegister(4, oper0->reg, ei0,
-					ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+			ei0 = il.Const(opSize, (uint32_t)(0xffffffff << (oper2->uimm)));
+			ei1 = il.Register(opSize, oper1->reg);
+			ei0 = il.And(opSize, ei1, ei0);
+			ei0 = il.SetRegister(opSize, oper0->reg, ei0,
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_ROTLWI:
+		// case PPC_ID_CLRLDIx:
+		// 	opSize = 8;
+		case PPC_ID_CLRLWIx:
+			REQUIRE3OPS
+			switch (instruction->id)
+			{
+			case PPC_ID_CLRLDIx:
+				ei0 = il.Const(opSize, (uint64_t)(0xffff'ffff'ffff'ffff >> oper2->uimm));
+				break;
+
+			case PPC_ID_CLRLWIx:
+				ei0 = il.Const(opSize, (uint32_t)(0xffffffff >> oper2->uimm));
+				break;
+			default: // Impossible
+				;
+			}
+			ei1 = il.Register(opSize, oper1->reg);
+			ei0 = il.And(opSize, ei1, ei0);
+			ei0 = il.SetRegister(opSize, oper0->reg, ei0,
+				instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
+				);
+			il.AddInstruction(ei0);
+			break;
+
+		// case PPC_ID_CLRLWIx:
+		// 	REQUIRE3OPS
+		// 	ei0 = il.Const(4, (uint32_t) (0xffffffff >> oper2->uimm));
+		// 	ei1 = il.Register(4, oper1->reg);
+		// 	ei0 = il.And(4, ei1, ei0);
+		// 	ei0 = il.SetRegister(4, oper0->reg, ei0,
+		// 			instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
+		// 	);
+		// 	il.AddInstruction(ei0);
+		// 	break;
+
+		case PPC_ID_ROTLWIx:
 			REQUIRE3OPS
 			ei0 = il.Register(4, oper1->reg);
-			ei0 = il.RotateLeft(4, ei0, il.Const(4, oper2->imm));
+			ei0 = il.RotateLeft(4, ei0, il.Const(4, oper2->uimm));
 			ei0 = il.SetRegister(4, oper0->reg, ei0,
-					ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_ROTLW:
-		case PPC_INS_RLWNM:
+		case PPC_ID_RLDCLx:
+		case PPC_ID_RLDCRx:
+			REQUIRE4OPS;
+		case PPC_ID_ROTLDx:
+			REQUIRE3OPS;
+			{
+				uint64_t mask = 0;
+				uint64_t mx = oper3 ? oper3->uimm : 0;
+				if (instruction->id == PPC_ID_RLDCRx)
+					mask = genMask64(0, mx);
+				else
+					mask = genMask64(mx, 63);
+
+				ei0 = il.Register(8, oper1->reg);
+				ei0 = il.RotateLeft(8, il.Register(8, oper2->reg), ei0);
+				if (mask != 0xffffffffffffffff)
+					ei0 = il.And(8, ei0, il.Const(8, mask));
+				ei0 = il.SetRegister(8, oper0->reg, ei0,
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
+				);
+				il.AddInstruction(ei0);
+			}
+
+		case PPC_ID_ROTLWx:
+		case PPC_ID_RLWNMx:
 			REQUIRE3OPS
 			{
 				uint32_t mask = 0xffffffff;
-				if (insn->id == PPC_INS_RLWNM)
+				if (instruction->id == PPC_ID_RLWNMx)
 				{
 					REQUIRE5OPS
-					mask = genMask(oper3->imm, oper4->imm);
+					mask = genMask(oper3->uimm, oper4->uimm);
 				}
 				ei0 = il.Register(4, oper1->reg);
 				ei1 = il.Register(4, oper2->reg);
@@ -1683,230 +1831,213 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 				if (mask != 0xffffffff)
 					ei0 = il.And(4, ei0, il.Const(4, mask));
 				ei0 = il.SetRegister(4, oper0->reg, ei0,
-						ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+						instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 				);
 				il.AddInstruction(ei0);
 			}
 			break;
 
 
-		case PPC_INS_SLW:
-		case PPC_INS_SRW:
+		case PPC_ID_SLWx:
+		case PPC_ID_SRWx:
 			REQUIRE3OPS
 			ei0 = il.Register(4, oper1->reg);
 			// permit bit 26 to survive to enable clearing the whole register
 			ei1 = il.And(4, il.Register(4, oper2->reg), il.Const(4, 0x3f));
-			if (insn->id == PPC_INS_SLW)
+			if (instruction->id == PPC_ID_SLWx)
 				ei0 = il.ShiftLeft(4, ei0, ei1);
 			else
 				ei0 = il.LogicalShiftRight(4, ei0, ei1);
 			il.AddInstruction(il.SetRegister(4, oper0->reg, ei0,
-					ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			));
 			break;
 
-		case PPC_INS_SLD:
-		case PPC_INS_SRD:
+		case PPC_ID_SLDx:
+		case PPC_ID_SRDx:
 			REQUIRE3OPS
 			ei0 = il.Register(8, oper1->reg);
 			// permit bit 25 to survive to enable clearing the whole register
 			ei1 = il.And(8, il.Register(8, oper2->reg), il.Const(8, 0x7f));
-			if (insn->id == PPC_INS_SLD)
+			if (instruction->id == PPC_ID_SLDx)
 				ei0 = il.ShiftLeft(8, ei0, ei1);
 			else
 				ei0 = il.LogicalShiftRight(8, ei0, ei1);
 			il.AddInstruction(il.SetRegister(8, oper0->reg, ei0,
-					ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			));
 			break;
 
-		case PPC_INS_SRAW:
+		case PPC_ID_SRAWx:
 			REQUIRE3OPS
 			ei0 = il.Register(4, oper1->reg);
 			ei1 = il.And(4, il.Register(4, oper2->reg), il.Const(4, 0x1f));
 			ei0 = il.ArithShiftRight(4, ei0, ei1, IL_FLAGWRITE_XER_CA);
 			il.AddInstruction(il.SetRegister(4, oper0->reg, ei0,
-					ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			));
 			break;
 
-		case PPC_INS_SRAWI:
+		case PPC_ID_SRAWIx:
 			REQUIRE3OPS
 			ei0 = il.Register(4, oper1->reg);
-			ei0 = il.ArithShiftRight(4, ei0, il.Const(4, oper2->imm), IL_FLAGWRITE_XER_CA);
+			ei0 = il.ArithShiftRight(4, ei0, il.Const(4, oper2->uimm), IL_FLAGWRITE_XER_CA);
 			il.AddInstruction(il.SetRegister(4, oper0->reg, ei0,
-					ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			));
 			break;
 
-		case PPC_INS_SRAD:
+		case PPC_ID_SRADx:
 			REQUIRE3OPS
 			ei0 = il.Register(8, oper1->reg);
 			ei1 = il.And(8, il.Register(8, oper2->reg), il.Const(8, 0x3f));
 			ei0 = il.ArithShiftRight(8, ei0, ei1, IL_FLAGWRITE_XER_CA);
 			il.AddInstruction(il.SetRegister(8, oper0->reg, ei0,
-					ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			));
 			break;
 
-		case PPC_INS_SRADI:
+		case PPC_ID_SRADIx:
 			REQUIRE3OPS
 			ei0 = il.Register(8, oper1->reg);
-			ei0 = il.ArithShiftRight(8, ei0, il.Const(8, oper2->imm), IL_FLAGWRITE_XER_CA);
+			ei0 = il.ArithShiftRight(8, ei0, il.Const(8, oper2->uimm), IL_FLAGWRITE_XER_CA);
 			il.AddInstruction(il.SetRegister(8, oper0->reg, ei0,
-					ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			));
 			break;
 
-		case PPC_INS_MULLW:
+		case PPC_ID_MULLWx:
 			REQUIRE3OPS
 			ei0 = il.Register(4, oper1->reg);
-			ei0 = il.Mult(4, ei0, il.Register(4, oper2->reg));
+			ei0 = il.MultDoublePrecUnsigned(4, ei0, il.Register(4, oper2->reg));
+			ei0 = il.LowPart(4, ei0);
 			il.AddInstruction(il.SetRegister(4, oper0->reg, ei0,
-					ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			));
 			break;
 
-		case PPC_INS_MULLI:
+		case PPC_ID_MULLI:
 			REQUIRE3OPS
 			ei0 = il.Register(4, oper1->reg);
-			ei0 = il.Mult(4, ei0, il.Const(4, oper2->imm));
+			ei0 = il.MultDoublePrecUnsigned(4, ei0, il.Const(4, oper2->uimm));
+			ei0 = il.LowPart(4, ei0);
 			il.AddInstruction(il.SetRegister(4, oper0->reg, ei0));
 			break;
 
-		case PPC_INS_MULHW:
+		case PPC_ID_MULHWx:
 			REQUIRE3OPS
 			ei0 = il.Register(4, oper1->reg);
 			ei0 = il.MultDoublePrecSigned(4, ei0, il.Register(4, oper2->reg));
-			// TODO: This may be incorrect for 64-bit mode:
-			// The 32-bit operands are the low-order 32 bits of RA and */ of RB.The high - order 32 bits of the 64 - bit product of the operands are placed into RT32 : 63. The contents of RT0 : 31 are undefined.
 			ei0 = il.LowPart(4, il.LogicalShiftRight(8, ei0, il.Const(1, 32)));
 			il.AddInstruction(il.SetRegister(4, oper0->reg, ei0,
-					ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			));
 			break;
 
-		case PPC_INS_MULHWU:
+		case PPC_ID_MULHWUx:
 			REQUIRE3OPS
 			ei0 = il.Register(4, oper1->reg);
 			ei0 = il.MultDoublePrecUnsigned(4, ei0, il.Register(4, oper2->reg));
-			// TODO: This may be incorrect for 64-bit mode:
-			// The 32-bit operands are the low-order 32 bits of RA and */ of RB.The high - order 32 bits of the 64 - bit product of the operands are placed into RT32 : 63. The contents of RT0 : 31 are undefined.
 			ei0 = il.LowPart(4, il.LogicalShiftRight(8, ei0, il.Const(1, 32)));
 			il.AddInstruction(il.SetRegister(4, oper0->reg, ei0,
-					ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			));
 			break;
 
-		case PPC_INS_DIVW:
+		case PPC_ID_DIVWx:
 			REQUIRE3OPS
 			ei0 = il.Register(4, oper1->reg);
 			ei0 = il.DivSigned(4, ei0, il.Register(4, oper2->reg));
 			il.AddInstruction(il.SetRegister(4, oper0->reg, ei0,
-					ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			));
 			break;
 
-		case PPC_INS_DIVWU:
+		case PPC_ID_DIVWUx:
 			REQUIRE3OPS
 			ei0 = il.Register(4, oper1->reg);
 			ei0 = il.DivUnsigned(4, ei0, il.Register(4, oper2->reg));
 			il.AddInstruction(il.SetRegister(4, oper0->reg, ei0,
-					ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0
+					instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0
 			));
 			break;
 
-		case PPC_INS_MR: /* move register */
+		case PPC_ID_MRx: /* move register */
 			REQUIRE2OPS
 			ei0 = il.SetRegister(addressSize_l, oper0->reg, operToIL_a(il, oper1, addressSize_l),
-				ppc->update_cr0 ? IL_FLAGWRITE_CR0_S : 0);
+				instruction->flags.rc ? IL_FLAGWRITE_CR0_S : 0);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_SC:
+		case PPC_ID_SC:
 			il.AddInstruction(il.SystemCall());
 			break;
 
-		case PPC_INS_RFI:
+		case PPC_ID_RFI:
 			il.AddInstruction(il.Return(il.Unimplemented()));
 			break;
 
-		case PPC_INS_TRAP:
+		case PPC_ID_TWU:
 			il.AddInstruction(il.Trap(0));
 			break;
 
-// =====================================
-// =====FLOATING POINT INSTRUCTIONS=====
-// =====================================
-
-		// case PPC_INS_FCMPO: /* compare (signed) word(32-bit) */
-		    // 	REQUIRE2OPS
-		    // 	ei0 = operToIL(il, oper2 ? oper1 : oper0);
-		    // 	ei1 = operToIL(il, oper2 ? oper2 : oper1);
-		    // 	ei2 = il.Sub(4, ei0, ei1, crxToFlagWriteType(oper2 ? oper0->reg : PPC_REG_CR0));
-		    // 	il.AddInstruction(ei2);
-		    // 	break;
+		// =====================================
+		// =====FLOATING POINT INSTRUCTIONS=====
+		// =====================================
 
-			// for this one, i guess the easiest thing to do is to summarize it by
-		    // the end result. For this instuction to happen, the end result is:
-		    // register Fn is stored at Rn.
-			// how do we achieve this result in IL?
-		    // had it not had the quantization, we could probably get away with
-		    // a cast and then store.
-
-		case PPC_INS_FADD:
+		case PPC_ID_FADDx:
 			REQUIRE3OPS
-			ei0 = il.FloatAdd(8, operToIL(il, oper1, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8),
-				operToIL(il, oper2, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8));
-			ei0 = il.SetRegister(8, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei0 = il.FloatAdd(8, operToIL_a(il, oper1,  8),
+				operToIL_a(il, oper2,  8));
+			ei0 = il.SetRegister(8, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_FADDS:
+		case PPC_ID_FADDSx:
 			REQUIRE3OPS
 			ei0 = il.FloatAdd(4, operToIL(il, oper1), operToIL(il, oper2));
-			ei0 = il.SetRegister(4, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei0 = il.SetRegister(4, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_FSUB:
+		case PPC_ID_FSUBx:
 			REQUIRE3OPS
-			ei0 = il.FloatSub(8, operToIL(il, oper1, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8),
-				operToIL(il, oper2, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8));
-			ei0 = il.SetRegister(8, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei0 = il.FloatSub(8, operToIL_a(il, oper1,  8),
+				operToIL_a(il, oper2,  8));
+			ei0 = il.SetRegister(8, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_FSUBS:
+		case PPC_ID_FSUBSx:
 			REQUIRE3OPS
 			ei0 = il.FloatSub(4, operToIL(il, oper1), operToIL(il, oper2));
-			ei0 = il.SetRegister(4, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei0 = il.SetRegister(4, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_FCMPU:
+		case PPC_ID_FCMPU:
 			REQUIRE3OPS
 			ei0 = il.Register(RZF, oper1->reg);
 			ei1 = il.Register(RZF, oper2->reg);
-			ei2 = il.FloatSub(RZF, ei0, ei1, crxToFlagWriteType(oper0->reg | PPC_CRX_FLOAT_MASK));
+			ei2 = il.FloatSub(RZF, ei0, ei1, crxToFlagWriteType(oper0->reg, PPC_SUF_F));
 			il.AddInstruction(ei2);
 			break;
 
-		case PPC_INS_BN_FCMPO:
+		case PPC_ID_FCMPO:
 			REQUIRE3OPS
 			ei0 = il.Register(RZF, oper1->reg);
 			ei1 = il.Register(RZF, oper2->reg);
-			ei2 = il.FloatSub(RZF, ei0, ei1, crxToFlagWriteType(oper0->reg | PPC_CRX_FLOAT_MASK));
+			ei2 = il.FloatSub(RZF, ei0, ei1, crxToFlagWriteType(oper0->reg, PPC_SUF_F));
 			il.AddInstruction(ei2);
 			break;
 
-		case PPC_INS_FMR:
+		case PPC_ID_FMRx:
 			REQUIRE2OPS
-			ei0 = il.SetRegister(8, oper0->reg, operToIL(il, oper1, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8));
+			ei0 = il.SetRegister(8, oper0->reg, operToIL_a(il, oper1,  8));
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_STFS:
+		case PPC_ID_STFS:
 			REQUIRE2OPS
 			ei0 = il.FloatConvert(4, operToIL(il, oper0));
 			ei0 = il.Store(4, operToIL(il, oper1), ei0);
@@ -1914,7 +2045,7 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_STFSX:
+		case PPC_ID_STFSX:
 			REQUIRE3OPS
 			ei0 = il.FloatConvert(4, operToIL(il, oper0));
 			ei1 = il.Add(4, operToIL(il, oper1), operToIL(il, oper2));
@@ -1923,15 +2054,15 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_STFD:
+		case PPC_ID_STFD:
 			REQUIRE2OPS
 			ei0 = il.Store(8, operToIL(il, oper1),
-				il.FloatConvert(8, operToIL(il, oper0, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8)));
+				il.FloatConvert(8, operToIL_a(il, oper0,  8)));
 			// ei0 = il.FloatConvert(8, ei0);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_LFS:
+		case PPC_ID_LFS:
 			REQUIRE2OPS
 			// ei0 = operToIL(il, oper1); // d(rA) or 0
 		    // ei0 = il.Load(4, ei0);                    // [d(rA)]
@@ -1940,10 +2071,10 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 		    // il.AddInstruction(ei1);
 
 			// alternatively, do it the way arm64 does it
-			loadstoreppcfs(il, 4, oper0, oper1);
+			load_float(il, 4, oper0, oper1);
 			break;
 
-		case PPC_INS_LFSX:
+		case PPC_ID_LFSX:
 			REQUIRE3OPS
 			// ei0 = il.Add(4, operToIL(il, oper1), operToIL(il, oper2));
 			// ei0 = il.Load(4, ei0);
@@ -1953,20 +2084,20 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			// // alternatively, do it the way arm64 does it
 			// il.AddInstruction(ei0);
 
-			loadstoreppcfs(il, 4, oper0, oper1, oper2);
+			load_float(il, 4, oper0, oper1, oper2);
 			break;
 
-		case PPC_INS_LFSU:
+		case PPC_ID_LFSU:
 			REQUIRE2OPS
-			loadstoreppcfs(il, 4, oper0, oper1, 0, true);
+			load_float(il, 4, oper0, oper1, 0, true);
 			break;
 
-		case PPC_INS_LFSUX:
+		case PPC_ID_LFSUX:
 			REQUIRE3OPS
-			loadstoreppcfs(il, 4, oper0, oper1, oper2, true);
+			load_float(il, 4, oper0, oper1, oper2, true);
 			break;
 
-		case PPC_INS_LFD:
+		case PPC_ID_LFD:
 			REQUIRE2OPS
 			// ei0 = operToIL(il, oper1); // d(rA) or 0
 		    // ei0 = il.Load(8, ei0);                    // [d(rA)]
@@ -1974,70 +2105,70 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 		    // il.AddInstruction(ei0);
 
 			// same as lfs
-			loadstoreppcfs(il, 8, oper0, oper1);
+			load_float(il, 8, oper0, oper1);
 			break;
 
-		case PPC_INS_FMUL:
+		case PPC_ID_FMULx:
 			REQUIRE3OPS
-			ei0 = il.FloatMult(8, operToIL(il, oper1, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8),
-				operToIL(il, oper2, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8));
-			ei1 = il.SetRegister(8, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei0 = il.MultDoublePrecSigned(8, operToIL_a(il, oper1,  8),
+				operToIL_a(il, oper2,  8));
+			ei1 = il.SetRegister(8, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei1);
 			break;
 
-		case PPC_INS_FMULS:
+		case PPC_ID_FMULSx:
 			REQUIRE3OPS
 			ei0 = il.FloatMult(4, operToIL(il, oper1), operToIL(il, oper2));
-			ei1 = il.SetRegister(4, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei1 = il.SetRegister(4, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei1);
 			break;
 
-		case PPC_INS_FDIV:
+		case PPC_ID_FDIVx:
 			REQUIRE3OPS
-			ei0 = il.FloatDiv(8, operToIL(il, oper1, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8),
-				operToIL(il, oper2, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8));
-			ei1 = il.SetRegister(8, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei0 = il.DivDoublePrecSigned(8, operToIL_a(il, oper1,  8),
+				operToIL_a(il, oper2,  8));
+			ei1 = il.SetRegister(8, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei1);
 			break;
 
-		case PPC_INS_FDIVS:
+		case PPC_ID_FDIVSx:
 			REQUIRE3OPS
 			ei0 = il.FloatDiv(4, operToIL(il, oper1), operToIL(il, oper2));
-			ei1 = il.SetRegister(4, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei1 = il.SetRegister(4, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei1);
 			break;
 
-		case PPC_INS_FMADD:
+		case PPC_ID_FMADDx:
 			REQUIRE4OPS
-			ei0 = il.FloatMult(8, operToIL(il, oper1, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8),
-				operToIL(il, oper3, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8));
-			ei0 = il.FloatAdd(8, ei0, operToIL(il, oper2, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8));
-			ei1 = il.SetRegister(8, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei0 = il.FloatMult(8, operToIL_a(il, oper1,  8),
+				operToIL_a(il, oper3,  8));
+			ei0 = il.FloatAdd(8, ei0, operToIL_a(il, oper2,  8));
+			ei1 = il.SetRegister(8, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei1);
 			break;
 
-		case PPC_INS_FMADDS:
+		case PPC_ID_FMADDSx:
 			REQUIRE4OPS
-			ei0 = il.FloatMult(4, operToIL(il, oper1), operToIL(il, oper3), (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
-			ei0 = il.FloatAdd(4, ei0, operToIL(il, oper2), (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei0 = il.FloatMult(4, operToIL(il, oper1), operToIL(il, oper3), (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
+			ei0 = il.FloatAdd(4, ei0, operToIL(il, oper2), (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			ei1 = il.SetRegister(4, oper0->reg, ei0);
 			il.AddInstruction(ei1);
 			break;
 
-		case PPC_INS_FMSUB:
+		case PPC_ID_FMSUBx:
 			REQUIRE4OPS
-			ei0 = il.FloatMult(8, operToIL(il, oper1, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8),
-				operToIL(il, oper3, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8));
-			ei0 = il.FloatSub(8, ei0, operToIL(il, oper2, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8));
-			ei1 = il.SetRegister(8, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei0 = il.FloatMult(8, operToIL_a(il, oper1,  8),
+				operToIL_a(il, oper3,  8));
+			ei0 = il.FloatSub(8, ei0, operToIL_a(il, oper2,  8));
+			ei1 = il.SetRegister(8, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei1);
 			break;
 
-		case PPC_INS_FMSUBS:
+		case PPC_ID_FMSUBSx:
 			REQUIRE4OPS
 			ei0 = il.FloatMult(4, operToIL(il, oper1), operToIL(il, oper3));
 			ei0 = il.FloatSub(4, ei0, operToIL(il, oper2));
-			ei1 = il.SetRegister(4, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei1 = il.SetRegister(4, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei1);
 			break;
 
@@ -2045,108 +2176,108 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 		// bits 32-63 of a double reg to that result, ignoring the lower 32 bits 0-31.
 		// TODO: needs further testing to verify that this is functional, and verify that the
 		// method used was correct, as well as the registers afffected, like FPSCR.
-		case PPC_INS_FCTIWZ:
+		case PPC_ID_FCTIWZx:
 			REQUIRE2OPS
 			ei0 = il.FloatTrunc(RZF, operToIL(il, oper1));
 			ei1 = il.Const(4, 32);
 			ei2 = il.ShiftLeft(8, ei0, ei1);
-			ei0 = il.SetRegister(8, oper0->reg, ei2, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei0 = il.SetRegister(8, oper0->reg, ei2, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_FNEG:
+		case PPC_ID_FNEGx:
 			REQUIRE2OPS
 			ei0 = il.FloatNeg(4, operToIL(il, oper1));
-			ei0 = il.SetRegister(4, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei0 = il.SetRegister(4, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_FNMADD:
+		case PPC_ID_FNMADDx:
 			REQUIRE4OPS
-			ei0 = il.FloatMult(8, operToIL(il, oper1, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8),
-				operToIL(il, oper3, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8));
-			ei0 = il.FloatAdd(8, ei0, operToIL(il, oper2, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8));
+			ei0 = il.FloatMult(8, operToIL_a(il, oper1,  8),
+				operToIL_a(il, oper3,  8));
+			ei0 = il.FloatAdd(8, ei0, operToIL_a(il, oper2,  8));
 			ei0 = il.FloatNeg(8, ei0);
-			ei1 = il.SetRegister(8, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei1 = il.SetRegister(8, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei1);
 			break;
 
-		case PPC_INS_FNMADDS:
+		case PPC_ID_FNMADDSx:
 			REQUIRE4OPS
-			ei0 = il.FloatMult(4, operToIL(il, oper1), operToIL(il, oper3), (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
-			ei0 = il.FloatAdd(4, ei0, operToIL(il, oper2), (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei0 = il.FloatMult(4, operToIL(il, oper1), operToIL(il, oper3), (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
+			ei0 = il.FloatAdd(4, ei0, operToIL(il, oper2), (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			ei0 = il.FloatNeg(4, ei0);
 			ei1 = il.SetRegister(4, oper0->reg, ei0);
 			il.AddInstruction(ei1);
 			break;
 
-		case PPC_INS_FNMSUB:
+		case PPC_ID_FNMSUBx:
 			REQUIRE4OPS
-			ei0 = il.FloatMult(8, operToIL(il, oper1, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8),
-				operToIL(il, oper3, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8));
-			ei0 = il.FloatSub(8, ei0, operToIL(il, oper2, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8));
+			ei0 = il.FloatMult(8, operToIL_a(il, oper1,  8),
+				operToIL_a(il, oper3,  8));
+			ei0 = il.FloatSub(8, ei0, operToIL_a(il, oper2,  8));
 			ei0 = il.FloatNeg(8, ei0);
-			ei1 = il.SetRegister(8, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei1 = il.SetRegister(8, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei1);
 			break;
 
-		case PPC_INS_FNMSUBS:
+		case PPC_ID_FNMSUBSx:
 			REQUIRE4OPS
 			ei0 = il.FloatMult(4, operToIL(il, oper1), operToIL(il, oper3));
 			ei0 = il.FloatSub(4, ei0, operToIL(il, oper2));
 			ei0 = il.FloatNeg(4, ei0);
-			ei1 = il.SetRegister(4, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei1 = il.SetRegister(4, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei1);
 			break;
 
-		case PPC_INS_FABS:
+		case PPC_ID_FABSx:
 			REQUIRE2OPS
 			ei0 = il.FloatAbs(4, operToIL(il, oper1));
-			ei1 = il.SetRegister(4, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei1 = il.SetRegister(4, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei1);
 			break;
 
-		case PPC_INS_FNABS:
+		case PPC_ID_FNABSx:
 			REQUIRE2OPS
 			ei0 = il.FloatAbs(4, operToIL(il, oper1));
 			ei0 = il.FloatNeg(4, ei0);
-			ei1 = il.SetRegister(4, oper0->reg, ei0, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei1 = il.SetRegister(4, oper0->reg, ei0, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei1);
 			break;
 
 		// TODO: needs more testing to make sure that stuff is good. the decompilation is a
 		// little rough, seems to be making the const double 1 into an int by default,
 		// gonna have to figure out how if its right and FPSCR is correct.
-		case PPC_INS_FRSQRTE:
+		case PPC_ID_FRSQRTEx:
 			REQUIRE2OPS
 			ei0 = il.FloatConstDouble(1);
-			ei1 = il.FloatSqrt(8, operToIL(il, oper1, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8));
-			ei1 = il.FloatDiv(8, ei0, ei1);
-			ei1 = il.SetRegister(8, oper0->reg, ei1, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei1 = il.FloatSqrt(8, operToIL_a(il, oper1,  8));
+			ei1 = il.DivDoublePrecSigned(8, ei0, ei1);
+			ei1 = il.SetRegister(8, oper0->reg, ei1, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei1);
 			break;
 
-		case PPC_INS_FRSQRTES:
+		case PPC_ID_FRSQRTESx:
 			REQUIRE2OPS
 			ei0 = il.FloatConstSingle(1);
-			ei1 = il.FloatSqrt(4, operToIL(il, oper1, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 8));
+			ei1 = il.FloatSqrt(4, operToIL_a(il, oper1,  8));
 			ei1 = il.FloatDiv(4, ei0, ei1);
-			ei1 = il.SetRegister(4, oper0->reg, ei1, (ppc->update_cr0) ? IL_FLAGWRITE_CR0_F : 0);
+			ei1 = il.SetRegister(4, oper0->reg, ei1, (instruction->flags.rc) ? IL_FLAGWRITE_CR0_F : 0);
 			il.AddInstruction(ei1);
 			break;
 
-		case PPC_INS_CNTLZW:
+		case PPC_ID_CNTLZWx:
 			ei0 = il.Intrinsic({RegisterOrFlag::Register(oper1->reg)}, PPC_INTRIN_CNTLZW,
 				{operToIL(il, oper0)});
 			il.AddInstruction(ei0);
 			break;
 
-		case PPC_INS_PSQ_ST:
+		case PPC_ID_PAIREDSINGLE_PSQ_ST:
 			REQUIRE4OPS
-		    MYLOG("0x%08x psq_st args f%d r%d[%d] w:%lldd gcqr:%lld\n",
-		      (uint32_t)addr, oper0->reg - PPC_REG_F0, oper1->mem.base - PPC_REG_R0, oper1->mem.disp, oper2->imm,
-		      oper3->imm);
-		    MYLOG("opcount %d insn pnem %s\n", ppc->op_count, insn->op_str);
+		    // MYLOG("0x%08x psq_st args f%d r%d[%d] w:%lldd gcqr:%lld\n",
+		    //   (uint32_t)addr, oper0->reg - PPC_REG_F0, oper1->mem.base - PPC_REG_R0, oper1->mem.disp, oper2->imm,
+		    //   oper3->imm);
+		    // MYLOG("opcount %d insn pnem %s\n", ppc->op_count, instruction->op_str);
 
 			// w_l = oper2->imm;
 
@@ -2156,8 +2287,8 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 				{RegisterOrFlag::Register(oper0->reg)},
 				PPC_PS_INTRIN_QUANTIZE,
 				{
-					operToIL(il, oper0, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 4),
-					il.Const(4, oper3->imm)
+					operToIL(il, oper0),
+					il.Const(4, oper3->uimm)
 					}
 				);
 
@@ -2167,7 +2298,7 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			ei0 = il.Store(8, operToIL(il, oper1),
 				// temporary measure to allow it to resemble the instruction, just oper2il oper0
 		        // ei0
-				operToIL(il, oper0, PPC_IL_OPTIONS_DEFAULT, PPC_IL_EXTRA_DEFAULT, 4)
+				operToIL(il, oper0)
 				// ei2
 			);
 			il.AddInstruction(ei0);
@@ -2179,7 +2310,7 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			// }
 			break;
 
-		case PPC_INS_PSQ_L:
+		case PPC_ID_PAIREDSINGLE_PSQ_L:
 			REQUIRE4OPS
 		    // w_l = oper2->imm;
 
@@ -2190,7 +2321,7 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 				{
 					ei0,
 					operToIL(il, oper0),
-					il.Const(4, oper3->imm)
+					il.Const(4, oper3->uimm)
 					}
 				);
 
@@ -2204,7 +2335,7 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 
 			break;
 
-		case PPC_INS_FRSP:
+		case PPC_ID_FRSPx:
 			ei0 = il.Intrinsic(
 				{RegisterOrFlag::Register(oper0->reg)},
 				PPC_INTRIN_FRSP,
@@ -2212,765 +2343,14 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 			il.AddInstruction(ei0);
 			break;
 
-			// =====================================
-		    // =====TO BE DEFINED INSTRUCTIONS======
-		    // =====================================
-
-		case PPC_INS_BCL:
-		case PPC_INS_BCLR:
-		case PPC_INS_BCLRL:
-		case PPC_INS_CNTLZD:
-		case PPC_INS_DCBA:
-		case PPC_INS_DCBF:
-		case PPC_INS_DCBI:
-		case PPC_INS_DCBST:
-		case PPC_INS_DCBT:
-		case PPC_INS_DCBTST:
-		case PPC_INS_DCBZ:
-		case PPC_INS_DCBZL:
-		case PPC_INS_DCCCI:
-		case PPC_INS_DIVD:
-		case PPC_INS_DIVDU:
-		case PPC_INS_DSS:
-		case PPC_INS_DSSALL:
-		case PPC_INS_DST:
-		case PPC_INS_DSTST:
-		case PPC_INS_DSTSTT:
-		case PPC_INS_DSTT:
-		case PPC_INS_EIEIO:
-		case PPC_INS_EVABS:
-		case PPC_INS_EVADDIW:
-		case PPC_INS_EVADDSMIAAW:
-		case PPC_INS_EVADDSSIAAW:
-		case PPC_INS_EVADDUMIAAW:
-		case PPC_INS_EVADDUSIAAW:
-		case PPC_INS_EVADDW:
-		case PPC_INS_EVAND:
-		case PPC_INS_EVANDC:
-		case PPC_INS_EVCMPEQ:
-		case PPC_INS_EVCMPGTS:
-		case PPC_INS_EVCMPGTU:
-		case PPC_INS_EVCMPLTS:
-		case PPC_INS_EVCMPLTU:
-		case PPC_INS_EVCNTLSW:
-		case PPC_INS_EVCNTLZW:
-		case PPC_INS_EVDIVWS:
-		case PPC_INS_EVDIVWU:
-		case PPC_INS_EVEQV:
-		case PPC_INS_EVEXTSB:
-		case PPC_INS_EVEXTSH:
-		case PPC_INS_EVLDD:
-		case PPC_INS_EVLDDX:
-		case PPC_INS_EVLDH:
-		case PPC_INS_EVLDHX:
-		case PPC_INS_EVLDW:
-		case PPC_INS_EVLDWX:
-		case PPC_INS_EVLHHESPLAT:
-		case PPC_INS_EVLHHESPLATX:
-		case PPC_INS_EVLHHOSSPLAT:
-		case PPC_INS_EVLHHOSSPLATX:
-		case PPC_INS_EVLHHOUSPLAT:
-		case PPC_INS_EVLHHOUSPLATX:
-		case PPC_INS_EVLWHE:
-		case PPC_INS_EVLWHEX:
-		case PPC_INS_EVLWHOS:
-		case PPC_INS_EVLWHOSX:
-		case PPC_INS_EVLWHOU:
-		case PPC_INS_EVLWHOUX:
-		case PPC_INS_EVLWHSPLAT:
-		case PPC_INS_EVLWHSPLATX:
-		case PPC_INS_EVLWWSPLAT:
-		case PPC_INS_EVLWWSPLATX:
-		case PPC_INS_EVMERGEHI:
-		case PPC_INS_EVMERGEHILO:
-		case PPC_INS_EVMERGELO:
-		case PPC_INS_EVMERGELOHI:
-		case PPC_INS_EVMHEGSMFAA:
-		case PPC_INS_EVMHEGSMFAN:
-		case PPC_INS_EVMHEGSMIAA:
-		case PPC_INS_EVMHEGSMIAN:
-		case PPC_INS_EVMHEGUMIAA:
-		case PPC_INS_EVMHEGUMIAN:
-		case PPC_INS_EVMHESMF:
-		case PPC_INS_EVMHESMFA:
-		case PPC_INS_EVMHESMFAAW:
-		case PPC_INS_EVMHESMFANW:
-		case PPC_INS_EVMHESMI:
-		case PPC_INS_EVMHESMIA:
-		case PPC_INS_EVMHESMIAAW:
-		case PPC_INS_EVMHESMIANW:
-		case PPC_INS_EVMHESSF:
-		case PPC_INS_EVMHESSFA:
-		case PPC_INS_EVMHESSFAAW:
-		case PPC_INS_EVMHESSFANW:
-		case PPC_INS_EVMHESSIAAW:
-		case PPC_INS_EVMHESSIANW:
-		case PPC_INS_EVMHEUMI:
-		case PPC_INS_EVMHEUMIA:
-		case PPC_INS_EVMHEUMIAAW:
-		case PPC_INS_EVMHEUMIANW:
-		case PPC_INS_EVMHEUSIAAW:
-		case PPC_INS_EVMHEUSIANW:
-		case PPC_INS_EVMHOGSMFAA:
-		case PPC_INS_EVMHOGSMFAN:
-		case PPC_INS_EVMHOGSMIAA:
-		case PPC_INS_EVMHOGSMIAN:
-		case PPC_INS_EVMHOGUMIAA:
-		case PPC_INS_EVMHOGUMIAN:
-		case PPC_INS_EVMHOSMF:
-		case PPC_INS_EVMHOSMFA:
-		case PPC_INS_EVMHOSMFAAW:
-		case PPC_INS_EVMHOSMFANW:
-		case PPC_INS_EVMHOSMI:
-		case PPC_INS_EVMHOSMIA:
-		case PPC_INS_EVMHOSMIAAW:
-		case PPC_INS_EVMHOSMIANW:
-		case PPC_INS_EVMHOSSF:
-		case PPC_INS_EVMHOSSFA:
-		case PPC_INS_EVMHOSSFAAW:
-		case PPC_INS_EVMHOSSFANW:
-		case PPC_INS_EVMHOSSIAAW:
-		case PPC_INS_EVMHOSSIANW:
-		case PPC_INS_EVMHOUMI:
-		case PPC_INS_EVMHOUMIA:
-		case PPC_INS_EVMHOUMIAAW:
-		case PPC_INS_EVMHOUMIANW:
-		case PPC_INS_EVMHOUSIAAW:
-		case PPC_INS_EVMHOUSIANW:
-		case PPC_INS_EVMRA:
-		case PPC_INS_EVMWHSMF:
-		case PPC_INS_EVMWHSMFA:
-		case PPC_INS_EVMWHSMI:
-		case PPC_INS_EVMWHSMIA:
-		case PPC_INS_EVMWHSSF:
-		case PPC_INS_EVMWHSSFA:
-		case PPC_INS_EVMWHUMI:
-		case PPC_INS_EVMWHUMIA:
-		case PPC_INS_EVMWLSMIAAW:
-		case PPC_INS_EVMWLSMIANW:
-		case PPC_INS_EVMWLSSIAAW:
-		case PPC_INS_EVMWLSSIANW:
-		case PPC_INS_EVMWLUMI:
-		case PPC_INS_EVMWLUMIA:
-		case PPC_INS_EVMWLUMIAAW:
-		case PPC_INS_EVMWLUMIANW:
-		case PPC_INS_EVMWLUSIAAW:
-		case PPC_INS_EVMWLUSIANW:
-		case PPC_INS_EVMWSMF:
-		case PPC_INS_EVMWSMFA:
-		case PPC_INS_EVMWSMFAA:
-		case PPC_INS_EVMWSMFAN:
-		case PPC_INS_EVMWSMI:
-		case PPC_INS_EVMWSMIA:
-		case PPC_INS_EVMWSMIAA:
-		case PPC_INS_EVMWSMIAN:
-		case PPC_INS_EVMWSSF:
-		case PPC_INS_EVMWSSFA:
-		case PPC_INS_EVMWSSFAA:
-		case PPC_INS_EVMWSSFAN:
-		case PPC_INS_EVMWUMI:
-		case PPC_INS_EVMWUMIA:
-		case PPC_INS_EVMWUMIAA:
-		case PPC_INS_EVMWUMIAN:
-		case PPC_INS_EVNAND:
-		case PPC_INS_EVNEG:
-		case PPC_INS_EVNOR:
-		case PPC_INS_EVOR:
-		case PPC_INS_EVORC:
-		case PPC_INS_EVRLW:
-		case PPC_INS_EVRLWI:
-		case PPC_INS_EVRNDW:
-		case PPC_INS_EVSLW:
-		case PPC_INS_EVSLWI:
-		case PPC_INS_EVSPLATFI:
-		case PPC_INS_EVSPLATI:
-		case PPC_INS_EVSRWIS:
-		case PPC_INS_EVSRWIU:
-		case PPC_INS_EVSRWS:
-		case PPC_INS_EVSRWU:
-		case PPC_INS_EVSTDD:
-		case PPC_INS_EVSTDDX:
-		case PPC_INS_EVSTDH:
-		case PPC_INS_EVSTDHX:
-		case PPC_INS_EVSTDW:
-		case PPC_INS_EVSTDWX:
-		case PPC_INS_EVSTWHE:
-		case PPC_INS_EVSTWHEX:
-		case PPC_INS_EVSTWHO:
-		case PPC_INS_EVSTWHOX:
-		case PPC_INS_EVSTWWE:
-		case PPC_INS_EVSTWWEX:
-		case PPC_INS_EVSTWWO:
-		case PPC_INS_EVSTWWOX:
-		case PPC_INS_EVSUBFSMIAAW:
-		case PPC_INS_EVSUBFSSIAAW:
-		case PPC_INS_EVSUBFUMIAAW:
-		case PPC_INS_EVSUBFUSIAAW:
-		case PPC_INS_EVSUBFW:
-		case PPC_INS_EVSUBIFW:
-		case PPC_INS_EVXOR:
-		case PPC_INS_FCFID:
-		case PPC_INS_FCFIDS:
-		case PPC_INS_FCFIDU:
-		case PPC_INS_FCFIDUS:
-		case PPC_INS_FCPSGN:
-		case PPC_INS_FCTID:
-		case PPC_INS_FCTIDUZ:
-		case PPC_INS_FCTIDZ:
-		case PPC_INS_FCTIW:
-		case PPC_INS_FCTIWUZ:
-		case PPC_INS_FRE:
-		case PPC_INS_FRES:
-		case PPC_INS_FRIM:
-		case PPC_INS_FRIN:
-		case PPC_INS_FRIP:
-		case PPC_INS_FRIZ:
-		case PPC_INS_FSEL:
-		case PPC_INS_FSQRT:
-		case PPC_INS_FSQRTS:
-		case PPC_INS_ICBI:
-		case PPC_INS_ICCCI:
-		case PPC_INS_ISYNC:
-		case PPC_INS_LDARX:
-		case PPC_INS_LDBRX:
-		case PPC_INS_LFDU:
-		case PPC_INS_LFDUX:
-		case PPC_INS_LFDX:
-		case PPC_INS_LFIWAX:
-		case PPC_INS_LFIWZX:
-		case PPC_INS_LSWI:
-		case PPC_INS_LVEBX:
-		case PPC_INS_LVEHX:
-		case PPC_INS_LVEWX:
-		case PPC_INS_LVSL:
-		case PPC_INS_LVSR:
-		case PPC_INS_LVX:
-		case PPC_INS_LVXL:
-		case PPC_INS_LWA:
-		case PPC_INS_LWARX:
-		case PPC_INS_LWAUX:
-		case PPC_INS_LWAX:
-		case PPC_INS_LXSDX:
-		case PPC_INS_LXVD2X:
-		case PPC_INS_LXVDSX:
-		case PPC_INS_LXVW4X:
-		case PPC_INS_MBAR:
-		case PPC_INS_MCRF:
-		case PPC_INS_MFDCR:
-		case PPC_INS_MFFS:
-		case PPC_INS_MFMSR:
-		case PPC_INS_MFOCRF:
-		case PPC_INS_MFSPR:
-		case PPC_INS_MFSR:
-		case PPC_INS_MFSRIN:
-		case PPC_INS_MFTB:
-		case PPC_INS_MFVSCR:
-		case PPC_INS_MSYNC:
-		case PPC_INS_MTDCR:
-		case PPC_INS_MTFSB0:
-		case PPC_INS_MTFSB1:
-		case PPC_INS_MTFSF:
-		case PPC_INS_MTMSR:
-		case PPC_INS_MTMSRD:
-		case PPC_INS_MTOCRF:
-		case PPC_INS_MTSPR:
-		case PPC_INS_MTSR:
-		case PPC_INS_MTSRIN:
-		case PPC_INS_MTVSCR:
-		case PPC_INS_MULHD:
-		case PPC_INS_MULHDU:
-		case PPC_INS_MULLD:
-		case PPC_INS_POPCNTD:
-		case PPC_INS_POPCNTW:
-		case PPC_INS_RFCI:
-		case PPC_INS_RFDI:
-		case PPC_INS_RFID:
-		case PPC_INS_RFMCI:
-		case PPC_INS_RLDCL:
-		case PPC_INS_RLDCR:
-		case PPC_INS_RLDIC:
-		case PPC_INS_RLDICL:
-		case PPC_INS_RLDICR:
-		case PPC_INS_RLDIMI:
-		case PPC_INS_SLBIA:
-		case PPC_INS_SLBIE:
-		case PPC_INS_SLBMFEE:
-		case PPC_INS_SLBMTE:
-		case PPC_INS_STDBRX:
-		case PPC_INS_STDCX:
-		case PPC_INS_STFDU:
-		case PPC_INS_STFDUX:
-		case PPC_INS_STFDX:
-		case PPC_INS_STFIWX:
-		case PPC_INS_STFSU:
-		case PPC_INS_STFSUX:
-		case PPC_INS_STSWI:
-		case PPC_INS_STVEBX:
-		case PPC_INS_STVEHX:
-		case PPC_INS_STVEWX:
-		case PPC_INS_STVX:
-		case PPC_INS_STVXL:
-		case PPC_INS_STWCX:
-		case PPC_INS_STXSDX:
-		case PPC_INS_STXVD2X:
-		case PPC_INS_STXVW4X:
-		case PPC_INS_SYNC:
-		case PPC_INS_TD:
-		case PPC_INS_TDI:
-		case PPC_INS_TLBIA:
-		case PPC_INS_TLBIE:
-		case PPC_INS_TLBIEL:
-		case PPC_INS_TLBIVAX:
-		case PPC_INS_TLBLD:
-		case PPC_INS_TLBLI:
-		case PPC_INS_TLBRE:
-		case PPC_INS_TLBSX:
-		case PPC_INS_TLBSYNC:
-		case PPC_INS_TLBWE:
-		case PPC_INS_TW:
-		case PPC_INS_TWI:
-		case PPC_INS_VADDCUW:
-		case PPC_INS_VADDFP:
-		case PPC_INS_VADDSBS:
-		case PPC_INS_VADDSHS:
-		case PPC_INS_VADDSWS:
-		case PPC_INS_VADDUBM:
-		case PPC_INS_VADDUBS:
-		case PPC_INS_VADDUHM:
-		case PPC_INS_VADDUHS:
-		case PPC_INS_VADDUWM:
-		case PPC_INS_VADDUWS:
-		case PPC_INS_VAND:
-		case PPC_INS_VANDC:
-		case PPC_INS_VAVGSB:
-		case PPC_INS_VAVGSH:
-		case PPC_INS_VAVGSW:
-		case PPC_INS_VAVGUB:
-		case PPC_INS_VAVGUH:
-		case PPC_INS_VAVGUW:
-		case PPC_INS_VCFSX:
-		case PPC_INS_VCFUX:
-		case PPC_INS_VCMPBFP:
-		case PPC_INS_VCMPEQFP:
-		case PPC_INS_VCMPEQUB:
-		case PPC_INS_VCMPEQUH:
-		case PPC_INS_VCMPEQUW:
-		case PPC_INS_VCMPGEFP:
-		case PPC_INS_VCMPGTFP:
-		case PPC_INS_VCMPGTSB:
-		case PPC_INS_VCMPGTSH:
-		case PPC_INS_VCMPGTSW:
-		case PPC_INS_VCMPGTUB:
-		case PPC_INS_VCMPGTUH:
-		case PPC_INS_VCMPGTUW:
-		case PPC_INS_VCTSXS:
-		case PPC_INS_VCTUXS:
-		case PPC_INS_VEXPTEFP:
-		case PPC_INS_VLOGEFP:
-		case PPC_INS_VMADDFP:
-		case PPC_INS_VMAXFP:
-		case PPC_INS_VMAXSB:
-		case PPC_INS_VMAXSH:
-		case PPC_INS_VMAXSW:
-		case PPC_INS_VMAXUB:
-		case PPC_INS_VMAXUH:
-		case PPC_INS_VMAXUW:
-		case PPC_INS_VMHADDSHS:
-		case PPC_INS_VMHRADDSHS:
-		case PPC_INS_VMINFP:
-		case PPC_INS_VMINSB:
-		case PPC_INS_VMINSH:
-		case PPC_INS_VMINSW:
-		case PPC_INS_VMINUB:
-		case PPC_INS_VMINUH:
-		case PPC_INS_VMINUW:
-		case PPC_INS_VMLADDUHM:
-		case PPC_INS_VMRGHB:
-		case PPC_INS_VMRGHH:
-		case PPC_INS_VMRGHW:
-		case PPC_INS_VMRGLB:
-		case PPC_INS_VMRGLH:
-		case PPC_INS_VMRGLW:
-		case PPC_INS_VMSUMMBM:
-		case PPC_INS_VMSUMSHM:
-		case PPC_INS_VMSUMSHS:
-		case PPC_INS_VMSUMUBM:
-		case PPC_INS_VMSUMUHM:
-		case PPC_INS_VMSUMUHS:
-		case PPC_INS_VMULESB:
-		case PPC_INS_VMULESH:
-		case PPC_INS_VMULEUB:
-		case PPC_INS_VMULEUH:
-		case PPC_INS_VMULOSB:
-		case PPC_INS_VMULOSH:
-		case PPC_INS_VMULOUB:
-		case PPC_INS_VMULOUH:
-		case PPC_INS_VNMSUBFP:
-		case PPC_INS_VNOR:
-		case PPC_INS_VOR:
-		case PPC_INS_VPERM:
-		case PPC_INS_VPKPX:
-		case PPC_INS_VPKSHSS:
-		case PPC_INS_VPKSHUS:
-		case PPC_INS_VPKSWSS:
-		case PPC_INS_VPKSWUS:
-		case PPC_INS_VPKUHUM:
-		case PPC_INS_VPKUHUS:
-		case PPC_INS_VPKUWUM:
-		case PPC_INS_VPKUWUS:
-		case PPC_INS_VREFP:
-		case PPC_INS_VRFIM:
-		case PPC_INS_VRFIN:
-		case PPC_INS_VRFIP:
-		case PPC_INS_VRFIZ:
-		case PPC_INS_VRLB:
-		case PPC_INS_VRLH:
-		case PPC_INS_VRLW:
-		case PPC_INS_VRSQRTEFP:
-		case PPC_INS_VSEL:
-		case PPC_INS_VSL:
-		case PPC_INS_VSLB:
-		case PPC_INS_VSLDOI:
-		case PPC_INS_VSLH:
-		case PPC_INS_VSLO:
-		case PPC_INS_VSLW:
-		case PPC_INS_VSPLTB:
-		case PPC_INS_VSPLTH:
-		case PPC_INS_VSPLTISB:
-		case PPC_INS_VSPLTISH:
-		case PPC_INS_VSPLTISW:
-		case PPC_INS_VSPLTW:
-		case PPC_INS_VSR:
-		case PPC_INS_VSRAB:
-		case PPC_INS_VSRAH:
-		case PPC_INS_VSRAW:
-		case PPC_INS_VSRB:
-		case PPC_INS_VSRH:
-		case PPC_INS_VSRO:
-		case PPC_INS_VSRW:
-		case PPC_INS_VSUBCUW:
-		case PPC_INS_VSUBFP:
-		case PPC_INS_VSUBSBS:
-		case PPC_INS_VSUBSHS:
-		case PPC_INS_VSUBSWS:
-		case PPC_INS_VSUBUBM:
-		case PPC_INS_VSUBUBS:
-		case PPC_INS_VSUBUHM:
-		case PPC_INS_VSUBUHS:
-		case PPC_INS_VSUBUWM:
-		case PPC_INS_VSUBUWS:
-		case PPC_INS_VSUM2SWS:
-		case PPC_INS_VSUM4SBS:
-		case PPC_INS_VSUM4SHS:
-		case PPC_INS_VSUM4UBS:
-		case PPC_INS_VSUMSWS:
-		case PPC_INS_VUPKHPX:
-		case PPC_INS_VUPKHSB:
-		case PPC_INS_VUPKHSH:
-		case PPC_INS_VUPKLPX:
-		case PPC_INS_VUPKLSB:
-		case PPC_INS_VUPKLSH:
-		case PPC_INS_VXOR:
-		case PPC_INS_WAIT:
-		case PPC_INS_WRTEE:
-		case PPC_INS_WRTEEI:
-		case PPC_INS_XSABSDP:
-		case PPC_INS_XSADDDP:
-		case PPC_INS_XSCMPODP:
-		case PPC_INS_XSCMPUDP:
-		case PPC_INS_XSCPSGNDP:
-		case PPC_INS_XSCVDPSP:
-		case PPC_INS_XSCVDPSXDS:
-		case PPC_INS_XSCVDPSXWS:
-		case PPC_INS_XSCVDPUXDS:
-		case PPC_INS_XSCVDPUXWS:
-		case PPC_INS_XSCVSPDP:
-		case PPC_INS_XSCVSXDDP:
-		case PPC_INS_XSCVUXDDP:
-		case PPC_INS_XSDIVDP:
-		case PPC_INS_XSMADDADP:
-		case PPC_INS_XSMADDMDP:
-		case PPC_INS_XSMAXDP:
-		case PPC_INS_XSMINDP:
-		case PPC_INS_XSMSUBADP:
-		case PPC_INS_XSMSUBMDP:
-		case PPC_INS_XSMULDP:
-		case PPC_INS_XSNABSDP:
-		case PPC_INS_XSNEGDP:
-		case PPC_INS_XSNMADDADP:
-		case PPC_INS_XSNMADDMDP:
-		case PPC_INS_XSNMSUBADP:
-		case PPC_INS_XSNMSUBMDP:
-		case PPC_INS_XSRDPI:
-		case PPC_INS_XSRDPIC:
-		case PPC_INS_XSRDPIM:
-		case PPC_INS_XSRDPIP:
-		case PPC_INS_XSRDPIZ:
-		case PPC_INS_XSREDP:
-		case PPC_INS_XSRSQRTEDP:
-		case PPC_INS_XSSQRTDP:
-		case PPC_INS_XSSUBDP:
-		case PPC_INS_XSTDIVDP:
-		case PPC_INS_XSTSQRTDP:
-		case PPC_INS_XVABSDP:
-		case PPC_INS_XVABSSP:
-		case PPC_INS_XVADDDP:
-		case PPC_INS_XVADDSP:
-		case PPC_INS_XVCMPEQDP:
-		case PPC_INS_XVCMPEQSP:
-		case PPC_INS_XVCMPGEDP:
-		case PPC_INS_XVCMPGESP:
-		case PPC_INS_XVCMPGTDP:
-		case PPC_INS_XVCMPGTSP:
-		case PPC_INS_XVCPSGNDP:
-		case PPC_INS_XVCPSGNSP:
-		case PPC_INS_XVCVDPSP:
-		case PPC_INS_XVCVDPSXDS:
-		case PPC_INS_XVCVDPSXWS:
-		case PPC_INS_XVCVDPUXDS:
-		case PPC_INS_XVCVDPUXWS:
-		case PPC_INS_XVCVSPDP:
-		case PPC_INS_XVCVSPSXDS:
-		case PPC_INS_XVCVSPSXWS:
-		case PPC_INS_XVCVSPUXDS:
-		case PPC_INS_XVCVSPUXWS:
-		case PPC_INS_XVCVSXDDP:
-		case PPC_INS_XVCVSXDSP:
-		case PPC_INS_XVCVSXWDP:
-		case PPC_INS_XVCVSXWSP:
-		case PPC_INS_XVCVUXDDP:
-		case PPC_INS_XVCVUXDSP:
-		case PPC_INS_XVCVUXWDP:
-		case PPC_INS_XVCVUXWSP:
-		case PPC_INS_XVDIVDP:
-		case PPC_INS_XVDIVSP:
-		case PPC_INS_XVMADDADP:
-		case PPC_INS_XVMADDASP:
-		case PPC_INS_XVMADDMDP:
-		case PPC_INS_XVMADDMSP:
-		case PPC_INS_XVMAXDP:
-		case PPC_INS_XVMAXSP:
-		case PPC_INS_XVMINDP:
-		case PPC_INS_XVMINSP:
-		case PPC_INS_XVMSUBADP:
-		case PPC_INS_XVMSUBASP:
-		case PPC_INS_XVMSUBMDP:
-		case PPC_INS_XVMSUBMSP:
-		case PPC_INS_XVMULDP:
-		case PPC_INS_XVMULSP:
-		case PPC_INS_XVNABSDP:
-		case PPC_INS_XVNABSSP:
-		case PPC_INS_XVNEGDP:
-		case PPC_INS_XVNEGSP:
-		case PPC_INS_XVNMADDADP:
-		case PPC_INS_XVNMADDASP:
-		case PPC_INS_XVNMADDMDP:
-		case PPC_INS_XVNMADDMSP:
-		case PPC_INS_XVNMSUBADP:
-		case PPC_INS_XVNMSUBASP:
-		case PPC_INS_XVNMSUBMDP:
-		case PPC_INS_XVNMSUBMSP:
-		case PPC_INS_XVRDPI:
-		case PPC_INS_XVRDPIC:
-		case PPC_INS_XVRDPIM:
-		case PPC_INS_XVRDPIP:
-		case PPC_INS_XVRDPIZ:
-		case PPC_INS_XVREDP:
-		case PPC_INS_XVRESP:
-		case PPC_INS_XVRSPI:
-		case PPC_INS_XVRSPIC:
-		case PPC_INS_XVRSPIM:
-		case PPC_INS_XVRSPIP:
-		case PPC_INS_XVRSPIZ:
-		case PPC_INS_XVRSQRTEDP:
-		case PPC_INS_XVRSQRTESP:
-		case PPC_INS_XVSQRTDP:
-		case PPC_INS_XVSQRTSP:
-		case PPC_INS_XVSUBDP:
-		case PPC_INS_XVSUBSP:
-		case PPC_INS_XVTDIVDP:
-		case PPC_INS_XVTDIVSP:
-		case PPC_INS_XVTSQRTDP:
-		case PPC_INS_XVTSQRTSP:
-		case PPC_INS_XXLAND:
-		case PPC_INS_XXLANDC:
-		case PPC_INS_XXLNOR:
-		case PPC_INS_XXLOR:
-		case PPC_INS_XXLXOR:
-		case PPC_INS_XXMRGHW:
-		case PPC_INS_XXMRGLW:
-		case PPC_INS_XXPERMDI:
-		case PPC_INS_XXSEL:
-		case PPC_INS_XXSLDWI:
-		case PPC_INS_XXSPLTW:
-		case PPC_INS_BCA:
-		case PPC_INS_BCLA:
-		case PPC_INS_SLDI:
-		case PPC_INS_BTA:
-		case PPC_INS_MFBR0:
-		case PPC_INS_MFBR1:
-		case PPC_INS_MFBR2:
-		case PPC_INS_MFBR3:
-		case PPC_INS_MFBR4:
-		case PPC_INS_MFBR5:
-		case PPC_INS_MFBR6:
-		case PPC_INS_MFBR7:
-		case PPC_INS_MFXER:
-		case PPC_INS_MFRTCU:
-		case PPC_INS_MFRTCL:
-		case PPC_INS_MFDSCR:
-		case PPC_INS_MFDSISR:
-		case PPC_INS_MFDAR:
-		case PPC_INS_MFSRR2:
-		case PPC_INS_MFSRR3:
-		case PPC_INS_MFCFAR:
-		case PPC_INS_MFAMR:
-		case PPC_INS_MFPID:
-		case PPC_INS_MFTBLO:
-		case PPC_INS_MFTBHI:
-		case PPC_INS_MFDBATU:
-		case PPC_INS_MFDBATL:
-		case PPC_INS_MFIBATU:
-		case PPC_INS_MFIBATL:
-		case PPC_INS_MFDCCR:
-		case PPC_INS_MFICCR:
-		case PPC_INS_MFDEAR:
-		case PPC_INS_MFESR:
-		case PPC_INS_MFSPEFSCR:
-		case PPC_INS_MFTCR:
-		case PPC_INS_MFASR:
-		case PPC_INS_MFPVR:
-		case PPC_INS_MFTBU:
-		case PPC_INS_MTCR:
-		case PPC_INS_MTBR0:
-		case PPC_INS_MTBR1:
-		case PPC_INS_MTBR2:
-		case PPC_INS_MTBR3:
-		case PPC_INS_MTBR4:
-		case PPC_INS_MTBR5:
-		case PPC_INS_MTBR6:
-		case PPC_INS_MTBR7:
-		case PPC_INS_MTXER:
-		case PPC_INS_MTDSCR:
-		case PPC_INS_MTDSISR:
-		case PPC_INS_MTDAR:
-		case PPC_INS_MTSRR2:
-		case PPC_INS_MTSRR3:
-		case PPC_INS_MTCFAR:
-		case PPC_INS_MTAMR:
-		case PPC_INS_MTPID:
-		case PPC_INS_MTTBL:
-		case PPC_INS_MTTBU:
-		case PPC_INS_MTTBLO:
-		case PPC_INS_MTTBHI:
-		case PPC_INS_MTDBATU:
-		case PPC_INS_MTDBATL:
-		case PPC_INS_MTIBATU:
-		case PPC_INS_MTIBATL:
-		case PPC_INS_MTDCCR:
-		case PPC_INS_MTICCR:
-		case PPC_INS_MTDEAR:
-		case PPC_INS_MTESR:
-		case PPC_INS_MTSPEFSCR:
-		case PPC_INS_MTTCR:
-		case PPC_INS_ROTLD:
-		case PPC_INS_ROTLDI:
-		case PPC_INS_CLRLDI:
-		case PPC_INS_SUB:
-		case PPC_INS_SUBC:
-		case PPC_INS_LWSYNC:
-		case PPC_INS_PTESYNC:
-		case PPC_INS_TDLT:
-		case PPC_INS_TDEQ:
-		case PPC_INS_TDGT:
-		case PPC_INS_TDNE:
-		case PPC_INS_TDLLT:
-		case PPC_INS_TDLGT:
-		case PPC_INS_TDU:
-		case PPC_INS_TDLTI:
-		case PPC_INS_TDEQI:
-		case PPC_INS_TDGTI:
-		case PPC_INS_TDNEI:
-		case PPC_INS_TDLLTI:
-		case PPC_INS_TDLGTI:
-		case PPC_INS_TDUI:
-		case PPC_INS_TLBREHI:
-		case PPC_INS_TLBRELO:
-		case PPC_INS_TLBWEHI:
-		case PPC_INS_TLBWELO:
-		case PPC_INS_TWLT:
-		case PPC_INS_TWEQ:
-		case PPC_INS_TWGT:
-		case PPC_INS_TWNE:
-		case PPC_INS_TWLLT:
-		case PPC_INS_TWLGT:
-		case PPC_INS_TWU:
-		case PPC_INS_TWLTI:
-		case PPC_INS_TWEQI:
-		case PPC_INS_TWGTI:
-		case PPC_INS_TWNEI:
-		case PPC_INS_TWLLTI:
-		case PPC_INS_TWLGTI:
-		case PPC_INS_TWUI:
-		case PPC_INS_WAITRSV:
-		case PPC_INS_WAITIMPL:
-		// TODO not technically implemented but capstone misinterprettation
-		// where it is posting that XORI is 1452, though that is XNOP
-		// case PPC_INS_XNOP:
-		case PPC_INS_XVMOVDP:
-		case PPC_INS_XVMOVSP:
-		case PPC_INS_XXSPLTD:
-		case PPC_INS_XXMRGHD:
-		case PPC_INS_XXMRGLD:
-		case PPC_INS_XXSWAPD:
-		case PPC_INS_BT:
-		case PPC_INS_BF:
-		case PPC_INS_BDNZT:
-		case PPC_INS_BDNZF:
-		case PPC_INS_BDZF:
-		case PPC_INS_BDZT:
-		case PPC_INS_BFA:
-		case PPC_INS_BDNZTA:
-		case PPC_INS_BDNZFA:
-		case PPC_INS_BDZTA:
-		case PPC_INS_BDZFA:
-		case PPC_INS_BTCTR:
-		case PPC_INS_BFCTR:
-		case PPC_INS_BTCTRL:
-		case PPC_INS_BFCTRL:
-		case PPC_INS_BTL:
-		case PPC_INS_BFL:
-		case PPC_INS_BDNZTL:
-		case PPC_INS_BDNZFL:
-		case PPC_INS_BDZTL:
-		case PPC_INS_BDZFL:
-		case PPC_INS_BTLA:
-		case PPC_INS_BFLA:
-		case PPC_INS_BDNZTLA:
-		case PPC_INS_BDNZFLA:
-		case PPC_INS_BDZTLA:
-		case PPC_INS_BDZFLA:
-		case PPC_INS_BTLR:
-		case PPC_INS_BFLR:
-		case PPC_INS_BDNZTLR:
-		case PPC_INS_BDZTLR:
-		case PPC_INS_BDZFLR:
-		case PPC_INS_BTLRL:
-		case PPC_INS_BFLRL:
-		case PPC_INS_BDNZTLRL:
-		case PPC_INS_BDNZFLRL:
-		case PPC_INS_BDZTLRL:
-		case PPC_INS_BDZFLRL:
-		case PPC_INS_BRINC:
-
 		ReturnUnimpl:
 		default:
 			MYLOG("%s:%s() returning Unimplemented(...) on:\n",
 			  __FILE__, __func__);
 
-			MYLOG("    %08llx: %02X %02X %02X %02X %s %s\n",
-			  addr, data[0], data[1], data[2], data[3],
-			  res->insn.mnemonic, res->insn.op_str);
+			// MYLOG("    %08llx: %02X %02X %02X %02X %s %s\n",
+			//   addr, data[0], data[1], data[2], data[3],
+			//   res->insn.mnemonic, res->insn.op_str);
 
 			il.AddInstruction(il.Unimplemented());
 	}