diff options
| author | Pete Dietl <petedietl@gmail.com> | 2024-02-18 13:58:38 -0800 |
|---|---|---|
| committer | Rusty Wagner <rusty.wagner@gmail.com> | 2024-03-08 17:49:09 -0500 |
| commit | a542d0c9cd33fed5919c3cd9d598bb8d1a300ae8 (patch) | |
| tree | 93019642e1d3bd4abde648b09e8c3ba40c4eaedd /arch/riscv/src | |
| parent | b25a2b9fadddd07cdd85d69264d7be9de16b2537 (diff) | |
Fix RISC-V CSRRW, CSRRS, and CSRRC instr disass
Make the CSR instructions show the CSR 12-bit immediate
operand as an unsigned integer.
This is a special case of the I-instruction format, where
it is same except that the 12-bit immediate is treated as
unsigned rather than signed.
Diffstat (limited to 'arch/riscv/src')
| -rw-r--r-- | arch/riscv/src/lib.rs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/riscv/src/lib.rs b/arch/riscv/src/lib.rs index d8f6cff5..8b9fde31 100644 --- a/arch/riscv/src/lib.rs +++ b/arch/riscv/src/lib.rs @@ -1314,7 +1314,7 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo Op::Csrrw(i) => { let rd = Register::from(i.rd()); let rs1 = Liftable::lift(il, Register::from(i.rs1())); - let csr = il.const_int(4, i.imm() as u64); + let csr = il.const_int(4, i.csr() as u64); if i.rd().id() == 0 { il.intrinsic(Lifter::<Self>::NO_OUTPUTS, Intrinsic::Csrwr, [csr, rs1]) @@ -1326,7 +1326,7 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo Op::Csrrs(i) => { let rd = Register::from(i.rd()); let rs1 = Liftable::lift(il, Register::from(i.rs1())); - let csr = il.const_int(4, i.imm() as u64); + let csr = il.const_int(4, i.csr() as u64); if i.rs1().id() == 0 { il.intrinsic([rd], Intrinsic::Csrrd, [csr]).append(); @@ -1337,7 +1337,7 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo Op::Csrrc(i) => { let rd = Register::from(i.rd()); let rs1 = Liftable::lift(il, Register::from(i.rs1())); - let csr = il.const_int(4, i.imm() as u64); + let csr = il.const_int(4, i.csr() as u64); if i.rs1().id() == 0 { il.intrinsic([rd], Intrinsic::Csrrd, [csr]).append(); |