diff options
| author | Xusheng <xusheng@vector35.com> | 2024-04-04 15:50:18 +0800 |
|---|---|---|
| committer | Xusheng <xusheng@vector35.com> | 2024-04-10 19:58:15 +0800 |
| commit | 16fc31044f3b202200a6f03a538cda5f985bbecb (patch) | |
| tree | c6a769b4015d40660bfbb1f64e8a833b1a58e477 /arch/x86/code_generator | |
| parent | f2f976e7d1c8d818f512f66179f93fa575eab3c3 (diff) | |
Update xed to v2024.04.01
Diffstat (limited to 'arch/x86/code_generator')
| -rw-r--r-- | arch/x86/code_generator/iform-type-dump.txt | 13388 | ||||
| -rwxr-xr-x | arch/x86/code_generator/parse-iform-types.py | 14 |
2 files changed, 12493 insertions, 909 deletions
diff --git a/arch/x86/code_generator/iform-type-dump.txt b/arch/x86/code_generator/iform-type-dump.txt index b34b2211..7a993ef7 100644 --- a/arch/x86/code_generator/iform-type-dump.txt +++ b/arch/x86/code_generator/iform-type-dump.txt @@ -1,629 +1,466 @@ -INTRINSIC_XED_IFORM_FADD_ST0_MEMmem32real +INTRINSIC_XED_IFORM_FADD_MEMmem32real f80 rw f80 f32 r mem32real - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FADD_ST0_X87 f80 rw f80 f80 r f80 - INVALID w XED_REG_X87STATUS -INTRINSIC_XED_IFORM_FADD_ST0_MEMm64real +INTRINSIC_XED_IFORM_FADD_MEMm64real f80 rw f80 f64 r m64real - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FADD_X87_ST0 f80 rw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FMUL_ST0_MEMmem32real f80 rw f80 f32 r mem32real - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FMUL_ST0_X87 f80 rw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FMUL_ST0_MEMm64real f80 rw f80 f64 r m64real - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FMUL_X87_ST0 f80 rw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FCOMP_ST0_MEMmem32real f80 r f80 f32 r mem32real - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FCOMP_ST0_X87 f80 r f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FCOMP_ST0_X87_DCD1 f80 r f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FCOMP_ST0_X87_DED0 f80 r f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FCOMP_ST0_MEMm64real f80 r f80 f64 r m64real - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSUB_ST0_MEMmem32real f80 rw f80 f32 r mem32real - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSUB_ST0_X87 f80 rw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSUB_ST0_MEMm64real f80 rw f80 f64 r m64real - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSUB_X87_ST0 f80 rw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSUBR_ST0_MEMmem32real f80 rw f80 f32 r mem32real - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSUBR_ST0_X87 f80 rw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSUBR_ST0_MEMm64real f80 rw f80 f64 r m64real - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSUBR_X87_ST0 f80 rw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FDIV_ST0_MEMmem32real f80 rw f80 f32 r mem32real - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FDIV_ST0_X87 f80 rw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FDIV_ST0_MEMm64real f80 rw f80 f64 r m64real - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FDIV_X87_ST0 f80 rw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FDIVR_ST0_MEMmem32real f80 rw f80 f32 r mem32real - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FDIVR_ST0_X87 f80 rw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FDIVR_ST0_MEMm64real f80 rw f80 f64 r m64real - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FDIVR_X87_ST0 f80 rw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FCOM_ST0_MEMmem32real f80 r f80 f32 r mem32real - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FCOM_ST0_MEMm64real f80 r f80 f64 r m64real - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FCOM_ST0_X87 f80 r f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FCOM_ST0_X87_DCD0 f80 r f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FLD_ST0_MEMmem32real f80 w f80 f32 r mem32real - INVALID r XED_REG_X87PUSH - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FLD_ST0_X87 f80 w f80 f80 r f80 - INVALID r XED_REG_X87PUSH - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FLD_ST0_MEMmem80real f80 w f80 f80 r mem80real - INVALID r XED_REG_X87PUSH - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FLD_ST0_MEMm64real f80 w f80 f64 r m64real - INVALID r XED_REG_X87PUSH - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FST_MEMmem32real_ST0 f32 w mem32real f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FST_MEMm64real_ST0 f64 w m64real f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FST_X87_ST0 f80 w f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSTP_MEMmem32real_ST0 f32 w mem32real f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSTP_MEMmem80real_ST0 f80 w mem80real f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSTP_MEMm64real_ST0 f64 w m64real f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSTP_X87_ST0 f80 w f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSTP_X87_ST0_DFD0 f80 w f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSTP_X87_ST0_DFD1 f80 w f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSTPNCE_X87_ST0 f80 w f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FLDENV_MEMmem14 struct r mem14 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FLDENV_MEMmem28 struct r mem28 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FLDCW_MEMmem16 struct r mem16 - INVALID w XED_REG_X87CONTROL - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FNSTENV_MEMmem14 struct w mem14 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FNSTENV_MEMmem28 struct w mem28 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FNSTCW_MEMmem16 struct w mem16 - INVALID r XED_REG_X87CONTROL - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FXCH_ST0_X87 f80 rw f80 f80 rw f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FXCH_ST0_X87_DFC1 f80 rw f80 f80 rw f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FXCH_ST0_X87_DDC1 f80 rw f80 f80 rw f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FNOP INTRINSIC_XED_IFORM_FCHS f80 rw f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FABS f80 rw f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FTST f80 rw f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FXAM f80 rw f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FLD1 f80 w f80 - INVALID r XED_REG_X87PUSH - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FLDL2T f80 w f80 - INVALID r XED_REG_X87PUSH - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FLDL2E f80 w f80 - INVALID r XED_REG_X87PUSH - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FLDPI f80 w f80 - INVALID r XED_REG_X87PUSH - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FLDLG2 f80 w f80 - INVALID r XED_REG_X87PUSH - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FLDLN2 f80 w f80 - INVALID r XED_REG_X87PUSH - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FLDZ f80 w f80 - INVALID r XED_REG_X87PUSH - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_F2XM1 f80 rw f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FYL2X f80 r f80 f80 rw f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FPTAN f80 rw f80 f80 w f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FPATAN f80 r f80 f80 rw f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FXTRACT f80 rw f80 f80 w f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FPREM1 f80 rw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FDECSTP - INVALID rw XED_REG_X87STATUS INTRINSIC_XED_IFORM_FINCSTP - INVALID rw XED_REG_X87STATUS INTRINSIC_XED_IFORM_FPREM f80 rw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FYL2XP1 f80 r f80 f80 rw f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSQRT f80 rw f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSINCOS f80 rw f80 f80 w f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FRNDINT f80 rw f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSCALE f80 rw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSIN f80 rw f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FCOS f80 rw f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FIADD_ST0_MEMmem32int f80 rw f80 i32 r mem32int - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FIADD_ST0_MEMmem16int f80 rw f80 i16 r mem16int - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FIMUL_ST0_MEMmem32int f80 rw f80 i32 r mem32int - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FIMUL_ST0_MEMmem16int f80 rw f80 i16 r mem16int - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FICOM_ST0_MEMmem32int f80 r f80 i32 r mem32int - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FICOM_ST0_MEMmem16int f80 r f80 i16 r mem16int - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FICOMP_ST0_MEMmem32int f80 r f80 i32 r mem32int - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FICOMP_ST0_MEMmem16int f80 r f80 i16 r mem16int - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FISUB_ST0_MEMmem32int f80 rw f80 i32 r mem32int - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FISUB_ST0_MEMmem16int f80 rw f80 i16 r mem16int - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FISUBR_ST0_MEMmem32int f80 rw f80 i32 r mem32int - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FISUBR_ST0_MEMmem16int f80 rw f80 i16 r mem16int - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FIDIV_ST0_MEMmem32int f80 rw f80 i32 r mem32int - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FIDIV_ST0_MEMmem16int f80 rw f80 i16 r mem16int - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FIDIVR_ST0_MEMmem32int f80 rw f80 i32 r mem32int - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FIDIVR_ST0_MEMmem16int f80 rw f80 i16 r mem16int - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FCMOVB_ST0_X87 f80 cw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INVALID rw rFLAGS INTRINSIC_XED_IFORM_FCMOVE_ST0_X87 f80 cw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INVALID rw rFLAGS INTRINSIC_XED_IFORM_FCMOVBE_ST0_X87 f80 cw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INVALID rw rFLAGS INTRINSIC_XED_IFORM_FCMOVU_ST0_X87 f80 cw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INVALID rw rFLAGS INTRINSIC_XED_IFORM_FUCOMPP f80 r f80 f80 r f80 - INVALID rw XED_REG_X87POP2 - INVALID rw XED_REG_X87STATUS INTRINSIC_XED_IFORM_FILD_ST0_MEMmem32int f80 w f80 i32 r mem32int - INVALID r XED_REG_X87PUSH - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FILD_ST0_MEMmem16int f80 w f80 i16 r mem16int - INVALID r XED_REG_X87PUSH - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FILD_ST0_MEMm64int f80 w f80 i64 r m64int - INVALID r XED_REG_X87PUSH - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FISTTP_MEMmem32int_ST0 i32 w mem32int f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FISTTP_MEMm64int_ST0 i64 w m64int f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FISTTP_MEMmem16int_ST0 i16 w mem16int f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FIST_MEMmem32int_ST0 i32 w mem32int f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FIST_MEMmem16int_ST0 i16 w mem16int f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FISTP_MEMmem32int_ST0 i32 w mem32int f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FISTP_MEMmem16int_ST0 i16 w mem16int f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FISTP_MEMm64int_ST0 i64 w m64int f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FCMOVNB_ST0_X87 f80 cw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INVALID rw rFLAGS INTRINSIC_XED_IFORM_FCMOVNE_ST0_X87 f80 cw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INVALID rw rFLAGS INTRINSIC_XED_IFORM_FCMOVNBE_ST0_X87 f80 cw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INVALID rw rFLAGS INTRINSIC_XED_IFORM_FCMOVNU_ST0_X87 f80 cw f80 f80 r f80 - INVALID w XED_REG_X87STATUS INVALID rw rFLAGS INTRINSIC_XED_IFORM_FNCLEX - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FNINIT - INVALID w XED_REG_X87CONTROL - INVALID w XED_REG_X87TAG - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSETPM287_NOP @@ -634,145 +471,108 @@ INTRINSIC_XED_IFORM_FDISI8087_NOP INTRINSIC_XED_IFORM_FUCOMI_ST0_X87 f80 r f80 f80 r f80 - INVALID w XED_REG_X87STATUS INVALID w rFLAGS INTRINSIC_XED_IFORM_FCOMI_ST0_X87 f80 r f80 f80 r f80 - INVALID w XED_REG_X87STATUS INVALID w rFLAGS INTRINSIC_XED_IFORM_FRSTOR_MEMmem94 struct r mem94 - INVALID w XED_REG_X87CONTROL INTRINSIC_XED_IFORM_FRSTOR_MEMmem108 struct r mem108 - INVALID w XED_REG_X87CONTROL INTRINSIC_XED_IFORM_FNSAVE_MEMmem94 struct w mem94 - INVALID rw XED_REG_X87CONTROL - INVALID rw XED_REG_X87TAG - INVALID rw XED_REG_X87STATUS INTRINSIC_XED_IFORM_FNSAVE_MEMmem108 struct w mem108 - INVALID rw XED_REG_X87CONTROL - INVALID rw XED_REG_X87TAG - INVALID rw XED_REG_X87STATUS INTRINSIC_XED_IFORM_FNSTSW_MEMmem16 struct w mem16 - INVALID rw XED_REG_X87STATUS INTRINSIC_XED_IFORM_FNSTSW_AX - INVALID w XED_REG_AX - INVALID rw XED_REG_X87STATUS INTRINSIC_XED_IFORM_FFREE_X87 f80 r f80 - INVALID w XED_REG_X87TAG INTRINSIC_XED_IFORM_FUCOM_ST0_X87 f80 r f80 f80 r f80 - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FUCOMP_ST0_X87 f80 r f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID rw XED_REG_X87STATUS INTRINSIC_XED_IFORM_FADDP_X87_ST0 f80 rw f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FMULP_X87_ST0 f80 rw f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FCOMPP f80 r f80 f80 r f80 - INVALID r XED_REG_X87POP2 - INVALID rw XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSUBRP_X87_ST0 f80 rw f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FSUBP_X87_ST0 f80 rw f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FDIVRP_X87_ST0 f80 rw f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FDIVP_X87_ST0 f80 rw f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FBLD_ST0_MEMmem80dec f80 w f80 b80 r mem80dec - INVALID r XED_REG_X87PUSH - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FBSTP_MEMmem80dec_ST0 b80 w mem80dec f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INTRINSIC_XED_IFORM_FFREEP_X87 f80 r f80 - INVALID w XED_REG_X87TAG - INVALID r XED_REG_X87POP INTRINSIC_XED_IFORM_FUCOMIP_ST0_X87 f80 r f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INVALID w rFLAGS INTRINSIC_XED_IFORM_FCOMIP_ST0_X87 f80 r f80 f80 r f80 - INVALID r XED_REG_X87POP - INVALID w XED_REG_X87STATUS INVALID w rFLAGS INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0 u8 rw b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_IMMz int rw v + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0 u8 rw b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_IMMb int rw v + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_GPR8 @@ -787,34 +587,42 @@ INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_GPRv INTRINSIC_XED_IFORM_ADD_MEMb_IMMb_80r0 u8 rw b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ADD_GPR8_IMMb_80r0 INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ADD_MEMv_IMMz int rw v + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_ADD_GPRv_IMMz INVALID rw GPRv_B + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_ADD_MEMb_IMMb_82r0 u8 rw b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ADD_GPR8_IMMb_82r0 INVALID rw GPR8_B + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ADD_MEMv_IMMb int rw v + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ADD_GPRv_IMMb INVALID rw GPRv_B + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ADD_MEMb_GPR8 @@ -858,27 +666,32 @@ INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_03 INVALID w rFLAGS INTRINSIC_XED_IFORM_ADD_AL_IMMb - INVALID rw XED_REG_AL + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ADD_OrAX_IMMz INVALID rw OrAX + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_OR_LOCK_MEMb_IMMb_80r1 u8 rw b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_OR_LOCK_MEMv_IMMz int rw v + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_OR_LOCK_MEMb_IMMb_82r1 u8 rw b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_OR_LOCK_MEMv_IMMb int rw v + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_OR_LOCK_MEMb_GPR8 @@ -893,34 +706,42 @@ INTRINSIC_XED_IFORM_OR_LOCK_MEMv_GPRv INTRINSIC_XED_IFORM_OR_MEMb_IMMb_80r1 u8 rw b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_OR_GPR8_IMMb_80r1 INVALID rw GPR8_B + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_OR_MEMv_IMMz int rw v + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_OR_GPRv_IMMz INVALID rw GPRv_B + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_OR_MEMb_IMMb_82r1 u8 rw b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_OR_GPR8_IMMb_82r1 INVALID rw GPR8_B + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_OR_MEMv_IMMb int rw v + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_OR_GPRv_IMMb INVALID rw GPRv_B + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_OR_MEMb_GPR8 @@ -964,27 +785,32 @@ INTRINSIC_XED_IFORM_OR_GPRv_GPRv_0B INVALID w rFLAGS INTRINSIC_XED_IFORM_OR_AL_IMMb - INVALID rw XED_REG_AL + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_OR_OrAX_IMMz INVALID rw OrAX + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2 u8 rw b + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_IMMz int rw v + int r z INVALID rw rFLAGS INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2 u8 rw b + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_IMMb int rw v + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_GPR8 @@ -999,34 +825,42 @@ INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_GPRv INTRINSIC_XED_IFORM_ADC_MEMb_IMMb_80r2 u8 rw b + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_ADC_GPR8_IMMb_80r2 INVALID rw GPR8_B + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_ADC_MEMv_IMMz int rw v + int r z INVALID rw rFLAGS INTRINSIC_XED_IFORM_ADC_GPRv_IMMz INVALID rw GPRv_B + int r z INVALID rw rFLAGS INTRINSIC_XED_IFORM_ADC_MEMb_IMMb_82r2 u8 rw b + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_ADC_GPR8_IMMb_82r2 INVALID rw GPR8_B + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_ADC_MEMv_IMMb int rw v + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_ADC_GPRv_IMMb INVALID rw GPRv_B + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_ADC_MEMb_GPR8 @@ -1070,27 +904,32 @@ INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_13 INVALID rw rFLAGS INTRINSIC_XED_IFORM_ADC_AL_IMMb - INVALID rw XED_REG_AL + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_ADC_OrAX_IMMz INVALID rw OrAX + int r z INVALID rw rFLAGS INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3 u8 rw b + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_IMMz int rw v + int r z INVALID rw rFLAGS INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3 u8 rw b + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_IMMb int rw v + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_GPR8 @@ -1105,34 +944,42 @@ INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_GPRv INTRINSIC_XED_IFORM_SBB_MEMb_IMMb_80r3 u8 rw b + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_SBB_GPR8_IMMb_80r3 INVALID rw GPR8_B + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_SBB_MEMv_IMMz int rw v + int r z INVALID rw rFLAGS INTRINSIC_XED_IFORM_SBB_GPRv_IMMz INVALID rw GPRv_B + int r z INVALID rw rFLAGS INTRINSIC_XED_IFORM_SBB_MEMb_IMMb_82r3 u8 rw b + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_SBB_GPR8_IMMb_82r3 INVALID rw GPR8_B + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_SBB_MEMv_IMMb int rw v + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_SBB_GPRv_IMMb INVALID rw GPRv_B + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_SBB_MEMb_GPR8 @@ -1176,27 +1023,32 @@ INTRINSIC_XED_IFORM_SBB_GPRv_MEMv INVALID rw rFLAGS INTRINSIC_XED_IFORM_SBB_AL_IMMb - INVALID rw XED_REG_AL + i8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_SBB_OrAX_IMMz INVALID rw OrAX + int r z INVALID rw rFLAGS INTRINSIC_XED_IFORM_AND_LOCK_MEMb_IMMb_80r4 u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_AND_LOCK_MEMv_IMMz int rw v + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_AND_LOCK_MEMb_IMMb_82r4 u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_AND_LOCK_MEMv_IMMb int rw v + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_AND_LOCK_MEMb_GPR8 @@ -1211,34 +1063,42 @@ INTRINSIC_XED_IFORM_AND_LOCK_MEMv_GPRv INTRINSIC_XED_IFORM_AND_MEMb_IMMb_80r4 u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_AND_GPR8_IMMb_80r4 INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_AND_MEMv_IMMz int rw v + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_AND_GPRv_IMMz INVALID rw GPRv_B + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_AND_MEMb_IMMb_82r4 u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_AND_GPR8_IMMb_82r4 INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_AND_MEMv_IMMb int rw v + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_AND_GPRv_IMMb INVALID rw GPRv_B + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_AND_MEMb_GPR8 @@ -1282,27 +1142,32 @@ INTRINSIC_XED_IFORM_AND_GPRv_MEMv INVALID w rFLAGS INTRINSIC_XED_IFORM_AND_AL_IMMb - INVALID rw XED_REG_AL + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_AND_OrAX_IMMz INVALID rw OrAX + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5 u8 rw b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_IMMz int rw v + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5 u8 rw b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_IMMb int rw v + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_GPR8 @@ -1317,34 +1182,42 @@ INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_GPRv INTRINSIC_XED_IFORM_SUB_MEMb_IMMb_80r5 u8 rw b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SUB_GPR8_IMMb_80r5 INVALID rw GPR8_B + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SUB_MEMv_IMMz int rw v + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_SUB_GPRv_IMMz INVALID rw GPRv_B + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_SUB_MEMb_IMMb_82r5 u8 rw b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SUB_GPR8_IMMb_82r5 INVALID rw GPR8_B + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SUB_MEMv_IMMb int rw v + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SUB_GPRv_IMMb INVALID rw GPRv_B + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SUB_MEMb_GPR8 @@ -1388,27 +1261,32 @@ INTRINSIC_XED_IFORM_SUB_GPRv_MEMv INVALID w rFLAGS INTRINSIC_XED_IFORM_SUB_AL_IMMb - INVALID rw XED_REG_AL + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SUB_OrAX_IMMz INVALID rw OrAX + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6 u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_IMMz int rw v + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6 u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_IMMb int rw v + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_GPR8 @@ -1423,34 +1301,42 @@ INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_GPRv INTRINSIC_XED_IFORM_XOR_MEMb_IMMb_80r6 u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_XOR_GPR8_IMMb_80r6 INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_XOR_MEMv_IMMz int rw v + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_XOR_GPRv_IMMz INVALID rw GPRv_B + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_XOR_MEMb_IMMb_82r6 u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_XOR_GPR8_IMMb_82r6 INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_XOR_MEMv_IMMb int rw v + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_XOR_GPRv_IMMb INVALID rw GPRv_B + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_XOR_MEMb_GPR8 @@ -1494,43 +1380,52 @@ INTRINSIC_XED_IFORM_XOR_GPRv_MEMv INVALID w rFLAGS INTRINSIC_XED_IFORM_XOR_AL_IMMb - INVALID rw XED_REG_AL + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_XOR_OrAX_IMMz INVALID rw OrAX + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_CMP_MEMb_IMMb_80r7 u8 r b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_CMP_GPR8_IMMb_80r7 INVALID r GPR8_B + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_CMP_MEMv_IMMz int r v + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_CMP_GPRv_IMMz INVALID r GPRv_B + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_CMP_MEMb_IMMb_82r7 u8 r b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_CMP_GPR8_IMMb_82r7 INVALID r GPR8_B + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_CMP_MEMv_IMMb int r v + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_CMP_GPRv_IMMb INVALID r GPRv_B + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_CMP_MEMb_GPR8 @@ -1574,499 +1469,551 @@ INTRINSIC_XED_IFORM_CMP_GPRv_GPRv_3B INVALID w rFLAGS INTRINSIC_XED_IFORM_CMP_AL_IMMb - INVALID r XED_REG_AL + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_CMP_OrAX_IMMz INVALID r OrAX + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_POP_MEMv int w v + int rw spw int r spw - int r spw + INVALID rw SrSP + INVALID r FINAL_SSEG1 INTRINSIC_XED_IFORM_POP_GPRv_8F INVALID w GPRv_B + int rw spw int r spw - int r spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_POP_ES - INVALID w XED_REG_ES - int r spw + int rw spw int r spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_POP_SS - INVALID w XED_REG_SS - int r spw + int rw spw int r spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_POP_DS - INVALID w XED_REG_DS - int r spw + int rw spw int r spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_POP_GPRv_58 INVALID w GPRv_SB + int rw spw int r spw - int r spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_POP_FS - INVALID w XED_REG_FS - int r spw + int rw spw int r spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_POP_GS - INVALID w XED_REG_GS - int r spw + int rw spw int r spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_ROL_MEMb_IMMb u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROL_GPR8_IMMb INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROL_MEMv_IMMb int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROL_GPRv_IMMb INVALID rw GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROL_MEMb_ONE u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROL_GPR8_ONE INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROL_MEMv_ONE int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROL_GPRv_ONE INVALID rw GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROL_MEMb_CL u8 rw b - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_ROL_GPR8_CL INVALID rw GPR8_B - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_ROL_MEMv_CL int rw v - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_ROL_GPRv_CL INVALID rw GPRv_B - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_ROR_MEMb_IMMb u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROR_GPR8_IMMb INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROR_GPRv_IMMb INVALID rw GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROR_MEMv_IMMb int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROR_MEMb_ONE u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROR_GPR8_ONE INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROR_MEMv_ONE int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROR_GPRv_ONE INVALID rw GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_ROR_MEMb_CL u8 rw b - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_ROR_GPR8_CL INVALID rw GPR8_B - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_ROR_MEMv_CL int rw v - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_ROR_GPRv_CL INVALID rw GPRv_B - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_RCL_MEMb_IMMb u8 rw b + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCL_GPR8_IMMb INVALID rw GPR8_B + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCL_MEMv_IMMb int rw v + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCL_GPRv_IMMb INVALID rw GPRv_B + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCL_MEMb_ONE u8 rw b + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCL_GPR8_ONE INVALID rw GPR8_B + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCL_MEMv_ONE int rw v + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCL_GPRv_ONE INVALID rw GPRv_B + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCL_MEMb_CL u8 rw b - INVALID r XED_REG_CL INVALID rcw rFLAGS INTRINSIC_XED_IFORM_RCL_GPR8_CL INVALID rw GPR8_B - INVALID r XED_REG_CL INVALID rcw rFLAGS INTRINSIC_XED_IFORM_RCL_MEMv_CL int rw v - INVALID r XED_REG_CL INVALID rcw rFLAGS INTRINSIC_XED_IFORM_RCL_GPRv_CL INVALID rw GPRv_B - INVALID r XED_REG_CL INVALID rcw rFLAGS INTRINSIC_XED_IFORM_RCR_MEMb_IMMb u8 rw b + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCR_GPR8_IMMb INVALID rw GPR8_B + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCR_MEMv_IMMb int rw v + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCR_GPRv_IMMb INVALID rw GPRv_B + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCR_MEMb_ONE u8 rw b + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCR_GPR8_ONE INVALID rw GPR8_B + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCR_MEMv_ONE int rw v + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCR_GPRv_ONE INVALID rw GPRv_B + u8 r b INVALID rw rFLAGS INTRINSIC_XED_IFORM_RCR_MEMb_CL u8 rw b - INVALID r XED_REG_CL INVALID rcw rFLAGS INTRINSIC_XED_IFORM_RCR_GPR8_CL INVALID rw GPR8_B - INVALID r XED_REG_CL INVALID rcw rFLAGS INTRINSIC_XED_IFORM_RCR_MEMv_CL int rw v - INVALID r XED_REG_CL INVALID rcw rFLAGS INTRINSIC_XED_IFORM_RCR_GPRv_CL INVALID rw GPRv_B - INVALID r XED_REG_CL INVALID rcw rFLAGS INTRINSIC_XED_IFORM_SHL_MEMb_IMMb_C0r4 u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHL_GPR8_IMMb_C0r4 INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHL_MEMb_IMMb_C0r6 u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHL_GPR8_IMMb_C0r6 INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHL_MEMv_IMMb_C1r4 int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHL_GPRv_IMMb_C1r4 INVALID rw GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHL_MEMv_IMMb_C1r6 int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHL_GPRv_IMMb_C1r6 INVALID rw GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHL_MEMb_ONE_D0r4 u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHL_GPR8_ONE_D0r4 INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHL_MEMb_ONE_D0r6 u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHL_GPR8_ONE_D0r6 INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHL_MEMv_ONE_D1r6 int rw v - INVALID w rFLAGS - -INTRINSIC_XED_IFORM_SHL_GPRv_ONE_D1r6 - INVALID rw GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHL_MEMv_ONE_D1r4 int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHL_GPRv_ONE_D1r4 INVALID rw GPRv_B + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_ONE_D1r6 + INVALID rw GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHL_MEMb_CL_D2r4 u8 rw b - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SHL_GPR8_CL_D2r4 INVALID rw GPR8_B - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SHL_MEMb_CL_D2r6 u8 rw b - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SHL_GPR8_CL_D2r6 INVALID rw GPR8_B - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SHL_MEMv_CL_D3r4 int rw v - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SHL_GPRv_CL_D3r4 INVALID rw GPRv_B - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SHL_MEMv_CL_D3r6 int rw v - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SHL_GPRv_CL_D3r6 INVALID rw GPRv_B - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SHR_MEMb_IMMb u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHR_GPR8_IMMb INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHR_MEMv_IMMb int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHR_GPRv_IMMb INVALID rw GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHR_MEMb_ONE u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHR_GPR8_ONE INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHR_MEMv_ONE int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHR_GPRv_ONE INVALID rw GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHR_MEMb_CL u8 rw b - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SHR_GPR8_CL INVALID rw GPR8_B - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SHR_MEMv_CL int rw v - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SHR_GPRv_CL INVALID rw GPRv_B - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SAR_MEMb_IMMb u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SAR_GPR8_IMMb INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SAR_MEMv_IMMb int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SAR_GPRv_IMMb INVALID rw GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SAR_MEMb_ONE u8 rw b + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SAR_GPR8_ONE INVALID rw GPR8_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SAR_MEMv_ONE int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SAR_GPRv_ONE INVALID rw GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SAR_MEMb_CL u8 rw b - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SAR_GPR8_CL INVALID rw GPR8_B - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SAR_MEMv_CL int rw v - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SAR_GPRv_CL INVALID rw GPRv_B - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_TEST_MEMb_IMMb_F6r0 u8 r b - INVALID w rFLAGS - -INTRINSIC_XED_IFORM_TEST_MEMb_IMMb_F6r1 - u8 r b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_TEST_GPR8_IMMb_F6r0 INVALID r GPR8_B + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_MEMb_IMMb_F6r1 + u8 r b + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_TEST_GPR8_IMMb_F6r1 INVALID r GPR8_B + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_TEST_MEMv_IMMz_F7r0 int r v - INVALID w rFLAGS - -INTRINSIC_XED_IFORM_TEST_MEMv_IMMz_F7r1 - int r v + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_TEST_GPRv_IMMz_F7r0 INVALID r GPRv_B + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_MEMv_IMMz_F7r1 + int r v + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_TEST_GPRv_IMMz_F7r1 INVALID r GPRv_B + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_TEST_MEMb_GPR8 @@ -2090,11 +2037,12 @@ INTRINSIC_XED_IFORM_TEST_GPRv_GPRv INVALID w rFLAGS INTRINSIC_XED_IFORM_TEST_AL_IMMb - INVALID r XED_REG_AL + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_TEST_OrAX_IMMz INVALID r OrAX + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_NOT_LOCK_MEMb @@ -2141,14 +2089,10 @@ INTRINSIC_XED_IFORM_NEG_GPRv INTRINSIC_XED_IFORM_MUL_MEMb u8 r b - INVALID r XED_REG_AL - INVALID w XED_REG_AX INVALID w rFLAGS INTRINSIC_XED_IFORM_MUL_GPR8 INVALID r GPR8_B - INVALID r XED_REG_AL - INVALID w XED_REG_AX INVALID w rFLAGS INTRINSIC_XED_IFORM_MUL_MEMv @@ -2165,14 +2109,10 @@ INTRINSIC_XED_IFORM_MUL_GPRv INTRINSIC_XED_IFORM_IMUL_MEMb u8 r b - INVALID r XED_REG_AL - INVALID w XED_REG_AX INVALID w rFLAGS INTRINSIC_XED_IFORM_IMUL_GPR8 INVALID r GPR8_B - INVALID r XED_REG_AL - INVALID w XED_REG_AX INVALID w rFLAGS INTRINSIC_XED_IFORM_IMUL_MEMv @@ -2190,21 +2130,25 @@ INTRINSIC_XED_IFORM_IMUL_GPRv INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv_IMMz INVALID w GPRv_R int r v + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_IMMz INVALID w GPRv_R INVALID r GPRv_B + int r z INVALID w rFLAGS INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv_IMMb INVALID w GPRv_R int r v + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_IMMb INVALID w GPRv_R INVALID r GPRv_B + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv @@ -2219,12 +2163,10 @@ INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv INTRINSIC_XED_IFORM_DIV_MEMb u8 r b - INVALID rw XED_REG_AX INVALID w rFLAGS INTRINSIC_XED_IFORM_DIV_GPR8 INVALID r GPR8_B - INVALID rw XED_REG_AX INVALID w rFLAGS INTRINSIC_XED_IFORM_DIV_MEMv @@ -2241,12 +2183,10 @@ INTRINSIC_XED_IFORM_DIV_GPRv INTRINSIC_XED_IFORM_IDIV_MEMb u8 r b - INVALID rw XED_REG_AX INVALID w rFLAGS INTRINSIC_XED_IFORM_IDIV_GPR8 INVALID r GPR8_B - INVALID rw XED_REG_AX INVALID w rFLAGS INTRINSIC_XED_IFORM_IDIV_MEMv @@ -2319,25 +2259,33 @@ INTRINSIC_XED_IFORM_DEC_GPRv_48 INTRINSIC_XED_IFORM_CALL_NEAR_MEMv int r v - int w spw + int rw spw INVALID rw rIP int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG1 INTRINSIC_XED_IFORM_CALL_NEAR_GPRv INVALID r GPRv_B - int w spw + int rw spw INVALID rw rIP int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_CALL_NEAR_RELBRz + int r z + int rw spw int w spw - INVALID rw XED_REG_EIP - int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_CALL_NEAR_RELBRd + i32 r d + int rw spw int w spw - INVALID rw XED_REG_RIP - int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_JMP_MEMv int r v @@ -2348,105 +2296,116 @@ INTRINSIC_XED_IFORM_JMP_GPRv INVALID w rIP INTRINSIC_XED_IFORM_JMP_RELBRz - INVALID rw XED_REG_EIP + int r z INTRINSIC_XED_IFORM_JMP_RELBRd - INVALID rw XED_REG_RIP + i32 r d INTRINSIC_XED_IFORM_JMP_RELBRb - INVALID rw XED_REG_EIP + i8 r b INTRINSIC_XED_IFORM_JMP_FAR_MEMp2 struct r p2 INVALID w rIP INTRINSIC_XED_IFORM_JMP_FAR_PTRp_IMMw - INVALID w XED_REG_EIP + struct r p + i16 r w INTRINSIC_XED_IFORM_PUSH_MEMv int r v + int rw spw int w spw - int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG1 INTRINSIC_XED_IFORM_PUSH_GPRv_FFr6 INVALID r GPRv_B + int rw spw int w spw - int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_PUSH_ES - INVALID r XED_REG_ES - int w spw + int rw spw int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_PUSH_CS - INVALID r XED_REG_CS - int w spw + int rw spw int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_PUSH_SS - INVALID r XED_REG_SS - int w spw + int rw spw int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_PUSH_DS - INVALID r XED_REG_DS - int w spw + int rw spw int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_PUSH_GPRv_50 INVALID r GPRv_SB + int rw spw int w spw - int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_PUSH_IMMz + int r z + int rw spw int w spw - int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_PUSH_IMMb + i8 r b + int rw spw int w spw - int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_PUSH_FS - INVALID r XED_REG_FS - int w spw + int rw spw int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_PUSH_GS - INVALID r XED_REG_GS - int w spw + int rw spw int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_SLDT_MEMw i16 w w - INVALID r XED_REG_LDTR INTRINSIC_XED_IFORM_SLDT_GPRv INVALID w GPRv_B - INVALID r XED_REG_LDTR INTRINSIC_XED_IFORM_STR_MEMw i16 w w - INVALID r XED_REG_TR INTRINSIC_XED_IFORM_STR_GPRv INVALID w GPRv_B - INVALID r XED_REG_TR INTRINSIC_XED_IFORM_LLDT_MEMw i16 r w - INVALID w XED_REG_LDTR INTRINSIC_XED_IFORM_LLDT_GPR16 INVALID r GPR16_B - INVALID w XED_REG_LDTR INTRINSIC_XED_IFORM_LTR_MEMw i16 r w - INVALID w XED_REG_TR INTRINSIC_XED_IFORM_LTR_GPR16 INVALID r GPR16_B - INVALID w XED_REG_TR INTRINSIC_XED_IFORM_VERR_MEMw i16 r w @@ -2466,34 +2425,30 @@ INTRINSIC_XED_IFORM_VERW_GPR16 INTRINSIC_XED_IFORM_LGDT_MEMs64 struct r s64 - INVALID w XED_REG_GDTR INTRINSIC_XED_IFORM_LGDT_MEMs struct r s - INVALID w XED_REG_GDTR INTRINSIC_XED_IFORM_SMSW_MEMw i16 w w - INVALID r XED_REG_CR0 INTRINSIC_XED_IFORM_SMSW_GPRv INVALID w GPRv_B - INVALID r XED_REG_CR0 INTRINSIC_XED_IFORM_LMSW_MEMw i16 r w - INVALID w XED_REG_CR0 INTRINSIC_XED_IFORM_LMSW_GPR16 INVALID r GPR16_B - INVALID w XED_REG_CR0 INTRINSIC_XED_IFORM_BT_MEMv_IMMb int r v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_BT_GPRv_IMMb INVALID r GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_BT_MEMv_GPRv @@ -2508,6 +2463,7 @@ INTRINSIC_XED_IFORM_BT_GPRv_GPRv INTRINSIC_XED_IFORM_BTS_LOCK_MEMv_IMMb int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_BTS_LOCK_MEMv_GPRv @@ -2517,10 +2473,12 @@ INTRINSIC_XED_IFORM_BTS_LOCK_MEMv_GPRv INTRINSIC_XED_IFORM_BTS_MEMv_IMMb int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_BTS_GPRv_IMMb INVALID rw GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_BTS_MEMv_GPRv @@ -2535,6 +2493,7 @@ INTRINSIC_XED_IFORM_BTS_GPRv_GPRv INTRINSIC_XED_IFORM_BTR_LOCK_MEMv_IMMb int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_BTR_LOCK_MEMv_GPRv @@ -2544,10 +2503,12 @@ INTRINSIC_XED_IFORM_BTR_LOCK_MEMv_GPRv INTRINSIC_XED_IFORM_BTR_MEMv_IMMb int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_BTR_GPRv_IMMb INVALID rw GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_BTR_MEMv_GPRv @@ -2562,6 +2523,7 @@ INTRINSIC_XED_IFORM_BTR_GPRv_GPRv INTRINSIC_XED_IFORM_BTC_LOCK_MEMv_IMMb int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_BTC_LOCK_MEMv_GPRv @@ -2571,10 +2533,12 @@ INTRINSIC_XED_IFORM_BTC_LOCK_MEMv_GPRv INTRINSIC_XED_IFORM_BTC_MEMv_IMMb int rw v + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_BTC_GPRv_IMMb INVALID rw GPRv_B + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_BTC_MEMv_GPRv @@ -2605,47 +2569,35 @@ INTRINSIC_XED_IFORM_VMXON_MEMq INTRINSIC_XED_IFORM_CMPXCHG8B_LOCK_MEMq i64 rcw q - INVALID rcw XED_REG_EDX - INVALID rcw XED_REG_EAX - INVALID r XED_REG_ECX - INVALID r XED_REG_EBX INVALID w rFLAGS INTRINSIC_XED_IFORM_CMPXCHG8B_MEMq i64 rcw q - INVALID rcw XED_REG_EDX - INVALID rcw XED_REG_EAX - INVALID r XED_REG_ECX - INVALID r XED_REG_EBX INVALID w rFLAGS INTRINSIC_XED_IFORM_CMPXCHG16B_LOCK_MEMdq i32 rcw dq - INVALID rcw XED_REG_RDX - INVALID rcw XED_REG_RAX - INVALID r XED_REG_RCX - INVALID r XED_REG_RBX INVALID w rFLAGS INTRINSIC_XED_IFORM_CMPXCHG16B_MEMdq i32 rcw dq - INVALID rcw XED_REG_RDX - INVALID rcw XED_REG_RAX - INVALID r XED_REG_RCX - INVALID r XED_REG_RBX INVALID w rFLAGS INTRINSIC_XED_IFORM_MOV_GPR8_IMMb_C6r0 INVALID w GPR8_B + u8 r b INTRINSIC_XED_IFORM_MOV_MEMb_IMMb u8 w b + u8 r b INTRINSIC_XED_IFORM_MOV_GPRv_IMMz INVALID w GPRv_B + int r z INTRINSIC_XED_IFORM_MOV_MEMv_IMMz int w v + int r z INTRINSIC_XED_IFORM_MOV_GPR8_GPR8_88 INVALID w GPR8_B @@ -2696,32 +2648,38 @@ INTRINSIC_XED_IFORM_MOV_SEG_GPR16 INVALID r GPR16_B INTRINSIC_XED_IFORM_MOV_AL_MEMb - INVALID w XED_REG_AL u8 r b + INVALID r FINAL_DSEG INTRINSIC_XED_IFORM_MOV_OrAX_MEMv INVALID w OrAX int r v + INVALID r FINAL_DSEG INTRINSIC_XED_IFORM_MOV_MEMb_AL u8 w b - INVALID r XED_REG_AL + INVALID r FINAL_DSEG INTRINSIC_XED_IFORM_MOV_MEMv_OrAX int w v INVALID r OrAX + INVALID r FINAL_DSEG INTRINSIC_XED_IFORM_MOV_GPR8_IMMb_B0 INVALID w GPR8_SB + u8 r b INTRINSIC_XED_IFORM_MOV_GPRv_IMMv INVALID w GPRv_SB + int r v INTRINSIC_XED_IFORM_PSRLW_MMXq_IMMb u16 rw q + u8 r b INTRINSIC_XED_IFORM_PSRLW_XMMdq_IMMb u16 rw dq + u8 r b INTRINSIC_XED_IFORM_PSRLW_MMXq_MEMq u16 rw q @@ -2741,9 +2699,11 @@ INTRINSIC_XED_IFORM_PSRLW_XMMdq_XMMdq INTRINSIC_XED_IFORM_PSRAW_MMXq_IMMb i16 rw q + u8 r b INTRINSIC_XED_IFORM_PSRAW_XMMdq_IMMb i16 rw dq + u8 r b INTRINSIC_XED_IFORM_PSRAW_MMXq_MEMq i16 rw q @@ -2763,9 +2723,11 @@ INTRINSIC_XED_IFORM_PSRAW_XMMdq_XMMdq INTRINSIC_XED_IFORM_PSLLW_MMXq_IMMb u16 rw q + u8 r b INTRINSIC_XED_IFORM_PSLLW_XMMdq_IMMb u16 rw dq + u8 r b INTRINSIC_XED_IFORM_PSLLW_MMXq_MEMq u16 rw q @@ -2785,9 +2747,11 @@ INTRINSIC_XED_IFORM_PSLLW_XMMdq_XMMdq INTRINSIC_XED_IFORM_PSRLD_MMXq_IMMb u32 rw q + u8 r b INTRINSIC_XED_IFORM_PSRLD_XMMdq_IMMb u32 rw dq + u8 r b INTRINSIC_XED_IFORM_PSRLD_MMXq_MEMq u32 rw q @@ -2807,9 +2771,11 @@ INTRINSIC_XED_IFORM_PSRLD_XMMdq_XMMdq INTRINSIC_XED_IFORM_PSRAD_MMXq_IMMb i32 rw q + u8 r b INTRINSIC_XED_IFORM_PSRAD_XMMdq_IMMb i32 rw dq + u8 r b INTRINSIC_XED_IFORM_PSRAD_MMXq_MEMq i32 rw q @@ -2829,9 +2795,11 @@ INTRINSIC_XED_IFORM_PSRAD_XMMdq_XMMdq INTRINSIC_XED_IFORM_PSLLD_MMXq_IMMb u32 rw q + u8 r b INTRINSIC_XED_IFORM_PSLLD_XMMdq_IMMb u32 rw dq + u8 r b INTRINSIC_XED_IFORM_PSLLD_MMXq_MEMq u32 rw q @@ -2851,9 +2819,11 @@ INTRINSIC_XED_IFORM_PSLLD_XMMdq_XMMdq INTRINSIC_XED_IFORM_PSRLQ_MMXq_IMMb u64 rw q + u8 r b INTRINSIC_XED_IFORM_PSRLQ_XMMdq_IMMb u64 rw dq + u8 r b INTRINSIC_XED_IFORM_PSRLQ_MMXq_MEMq u64 rw q @@ -2873,9 +2843,11 @@ INTRINSIC_XED_IFORM_PSRLQ_XMMdq_XMMdq INTRINSIC_XED_IFORM_PSLLQ_MMXq_IMMb u64 rw q + u8 r b INTRINSIC_XED_IFORM_PSLLQ_XMMdq_IMMb u64 rw dq + u8 r b INTRINSIC_XED_IFORM_PSLLQ_MMXq_MEMq u64 rw q @@ -2895,33 +2867,29 @@ INTRINSIC_XED_IFORM_PSLLQ_XMMdq_XMMdq INTRINSIC_XED_IFORM_PSRLDQ_XMMdq_IMMb u128 rw dq + u8 r b INTRINSIC_XED_IFORM_PSLLDQ_XMMdq_IMMb u128 rw dq + u8 r b INTRINSIC_XED_IFORM_FXSAVE_MEMmfpxenv struct w mfpxenv - INVALID r XED_REG_X87CONTROL INTRINSIC_XED_IFORM_FXRSTOR_MEMmfpxenv struct r mfpxenv - INVALID w XED_REG_X87CONTROL INTRINSIC_XED_IFORM_FXSAVE64_MEMmfpxenv struct w mfpxenv - INVALID r XED_REG_X87CONTROL INTRINSIC_XED_IFORM_FXRSTOR64_MEMmfpxenv struct r mfpxenv - INVALID w XED_REG_X87CONTROL INTRINSIC_XED_IFORM_LDMXCSR_MEMd i32 r d - INVALID w XED_REG_MXCSR INTRINSIC_XED_IFORM_STMXCSR_MEMd i32 w d - INVALID r XED_REG_MXCSR INTRINSIC_XED_IFORM_PREFETCHNTA_MEMmprefetch i64 r mprefetch @@ -2947,9 +2915,6 @@ INTRINSIC_XED_IFORM_NOP_GPRv_0F18r2 INTRINSIC_XED_IFORM_NOP_GPRv_0F18r3 INVALID r GPRv_B -INTRINSIC_XED_IFORM_NOP_MEMv_0F18r4 - int r v - INTRINSIC_XED_IFORM_NOP_GPRv_0F18r4 INVALID r GPRv_B @@ -2959,18 +2924,15 @@ INTRINSIC_XED_IFORM_NOP_MEMv_0F18r5 INTRINSIC_XED_IFORM_NOP_GPRv_0F18r5 INVALID r GPRv_B -INTRINSIC_XED_IFORM_NOP_MEMv_0F18r6 - int r v - INTRINSIC_XED_IFORM_NOP_GPRv_0F18r6 INVALID r GPRv_B -INTRINSIC_XED_IFORM_NOP_MEMv_0F18r7 - int r v - INTRINSIC_XED_IFORM_NOP_GPRv_0F18r7 INVALID r GPRv_B +INTRINSIC_XED_IFORM_NOP_MEMv_0F18r4 + int r v + INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F19 int r v INVALID r GPRv_R @@ -2987,13 +2949,11 @@ INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1D INVALID r GPRv_B INVALID r GPRv_R -INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1F +INTRINSIC_XED_IFORM_NOP_MEMv_0F1F int r v - INVALID r GPRv_R -INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1F +INTRINSIC_XED_IFORM_NOP_GPRv_0F1F INVALID r GPRv_B - INVALID r GPRv_R INTRINSIC_XED_IFORM_NOP_90 @@ -3047,36 +3007,25 @@ INTRINSIC_XED_IFORM_VMXOFF INTRINSIC_XED_IFORM_SGDT_MEMs64 struct w s64 - INVALID r XED_REG_GDTR INTRINSIC_XED_IFORM_SGDT_MEMs struct w s - INVALID r XED_REG_GDTR INTRINSIC_XED_IFORM_LIDT_MEMs64 struct r s64 - INVALID w XED_REG_IDTR INTRINSIC_XED_IFORM_LIDT_MEMs struct r s - INVALID w XED_REG_IDTR INTRINSIC_XED_IFORM_MONITOR - INVALID r XED_REG_EAX - INVALID r XED_REG_ECX - INVALID r XED_REG_EDX INTRINSIC_XED_IFORM_MWAIT - INVALID r XED_REG_EAX - INVALID r XED_REG_ECX INTRINSIC_XED_IFORM_SIDT_MEMs struct w s - INVALID r XED_REG_IDTR INTRINSIC_XED_IFORM_SIDT_MEMs64 struct w s64 - INVALID r XED_REG_IDTR INTRINSIC_XED_IFORM_INVLPG_MEMb u8 r b @@ -3084,11 +3033,6 @@ INTRINSIC_XED_IFORM_INVLPG_MEMb INTRINSIC_XED_IFORM_SWAPGS INTRINSIC_XED_IFORM_RDTSCP - INVALID w XED_REG_EAX - INVALID w XED_REG_EDX - INVALID w XED_REG_ECX - INVALID r XED_REG_TSC - INVALID r XED_REG_TSCAUX INTRINSIC_XED_IFORM_SFENCE @@ -3100,23 +3044,23 @@ INTRINSIC_XED_IFORM_LFENCE INTRINSIC_XED_IFORM_MFENCE INTRINSIC_XED_IFORM_MOVHLPS_XMMq_XMMq - f32 w q + f32 rw q f32 r q INTRINSIC_XED_IFORM_MOVLPS_XMMq_MEMq - f32 w q + f32 rw q f32 r q -INTRINSIC_XED_IFORM_MOVLPS_MEMq_XMMps +INTRINSIC_XED_IFORM_MOVLPS_MEMq_XMMq f32 w q - f32 r ps + f32 r q INTRINSIC_XED_IFORM_MOVLHPS_XMMq_XMMq - f32 w q + f32 rw q f32 r q INTRINSIC_XED_IFORM_MOVHPS_XMMq_MEMq - f32 w q + f32 rw q f32 r q INTRINSIC_XED_IFORM_MOVHPS_MEMq_XMMps @@ -3124,68 +3068,40 @@ INTRINSIC_XED_IFORM_MOVHPS_MEMq_XMMps f32 r ps INTRINSIC_XED_IFORM_DAA - INVALID rw XED_REG_AL INVALID rw rFLAGS INTRINSIC_XED_IFORM_DAS - INVALID rw XED_REG_AL INVALID rw rFLAGS INTRINSIC_XED_IFORM_AAA - INVALID rw XED_REG_AL - INVALID rw XED_REG_AH INVALID rw rFLAGS INTRINSIC_XED_IFORM_AAS - INVALID rw XED_REG_AL - INVALID rw XED_REG_AH INVALID rw rFLAGS INTRINSIC_XED_IFORM_PUSHA + int rw spw8 int w spw8 - INVALID r XED_REG_AX - INVALID r XED_REG_CX - INVALID r XED_REG_DX - INVALID r XED_REG_BX - INVALID r XED_REG_SP - INVALID r XED_REG_BP - INVALID r XED_REG_SI - INVALID r XED_REG_DI - int w spw8 + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_PUSHAD + int rw spw8 int w spw8 - INVALID r XED_REG_EAX - INVALID r XED_REG_ECX - INVALID r XED_REG_EDX - INVALID r XED_REG_EBX - INVALID r XED_REG_ESP - INVALID r XED_REG_EBP - INVALID r XED_REG_ESI - INVALID r XED_REG_EDI - int w spw8 + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_POPA + int rw spw8 int r spw8 - INVALID w XED_REG_AX - INVALID w XED_REG_CX - INVALID w XED_REG_DX - INVALID w XED_REG_BX - INVALID w XED_REG_BP - INVALID w XED_REG_SI - INVALID w XED_REG_DI - int r spw8 + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_POPAD + int rw spw8 int r spw8 - INVALID w XED_REG_EAX - INVALID w XED_REG_ECX - INVALID w XED_REG_EDX - INVALID w XED_REG_EBX - INVALID w XED_REG_EBP - INVALID w XED_REG_ESI - INVALID w XED_REG_EDI - int r spw8 + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_BOUND_GPRv_MEMa16 INVALID r GPRv_R @@ -3215,260 +3131,272 @@ INTRINSIC_XED_IFORM_MOVSXD_GPRv_GPRz INTRINSIC_XED_IFORM_REP_INSB u8 cw b - INVALID r XED_REG_DX + INVALID rcw ArDI + INVALID r FINAL_ESEG INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_INSB u8 w b - INVALID r XED_REG_DX + INVALID rw ArDI + INVALID r FINAL_ESEG INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_INSW i16 cw w - INVALID r XED_REG_DX + INVALID rcw ArDI + INVALID r FINAL_ESEG INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_INSW i16 w w - INVALID r XED_REG_DX + INVALID rw ArDI + INVALID r FINAL_ESEG INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_INSD i32 cw d - INVALID r XED_REG_DX + INVALID rcw ArDI + INVALID r FINAL_ESEG INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_INSD i32 w d - INVALID r XED_REG_DX + INVALID rw ArDI + INVALID r FINAL_ESEG INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_OUTSB - INVALID r XED_REG_DX u8 cr b + INVALID rcw ArSI + INVALID r FINAL_DSEG INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_OUTSB - INVALID r XED_REG_DX u8 r b + INVALID rw ArSI + INVALID r FINAL_DSEG INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_OUTSW - INVALID r XED_REG_DX i16 cr w + INVALID rcw ArSI + INVALID r FINAL_DSEG INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_OUTSW - INVALID r XED_REG_DX i16 r w + INVALID rw ArSI + INVALID r FINAL_DSEG INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_OUTSD - INVALID r XED_REG_DX i32 cr d + INVALID rcw ArSI + INVALID r FINAL_DSEG INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_OUTSD - INVALID r XED_REG_DX i32 r d + INVALID rw ArSI + INVALID r FINAL_DSEG INVALID r rFLAGS INTRINSIC_XED_IFORM_JO_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JO_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_JO_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JNO_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JNO_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JNO_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_JB_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JB_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JB_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_JNB_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JNB_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JNB_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_JZ_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JZ_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JZ_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_JNZ_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JNZ_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JNZ_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_JBE_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JBE_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JBE_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_JNBE_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JNBE_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JNBE_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_JS_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JS_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JS_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_JNS_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JNS_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JNS_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_JP_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JP_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JP_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_JNP_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JNP_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JNP_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_JL_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JL_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JL_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_JNL_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JNL_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JNL_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_JLE_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JLE_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JLE_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_JNLE_RELBRb - INVALID rw XED_REG_RIP + i8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_JNLE_RELBRz - INVALID rw XED_REG_EIP + int r z INVALID r rFLAGS INTRINSIC_XED_IFORM_JNLE_RELBRd - INVALID rw XED_REG_RIP + i32 r d INVALID r rFLAGS INTRINSIC_XED_IFORM_XCHG_MEMb_GPR8 @@ -3497,495 +3425,619 @@ INTRINSIC_XED_IFORM_LEA_GPRv_AGEN INTRINSIC_XED_IFORM_PAUSE INTRINSIC_XED_IFORM_CBW - INVALID w XED_REG_AX - INVALID r XED_REG_AL INTRINSIC_XED_IFORM_CDQE - INVALID w XED_REG_RAX - INVALID r XED_REG_EAX INTRINSIC_XED_IFORM_CWDE - INVALID w XED_REG_EAX - INVALID r XED_REG_AX INTRINSIC_XED_IFORM_CWD - INVALID w XED_REG_DX - INVALID r XED_REG_AX INTRINSIC_XED_IFORM_CQO - INVALID w XED_REG_RDX - INVALID r XED_REG_RAX INTRINSIC_XED_IFORM_CDQ - INVALID w XED_REG_EDX - INVALID r XED_REG_EAX INTRINSIC_XED_IFORM_CALL_FAR_MEMp2 struct r p2 - int w spw2 + int rw spw2 INVALID w rIP int w spw2 + INVALID rw SrSP + INVALID r FINAL_SSEG1 INTRINSIC_XED_IFORM_CALL_FAR_PTRp_IMMw + struct r p + i16 r w + int rw spw2 int w spw2 - INVALID w XED_REG_EIP - int w spw2 + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_FWAIT INTRINSIC_XED_IFORM_PUSHF + i16 rw w + u16 r w i16 w w - i16 w w - INVALID r rFLAGS + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_PUSHFD + i32 rw d + u32 r d i32 w d - i32 w d - INVALID r rFLAGS + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_PUSHFQ + i64 rw q + u64 r q i64 w q - i64 w q - INVALID r rFLAGS + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_POPF + i16 rw w + u16 rw w i16 r w - i16 r w - INVALID rw rFLAGS + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_POPFD + i32 rw d + u32 rw d i32 r d - i32 r d - INVALID rw rFLAGS + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_POPFQ + i64 rw q + u64 rw q i64 r q - i64 r q - INVALID rw rFLAGS + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_SAHF - INVALID r XED_REG_AH INVALID w rFLAGS INTRINSIC_XED_IFORM_LAHF - INVALID w XED_REG_AH INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_MOVSB u8 cw b + INVALID rcw ArDI + INVALID r FINAL_ESEG u8 cr b + INVALID rcw ArSI + INVALID r FINAL_DSEG1 INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_MOVSB u8 w b + INVALID rw ArDI + INVALID r FINAL_ESEG u8 r b + INVALID rw ArSI + INVALID r FINAL_DSEG1 INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_MOVSW i16 cw w + INVALID rcw ArDI + INVALID r FINAL_ESEG i16 cr w + INVALID rcw ArSI + INVALID r FINAL_DSEG1 INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_MOVSW i16 w w + INVALID rw ArDI + INVALID r FINAL_ESEG i16 r w + INVALID rw ArSI + INVALID r FINAL_DSEG1 INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_MOVSD i32 cw d + INVALID rcw ArDI + INVALID r FINAL_ESEG i32 cr d + INVALID rcw ArSI + INVALID r FINAL_DSEG1 INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_MOVSD i32 w d + INVALID rw ArDI + INVALID r FINAL_ESEG i32 r d + INVALID rw ArSI + INVALID r FINAL_DSEG1 INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_MOVSQ i64 cw q + INVALID rcw ArDI + INVALID r FINAL_ESEG i64 cr q + INVALID rcw ArSI + INVALID r FINAL_DSEG1 INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_MOVSQ i64 w q + INVALID rw ArDI + INVALID r FINAL_ESEG i64 r q + INVALID rw ArSI + INVALID r FINAL_DSEG1 INVALID r rFLAGS INTRINSIC_XED_IFORM_REPE_CMPSB u8 cr b + INVALID rcw ArSI + INVALID r FINAL_DSEG u8 cr b + INVALID rcw ArDI + INVALID r FINAL_ESEG1 INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_REPNE_CMPSB u8 cr b + INVALID rcw ArSI + INVALID r FINAL_DSEG u8 cr b + INVALID rcw ArDI + INVALID r FINAL_ESEG1 INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_CMPSB u8 r b + INVALID rw ArSI + INVALID r FINAL_DSEG u8 r b + INVALID rw ArDI + INVALID r FINAL_ESEG1 INVALID rw rFLAGS INTRINSIC_XED_IFORM_REPE_CMPSW i16 cr w + INVALID rcw ArSI + INVALID r FINAL_DSEG i16 cr w + INVALID rcw ArDI + INVALID r FINAL_ESEG1 INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_REPNE_CMPSW i16 cr w + INVALID rcw ArSI + INVALID r FINAL_DSEG i16 cr w + INVALID rcw ArDI + INVALID r FINAL_ESEG1 INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_CMPSW i16 r w + INVALID rw ArSI + INVALID r FINAL_DSEG i16 r w + INVALID rw ArDI + INVALID r FINAL_ESEG1 INVALID rw rFLAGS INTRINSIC_XED_IFORM_REPE_CMPSD i32 cr d + INVALID rcw ArSI + INVALID r FINAL_DSEG i32 cr d + INVALID rcw ArDI + INVALID r FINAL_ESEG1 INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_REPNE_CMPSD i32 cr d + INVALID rcw ArSI + INVALID r FINAL_DSEG i32 cr d + INVALID rcw ArDI + INVALID r FINAL_ESEG1 INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_CMPSD i32 r d + INVALID rw ArSI + INVALID r FINAL_DSEG i32 r d + INVALID rw ArDI + INVALID r FINAL_ESEG1 INVALID rw rFLAGS INTRINSIC_XED_IFORM_REPE_CMPSQ i64 cr q + INVALID rcw ArSI + INVALID r FINAL_DSEG i64 cr q + INVALID rcw ArDI + INVALID r FINAL_ESEG1 INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_REPNE_CMPSQ i64 cr q + INVALID rcw ArSI + INVALID r FINAL_DSEG i64 cr q + INVALID rcw ArDI + INVALID r FINAL_ESEG1 INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_CMPSQ i64 r q + INVALID rw ArSI + INVALID r FINAL_DSEG i64 r q + INVALID rw ArDI + INVALID r FINAL_ESEG1 INVALID rw rFLAGS INTRINSIC_XED_IFORM_REP_STOSB u8 cw b - INVALID r XED_REG_AL + INVALID rcw ArDI + INVALID r FINAL_ESEG INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_STOSB u8 w b - INVALID r XED_REG_AL + INVALID rw ArDI + INVALID r FINAL_ESEG INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_STOSW i16 cw w - INVALID r XED_REG_AX + INVALID rcw ArDI + INVALID r FINAL_ESEG INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_STOSW i16 w w - INVALID r XED_REG_AX + INVALID rw ArDI + INVALID r FINAL_ESEG INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_STOSD i32 cw d - INVALID r XED_REG_EAX + INVALID rcw ArDI + INVALID r FINAL_ESEG INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_STOSD i32 w d - INVALID r XED_REG_EAX + INVALID rw ArDI + INVALID r FINAL_ESEG INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_STOSQ i64 cw q - INVALID r XED_REG_RAX + INVALID rcw ArDI + INVALID r FINAL_ESEG INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_STOSQ i64 w q - INVALID r XED_REG_RAX + INVALID rw ArDI + INVALID r FINAL_ESEG INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_LODSB - INVALID cw XED_REG_AL u8 cr b + INVALID rcw ArSI + INVALID r FINAL_DSEG INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_LODSB - INVALID w XED_REG_AL u8 r b + INVALID rw ArSI + INVALID r FINAL_DSEG INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_LODSW - INVALID cw XED_REG_AX i16 cr w + INVALID rcw ArSI + INVALID r FINAL_DSEG INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_LODSW - INVALID w XED_REG_AX i16 r w + INVALID rw ArSI + INVALID r FINAL_DSEG INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_LODSD - INVALID cw XED_REG_EAX i32 cr d + INVALID rcw ArSI + INVALID r FINAL_DSEG INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_LODSD - INVALID w XED_REG_EAX i32 r d + INVALID rw ArSI + INVALID r FINAL_DSEG INVALID r rFLAGS INTRINSIC_XED_IFORM_REP_LODSQ - INVALID cw XED_REG_RAX i64 cr q + INVALID rcw ArSI + INVALID r FINAL_DSEG INVALID rcw ArCX INVALID r rFLAGS INTRINSIC_XED_IFORM_LODSQ - INVALID w XED_REG_RAX i64 r q + INVALID rw ArSI + INVALID r FINAL_DSEG INVALID r rFLAGS INTRINSIC_XED_IFORM_REPE_SCASB - INVALID r XED_REG_AL u8 cr b + INVALID rcw ArDI + INVALID r FINAL_ESEG INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_REPNE_SCASB - INVALID r XED_REG_AL u8 cr b + INVALID rcw ArDI + INVALID r FINAL_ESEG INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_SCASB - INVALID r XED_REG_AL u8 r b + INVALID rw ArDI + INVALID r FINAL_ESEG INVALID rw rFLAGS INTRINSIC_XED_IFORM_REPE_SCASW - INVALID r XED_REG_AX i16 cr w + INVALID rcw ArDI + INVALID r FINAL_ESEG INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_REPNE_SCASW - INVALID r XED_REG_AX i16 cr w + INVALID rcw ArDI + INVALID r FINAL_ESEG INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_SCASW - INVALID r XED_REG_AX i16 r w + INVALID rw ArDI + INVALID r FINAL_ESEG INVALID rw rFLAGS INTRINSIC_XED_IFORM_REPE_SCASD - INVALID r XED_REG_EAX i32 cr d + INVALID rcw ArDI + INVALID r FINAL_ESEG INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_REPNE_SCASD - INVALID r XED_REG_EAX i32 cr d + INVALID rcw ArDI + INVALID r FINAL_ESEG INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_SCASD - INVALID r XED_REG_EAX i32 r d + INVALID rw ArDI + INVALID r FINAL_ESEG INVALID rw rFLAGS INTRINSIC_XED_IFORM_REPE_SCASQ - INVALID r XED_REG_RAX i64 cr q + INVALID rcw ArDI + INVALID r FINAL_ESEG INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_REPNE_SCASQ - INVALID r XED_REG_RAX i64 cr q + INVALID rcw ArDI + INVALID r FINAL_ESEG INVALID rcw ArCX INVALID rcw rFLAGS INTRINSIC_XED_IFORM_SCASQ - INVALID r XED_REG_RAX i64 r q + INVALID rw ArDI + INVALID r FINAL_ESEG INVALID rw rFLAGS INTRINSIC_XED_IFORM_RET_NEAR_IMMw - int r spw + i16 r w + int rw spw INVALID w rIP int r spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_RET_NEAR - int r spw + int rw spw INVALID w rIP int r spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_LES_GPRz_MEMp INVALID w GPRz_R struct r p - INVALID w XED_REG_ES INTRINSIC_XED_IFORM_LDS_GPRz_MEMp INVALID w GPRz_R struct r p - INVALID w XED_REG_DS INTRINSIC_XED_IFORM_ENTER_IMMw_IMMb - int w spw + i16 r w + u8 r b + int rw spw INVALID rw OrBP int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_LEAVE int r v + INVALID r ArBP + INVALID r FINAL_SSEG0 INVALID rw OrBP INVALID rw OrSP INTRINSIC_XED_IFORM_RET_FAR_IMMw - int r spw2 + i16 r w + int rw spw2 INVALID w rIP int r spw2 + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_RET_FAR - int r spw2 + int rw spw2 INVALID w rIP int r spw2 + INVALID rw SrSP + INVALID r FINAL_SSEG0 INTRINSIC_XED_IFORM_INT3 INVALID w rIP INVALID rw rFLAGS INTRINSIC_XED_IFORM_INT_IMMb + u8 r b INVALID w rIP INVALID rw rFLAGS INTRINSIC_XED_IFORM_INTO - INVALID w XED_REG_EIP INVALID rw rFLAGS INTRINSIC_XED_IFORM_IRET - int r spw5 + int rw spw5 INVALID w rIP int r spw5 + INVALID rw SrSP + INVALID r FINAL_SSEG0 INVALID rw rFLAGS INTRINSIC_XED_IFORM_IRETD - int r spw5 + int rw spw5 INVALID w rIP int r spw5 + INVALID rw SrSP + INVALID r FINAL_SSEG0 INVALID rw rFLAGS INTRINSIC_XED_IFORM_IRETQ + int rw spw5 int r spw5 - INVALID w XED_REG_RIP - int r spw5 + INVALID rw SrSP + INVALID r FINAL_SSEG0 INVALID rw rFLAGS INTRINSIC_XED_IFORM_AAM_IMMb - INVALID rw XED_REG_AL - INVALID w XED_REG_AH + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_AAD_IMMb - INVALID rw XED_REG_AL - INVALID rw XED_REG_AH + i8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SALC - INVALID w XED_REG_AL INVALID r rFLAGS INTRINSIC_XED_IFORM_XLAT u8 r b - INVALID w XED_REG_AL + INVALID r ArBX + INVALID r FINAL_DSEG INTRINSIC_XED_IFORM_LOOPNE_RELBRb + i8 r b INVALID rw ArCX INVALID rw rIP INVALID r rFLAGS INTRINSIC_XED_IFORM_LOOPE_RELBRb + i8 r b INVALID rw ArCX INVALID rw rIP INVALID r rFLAGS INTRINSIC_XED_IFORM_LOOP_RELBRb + i8 r b INVALID rw ArCX INVALID rw rIP INTRINSIC_XED_IFORM_JCXZ_RELBRb - INVALID r XED_REG_CX - INVALID rw XED_REG_IP + i8 r b INTRINSIC_XED_IFORM_JECXZ_RELBRb - INVALID r XED_REG_ECX - INVALID rw XED_REG_EIP + i8 r b INTRINSIC_XED_IFORM_JRCXZ_RELBRb - INVALID r XED_REG_RCX - INVALID rw XED_REG_RIP + i8 r b INTRINSIC_XED_IFORM_IN_AL_IMMb - INVALID w XED_REG_AL + u8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_IN_OeAX_IMMb INVALID w OeAX + u8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_IN_AL_DX - INVALID w XED_REG_AL - INVALID r XED_REG_DX INVALID r rFLAGS INTRINSIC_XED_IFORM_IN_OeAX_DX INVALID w OeAX - INVALID r XED_REG_DX INVALID r rFLAGS INTRINSIC_XED_IFORM_OUT_IMMb_AL - INVALID r XED_REG_AL + u8 r b INVALID r rFLAGS INTRINSIC_XED_IFORM_OUT_IMMb_OeAX + u8 r b INVALID r OeAX INVALID r rFLAGS INTRINSIC_XED_IFORM_OUT_DX_AL - INVALID r XED_REG_DX - INVALID r XED_REG_AL INVALID r rFLAGS INTRINSIC_XED_IFORM_OUT_DX_OeAX - INVALID r XED_REG_DX INVALID r OeAX INVALID r rFLAGS @@ -4036,22 +4088,14 @@ INTRINSIC_XED_IFORM_LSL_GPRv_GPRz INVALID w rFLAGS INTRINSIC_XED_IFORM_SYSCALL - INVALID w XED_REG_RIP - INVALID w XED_REG_RCX - INVALID w XED_REG_R11 INVALID w rFLAGS INTRINSIC_XED_IFORM_CLTS INTRINSIC_XED_IFORM_SYSRET - INVALID w XED_REG_EIP - INVALID r XED_REG_ECX INVALID w rFLAGS INTRINSIC_XED_IFORM_SYSRET64 - INVALID w XED_REG_RIP - INVALID r XED_REG_RCX - INVALID r XED_REG_R11 INVALID w rFLAGS INTRINSIC_XED_IFORM_MOVUPS_XMMps_MEMps @@ -4135,7 +4179,7 @@ INTRINSIC_XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11 f64 r pd INTRINSIC_XED_IFORM_MOVLPD_XMMsd_MEMq - f64 w sd + f64 rw sd i64 r q INTRINSIC_XED_IFORM_MOVLPD_MEMq_XMMsd @@ -4159,7 +4203,7 @@ INTRINSIC_XED_IFORM_UNPCKHPD_XMMpd_XMMq i64 r q INTRINSIC_XED_IFORM_MOVHPD_XMMsd_MEMq - f64 w sd + f64 rw sd i64 r q INTRINSIC_XED_IFORM_MOVHPD_MEMq_XMMsd @@ -4223,38 +4267,17 @@ INTRINSIC_XED_IFORM_MOV_DR_GPR64_DR INVALID r DR_R INTRINSIC_XED_IFORM_WRMSR - INVALID r XED_REG_EAX - INVALID r XED_REG_EDX - INVALID r XED_REG_ECX - INVALID w XED_REG_MSRS INTRINSIC_XED_IFORM_RDTSC - INVALID w XED_REG_EAX - INVALID w XED_REG_EDX - INVALID r XED_REG_TSC INTRINSIC_XED_IFORM_RDMSR - INVALID w XED_REG_EAX - INVALID w XED_REG_EDX - INVALID r XED_REG_ECX - INVALID r XED_REG_MSRS INTRINSIC_XED_IFORM_RDPMC - INVALID w XED_REG_EAX - INVALID w XED_REG_EDX - INVALID r XED_REG_ECX - INVALID r XED_REG_MSRS INTRINSIC_XED_IFORM_SYSENTER - INVALID w XED_REG_EIP - INVALID w XED_REG_ESP INVALID w rFLAGS INTRINSIC_XED_IFORM_SYSEXIT - INVALID w XED_REG_EIP - INVALID w XED_REG_ESP - INVALID r XED_REG_ECX - INVALID r XED_REG_EDX INTRINSIC_XED_IFORM_CMOVO_GPRv_MEMv INVALID cw GPRv_R @@ -4397,27 +4420,27 @@ INTRINSIC_XED_IFORM_XORPS_XMMxud_XMMxud u32 r xud INTRINSIC_XED_IFORM_SQRTSS_XMMss_MEMss - f32 w ss + f32 rw ss f32 r ss INTRINSIC_XED_IFORM_SQRTSS_XMMss_XMMss - f32 w ss + f32 rw ss f32 r ss INTRINSIC_XED_IFORM_RSQRTSS_XMMss_MEMss - f32 w ss + f32 rw ss f32 r ss INTRINSIC_XED_IFORM_RSQRTSS_XMMss_XMMss - f32 w ss + f32 rw ss f32 r ss INTRINSIC_XED_IFORM_RCPSS_XMMss_MEMss - f32 w ss + f32 rw ss f32 r ss INTRINSIC_XED_IFORM_RCPSS_XMMss_XMMss - f32 w ss + f32 rw ss f32 r ss INTRINSIC_XED_IFORM_MOVMSKPD_GPR32_XMMpd @@ -4465,11 +4488,11 @@ INTRINSIC_XED_IFORM_XORPD_XMMxuq_XMMxuq u64 r xuq INTRINSIC_XED_IFORM_SQRTSD_XMMsd_MEMsd - f64 w sd + f64 rw sd f64 r sd INTRINSIC_XED_IFORM_SQRTSD_XMMsd_XMMsd - f64 w sd + f64 rw sd f64 r sd INTRINSIC_XED_IFORM_PUNPCKLBW_MMXq_MEMd @@ -4603,10 +4626,12 @@ INTRINSIC_XED_IFORM_PACKUSWB_XMMdq_XMMdq INTRINSIC_XED_IFORM_PSHUFW_MMXq_MEMq_IMMb u16 w q u16 r q + u8 r b INTRINSIC_XED_IFORM_PSHUFW_MMXq_MMXq_IMMb u16 w q u16 r q + u8 r b INTRINSIC_XED_IFORM_PCMPEQB_MMXq_MEMq i8 rw q @@ -4661,26 +4686,32 @@ INTRINSIC_XED_IFORM_EMMS INTRINSIC_XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb u32 w dq u32 r dq + u8 r b INTRINSIC_XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb u32 w dq u32 r dq + u8 r b INTRINSIC_XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb u16 w dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb u16 w dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb u16 w dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb u16 w dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_SETO_MEMb u8 w b @@ -4747,15 +4778,10 @@ INTRINSIC_XED_IFORM_SETNBE_GPR8 INVALID r rFLAGS INTRINSIC_XED_IFORM_CPUID - INVALID rw XED_REG_EAX - INVALID w XED_REG_EBX - INVALID crw XED_REG_ECX - INVALID w XED_REG_EDX INTRINSIC_XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8 u8 rcw b INVALID r GPR8_R - INVALID rcw XED_REG_AL INVALID w rFLAGS INTRINSIC_XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv @@ -4767,13 +4793,11 @@ INTRINSIC_XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv INTRINSIC_XED_IFORM_CMPXCHG_MEMb_GPR8 u8 rcw b INVALID r GPR8_R - INVALID rcw XED_REG_AL INVALID w rFLAGS INTRINSIC_XED_IFORM_CMPXCHG_GPR8_GPR8 INVALID rcw GPR8_B INVALID r GPR8_R - INVALID rcw XED_REG_AL INVALID w rFLAGS INTRINSIC_XED_IFORM_CMPXCHG_MEMv_GPRv @@ -4791,17 +4815,14 @@ INTRINSIC_XED_IFORM_CMPXCHG_GPRv_GPRv INTRINSIC_XED_IFORM_LSS_GPRv_MEMp2 INVALID w GPRv_R struct r p2 - INVALID w XED_REG_SS INTRINSIC_XED_IFORM_LFS_GPRv_MEMp2 INVALID w GPRv_R struct r p2 - INVALID w XED_REG_FS INTRINSIC_XED_IFORM_LGS_GPRv_MEMp2 INVALID w GPRv_R struct r p2 - INVALID w XED_REG_GS INTRINSIC_XED_IFORM_MOVZX_GPRv_MEMb INVALID w GPRv_R @@ -4852,10 +4873,12 @@ INTRINSIC_XED_IFORM_XADD_GPRv_GPRv INTRINSIC_XED_IFORM_CMPPS_XMMps_MEMps_IMMb f32 rw ps f32 r ps + u8 r b INTRINSIC_XED_IFORM_CMPPS_XMMps_XMMps_IMMb f32 rw ps f32 r ps + u8 r b INTRINSIC_XED_IFORM_MOVNTI_MEMd_GPR32 i32 w d @@ -4868,66 +4891,82 @@ INTRINSIC_XED_IFORM_MOVNTI_MEMq_GPR64 INTRINSIC_XED_IFORM_PINSRW_MMXq_MEMw_IMMb u16 rw q u16 r w + u8 r b INTRINSIC_XED_IFORM_PINSRW_MMXq_GPR32_IMMb u16 rw q INVALID r GPR32_B + u8 r b INTRINSIC_XED_IFORM_PINSRW_XMMdq_MEMw_IMMb i32 rw dq i16 r w + u8 r b INTRINSIC_XED_IFORM_PINSRW_XMMdq_GPR32_IMMb i32 rw dq INVALID r GPR32_B + u8 r b INTRINSIC_XED_IFORM_PEXTRW_GPR32_MMXq_IMMb INVALID w GPR32_R u16 r q + u8 r b INTRINSIC_XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb INVALID w GPR32_R i32 r dq + u8 r b INTRINSIC_XED_IFORM_SHUFPS_XMMps_MEMps_IMMb f32 rw ps f32 r ps + u8 r b INTRINSIC_XED_IFORM_SHUFPS_XMMps_XMMps_IMMb f32 rw ps f32 r ps + u8 r b INTRINSIC_XED_IFORM_CMPSS_XMMss_MEMss_IMMb f32 rw ss f32 r ss + u8 r b INTRINSIC_XED_IFORM_CMPSS_XMMss_XMMss_IMMb f32 rw ss f32 r ss + u8 r b INTRINSIC_XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb f64 rw pd f64 r pd + u8 r b INTRINSIC_XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb f64 rw pd f64 r pd + u8 r b INTRINSIC_XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb f64 rw pd f64 r pd + u8 r b INTRINSIC_XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb f64 rw pd f64 r pd + u8 r b INTRINSIC_XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb f64 rw sd f64 r sd + u8 r b INTRINSIC_XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb f64 rw sd f64 r sd + u8 r b INTRINSIC_XED_IFORM_PADDQ_MMXq_MEMq u64 rw q @@ -5141,11 +5180,15 @@ INTRINSIC_XED_IFORM_MASKMOVQ_MMXq_MMXq u8 r q i8 r q i64 w q + INVALID r ArDI + INVALID r FINAL_DSEG -INTRINSIC_XED_IFORM_MASKMOVDQU_XMMdq_XMMdq - i32 r dq - i32 r dq - i32 w dq +INTRINSIC_XED_IFORM_MASKMOVDQU_XMMxub_XMMxub + u8 r xub + u8 r xub + u8 w xub + INVALID r ArDI + INVALID r FINAL_DSEG INTRINSIC_XED_IFORM_LDDQU_XMMpd_MEMdq f64 w pd @@ -5153,6 +5196,8 @@ INTRINSIC_XED_IFORM_LDDQU_XMMpd_MEMdq INTRINSIC_XED_IFORM_INVD +INTRINSIC_XED_IFORM_UD0 + INTRINSIC_XED_IFORM_UD0_GPR32_MEMd INVALID r GPR32_R i32 r d @@ -5188,11 +5233,11 @@ INTRINSIC_XED_IFORM_MOVAPS_XMMps_XMMps_0F29 f32 r ps INTRINSIC_XED_IFORM_CVTPI2PS_XMMq_MEMq - f32 w q + f32 rw q i32 r q INTRINSIC_XED_IFORM_CVTPI2PS_XMMq_MMXq - f32 w q + f32 rw q i32 r q INTRINSIC_XED_IFORM_MOVNTPS_MEMdq_XMMps @@ -5236,19 +5281,19 @@ INTRINSIC_XED_IFORM_COMISS_XMMss_XMMss INVALID w rFLAGS INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_MEMd - f32 w ss + f32 rw ss i32 r d INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_GPR32d - f32 w ss + f32 rw ss i32 r d INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_MEMq - f32 w ss + f32 rw ss i32 r q INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_GPR64q - f32 w ss + f32 rw ss i32 r q INTRINSIC_XED_IFORM_CVTTSS2SI_GPR32d_MEMss @@ -5348,19 +5393,19 @@ INTRINSIC_XED_IFORM_COMISD_XMMsd_XMMsd INVALID w rFLAGS INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_MEMd - f64 w sd + f64 rw sd i32 r d INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_GPR32d - f64 w sd + f64 rw sd i32 r d INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_MEMq - f64 w sd + f64 rw sd i64 r q INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_GPR64q - f64 w sd + f64 rw sd i64 r q INTRINSIC_XED_IFORM_CVTTSD2SI_GPR32d_MEMsd @@ -5556,11 +5601,11 @@ INTRINSIC_XED_IFORM_MULSS_XMMss_XMMss f32 r ss INTRINSIC_XED_IFORM_CVTSS2SD_XMMsd_MEMss - f64 w sd + f64 rw sd f32 r ss INTRINSIC_XED_IFORM_CVTSS2SD_XMMsd_XMMss - f64 w sd + f64 rw sd f32 r ss INTRINSIC_XED_IFORM_CVTTPS2DQ_XMMdq_MEMps @@ -5684,11 +5729,11 @@ INTRINSIC_XED_IFORM_MULSD_XMMsd_XMMsd f64 r sd INTRINSIC_XED_IFORM_CVTSD2SS_XMMss_MEMsd - f32 w ss + f32 rw ss f64 r sd INTRINSIC_XED_IFORM_CVTSD2SS_XMMss_XMMsd - f32 w ss + f32 rw ss f64 r sd INTRINSIC_XED_IFORM_SUBSD_XMMsd_MEMsd @@ -6074,45 +6119,45 @@ INTRINSIC_XED_IFORM_RSM INTRINSIC_XED_IFORM_SHRD_MEMv_GPRv_IMMb int rcw v INVALID r GPRv_R + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_IMMb INVALID rcw GPRv_B INVALID r GPRv_R + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHRD_MEMv_GPRv_CL int rcw v INVALID r GPRv_R - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_CL INVALID rcw GPRv_B INVALID r GPRv_R - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SHLD_MEMv_GPRv_IMMb int rcw v INVALID r GPRv_R + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_IMMb INVALID rcw GPRv_B INVALID r GPRv_R + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_SHLD_MEMv_GPRv_CL int rcw v INVALID r GPRv_R - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_CL INVALID rcw GPRv_B INVALID r GPRv_R - INVALID r XED_REG_CL INVALID cw rFLAGS INTRINSIC_XED_IFORM_MOVSX_GPRv_MEMb @@ -6697,18 +6742,22 @@ INTRINSIC_XED_IFORM_PSIGND_XMMdq_XMMdq INTRINSIC_XED_IFORM_PALIGNR_MMXq_MEMq_IMMb i64 rw q i64 r q + u8 r b INTRINSIC_XED_IFORM_PALIGNR_MMXq_MMXq_IMMb i64 rw q i64 r q + u8 r b INTRINSIC_XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb i32 rw dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb i32 rw dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_PABSB_MMXq_MEMq i64 w q @@ -6795,18 +6844,22 @@ INTRINSIC_XED_IFORM_CRC32_GPRyy_GPRv INTRINSIC_XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb f64 rw dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb f64 rw dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb f32 rw dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb f32 rw dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_BLENDVPD_XMMdq_MEMdq f64 rw dq @@ -6839,18 +6892,22 @@ INTRINSIC_XED_IFORM_PCMPEQQ_XMMdq_XMMdq INTRINSIC_XED_IFORM_DPPD_XMMdq_MEMdq_IMMb f64 rw dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_DPPD_XMMdq_XMMdq_IMMb f64 rw dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_DPPS_XMMdq_MEMdq_IMMb f32 rw dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_DPPS_XMMdq_XMMdq_IMMb f32 rw dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_MOVNTDQA_XMMdq_MEMdq i32 w dq @@ -6859,26 +6916,32 @@ INTRINSIC_XED_IFORM_MOVNTDQA_XMMdq_MEMdq INTRINSIC_XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb i32 w d f32 r ps + u8 r b INTRINSIC_XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb i32 w d i32 r dq + u8 r b INTRINSIC_XED_IFORM_INSERTPS_XMMps_MEMd_IMMb f32 rw ps i32 r d + u8 r b INTRINSIC_XED_IFORM_INSERTPS_XMMps_XMMps_IMMb f32 rw ps f32 r ps + u8 r b INTRINSIC_XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb u8 rw dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb u8 rw dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_PACKUSDW_XMMdq_MEMdq i32 rw dq @@ -6891,10 +6954,12 @@ INTRINSIC_XED_IFORM_PACKUSDW_XMMdq_XMMdq INTRINSIC_XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb i32 rw dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb i32 rw dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_PBLENDVB_XMMdq_MEMdq i32 rw dq @@ -6909,90 +6974,112 @@ INTRINSIC_XED_IFORM_PBLENDVB_XMMdq_XMMdq INTRINSIC_XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb u8 w b i32 r dq + u8 r b INTRINSIC_XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb i32 w d i32 r dq + u8 r b INTRINSIC_XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb i16 w w i32 r dq + u8 r b INTRINSIC_XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb INVALID w GPR32_B i32 r dq + u8 r b INTRINSIC_XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb i64 w q i32 r dq + u8 r b INTRINSIC_XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb i64 w q i32 r dq + u8 r b INTRINSIC_XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb i32 w d i32 r dq + u8 r b INTRINSIC_XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb i32 w d i32 r dq + u8 r b INTRINSIC_XED_IFORM_PINSRB_XMMdq_MEMb_IMMb i32 rw dq u8 r b + u8 r b INTRINSIC_XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb i32 rw dq i32 r d + u8 r b INTRINSIC_XED_IFORM_PINSRD_XMMdq_MEMd_IMMb i32 rw dq i32 r d + u8 r b INTRINSIC_XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb i32 rw dq i32 r d + u8 r b INTRINSIC_XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb i32 rw dq i64 r q + u8 r b INTRINSIC_XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb i32 rw dq i64 r q + u8 r b INTRINSIC_XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb f64 w pd f64 r pd + u8 r b INTRINSIC_XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb f64 w pd f64 r pd + u8 r b INTRINSIC_XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb f32 w ps f32 r ps + u8 r b INTRINSIC_XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb f32 w ps f32 r ps + u8 r b INTRINSIC_XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb - i64 w q + i64 rw q i64 r q + u8 r b INTRINSIC_XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb - i64 w q + i64 rw q i64 r q + u8 r b INTRINSIC_XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb - i32 w d + i32 rw d i32 r d + u8 r b INTRINSIC_XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb - i32 w d + i32 rw d i32 r d + u8 r b INTRINSIC_XED_IFORM_PTEST_XMMdq_MEMdq i32 r dq @@ -7191,138 +7278,108 @@ INTRINSIC_XED_IFORM_PMOVZXDQ_XMMdq_XMMq INTRINSIC_XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb i32 r dq i32 r dq - INVALID r XED_REG_EAX - INVALID r XED_REG_EDX - INVALID w XED_REG_ECX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb i32 r dq i32 r dq - INVALID r XED_REG_EAX - INVALID r XED_REG_EDX - INVALID w XED_REG_ECX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb i32 r dq i32 r dq - INVALID r XED_REG_RAX - INVALID r XED_REG_RDX - INVALID w XED_REG_RCX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb i32 r dq i32 r dq - INVALID r XED_REG_RAX - INVALID r XED_REG_RDX - INVALID w XED_REG_RCX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb i32 r dq i32 r dq - INVALID w XED_REG_ECX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb i32 r dq i32 r dq - INVALID w XED_REG_ECX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb i32 r dq i32 r dq - INVALID w XED_REG_RCX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb i32 r dq i32 r dq - INVALID w XED_REG_RCX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb i32 r dq i32 r dq - INVALID r XED_REG_EAX - INVALID r XED_REG_EDX + u8 r b i32 w dq INVALID w rFLAGS INTRINSIC_XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb i32 r dq i32 r dq - INVALID r XED_REG_EAX - INVALID r XED_REG_EDX + u8 r b i32 w dq INVALID w rFLAGS INTRINSIC_XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb i32 r dq i32 r dq - INVALID r XED_REG_RAX - INVALID r XED_REG_RDX + u8 r b i32 w dq INVALID w rFLAGS INTRINSIC_XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb i32 r dq i32 r dq - INVALID r XED_REG_RAX - INVALID r XED_REG_RDX + u8 r b i32 w dq INVALID w rFLAGS INTRINSIC_XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb i32 r dq i32 r dq + u8 r b i32 w dq INVALID w rFLAGS INTRINSIC_XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb i32 r dq i32 r dq + u8 r b i32 w dq INVALID w rFLAGS INTRINSIC_XED_IFORM_XGETBV - INVALID r XED_REG_ECX - INVALID w XED_REG_EDX - INVALID w XED_REG_EAX - INVALID r XED_REG_XCR0 INTRINSIC_XED_IFORM_XSETBV - INVALID r XED_REG_ECX - INVALID r XED_REG_EDX - INVALID r XED_REG_EAX - INVALID w XED_REG_XCR0 INTRINSIC_XED_IFORM_XSAVE_MEMmxsave struct rw mxsave - INVALID r XED_REG_EDX - INVALID r XED_REG_EAX - INVALID r XED_REG_XCR0 INTRINSIC_XED_IFORM_XRSTOR_MEMmxsave struct r mxsave - INVALID r XED_REG_EDX - INVALID r XED_REG_EAX - INVALID r XED_REG_XCR0 INTRINSIC_XED_IFORM_XSAVE64_MEMmxsave struct rw mxsave - INVALID r XED_REG_EDX - INVALID r XED_REG_EAX - INVALID r XED_REG_XCR0 INTRINSIC_XED_IFORM_XRSTOR64_MEMmxsave struct r mxsave - INVALID r XED_REG_EDX - INVALID r XED_REG_EAX - INVALID r XED_REG_XCR0 INTRINSIC_XED_IFORM_MOVBE_GPRv_MEMv INVALID w GPRv_R @@ -7333,16 +7390,16 @@ INTRINSIC_XED_IFORM_MOVBE_MEMv_GPRv INVALID r GPRv_R INTRINSIC_XED_IFORM_GETSEC - INVALID rcw XED_REG_EAX - INVALID r XED_REG_EBX INTRINSIC_XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb i32 w dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb i32 w dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_AESENC_XMMdq_XMMdq i32 rw dq @@ -7387,10 +7444,12 @@ INTRINSIC_XED_IFORM_AESIMC_XMMdq_MEMdq INTRINSIC_XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb i32 rw dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb i32 rw dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_INVEPT_GPR64_MEMdq INVALID r GPR64_R @@ -7438,19 +7497,27 @@ INTRINSIC_XED_IFORM_XSTORE INVALID r OrCX INVALID rw OrDX INVALID w OrAX + INVALID rw ArDI + INVALID r FINAL_ESEG INTRINSIC_XED_IFORM_REP_XSTORE u8 w b INVALID rw OrCX INVALID rw OrDX INVALID w OrAX + INVALID rw ArDI + INVALID r FINAL_ESEG INTRINSIC_XED_IFORM_REP_XCRYPTECB u8 w b INVALID rw OrCX INVALID r OrDX INVALID r OrBX + INVALID rw ArDI + INVALID r FINAL_ESEG u8 cr b + INVALID rcw ArSI + INVALID r FINAL_DSEG1 INTRINSIC_XED_IFORM_REP_XCRYPTCBC u8 w b @@ -7458,7 +7525,11 @@ INTRINSIC_XED_IFORM_REP_XCRYPTCBC INVALID r OrDX INVALID r OrBX INVALID r ArAX + INVALID rw ArDI + INVALID r FINAL_ESEG u8 cr b + INVALID rcw ArSI + INVALID r FINAL_DSEG1 INTRINSIC_XED_IFORM_REP_XCRYPTCTR u8 w b @@ -7466,7 +7537,11 @@ INTRINSIC_XED_IFORM_REP_XCRYPTCTR INVALID r OrDX INVALID r OrBX INVALID r ArAX + INVALID rw ArDI + INVALID r FINAL_ESEG u8 cr b + INVALID rcw ArSI + INVALID r FINAL_DSEG1 INTRINSIC_XED_IFORM_REP_XCRYPTCFB u8 w b @@ -7474,7 +7549,11 @@ INTRINSIC_XED_IFORM_REP_XCRYPTCFB INVALID r OrDX INVALID r OrBX INVALID r ArAX + INVALID rw ArDI + INVALID r FINAL_ESEG u8 cr b + INVALID rcw ArSI + INVALID r FINAL_DSEG1 INTRINSIC_XED_IFORM_REP_XCRYPTOFB u8 w b @@ -7482,25 +7561,36 @@ INTRINSIC_XED_IFORM_REP_XCRYPTOFB INVALID r OrDX INVALID r OrBX INVALID r ArAX + INVALID rw ArDI + INVALID r FINAL_ESEG u8 cr b + INVALID rcw ArSI + INVALID r FINAL_DSEG1 INTRINSIC_XED_IFORM_REP_XSHA1 INVALID rcw ArAX INVALID rcw OrCX u8 w b + INVALID rw ArSI + INVALID r FINAL_ESEG u8 r b + INVALID r ArDI + INVALID r FINAL_ESEG1 INTRINSIC_XED_IFORM_REP_XSHA256 INVALID rcw ArAX INVALID rcw OrCX u8 w b + INVALID rw ArSI + INVALID r FINAL_ESEG u8 r b + INVALID r ArDI + INVALID r FINAL_ESEG1 INTRINSIC_XED_IFORM_REP_MONTMUL - INVALID rw XED_REG_EAX - INVALID rw XED_REG_ECX - INVALID w XED_REG_EDX struct rw pmmsz16 + INVALID r ArSI + INVALID r FINAL_ESEG INTRINSIC_XED_IFORM_FEMMS @@ -7696,12 +7786,7 @@ INTRINSIC_XED_IFORM_PAVGUSB_MMXq_MMXq i64 rw q i64 r q -INTRINSIC_XED_IFORM_SYSCALL_AMD - INVALID w rIP - INVALID w rFLAGS - INTRINSIC_XED_IFORM_SYSRET_AMD - INVALID w XED_REG_EIP INVALID w rFLAGS INTRINSIC_XED_IFORM_VMRUN_ArAX @@ -7719,14 +7804,14 @@ INTRINSIC_XED_IFORM_STGI INTRINSIC_XED_IFORM_CLGI INTRINSIC_XED_IFORM_SKINIT_EAX - INVALID r XED_REG_EAX INTRINSIC_XED_IFORM_INVLPGA_ArAX_ECX INVALID r ArAX - INVALID r XED_REG_ECX INTRINSIC_XED_IFORM_EXTRQ_XMMq_IMMb_IMMb i64 w q + u8 r b + u8 r b INTRINSIC_XED_IFORM_EXTRQ_XMMq_XMMdq i64 w q @@ -7735,6 +7820,8 @@ INTRINSIC_XED_IFORM_EXTRQ_XMMq_XMMdq INTRINSIC_XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb i64 w q i64 r q + u8 r b + u8 r b INTRINSIC_XED_IFORM_INSERTQ_XMMq_XMMdq i64 w q @@ -7752,13 +7839,8 @@ INTRINSIC_XED_IFORM_CLZERO INVALID r ArAX INTRINSIC_XED_IFORM_MONITORX - INVALID r XED_REG_EAX - INVALID r XED_REG_ECX - INVALID r XED_REG_EDX INTRINSIC_XED_IFORM_MWAITX - INVALID rw XED_REG_EAX - INVALID r XED_REG_ECX INTRINSIC_XED_IFORM_MCOMMIT INVALID w rFLAGS @@ -7769,26 +7851,23 @@ INTRINSIC_XED_IFORM_RDPRU i32 r d INTRINSIC_XED_IFORM_PSMASH_RAX - INVALID rw XED_REG_RAX INVALID w rFLAGS INTRINSIC_XED_IFORM_PVALIDATE_RAX_ECX_EDX - INVALID rw XED_REG_RAX - INVALID r XED_REG_ECX - INVALID r XED_REG_EDX INVALID w rFLAGS INTRINSIC_XED_IFORM_RMPADJUST_RAX_RCX_RDX - INVALID rw XED_REG_RAX - INVALID r XED_REG_RCX - INVALID r XED_REG_RDX INVALID w rFLAGS INTRINSIC_XED_IFORM_RMPUPDATE_RAX_RCX - INVALID rw XED_REG_RAX - INVALID r XED_REG_RCX INVALID w rFLAGS +INTRINSIC_XED_IFORM_INVLPGB_EAX_EDX_ECX + +INTRINSIC_XED_IFORM_INVLPGB_RAX_EDX_ECX + +INTRINSIC_XED_IFORM_TLBSYNC + INTRINSIC_XED_IFORM_BNDMK_BND_AGEN INVALID w BND_R @@ -7940,10 +8019,12 @@ INTRINSIC_XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA INTRINSIC_XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA i32 rw dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA i32 rw dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA i32 rw dq @@ -7973,51 +8054,27 @@ INTRINSIC_XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA INTRINSIC_XED_IFORM_XSAVEOPT_MEMmxsave struct rw mxsave - INVALID r XED_REG_EDX - INVALID r XED_REG_EAX - INVALID r XED_REG_XCR0 INTRINSIC_XED_IFORM_XSAVEOPT64_MEMmxsave struct rw mxsave - INVALID r XED_REG_EDX - INVALID r XED_REG_EAX - INVALID r XED_REG_XCR0 INTRINSIC_XED_IFORM_XSAVES_MEMmxsave struct w mxsave - INVALID r XED_REG_EDX - INVALID r XED_REG_EAX - INVALID r XED_REG_XCR0 INTRINSIC_XED_IFORM_XSAVES64_MEMmxsave struct w mxsave - INVALID r XED_REG_EDX - INVALID r XED_REG_EAX - INVALID r XED_REG_XCR0 INTRINSIC_XED_IFORM_XRSTORS_MEMmxsave struct r mxsave - INVALID r XED_REG_EDX - INVALID r XED_REG_EAX - INVALID r XED_REG_XCR0 INTRINSIC_XED_IFORM_XRSTORS64_MEMmxsave struct r mxsave - INVALID r XED_REG_EDX - INVALID r XED_REG_EAX - INVALID r XED_REG_XCR0 INTRINSIC_XED_IFORM_XSAVEC_MEMmxsave struct w mxsave - INVALID r XED_REG_EDX - INVALID r XED_REG_EAX - INVALID r XED_REG_XCR0 INTRINSIC_XED_IFORM_XSAVEC64_MEMmxsave struct w mxsave - INVALID r XED_REG_EDX - INVALID r XED_REG_EAX - INVALID r XED_REG_XCR0 INTRINSIC_XED_IFORM_CLFLUSHOPT_MEMmprefetch i64 r mprefetch @@ -8049,16 +8106,8 @@ INTRINSIC_XED_IFORM_STAC INVALID w rFLAGS INTRINSIC_XED_IFORM_ENCLU - INVALID r XED_REG_EAX - INVALID crw XED_REG_RBX - INVALID crw XED_REG_RCX - INVALID crw XED_REG_RDX INTRINSIC_XED_IFORM_ENCLS - INVALID r XED_REG_EAX - INVALID crw XED_REG_RBX - INVALID crw XED_REG_RCX - INVALID crw XED_REG_RDX INTRINSIC_XED_IFORM_RDPID_GPR32u32 u32 w d @@ -8078,6 +8127,7 @@ INTRINSIC_XED_IFORM_MOVDIR64B_GPRa_MEM INVALID r A_GPR_R u32 r zd i32 w zd + INVALID r A_GPR_R INTRINSIC_XED_IFORM_MOVDIRI_MEMu32_GPR32u32 u32 w d @@ -8093,12 +8143,6 @@ INTRINSIC_XED_IFORM_TPAUSE_GPR32u32 u32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_TPAUSE_GPR64u64 - u64 r q - u32 r d - u32 r d - INVALID w rFLAGS - INTRINSIC_XED_IFORM_UMONITOR_GPRa INVALID r A_GPR_B @@ -8108,21 +8152,9 @@ INTRINSIC_XED_IFORM_UMWAIT_GPR32 u32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_UMWAIT_GPR64 - u64 r q - u32 r d - u32 r d - INVALID w rFLAGS - INTRINSIC_XED_IFORM_CLDEMOTE_MEMu8 u8 r b -INTRINSIC_XED_IFORM_ENCLV - u32 r d - u64 crw q - u64 crw q - u64 crw q - INTRINSIC_XED_IFORM_TZCNT_GPRv_MEMv INVALID w GPRv_R int r v @@ -8144,7 +8176,6 @@ INTRINSIC_XED_IFORM_BSF_GPRv_GPRv INVALID w rFLAGS INTRINSIC_XED_IFORM_VMFUNC - INVALID r XED_REG_EAX INTRINSIC_XED_IFORM_INVPCID_GPR64_MEMdq INVALID r GPR64_R @@ -8175,13 +8206,13 @@ INTRINSIC_XED_IFORM_BSR_GPRv_GPRv INVALID w rFLAGS INTRINSIC_XED_IFORM_XBEGIN_RELBRz + int r z INVALID rw rIP - INVALID cw XED_REG_EAX INTRINSIC_XED_IFORM_XEND INTRINSIC_XED_IFORM_XABORT_IMMb - INVALID rcw XED_REG_EAX + u8 r b INTRINSIC_XED_IFORM_XTEST INVALID w rFLAGS @@ -8227,25 +8258,25 @@ INTRINSIC_XED_IFORM_ADOX_GPR64q_MEMq INVALID rw rFLAGS INTRINSIC_XED_IFORM_RDPKRU - INVALID w XED_REG_EDX - INVALID w XED_REG_EAX - INVALID r XED_REG_ECX INTRINSIC_XED_IFORM_WRPKRU - INVALID r XED_REG_EDX - INVALID r XED_REG_EAX - INVALID r XED_REG_ECX INTRINSIC_XED_IFORM_CLWB_MEMmprefetch i64 r mprefetch INTRINSIC_XED_IFORM_PREFETCHWT1_MEMu8 - u8 r b + i64 r mprefetch INTRINSIC_XED_IFORM_WBINVD INTRINSIC_XED_IFORM_WBNOINVD +INTRINSIC_XED_IFORM_ENCLV + u32 r d + u64 crw q + u64 crw q + u64 crw q + INTRINSIC_XED_IFORM_PCONFIG u32 rw d u32 crw d @@ -8253,21 +8284,32 @@ INTRINSIC_XED_IFORM_PCONFIG u32 crw d INVALID w rFLAGS +INTRINSIC_XED_IFORM_PCONFIG64 + u32 rw d + u64 crw q + u64 crw q + u64 crw q + INVALID w rFLAGS + INTRINSIC_XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8 u8 rw dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8 u8 rw dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8 u8 rw dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8 u8 rw dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_GF2P8MULB_XMMu8_XMMu8 u8 rw dq @@ -8277,6 +8319,129 @@ INTRINSIC_XED_IFORM_GF2P8MULB_XMMu8_MEMu8 u8 rw dq u8 r dq +INTRINSIC_XED_IFORM_AESDEC128KL_XMMu8_MEMu8 + u8 rw dq + u8 r m384 + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AESDEC256KL_XMMu8_MEMu8 + u8 rw dq + u8 r zd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AESDECWIDE128KL_MEMu8 + u8 r m384 + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AESDECWIDE256KL_MEMu8 + u8 r zd + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AESENC128KL_XMMu8_MEMu8 + u8 rw dq + u8 r m384 + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AESENC256KL_XMMu8_MEMu8 + u8 rw dq + u8 r zd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AESENCWIDE128KL_MEMu8 + u8 r m384 + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AESENCWIDE256KL_MEMu8 + u8 r zd + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + u8 rw dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8 + u8 w d + u8 r d + u8 rw dq + u8 w dq + u8 w dq + u8 w dq + u8 w dq + u8 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8 + u8 w d + u8 r d + u8 rw dq + u8 rw dq + u8 w dq + u8 w dq + u8 w dq + u8 w dq + u8 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LOADIWKEY_XMMu8_XMMu8 + u8 r dq + u8 r dq + u32 r d + u8 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_HRESET_IMM8 + u8 r b + u32 r d + +INTRINSIC_XED_IFORM_CLUI + int w i1 + +INTRINSIC_XED_IFORM_SENDUIPI_GPR64u32 + u32 r q + +INTRINSIC_XED_IFORM_STUI + int w i1 + +INTRINSIC_XED_IFORM_TESTUI + int r i1 + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_UIRET + INVALID w rIP + int rw spw + int r spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 + INVALID w rFLAGS + INTRINSIC_XED_IFORM_ENQCMD_GPRa_MEMu32 INVALID r A_GPR_R u32 r zd @@ -8293,6 +8458,134 @@ INTRINSIC_XED_IFORM_XSUSLDTRK INTRINSIC_XED_IFORM_SERIALIZE +INTRINSIC_XED_IFORM_SEAMCALL + u64 rw q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SEAMOPS + u64 rw q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SEAMRET + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TDCALL + u64 r q + +INTRINSIC_XED_IFORM_PREFETCHIT0_MEMu8 + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCHIT1_MEMu8 + i64 r mprefetch + +INTRINSIC_XED_IFORM_RDMSRLIST + u64 r q + u64 r q + u64 rw q + +INTRINSIC_XED_IFORM_WRMSRLIST + u64 r q + u64 r q + u64 rw q + +INTRINSIC_XED_IFORM_WRMSRNS + u32 r d + u32 r d + u32 r d + +INTRINSIC_XED_IFORM_URDMSR_GPR64u64_GPR64u64 + u64 w q + u64 r q + +INTRINSIC_XED_IFORM_UWRMSR_GPR64u64_GPR64u64 + u64 r q + u64 r q + +INTRINSIC_XED_IFORM_PBNDKB + u64 w q + u64 r q + u64 r q + +INTRINSIC_XED_IFORM_ERETS + int rw spw5 + u64 w q + int r spw5 + INVALID rw SrSP + INVALID r FINAL_SSEG0 + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ERETU + int rw spw5 + u16 w u16 + u16 w u16 + u64 w q + u64 w u64 + u64 w u64 + int r spw5 + INVALID rw SrSP + INVALID r FINAL_SSEG0 + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LKGS_GPR16u16 + u16 r w + u64 w u64 + +INTRINSIC_XED_IFORM_LKGS_MEMu16 + u16 r wrd + u64 w u64 + +INTRINSIC_XED_IFORM_SYSCALL_32 + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_JMPABS_ABSBRu64_APX + u64 r u64 + +INTRINSIC_XED_IFORM_PUSHP_GPR64 + INVALID r GPR64_SB + int rw spw + int w spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 + +INTRINSIC_XED_IFORM_POPP_GPR64 + INVALID w GPR64_SB + int rw spw + int r spw + INVALID rw SrSP + INVALID r FINAL_SSEG0 + +INTRINSIC_XED_IFORM_AADD_MEM32_GPR32 + i32 rw d + i32 r d + +INTRINSIC_XED_IFORM_AADD_MEM64_GPR64 + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_AAND_MEM32_GPR32 + i32 rw d + i32 r d + +INTRINSIC_XED_IFORM_AAND_MEM64_GPR64 + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_AOR_MEM32_GPR32 + i32 rw d + i32 r d + +INTRINSIC_XED_IFORM_AOR_MEM64_GPR64 + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_AXOR_MEM32_GPR32 + i32 rw d + i32 r d + +INTRINSIC_XED_IFORM_AXOR_MEM64_GPR64 + i64 rw q + i64 r q + INTRINSIC_XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq VL128 i16 w dq @@ -8472,11 +8765,13 @@ INTRINSIC_XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb VL128 u8 w dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb VL128 u8 w dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq VL128 @@ -8500,11 +8795,13 @@ INTRINSIC_XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb VL128 u16 w dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb VL128 u16 w dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq VL128 @@ -8528,11 +8825,13 @@ INTRINSIC_XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb VL128 u32 w dq u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb VL128 u32 w dq u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq VL128 @@ -8556,11 +8855,13 @@ INTRINSIC_XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb VL128 u64 w dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb VL128 u64 w dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq VL128 @@ -8641,96 +8942,112 @@ VL128 i8 w dq i8 r dq i8 r dq + u8 r b INTRINSIC_XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb VL128 i8 w dq i8 r dq i8 r dq + u8 r b INTRINSIC_XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb VL128 i16 w dq i16 r dq i16 r dq + u8 r b INTRINSIC_XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb VL128 i16 w dq i16 r dq i16 r dq + u8 r b INTRINSIC_XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb VL128 i32 w dq i32 r dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb VL128 i32 w dq i32 r dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb VL128 i64 w dq i64 r dq i64 r dq + u8 r b INTRINSIC_XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb VL128 i64 w dq i64 r dq i64 r dq + u8 r b INTRINSIC_XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb VL128 u8 w dq u8 r dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb VL128 u8 w dq u8 r dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb VL128 u16 w dq u16 r dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb VL128 u16 w dq u16 r dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb VL128 u32 w dq u32 r dq u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb VL128 u32 w dq u32 r dq u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb VL128 u64 w dq u64 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb VL128 u64 w dq u64 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VFRCZPS_XMMdq_MEMdq VL128 @@ -9090,237 +9407,241 @@ INTRINSIC_XED_IFORM_BEXTR_XOP_GPR32d_MEMd_IMMd VL128 i32 w d i32 r d + i32 r d INVALID w rFLAGS INTRINSIC_XED_IFORM_BEXTR_XOP_GPRyy_MEMy_IMMd VL128 int w y int r y + i32 r d INVALID w rFLAGS INTRINSIC_XED_IFORM_BEXTR_XOP_GPR32d_GPR32d_IMMd VL128 i32 w d i32 r d + i32 r d INVALID w rFLAGS INTRINSIC_XED_IFORM_BEXTR_XOP_GPRyy_GPRyy_IMMd VL128 int w y int r y + i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCFILL_VGPR32d_MEMd +INTRINSIC_XED_IFORM_BLCFILL_GPR32d_MEMd VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCFILL_VGPRyy_MEMy +INTRINSIC_XED_IFORM_BLCFILL_GPRyy_MEMy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCFILL_VGPR32d_GPR32d +INTRINSIC_XED_IFORM_BLCFILL_GPR32d_GPR32d VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCFILL_VGPRyy_GPRyy +INTRINSIC_XED_IFORM_BLCFILL_GPRyy_GPRyy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSFILL_VGPR32d_MEMd +INTRINSIC_XED_IFORM_BLSFILL_GPR32d_MEMd VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSFILL_VGPRyy_MEMy +INTRINSIC_XED_IFORM_BLSFILL_GPRyy_MEMy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSFILL_VGPR32d_GPR32d +INTRINSIC_XED_IFORM_BLSFILL_GPR32d_GPR32d VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSFILL_VGPRyy_GPRyy +INTRINSIC_XED_IFORM_BLSFILL_GPRyy_GPRyy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCS_VGPR32d_MEMd +INTRINSIC_XED_IFORM_BLCS_GPR32d_MEMd VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCS_VGPRyy_MEMy +INTRINSIC_XED_IFORM_BLCS_GPRyy_MEMy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCS_VGPR32d_GPR32d +INTRINSIC_XED_IFORM_BLCS_GPR32d_GPR32d VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCS_VGPRyy_GPRyy +INTRINSIC_XED_IFORM_BLCS_GPRyy_GPRyy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_TZMSK_VGPR32d_MEMd +INTRINSIC_XED_IFORM_TZMSK_GPR32d_MEMd VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_TZMSK_VGPRyy_MEMy +INTRINSIC_XED_IFORM_TZMSK_GPRyy_MEMy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_TZMSK_VGPR32d_GPR32d +INTRINSIC_XED_IFORM_TZMSK_GPR32d_GPR32d VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_TZMSK_VGPRyy_GPRyy +INTRINSIC_XED_IFORM_TZMSK_GPRyy_GPRyy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCIC_VGPR32d_MEMd +INTRINSIC_XED_IFORM_BLCIC_GPR32d_MEMd VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCIC_VGPRyy_MEMy +INTRINSIC_XED_IFORM_BLCIC_GPRyy_MEMy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCIC_VGPR32d_GPR32d +INTRINSIC_XED_IFORM_BLCIC_GPR32d_GPR32d VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCIC_VGPRyy_GPRyy +INTRINSIC_XED_IFORM_BLCIC_GPRyy_GPRyy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSIC_VGPR32d_MEMd +INTRINSIC_XED_IFORM_BLSIC_GPR32d_MEMd VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSIC_VGPRyy_MEMy +INTRINSIC_XED_IFORM_BLSIC_GPRyy_MEMy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSIC_VGPR32d_GPR32d +INTRINSIC_XED_IFORM_BLSIC_GPR32d_GPR32d VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSIC_VGPRyy_GPRyy +INTRINSIC_XED_IFORM_BLSIC_GPRyy_GPRyy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_T1MSKC_VGPR32d_MEMd +INTRINSIC_XED_IFORM_T1MSKC_GPR32d_MEMd VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_T1MSKC_VGPRyy_MEMy +INTRINSIC_XED_IFORM_T1MSKC_GPRyy_MEMy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_T1MSKC_VGPR32d_GPR32d +INTRINSIC_XED_IFORM_T1MSKC_GPR32d_GPR32d VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_T1MSKC_VGPRyy_GPRyy +INTRINSIC_XED_IFORM_T1MSKC_GPRyy_GPRyy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCMSK_VGPR32d_MEMd +INTRINSIC_XED_IFORM_BLCMSK_GPR32d_MEMd VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCMSK_VGPRyy_MEMy +INTRINSIC_XED_IFORM_BLCMSK_GPRyy_MEMy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCMSK_VGPR32d_GPR32d +INTRINSIC_XED_IFORM_BLCMSK_GPR32d_GPR32d VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCMSK_VGPRyy_GPRyy +INTRINSIC_XED_IFORM_BLCMSK_GPRyy_GPRyy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCI_VGPR32d_MEMd +INTRINSIC_XED_IFORM_BLCI_GPR32d_MEMd VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCI_VGPRyy_MEMy +INTRINSIC_XED_IFORM_BLCI_GPRyy_MEMy VL128 int w y int r y INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCI_VGPR32d_GPR32d +INTRINSIC_XED_IFORM_BLCI_GPR32d_GPR32d VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLCI_VGPRyy_GPRyy +INTRINSIC_XED_IFORM_BLCI_GPRyy_GPRyy VL128 int w y int r y @@ -9334,27 +9655,31 @@ INTRINSIC_XED_IFORM_SLWPCB_GPRyy VL128 int w y -INTRINSIC_XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd +INTRINSIC_XED_IFORM_LWPINS_GPRyy_MEMd_IMMd VL128 int w y i32 r d + i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_LWPINS_VGPRyy_GPR32y_IMMd +INTRINSIC_XED_IFORM_LWPINS_GPRyy_GPR32d_IMMd VL128 int w y - int r y + i32 r d + i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd +INTRINSIC_XED_IFORM_LWPVAL_GPRyy_MEMd_IMMd VL128 int w y i32 r d + i32 r d -INTRINSIC_XED_IFORM_LWPVAL_VGPRyy_GPR32y_IMMd +INTRINSIC_XED_IFORM_LWPVAL_GPRyy_GPR32d_IMMd VL128 int w y - int r y + i32 r d + i32 r d INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq VL128 @@ -10010,6 +10335,7 @@ VL128 f32 r dq f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb VL128 @@ -10017,6 +10343,7 @@ VL128 f32 r dq f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb VL256 @@ -10024,6 +10351,7 @@ VL256 f32 r qq f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb VL256 @@ -10031,6 +10359,7 @@ VL256 f32 r qq f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb VL128 @@ -10038,6 +10367,7 @@ VL128 f32 r dq f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb VL256 @@ -10045,6 +10375,7 @@ VL256 f32 r qq f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb VL128 @@ -10052,6 +10383,7 @@ VL128 f64 r dq f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb VL128 @@ -10059,6 +10391,7 @@ VL128 f64 r dq f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb VL256 @@ -10066,6 +10399,7 @@ VL256 f64 r qq f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb VL256 @@ -10073,6 +10407,7 @@ VL256 f64 r qq f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb VL128 @@ -10080,6 +10415,7 @@ VL128 f64 r dq f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb VL256 @@ -10087,6 +10423,7 @@ VL256 f64 r qq f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq VL128 @@ -10305,116 +10642,136 @@ VL128 f64 w dq f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb VL128 f64 w dq f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb VL256 f64 w qq f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb VL256 f64 w qq f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb VL128 f32 w dq f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb VL128 f32 w dq f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb VL256 f32 w qq f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb VL256 f32 w qq f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb VL128 f64 w dq f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb VL128 f64 w dq f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb VL256 f64 w qq f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb VL256 f64 w qq f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb VL128 f32 w dq f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb VL128 f32 w dq f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb VL256 f32 w qq f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb VL256 f32 w qq f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb f64 w dq f64 r dq f64 r q + u8 r b INTRINSIC_XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb f64 w dq f64 r dq f64 r q + u8 r b INTRINSIC_XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb f32 w dq f32 r dq f32 r d + u8 r b INTRINSIC_XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb f32 w dq f32 r dq f32 r d + u8 r b INTRINSIC_XED_IFORM_VCOMISD_XMMq_MEMq f64 r q @@ -10792,57 +11149,67 @@ INTRINSIC_XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb VL256 f64 w dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb VL256 f64 w dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb VL128 f64 w dq f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb VL128 f64 w dq f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb VL128 f32 w dq f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb VL128 f32 w dq f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb VL256 f32 w qq f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb VL256 f32 w qq f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb VL128 f32 w d f32 r dq + u8 r b INTRINSIC_XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb VL128 - INVALID w GPR32_B + INVALID w VGPR32_B f32 r dq + u8 r b INTRINSIC_XED_IFORM_VZEROALL VL256 @@ -10974,21 +11341,25 @@ INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb VL128 f64 w dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb VL128 f64 w dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb VL256 f64 w qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb VL256 f64 w qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq VL128 @@ -11018,33 +11389,39 @@ INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb VL128 f32 w dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb VL128 f32 w dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb VL256 f32 w qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb VL256 f32 w qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb VL256 f64 w qq f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb VL256 f64 w qq f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VBROADCASTSS_XMMdq_MEMd VL128 @@ -11086,24 +11463,28 @@ VL256 f64 w qq f64 r qq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb VL256 f64 w qq f64 r qq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb VL128 f32 w dq f32 r dq f32 r d + u8 r b INTRINSIC_XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb VL128 f32 w dq f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VLDDQU_XMMdq_MEMdq VL128 @@ -11516,10 +11897,10 @@ VL128 f64 w dq f64 r q -INTRINSIC_XED_IFORM_VMOVDDUP_XMMdq_XMMdq +INTRINSIC_XED_IFORM_VMOVDDUP_XMMdq_XMMq VL128 f64 w dq - f64 r dq + f64 r q INTRINSIC_XED_IFORM_VMOVDDUP_YMMqq_MEMqq VL256 @@ -11821,61 +12202,73 @@ INTRINSIC_XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb VL128 i32 w dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb VL128 i32 w dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb VL256 u32 w qq u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb VL256 u32 w qq u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb VL128 i32 w dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb VL128 i32 w dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb VL256 u16 w qq u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb VL256 u16 w qq u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb VL128 i32 w dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb VL128 i32 w dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb VL256 u16 w qq u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb VL256 u16 w qq u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq VL128 @@ -11989,6 +12382,7 @@ INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb VL128 u16 w dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq VL256 @@ -12006,6 +12400,7 @@ INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb VL256 u16 w qq u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq VL128 @@ -12023,6 +12418,7 @@ INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb VL128 u32 w dq u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq VL256 @@ -12040,6 +12436,7 @@ INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb VL256 u32 w qq u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq VL128 @@ -12057,6 +12454,7 @@ INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb VL128 u64 w dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq VL256 @@ -12074,6 +12472,7 @@ INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb VL256 u64 w qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq VL128 @@ -12091,6 +12490,7 @@ INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb VL128 u16 w dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq VL256 @@ -12108,6 +12508,7 @@ INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb VL256 u16 w qq u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq VL128 @@ -12125,6 +12526,7 @@ INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb VL128 u32 w dq u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq VL256 @@ -12142,6 +12544,7 @@ INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb VL256 u32 w qq u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq VL128 @@ -12159,6 +12562,7 @@ INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb VL128 u64 w dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq VL256 @@ -12176,6 +12580,7 @@ INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb VL256 u64 w qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq VL128 @@ -12193,6 +12598,7 @@ INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb VL128 i16 w dq i16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq VL256 @@ -12210,6 +12616,7 @@ INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb VL256 i16 w qq i16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq VL128 @@ -12227,6 +12634,7 @@ INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb VL128 i32 w dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq VL256 @@ -12244,6 +12652,7 @@ INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb VL256 i32 w qq i32 r qq + u8 r b INTRINSIC_XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq VL128 @@ -13497,21 +13906,25 @@ INTRINSIC_XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb VL128 u128 w dq u128 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb VL256 u128 w qq u128 r qq + u8 r b INTRINSIC_XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb VL128 u128 w dq u128 r dq + u8 r b INTRINSIC_XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb VL256 u128 w qq u128 r qq + u8 r b INTRINSIC_XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq VL128 @@ -13530,156 +13943,184 @@ VL128 u8 w dq u8 r dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb VL128 u8 w dq u8 r dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb VL256 u8 w qq u8 r qq u8 r qq + u8 r b INTRINSIC_XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb VL256 u8 w qq u8 r qq u8 r qq + u8 r b INTRINSIC_XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb VL128 u16 w dq u16 r dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb VL128 u16 w dq u16 r dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb VL256 u16 w qq u16 r qq u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb VL256 u16 w qq u16 r qq u16 r qq + u8 r b INTRINSIC_XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb VL128 f64 w dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb VL128 f64 w dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb VL256 f64 w qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb VL256 f64 w qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb VL128 f32 w dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb VL128 f32 w dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb VL256 f32 w qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb VL256 f32 w qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb f64 w dq f64 r dq f64 r q + u8 r b INTRINSIC_XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb f64 w dq f64 r dq f64 r q + u8 r b INTRINSIC_XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb f32 w dq f32 r dq f32 r d + u8 r b INTRINSIC_XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb f32 w dq f32 r dq f32 r d + u8 r b INTRINSIC_XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb VL128 f64 w dq f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb VL128 f64 w dq f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb VL256 f64 w qq f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb VL256 f64 w qq f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb VL128 f32 w dq f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb VL128 f32 w dq f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb VL256 f32 w qq f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb VL256 f32 w qq f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VRCPPS_XMMdq_MEMdq VL128 @@ -14374,24 +14815,28 @@ VL128 u16 w dq u8 r dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb VL128 u16 w dq u8 r dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb VL256 u16 w qq u8 r qq u8 r qq + u8 r b INTRINSIC_XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb VL256 u16 w qq u8 r qq u8 r qq + u8 r b INTRINSIC_XED_IFORM_VUCOMISD_XMMdq_MEMq f64 r dq @@ -14943,165 +15388,173 @@ INTRINSIC_XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb VL128 u8 w b u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb VL128 i32 w d u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb VL128 i16 w w u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15 VL128 i32 w d u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5 VL128 i32 w d u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb VL128 i64 w q u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb VL128 i64 w q u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb VL128 i32 w d u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb VL128 i32 w d u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb VL128 u8 w dq u8 r dq u8 r b + u8 r b INTRINSIC_XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb VL128 u8 w dq u8 r dq u8 r d + u8 r b INTRINSIC_XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb VL128 u16 w dq u16 r dq u16 r w + u8 r b INTRINSIC_XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb VL128 u16 w dq u16 r dq u16 r d + u8 r b INTRINSIC_XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb VL128 u32 w dq u32 r dq u32 r d + u8 r b INTRINSIC_XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb VL128 u32 w dq u32 r dq u32 r d + u8 r b INTRINSIC_XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb VL128 u64 w dq u64 r dq u64 r q + u8 r b INTRINSIC_XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb VL128 u64 w dq u64 r dq u64 r q + u8 r b INTRINSIC_XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb VL128 i32 r dq i32 r dq - INVALID r XED_REG_EAX - INVALID r XED_REG_EDX - INVALID w XED_REG_ECX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb VL128 i32 r dq i32 r dq - INVALID r XED_REG_EAX - INVALID r XED_REG_EDX - INVALID w XED_REG_ECX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb VL128 i32 r dq i32 r dq - INVALID r XED_REG_RAX - INVALID r XED_REG_RDX - INVALID w XED_REG_RCX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb VL128 i32 r dq i32 r dq - INVALID r XED_REG_RAX - INVALID r XED_REG_RDX - INVALID w XED_REG_RCX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb VL128 i32 r dq i32 r dq - INVALID w XED_REG_ECX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb VL128 i32 r dq i32 r dq - INVALID w XED_REG_ECX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb VL128 i32 r dq i32 r dq - INVALID w XED_REG_RCX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb VL128 i32 r dq i32 r dq - INVALID w XED_REG_RCX + u8 r b INVALID w rFLAGS INTRINSIC_XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb VL128 i32 r dq i32 r dq - INVALID r XED_REG_EAX - INVALID r XED_REG_EDX + u8 r b i32 w dq INVALID w rFLAGS @@ -15109,8 +15562,7 @@ INTRINSIC_XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb VL128 i32 r dq i32 r dq - INVALID r XED_REG_EAX - INVALID r XED_REG_EDX + u8 r b i32 w dq INVALID w rFLAGS @@ -15118,8 +15570,7 @@ INTRINSIC_XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb VL128 i32 r dq i32 r dq - INVALID r XED_REG_RAX - INVALID r XED_REG_RDX + u8 r b i32 w dq INVALID w rFLAGS @@ -15127,8 +15578,7 @@ INTRINSIC_XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb VL128 i32 r dq i32 r dq - INVALID r XED_REG_RAX - INVALID r XED_REG_RDX + u8 r b i32 w dq INVALID w rFLAGS @@ -15136,6 +15586,7 @@ INTRINSIC_XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb VL128 i32 r dq i32 r dq + u8 r b i32 w dq INVALID w rFLAGS @@ -15143,24 +15594,25 @@ INTRINSIC_XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb VL128 i32 r dq i32 r dq + u8 r b i32 w dq INVALID w rFLAGS -INTRINSIC_XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq +INTRINSIC_XED_IFORM_VMASKMOVDQU_XMMxub_XMMxub VL128 - u8 r dq - u8 r dq - u8 w dq + u8 r xub + u8 r xub + u8 w xub + INVALID r ArDI + INVALID r FINAL_DSEG INTRINSIC_XED_IFORM_VLDMXCSR_MEMd VL128 i32 r d - INVALID w XED_REG_MXCSR INTRINSIC_XED_IFORM_VSTMXCSR_MEMd VL128 i32 w d - INVALID r XED_REG_MXCSR INTRINSIC_XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq VL128 @@ -15290,11 +15742,13 @@ INTRINSIC_XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb VL128 i32 w dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb VL128 i32 w dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq VL128 @@ -15407,24 +15861,28 @@ VL128 u128 w dq u64 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb VL128 u128 w dq u64 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 VL256 u128 w qq u64 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 VL256 u128 w qq u64 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VCVTPH2PS_XMMdq_MEMq VL128 @@ -15450,21 +15908,25 @@ INTRINSIC_XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb VL128 f16 w q f32 r dq + u8 r b INTRINSIC_XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb VL128 f16 w q f32 r dq + u8 r b INTRINSIC_XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb VL256 f16 w dq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb VL256 f16 w dq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq VL128 @@ -16671,22 +17133,26 @@ VL256 u128 w qq u128 r qq u128 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb VL256 u128 w qq u128 r qq u128 r dq + u8 r b INTRINSIC_XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb VL256 u128 w dq u128 r qq + u8 r b INTRINSIC_XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb VL256 u128 w dq u128 r qq + u8 r b INTRINSIC_XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq VL128 @@ -16741,32 +17207,38 @@ VL256 u128 w qq u128 r qq u128 r qq + u8 r b INTRINSIC_XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb VL256 u128 w qq u128 r qq u128 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb VL256 u64 w qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb VL256 u64 w qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb VL256 f64 w qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb VL256 f64 w qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq VL256 @@ -16797,24 +17269,28 @@ VL128 u32 w dq u32 r dq u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb VL128 u32 w dq u32 r dq u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb VL256 u32 w qq u32 r qq u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb VL256 u32 w qq u32 r qq u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPBROADCASTB_XMMdq_MEMb VL128 @@ -17021,329 +17497,329 @@ VL256 i32 r qq i32 r qq -INTRINSIC_XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd +INTRINSIC_XED_IFORM_PDEP_GPR32d_GPR32d_MEMd VL128 i32 w d i32 r d i32 r d -INTRINSIC_XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d +INTRINSIC_XED_IFORM_PDEP_GPR32d_GPR32d_GPR32d VL128 i32 w d i32 r d i32 r d -INTRINSIC_XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq +INTRINSIC_XED_IFORM_PDEP_GPR64q_GPR64q_MEMq VL128 i64 w q i64 r q i64 r q -INTRINSIC_XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q +INTRINSIC_XED_IFORM_PDEP_GPR64q_GPR64q_GPR64q VL128 i64 w q i64 r q i64 r q -INTRINSIC_XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd +INTRINSIC_XED_IFORM_PEXT_GPR32d_GPR32d_MEMd VL128 i32 w d i32 r d i32 r d -INTRINSIC_XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d +INTRINSIC_XED_IFORM_PEXT_GPR32d_GPR32d_GPR32d VL128 i32 w d i32 r d i32 r d -INTRINSIC_XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq +INTRINSIC_XED_IFORM_PEXT_GPR64q_GPR64q_MEMq VL128 i64 w q i64 r q i64 r q -INTRINSIC_XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q +INTRINSIC_XED_IFORM_PEXT_GPR64q_GPR64q_GPR64q VL128 i64 w q i64 r q i64 r q -INTRINSIC_XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd +INTRINSIC_XED_IFORM_ANDN_GPR32d_GPR32d_MEMd VL128 i32 w d i32 r d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d +INTRINSIC_XED_IFORM_ANDN_GPR32d_GPR32d_GPR32d VL128 i32 w d i32 r d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq +INTRINSIC_XED_IFORM_ANDN_GPR64q_GPR64q_MEMq VL128 i64 w q i64 r q i64 r q INVALID w rFLAGS -INTRINSIC_XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q +INTRINSIC_XED_IFORM_ANDN_GPR64q_GPR64q_GPR64q VL128 i64 w q i64 r q i64 r q INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSR_VGPR32d_MEMd +INTRINSIC_XED_IFORM_BLSR_GPR32d_MEMd VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSR_VGPR32d_VGPR32d +INTRINSIC_XED_IFORM_BLSR_GPR32d_GPR32d VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSR_VGPR64q_MEMq +INTRINSIC_XED_IFORM_BLSR_GPR64q_MEMq VL128 i64 w q i64 r q INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSR_VGPR64q_VGPR64q +INTRINSIC_XED_IFORM_BLSR_GPR64q_GPR64q VL128 i64 w q i64 r q INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSMSK_VGPR32d_MEMd +INTRINSIC_XED_IFORM_BLSMSK_GPR32d_MEMd VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSMSK_VGPR32d_VGPR32d +INTRINSIC_XED_IFORM_BLSMSK_GPR32d_GPR32d VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSMSK_VGPR64q_MEMq +INTRINSIC_XED_IFORM_BLSMSK_GPR64q_MEMq VL128 i64 w q i64 r q INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSMSK_VGPR64q_VGPR64q +INTRINSIC_XED_IFORM_BLSMSK_GPR64q_GPR64q VL128 i64 w q i64 r q INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSI_VGPR32d_MEMd +INTRINSIC_XED_IFORM_BLSI_GPR32d_MEMd VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSI_VGPR32d_VGPR32d +INTRINSIC_XED_IFORM_BLSI_GPR32d_GPR32d VL128 i32 w d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSI_VGPR64q_MEMq +INTRINSIC_XED_IFORM_BLSI_GPR64q_MEMq VL128 i64 w q i64 r q INVALID w rFLAGS -INTRINSIC_XED_IFORM_BLSI_VGPR64q_VGPR64q +INTRINSIC_XED_IFORM_BLSI_GPR64q_GPR64q VL128 i64 w q i64 r q INVALID w rFLAGS -INTRINSIC_XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d +INTRINSIC_XED_IFORM_BZHI_GPR32d_MEMd_GPR32d VL128 i32 w d i32 r d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d +INTRINSIC_XED_IFORM_BZHI_GPR32d_GPR32d_GPR32d VL128 i32 w d i32 r d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q +INTRINSIC_XED_IFORM_BZHI_GPR64q_MEMq_GPR64q VL128 i64 w q i64 r q i64 r q INVALID w rFLAGS -INTRINSIC_XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q +INTRINSIC_XED_IFORM_BZHI_GPR64q_GPR64q_GPR64q VL128 i64 w q i64 r q i64 r q INVALID w rFLAGS -INTRINSIC_XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d +INTRINSIC_XED_IFORM_BEXTR_GPR32d_MEMd_GPR32d VL128 i32 w d i32 r d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d +INTRINSIC_XED_IFORM_BEXTR_GPR32d_GPR32d_GPR32d VL128 i32 w d i32 r d i32 r d INVALID w rFLAGS -INTRINSIC_XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q +INTRINSIC_XED_IFORM_BEXTR_GPR64q_MEMq_GPR64q VL128 i64 w q i64 r q i64 r q INVALID w rFLAGS -INTRINSIC_XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q +INTRINSIC_XED_IFORM_BEXTR_GPR64q_GPR64q_GPR64q VL128 i64 w q i64 r q i64 r q INVALID w rFLAGS -INTRINSIC_XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d +INTRINSIC_XED_IFORM_SHLX_GPR32d_MEMd_GPR32d VL128 i32 w d i32 r d i32 r d -INTRINSIC_XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d +INTRINSIC_XED_IFORM_SHLX_GPR32d_GPR32d_GPR32d VL128 i32 w d i32 r d i32 r d -INTRINSIC_XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q +INTRINSIC_XED_IFORM_SHLX_GPR64q_MEMq_GPR64q VL128 i64 w q i64 r q i64 r q -INTRINSIC_XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q +INTRINSIC_XED_IFORM_SHLX_GPR64q_GPR64q_GPR64q VL128 i64 w q i64 r q i64 r q -INTRINSIC_XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d +INTRINSIC_XED_IFORM_SARX_GPR32d_MEMd_GPR32d VL128 i32 w d i32 r d i32 r d -INTRINSIC_XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d +INTRINSIC_XED_IFORM_SARX_GPR32d_GPR32d_GPR32d VL128 i32 w d i32 r d i32 r d -INTRINSIC_XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q +INTRINSIC_XED_IFORM_SARX_GPR64q_MEMq_GPR64q VL128 i64 w q i64 r q i64 r q -INTRINSIC_XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q +INTRINSIC_XED_IFORM_SARX_GPR64q_GPR64q_GPR64q VL128 i64 w q i64 r q i64 r q -INTRINSIC_XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d +INTRINSIC_XED_IFORM_SHRX_GPR32d_MEMd_GPR32d VL128 i32 w d i32 r d i32 r d -INTRINSIC_XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d +INTRINSIC_XED_IFORM_SHRX_GPR32d_GPR32d_GPR32d VL128 i32 w d i32 r d i32 r d -INTRINSIC_XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q +INTRINSIC_XED_IFORM_SHRX_GPR64q_MEMq_GPR64q VL128 i64 w q i64 r q i64 r q -INTRINSIC_XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q +INTRINSIC_XED_IFORM_SHRX_GPR64q_GPR64q_GPR64q VL128 i64 w q i64 r q i64 r q -INTRINSIC_XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d +INTRINSIC_XED_IFORM_MULX_GPR32d_GPR32d_GPR32d VL128 i32 w d i32 w d i32 r d - INVALID r XED_REG_EDX -INTRINSIC_XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd +INTRINSIC_XED_IFORM_MULX_GPR32d_GPR32d_MEMd VL128 i32 w d i32 w d i32 r d - INVALID r XED_REG_EDX -INTRINSIC_XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q +INTRINSIC_XED_IFORM_MULX_GPR64q_GPR64q_GPR64q VL128 i64 w q i64 w q i64 r q - INVALID r XED_REG_RDX -INTRINSIC_XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq +INTRINSIC_XED_IFORM_MULX_GPR64q_GPR64q_MEMq VL128 i64 w q i64 w q i64 r q - INVALID r XED_REG_RDX -INTRINSIC_XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb +INTRINSIC_XED_IFORM_RORX_GPR32d_GPR32d_IMMb VL128 i32 w d i32 r d + u8 r b -INTRINSIC_XED_IFORM_RORX_VGPR32d_MEMd_IMMb +INTRINSIC_XED_IFORM_RORX_GPR32d_MEMd_IMMb VL128 i32 w d i32 r d + u8 r b -INTRINSIC_XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb +INTRINSIC_XED_IFORM_RORX_GPR64q_GPR64q_IMMb VL128 i64 w q i64 r q + u8 r b -INTRINSIC_XED_IFORM_RORX_VGPR64q_MEMq_IMMb +INTRINSIC_XED_IFORM_RORX_GPR64q_MEMq_IMMb VL128 i64 w q i64 r q + u8 r b INTRINSIC_XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 VL256 @@ -17403,11 +17879,13 @@ INTRINSIC_XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 VL128 i1 w mskw i1 r mskw + u8 r b INTRINSIC_XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 VL128 i1 w mskw i1 r mskw + u8 r b INTRINSIC_XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 VL256 @@ -17617,31 +18095,37 @@ INTRINSIC_XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 VL128 i1 w mskw i1 r mskw + u8 r b INTRINSIC_XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 VL128 i1 w mskw i1 r mskw + u8 r b INTRINSIC_XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 VL128 i1 w mskw i1 r mskw + u8 r b INTRINSIC_XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 VL128 i1 w mskw i1 r mskw + u8 r b INTRINSIC_XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 VL128 i1 w mskw i1 r mskw + u8 r b INTRINSIC_XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 VL128 i1 w mskw i1 r mskw + u8 r b INTRINSIC_XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512 VL128 @@ -17720,48 +18204,56 @@ VL128 u8 w dq u8 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 VL128 u8 w dq u8 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 VL256 u8 w qq u8 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 VL256 u8 w qq u8 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 VL128 u8 w dq u8 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 VL128 u8 w dq u8 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 VL256 u8 w qq u8 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 VL256 u8 w qq u8 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8 VL128 @@ -17787,6 +18279,932 @@ VL256 u8 r qq u8 r qq +INTRINSIC_XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32 +VL128 + i32 rw dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32 +VL128 + i32 rw dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32 +VL256 + i32 rw qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32 +VL256 + i32 rw qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32 +VL128 + i32 rw dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32 +VL128 + i32 rw dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32 +VL256 + i32 rw qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32 +VL256 + i32 rw qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32 +VL128 + i32 rw dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32 +VL128 + i32 rw dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32 +VL256 + i32 rw qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32 +VL256 + i32 rw qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32 +VL128 + i32 rw dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32 +VL128 + i32 rw dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32 +VL256 + i32 rw qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32 +VL256 + i32 rw qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_LDTILECFG_MEM +VL128 + struct r m512 + +INTRINSIC_XED_IFORM_STTILECFG_MEM +VL128 + struct w m512 + +INTRINSIC_XED_IFORM_TDPBF16PS_TMMf32_TMM2bf16_TMM2bf16 +VL128 + f32 rw tv + 2bf16 r tv + 2bf16 r tv + +INTRINSIC_XED_IFORM_TDPBSSD_TMMi32_TMM4i8_TMM4i8 +VL128 + i32 rw tv + 4i8 r tv + 4i8 r tv + +INTRINSIC_XED_IFORM_TDPBSUD_TMMi32_TMM4i8_TMM4u8 +VL128 + i32 rw tv + 4i8 r tv + 4u8 r tv + +INTRINSIC_XED_IFORM_TDPBUSD_TMMi32_TMM4u8_TMM4i8 +VL128 + i32 rw tv + 4u8 r tv + 4i8 r tv + +INTRINSIC_XED_IFORM_TDPBUUD_TMMu32_TMM4u8_TMM4u8 +VL128 + u32 rw tv + 4u8 r tv + 4u8 r tv + +INTRINSIC_XED_IFORM_TILELOADD_TMMu32_MEMu32 +VL128 + u32 w tv + u32 r ptr + +INTRINSIC_XED_IFORM_TILELOADDT1_TMMu32_MEMu32 +VL128 + u32 w tv + u32 r ptr + +INTRINSIC_XED_IFORM_TILERELEASE +VL128 + +INTRINSIC_XED_IFORM_TILESTORED_MEMu32_TMMu32 +VL128 + u32 w ptr + u32 r tv + +INTRINSIC_XED_IFORM_TILEZERO_TMMu32 +VL128 + u32 w tv + +INTRINSIC_XED_IFORM_TDPFP16PS_TMMf32_TMM2f16_TMM2f16 +VL128 + f32 rw tv + 2f16 r tv + 2f16 r tv + +INTRINSIC_XED_IFORM_TCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16 +VL128 + f32 rw tv + 2f16 r tv + 2f16 r tv + +INTRINSIC_XED_IFORM_TCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16 +VL128 + f32 rw tv + 2f16 r tv + 2f16 r tv + +INTRINSIC_XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_XMMu64 +VL128 + u64 rw dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_MEMu64 +VL128 + u64 rw dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_YMMu64 +VL256 + u64 rw qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_MEMu64 +VL256 + u64 rw qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_XMMu64 +VL128 + u64 rw dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_MEMu64 +VL128 + u64 rw dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_YMMu64 +VL256 + u64 rw qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_MEMu64 +VL256 + u64 rw qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VBCSTNEBF162PS_XMMf32_MEMbf16 +VL128 + f32 w dq + bf16 r wrd + +INTRINSIC_XED_IFORM_VBCSTNEBF162PS_YMMf32_MEMbf16 +VL256 + f32 w qq + bf16 r wrd + +INTRINSIC_XED_IFORM_VBCSTNESH2PS_XMMf32_MEMf16 +VL128 + f32 w dq + f16 r wrd + +INTRINSIC_XED_IFORM_VBCSTNESH2PS_YMMf32_MEMf16 +VL256 + f32 w qq + f16 r wrd + +INTRINSIC_XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16 +VL128 + f32 w dq + 2bf16 r dq + +INTRINSIC_XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16 +VL256 + f32 w qq + 2bf16 r qq + +INTRINSIC_XED_IFORM_VCVTNEEPH2PS_XMMf32_MEM2f16 +VL128 + f32 w dq + 2f16 r dq + +INTRINSIC_XED_IFORM_VCVTNEEPH2PS_YMMf32_MEM2f16 +VL256 + f32 w qq + 2f16 r qq + +INTRINSIC_XED_IFORM_VCVTNEOBF162PS_XMMf32_MEM2bf16 +VL128 + f32 w dq + 2bf16 r dq + +INTRINSIC_XED_IFORM_VCVTNEOBF162PS_YMMf32_MEM2bf16 +VL256 + f32 w qq + 2bf16 r qq + +INTRINSIC_XED_IFORM_VCVTNEOPH2PS_XMMf32_MEM2f16 +VL128 + f32 w dq + 2f16 r dq + +INTRINSIC_XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16 +VL256 + f32 w qq + 2f16 r qq + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_XMMf32 +VL128 + bf16 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL128 +VL128 + bf16 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_YMMf32 +VL256 + bf16 w dq + f32 r qq + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL256 +VL256 + bf16 w dq + f32 r qq + +INTRINSIC_XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_XMM4i8 +VL128 + i32 rw dq + 4i8 r dq + 4i8 r dq + +INTRINSIC_XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_MEM4i8 +VL128 + i32 rw dq + 4i8 r dq + 4i8 r dq + +INTRINSIC_XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_YMM4i8 +VL256 + i32 rw qq + 4i8 r qq + 4i8 r qq + +INTRINSIC_XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_MEM4i8 +VL256 + i32 rw qq + 4i8 r qq + 4i8 r qq + +INTRINSIC_XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_XMM4i8 +VL128 + i32 rw dq + 4i8 r dq + 4i8 r dq + +INTRINSIC_XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_MEM4i8 +VL128 + i32 rw dq + 4i8 r dq + 4i8 r dq + +INTRINSIC_XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_YMM4i8 +VL256 + i32 rw qq + 4i8 r qq + 4i8 r qq + +INTRINSIC_XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_MEM4i8 +VL256 + i32 rw qq + 4i8 r qq + 4i8 r qq + +INTRINSIC_XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_XMM4u8 +VL128 + i32 rw dq + 4i8 r dq + 4u8 r dq + +INTRINSIC_XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_MEM4u8 +VL128 + i32 rw dq + 4i8 r dq + 4u8 r dq + +INTRINSIC_XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_YMM4u8 +VL256 + i32 rw qq + 4i8 r qq + 4u8 r qq + +INTRINSIC_XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_MEM4u8 +VL256 + i32 rw qq + 4i8 r qq + 4u8 r qq + +INTRINSIC_XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_XMM4u8 +VL128 + i32 rw dq + 4i8 r dq + 4u8 r dq + +INTRINSIC_XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_MEM4u8 +VL128 + i32 rw dq + 4i8 r dq + 4u8 r dq + +INTRINSIC_XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_YMM4u8 +VL256 + i32 rw qq + 4i8 r qq + 4u8 r qq + +INTRINSIC_XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_MEM4u8 +VL256 + i32 rw qq + 4i8 r qq + 4u8 r qq + +INTRINSIC_XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_XMM4u8 +VL128 + u32 rw dq + 4u8 r dq + 4u8 r dq + +INTRINSIC_XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_MEM4u8 +VL128 + u32 rw dq + 4u8 r dq + 4u8 r dq + +INTRINSIC_XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_YMM4u8 +VL256 + u32 rw qq + 4u8 r qq + 4u8 r qq + +INTRINSIC_XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_MEM4u8 +VL256 + u32 rw qq + 4u8 r qq + 4u8 r qq + +INTRINSIC_XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_XMM4u8 +VL128 + u32 rw dq + 4u8 r dq + 4u8 r dq + +INTRINSIC_XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_MEM4u8 +VL128 + u32 rw dq + 4u8 r dq + 4u8 r dq + +INTRINSIC_XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_YMM4u8 +VL256 + u32 rw qq + 4u8 r qq + 4u8 r qq + +INTRINSIC_XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_MEM4u8 +VL256 + u32 rw qq + 4u8 r qq + 4u8 r qq + +INTRINSIC_XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32 +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64 +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_URDMSR_GPR64u64_IMM32 +VL128 + u64 w q + i32 r d + +INTRINSIC_XED_IFORM_UWRMSR_IMM32_GPR64u64 +VL128 + i32 r d + u64 r q + +INTRINSIC_XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_XMM2u16 +VL128 + i32 rw dq + 2i16 r dq + 2u16 r dq + +INTRINSIC_XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_MEM2u16 +VL128 + i32 rw dq + 2i16 r dq + 2u16 r dq + +INTRINSIC_XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_YMM2u16 +VL256 + i32 rw qq + 2i16 r qq + 2u16 r qq + +INTRINSIC_XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_MEM2u16 +VL256 + i32 rw qq + 2i16 r qq + 2u16 r qq + +INTRINSIC_XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_XMM2u16 +VL128 + i32 rw dq + 2i16 r dq + 2u16 r dq + +INTRINSIC_XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_MEM2u16 +VL128 + i32 rw dq + 2i16 r dq + 2u16 r dq + +INTRINSIC_XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_YMM2u16 +VL256 + i32 rw qq + 2i16 r qq + 2u16 r qq + +INTRINSIC_XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_MEM2u16 +VL256 + i32 rw qq + 2i16 r qq + 2u16 r qq + +INTRINSIC_XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_XMM2i16 +VL128 + i32 rw dq + 2u16 r dq + 2i16 r dq + +INTRINSIC_XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_MEM2i16 +VL128 + i32 rw dq + 2u16 r dq + 2i16 r dq + +INTRINSIC_XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_YMM2i16 +VL256 + i32 rw qq + 2u16 r qq + 2i16 r qq + +INTRINSIC_XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_MEM2i16 +VL256 + i32 rw qq + 2u16 r qq + 2i16 r qq + +INTRINSIC_XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_XMM2i16 +VL128 + i32 rw dq + 2u16 r dq + 2i16 r dq + +INTRINSIC_XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_MEM2i16 +VL128 + i32 rw dq + 2u16 r dq + 2i16 r dq + +INTRINSIC_XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_YMM2i16 +VL256 + i32 rw qq + 2u16 r qq + 2i16 r qq + +INTRINSIC_XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_MEM2i16 +VL256 + i32 rw qq + 2u16 r qq + 2i16 r qq + +INTRINSIC_XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_XMM2u16 +VL128 + u32 rw dq + 2u16 r dq + 2u16 r dq + +INTRINSIC_XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_MEM2u16 +VL128 + u32 rw dq + 2u16 r dq + 2u16 r dq + +INTRINSIC_XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_YMM2u16 +VL256 + u32 rw qq + 2u16 r qq + 2u16 r qq + +INTRINSIC_XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_MEM2u16 +VL256 + u32 rw qq + 2u16 r qq + 2u16 r qq + +INTRINSIC_XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_XMM2u16 +VL128 + u32 rw dq + 2u16 r dq + 2u16 r dq + +INTRINSIC_XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_MEM2u16 +VL128 + u32 rw dq + 2u16 r dq + 2u16 r dq + +INTRINSIC_XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_YMM2u16 +VL256 + u32 rw qq + 2u16 r qq + 2u16 r qq + +INTRINSIC_XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_MEM2u16 +VL256 + u32 rw qq + 2u16 r qq + 2u16 r qq + +INTRINSIC_XED_IFORM_VSHA512MSG1_YMMu64_XMMu64 +VL256 + u64 rw qq + u64 r dq + +INTRINSIC_XED_IFORM_VSHA512MSG2_YMMu64_YMMu64 +VL256 + u64 rw qq + u64 r qq + +INTRINSIC_XED_IFORM_VSHA512RNDS2_YMMu64_YMMu64_XMMu64 +VL256 + u64 rw qq + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VSM3MSG1_XMMu32_XMMu32_XMMu32 +VL128 + u32 rw dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VSM3MSG1_XMMu32_XMMu32_MEMu32 +VL128 + u32 rw dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VSM3MSG2_XMMu32_XMMu32_XMMu32 +VL128 + u32 rw dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VSM3MSG2_XMMu32_XMMu32_MEMu32 +VL128 + u32 rw dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8 +VL128 + u32 rw dq + u32 r dq + u32 r dq + u8 r b + +INTRINSIC_XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_MEMu32_IMM8 +VL128 + u32 rw dq + u32 r dq + u32 r dq + u8 r b + +INTRINSIC_XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32 +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32 +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32 +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32 +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32 +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32 +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32 +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32 +VL256 + u32 w qq + u32 r qq + u32 r qq + INTRINSIC_XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 VL128 i32 rw dq @@ -18501,6 +19919,7 @@ VL512 i1 r mskw u32 r zu32 u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 VL512 @@ -18508,6 +19927,7 @@ VL512 i1 r mskw u32 r zu32 u32 r vv + u8 r b INTRINSIC_XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 VL128 @@ -18515,6 +19935,7 @@ VL128 i1 r mskw u32 r dq u32 r dq + u8 r b INTRINSIC_XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 VL128 @@ -18522,6 +19943,7 @@ VL128 i1 r mskw u32 r dq u32 r vv + u8 r b INTRINSIC_XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 VL256 @@ -18529,6 +19951,7 @@ VL256 i1 r mskw u32 r qq u32 r qq + u8 r b INTRINSIC_XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 VL256 @@ -18536,6 +19959,7 @@ VL256 i1 r mskw u32 r qq u32 r vv + u8 r b INTRINSIC_XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 VL512 @@ -18543,6 +19967,7 @@ VL512 i1 r mskw u64 r zu64 u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 VL512 @@ -18550,6 +19975,7 @@ VL512 i1 r mskw u64 r zu64 u64 r vv + u8 r b INTRINSIC_XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 VL128 @@ -18557,6 +19983,7 @@ VL128 i1 r mskw u64 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 VL128 @@ -18564,6 +19991,7 @@ VL128 i1 r mskw u64 r dq u64 r vv + u8 r b INTRINSIC_XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 VL256 @@ -18571,6 +19999,7 @@ VL256 i1 r mskw u64 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 VL256 @@ -18578,6 +20007,7 @@ VL256 i1 r mskw u64 r qq u64 r vv + u8 r b INTRINSIC_XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 VL512 @@ -18765,6 +20195,7 @@ VL512 i1 r mskw f64 r zf64 f64 r zf64 + u8 r b INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 VL512 @@ -18772,6 +20203,7 @@ VL512 i1 r mskw f64 r zf64 f64 r vv + u8 r b INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 VL128 @@ -18779,6 +20211,7 @@ VL128 i1 r mskw f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 VL128 @@ -18786,6 +20219,7 @@ VL128 i1 r mskw f64 r dq f64 r vv + u8 r b INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 VL256 @@ -18793,6 +20227,7 @@ VL256 i1 r mskw f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 VL256 @@ -18800,6 +20235,7 @@ VL256 i1 r mskw f64 r qq f64 r vv + u8 r b INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 VL512 @@ -18807,6 +20243,7 @@ VL512 i1 r mskw f32 r zf32 f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 VL512 @@ -18814,6 +20251,7 @@ VL512 i1 r mskw f32 r zf32 f32 r vv + u8 r b INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 VL128 @@ -18821,6 +20259,7 @@ VL128 i1 r mskw f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 VL128 @@ -18828,6 +20267,7 @@ VL128 i1 r mskw f32 r dq f32 r vv + u8 r b INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 VL256 @@ -18835,6 +20275,7 @@ VL256 i1 r mskw f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 VL256 @@ -18842,30 +20283,35 @@ VL256 i1 r mskw f32 r qq f32 r vv + u8 r b INTRINSIC_XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 i1 w mskw i1 r mskw f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 i1 w mskw i1 r mskw f64 r dq f64 r q + u8 r b INTRINSIC_XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 i1 w mskw i1 r mskw f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 i1 w mskw i1 r mskw f32 r dq f32 r d + u8 r b INTRINSIC_XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512 f64 r dq @@ -19252,36 +20698,42 @@ VL512 f16 w qq i1 r mskw f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 VL512 f16 w qq i1 r mskw f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 VL128 f16 w dq i1 r mskw f32 r dq + u8 r b INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 VL128 f16 w q i1 r mskw f32 r dq + u8 r b INTRINSIC_XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 VL256 f16 w dq i1 r mskw f32 r qq + u8 r b INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 VL256 f16 w dq i1 r mskw f32 r qq + u8 r b INTRINSIC_XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 VL512 @@ -19952,82 +21404,96 @@ VL512 f32 w dq i1 r mskw f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 VL512 f32 w dq i1 r mskw f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 VL256 f32 w dq i1 r mskw f32 r qq + u8 r b INTRINSIC_XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 VL256 f32 w dq i1 r mskw f32 r qq + u8 r b INTRINSIC_XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 VL512 f64 w qq i1 r mskw f64 r zf64 + u8 r b INTRINSIC_XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 VL512 f64 w qq i1 r mskw f64 r zf64 + u8 r b INTRINSIC_XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 VL512 u32 w dq i1 r mskw u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 VL512 u32 w dq i1 r mskw u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 VL256 u32 w dq i1 r mskw u32 r qq + u8 r b INTRINSIC_XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 VL256 u32 w dq i1 r mskw u32 r qq + u8 r b INTRINSIC_XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 VL512 u64 w qq i1 r mskw u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 VL512 u64 w qq i1 r mskw u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 VL128 f32 w d f32 r dq + u8 r b INTRINSIC_XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 VL128 f32 w d f32 r dq + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 VL512 @@ -20035,6 +21501,7 @@ VL512 i1 r mskw f64 r zf64 f64 r zf64 + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 VL512 @@ -20042,6 +21509,7 @@ VL512 i1 r mskw f64 r zf64 f64 r vv + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 VL128 @@ -20049,6 +21517,7 @@ VL128 i1 r mskw f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 VL128 @@ -20056,6 +21525,7 @@ VL128 i1 r mskw f64 r dq f64 r vv + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 VL256 @@ -20063,6 +21533,7 @@ VL256 i1 r mskw f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 VL256 @@ -20070,6 +21541,7 @@ VL256 i1 r mskw f64 r qq f64 r vv + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 VL512 @@ -20077,6 +21549,7 @@ VL512 i1 r mskw f32 r zf32 f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 VL512 @@ -20084,6 +21557,7 @@ VL512 i1 r mskw f32 r zf32 f32 r vv + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 VL128 @@ -20091,6 +21565,7 @@ VL128 i1 r mskw f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 VL128 @@ -20098,6 +21573,7 @@ VL128 i1 r mskw f32 r dq f32 r vv + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 VL256 @@ -20105,6 +21581,7 @@ VL256 i1 r mskw f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 VL256 @@ -20112,30 +21589,35 @@ VL256 i1 r mskw f32 r qq f32 r vv + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 f64 rw dq i1 r mskw f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 f64 rw dq i1 r mskw f64 r dq f64 r q + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 f32 rw dq i1 r mskw f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 f32 rw dq i1 r mskw f32 r dq f32 r d + u8 r b INTRINSIC_XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 VL512 @@ -22110,96 +23592,112 @@ VL512 f64 w zf64 i1 r mskw f64 r zf64 + u8 r b INTRINSIC_XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 VL512 f64 w zf64 i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 VL128 f64 w dq i1 r mskw f64 r dq + u8 r b INTRINSIC_XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 VL128 f64 w dq i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 VL256 f64 w qq i1 r mskw f64 r qq + u8 r b INTRINSIC_XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 VL256 f64 w qq i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 VL512 f32 w zf32 i1 r mskw f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 VL512 f32 w zf32 i1 r mskw f32 r vv + u8 r b INTRINSIC_XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 VL128 f32 w dq i1 r mskw f32 r dq + u8 r b INTRINSIC_XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 VL128 f32 w dq i1 r mskw f32 r vv + u8 r b INTRINSIC_XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 VL256 f32 w qq i1 r mskw f32 r qq + u8 r b INTRINSIC_XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 VL256 f32 w qq i1 r mskw f32 r vv + u8 r b INTRINSIC_XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 f64 w dq i1 r mskw f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 f64 w dq i1 r mskw f64 r dq f64 r q + u8 r b INTRINSIC_XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 f32 w dq i1 r mskw f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 f32 w dq i1 r mskw f32 r dq f32 r d + u8 r b INTRINSIC_XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 VL512 @@ -22207,6 +23705,7 @@ VL512 i1 r mskw f32 r zf32 f32 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 VL512 @@ -22214,6 +23713,7 @@ VL512 i1 r mskw f32 r zf32 f32 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 VL256 @@ -22221,6 +23721,7 @@ VL256 i1 r mskw f32 r qq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 VL256 @@ -22228,6 +23729,7 @@ VL256 i1 r mskw f32 r qq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 VL512 @@ -22235,6 +23737,7 @@ VL512 i1 r mskw f64 r zf64 f64 r qq + u8 r b INTRINSIC_XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 VL512 @@ -22242,6 +23745,7 @@ VL512 i1 r mskw f64 r zf64 f64 r qq + u8 r b INTRINSIC_XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 VL512 @@ -22249,6 +23753,7 @@ VL512 i1 r mskw u32 r zu32 u32 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 VL512 @@ -22256,6 +23761,7 @@ VL512 i1 r mskw u32 r zu32 u32 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 VL256 @@ -22263,6 +23769,7 @@ VL256 i1 r mskw u32 r qq u32 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 VL256 @@ -22270,6 +23777,7 @@ VL256 i1 r mskw u32 r qq u32 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 VL512 @@ -22277,6 +23785,7 @@ VL512 i1 r mskw u64 r zu64 u64 r qq + u8 r b INTRINSIC_XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 VL512 @@ -22284,18 +23793,21 @@ VL512 i1 r mskw u64 r zu64 u64 r qq + u8 r b INTRINSIC_XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 VL128 f32 w dq f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 VL128 f32 w dq f32 r dq f32 r d + u8 r b INTRINSIC_XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 VL512 @@ -23876,6 +25388,7 @@ VL512 i1 r mskw i32 r zi32 i32 r zi32 + u8 r b INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 VL512 @@ -23883,6 +25396,7 @@ VL512 i1 r mskw i32 r zi32 i32 r vv + u8 r b INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 VL128 @@ -23890,6 +25404,7 @@ VL128 i1 r mskw i32 r dq i32 r dq + u8 r b INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 VL128 @@ -23897,6 +25412,7 @@ VL128 i1 r mskw i32 r dq i32 r vv + u8 r b INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 VL256 @@ -23904,6 +25420,7 @@ VL256 i1 r mskw i32 r qq i32 r qq + u8 r b INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 VL256 @@ -23911,6 +25428,7 @@ VL256 i1 r mskw i32 r qq i32 r vv + u8 r b INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 VL512 @@ -24086,6 +25604,7 @@ VL512 i1 r mskw i64 r zi64 i64 r zi64 + u8 r b INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 VL512 @@ -24093,6 +25612,7 @@ VL512 i1 r mskw i64 r zi64 i64 r vv + u8 r b INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 VL128 @@ -24100,6 +25620,7 @@ VL128 i1 r mskw i64 r dq i64 r dq + u8 r b INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 VL128 @@ -24107,6 +25628,7 @@ VL128 i1 r mskw i64 r dq i64 r vv + u8 r b INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 VL256 @@ -24114,6 +25636,7 @@ VL256 i1 r mskw i64 r qq i64 r qq + u8 r b INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 VL256 @@ -24121,6 +25644,7 @@ VL256 i1 r mskw i64 r qq i64 r vv + u8 r b INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 VL512 @@ -24128,6 +25652,7 @@ VL512 i1 r mskw u32 r zu32 u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 VL512 @@ -24135,6 +25660,7 @@ VL512 i1 r mskw u32 r zu32 u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 VL128 @@ -24142,6 +25668,7 @@ VL128 i1 r mskw u32 r dq u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 VL128 @@ -24149,6 +25676,7 @@ VL128 i1 r mskw u32 r dq u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 VL256 @@ -24156,6 +25684,7 @@ VL256 i1 r mskw u32 r qq u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 VL256 @@ -24163,6 +25692,7 @@ VL256 i1 r mskw u32 r qq u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 VL512 @@ -24170,6 +25700,7 @@ VL512 i1 r mskw u64 r zu64 u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 VL512 @@ -24177,6 +25708,7 @@ VL512 i1 r mskw u64 r zu64 u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 VL128 @@ -24184,6 +25716,7 @@ VL128 i1 r mskw u64 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 VL128 @@ -24191,6 +25724,7 @@ VL128 i1 r mskw u64 r dq u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 VL256 @@ -24198,6 +25732,7 @@ VL256 i1 r mskw u64 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 VL256 @@ -24205,6 +25740,7 @@ VL256 i1 r mskw u64 r qq u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 VL512 @@ -24479,12 +26015,14 @@ VL512 f64 w zf64 i1 r mskw f64 r zf64 + u8 r b INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 VL512 f64 w zf64 i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 VL512 @@ -24505,12 +26043,14 @@ VL128 f64 w dq i1 r mskw f64 r dq + u8 r b INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 VL128 f64 w dq i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 VL128 @@ -24531,12 +26071,14 @@ VL256 f64 w qq i1 r mskw f64 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 VL256 f64 w qq i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 VL256 @@ -24557,12 +26099,14 @@ VL512 f32 w zf32 i1 r mskw f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 VL512 f32 w zf32 i1 r mskw f32 r vv + u8 r b INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 VL512 @@ -24583,12 +26127,14 @@ VL128 f32 w dq i1 r mskw f32 r dq + u8 r b INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 VL128 f32 w dq i1 r mskw f32 r vv + u8 r b INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 VL128 @@ -24609,12 +26155,14 @@ VL256 f32 w qq i1 r mskw f32 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 VL256 f32 w qq i1 r mskw f32 r vv + u8 r b INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 VL256 @@ -24635,12 +26183,14 @@ VL512 f64 w zf64 i1 r mskw f64 r zf64 + u8 r b INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 VL512 f64 w zf64 i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 VL512 @@ -24661,12 +26211,14 @@ VL256 f64 w qq i1 r mskw f64 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 VL256 f64 w qq i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 VL256 @@ -24715,12 +26267,14 @@ VL512 u64 w zu64 i1 r mskw u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL512 u64 w zu64 i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 VL512 @@ -24741,12 +26295,14 @@ VL256 u64 w qq i1 r mskw u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL256 u64 w qq i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 VL256 @@ -26525,72 +28081,84 @@ VL512 u32 w zu32 i1 r mskw u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL512 u32 w zu32 i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 VL128 u32 w dq i1 r mskw u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL128 u32 w dq i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 VL256 u32 w qq i1 r mskw u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL256 u32 w qq i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 VL512 u64 w zu64 i1 r mskw u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL512 u64 w zu64 i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 VL128 u64 w dq i1 r mskw u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL128 u64 w dq i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 VL256 u64 w qq i1 r mskw u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL256 u64 w qq i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 VL512 @@ -26681,72 +28249,84 @@ VL512 u32 w zu32 i1 r mskw u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL512 u32 w zu32 i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 VL128 u32 w dq i1 r mskw u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL128 u32 w dq i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 VL256 u32 w qq i1 r mskw u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL256 u32 w qq i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 VL512 u64 w zu64 i1 r mskw u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL512 u64 w zu64 i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 VL128 u64 w dq i1 r mskw u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL128 u64 w dq i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 VL256 u64 w qq i1 r mskw u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL256 u64 w qq i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 VL512 @@ -26909,36 +28489,42 @@ VL512 u32 w zu32 i1 r mskw u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL512 u32 w zu32 i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 VL128 u32 w dq i1 r mskw u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL128 u32 w dq i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 VL256 u32 w qq i1 r mskw u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL256 u32 w qq i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 VL512 @@ -26959,12 +28545,14 @@ VL512 u32 w zu32 i1 r mskw u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL512 u32 w zu32 i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 VL128 @@ -26985,12 +28573,14 @@ VL128 u32 w dq i1 r mskw u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL128 u32 w dq i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 VL256 @@ -27011,12 +28601,14 @@ VL256 u32 w qq i1 r mskw u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL256 u32 w qq i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 VL512 @@ -27037,12 +28629,14 @@ VL512 u64 w zu64 i1 r mskw u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL512 u64 w zu64 i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 VL128 @@ -27063,12 +28657,14 @@ VL128 u64 w dq i1 r mskw u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL128 u64 w dq i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 VL256 @@ -27089,12 +28685,14 @@ VL256 u64 w qq i1 r mskw u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL256 u64 w qq i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 VL512 @@ -27199,12 +28797,14 @@ VL512 u32 w zu32 i1 r mskw u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL512 u32 w zu32 i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 VL128 @@ -27225,12 +28825,14 @@ VL128 u32 w dq i1 r mskw u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL128 u32 w dq i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 VL256 @@ -27251,12 +28853,14 @@ VL256 u32 w qq i1 r mskw u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL256 u32 w qq i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 VL512 @@ -27277,12 +28881,14 @@ VL512 u64 w zu64 i1 r mskw u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL512 u64 w zu64 i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 VL128 @@ -27303,12 +28909,14 @@ VL128 u64 w dq i1 r mskw u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL128 u64 w dq i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 VL256 @@ -27329,12 +28937,14 @@ VL256 u64 w qq i1 r mskw u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL256 u64 w qq i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 VL512 @@ -27439,12 +29049,14 @@ VL512 u32 w zu32 i1 r mskw u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL512 u32 w zu32 i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 VL128 @@ -27465,12 +29077,14 @@ VL128 u32 w dq i1 r mskw u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL128 u32 w dq i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 VL256 @@ -27491,12 +29105,14 @@ VL256 u32 w qq i1 r mskw u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 VL256 u32 w qq i1 r mskw u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 VL512 @@ -27517,12 +29133,14 @@ VL512 u64 w zu64 i1 r mskw u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL512 u64 w zu64 i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 VL128 @@ -27543,12 +29161,14 @@ VL128 u64 w dq i1 r mskw u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL128 u64 w dq i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 VL256 @@ -27569,12 +29189,14 @@ VL256 u64 w qq i1 r mskw u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 VL256 u64 w qq i1 r mskw u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 VL512 @@ -27750,6 +29372,7 @@ VL512 i1 r mskw u32 r zu32 u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 VL512 @@ -27757,6 +29380,7 @@ VL512 i1 r mskw u32 r zu32 u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 VL128 @@ -27764,6 +29388,7 @@ VL128 i1 r mskw u32 r dq u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 VL128 @@ -27771,6 +29396,7 @@ VL128 i1 r mskw u32 r dq u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 VL256 @@ -27778,6 +29404,7 @@ VL256 i1 r mskw u32 r qq u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 VL256 @@ -27785,6 +29412,7 @@ VL256 i1 r mskw u32 r qq u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 VL512 @@ -27792,6 +29420,7 @@ VL512 i1 r mskw u64 r zu64 u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 VL512 @@ -27799,6 +29428,7 @@ VL512 i1 r mskw u64 r zu64 u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 VL128 @@ -27806,6 +29436,7 @@ VL128 i1 r mskw u64 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 VL128 @@ -27813,6 +29444,7 @@ VL128 i1 r mskw u64 r dq u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 VL256 @@ -27820,6 +29452,7 @@ VL256 i1 r mskw u64 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 VL256 @@ -27827,6 +29460,7 @@ VL256 i1 r mskw u64 r qq u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 VL512 @@ -28349,96 +29983,112 @@ VL512 f64 w zf64 i1 r mskw f64 r zf64 + u8 r b INTRINSIC_XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 VL512 f64 w zf64 i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 VL128 f64 w dq i1 r mskw f64 r dq + u8 r b INTRINSIC_XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 VL128 f64 w dq i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 VL256 f64 w qq i1 r mskw f64 r qq + u8 r b INTRINSIC_XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 VL256 f64 w qq i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 VL512 f32 w zf32 i1 r mskw f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 VL512 f32 w zf32 i1 r mskw f32 r vv + u8 r b INTRINSIC_XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 VL128 f32 w dq i1 r mskw f32 r dq + u8 r b INTRINSIC_XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 VL128 f32 w dq i1 r mskw f32 r vv + u8 r b INTRINSIC_XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 VL256 f32 w qq i1 r mskw f32 r qq + u8 r b INTRINSIC_XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 VL256 f32 w qq i1 r mskw f32 r vv + u8 r b INTRINSIC_XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 f64 w dq i1 r mskw f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 f64 w dq i1 r mskw f64 r dq f64 r q + u8 r b INTRINSIC_XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 f32 w dq i1 r mskw f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 f32 w dq i1 r mskw f32 r dq f32 r d + u8 r b INTRINSIC_XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 VL512 @@ -28722,6 +30372,7 @@ VL512 i1 r mskw f32 r zf32 f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 VL512 @@ -28729,6 +30380,7 @@ VL512 i1 r mskw f32 r zf32 f32 r vv + u8 r b INTRINSIC_XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 VL256 @@ -28736,6 +30388,7 @@ VL256 i1 r mskw f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 VL256 @@ -28743,6 +30396,7 @@ VL256 i1 r mskw f32 r qq f32 r vv + u8 r b INTRINSIC_XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 VL512 @@ -28750,6 +30404,7 @@ VL512 i1 r mskw f64 r zf64 f64 r zf64 + u8 r b INTRINSIC_XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 VL512 @@ -28757,6 +30412,7 @@ VL512 i1 r mskw f64 r zf64 f64 r vv + u8 r b INTRINSIC_XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 VL256 @@ -28764,6 +30420,7 @@ VL256 i1 r mskw f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 VL256 @@ -28771,6 +30428,7 @@ VL256 i1 r mskw f64 r qq f64 r vv + u8 r b INTRINSIC_XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 VL512 @@ -28778,6 +30436,7 @@ VL512 i1 r mskw u32 r zu32 u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 VL512 @@ -28785,6 +30444,7 @@ VL512 i1 r mskw u32 r zu32 u32 r vv + u8 r b INTRINSIC_XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 VL256 @@ -28792,6 +30452,7 @@ VL256 i1 r mskw u32 r qq u32 r qq + u8 r b INTRINSIC_XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 VL256 @@ -28799,6 +30460,7 @@ VL256 i1 r mskw u32 r qq u32 r vv + u8 r b INTRINSIC_XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 VL512 @@ -28806,6 +30468,7 @@ VL512 i1 r mskw u64 r zu64 u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 VL512 @@ -28813,6 +30476,7 @@ VL512 i1 r mskw u64 r zu64 u64 r vv + u8 r b INTRINSIC_XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 VL256 @@ -28820,6 +30484,7 @@ VL256 i1 r mskw u64 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 VL256 @@ -28827,6 +30492,7 @@ VL256 i1 r mskw u64 r qq u64 r vv + u8 r b INTRINSIC_XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 VL512 @@ -28834,6 +30500,7 @@ VL512 i1 r mskw f64 r zf64 f64 r zf64 + u8 r b INTRINSIC_XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 VL512 @@ -28841,6 +30508,7 @@ VL512 i1 r mskw f64 r zf64 f64 r vv + u8 r b INTRINSIC_XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 VL128 @@ -28848,6 +30516,7 @@ VL128 i1 r mskw f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 VL128 @@ -28855,6 +30524,7 @@ VL128 i1 r mskw f64 r dq f64 r vv + u8 r b INTRINSIC_XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 VL256 @@ -28862,6 +30532,7 @@ VL256 i1 r mskw f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 VL256 @@ -28869,6 +30540,7 @@ VL256 i1 r mskw f64 r qq f64 r vv + u8 r b INTRINSIC_XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 VL512 @@ -28876,6 +30548,7 @@ VL512 i1 r mskw f32 r zf32 f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 VL512 @@ -28883,6 +30556,7 @@ VL512 i1 r mskw f32 r zf32 f32 r vv + u8 r b INTRINSIC_XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 VL128 @@ -28890,6 +30564,7 @@ VL128 i1 r mskw f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 VL128 @@ -28897,6 +30572,7 @@ VL128 i1 r mskw f32 r dq f32 r vv + u8 r b INTRINSIC_XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 VL256 @@ -28904,6 +30580,7 @@ VL256 i1 r mskw f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 VL256 @@ -28911,6 +30588,7 @@ VL256 i1 r mskw f32 r qq f32 r vv + u8 r b INTRINSIC_XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 VL512 @@ -30180,6 +31858,7 @@ VL128 i1 r mskw u8 r dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 VL128 @@ -30187,6 +31866,7 @@ VL128 i1 r mskw u8 r dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 VL256 @@ -30194,6 +31874,7 @@ VL256 i1 r mskw u8 r qq u8 r qq + u8 r b INTRINSIC_XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 VL256 @@ -30201,6 +31882,7 @@ VL256 i1 r mskw u8 r qq u8 r qq + u8 r b INTRINSIC_XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 VL512 @@ -30208,6 +31890,7 @@ VL512 i1 r mskw u8 r zu8 u8 r zu8 + u8 r b INTRINSIC_XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 VL512 @@ -30215,170 +31898,199 @@ VL512 i1 r mskw u8 r zu8 u8 r zd + u8 r b INTRINSIC_XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 VL512 f32 w qq i1 r mskw f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 VL512 f32 w qq i1 r mskw f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 VL256 f64 w dq i1 r mskw f64 r qq + u8 r b INTRINSIC_XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 VL256 f64 w dq i1 r mskw f64 r qq + u8 r b INTRINSIC_XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 VL512 f64 w dq i1 r mskw f64 r zf64 + u8 r b INTRINSIC_XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 VL512 f64 w dq i1 r mskw f64 r zf64 + u8 r b INTRINSIC_XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 VL512 u32 w qq i1 r mskw u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 VL512 u32 w qq i1 r mskw u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 VL256 u64 w dq i1 r mskw u64 r qq + u8 r b INTRINSIC_XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 VL256 u64 w dq i1 r mskw u64 r qq + u8 r b INTRINSIC_XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 VL512 u64 w dq i1 r mskw u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 VL512 u64 w dq i1 r mskw u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 VL128 i1 w mskw i1 r mskw f64 r dq + u8 r b INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 VL128 i1 w mskw i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 VL256 i1 w mskw i1 r mskw f64 r qq + u8 r b INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 VL256 i1 w mskw i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 VL512 i1 w mskw i1 r mskw f64 r zf64 + u8 r b INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 VL512 i1 w mskw i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 VL128 i1 w mskw i1 r mskw f32 r dq + u8 r b INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 VL128 i1 w mskw i1 r mskw f32 r vv + u8 r b INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 VL256 i1 w mskw i1 r mskw f32 r qq + u8 r b INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 VL256 i1 w mskw i1 r mskw f32 r vv + u8 r b INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 VL512 i1 w mskw i1 r mskw f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 VL512 i1 w mskw i1 r mskw f32 r vv + u8 r b INTRINSIC_XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 i1 w mskw i1 r mskw f64 r dq + u8 r b INTRINSIC_XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 i1 w mskw i1 r mskw f64 r q + u8 r b INTRINSIC_XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 i1 w mskw i1 r mskw f32 r dq + u8 r b INTRINSIC_XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 i1 w mskw i1 r mskw f32 r d + u8 r b INTRINSIC_XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 VL512 @@ -30386,6 +32098,7 @@ VL512 i1 r mskw f32 r zf32 f32 r qq + u8 r b INTRINSIC_XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 VL512 @@ -30393,6 +32106,7 @@ VL512 i1 r mskw f32 r zf32 f32 r qq + u8 r b INTRINSIC_XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 VL256 @@ -30400,6 +32114,7 @@ VL256 i1 r mskw f64 r qq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 VL256 @@ -30407,6 +32122,7 @@ VL256 i1 r mskw f64 r qq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 VL512 @@ -30414,6 +32130,7 @@ VL512 i1 r mskw f64 r zf64 f64 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 VL512 @@ -30421,6 +32138,7 @@ VL512 i1 r mskw f64 r zf64 f64 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 VL512 @@ -30428,6 +32146,7 @@ VL512 i1 r mskw u32 r zu32 u32 r qq + u8 r b INTRINSIC_XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 VL512 @@ -30435,6 +32154,7 @@ VL512 i1 r mskw u32 r zu32 u32 r qq + u8 r b INTRINSIC_XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 VL256 @@ -30442,6 +32162,7 @@ VL256 i1 r mskw u64 r qq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 VL256 @@ -30449,6 +32170,7 @@ VL256 i1 r mskw u64 r qq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 VL512 @@ -30456,6 +32178,7 @@ VL512 i1 r mskw u64 r zu64 u64 r dq + u8 r b INTRINSIC_XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 VL512 @@ -30463,6 +32186,7 @@ VL512 i1 r mskw u64 r zu64 u64 r dq + u8 r b INTRINSIC_XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 VL128 @@ -31154,6 +32878,7 @@ VL128 i1 r mskw u8 r dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 VL128 @@ -31161,6 +32886,7 @@ VL128 i1 r mskw u8 r dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 VL256 @@ -31168,6 +32894,7 @@ VL256 i1 r mskw u8 r qq u8 r qq + u8 r b INTRINSIC_XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 VL256 @@ -31175,6 +32902,7 @@ VL256 i1 r mskw u8 r qq u8 r qq + u8 r b INTRINSIC_XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 VL512 @@ -31182,6 +32910,7 @@ VL512 i1 r mskw u8 r zu8 u8 r zu8 + u8 r b INTRINSIC_XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 VL512 @@ -31189,6 +32918,7 @@ VL512 i1 r mskw u8 r zu8 u8 r zd + u8 r b INTRINSIC_XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 VL128 @@ -31472,6 +33202,7 @@ VL128 i1 r mskw i8 r dq i8 r dq + u8 r b INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 VL128 @@ -31479,6 +33210,7 @@ VL128 i1 r mskw i8 r dq i8 r dq + u8 r b INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 VL256 @@ -31486,6 +33218,7 @@ VL256 i1 r mskw i8 r qq i8 r qq + u8 r b INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 VL256 @@ -31493,6 +33226,7 @@ VL256 i1 r mskw i8 r qq i8 r qq + u8 r b INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 VL512 @@ -31500,6 +33234,7 @@ VL512 i1 r mskw i8 r zi8 i8 r zi8 + u8 r b INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 VL512 @@ -31507,6 +33242,7 @@ VL512 i1 r mskw i8 r zi8 i8 r zd + u8 r b INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 VL128 @@ -31682,6 +33418,7 @@ VL128 i1 r mskw u8 r dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 VL128 @@ -31689,6 +33426,7 @@ VL128 i1 r mskw u8 r dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 VL256 @@ -31696,6 +33434,7 @@ VL256 i1 r mskw u8 r qq u8 r qq + u8 r b INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 VL256 @@ -31703,6 +33442,7 @@ VL256 i1 r mskw u8 r qq u8 r qq + u8 r b INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 VL512 @@ -31710,6 +33450,7 @@ VL512 i1 r mskw u8 r zu8 u8 r zu8 + u8 r b INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 VL512 @@ -31717,6 +33458,7 @@ VL512 i1 r mskw u8 r zu8 u8 r zd + u8 r b INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 VL128 @@ -31724,6 +33466,7 @@ VL128 i1 r mskw u16 r dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 VL128 @@ -31731,6 +33474,7 @@ VL128 i1 r mskw u16 r dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 VL256 @@ -31738,6 +33482,7 @@ VL256 i1 r mskw u16 r qq u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 VL256 @@ -31745,6 +33490,7 @@ VL256 i1 r mskw u16 r qq u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 VL512 @@ -31752,6 +33498,7 @@ VL512 i1 r mskw u16 r zu16 u16 r zu16 + u8 r b INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 VL512 @@ -31759,6 +33506,7 @@ VL512 i1 r mskw u16 r zu16 u16 r zd + u8 r b INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 VL128 @@ -31766,6 +33514,7 @@ VL128 i1 r mskw i16 r dq i16 r dq + u8 r b INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 VL128 @@ -31773,6 +33522,7 @@ VL128 i1 r mskw i16 r dq i16 r dq + u8 r b INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 VL256 @@ -31780,6 +33530,7 @@ VL256 i1 r mskw i16 r qq i16 r qq + u8 r b INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 VL256 @@ -31787,6 +33538,7 @@ VL256 i1 r mskw i16 r qq i16 r qq + u8 r b INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 VL512 @@ -31794,6 +33546,7 @@ VL512 i1 r mskw i16 r zi16 i16 r zi16 + u8 r b INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 VL512 @@ -31801,6 +33554,7 @@ VL512 i1 r mskw i16 r zi16 i16 r zd + u8 r b INTRINSIC_XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 VL128 @@ -31932,94 +33686,111 @@ INTRINSIC_XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 VL128 u8 w d u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 VL128 u8 w b u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 VL128 u32 w d u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 VL128 u32 w d u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 VL128 u64 w q u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 VL128 u64 w q u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 VL128 u16 w d u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 VL128 u16 w wrd u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 VL128 u16 w d u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 VL128 u8 w dq u8 r dq u8 r d + u8 r b INTRINSIC_XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 VL128 u8 w dq u8 r dq u8 r b + u8 r b INTRINSIC_XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 VL128 u32 w dq u32 r dq u32 r d + u8 r b INTRINSIC_XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 VL128 u32 w dq u32 r dq u32 r d + u8 r b INTRINSIC_XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 VL128 u64 w dq u64 r dq u64 r q + u8 r b INTRINSIC_XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 VL128 u64 w dq u64 r dq u64 r q + u8 r b INTRINSIC_XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 VL128 u16 w dq u16 r dq u16 r d + u8 r b INTRINSIC_XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 VL128 u16 w dq u16 r dq u16 r wrd + u8 r b INTRINSIC_XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 VL128 @@ -33034,102 +34805,120 @@ VL128 u16 w dq i1 r mskw u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 VL128 u16 w dq i1 r mskw u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 VL256 u16 w qq i1 r mskw u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 VL256 u16 w qq i1 r mskw u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 VL512 u16 w zu16 i1 r mskw u16 r zu16 + u8 r b INTRINSIC_XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 VL512 u16 w zu16 i1 r mskw u16 r zd + u8 r b INTRINSIC_XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 VL128 u16 w dq i1 r mskw u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 VL128 u16 w dq i1 r mskw u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 VL256 u16 w qq i1 r mskw u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 VL256 u16 w qq i1 r mskw u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 VL512 u16 w zu16 i1 r mskw u16 r zu16 + u8 r b INTRINSIC_XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 VL512 u16 w zu16 i1 r mskw u16 r zd + u8 r b INTRINSIC_XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 VL128 u8 w dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 VL128 u8 w dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 VL256 u8 w qq u8 r qq + u8 r b INTRINSIC_XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 VL256 u8 w qq u8 r qq + u8 r b INTRINSIC_XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 VL512 u8 w zu8 u8 r zu8 + u8 r b INTRINSIC_XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 VL512 u8 w zu8 u8 r zd + u8 r b INTRINSIC_XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 VL128 @@ -33192,12 +34981,14 @@ VL128 u16 w dq i1 r mskw u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 VL128 u16 w dq i1 r mskw u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 VL256 @@ -33218,12 +35009,14 @@ VL256 u16 w qq i1 r mskw u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 VL256 u16 w qq i1 r mskw u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 VL512 @@ -33244,12 +35037,14 @@ VL512 u16 w zu16 i1 r mskw u16 r zu16 + u8 r b INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 VL512 u16 w zu16 i1 r mskw u16 r zd + u8 r b INTRINSIC_XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 VL128 @@ -33312,12 +35107,14 @@ VL128 u16 w dq i1 r mskw u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 VL128 u16 w dq i1 r mskw u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 VL256 @@ -33338,12 +35135,14 @@ VL256 u16 w qq i1 r mskw u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 VL256 u16 w qq i1 r mskw u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 VL512 @@ -33364,42 +35163,50 @@ VL512 u16 w zu16 i1 r mskw u16 r zu16 + u8 r b INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 VL512 u16 w zu16 i1 r mskw u16 r zd + u8 r b INTRINSIC_XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 VL128 u8 w dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 VL128 u8 w dq u8 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 VL256 u8 w qq u8 r qq + u8 r b INTRINSIC_XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 VL256 u8 w qq u8 r qq + u8 r b INTRINSIC_XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 VL512 u8 w zu8 u8 r zu8 + u8 r b INTRINSIC_XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 VL512 u8 w zu8 u8 r zd + u8 r b INTRINSIC_XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 VL128 @@ -33462,12 +35269,14 @@ VL128 u16 w dq i1 r mskw u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 VL128 u16 w dq i1 r mskw u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 VL256 @@ -33488,12 +35297,14 @@ VL256 u16 w qq i1 r mskw u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 VL256 u16 w qq i1 r mskw u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 VL512 @@ -33514,12 +35325,14 @@ VL512 u16 w zu16 i1 r mskw u16 r zu16 + u8 r b INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 VL512 u16 w zu16 i1 r mskw u16 r zd + u8 r b INTRINSIC_XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 VL128 @@ -34115,6 +35928,7 @@ VL128 i1 r mskw f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 VL128 @@ -34122,6 +35936,7 @@ VL128 i1 r mskw f64 r dq f64 r vv + u8 r b INTRINSIC_XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 VL256 @@ -34129,6 +35944,7 @@ VL256 i1 r mskw f64 r qq f64 r qq + u8 r b INTRINSIC_XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 VL256 @@ -34136,6 +35952,7 @@ VL256 i1 r mskw f64 r qq f64 r vv + u8 r b INTRINSIC_XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 VL512 @@ -34143,6 +35960,7 @@ VL512 i1 r mskw f64 r zf64 f64 r zf64 + u8 r b INTRINSIC_XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 VL512 @@ -34150,6 +35968,7 @@ VL512 i1 r mskw f64 r zf64 f64 r vv + u8 r b INTRINSIC_XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 VL128 @@ -34157,6 +35976,7 @@ VL128 i1 r mskw f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 VL128 @@ -34164,6 +35984,7 @@ VL128 i1 r mskw f32 r dq f32 r vv + u8 r b INTRINSIC_XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 VL256 @@ -34171,6 +35992,7 @@ VL256 i1 r mskw f32 r qq f32 r qq + u8 r b INTRINSIC_XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 VL256 @@ -34178,6 +36000,7 @@ VL256 i1 r mskw f32 r qq f32 r vv + u8 r b INTRINSIC_XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 VL512 @@ -34185,6 +36008,7 @@ VL512 i1 r mskw f32 r zf32 f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 VL512 @@ -34192,126 +36016,147 @@ VL512 i1 r mskw f32 r zf32 f32 r vv + u8 r b INTRINSIC_XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 f64 w dq i1 r mskw f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 f64 w dq i1 r mskw f64 r dq f64 r q + u8 r b INTRINSIC_XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 f32 w dq i1 r mskw f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 f32 w dq i1 r mskw f32 r dq f32 r d + u8 r b INTRINSIC_XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 VL128 f64 w dq i1 r mskw f64 r dq + u8 r b INTRINSIC_XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 VL128 f64 w dq i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 VL256 f64 w qq i1 r mskw f64 r qq + u8 r b INTRINSIC_XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 VL256 f64 w qq i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 VL512 f64 w zf64 i1 r mskw f64 r zf64 + u8 r b INTRINSIC_XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 VL512 f64 w zf64 i1 r mskw f64 r vv + u8 r b INTRINSIC_XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 VL128 f32 w dq i1 r mskw f32 r dq + u8 r b INTRINSIC_XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 VL128 f32 w dq i1 r mskw f32 r vv + u8 r b INTRINSIC_XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 VL256 f32 w qq i1 r mskw f32 r qq + u8 r b INTRINSIC_XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 VL256 f32 w qq i1 r mskw f32 r vv + u8 r b INTRINSIC_XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 VL512 f32 w zf32 i1 r mskw f32 r zf32 + u8 r b INTRINSIC_XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 VL512 f32 w zf32 i1 r mskw f32 r vv + u8 r b INTRINSIC_XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 f64 w dq i1 r mskw f64 r dq f64 r dq + u8 r b INTRINSIC_XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 f64 w dq i1 r mskw f64 r dq f64 r q + u8 r b INTRINSIC_XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 f32 w dq i1 r mskw f32 r dq f32 r dq + u8 r b INTRINSIC_XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 f32 w dq i1 r mskw f32 r dq f32 r d + u8 r b INTRINSIC_XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 VL128 @@ -34913,6 +36758,7 @@ VL128 i1 r mskw u32 r dq u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 VL128 @@ -34920,6 +36766,7 @@ VL128 i1 r mskw u32 r dq u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 VL256 @@ -34927,6 +36774,7 @@ VL256 i1 r mskw u32 r qq u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 VL256 @@ -34934,6 +36782,7 @@ VL256 i1 r mskw u32 r qq u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 VL512 @@ -34941,6 +36790,7 @@ VL512 i1 r mskw u32 r zu32 u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 VL512 @@ -34948,6 +36798,7 @@ VL512 i1 r mskw u32 r zu32 u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 VL128 @@ -34955,6 +36806,7 @@ VL128 i1 r mskw u64 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 VL128 @@ -34962,6 +36814,7 @@ VL128 i1 r mskw u64 r dq u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 VL256 @@ -34969,6 +36822,7 @@ VL256 i1 r mskw u64 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 VL256 @@ -34976,6 +36830,7 @@ VL256 i1 r mskw u64 r qq u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 VL512 @@ -34983,6 +36838,7 @@ VL512 i1 r mskw u64 r zu64 u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 VL512 @@ -34990,6 +36846,7 @@ VL512 i1 r mskw u64 r zu64 u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 VL128 @@ -35123,6 +36980,7 @@ VL128 i1 r mskw u16 r dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 VL128 @@ -35130,6 +36988,7 @@ VL128 i1 r mskw u16 r dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 VL256 @@ -35137,6 +36996,7 @@ VL256 i1 r mskw u16 r qq u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 VL256 @@ -35144,6 +37004,7 @@ VL256 i1 r mskw u16 r qq u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 VL512 @@ -35151,6 +37012,7 @@ VL512 i1 r mskw u16 r zu16 u16 r zu16 + u8 r b INTRINSIC_XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 VL512 @@ -35158,6 +37020,7 @@ VL512 i1 r mskw u16 r zu16 u16 r zd + u8 r b INTRINSIC_XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 VL128 @@ -35165,6 +37028,7 @@ VL128 i1 r mskw u32 r dq u32 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 VL128 @@ -35172,6 +37036,7 @@ VL128 i1 r mskw u32 r dq u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 VL256 @@ -35179,6 +37044,7 @@ VL256 i1 r mskw u32 r qq u32 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 VL256 @@ -35186,6 +37052,7 @@ VL256 i1 r mskw u32 r qq u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 VL512 @@ -35193,6 +37060,7 @@ VL512 i1 r mskw u32 r zu32 u32 r zu32 + u8 r b INTRINSIC_XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 VL512 @@ -35200,6 +37068,7 @@ VL512 i1 r mskw u32 r zu32 u32 r vv + u8 r b INTRINSIC_XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 VL128 @@ -35207,6 +37076,7 @@ VL128 i1 r mskw u64 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 VL128 @@ -35214,6 +37084,7 @@ VL128 i1 r mskw u64 r dq u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 VL256 @@ -35221,6 +37092,7 @@ VL256 i1 r mskw u64 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 VL256 @@ -35228,6 +37100,7 @@ VL256 i1 r mskw u64 r qq u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 VL512 @@ -35235,6 +37108,7 @@ VL512 i1 r mskw u64 r zu64 u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 VL512 @@ -35242,6 +37116,7 @@ VL512 i1 r mskw u64 r zu64 u64 r vv + u8 r b INTRINSIC_XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 VL128 @@ -35375,6 +37250,7 @@ VL128 i1 r mskw u16 r dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 VL128 @@ -35382,6 +37258,7 @@ VL128 i1 r mskw u16 r dq u16 r dq + u8 r b INTRINSIC_XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 VL256 @@ -35389,6 +37266,7 @@ VL256 i1 r mskw u16 r qq u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 VL256 @@ -35396,6 +37274,7 @@ VL256 i1 r mskw u16 r qq u16 r qq + u8 r b INTRINSIC_XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 VL512 @@ -35403,6 +37282,7 @@ VL512 i1 r mskw u16 r zu16 u16 r zu16 + u8 r b INTRINSIC_XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 VL512 @@ -35410,6 +37290,7 @@ VL512 i1 r mskw u16 r zu16 u16 r zd + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 VL128 @@ -35417,6 +37298,7 @@ VL128 i1 r mskw u8 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 VL128 @@ -35424,6 +37306,7 @@ VL128 i1 r mskw u8 r dq u64 r vv + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 VL256 @@ -35431,6 +37314,7 @@ VL256 i1 r mskw u8 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 VL256 @@ -35438,6 +37322,7 @@ VL256 i1 r mskw u8 r qq u64 r vv + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 VL512 @@ -35445,6 +37330,7 @@ VL512 i1 r mskw u8 r zu8 u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 VL512 @@ -35452,6 +37338,7 @@ VL512 i1 r mskw u8 r zu8 u64 r vv + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 VL128 @@ -35459,6 +37346,7 @@ VL128 i1 r mskw u8 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 VL128 @@ -35466,6 +37354,7 @@ VL128 i1 r mskw u8 r dq u64 r vv + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 VL256 @@ -35473,6 +37362,7 @@ VL256 i1 r mskw u8 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 VL256 @@ -35480,6 +37370,7 @@ VL256 i1 r mskw u8 r qq u64 r vv + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 VL512 @@ -35487,6 +37378,7 @@ VL512 i1 r mskw u8 r zu8 u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 VL512 @@ -35494,6 +37386,7 @@ VL512 i1 r mskw u8 r zu8 u64 r vv + u8 r b INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 VL128 @@ -35686,36 +37579,42 @@ VL128 u128 w dq u64 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 VL128 u128 w dq u64 r dq u64 r dq + u8 r b INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 VL256 u128 w qq u64 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 VL256 u128 w qq u64 r qq u64 r qq + u8 r b INTRINSIC_XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 VL512 u128 w zu128 u64 r zu64 u64 r zu64 + u8 r b INTRINSIC_XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 VL512 u128 w zu128 u64 r zu64 u64 r zd + u8 r b INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512 VL128 @@ -35789,3 +37688,9674 @@ VL512 u64 r zu64 u64 r vv +INTRINSIC_XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + f16 r dq + f16 r dq + u8 r b + +INTRINSIC_XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + f16 r dq + f16 r vv + u8 r b + +INTRINSIC_XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + f16 r qq + f16 r qq + u8 r b + +INTRINSIC_XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + f16 r qq + f16 r vv + u8 r b + +INTRINSIC_XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + f16 r zf16 + f16 r zf16 + u8 r b + +INTRINSIC_XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + f16 r zf16 + f16 r vv + u8 r b + +INTRINSIC_XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 + i1 w mskw + i1 r mskw + f16 r dq + f16 r dq + u8 r b + +INTRINSIC_XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 + i1 w mskw + i1 r mskw + f16 r dq + f16 r wrd + u8 r b + +INTRINSIC_XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512 + f16 r dq + f16 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512 + f16 r dq + f16 r wrd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512 +VL128 + f16 w dq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128 +VL128 + f16 w dq + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512 +VL256 + f16 w dq + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256 +VL256 + f16 w dq + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512 +VL512 + f16 w qq + i1 r mskw + i32 r zi32 + +INTRINSIC_XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512 +VL512 + f16 w qq + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512 +VL128 + f16 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128 +VL128 + f16 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512 +VL256 + f16 w dq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256 +VL256 + f16 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512 +VL512 + f16 w dq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512 +VL512 + f16 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 +VL128 + i32 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 +VL128 + i32 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 +VL256 + i32 w qq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 +VL256 + i32 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512 +VL128 + f64 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512 +VL128 + f64 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512 +VL256 + f64 w qq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512 +VL256 + f64 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512 +VL128 + f32 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512 +VL128 + f32 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512 +VL256 + f32 w qq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512 +VL256 + f32 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 +VL128 + i64 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 +VL128 + i64 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 +VL256 + i64 w qq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 +VL256 + i64 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 +VL128 + u32 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 +VL128 + u32 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 +VL256 + u32 w qq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 +VL256 + u32 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 +VL512 + u32 w zu32 + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 +VL512 + u32 w zu32 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 +VL128 + u64 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 +VL128 + u64 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 +VL256 + u64 w qq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 +VL256 + u64 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 +VL128 + u16 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 +VL128 + u16 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 +VL256 + u16 w qq + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 +VL256 + u16 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + f16 r zf16 + +INTRINSIC_XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 +VL128 + i16 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 +VL128 + i16 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 +VL256 + i16 w qq + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 +VL256 + i16 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + f16 r zf16 + +INTRINSIC_XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512 +VL128 + f16 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128 +VL128 + f16 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512 +VL256 + f16 w dq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256 +VL256 + f16 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512 +VL512 + f16 w qq + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512 +VL512 + f16 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 +VL128 + f16 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 +VL128 + f16 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 +VL256 + f16 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 +VL256 + f16 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 +VL512 + f16 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 +VL512 + f16 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512 + f16 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512 + f16 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512 + i32 w d + f16 r dq + +INTRINSIC_XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512 + i32 w d + f16 r wrd + +INTRINSIC_XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512 + i64 w q + f16 r dq + +INTRINSIC_XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512 + i64 w q + f16 r wrd + +INTRINSIC_XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512 + u32 w d + f16 r dq + +INTRINSIC_XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512 + u32 w d + f16 r wrd + +INTRINSIC_XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512 + u64 w q + f16 r dq + +INTRINSIC_XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512 + u64 w q + f16 r wrd + +INTRINSIC_XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 + f16 w dq + f16 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 + f16 w dq + f16 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 + f16 w dq + f16 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512 + f16 w dq + f16 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f32 r d + +INTRINSIC_XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 +VL128 + i32 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 +VL128 + i32 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 +VL256 + i32 w qq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 +VL256 + i32 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 +VL128 + i64 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 +VL128 + i64 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 +VL256 + i64 w qq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 +VL256 + i64 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 +VL128 + u32 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 +VL128 + u32 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 +VL256 + u32 w qq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 +VL256 + u32 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 +VL512 + u32 w zu32 + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 +VL512 + u32 w zu32 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 +VL128 + u64 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 +VL128 + u64 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 +VL256 + u64 w qq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 +VL256 + u64 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 +VL128 + u16 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 +VL128 + u16 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 +VL256 + u16 w qq + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 +VL256 + u16 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + f16 r zf16 + +INTRINSIC_XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 +VL128 + i16 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 +VL128 + i16 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 +VL256 + i16 w qq + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 +VL256 + i16 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + f16 r zf16 + +INTRINSIC_XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512 + i32 w d + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512 + i32 w d + f16 r wrd + +INTRINSIC_XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512 + i64 w q + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512 + i64 w q + f16 r wrd + +INTRINSIC_XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512 + u32 w d + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512 + u32 w d + f16 r wrd + +INTRINSIC_XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512 + u64 w q + f16 r dq + +INTRINSIC_XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512 + u64 w q + f16 r wrd + +INTRINSIC_XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512 +VL128 + f16 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128 +VL128 + f16 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512 +VL256 + f16 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256 +VL256 + f16 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512 +VL512 + f16 w qq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512 +VL512 + f16 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 +VL128 + f16 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 +VL128 + f16 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 +VL256 + f16 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 +VL256 + f16 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 +VL512 + f16 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 +VL512 + f16 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 + f16 w dq + f16 r dq + u32 r d + +INTRINSIC_XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 + f16 w dq + f16 r dq + u32 r d + +INTRINSIC_XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 + f16 w dq + f16 r dq + u64 r q + +INTRINSIC_XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512 + f16 w dq + f16 r dq + u64 r q + +INTRINSIC_XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512 +VL128 + f16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512 +VL128 + f16 w dq + i1 r mskw + u16 r vv + +INTRINSIC_XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512 +VL256 + f16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512 +VL256 + f16 w qq + i1 r mskw + u16 r vv + +INTRINSIC_XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + u16 r vv + +INTRINSIC_XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512 +VL128 + f16 w dq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512 +VL128 + f16 w dq + i1 r mskw + i16 r vv + +INTRINSIC_XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512 +VL256 + f16 w qq + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512 +VL256 + f16 w qq + i1 r mskw + i16 r vv + +INTRINSIC_XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + i16 r zi16 + +INTRINSIC_XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + i16 r vv + +INTRINSIC_XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +VL128 + 2f16 rw dq + i1 r mskw + 2f16 r dq + 2f16 r dq + +INTRINSIC_XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +VL128 + 2f16 rw dq + i1 r mskw + 2f16 r dq + 2f16 r vv + +INTRINSIC_XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 +VL256 + 2f16 rw qq + i1 r mskw + 2f16 r qq + 2f16 r qq + +INTRINSIC_XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 +VL256 + 2f16 rw qq + i1 r mskw + 2f16 r qq + 2f16 r vv + +INTRINSIC_XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +VL512 + 2f16 rw z2f16 + i1 r mskw + 2f16 r z2f16 + 2f16 r z2f16 + +INTRINSIC_XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 +VL512 + 2f16 rw z2f16 + i1 r mskw + 2f16 r z2f16 + 2f16 r vv + +INTRINSIC_XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 + 2f16 rw dq + i1 r mskw + 2f16 r dq + 2f16 r dq + +INTRINSIC_XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 + 2f16 rw dq + i1 r mskw + 2f16 r dq + 2f16 r d + +INTRINSIC_XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +VL128 + 2f16 w dq + i1 r mskw + 2f16 r dq + 2f16 r dq + +INTRINSIC_XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +VL128 + 2f16 w dq + i1 r mskw + 2f16 r dq + 2f16 r vv + +INTRINSIC_XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 +VL256 + 2f16 w qq + i1 r mskw + 2f16 r qq + 2f16 r qq + +INTRINSIC_XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 +VL256 + 2f16 w qq + i1 r mskw + 2f16 r qq + 2f16 r vv + +INTRINSIC_XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +VL512 + 2f16 w z2f16 + i1 r mskw + 2f16 r z2f16 + 2f16 r z2f16 + +INTRINSIC_XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 +VL512 + 2f16 w z2f16 + i1 r mskw + 2f16 r z2f16 + 2f16 r vv + +INTRINSIC_XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 + 2f16 w dq + i1 r mskw + 2f16 r dq + 2f16 r dq + +INTRINSIC_XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 + 2f16 w dq + i1 r mskw + 2f16 r dq + 2f16 r d + +INTRINSIC_XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +VL128 + 2f16 rw dq + i1 r mskw + 2f16 r dq + 2f16 r dq + +INTRINSIC_XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +VL128 + 2f16 rw dq + i1 r mskw + 2f16 r dq + 2f16 r vv + +INTRINSIC_XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 +VL256 + 2f16 rw qq + i1 r mskw + 2f16 r qq + 2f16 r qq + +INTRINSIC_XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 +VL256 + 2f16 rw qq + i1 r mskw + 2f16 r qq + 2f16 r vv + +INTRINSIC_XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +VL512 + 2f16 rw z2f16 + i1 r mskw + 2f16 r z2f16 + 2f16 r z2f16 + +INTRINSIC_XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 +VL512 + 2f16 rw z2f16 + i1 r mskw + 2f16 r z2f16 + 2f16 r vv + +INTRINSIC_XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 + 2f16 rw dq + i1 r mskw + 2f16 r dq + 2f16 r dq + +INTRINSIC_XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 + 2f16 rw dq + i1 r mskw + 2f16 r dq + 2f16 r d + +INTRINSIC_XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +VL128 + 2f16 w dq + i1 r mskw + 2f16 r dq + 2f16 r dq + +INTRINSIC_XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +VL128 + 2f16 w dq + i1 r mskw + 2f16 r dq + 2f16 r vv + +INTRINSIC_XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 +VL256 + 2f16 w qq + i1 r mskw + 2f16 r qq + 2f16 r qq + +INTRINSIC_XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 +VL256 + 2f16 w qq + i1 r mskw + 2f16 r qq + 2f16 r vv + +INTRINSIC_XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +VL512 + 2f16 w z2f16 + i1 r mskw + 2f16 r z2f16 + 2f16 r z2f16 + +INTRINSIC_XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 +VL512 + 2f16 w z2f16 + i1 r mskw + 2f16 r z2f16 + 2f16 r vv + +INTRINSIC_XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 + 2f16 w dq + i1 r mskw + 2f16 r dq + 2f16 r dq + +INTRINSIC_XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 + 2f16 w dq + i1 r mskw + 2f16 r dq + 2f16 r d + +INTRINSIC_XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 rw dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 rw qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 rw zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 rw dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + f16 r dq + u8 r b + +INTRINSIC_XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128 +VL128 + i1 w mskw + i1 r mskw + f16 r vv + u8 r b + +INTRINSIC_XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + f16 r qq + u8 r b + +INTRINSIC_XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256 +VL256 + i1 w mskw + i1 r mskw + f16 r vv + u8 r b + +INTRINSIC_XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + f16 r zf16 + u8 r b + +INTRINSIC_XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512 +VL512 + i1 w mskw + i1 r mskw + f16 r vv + u8 r b + +INTRINSIC_XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 + i1 w mskw + i1 r mskw + f16 r dq + u8 r b + +INTRINSIC_XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512 + i1 w mskw + i1 r mskw + f16 r wrd + u8 r b + +INTRINSIC_XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + +INTRINSIC_XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + u8 r b + +INTRINSIC_XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r vv + u8 r b + +INTRINSIC_XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + u8 r b + +INTRINSIC_XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r vv + u8 r b + +INTRINSIC_XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + u8 r b + +INTRINSIC_XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r vv + u8 r b + +INTRINSIC_XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + u8 r b + +INTRINSIC_XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r wrd + u8 r b + +INTRINSIC_XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512 + f16 w dq + i1 r mskw + f16 r wrd + +INTRINSIC_XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512 + f16 w wrd + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512 +VL128 + f16 w dq + f16 r d + +INTRINSIC_XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512 +VL128 + f16 w dq + f16 r wrd + +INTRINSIC_XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512 +VL128 + f16 w d + f16 r dq + +INTRINSIC_XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512 +VL128 + f16 w wrd + f16 r dq + +INTRINSIC_XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + +INTRINSIC_XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + u8 r b + +INTRINSIC_XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r vv + u8 r b + +INTRINSIC_XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + u8 r b + +INTRINSIC_XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r vv + u8 r b + +INTRINSIC_XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + u8 r b + +INTRINSIC_XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r vv + u8 r b + +INTRINSIC_XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + u8 r b + +INTRINSIC_XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r wrd + u8 r b + +INTRINSIC_XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + u8 r b + +INTRINSIC_XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r vv + u8 r b + +INTRINSIC_XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + u8 r b + +INTRINSIC_XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r vv + u8 r b + +INTRINSIC_XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + u8 r b + +INTRINSIC_XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r vv + u8 r b + +INTRINSIC_XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + u8 r b + +INTRINSIC_XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r wrd + u8 r b + +INTRINSIC_XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + +INTRINSIC_XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + +INTRINSIC_XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r vv + +INTRINSIC_XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +VL128 + f16 w dq + i1 r mskw + f16 r dq + f16 r vv + +INTRINSIC_XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + f16 r qq + +INTRINSIC_XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +VL256 + f16 w qq + i1 r mskw + f16 r qq + f16 r vv + +INTRINSIC_XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + f16 r zf16 + +INTRINSIC_XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +VL512 + f16 w zf16 + i1 r mskw + f16 r zf16 + f16 r vv + +INTRINSIC_XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r dq + +INTRINSIC_XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 + f16 w dq + i1 r mskw + f16 r dq + f16 r wrd + +INTRINSIC_XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512 + f16 r dq + f16 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512 + f16 r dq + f16 r wrd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AADD_MEMi32_GPR32i32_APX +VL128 + i32 rw d + i32 r d + +INTRINSIC_XED_IFORM_AADD_MEMi64_GPR64i64_APX +VL128 + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_AAND_MEMi32_GPR32i32_APX +VL128 + i32 rw d + i32 r d + +INTRINSIC_XED_IFORM_AAND_MEMi64_GPR64i64_APX +VL128 + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_ADC_GPR8i8_GPR8i8_APX +VL128 + i8 rw b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMi8_GPR8i8_APX +VL128 + i8 rw b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_MEMv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8i8_GPR8i8_GPR8i8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8i8_MEMi8_GPR8i8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_APX +VL128 + int rw v + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMv_GPRv_APX +VL128 + int rw v + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_MEMv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8i8_MEMi8_APX +VL128 + i8 rw b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8i8_GPR8i8_MEMi8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_MEMv_APX +VL128 + int rw v + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8i8_GPR8i8_IMM8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8i8_MEMi8_IMM8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8i8_IMM8_APX +VL128 + i8 rw b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMi8_IMM8_APX +VL128 + i8 rw b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_IMMz_APX +VL128 + int rw v + int r z + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMv_IMMz_APX +VL128 + int rw v + int r z + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_MEMv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_IMM8_APX +VL128 + int rw v + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMv_IMM8_APX +VL128 + int rw v + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR32i32_GPR32i32_APX +VL128 + i32 rw d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR32i32_MEMi32_APX +VL128 + i32 rw d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR64i64_GPR64i64_APX +VL128 + i64 rw q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR64i64_MEMi64_APX +VL128 + i64 rw q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR32i32_GPR32i32_GPR32i32_APX +VL128 + i32 w d + i32 r d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR32i32_GPR32i32_MEMi32_APX +VL128 + i32 w d + i32 r d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR64i64_GPR64i64_GPR64i64_APX +VL128 + i64 w q + i64 r q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR64i64_GPR64i64_MEMi64_APX +VL128 + i64 w q + i64 r q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8i8_GPR8i8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMi8_GPR8i8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_MEMv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8i8_GPR8i8_GPR8i8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8i8_MEMi8_GPR8i8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMv_GPRv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_MEMv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8i8_MEMi8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8i8_GPR8i8_MEMi8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_MEMv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8i8_GPR8i8_IMM8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8i8_MEMi8_IMM8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8i8_IMM8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMi8_IMM8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_IMMz_APX +VL128 + int rw v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMv_IMMz_APX +VL128 + int rw v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_MEMv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_IMM8_APX +VL128 + int rw v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMv_IMM8_APX +VL128 + int rw v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR32i32_GPR32i32_APX +VL128 + i32 rw d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR32i32_MEMi32_APX +VL128 + i32 rw d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR64i64_GPR64i64_APX +VL128 + i64 rw q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR64i64_MEMi64_APX +VL128 + i64 rw q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR32i32_GPR32i32_GPR32i32_APX +VL128 + i32 w d + i32 r d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR32i32_GPR32i32_MEMi32_APX +VL128 + i32 w d + i32 r d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR64i64_GPR64i64_GPR64i64_APX +VL128 + i64 w q + i64 r q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR64i64_GPR64i64_MEMi64_APX +VL128 + i64 w q + i64 r q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8i8_GPR8i8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMi8_GPR8i8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_MEMv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8i8_GPR8i8_GPR8i8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8i8_MEMi8_GPR8i8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_GPRv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMv_GPRv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_MEMv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8i8_MEMi8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8i8_GPR8i8_MEMi8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_MEMv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8i8_GPR8i8_IMM8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8i8_MEMi8_IMM8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8i8_IMM8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMi8_IMM8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_IMMz_APX +VL128 + int rw v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMv_IMMz_APX +VL128 + int rw v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_GPRv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_MEMv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_IMM8_APX +VL128 + int rw v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMv_IMM8_APX +VL128 + int rw v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ANDN_GPR32i32_GPR32i32_GPR32i32_APX +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ANDN_GPR32i32_GPR32i32_MEMi32_APX +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ANDN_GPR64i64_GPR64i64_GPR64i64_APX +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ANDN_GPR64i64_GPR64i64_MEMi64_APX +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AOR_MEMi32_GPR32i32_APX +VL128 + i32 rw d + i32 r d + +INTRINSIC_XED_IFORM_AOR_MEMi64_GPR64i64_APX +VL128 + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_AXOR_MEMi32_GPR32i32_APX +VL128 + i32 rw d + i32 r d + +INTRINSIC_XED_IFORM_AXOR_MEMi64_GPR64i64_APX +VL128 + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_BEXTR_GPR32i32_GPR32i32_GPR32i32_APX +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_GPR32i32_MEMi32_GPR32i32_APX +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_GPR64i64_GPR64i64_GPR64i64_APX +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_GPR64i64_MEMi64_GPR64i64_APX +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSI_GPR32i32_GPR32i32_APX +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSI_GPR32i32_MEMi32_APX +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSI_GPR64i64_GPR64i64_APX +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSI_GPR64i64_MEMi64_APX +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSMSK_GPR32i32_GPR32i32_APX +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSMSK_GPR32i32_MEMi32_APX +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSMSK_GPR64i64_GPR64i64_APX +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSMSK_GPR64i64_MEMi64_APX +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSR_GPR32i32_GPR32i32_APX +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSR_GPR32i32_MEMi32_APX +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSR_GPR64i64_GPR64i64_APX +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSR_GPR64i64_MEMi64_APX +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BZHI_GPR32i32_GPR32i32_GPR32i32_APX +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BZHI_GPR32i32_MEMi32_GPR32i32_APX +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BZHI_GPR64i64_GPR64i64_GPR64i64_APX +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BZHI_GPR64i64_MEMi64_GPR64i64_APX +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPB_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPB_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPB_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPB_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPB_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPB_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPB_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPB_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPB_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPB_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPB_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPB_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPBE_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPBE_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPBE_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPBE_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPBE_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPBE_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPBE_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPBE_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPBE_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPBE_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPBE_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPBE_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPF_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPF_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPF_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPF_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPF_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPF_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPF_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPF_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPF_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPF_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPF_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPF_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPL_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPL_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPL_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPL_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPL_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPL_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPL_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPL_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPL_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPL_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPL_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPL_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPLE_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPLE_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPLE_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPLE_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPLE_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPLE_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPLE_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPLE_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPLE_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPLE_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPLE_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPLE_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNB_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNB_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNB_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNB_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNB_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNB_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNB_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNB_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNB_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNB_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNB_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNB_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNBE_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNBE_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNBE_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNBE_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNBE_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNBE_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNBE_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNBE_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNBE_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNBE_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNBE_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNBE_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNL_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNL_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNL_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNL_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNL_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNL_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNL_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNL_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNL_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNL_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNL_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNL_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNLE_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNLE_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNLE_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNLE_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNLE_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNLE_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNLE_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNLE_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNLE_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNLE_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNLE_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNLE_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNO_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNO_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNO_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNO_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNO_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNO_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNO_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNO_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNO_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNO_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNO_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNO_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNS_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNS_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNS_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNS_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNS_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNS_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNS_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNS_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNS_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNS_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNS_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNS_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNZ_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNZ_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNZ_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNZ_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNZ_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNZ_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNZ_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNZ_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNZ_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNZ_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNZ_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPNZ_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPO_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPO_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPO_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPO_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPO_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPO_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPO_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPO_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPO_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPO_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPO_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPO_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPS_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPS_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPS_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPS_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPS_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPS_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPS_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPS_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPS_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPS_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPS_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPS_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPT_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPT_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPT_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPT_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPT_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPT_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPT_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPT_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPT_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPT_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPT_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPT_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPZ_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPZ_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPZ_GPRv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPZ_MEMv_IMM8_DFV_APX +VL128 + int r v + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPZ_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPZ_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPZ_GPR8i8_MEMi8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPZ_GPRv_MEMv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPZ_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPZ_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPZ_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CCMPZ_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVB_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVB_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVB_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVB_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVB_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVBE_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVBE_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVBE_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVBE_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVBE_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVL_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVL_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVL_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVL_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVL_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVLE_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVLE_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVLE_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVLE_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVLE_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNB_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNB_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNB_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNB_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNB_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNBE_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNBE_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNBE_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNBE_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNBE_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNL_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNL_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNL_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNL_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNL_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNLE_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNLE_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNLE_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNLE_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNLE_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNO_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNO_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNO_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNO_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNO_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNP_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNP_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNP_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNP_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNP_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNS_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNS_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNS_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNS_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNS_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNZ_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNZ_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNZ_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNZ_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVNZ_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVO_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVO_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVO_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVO_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVO_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVP_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVP_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVP_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVP_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVP_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVS_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVS_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVS_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVS_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVS_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVZ_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVZ_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVZ_MEMv_GPRv_APX +VL128 + int cw v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVZ_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CFCMOVZ_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVB_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVB_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVBE_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVBE_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVL_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVL_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVLE_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVLE_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNB_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNB_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNBE_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNBE_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNL_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNL_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNLE_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNLE_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNO_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNO_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNP_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNP_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNS_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNS_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNZ_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNZ_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVO_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVO_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVP_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVP_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVS_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVS_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVZ_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVZ_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32_APX +VL128 + u32 rw d + u32 rw d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64_APX +VL128 + u64 rw q + u64 rw q + u64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CRC32_GPRy_GPR8i8_APX +VL128 + int rw y + i8 r b + +INTRINSIC_XED_IFORM_CRC32_GPRy_MEMi8_APX +VL128 + int rw y + i8 r b + +INTRINSIC_XED_IFORM_CRC32_GPRy_GPRv_APX +VL128 + int rw y + int r v + +INTRINSIC_XED_IFORM_CRC32_GPRy_MEMv_APX +VL128 + int rw y + int r v + +INTRINSIC_XED_IFORM_CTESTB_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTB_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTB_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTB_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTB_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTB_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTB_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTB_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTBE_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTBE_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTBE_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTBE_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTBE_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTBE_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTBE_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTBE_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTF_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTF_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTF_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTF_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTF_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTF_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTF_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTF_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTL_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTL_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTL_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTL_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTL_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTL_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTL_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTL_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTLE_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTLE_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTLE_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTLE_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTLE_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTLE_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTLE_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTLE_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNB_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNB_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNB_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNB_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNB_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNB_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNB_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNB_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNBE_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNBE_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNBE_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNBE_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNBE_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNBE_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNBE_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNBE_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNL_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNL_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNL_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNL_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNL_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNL_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNL_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNL_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNLE_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNLE_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNLE_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNLE_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNLE_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNLE_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNLE_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNLE_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNO_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNO_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNO_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNO_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNO_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNO_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNO_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNO_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNS_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNS_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNS_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNS_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNS_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNS_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNS_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNS_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNZ_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNZ_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNZ_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNZ_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNZ_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNZ_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNZ_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTNZ_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTO_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTO_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTO_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTO_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTO_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTO_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTO_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTO_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTS_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTS_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTS_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTS_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTS_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTS_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTS_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTS_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTT_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTT_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTT_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTT_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTT_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTT_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTT_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTT_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTZ_GPR8i8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTZ_MEMi8_GPR8i8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTZ_GPRv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTZ_MEMv_GPRv_DFV_APX +VL128 + int r v + int r v + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTZ_GPR8i8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTZ_MEMi8_IMM8_DFV_APX +VL128 + i8 r b + i8 r b + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTZ_GPRv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CTESTZ_MEMv_IMMz_DFV_APX +VL128 + int r v + int r z + INVALID r DFV + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_GPR8i8_APX +VL128 + i8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_MEMi8_APX +VL128 + i8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_GPR8i8_GPR8i8_APX +VL128 + i8 w b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_GPR8i8_MEMi8_APX +VL128 + i8 w b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_GPRv_APX +VL128 + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_MEMv_APX +VL128 + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DIV_GPR8i8_APX +VL128 + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DIV_MEMi8_APX +VL128 + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DIV_GPRv_APX +VL128 + int r v + INVALID rw OrAX + INVALID rw OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DIV_MEMv_APX +VL128 + int r v + INVALID rw OrAX + INVALID rw OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ENQCMD_GPRav_MEMu32_APX +VL128 + INVALID r A_GPR_R + u32 r zd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ENQCMDS_GPRav_MEMu32_APX +VL128 + INVALID r A_GPR_R + u32 r zd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IDIV_GPR8i8_APX +VL128 + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IDIV_MEMi8_APX +VL128 + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IDIV_GPRv_APX +VL128 + int r v + INVALID rw OrAX + INVALID rw OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IDIV_MEMv_APX +VL128 + int r v + INVALID rw OrAX + INVALID rw OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_APX +VL128 + int r v + INVALID rw OrAX + INVALID w OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_MEMv_APX +VL128 + int r v + INVALID rw OrAX + INVALID w OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPR8i8_APX +VL128 + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_MEMi8_APX +VL128 + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_GPR8i8_APX +VL128 + i8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_MEMi8_APX +VL128 + i8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_GPR8i8_GPR8i8_APX +VL128 + i8 w b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_GPR8i8_MEMi8_APX +VL128 + i8 w b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_GPRv_APX +VL128 + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_MEMv_APX +VL128 + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INVEPT_GPR64i64_MEMi128_APX +VL128 + i64 r q + i128 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INVPCID_GPR64i64_MEMi128_APX +VL128 + i64 r q + i128 r dq + +INTRINSIC_XED_IFORM_INVVPID_GPR64i64_MEMi128_APX +VL128 + i64 r q + i128 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KMOVB_MASKmskw_MASKu8_APX +VL128 + i1 w mskw + u8 r mskw + +INTRINSIC_XED_IFORM_KMOVB_MASKmskw_MEMu8_APX +VL128 + i1 w mskw + u8 r b + +INTRINSIC_XED_IFORM_KMOVB_MASKmskw_GPR32u32_APX +VL128 + i1 w mskw + u32 r d + +INTRINSIC_XED_IFORM_KMOVB_GPR32u32_MASKmskw_APX +VL128 + u32 w d + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVB_MEMu8_MASKmskw_APX +VL128 + u8 w b + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVD_GPR32u32_MASKmskw_APX +VL128 + u32 w d + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVD_MEMu32_MASKmskw_APX +VL128 + u32 w d + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVD_MASKmskw_MASKu32_APX +VL128 + i1 w mskw + u32 r mskw + +INTRINSIC_XED_IFORM_KMOVD_MASKmskw_MEMu32_APX +VL128 + i1 w mskw + u32 r d + +INTRINSIC_XED_IFORM_KMOVD_MASKmskw_GPR32u32_APX +VL128 + i1 w mskw + u32 r d + +INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_MASKu64_APX +VL128 + i1 w mskw + u64 r mskw + +INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_MEMu64_APX +VL128 + i1 w mskw + u64 r q + +INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_GPR64u64_APX +VL128 + i1 w mskw + u64 r q + +INTRINSIC_XED_IFORM_KMOVQ_GPR64u64_MASKmskw_APX +VL128 + u64 w q + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVQ_MEMu64_MASKmskw_APX +VL128 + u64 w q + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVW_MASKmskw_MASKu16_APX +VL128 + i1 w mskw + u16 r mskw + +INTRINSIC_XED_IFORM_KMOVW_MASKmskw_MEMu16_APX +VL128 + i1 w mskw + u16 r wrd + +INTRINSIC_XED_IFORM_KMOVW_MASKmskw_GPR32u32_APX +VL128 + i1 w mskw + u32 r d + +INTRINSIC_XED_IFORM_KMOVW_GPR32u32_MASKmskw_APX +VL128 + u32 w d + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVW_MEMu16_MASKmskw_APX +VL128 + u16 w wrd + i1 r mskw + +INTRINSIC_XED_IFORM_LZCNT_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LZCNT_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MOVBE_GPRv_GPRv_APX +VL128 + int w v + int r v + +INTRINSIC_XED_IFORM_MOVBE_GPRv_MEMv_APX +VL128 + int w v + int r v + +INTRINSIC_XED_IFORM_MOVBE_MEMv_GPRv_APX +VL128 + int w v + int r v + +INTRINSIC_XED_IFORM_MOVDIR64B_GPRav_MEMu32_APX +VL128 + INVALID r A_GPR_R + u32 r zd + u32 w zd + INVALID r A_GPR_R + +INTRINSIC_XED_IFORM_MOVDIRI_MEMyu_GPRyu_APX +VL128 + uint w yu + uint r yu + +INTRINSIC_XED_IFORM_MUL_GPR8i8_APX +VL128 + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MUL_MEMi8_APX +VL128 + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MUL_GPRv_APX +VL128 + int r v + INVALID rw OrAX + INVALID w OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MUL_MEMv_APX +VL128 + int r v + INVALID rw OrAX + INVALID w OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MULX_GPR32i32_GPR32i32_GPR32i32_APX +VL128 + i32 w d + i32 w d + i32 r d + u32 r d + +INTRINSIC_XED_IFORM_MULX_GPR32i32_GPR32i32_MEMi32_APX +VL128 + i32 w d + i32 w d + i32 r d + u32 r d + +INTRINSIC_XED_IFORM_MULX_GPR64i64_GPR64i64_GPR64i64_APX +VL128 + i64 w q + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_MULX_GPR64i64_GPR64i64_MEMi64_APX +VL128 + i64 w q + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_NEG_GPR8i8_APX +VL128 + i8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_MEMi8_APX +VL128 + i8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_GPR8i8_GPR8i8_APX +VL128 + i8 w b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_GPR8i8_MEMi8_APX +VL128 + i8 w b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_GPRv_APX +VL128 + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_MEMv_APX +VL128 + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NOT_GPR8i8_APX +VL128 + i8 rw b + +INTRINSIC_XED_IFORM_NOT_MEMi8_APX +VL128 + i8 rw b + +INTRINSIC_XED_IFORM_NOT_GPR8i8_GPR8i8_APX +VL128 + i8 w b + i8 r b + +INTRINSIC_XED_IFORM_NOT_GPR8i8_MEMi8_APX +VL128 + i8 w b + i8 r b + +INTRINSIC_XED_IFORM_NOT_GPRv_APX +VL128 + int rw v + +INTRINSIC_XED_IFORM_NOT_MEMv_APX +VL128 + int rw v + +INTRINSIC_XED_IFORM_NOT_GPRv_GPRv_APX +VL128 + int w v + int r v + +INTRINSIC_XED_IFORM_NOT_GPRv_MEMv_APX +VL128 + int w v + int r v + +INTRINSIC_XED_IFORM_OR_GPR8i8_GPR8i8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMi8_GPR8i8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_MEMv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8i8_GPR8i8_GPR8i8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8i8_MEMi8_GPR8i8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_GPRv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMv_GPRv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_MEMv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8i8_MEMi8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8i8_GPR8i8_MEMi8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_MEMv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8i8_GPR8i8_IMM8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8i8_MEMi8_IMM8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8i8_IMM8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMi8_IMM8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_IMMz_APX +VL128 + int rw v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMv_IMMz_APX +VL128 + int rw v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_GPRv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_MEMv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_IMM8_APX +VL128 + int rw v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMv_IMM8_APX +VL128 + int rw v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PDEP_GPR32i32_GPR32i32_GPR32i32_APX +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_PDEP_GPR32i32_GPR32i32_MEMi32_APX +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_PDEP_GPR64i64_GPR64i64_GPR64i64_APX +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_PDEP_GPR64i64_GPR64i64_MEMi64_APX +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_PEXT_GPR32i32_GPR32i32_GPR32i32_APX +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_PEXT_GPR32i32_GPR32i32_MEMi32_APX +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_PEXT_GPR64i64_GPR64i64_GPR64i64_APX +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_PEXT_GPR64i64_GPR64i64_MEMi64_APX +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_POP2_GPR64u64_GPR64u64_APX +VL128 + u64 w q + u64 w q + int rw spw2 + int r spw2 + INVALID rw SrSP + INVALID r FINAL_SSEG0 + +INTRINSIC_XED_IFORM_POP2P_GPR64u64_GPR64u64_APX +VL128 + u64 w q + u64 w q + int rw spw2 + int r spw2 + INVALID rw SrSP + INVALID r FINAL_SSEG0 + +INTRINSIC_XED_IFORM_POPCNT_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_POPCNT_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PUSH2_GPR64u64_GPR64u64_APX +VL128 + u64 r q + u64 r q + int rw spw2 + int w spw2 + INVALID rw SrSP + INVALID r FINAL_SSEG0 + +INTRINSIC_XED_IFORM_PUSH2P_GPR64u64_GPR64u64_APX +VL128 + u64 r q + u64 r q + int rw spw2 + int w spw2 + INVALID rw SrSP + INVALID r FINAL_SSEG0 + +INTRINSIC_XED_IFORM_RCL_GPR8i8_IMM8_APX +VL128 + i8 rw b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMi8_IMM8_APX +VL128 + i8 rw b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPRv_MEMv_IMM8_APX +VL128 + int w v + int r v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPR8i8_ONE_APX +VL128 + i8 rw b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMi8_ONE_APX +VL128 + i8 rw b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPR8i8_GPR8i8_ONE_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPR8i8_MEMi8_ONE_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPRv_ONE_APX +VL128 + int rw v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMv_ONE_APX +VL128 + int rw v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPRv_GPRv_ONE_APX +VL128 + int w v + int r v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPRv_MEMv_ONE_APX +VL128 + int w v + int r v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPR8i8_CL_APX +VL128 + i8 rw b + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMi8_CL_APX +VL128 + i8 rw b + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPR8i8_GPR8i8_CL_APX +VL128 + i8 w b + i8 r b + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPR8i8_MEMi8_CL_APX +VL128 + i8 w b + i8 r b + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPRv_CL_APX +VL128 + int rw v + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMv_CL_APX +VL128 + int rw v + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPRv_GPRv_CL_APX +VL128 + int w v + int r v + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPRv_MEMv_CL_APX +VL128 + int w v + int r v + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPR8i8_GPR8i8_IMM8_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPR8i8_MEMi8_IMM8_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPRv_IMM8_APX +VL128 + int rw v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMv_IMM8_APX +VL128 + int rw v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPR8i8_IMM8_APX +VL128 + i8 rw b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMi8_IMM8_APX +VL128 + i8 rw b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPRv_MEMv_IMM8_APX +VL128 + int w v + int r v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPR8i8_ONE_APX +VL128 + i8 rw b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMi8_ONE_APX +VL128 + i8 rw b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPR8i8_GPR8i8_ONE_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPR8i8_MEMi8_ONE_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPRv_ONE_APX +VL128 + int rw v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMv_ONE_APX +VL128 + int rw v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPRv_GPRv_ONE_APX +VL128 + int w v + int r v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPRv_MEMv_ONE_APX +VL128 + int w v + int r v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPR8i8_CL_APX +VL128 + i8 rw b + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMi8_CL_APX +VL128 + i8 rw b + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPR8i8_GPR8i8_CL_APX +VL128 + i8 w b + i8 r b + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPR8i8_MEMi8_CL_APX +VL128 + i8 w b + i8 r b + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPRv_CL_APX +VL128 + int rw v + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMv_CL_APX +VL128 + int rw v + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPRv_GPRv_CL_APX +VL128 + int w v + int r v + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPRv_MEMv_CL_APX +VL128 + int w v + int r v + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPR8i8_GPR8i8_IMM8_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPR8i8_MEMi8_IMM8_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPRv_IMM8_APX +VL128 + int rw v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMv_IMM8_APX +VL128 + int rw v + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPR8i8_IMM8_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMi8_IMM8_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPRv_MEMv_IMM8_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPR8i8_ONE_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMi8_ONE_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPR8i8_GPR8i8_ONE_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPR8i8_MEMi8_ONE_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPRv_ONE_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMv_ONE_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPRv_GPRv_ONE_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPRv_MEMv_ONE_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPR8i8_CL_APX +VL128 + i8 rw b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMi8_CL_APX +VL128 + i8 rw b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPR8i8_GPR8i8_CL_APX +VL128 + i8 w b + i8 r b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPR8i8_MEMi8_CL_APX +VL128 + i8 w b + i8 r b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPRv_CL_APX +VL128 + int rw v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMv_CL_APX +VL128 + int rw v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPRv_GPRv_CL_APX +VL128 + int w v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPRv_MEMv_CL_APX +VL128 + int w v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPR8i8_GPR8i8_IMM8_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPR8i8_MEMi8_IMM8_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPRv_IMM8_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMv_IMM8_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPR8i8_IMM8_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMi8_IMM8_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPRv_MEMv_IMM8_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPR8i8_ONE_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMi8_ONE_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPR8i8_GPR8i8_ONE_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPR8i8_MEMi8_ONE_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPRv_ONE_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMv_ONE_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPRv_GPRv_ONE_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPRv_MEMv_ONE_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPR8i8_CL_APX +VL128 + i8 rw b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMi8_CL_APX +VL128 + i8 rw b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPR8i8_GPR8i8_CL_APX +VL128 + i8 w b + i8 r b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPR8i8_MEMi8_CL_APX +VL128 + i8 w b + i8 r b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPRv_CL_APX +VL128 + int rw v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMv_CL_APX +VL128 + int rw v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPRv_GPRv_CL_APX +VL128 + int w v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPRv_MEMv_CL_APX +VL128 + int w v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPR8i8_GPR8i8_IMM8_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPR8i8_MEMi8_IMM8_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPRv_IMM8_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMv_IMM8_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_RORX_GPR32i32_GPR32i32_IMM8_APX +VL128 + i32 w d + i32 r d + i8 r b + +INTRINSIC_XED_IFORM_RORX_GPR32i32_MEMi32_IMM8_APX +VL128 + i32 w d + i32 r d + i8 r b + +INTRINSIC_XED_IFORM_RORX_GPR64i64_GPR64i64_IMM8_APX +VL128 + i64 w q + i64 r q + i8 r b + +INTRINSIC_XED_IFORM_RORX_GPR64i64_MEMi64_IMM8_APX +VL128 + i64 w q + i64 r q + i8 r b + +INTRINSIC_XED_IFORM_SAR_GPR8i8_IMM8_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMi8_IMM8_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPRv_MEMv_IMM8_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPR8i8_ONE_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMi8_ONE_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPR8i8_GPR8i8_ONE_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPR8i8_MEMi8_ONE_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPRv_ONE_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMv_ONE_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPRv_GPRv_ONE_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPRv_MEMv_ONE_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPR8i8_CL_APX +VL128 + i8 rw b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMi8_CL_APX +VL128 + i8 rw b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPR8i8_GPR8i8_CL_APX +VL128 + i8 w b + i8 r b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPR8i8_MEMi8_CL_APX +VL128 + i8 w b + i8 r b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPRv_CL_APX +VL128 + int rw v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMv_CL_APX +VL128 + int rw v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPRv_GPRv_CL_APX +VL128 + int w v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPRv_MEMv_CL_APX +VL128 + int w v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPR8i8_GPR8i8_IMM8_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPR8i8_MEMi8_IMM8_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPRv_IMM8_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMv_IMM8_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SARX_GPR32i32_GPR32i32_GPR32i32_APX +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SARX_GPR32i32_MEMi32_GPR32i32_APX +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SARX_GPR64i64_GPR64i64_GPR64i64_APX +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SARX_GPR64i64_MEMi64_GPR64i64_APX +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SBB_GPR8i8_GPR8i8_APX +VL128 + i8 rw b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMi8_GPR8i8_APX +VL128 + i8 rw b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_MEMv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8i8_GPR8i8_GPR8i8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8i8_MEMi8_GPR8i8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_APX +VL128 + int rw v + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMv_GPRv_APX +VL128 + int rw v + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_MEMv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8i8_MEMi8_APX +VL128 + i8 rw b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8i8_GPR8i8_MEMi8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_MEMv_APX +VL128 + int rw v + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8i8_GPR8i8_IMM8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8i8_MEMi8_IMM8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8i8_IMM8_APX +VL128 + i8 rw b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMi8_IMM8_APX +VL128 + i8 rw b + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_IMMz_APX +VL128 + int rw v + int r z + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMv_IMMz_APX +VL128 + int rw v + int r z + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_MEMv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_IMM8_APX +VL128 + int rw v + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMv_IMM8_APX +VL128 + int rw v + i8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SETB_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETB_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETBE_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETBE_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETL_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETL_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETLE_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETLE_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNB_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNB_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNBE_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNBE_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNL_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNL_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNLE_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNLE_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNO_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNO_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNP_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNP_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNS_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNS_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNZ_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNZ_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETO_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETO_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETP_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETP_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETS_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETS_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETZ_GPR8i8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETZ_MEMi8_APX +VL128 + i8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8i8_IMM8_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMi8_IMM8_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_GPRv_ONE_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_MEMv_ONE_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8i8_CL_APX +VL128 + i8 rw b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMi8_CL_APX +VL128 + i8 rw b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8i8_GPR8i8_CL_APX +VL128 + i8 w b + i8 r b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8i8_MEMi8_CL_APX +VL128 + i8 w b + i8 r b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_CL_APX +VL128 + int rw v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMv_CL_APX +VL128 + int rw v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8i8_ONE_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMi8_ONE_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_GPRv_CL_APX +VL128 + int w v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_MEMv_CL_APX +VL128 + int w v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8i8_GPR8i8_IMM8_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8i8_MEMi8_IMM8_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_IMM8_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMv_IMM8_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8i8_GPR8i8_ONE_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8i8_MEMi8_ONE_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_MEMv_IMM8_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_ONE_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMv_ONE_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_IMM8_APX +VL128 + int rcw v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHLD_MEMv_GPRv_IMM8_APX +VL128 + int rcw v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHLD_GPRv_MEMv_GPRv_IMM8_APX +VL128 + int w v + int r v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_CL_APX +VL128 + int rcw v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHLD_MEMv_GPRv_CL_APX +VL128 + int rcw v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_GPRv_CL_APX +VL128 + int w v + int r v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHLD_GPRv_MEMv_GPRv_CL_APX +VL128 + int w v + int r v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHLX_GPR32i32_GPR32i32_GPR32i32_APX +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SHLX_GPR32i32_MEMi32_GPR32i32_APX +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SHLX_GPR64i64_GPR64i64_GPR64i64_APX +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SHLX_GPR64i64_MEMi64_GPR64i64_APX +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SHR_GPR8i8_IMM8_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMi8_IMM8_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPRv_MEMv_IMM8_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPR8i8_ONE_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMi8_ONE_APX +VL128 + i8 rw b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPR8i8_GPR8i8_ONE_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPR8i8_MEMi8_ONE_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPRv_ONE_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMv_ONE_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPRv_GPRv_ONE_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPRv_MEMv_ONE_APX +VL128 + int w v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPR8i8_CL_APX +VL128 + i8 rw b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMi8_CL_APX +VL128 + i8 rw b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPR8i8_GPR8i8_CL_APX +VL128 + i8 w b + i8 r b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPR8i8_MEMi8_CL_APX +VL128 + i8 w b + i8 r b + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPRv_CL_APX +VL128 + int rw v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMv_CL_APX +VL128 + int rw v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPRv_GPRv_CL_APX +VL128 + int w v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPRv_MEMv_CL_APX +VL128 + int w v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPR8i8_GPR8i8_IMM8_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPR8i8_MEMi8_IMM8_APX +VL128 + i8 w b + i8 r b + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPRv_IMM8_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMv_IMM8_APX +VL128 + int rw v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_IMM8_APX +VL128 + int rcw v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHRD_MEMv_GPRv_IMM8_APX +VL128 + int rcw v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHRD_GPRv_MEMv_GPRv_IMM8_APX +VL128 + int w v + int r v + int r v + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_CL_APX +VL128 + int rcw v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHRD_MEMv_GPRv_CL_APX +VL128 + int rcw v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_GPRv_CL_APX +VL128 + int w v + int r v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHRD_GPRv_MEMv_GPRv_CL_APX +VL128 + int w v + int r v + int r v + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHRX_GPR32i32_GPR32i32_GPR32i32_APX +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SHRX_GPR32i32_MEMi32_GPR32i32_APX +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SHRX_GPR64i64_GPR64i64_GPR64i64_APX +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SHRX_GPR64i64_MEMi64_GPR64i64_APX +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SUB_GPR8i8_GPR8i8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMi8_GPR8i8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_MEMv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8i8_GPR8i8_GPR8i8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8i8_MEMi8_GPR8i8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_GPRv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMv_GPRv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_MEMv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8i8_MEMi8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8i8_GPR8i8_MEMi8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_MEMv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8i8_GPR8i8_IMM8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8i8_MEMi8_IMM8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8i8_IMM8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMi8_IMM8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_IMMz_APX +VL128 + int rw v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMv_IMMz_APX +VL128 + int rw v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_GPRv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_MEMv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_IMM8_APX +VL128 + int rw v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMv_IMM8_APX +VL128 + int rw v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TZCNT_GPRv_GPRv_APX +VL128 + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TZCNT_GPRv_MEMv_APX +VL128 + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_URDMSR_GPR64u64_GPR64u64_APX +VL128 + u64 w q + u64 r q + +INTRINSIC_XED_IFORM_URDMSR_GPR64u64_IMM32_APX +VL128 + u64 w q + i32 r d + +INTRINSIC_XED_IFORM_UWRMSR_GPR64u64_GPR64u64_APX +VL128 + u64 r q + u64 r q + +INTRINSIC_XED_IFORM_UWRMSR_IMM32_GPR64u64_APX +VL128 + i32 r d + u64 r q + +INTRINSIC_XED_IFORM_WRSSD_MEMu32_GPR32u32_APX +VL128 + u32 w d + u32 r d + +INTRINSIC_XED_IFORM_WRSSQ_MEMu64_GPR64u64_APX +VL128 + u64 w q + u64 r q + +INTRINSIC_XED_IFORM_WRUSSD_MEMu32_GPR32u32_APX +VL128 + u32 w d + u32 r d + +INTRINSIC_XED_IFORM_WRUSSQ_MEMu64_GPR64u64_APX +VL128 + u64 w q + u64 r q + +INTRINSIC_XED_IFORM_XOR_GPR8i8_GPR8i8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMi8_GPR8i8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_GPRv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_MEMv_IMM8_APX +VL128 + int w v + int r v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8i8_GPR8i8_GPR8i8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8i8_MEMi8_GPR8i8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_GPRv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMv_GPRv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_GPRv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_MEMv_GPRv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8i8_MEMi8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8i8_GPR8i8_MEMi8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_MEMv_APX +VL128 + int rw v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8i8_GPR8i8_IMM8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8i8_MEMi8_IMM8_APX +VL128 + i8 w b + i8 r b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_GPRv_MEMv_APX +VL128 + int w v + int r v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8i8_IMM8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMi8_IMM8_APX +VL128 + i8 rw b + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_IMMz_APX +VL128 + int rw v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMv_IMMz_APX +VL128 + int rw v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_GPRv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_MEMv_IMMz_APX +VL128 + int w v + int r v + int r z + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_IMM8_APX +VL128 + int rw v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMv_IMM8_APX +VL128 + int rw v + i8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LDTILECFG_MEM_APX +VL128 + struct r m512 + +INTRINSIC_XED_IFORM_STTILECFG_MEM_APX +VL128 + struct w m512 + +INTRINSIC_XED_IFORM_TILELOADD_TMMu32_MEMu32_APX +VL128 + u32 w tv + u32 r ptr + +INTRINSIC_XED_IFORM_TILELOADDT1_TMMu32_MEMu32_APX +VL128 + u32 w tv + u32 r ptr + +INTRINSIC_XED_IFORM_TILESTORED_MEMu32_TMMu32_APX +VL128 + u32 w ptr + u32 r tv + diff --git a/arch/x86/code_generator/parse-iform-types.py b/arch/x86/code_generator/parse-iform-types.py index 27631d2a..68336154 100755 --- a/arch/x86/code_generator/parse-iform-types.py +++ b/arch/x86/code_generator/parse-iform-types.py @@ -381,8 +381,22 @@ class Operand(): self.element_size = self.width elif self.xtype == 'int': self.element_size = 32 + elif self.xtype == 'uint': + self.element_size = 32 elif self.xtype == 'bf16': self.element_size = 16 + elif self.xtype == '2bf16': + self.element_size = 32 + elif self.xtype == '2f16': + self.element_size = 32 + elif self.xtype == '2i16': + self.element_size = 32 + elif self.xtype == '2u16': + self.element_size = 32 + elif self.xtype == '4i8': + self.element_size = 32 + elif self.xtype == '4u8': + self.element_size = 32 else: size_str = self.xtype[1:] self.element_size = int(size_str) |