diff options
| author | Rusty Wagner <rusty.wagner@gmail.com> | 2024-03-05 19:50:13 -0500 |
|---|---|---|
| committer | Rusty Wagner <rusty.wagner@gmail.com> | 2024-03-05 20:34:34 -0500 |
| commit | e093c21ed880ac3eb72119be15093ee04f8ce299 (patch) | |
| tree | 9f720ebdc0ae415734b1199ed341668c69710a94 /arch/x86/code_generator | |
| parent | 0609276712622908254065546102381466033141 (diff) | |
Move architecture modules into the API repo
Diffstat (limited to 'arch/x86/code_generator')
| -rw-r--r-- | arch/x86/code_generator/README.md | 11 | ||||
| -rw-r--r-- | arch/x86/code_generator/iform-type-dump.txt | 35791 | ||||
| -rwxr-xr-x | arch/x86/code_generator/parse-iform-types.py | 452 | ||||
| -rw-r--r-- | arch/x86/code_generator/patch.diff | 43 |
4 files changed, 36297 insertions, 0 deletions
diff --git a/arch/x86/code_generator/README.md b/arch/x86/code_generator/README.md new file mode 100644 index 00000000..5c53ad1f --- /dev/null +++ b/arch/x86/code_generator/README.md @@ -0,0 +1,11 @@ +This README explains the process of generating the input and output type information for x86 intrinsics. + +It takes two major steps: + +1. Tweak the xed build process and generate the information for each iform. + - Apply the `patch.diff` to `$XED_SOURCE/pysrc/generator.py` + - Build xed and harvest the `iform-type-dump.txt` + - Copy the `iform-type-dump.txt` to the current folder + +2. run the `parse-iform-types.py` + - It will generate `../x86_intrinsic_input_type.cpp` and `../x86_intrinsic_output_type.cpp`.
\ No newline at end of file diff --git a/arch/x86/code_generator/iform-type-dump.txt b/arch/x86/code_generator/iform-type-dump.txt new file mode 100644 index 00000000..b34b2211 --- /dev/null +++ b/arch/x86/code_generator/iform-type-dump.txt @@ -0,0 +1,35791 @@ +INTRINSIC_XED_IFORM_FADD_ST0_MEMmem32real + f80 rw f80 + f32 r mem32real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FADD_ST0_X87 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FADD_ST0_MEMm64real + f80 rw f80 + f64 r m64real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FADD_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FMUL_ST0_MEMmem32real + f80 rw f80 + f32 r mem32real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FMUL_ST0_X87 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FMUL_ST0_MEMm64real + f80 rw f80 + f64 r m64real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FMUL_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOMP_ST0_MEMmem32real + f80 r f80 + f32 r mem32real + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOMP_ST0_X87 + f80 r f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOMP_ST0_X87_DCD1 + f80 r f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOMP_ST0_X87_DED0 + f80 r f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOMP_ST0_MEMm64real + f80 r f80 + f64 r m64real + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUB_ST0_MEMmem32real + f80 rw f80 + f32 r mem32real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUB_ST0_X87 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUB_ST0_MEMm64real + f80 rw f80 + f64 r m64real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUB_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUBR_ST0_MEMmem32real + f80 rw f80 + f32 r mem32real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUBR_ST0_X87 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUBR_ST0_MEMm64real + f80 rw f80 + f64 r m64real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUBR_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIV_ST0_MEMmem32real + f80 rw f80 + f32 r mem32real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIV_ST0_X87 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIV_ST0_MEMm64real + f80 rw f80 + f64 r m64real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIV_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIVR_ST0_MEMmem32real + f80 rw f80 + f32 r mem32real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIVR_ST0_X87 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIVR_ST0_MEMm64real + f80 rw f80 + f64 r m64real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIVR_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOM_ST0_MEMmem32real + f80 r f80 + f32 r mem32real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOM_ST0_MEMm64real + f80 r f80 + f64 r m64real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOM_ST0_X87 + f80 r f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOM_ST0_X87_DCD0 + f80 r f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLD_ST0_MEMmem32real + f80 w f80 + f32 r mem32real + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLD_ST0_X87 + f80 w f80 + f80 r f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLD_ST0_MEMmem80real + f80 w f80 + f80 r mem80real + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLD_ST0_MEMm64real + f80 w f80 + f64 r m64real + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FST_MEMmem32real_ST0 + f32 w mem32real + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FST_MEMm64real_ST0 + f64 w m64real + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FST_X87_ST0 + f80 w f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSTP_MEMmem32real_ST0 + f32 w mem32real + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSTP_MEMmem80real_ST0 + f80 w mem80real + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSTP_MEMm64real_ST0 + f64 w m64real + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSTP_X87_ST0 + f80 w f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSTP_X87_ST0_DFD0 + f80 w f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSTP_X87_ST0_DFD1 + f80 w f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSTPNCE_X87_ST0 + f80 w f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDENV_MEMmem14 + struct r mem14 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDENV_MEMmem28 + struct r mem28 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDCW_MEMmem16 + struct r mem16 + INVALID w XED_REG_X87CONTROL + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNSTENV_MEMmem14 + struct w mem14 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNSTENV_MEMmem28 + struct w mem28 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNSTCW_MEMmem16 + struct w mem16 + INVALID r XED_REG_X87CONTROL + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FXCH_ST0_X87 + f80 rw f80 + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FXCH_ST0_X87_DFC1 + f80 rw f80 + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FXCH_ST0_X87_DDC1 + f80 rw f80 + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNOP + +INTRINSIC_XED_IFORM_FCHS + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FABS + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FTST + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FXAM + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLD1 + f80 w f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDL2T + f80 w f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDL2E + f80 w f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDPI + f80 w f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDLG2 + f80 w f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDLN2 + f80 w f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDZ + f80 w f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_F2XM1 + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FYL2X + f80 r f80 + f80 rw f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FPTAN + f80 rw f80 + f80 w f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FPATAN + f80 r f80 + f80 rw f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FXTRACT + f80 rw f80 + f80 w f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FPREM1 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDECSTP + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FINCSTP + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FPREM + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FYL2XP1 + f80 r f80 + f80 rw f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSQRT + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSINCOS + f80 rw f80 + f80 w f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FRNDINT + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSCALE + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSIN + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOS + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIADD_ST0_MEMmem32int + f80 rw f80 + i32 r mem32int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIADD_ST0_MEMmem16int + f80 rw f80 + i16 r mem16int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIMUL_ST0_MEMmem32int + f80 rw f80 + i32 r mem32int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIMUL_ST0_MEMmem16int + f80 rw f80 + i16 r mem16int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FICOM_ST0_MEMmem32int + f80 r f80 + i32 r mem32int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FICOM_ST0_MEMmem16int + f80 r f80 + i16 r mem16int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FICOMP_ST0_MEMmem32int + f80 r f80 + i32 r mem32int + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FICOMP_ST0_MEMmem16int + f80 r f80 + i16 r mem16int + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISUB_ST0_MEMmem32int + f80 rw f80 + i32 r mem32int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISUB_ST0_MEMmem16int + f80 rw f80 + i16 r mem16int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISUBR_ST0_MEMmem32int + f80 rw f80 + i32 r mem32int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISUBR_ST0_MEMmem16int + f80 rw f80 + i16 r mem16int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIDIV_ST0_MEMmem32int + f80 rw f80 + i32 r mem32int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIDIV_ST0_MEMmem16int + f80 rw f80 + i16 r mem16int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIDIVR_ST0_MEMmem32int + f80 rw f80 + i32 r mem32int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIDIVR_ST0_MEMmem16int + f80 rw f80 + i16 r mem16int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCMOVB_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FCMOVE_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FCMOVBE_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FCMOVU_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FUCOMPP + f80 r f80 + f80 r f80 + INVALID rw XED_REG_X87POP2 + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FILD_ST0_MEMmem32int + f80 w f80 + i32 r mem32int + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FILD_ST0_MEMmem16int + f80 w f80 + i16 r mem16int + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FILD_ST0_MEMm64int + f80 w f80 + i64 r m64int + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISTTP_MEMmem32int_ST0 + i32 w mem32int + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISTTP_MEMm64int_ST0 + i64 w m64int + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISTTP_MEMmem16int_ST0 + i16 w mem16int + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIST_MEMmem32int_ST0 + i32 w mem32int + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIST_MEMmem16int_ST0 + i16 w mem16int + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISTP_MEMmem32int_ST0 + i32 w mem32int + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISTP_MEMmem16int_ST0 + i16 w mem16int + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISTP_MEMm64int_ST0 + i64 w m64int + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCMOVNB_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FCMOVNE_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FCMOVNBE_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FCMOVNU_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FNCLEX + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNINIT + INVALID w XED_REG_X87CONTROL + INVALID w XED_REG_X87TAG + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSETPM287_NOP + +INTRINSIC_XED_IFORM_FENI8087_NOP + +INTRINSIC_XED_IFORM_FDISI8087_NOP + +INTRINSIC_XED_IFORM_FUCOMI_ST0_X87 + f80 r f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_FCOMI_ST0_X87 + f80 r f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_FRSTOR_MEMmem94 + struct r mem94 + INVALID w XED_REG_X87CONTROL + +INTRINSIC_XED_IFORM_FRSTOR_MEMmem108 + struct r mem108 + INVALID w XED_REG_X87CONTROL + +INTRINSIC_XED_IFORM_FNSAVE_MEMmem94 + struct w mem94 + INVALID rw XED_REG_X87CONTROL + INVALID rw XED_REG_X87TAG + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNSAVE_MEMmem108 + struct w mem108 + INVALID rw XED_REG_X87CONTROL + INVALID rw XED_REG_X87TAG + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNSTSW_MEMmem16 + struct w mem16 + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNSTSW_AX + INVALID w XED_REG_AX + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FFREE_X87 + f80 r f80 + INVALID w XED_REG_X87TAG + +INTRINSIC_XED_IFORM_FUCOM_ST0_X87 + f80 r f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FUCOMP_ST0_X87 + f80 r f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FADDP_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FMULP_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOMPP + f80 r f80 + f80 r f80 + INVALID r XED_REG_X87POP2 + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUBRP_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUBP_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIVRP_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIVP_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FBLD_ST0_MEMmem80dec + f80 w f80 + b80 r mem80dec + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FBSTP_MEMmem80dec_ST0 + b80 w mem80dec + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FFREEP_X87 + f80 r f80 + INVALID w XED_REG_X87TAG + INVALID r XED_REG_X87POP + +INTRINSIC_XED_IFORM_FUCOMIP_ST0_X87 + f80 r f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_FCOMIP_ST0_X87 + f80 r f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMb_IMMb_80r0 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8_IMMb_80r0 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_IMMz + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMb_IMMb_82r0 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8_IMMb_82r0 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8_GPR8_00 + INVALID rw GPR8_B + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_01 + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8_MEMb + INVALID rw GPR8_R + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8_GPR8_02 + INVALID rw GPR8_R + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_03 + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_AL_IMMb + INVALID rw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_OrAX_IMMz + INVALID rw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_LOCK_MEMb_IMMb_80r1 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_LOCK_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_LOCK_MEMb_IMMb_82r1 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_LOCK_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMb_IMMb_80r1 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8_IMMb_80r1 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_IMMz + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMb_IMMb_82r1 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8_IMMb_82r1 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8_GPR8_08 + INVALID rw GPR8_B + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_GPRv_09 + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8_MEMb + INVALID rw GPR8_R + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8_GPR8_0A + INVALID rw GPR8_R + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_GPRv_0B + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_AL_IMMb + INVALID rw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_OrAX_IMMz + INVALID rw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_IMMz + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_IMMb + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMb_IMMb_80r2 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8_IMMb_80r2 + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMv_IMMz + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_IMMz + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMb_IMMb_82r2 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8_IMMb_82r2 + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMv_IMMb + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_IMMb + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8_GPR8_10 + INVALID rw GPR8_B + INVALID r GPR8_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_11 + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8_MEMb + INVALID rw GPR8_R + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8_GPR8_12 + INVALID rw GPR8_R + INVALID r GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_13 + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_AL_IMMb + INVALID rw XED_REG_AL + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_OrAX_IMMz + INVALID rw OrAX + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_IMMz + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_IMMb + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMb_IMMb_80r3 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8_IMMb_80r3 + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMv_IMMz + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_IMMz + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMb_IMMb_82r3 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8_IMMb_82r3 + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMv_IMMb + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_IMMb + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8_GPR8_18 + INVALID rw GPR8_B + INVALID r GPR8_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_19 + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8_GPR8_1A + INVALID rw GPR8_R + INVALID r GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8_MEMb + INVALID rw GPR8_R + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_1B + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_AL_IMMb + INVALID rw XED_REG_AL + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_OrAX_IMMz + INVALID rw OrAX + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_AND_LOCK_MEMb_IMMb_80r4 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_LOCK_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_LOCK_MEMb_IMMb_82r4 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_LOCK_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMb_IMMb_80r4 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8_IMMb_80r4 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_IMMz + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMb_IMMb_82r4 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8_IMMb_82r4 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8_GPR8_20 + INVALID rw GPR8_B + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_GPRv_21 + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8_GPR8_22 + INVALID rw GPR8_R + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8_MEMb + INVALID rw GPR8_R + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_GPRv_23 + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_AL_IMMb + INVALID rw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_OrAX_IMMz + INVALID rw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMb_IMMb_80r5 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8_IMMb_80r5 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_IMMz + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMb_IMMb_82r5 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8_IMMb_82r5 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8_GPR8_28 + INVALID rw GPR8_B + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_GPRv_29 + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8_GPR8_2A + INVALID rw GPR8_R + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8_MEMb + INVALID rw GPR8_R + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_GPRv_2B + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_AL_IMMb + INVALID rw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_OrAX_IMMz + INVALID rw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMb_IMMb_80r6 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8_IMMb_80r6 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_IMMz + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMb_IMMb_82r6 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8_IMMb_82r6 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8_GPR8_30 + INVALID rw GPR8_B + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_GPRv_31 + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8_GPR8_32 + INVALID rw GPR8_R + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8_MEMb + INVALID rw GPR8_R + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_GPRv_33 + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_AL_IMMb + INVALID rw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_OrAX_IMMz + INVALID rw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_MEMb_IMMb_80r7 + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPR8_IMMb_80r7 + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_MEMv_IMMz + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPRv_IMMz + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_MEMb_IMMb_82r7 + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPR8_IMMb_82r7 + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_MEMv_IMMb + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPRv_IMMb + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_MEMb_GPR8 + u8 r b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPR8_GPR8_38 + INVALID r GPR8_B + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_MEMv_GPRv + int r v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPRv_GPRv_39 + INVALID r GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPR8_MEMb + INVALID r GPR8_R + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPR8_GPR8_3A + INVALID r GPR8_R + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPRv_MEMv + INVALID r GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPRv_GPRv_3B + INVALID r GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_AL_IMMb + INVALID r XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_OrAX_IMMz + INVALID r OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_POP_MEMv + int w v + int r spw + int r spw + +INTRINSIC_XED_IFORM_POP_GPRv_8F + INVALID w GPRv_B + int r spw + int r spw + +INTRINSIC_XED_IFORM_POP_ES + INVALID w XED_REG_ES + int r spw + int r spw + +INTRINSIC_XED_IFORM_POP_SS + INVALID w XED_REG_SS + int r spw + int r spw + +INTRINSIC_XED_IFORM_POP_DS + INVALID w XED_REG_DS + int r spw + int r spw + +INTRINSIC_XED_IFORM_POP_GPRv_58 + INVALID w GPRv_SB + int r spw + int r spw + +INTRINSIC_XED_IFORM_POP_FS + INVALID w XED_REG_FS + int r spw + int r spw + +INTRINSIC_XED_IFORM_POP_GS + INVALID w XED_REG_GS + int r spw + int r spw + +INTRINSIC_XED_IFORM_ROL_MEMb_IMMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPR8_IMMb + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMb_ONE + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPR8_ONE + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMv_ONE + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPRv_ONE + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMb_CL + u8 rw b + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPR8_CL + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMv_CL + int rw v + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPRv_CL + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMb_IMMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPR8_IMMb + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMb_ONE + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPR8_ONE + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMv_ONE + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPRv_ONE + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMb_CL + u8 rw b + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPR8_CL + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMv_CL + int rw v + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPRv_CL + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMb_IMMb + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPR8_IMMb + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMv_IMMb + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPRv_IMMb + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMb_ONE + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPR8_ONE + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMv_ONE + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPRv_ONE + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMb_CL + u8 rw b + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPR8_CL + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMv_CL + int rw v + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPRv_CL + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMb_IMMb + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPR8_IMMb + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMv_IMMb + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPRv_IMMb + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMb_ONE + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPR8_ONE + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMv_ONE + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPRv_ONE + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMb_CL + u8 rw b + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPR8_CL + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMv_CL + int rw v + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPRv_CL + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMb_IMMb_C0r4 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8_IMMb_C0r4 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMb_IMMb_C0r6 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8_IMMb_C0r6 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMv_IMMb_C1r4 + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_IMMb_C1r4 + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMv_IMMb_C1r6 + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_IMMb_C1r6 + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMb_ONE_D0r4 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8_ONE_D0r4 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMb_ONE_D0r6 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8_ONE_D0r6 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMv_ONE_D1r6 + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_ONE_D1r6 + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMv_ONE_D1r4 + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_ONE_D1r4 + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMb_CL_D2r4 + u8 rw b + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8_CL_D2r4 + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMb_CL_D2r6 + u8 rw b + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8_CL_D2r6 + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMv_CL_D3r4 + int rw v + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_CL_D3r4 + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMv_CL_D3r6 + int rw v + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_CL_D3r6 + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMb_IMMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPR8_IMMb + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMb_ONE + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPR8_ONE + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMv_ONE + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPRv_ONE + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMb_CL + u8 rw b + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPR8_CL + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMv_CL + int rw v + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPRv_CL + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMb_IMMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPR8_IMMb + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMb_ONE + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPR8_ONE + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMv_ONE + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPRv_ONE + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMb_CL + u8 rw b + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPR8_CL + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMv_CL + int rw v + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPRv_CL + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_TEST_MEMb_IMMb_F6r0 + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_MEMb_IMMb_F6r1 + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_GPR8_IMMb_F6r0 + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_GPR8_IMMb_F6r1 + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_MEMv_IMMz_F7r0 + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_MEMv_IMMz_F7r1 + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_GPRv_IMMz_F7r0 + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_GPRv_IMMz_F7r1 + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_MEMb_GPR8 + u8 r b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_GPR8_GPR8 + INVALID r GPR8_B + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_MEMv_GPRv + int r v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_GPRv_GPRv + INVALID r GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_AL_IMMb + INVALID r XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_OrAX_IMMz + INVALID r OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NOT_LOCK_MEMb + u8 rw b + +INTRINSIC_XED_IFORM_NOT_LOCK_MEMv + int rw v + +INTRINSIC_XED_IFORM_NOT_MEMb + u8 rw b + +INTRINSIC_XED_IFORM_NOT_GPR8 + INVALID rw GPR8_B + +INTRINSIC_XED_IFORM_NOT_MEMv + int rw v + +INTRINSIC_XED_IFORM_NOT_GPRv + INVALID rw GPRv_B + +INTRINSIC_XED_IFORM_NEG_LOCK_MEMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_LOCK_MEMv + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_MEMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_GPR8 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_MEMv + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_GPRv + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MUL_MEMb + u8 r b + INVALID r XED_REG_AL + INVALID w XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MUL_GPR8 + INVALID r GPR8_B + INVALID r XED_REG_AL + INVALID w XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MUL_MEMv + int r v + INVALID rw OrAX + INVALID w OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MUL_GPRv + INVALID r GPRv_B + INVALID rw OrAX + INVALID w OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_MEMb + u8 r b + INVALID r XED_REG_AL + INVALID w XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPR8 + INVALID r GPR8_B + INVALID r XED_REG_AL + INVALID w XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_MEMv + int r v + INVALID rw OrAX + INVALID w OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv + INVALID r GPRv_B + INVALID rw OrAX + INVALID w OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv_IMMz + INVALID w GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_IMMz + INVALID w GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv_IMMb + INVALID w GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_IMMb + INVALID w GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DIV_MEMb + u8 r b + INVALID rw XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DIV_GPR8 + INVALID r GPR8_B + INVALID rw XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DIV_MEMv + int r v + INVALID rw OrAX + INVALID rw OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DIV_GPRv + INVALID r GPRv_B + INVALID rw OrAX + INVALID rw OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IDIV_MEMb + u8 r b + INVALID rw XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IDIV_GPR8 + INVALID r GPR8_B + INVALID rw XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IDIV_MEMv + int r v + INVALID rw OrAX + INVALID rw OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IDIV_GPRv + INVALID r GPRv_B + INVALID rw OrAX + INVALID rw OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_LOCK_MEMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_LOCK_MEMv + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_MEMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_GPR8 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_MEMv + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_GPRv_FFr0 + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_GPRv_40 + INVALID rw GPRv_SB + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_LOCK_MEMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_LOCK_MEMv + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_MEMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_GPR8 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_MEMv + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_GPRv_FFr1 + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_GPRv_48 + INVALID rw GPRv_SB + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CALL_NEAR_MEMv + int r v + int w spw + INVALID rw rIP + int w spw + +INTRINSIC_XED_IFORM_CALL_NEAR_GPRv + INVALID r GPRv_B + int w spw + INVALID rw rIP + int w spw + +INTRINSIC_XED_IFORM_CALL_NEAR_RELBRz + int w spw + INVALID rw XED_REG_EIP + int w spw + +INTRINSIC_XED_IFORM_CALL_NEAR_RELBRd + int w spw + INVALID rw XED_REG_RIP + int w spw + +INTRINSIC_XED_IFORM_JMP_MEMv + int r v + INVALID w rIP + +INTRINSIC_XED_IFORM_JMP_GPRv + INVALID r GPRv_B + INVALID w rIP + +INTRINSIC_XED_IFORM_JMP_RELBRz + INVALID rw XED_REG_EIP + +INTRINSIC_XED_IFORM_JMP_RELBRd + INVALID rw XED_REG_RIP + +INTRINSIC_XED_IFORM_JMP_RELBRb + INVALID rw XED_REG_EIP + +INTRINSIC_XED_IFORM_JMP_FAR_MEMp2 + struct r p2 + INVALID w rIP + +INTRINSIC_XED_IFORM_JMP_FAR_PTRp_IMMw + INVALID w XED_REG_EIP + +INTRINSIC_XED_IFORM_PUSH_MEMv + int r v + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_GPRv_FFr6 + INVALID r GPRv_B + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_ES + INVALID r XED_REG_ES + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_CS + INVALID r XED_REG_CS + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_SS + INVALID r XED_REG_SS + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_DS + INVALID r XED_REG_DS + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_GPRv_50 + INVALID r GPRv_SB + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_IMMz + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_IMMb + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_FS + INVALID r XED_REG_FS + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_GS + INVALID r XED_REG_GS + int w spw + int w spw + +INTRINSIC_XED_IFORM_SLDT_MEMw + i16 w w + INVALID r XED_REG_LDTR + +INTRINSIC_XED_IFORM_SLDT_GPRv + INVALID w GPRv_B + INVALID r XED_REG_LDTR + +INTRINSIC_XED_IFORM_STR_MEMw + i16 w w + INVALID r XED_REG_TR + +INTRINSIC_XED_IFORM_STR_GPRv + INVALID w GPRv_B + INVALID r XED_REG_TR + +INTRINSIC_XED_IFORM_LLDT_MEMw + i16 r w + INVALID w XED_REG_LDTR + +INTRINSIC_XED_IFORM_LLDT_GPR16 + INVALID r GPR16_B + INVALID w XED_REG_LDTR + +INTRINSIC_XED_IFORM_LTR_MEMw + i16 r w + INVALID w XED_REG_TR + +INTRINSIC_XED_IFORM_LTR_GPR16 + INVALID r GPR16_B + INVALID w XED_REG_TR + +INTRINSIC_XED_IFORM_VERR_MEMw + i16 r w + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VERR_GPR16 + INVALID r GPR16_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VERW_MEMw + i16 r w + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VERW_GPR16 + INVALID r GPR16_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LGDT_MEMs64 + struct r s64 + INVALID w XED_REG_GDTR + +INTRINSIC_XED_IFORM_LGDT_MEMs + struct r s + INVALID w XED_REG_GDTR + +INTRINSIC_XED_IFORM_SMSW_MEMw + i16 w w + INVALID r XED_REG_CR0 + +INTRINSIC_XED_IFORM_SMSW_GPRv + INVALID w GPRv_B + INVALID r XED_REG_CR0 + +INTRINSIC_XED_IFORM_LMSW_MEMw + i16 r w + INVALID w XED_REG_CR0 + +INTRINSIC_XED_IFORM_LMSW_GPR16 + INVALID r GPR16_B + INVALID w XED_REG_CR0 + +INTRINSIC_XED_IFORM_BT_MEMv_IMMb + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BT_GPRv_IMMb + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BT_MEMv_GPRv + int r v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BT_GPRv_GPRv + INVALID r GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTS_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTS_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTS_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTS_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTS_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTS_GPRv_GPRv + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTR_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTR_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTR_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTR_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTR_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTR_GPRv_GPRv + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTC_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTC_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTC_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTC_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTC_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTC_GPRv_GPRv + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMCLEAR_MEMq + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMPTRLD_MEMq + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMPTRST_MEMq + i64 w q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMXON_MEMq + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG8B_LOCK_MEMq + i64 rcw q + INVALID rcw XED_REG_EDX + INVALID rcw XED_REG_EAX + INVALID r XED_REG_ECX + INVALID r XED_REG_EBX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG8B_MEMq + i64 rcw q + INVALID rcw XED_REG_EDX + INVALID rcw XED_REG_EAX + INVALID r XED_REG_ECX + INVALID r XED_REG_EBX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG16B_LOCK_MEMdq + i32 rcw dq + INVALID rcw XED_REG_RDX + INVALID rcw XED_REG_RAX + INVALID r XED_REG_RCX + INVALID r XED_REG_RBX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG16B_MEMdq + i32 rcw dq + INVALID rcw XED_REG_RDX + INVALID rcw XED_REG_RAX + INVALID r XED_REG_RCX + INVALID r XED_REG_RBX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MOV_GPR8_IMMb_C6r0 + INVALID w GPR8_B + +INTRINSIC_XED_IFORM_MOV_MEMb_IMMb + u8 w b + +INTRINSIC_XED_IFORM_MOV_GPRv_IMMz + INVALID w GPRv_B + +INTRINSIC_XED_IFORM_MOV_MEMv_IMMz + int w v + +INTRINSIC_XED_IFORM_MOV_GPR8_GPR8_88 + INVALID w GPR8_B + INVALID r GPR8_R + +INTRINSIC_XED_IFORM_MOV_MEMb_GPR8 + u8 w b + INVALID r GPR8_R + +INTRINSIC_XED_IFORM_MOV_MEMv_GPRv + int w v + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_MOV_GPRv_GPRv_89 + INVALID w GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_MOV_GPR8_MEMb + INVALID w GPR8_R + u8 r b + +INTRINSIC_XED_IFORM_MOV_GPR8_GPR8_8A + INVALID w GPR8_R + INVALID r GPR8_B + +INTRINSIC_XED_IFORM_MOV_GPRv_MEMv + INVALID w GPRv_R + int r v + +INTRINSIC_XED_IFORM_MOV_GPRv_GPRv_8B + INVALID w GPRv_R + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_MOV_MEMw_SEG + i16 w w + INVALID r SEG + +INTRINSIC_XED_IFORM_MOV_GPRv_SEG + INVALID w GPRv_B + INVALID r SEG + +INTRINSIC_XED_IFORM_MOV_SEG_MEMw + INVALID w SEG_MOV + i16 r w + +INTRINSIC_XED_IFORM_MOV_SEG_GPR16 + INVALID w SEG_MOV + INVALID r GPR16_B + +INTRINSIC_XED_IFORM_MOV_AL_MEMb + INVALID w XED_REG_AL + u8 r b + +INTRINSIC_XED_IFORM_MOV_OrAX_MEMv + INVALID w OrAX + int r v + +INTRINSIC_XED_IFORM_MOV_MEMb_AL + u8 w b + INVALID r XED_REG_AL + +INTRINSIC_XED_IFORM_MOV_MEMv_OrAX + int w v + INVALID r OrAX + +INTRINSIC_XED_IFORM_MOV_GPR8_IMMb_B0 + INVALID w GPR8_SB + +INTRINSIC_XED_IFORM_MOV_GPRv_IMMv + INVALID w GPRv_SB + +INTRINSIC_XED_IFORM_PSRLW_MMXq_IMMb + u16 rw q + +INTRINSIC_XED_IFORM_PSRLW_XMMdq_IMMb + u16 rw dq + +INTRINSIC_XED_IFORM_PSRLW_MMXq_MEMq + u16 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRLW_MMXq_MMXq + u16 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRLW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSRLW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSRAW_MMXq_IMMb + i16 rw q + +INTRINSIC_XED_IFORM_PSRAW_XMMdq_IMMb + i16 rw dq + +INTRINSIC_XED_IFORM_PSRAW_MMXq_MEMq + i16 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRAW_MMXq_MMXq + i16 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRAW_XMMdq_MEMdq + i16 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_PSRAW_XMMdq_XMMdq + i16 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_PSLLW_MMXq_IMMb + u16 rw q + +INTRINSIC_XED_IFORM_PSLLW_XMMdq_IMMb + u16 rw dq + +INTRINSIC_XED_IFORM_PSLLW_MMXq_MEMq + u16 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSLLW_MMXq_MMXq + u16 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSLLW_XMMdq_MEMdq + u16 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSLLW_XMMdq_XMMdq + u16 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSRLD_MMXq_IMMb + u32 rw q + +INTRINSIC_XED_IFORM_PSRLD_XMMdq_IMMb + u32 rw dq + +INTRINSIC_XED_IFORM_PSRLD_MMXq_MEMq + u32 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRLD_MMXq_MMXq + u32 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRLD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSRLD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSRAD_MMXq_IMMb + i32 rw q + +INTRINSIC_XED_IFORM_PSRAD_XMMdq_IMMb + i32 rw dq + +INTRINSIC_XED_IFORM_PSRAD_MMXq_MEMq + i32 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRAD_MMXq_MMXq + i32 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRAD_XMMdq_MEMdq + i32 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_PSRAD_XMMdq_XMMdq + i32 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_PSLLD_MMXq_IMMb + u32 rw q + +INTRINSIC_XED_IFORM_PSLLD_XMMdq_IMMb + u32 rw dq + +INTRINSIC_XED_IFORM_PSLLD_MMXq_MEMq + u32 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSLLD_MMXq_MMXq + u32 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSLLD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSLLD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSRLQ_MMXq_IMMb + u64 rw q + +INTRINSIC_XED_IFORM_PSRLQ_XMMdq_IMMb + u64 rw dq + +INTRINSIC_XED_IFORM_PSRLQ_MMXq_MEMq + u64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRLQ_MMXq_MMXq + u64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRLQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSRLQ_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSLLQ_MMXq_IMMb + u64 rw q + +INTRINSIC_XED_IFORM_PSLLQ_XMMdq_IMMb + u64 rw dq + +INTRINSIC_XED_IFORM_PSLLQ_MMXq_MEMq + u64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSLLQ_MMXq_MMXq + u64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSLLQ_XMMdq_MEMdq + u64 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_PSLLQ_XMMdq_XMMdq + u64 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_PSRLDQ_XMMdq_IMMb + u128 rw dq + +INTRINSIC_XED_IFORM_PSLLDQ_XMMdq_IMMb + u128 rw dq + +INTRINSIC_XED_IFORM_FXSAVE_MEMmfpxenv + struct w mfpxenv + INVALID r XED_REG_X87CONTROL + +INTRINSIC_XED_IFORM_FXRSTOR_MEMmfpxenv + struct r mfpxenv + INVALID w XED_REG_X87CONTROL + +INTRINSIC_XED_IFORM_FXSAVE64_MEMmfpxenv + struct w mfpxenv + INVALID r XED_REG_X87CONTROL + +INTRINSIC_XED_IFORM_FXRSTOR64_MEMmfpxenv + struct r mfpxenv + INVALID w XED_REG_X87CONTROL + +INTRINSIC_XED_IFORM_LDMXCSR_MEMd + i32 r d + INVALID w XED_REG_MXCSR + +INTRINSIC_XED_IFORM_STMXCSR_MEMd + i32 w d + INVALID r XED_REG_MXCSR + +INTRINSIC_XED_IFORM_PREFETCHNTA_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCHT0_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCHT1_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCHT2_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r0 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r1 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r2 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r3 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_MEMv_0F18r4 + int r v + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r4 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_MEMv_0F18r5 + int r v + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r5 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_MEMv_0F18r6 + int r v + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r6 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_MEMv_0F18r7 + int r v + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r7 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F19 + int r v + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F19 + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1D + int r v + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1D + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1F + int r v + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1F + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_90 + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F0D + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1A + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1B + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_MEMv_0F1A + INVALID r GPRv_B + int r v + +INTRINSIC_XED_IFORM_NOP_GPRv_MEM_0F1B + INVALID r GPRv_B + int r v + +INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1E + int r v + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1E + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1C + int r v + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1C + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_VMCALL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_VMLAUNCH + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_VMRESUME + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_VMXOFF + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SGDT_MEMs64 + struct w s64 + INVALID r XED_REG_GDTR + +INTRINSIC_XED_IFORM_SGDT_MEMs + struct w s + INVALID r XED_REG_GDTR + +INTRINSIC_XED_IFORM_LIDT_MEMs64 + struct r s64 + INVALID w XED_REG_IDTR + +INTRINSIC_XED_IFORM_LIDT_MEMs + struct r s + INVALID w XED_REG_IDTR + +INTRINSIC_XED_IFORM_MONITOR + INVALID r XED_REG_EAX + INVALID r XED_REG_ECX + INVALID r XED_REG_EDX + +INTRINSIC_XED_IFORM_MWAIT + INVALID r XED_REG_EAX + INVALID r XED_REG_ECX + +INTRINSIC_XED_IFORM_SIDT_MEMs + struct w s + INVALID r XED_REG_IDTR + +INTRINSIC_XED_IFORM_SIDT_MEMs64 + struct w s64 + INVALID r XED_REG_IDTR + +INTRINSIC_XED_IFORM_INVLPG_MEMb + u8 r b + +INTRINSIC_XED_IFORM_SWAPGS + +INTRINSIC_XED_IFORM_RDTSCP + INVALID w XED_REG_EAX + INVALID w XED_REG_EDX + INVALID w XED_REG_ECX + INVALID r XED_REG_TSC + INVALID r XED_REG_TSCAUX + +INTRINSIC_XED_IFORM_SFENCE + +INTRINSIC_XED_IFORM_CLFLUSH_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_LFENCE + +INTRINSIC_XED_IFORM_MFENCE + +INTRINSIC_XED_IFORM_MOVHLPS_XMMq_XMMq + f32 w q + f32 r q + +INTRINSIC_XED_IFORM_MOVLPS_XMMq_MEMq + f32 w q + f32 r q + +INTRINSIC_XED_IFORM_MOVLPS_MEMq_XMMps + f32 w q + f32 r ps + +INTRINSIC_XED_IFORM_MOVLHPS_XMMq_XMMq + f32 w q + f32 r q + +INTRINSIC_XED_IFORM_MOVHPS_XMMq_MEMq + f32 w q + f32 r q + +INTRINSIC_XED_IFORM_MOVHPS_MEMq_XMMps + f32 w q + f32 r ps + +INTRINSIC_XED_IFORM_DAA + INVALID rw XED_REG_AL + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_DAS + INVALID rw XED_REG_AL + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_AAA + INVALID rw XED_REG_AL + INVALID rw XED_REG_AH + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_AAS + INVALID rw XED_REG_AL + INVALID rw XED_REG_AH + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_PUSHA + int w spw8 + INVALID r XED_REG_AX + INVALID r XED_REG_CX + INVALID r XED_REG_DX + INVALID r XED_REG_BX + INVALID r XED_REG_SP + INVALID r XED_REG_BP + INVALID r XED_REG_SI + INVALID r XED_REG_DI + int w spw8 + +INTRINSIC_XED_IFORM_PUSHAD + int w spw8 + INVALID r XED_REG_EAX + INVALID r XED_REG_ECX + INVALID r XED_REG_EDX + INVALID r XED_REG_EBX + INVALID r XED_REG_ESP + INVALID r XED_REG_EBP + INVALID r XED_REG_ESI + INVALID r XED_REG_EDI + int w spw8 + +INTRINSIC_XED_IFORM_POPA + int r spw8 + INVALID w XED_REG_AX + INVALID w XED_REG_CX + INVALID w XED_REG_DX + INVALID w XED_REG_BX + INVALID w XED_REG_BP + INVALID w XED_REG_SI + INVALID w XED_REG_DI + int r spw8 + +INTRINSIC_XED_IFORM_POPAD + int r spw8 + INVALID w XED_REG_EAX + INVALID w XED_REG_ECX + INVALID w XED_REG_EDX + INVALID w XED_REG_EBX + INVALID w XED_REG_EBP + INVALID w XED_REG_ESI + INVALID w XED_REG_EDI + int r spw8 + +INTRINSIC_XED_IFORM_BOUND_GPRv_MEMa16 + INVALID r GPRv_R + i16 r a16 + +INTRINSIC_XED_IFORM_BOUND_GPRv_MEMa32 + INVALID r GPRv_R + i32 r a32 + +INTRINSIC_XED_IFORM_ARPL_MEMw_GPR16 + i16 rw w + INVALID r GPR16_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ARPL_GPR16_GPR16 + INVALID rw GPR16_B + INVALID r GPR16_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MOVSXD_GPRv_MEMz + INVALID w GPRv_R + int r z + +INTRINSIC_XED_IFORM_MOVSXD_GPRv_GPRz + INVALID w GPRv_R + INVALID r GPRz_B + +INTRINSIC_XED_IFORM_REP_INSB + u8 cw b + INVALID r XED_REG_DX + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_INSB + u8 w b + INVALID r XED_REG_DX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_INSW + i16 cw w + INVALID r XED_REG_DX + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_INSW + i16 w w + INVALID r XED_REG_DX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_INSD + i32 cw d + INVALID r XED_REG_DX + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_INSD + i32 w d + INVALID r XED_REG_DX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_OUTSB + INVALID r XED_REG_DX + u8 cr b + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_OUTSB + INVALID r XED_REG_DX + u8 r b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_OUTSW + INVALID r XED_REG_DX + i16 cr w + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_OUTSW + INVALID r XED_REG_DX + i16 r w + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_OUTSD + INVALID r XED_REG_DX + i32 cr d + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_OUTSD + INVALID r XED_REG_DX + i32 r d + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JO_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JO_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JO_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNO_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNO_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNO_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JB_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JB_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JB_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNB_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNB_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNB_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JZ_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JZ_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JZ_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNZ_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNZ_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNZ_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JBE_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JBE_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JBE_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNBE_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNBE_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNBE_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JS_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JS_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JS_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNS_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNS_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNS_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JP_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JP_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JP_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNP_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNP_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNP_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JL_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JL_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JL_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNL_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNL_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNL_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JLE_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JLE_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JLE_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNLE_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNLE_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNLE_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_XCHG_MEMb_GPR8 + u8 rw b + INVALID rw GPR8_R + +INTRINSIC_XED_IFORM_XCHG_GPR8_GPR8 + INVALID rw GPR8_B + INVALID rw GPR8_R + +INTRINSIC_XED_IFORM_XCHG_MEMv_GPRv + int rw v + INVALID rw GPRv_R + +INTRINSIC_XED_IFORM_XCHG_GPRv_GPRv + INVALID rw GPRv_B + INVALID rw GPRv_R + +INTRINSIC_XED_IFORM_XCHG_GPRv_OrAX + INVALID rw GPRv_SB + INVALID rw OrAX + +INTRINSIC_XED_IFORM_LEA_GPRv_AGEN + INVALID w GPRv_R + +INTRINSIC_XED_IFORM_PAUSE + +INTRINSIC_XED_IFORM_CBW + INVALID w XED_REG_AX + INVALID r XED_REG_AL + +INTRINSIC_XED_IFORM_CDQE + INVALID w XED_REG_RAX + INVALID r XED_REG_EAX + +INTRINSIC_XED_IFORM_CWDE + INVALID w XED_REG_EAX + INVALID r XED_REG_AX + +INTRINSIC_XED_IFORM_CWD + INVALID w XED_REG_DX + INVALID r XED_REG_AX + +INTRINSIC_XED_IFORM_CQO + INVALID w XED_REG_RDX + INVALID r XED_REG_RAX + +INTRINSIC_XED_IFORM_CDQ + INVALID w XED_REG_EDX + INVALID r XED_REG_EAX + +INTRINSIC_XED_IFORM_CALL_FAR_MEMp2 + struct r p2 + int w spw2 + INVALID w rIP + int w spw2 + +INTRINSIC_XED_IFORM_CALL_FAR_PTRp_IMMw + int w spw2 + INVALID w XED_REG_EIP + int w spw2 + +INTRINSIC_XED_IFORM_FWAIT + +INTRINSIC_XED_IFORM_PUSHF + i16 w w + i16 w w + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_PUSHFD + i32 w d + i32 w d + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_PUSHFQ + i64 w q + i64 w q + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_POPF + i16 r w + i16 r w + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_POPFD + i32 r d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_POPFQ + i64 r q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SAHF + INVALID r XED_REG_AH + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LAHF + INVALID w XED_REG_AH + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_MOVSB + u8 cw b + u8 cr b + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_MOVSB + u8 w b + u8 r b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_MOVSW + i16 cw w + i16 cr w + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_MOVSW + i16 w w + i16 r w + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_MOVSD + i32 cw d + i32 cr d + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_MOVSD + i32 w d + i32 r d + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_MOVSQ + i64 cw q + i64 cr q + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_MOVSQ + i64 w q + i64 r q + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REPE_CMPSB + u8 cr b + u8 cr b + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_CMPSB + u8 cr b + u8 cr b + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_CMPSB + u8 r b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_REPE_CMPSW + i16 cr w + i16 cr w + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_CMPSW + i16 cr w + i16 cr w + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_CMPSW + i16 r w + i16 r w + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_REPE_CMPSD + i32 cr d + i32 cr d + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_CMPSD + i32 cr d + i32 cr d + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_CMPSD + i32 r d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_REPE_CMPSQ + i64 cr q + i64 cr q + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_CMPSQ + i64 cr q + i64 cr q + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_CMPSQ + i64 r q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_REP_STOSB + u8 cw b + INVALID r XED_REG_AL + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_STOSB + u8 w b + INVALID r XED_REG_AL + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_STOSW + i16 cw w + INVALID r XED_REG_AX + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_STOSW + i16 w w + INVALID r XED_REG_AX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_STOSD + i32 cw d + INVALID r XED_REG_EAX + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_STOSD + i32 w d + INVALID r XED_REG_EAX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_STOSQ + i64 cw q + INVALID r XED_REG_RAX + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_STOSQ + i64 w q + INVALID r XED_REG_RAX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_LODSB + INVALID cw XED_REG_AL + u8 cr b + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_LODSB + INVALID w XED_REG_AL + u8 r b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_LODSW + INVALID cw XED_REG_AX + i16 cr w + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_LODSW + INVALID w XED_REG_AX + i16 r w + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_LODSD + INVALID cw XED_REG_EAX + i32 cr d + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_LODSD + INVALID w XED_REG_EAX + i32 r d + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_LODSQ + INVALID cw XED_REG_RAX + i64 cr q + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_LODSQ + INVALID w XED_REG_RAX + i64 r q + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REPE_SCASB + INVALID r XED_REG_AL + u8 cr b + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_SCASB + INVALID r XED_REG_AL + u8 cr b + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_SCASB + INVALID r XED_REG_AL + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_REPE_SCASW + INVALID r XED_REG_AX + i16 cr w + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_SCASW + INVALID r XED_REG_AX + i16 cr w + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_SCASW + INVALID r XED_REG_AX + i16 r w + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_REPE_SCASD + INVALID r XED_REG_EAX + i32 cr d + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_SCASD + INVALID r XED_REG_EAX + i32 cr d + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_SCASD + INVALID r XED_REG_EAX + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_REPE_SCASQ + INVALID r XED_REG_RAX + i64 cr q + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_SCASQ + INVALID r XED_REG_RAX + i64 cr q + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_SCASQ + INVALID r XED_REG_RAX + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RET_NEAR_IMMw + int r spw + INVALID w rIP + int r spw + +INTRINSIC_XED_IFORM_RET_NEAR + int r spw + INVALID w rIP + int r spw + +INTRINSIC_XED_IFORM_LES_GPRz_MEMp + INVALID w GPRz_R + struct r p + INVALID w XED_REG_ES + +INTRINSIC_XED_IFORM_LDS_GPRz_MEMp + INVALID w GPRz_R + struct r p + INVALID w XED_REG_DS + +INTRINSIC_XED_IFORM_ENTER_IMMw_IMMb + int w spw + INVALID rw OrBP + int w spw + +INTRINSIC_XED_IFORM_LEAVE + int r v + INVALID rw OrBP + INVALID rw OrSP + +INTRINSIC_XED_IFORM_RET_FAR_IMMw + int r spw2 + INVALID w rIP + int r spw2 + +INTRINSIC_XED_IFORM_RET_FAR + int r spw2 + INVALID w rIP + int r spw2 + +INTRINSIC_XED_IFORM_INT3 + INVALID w rIP + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_INT_IMMb + INVALID w rIP + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_INTO + INVALID w XED_REG_EIP + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_IRET + int r spw5 + INVALID w rIP + int r spw5 + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_IRETD + int r spw5 + INVALID w rIP + int r spw5 + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_IRETQ + int r spw5 + INVALID w XED_REG_RIP + int r spw5 + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_AAM_IMMb + INVALID rw XED_REG_AL + INVALID w XED_REG_AH + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AAD_IMMb + INVALID rw XED_REG_AL + INVALID rw XED_REG_AH + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SALC + INVALID w XED_REG_AL + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_XLAT + u8 r b + INVALID w XED_REG_AL + +INTRINSIC_XED_IFORM_LOOPNE_RELBRb + INVALID rw ArCX + INVALID rw rIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_LOOPE_RELBRb + INVALID rw ArCX + INVALID rw rIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_LOOP_RELBRb + INVALID rw ArCX + INVALID rw rIP + +INTRINSIC_XED_IFORM_JCXZ_RELBRb + INVALID r XED_REG_CX + INVALID rw XED_REG_IP + +INTRINSIC_XED_IFORM_JECXZ_RELBRb + INVALID r XED_REG_ECX + INVALID rw XED_REG_EIP + +INTRINSIC_XED_IFORM_JRCXZ_RELBRb + INVALID r XED_REG_RCX + INVALID rw XED_REG_RIP + +INTRINSIC_XED_IFORM_IN_AL_IMMb + INVALID w XED_REG_AL + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_IN_OeAX_IMMb + INVALID w OeAX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_IN_AL_DX + INVALID w XED_REG_AL + INVALID r XED_REG_DX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_IN_OeAX_DX + INVALID w OeAX + INVALID r XED_REG_DX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_OUT_IMMb_AL + INVALID r XED_REG_AL + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_OUT_IMMb_OeAX + INVALID r OeAX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_OUT_DX_AL + INVALID r XED_REG_DX + INVALID r XED_REG_AL + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_OUT_DX_OeAX + INVALID r XED_REG_DX + INVALID r OeAX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_INT1 + INVALID w rIP + +INTRINSIC_XED_IFORM_HLT + +INTRINSIC_XED_IFORM_CMC + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_CLC + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_STC + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CLI + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_STI + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_CLD + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_STD + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LAR_GPRv_MEMw + INVALID cw GPRv_R + i16 r w + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LAR_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LSL_GPRv_MEMw + INVALID rw GPRv_R + i16 r w + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LSL_GPRv_GPRz + INVALID rw GPRv_R + INVALID r GPRz_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SYSCALL + INVALID w XED_REG_RIP + INVALID w XED_REG_RCX + INVALID w XED_REG_R11 + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CLTS + +INTRINSIC_XED_IFORM_SYSRET + INVALID w XED_REG_EIP + INVALID r XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SYSRET64 + INVALID w XED_REG_RIP + INVALID r XED_REG_RCX + INVALID r XED_REG_R11 + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MOVUPS_XMMps_MEMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVUPS_XMMps_XMMps_0F10 + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVUPS_MEMps_XMMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVUPS_XMMps_XMMps_0F11 + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_UNPCKLPS_XMMps_MEMdq + f32 rw ps + i32 r dq + +INTRINSIC_XED_IFORM_UNPCKLPS_XMMps_XMMq + f32 rw ps + i64 r q + +INTRINSIC_XED_IFORM_UNPCKHPS_XMMps_MEMdq + f32 rw ps + i32 r dq + +INTRINSIC_XED_IFORM_UNPCKHPS_XMMps_XMMdq + f32 rw ps + i32 r dq + +INTRINSIC_XED_IFORM_MOVSS_XMMdq_MEMss + f32 w dq + f32 r ss + +INTRINSIC_XED_IFORM_MOVSS_XMMss_XMMss_0F10 + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_MOVSS_MEMss_XMMss + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_MOVSS_XMMss_XMMss_0F11 + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_MOVSLDUP_XMMps_MEMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVSLDUP_XMMps_XMMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVSHDUP_XMMps_MEMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVSHDUP_XMMps_XMMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVUPD_XMMpd_MEMpd + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10 + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVUPD_MEMpd_XMMpd + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11 + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVLPD_XMMsd_MEMq + f64 w sd + i64 r q + +INTRINSIC_XED_IFORM_MOVLPD_MEMq_XMMsd + i64 w q + f64 r sd + +INTRINSIC_XED_IFORM_UNPCKLPD_XMMpd_MEMdq + f64 rw pd + i32 r dq + +INTRINSIC_XED_IFORM_UNPCKLPD_XMMpd_XMMq + f64 rw pd + i64 r q + +INTRINSIC_XED_IFORM_UNPCKHPD_XMMpd_MEMdq + f64 rw pd + i32 r dq + +INTRINSIC_XED_IFORM_UNPCKHPD_XMMpd_XMMq + f64 rw pd + i64 r q + +INTRINSIC_XED_IFORM_MOVHPD_XMMsd_MEMq + f64 w sd + i64 r q + +INTRINSIC_XED_IFORM_MOVHPD_MEMq_XMMsd + i64 w q + f64 r sd + +INTRINSIC_XED_IFORM_MOVSD_XMM_XMMdq_MEMsd + f64 w dq + f64 r sd + +INTRINSIC_XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10 + f64 w sd + f64 r sd + +INTRINSIC_XED_IFORM_MOVSD_XMM_MEMsd_XMMsd + f64 w sd + f64 r sd + +INTRINSIC_XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11 + f64 w sd + f64 r sd + +INTRINSIC_XED_IFORM_MOVDDUP_XMMdq_MEMq + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_MOVDDUP_XMMdq_XMMq + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_MOV_CR_CR_GPR32 + INVALID w CR_R + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_MOV_CR_CR_GPR64 + INVALID w CR_R + INVALID r GPR64_B + +INTRINSIC_XED_IFORM_MOV_CR_GPR32_CR + INVALID w GPR32_B + INVALID r CR_R + +INTRINSIC_XED_IFORM_MOV_CR_GPR64_CR + INVALID w GPR64_B + INVALID r CR_R + +INTRINSIC_XED_IFORM_MOV_DR_DR_GPR32 + INVALID w DR_R + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_MOV_DR_DR_GPR64 + INVALID w DR_R + INVALID r GPR64_B + +INTRINSIC_XED_IFORM_MOV_DR_GPR32_DR + INVALID w GPR32_B + INVALID r DR_R + +INTRINSIC_XED_IFORM_MOV_DR_GPR64_DR + INVALID w GPR64_B + INVALID r DR_R + +INTRINSIC_XED_IFORM_WRMSR + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + INVALID r XED_REG_ECX + INVALID w XED_REG_MSRS + +INTRINSIC_XED_IFORM_RDTSC + INVALID w XED_REG_EAX + INVALID w XED_REG_EDX + INVALID r XED_REG_TSC + +INTRINSIC_XED_IFORM_RDMSR + INVALID w XED_REG_EAX + INVALID w XED_REG_EDX + INVALID r XED_REG_ECX + INVALID r XED_REG_MSRS + +INTRINSIC_XED_IFORM_RDPMC + INVALID w XED_REG_EAX + INVALID w XED_REG_EDX + INVALID r XED_REG_ECX + INVALID r XED_REG_MSRS + +INTRINSIC_XED_IFORM_SYSENTER + INVALID w XED_REG_EIP + INVALID w XED_REG_ESP + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SYSEXIT + INVALID w XED_REG_EIP + INVALID w XED_REG_ESP + INVALID r XED_REG_ECX + INVALID r XED_REG_EDX + +INTRINSIC_XED_IFORM_CMOVO_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVO_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNO_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNO_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVB_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVB_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNB_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNB_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVZ_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVZ_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNZ_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNZ_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVBE_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVBE_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNBE_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNBE_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_MOVMSKPS_GPR32_XMMps + INVALID w GPR32_R + f32 r ps + +INTRINSIC_XED_IFORM_SQRTPS_XMMps_MEMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_SQRTPS_XMMps_XMMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_RSQRTPS_XMMps_MEMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_RSQRTPS_XMMps_XMMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_RCPPS_XMMps_MEMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_RCPPS_XMMps_XMMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_ANDPS_XMMxud_MEMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_ANDPS_XMMxud_XMMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_ANDNPS_XMMxud_MEMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_ANDNPS_XMMxud_XMMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_ORPS_XMMxud_MEMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_ORPS_XMMxud_XMMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_XORPS_XMMxud_MEMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_XORPS_XMMxud_XMMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_SQRTSS_XMMss_MEMss + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_SQRTSS_XMMss_XMMss + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_RSQRTSS_XMMss_MEMss + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_RSQRTSS_XMMss_XMMss + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_RCPSS_XMMss_MEMss + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_RCPSS_XMMss_XMMss + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_MOVMSKPD_GPR32_XMMpd + INVALID w GPR32_R + f64 r pd + +INTRINSIC_XED_IFORM_SQRTPD_XMMpd_MEMpd + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_SQRTPD_XMMpd_XMMpd + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_ANDPD_XMMxuq_MEMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_ANDPD_XMMxuq_XMMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_ANDNPD_XMMxuq_MEMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_ANDNPD_XMMxuq_XMMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_ORPD_XMMxuq_MEMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_ORPD_XMMxuq_XMMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_XORPD_XMMxuq_MEMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_XORPD_XMMxuq_XMMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_SQRTSD_XMMsd_MEMsd + f64 w sd + f64 r sd + +INTRINSIC_XED_IFORM_SQRTSD_XMMsd_XMMsd + f64 w sd + f64 r sd + +INTRINSIC_XED_IFORM_PUNPCKLBW_MMXq_MEMd + u8 rw q + u8 r d + +INTRINSIC_XED_IFORM_PUNPCKLBW_MMXq_MMXd + u8 rw q + u8 r d + +INTRINSIC_XED_IFORM_PUNPCKLBW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKLBW_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKLWD_MMXq_MEMd + u16 rw q + u16 r d + +INTRINSIC_XED_IFORM_PUNPCKLWD_MMXq_MMXd + u16 rw q + u16 r d + +INTRINSIC_XED_IFORM_PUNPCKLWD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKLWD_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKLDQ_MMXq_MEMd + u32 rw q + u32 r d + +INTRINSIC_XED_IFORM_PUNPCKLDQ_MMXq_MMXd + u32 rw q + u32 r d + +INTRINSIC_XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKLDQ_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PACKSSWB_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PACKSSWB_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PACKSSWB_XMMdq_MEMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PACKSSWB_XMMdq_XMMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PCMPGTB_MMXq_MEMq + i8 rw q + i8 r q + +INTRINSIC_XED_IFORM_PCMPGTB_MMXq_MMXq + i8 rw q + i8 r q + +INTRINSIC_XED_IFORM_PCMPGTB_XMMdq_MEMdq + i8 rw dq + i8 r dq + +INTRINSIC_XED_IFORM_PCMPGTB_XMMdq_XMMdq + i8 rw dq + i8 r dq + +INTRINSIC_XED_IFORM_PCMPGTW_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PCMPGTW_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PCMPGTW_XMMdq_MEMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PCMPGTW_XMMdq_XMMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PCMPGTD_MMXq_MEMq + i32 rw q + i32 r q + +INTRINSIC_XED_IFORM_PCMPGTD_MMXq_MMXq + i32 rw q + i32 r q + +INTRINSIC_XED_IFORM_PCMPGTD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PCMPGTD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PACKUSWB_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PACKUSWB_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PACKUSWB_XMMdq_MEMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PACKUSWB_XMMdq_XMMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PSHUFW_MMXq_MEMq_IMMb + u16 w q + u16 r q + +INTRINSIC_XED_IFORM_PSHUFW_MMXq_MMXq_IMMb + u16 w q + u16 r q + +INTRINSIC_XED_IFORM_PCMPEQB_MMXq_MEMq + i8 rw q + i8 r q + +INTRINSIC_XED_IFORM_PCMPEQB_MMXq_MMXq + i8 rw q + i8 r q + +INTRINSIC_XED_IFORM_PCMPEQB_XMMdq_MEMdq + i8 rw dq + i8 r dq + +INTRINSIC_XED_IFORM_PCMPEQB_XMMdq_XMMdq + i8 rw dq + i8 r dq + +INTRINSIC_XED_IFORM_PCMPEQW_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PCMPEQW_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PCMPEQW_XMMdq_MEMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PCMPEQW_XMMdq_XMMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PCMPEQD_MMXq_MEMq + i32 rw q + i32 r q + +INTRINSIC_XED_IFORM_PCMPEQD_MMXq_MMXq + i32 rw q + i32 r q + +INTRINSIC_XED_IFORM_PCMPEQD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PCMPEQD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_EMMS + +INTRINSIC_XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_SETO_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETO_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNO_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNO_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETB_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETB_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNB_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNB_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETZ_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETZ_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNZ_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNZ_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETBE_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETBE_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNBE_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNBE_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CPUID + INVALID rw XED_REG_EAX + INVALID w XED_REG_EBX + INVALID crw XED_REG_ECX + INVALID w XED_REG_EDX + +INTRINSIC_XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8 + u8 rcw b + INVALID r GPR8_R + INVALID rcw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv + int rcw v + INVALID r GPRv_R + INVALID rcw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG_MEMb_GPR8 + u8 rcw b + INVALID r GPR8_R + INVALID rcw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG_GPR8_GPR8 + INVALID rcw GPR8_B + INVALID r GPR8_R + INVALID rcw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG_MEMv_GPRv + int rcw v + INVALID r GPRv_R + INVALID rcw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG_GPRv_GPRv + INVALID rcw GPRv_B + INVALID r GPRv_R + INVALID rcw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LSS_GPRv_MEMp2 + INVALID w GPRv_R + struct r p2 + INVALID w XED_REG_SS + +INTRINSIC_XED_IFORM_LFS_GPRv_MEMp2 + INVALID w GPRv_R + struct r p2 + INVALID w XED_REG_FS + +INTRINSIC_XED_IFORM_LGS_GPRv_MEMp2 + INVALID w GPRv_R + struct r p2 + INVALID w XED_REG_GS + +INTRINSIC_XED_IFORM_MOVZX_GPRv_MEMb + INVALID w GPRv_R + u8 r b + +INTRINSIC_XED_IFORM_MOVZX_GPRv_GPR8 + INVALID w GPRv_R + INVALID r GPR8_B + +INTRINSIC_XED_IFORM_MOVZX_GPRv_MEMw + INVALID w GPRv_R + i16 r w + +INTRINSIC_XED_IFORM_MOVZX_GPRv_GPR16 + INVALID w GPRv_R + INVALID r GPR16_B + +INTRINSIC_XED_IFORM_XADD_LOCK_MEMb_GPR8 + u8 rw b + INVALID rw GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XADD_LOCK_MEMv_GPRv + int rw v + INVALID rw GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XADD_MEMb_GPR8 + u8 rw b + INVALID rw GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XADD_GPR8_GPR8 + INVALID rw GPR8_B + INVALID rw GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XADD_MEMv_GPRv + int rw v + INVALID rw GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XADD_GPRv_GPRv + INVALID rw GPRv_B + INVALID rw GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPPS_XMMps_MEMps_IMMb + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_CMPPS_XMMps_XMMps_IMMb + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVNTI_MEMd_GPR32 + i32 w d + INVALID r GPR32_R + +INTRINSIC_XED_IFORM_MOVNTI_MEMq_GPR64 + i64 w q + INVALID r GPR64_R + +INTRINSIC_XED_IFORM_PINSRW_MMXq_MEMw_IMMb + u16 rw q + u16 r w + +INTRINSIC_XED_IFORM_PINSRW_MMXq_GPR32_IMMb + u16 rw q + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_PINSRW_XMMdq_MEMw_IMMb + i32 rw dq + i16 r w + +INTRINSIC_XED_IFORM_PINSRW_XMMdq_GPR32_IMMb + i32 rw dq + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_PEXTRW_GPR32_MMXq_IMMb + INVALID w GPR32_R + u16 r q + +INTRINSIC_XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb + INVALID w GPR32_R + i32 r dq + +INTRINSIC_XED_IFORM_SHUFPS_XMMps_MEMps_IMMb + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_SHUFPS_XMMps_XMMps_IMMb + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_CMPSS_XMMss_MEMss_IMMb + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_CMPSS_XMMss_XMMss_IMMb + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_PADDQ_MMXq_MEMq + u64 rw q + u64 r q + +INTRINSIC_XED_IFORM_PADDQ_MMXq_MMXq + u64 rw q + u64 r q + +INTRINSIC_XED_IFORM_PADDQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDQ_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULLW_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PMULLW_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PMULLW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULLW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMOVMSKB_GPR32_MMXq + INVALID w GPR32_R + i8 r q + +INTRINSIC_XED_IFORM_PMOVMSKB_GPR32_XMMdq + INVALID w GPR32_R + i8 r dq + +INTRINSIC_XED_IFORM_ADDSUBPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_ADDSUBPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVQ2DQ_XMMdq_MMXq + u64 w dq + u64 r q + +INTRINSIC_XED_IFORM_ADDSUBPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_ADDSUBPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVDQ2Q_MMXq_XMMq + u64 w q + u64 r q + +INTRINSIC_XED_IFORM_PAVGB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PAVGB_MMXq_MMXq + i8 rw q + i8 r q + +INTRINSIC_XED_IFORM_PAVGB_XMMdq_MEMdq + u8 rw dq + u8 r dq + +INTRINSIC_XED_IFORM_PAVGB_XMMdq_XMMdq + u8 rw dq + u8 r dq + +INTRINSIC_XED_IFORM_PAVGW_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PAVGW_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PAVGW_XMMdq_MEMdq + u16 rw dq + u16 r dq + +INTRINSIC_XED_IFORM_PAVGW_XMMdq_XMMdq + u16 rw dq + u16 r dq + +INTRINSIC_XED_IFORM_PMULHUW_MMXq_MEMq + u16 rw q + u16 r q + +INTRINSIC_XED_IFORM_PMULHUW_MMXq_MMXq + u16 rw q + u16 r q + +INTRINSIC_XED_IFORM_PMULHUW_XMMdq_MEMdq + u16 rw dq + u16 r dq + +INTRINSIC_XED_IFORM_PMULHUW_XMMdq_XMMdq + u16 rw dq + u16 r dq + +INTRINSIC_XED_IFORM_PMULHW_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PMULHW_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PMULHW_XMMdq_MEMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PMULHW_XMMdq_XMMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_MOVNTQ_MEMq_MMXq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd + i32 w dq + f64 r pd + +INTRINSIC_XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd + i32 w dq + f64 r pd + +INTRINSIC_XED_IFORM_MOVNTDQ_MEMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_CVTDQ2PD_XMMpd_MEMq + f64 w pd + i32 r q + +INTRINSIC_XED_IFORM_CVTDQ2PD_XMMpd_XMMq + f64 w pd + i32 r q + +INTRINSIC_XED_IFORM_CVTPD2DQ_XMMdq_MEMpd + i32 w dq + f64 r pd + +INTRINSIC_XED_IFORM_CVTPD2DQ_XMMdq_XMMpd + i32 w dq + f64 r pd + +INTRINSIC_XED_IFORM_PMULUDQ_MMXq_MEMq + u32 rw q + u32 r q + +INTRINSIC_XED_IFORM_PMULUDQ_MMXq_MMXq + u32 rw q + u32 r q + +INTRINSIC_XED_IFORM_PMULUDQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULUDQ_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMADDWD_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PMADDWD_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PMADDWD_XMMdq_MEMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PMADDWD_XMMdq_XMMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PSADBW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSADBW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSADBW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSADBW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_MASKMOVQ_MMXq_MMXq + u8 r q + i8 r q + i64 w q + +INTRINSIC_XED_IFORM_MASKMOVDQU_XMMdq_XMMdq + i32 r dq + i32 r dq + i32 w dq + +INTRINSIC_XED_IFORM_LDDQU_XMMpd_MEMdq + f64 w pd + i32 r dq + +INTRINSIC_XED_IFORM_INVD + +INTRINSIC_XED_IFORM_UD0_GPR32_MEMd + INVALID r GPR32_R + i32 r d + +INTRINSIC_XED_IFORM_UD0_GPR32_GPR32 + INVALID r GPR32_R + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_UD1_GPR32_MEMd + INVALID r GPR32_R + i32 r d + +INTRINSIC_XED_IFORM_UD1_GPR32_GPR32 + INVALID r GPR32_R + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_UD2 + +INTRINSIC_XED_IFORM_MOVAPS_XMMps_MEMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVAPS_XMMps_XMMps_0F28 + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVAPS_MEMps_XMMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVAPS_XMMps_XMMps_0F29 + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_CVTPI2PS_XMMq_MEMq + f32 w q + i32 r q + +INTRINSIC_XED_IFORM_CVTPI2PS_XMMq_MMXq + f32 w q + i32 r q + +INTRINSIC_XED_IFORM_MOVNTPS_MEMdq_XMMps + i32 w dq + f32 r ps + +INTRINSIC_XED_IFORM_CVTTPS2PI_MMXq_MEMq + i32 w q + f32 r q + +INTRINSIC_XED_IFORM_CVTTPS2PI_MMXq_XMMq + i32 w q + f32 r q + +INTRINSIC_XED_IFORM_CVTPS2PI_MMXq_MEMq + i32 w q + f32 r q + +INTRINSIC_XED_IFORM_CVTPS2PI_MMXq_XMMq + i32 w q + f32 r q + +INTRINSIC_XED_IFORM_UCOMISS_XMMss_MEMss + f32 r ss + f32 r ss + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_UCOMISS_XMMss_XMMss + f32 r ss + f32 r ss + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_COMISS_XMMss_MEMss + f32 r ss + f32 r ss + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_COMISS_XMMss_XMMss + f32 r ss + f32 r ss + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_MEMd + f32 w ss + i32 r d + +INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_GPR32d + f32 w ss + i32 r d + +INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_MEMq + f32 w ss + i32 r q + +INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_GPR64q + f32 w ss + i32 r q + +INTRINSIC_XED_IFORM_CVTTSS2SI_GPR32d_MEMss + i32 w d + f32 r ss + +INTRINSIC_XED_IFORM_CVTTSS2SI_GPR32d_XMMss + i32 w d + f32 r ss + +INTRINSIC_XED_IFORM_CVTTSS2SI_GPR64q_MEMss + i64 w q + f32 r ss + +INTRINSIC_XED_IFORM_CVTTSS2SI_GPR64q_XMMss + i64 w q + f32 r ss + +INTRINSIC_XED_IFORM_CVTSS2SI_GPR32d_MEMss + i32 w d + f32 r ss + +INTRINSIC_XED_IFORM_CVTSS2SI_GPR32d_XMMss + i32 w d + f32 r ss + +INTRINSIC_XED_IFORM_CVTSS2SI_GPR64q_MEMss + i64 w q + f32 r ss + +INTRINSIC_XED_IFORM_CVTSS2SI_GPR64q_XMMss + i64 w q + f32 r ss + +INTRINSIC_XED_IFORM_MOVAPD_XMMpd_MEMpd + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28 + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVAPD_MEMpd_XMMpd + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29 + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_CVTPI2PD_XMMpd_MEMq + f64 w pd + i32 r q + +INTRINSIC_XED_IFORM_CVTPI2PD_XMMpd_MMXq + f64 w pd + i32 r q + +INTRINSIC_XED_IFORM_MOVNTPD_MEMdq_XMMpd + i32 w dq + f64 r pd + +INTRINSIC_XED_IFORM_CVTTPD2PI_MMXq_MEMpd + i32 w q + f64 r pd + +INTRINSIC_XED_IFORM_CVTTPD2PI_MMXq_XMMpd + i32 w q + f64 r pd + +INTRINSIC_XED_IFORM_CVTPD2PI_MMXq_MEMpd + i32 w q + f64 r pd + +INTRINSIC_XED_IFORM_CVTPD2PI_MMXq_XMMpd + i32 w q + f64 r pd + +INTRINSIC_XED_IFORM_UCOMISD_XMMsd_MEMsd + f64 r sd + f64 r sd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_UCOMISD_XMMsd_XMMsd + f64 r sd + f64 r sd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_COMISD_XMMsd_MEMsd + f64 r sd + f64 r sd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_COMISD_XMMsd_XMMsd + f64 r sd + f64 r sd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_MEMd + f64 w sd + i32 r d + +INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_GPR32d + f64 w sd + i32 r d + +INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_MEMq + f64 w sd + i64 r q + +INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_GPR64q + f64 w sd + i64 r q + +INTRINSIC_XED_IFORM_CVTTSD2SI_GPR32d_MEMsd + i32 w d + f64 r sd + +INTRINSIC_XED_IFORM_CVTTSD2SI_GPR32d_XMMsd + i32 w d + f64 r sd + +INTRINSIC_XED_IFORM_CVTTSD2SI_GPR64q_MEMsd + i64 w q + f64 r sd + +INTRINSIC_XED_IFORM_CVTTSD2SI_GPR64q_XMMsd + i64 w q + f64 r sd + +INTRINSIC_XED_IFORM_CVTSD2SI_GPR32d_MEMsd + i32 w d + f64 r sd + +INTRINSIC_XED_IFORM_CVTSD2SI_GPR32d_XMMsd + i32 w d + f64 r sd + +INTRINSIC_XED_IFORM_CVTSD2SI_GPR64q_MEMsd + i64 w q + f64 r sd + +INTRINSIC_XED_IFORM_CVTSD2SI_GPR64q_XMMsd + i64 w q + f64 r sd + +INTRINSIC_XED_IFORM_CMOVS_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVS_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNS_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNS_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVP_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVP_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNP_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNP_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVL_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVL_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNL_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNL_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVLE_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVLE_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNLE_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNLE_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_ADDPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_ADDPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MULPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MULPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_CVTPS2PD_XMMpd_MEMq + f64 w pd + f32 r q + +INTRINSIC_XED_IFORM_CVTPS2PD_XMMpd_XMMq + f64 w pd + f32 r q + +INTRINSIC_XED_IFORM_CVTDQ2PS_XMMps_MEMdq + f32 w ps + i32 r dq + +INTRINSIC_XED_IFORM_CVTDQ2PS_XMMps_XMMdq + f32 w ps + i32 r dq + +INTRINSIC_XED_IFORM_SUBPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_SUBPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MINPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MINPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_DIVPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_DIVPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MAXPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MAXPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_ADDSS_XMMss_MEMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_ADDSS_XMMss_XMMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_MULSS_XMMss_MEMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_MULSS_XMMss_XMMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_CVTSS2SD_XMMsd_MEMss + f64 w sd + f32 r ss + +INTRINSIC_XED_IFORM_CVTSS2SD_XMMsd_XMMss + f64 w sd + f32 r ss + +INTRINSIC_XED_IFORM_CVTTPS2DQ_XMMdq_MEMps + i32 w dq + f32 r ps + +INTRINSIC_XED_IFORM_CVTTPS2DQ_XMMdq_XMMps + i32 w dq + f32 r ps + +INTRINSIC_XED_IFORM_SUBSS_XMMss_MEMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_SUBSS_XMMss_XMMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_MINSS_XMMss_MEMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_MINSS_XMMss_XMMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_DIVSS_XMMss_MEMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_DIVSS_XMMss_XMMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_MAXSS_XMMss_MEMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_MAXSS_XMMss_XMMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_ADDPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_ADDPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MULPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MULPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_CVTPD2PS_XMMps_MEMpd + f32 w ps + f64 r pd + +INTRINSIC_XED_IFORM_CVTPD2PS_XMMps_XMMpd + f32 w ps + f64 r pd + +INTRINSIC_XED_IFORM_CVTPS2DQ_XMMdq_MEMps + i32 w dq + f32 r ps + +INTRINSIC_XED_IFORM_CVTPS2DQ_XMMdq_XMMps + i32 w dq + f32 r ps + +INTRINSIC_XED_IFORM_SUBPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_SUBPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MINPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MINPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_DIVPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_DIVPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MAXPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MAXPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_ADDSD_XMMsd_MEMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_ADDSD_XMMsd_XMMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_MULSD_XMMsd_MEMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_MULSD_XMMsd_XMMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_CVTSD2SS_XMMss_MEMsd + f32 w ss + f64 r sd + +INTRINSIC_XED_IFORM_CVTSD2SS_XMMss_XMMsd + f32 w ss + f64 r sd + +INTRINSIC_XED_IFORM_SUBSD_XMMsd_MEMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_SUBSD_XMMsd_XMMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_MINSD_XMMsd_MEMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_MINSD_XMMsd_XMMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_DIVSD_XMMsd_MEMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_DIVSD_XMMsd_XMMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_MAXSD_XMMsd_MEMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_MAXSD_XMMsd_XMMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_PUNPCKHBW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKHBW_MMXq_MMXd + i64 rw q + i32 r d + +INTRINSIC_XED_IFORM_PUNPCKHBW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKHBW_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKHWD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKHWD_MMXq_MMXd + i64 rw q + i32 r d + +INTRINSIC_XED_IFORM_PUNPCKHWD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKHWD_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKHDQ_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKHDQ_MMXq_MMXd + i64 rw q + i32 r d + +INTRINSIC_XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKHDQ_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PACKSSDW_MMXq_MEMq + i32 rw q + i32 r q + +INTRINSIC_XED_IFORM_PACKSSDW_MMXq_MMXq + i32 rw q + i32 r q + +INTRINSIC_XED_IFORM_PACKSSDW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PACKSSDW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_MOVD_XMMdq_MEMd + i32 w dq + i32 r d + +INTRINSIC_XED_IFORM_MOVD_XMMdq_GPR32 + i32 w dq + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_MOVD_MEMd_XMMd + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_MOVD_GPR32_XMMd + INVALID w GPR32_B + i32 r d + +INTRINSIC_XED_IFORM_MOVD_MMXq_MEMd + i64 w q + i32 r d + +INTRINSIC_XED_IFORM_MOVD_MMXq_GPR32 + i64 w q + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_MOVD_MEMd_MMXd + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_MOVD_GPR32_MMXd + INVALID w GPR32_B + i32 r d + +INTRINSIC_XED_IFORM_MOVQ_XMMdq_MEMq_0F6E + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_XMMdq_GPR64 + i32 w dq + INVALID r GPR64_B + +INTRINSIC_XED_IFORM_MOVQ_MEMq_XMMq_0F7E + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_GPR64_XMMq + INVALID w GPR64_B + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_MEMq_XMMq_0FD6 + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_XMMdq_XMMq_0FD6 + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_XMMdq_MEMq_0F7E + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_XMMdq_XMMq_0F7E + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_MMXq_MEMq_0F6E + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_MMXq_GPR64 + i64 w q + INVALID r GPR64_B + +INTRINSIC_XED_IFORM_MOVQ_MEMq_MMXq_0F7E + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_GPR64_MMXq + INVALID w GPR64_B + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_MMXq_MEMq_0F6F + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_MMXq_MMXq_0F6F + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_MEMq_MMXq_0F7F + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_MMXq_MMXq_0F7F + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_MOVDQU_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_MOVDQU_MEMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMREAD_MEMq_GPR64 + i64 w q + INVALID r GPR64_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMREAD_GPR64_GPR64 + INVALID w GPR64_B + INVALID r GPR64_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMREAD_MEMd_GPR32 + i32 w d + INVALID r GPR32_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMREAD_GPR32_GPR32 + INVALID w GPR32_B + INVALID r GPR32_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMWRITE_GPR64_MEMq + INVALID r GPR64_R + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMWRITE_GPR64_GPR64 + INVALID r GPR64_R + INVALID r GPR64_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMWRITE_GPR32_MEMd + INVALID r GPR32_R + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMWRITE_GPR32_GPR32 + INVALID r GPR32_R + INVALID r GPR32_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_HADDPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_HADDPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_HSUBPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_HSUBPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVDQA_MEMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_MOVDQA_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_HADDPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_HADDPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_HSUBPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_HSUBPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_SETS_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETS_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNS_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNS_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETP_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETP_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNP_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNP_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETL_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETL_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNL_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNL_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETLE_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETLE_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNLE_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNLE_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_RSM + INVALID w rIP + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHRD_MEMv_GPRv_IMMb + int rcw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_IMMb + INVALID rcw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHRD_MEMv_GPRv_CL + int rcw v + INVALID r GPRv_R + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_CL + INVALID rcw GPRv_B + INVALID r GPRv_R + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHLD_MEMv_GPRv_IMMb + int rcw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_IMMb + INVALID rcw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHLD_MEMv_GPRv_CL + int rcw v + INVALID r GPRv_R + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_CL + INVALID rcw GPRv_B + INVALID r GPRv_R + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_MOVSX_GPRv_MEMb + INVALID w GPRv_R + u8 r b + +INTRINSIC_XED_IFORM_MOVSX_GPRv_GPR8 + INVALID w GPRv_R + INVALID r GPR8_B + +INTRINSIC_XED_IFORM_MOVSX_GPRv_MEMw + INVALID w GPRv_R + i16 r w + +INTRINSIC_XED_IFORM_MOVSX_GPRv_GPR16 + INVALID w GPRv_R + INVALID r GPR16_B + +INTRINSIC_XED_IFORM_BSWAP_GPRv + INVALID rw GPRv_SB + +INTRINSIC_XED_IFORM_PSUBUSB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBUSB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBUSB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBUSB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBUSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBUSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBUSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBUSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINUB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMINUB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMINUB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINUB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PAND_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PAND_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PAND_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PAND_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDUSB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDUSB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDUSB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDUSB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDUSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDUSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDUSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDUSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXUB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMAXUB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMAXUB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXUB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PANDN_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PANDN_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PANDN_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PANDN_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBSB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBSB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBSB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBSB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMINSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMINSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_POR_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_POR_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_POR_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_POR_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDSB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDSB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDSB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDSB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMAXSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMAXSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PXOR_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PXOR_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PXOR_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PXOR_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBD_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBQ_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBQ_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBQ_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDW_XMMdq_MEMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PADDW_XMMdq_XMMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PADDD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDD_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHADDW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHADDW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHADDW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHADDW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHADDD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHADDD_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHADDD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHADDD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHADDSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHADDSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHADDSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHADDSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHSUBW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHSUBW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHSUBW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHSUBW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHSUBD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHSUBD_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHSUBD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHSUBD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHSUBSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHSUBSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHSUBSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHSUBSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMADDUBSW_MMXq_MEMq + i8 rw q + i8 r q + +INTRINSIC_XED_IFORM_PMADDUBSW_MMXq_MMXq + i8 rw q + i8 r q + +INTRINSIC_XED_IFORM_PMADDUBSW_XMMdq_MEMdq + i8 rw dq + i8 r dq + +INTRINSIC_XED_IFORM_PMADDUBSW_XMMdq_XMMdq + i8 rw dq + i8 r dq + +INTRINSIC_XED_IFORM_PMULHRSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMULHRSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMULHRSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULHRSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSHUFB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSHUFB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSHUFB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSHUFB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSIGNB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSIGNB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSIGNB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSIGNB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSIGNW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSIGNW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSIGNW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSIGNW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSIGND_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSIGND_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSIGND_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSIGND_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PALIGNR_MMXq_MEMq_IMMb + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PALIGNR_MMXq_MMXq_IMMb + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PABSB_MMXq_MEMq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_PABSB_MMXq_MMXq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_PABSB_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PABSB_XMMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PABSW_MMXq_MEMq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_PABSW_MMXq_MMXq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_PABSW_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PABSW_XMMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PABSD_MMXq_MEMq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_PABSD_MMXq_MMXq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_PABSD_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PABSD_XMMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_POPCNT_GPRv_MEMv + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_POPCNT_GPRv_GPRv + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPGTQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PCMPGTQ_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_CRC32_GPRyy_MEMb + int rw y + u8 r b + +INTRINSIC_XED_IFORM_CRC32_GPRyy_GPR8b + int rw y + u8 r b + +INTRINSIC_XED_IFORM_CRC32_GPRyy_MEMv + int rw y + int r v + +INTRINSIC_XED_IFORM_CRC32_GPRyy_GPRv + int rw y + int r v + +INTRINSIC_XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb + f64 rw dq + f64 r dq + +INTRINSIC_XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb + f64 rw dq + f64 r dq + +INTRINSIC_XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb + f32 rw dq + f32 r dq + +INTRINSIC_XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb + f32 rw dq + f32 r dq + +INTRINSIC_XED_IFORM_BLENDVPD_XMMdq_MEMdq + f64 rw dq + f64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_BLENDVPD_XMMdq_XMMdq + f64 rw dq + f64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_BLENDVPS_XMMdq_MEMdq + f32 rw dq + f32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_BLENDVPS_XMMdq_XMMdq + f32 rw dq + f32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_PCMPEQQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PCMPEQQ_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_DPPD_XMMdq_MEMdq_IMMb + f64 rw dq + f64 r dq + +INTRINSIC_XED_IFORM_DPPD_XMMdq_XMMdq_IMMb + f64 rw dq + f64 r dq + +INTRINSIC_XED_IFORM_DPPS_XMMdq_MEMdq_IMMb + f32 rw dq + f32 r dq + +INTRINSIC_XED_IFORM_DPPS_XMMdq_XMMdq_IMMb + f32 rw dq + f32 r dq + +INTRINSIC_XED_IFORM_MOVNTDQA_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb + i32 w d + f32 r ps + +INTRINSIC_XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb + i32 w d + i32 r dq + +INTRINSIC_XED_IFORM_INSERTPS_XMMps_MEMd_IMMb + f32 rw ps + i32 r d + +INTRINSIC_XED_IFORM_INSERTPS_XMMps_XMMps_IMMb + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb + u8 rw dq + u8 r dq + +INTRINSIC_XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb + u8 rw dq + u8 r dq + +INTRINSIC_XED_IFORM_PACKUSDW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PACKUSDW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PBLENDVB_XMMdq_MEMdq + i32 rw dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_PBLENDVB_XMMdq_XMMdq + i32 rw dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb + u8 w b + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb + i32 w d + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb + i16 w w + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb + INVALID w GPR32_B + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb + i64 w q + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb + i64 w q + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb + i32 w d + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb + i32 w d + i32 r dq + +INTRINSIC_XED_IFORM_PINSRB_XMMdq_MEMb_IMMb + i32 rw dq + u8 r b + +INTRINSIC_XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb + i32 rw dq + i32 r d + +INTRINSIC_XED_IFORM_PINSRD_XMMdq_MEMd_IMMb + i32 rw dq + i32 r d + +INTRINSIC_XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb + i32 rw dq + i32 r d + +INTRINSIC_XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_PTEST_XMMdq_MEMdq + i32 r dq + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PTEST_XMMdq_XMMdq + i32 r dq + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PHMINPOSUW_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PHMINPOSUW_XMMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXSB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXSB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXSD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXSD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXUD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXUD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXUW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXUW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINSB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINSB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINSD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINSD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINUD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINUD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINUW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINUW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULLD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULLD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULDQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULDQ_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMOVSXBW_XMMdq_MEMq + i16 w dq + i8 r q + +INTRINSIC_XED_IFORM_PMOVSXBW_XMMdq_XMMq + i16 w dq + i8 r q + +INTRINSIC_XED_IFORM_PMOVSXBD_XMMdq_MEMd + i32 w dq + i8 r d + +INTRINSIC_XED_IFORM_PMOVSXBD_XMMdq_XMMd + i32 w dq + i8 r d + +INTRINSIC_XED_IFORM_PMOVSXBQ_XMMdq_MEMw + i64 w dq + i8 r w + +INTRINSIC_XED_IFORM_PMOVSXBQ_XMMdq_XMMw + i64 w dq + i8 r w + +INTRINSIC_XED_IFORM_PMOVSXWD_XMMdq_MEMq + i32 w dq + i16 r q + +INTRINSIC_XED_IFORM_PMOVSXWD_XMMdq_XMMq + i32 w dq + i16 r q + +INTRINSIC_XED_IFORM_PMOVSXWQ_XMMdq_MEMd + i64 w dq + i16 r d + +INTRINSIC_XED_IFORM_PMOVSXWQ_XMMdq_XMMd + i64 w dq + i16 r d + +INTRINSIC_XED_IFORM_PMOVSXDQ_XMMdq_MEMq + i64 w dq + i32 r q + +INTRINSIC_XED_IFORM_PMOVSXDQ_XMMdq_XMMq + i64 w dq + i32 r q + +INTRINSIC_XED_IFORM_PMOVZXBW_XMMdq_MEMq + u16 w dq + u8 r q + +INTRINSIC_XED_IFORM_PMOVZXBW_XMMdq_XMMq + u16 w dq + u8 r q + +INTRINSIC_XED_IFORM_PMOVZXBD_XMMdq_MEMd + u32 w dq + u8 r d + +INTRINSIC_XED_IFORM_PMOVZXBD_XMMdq_XMMd + u32 w dq + u8 r d + +INTRINSIC_XED_IFORM_PMOVZXBQ_XMMdq_MEMw + u64 w dq + u8 r w + +INTRINSIC_XED_IFORM_PMOVZXBQ_XMMdq_XMMw + u64 w dq + u8 r w + +INTRINSIC_XED_IFORM_PMOVZXWD_XMMdq_MEMq + u32 w dq + u16 r q + +INTRINSIC_XED_IFORM_PMOVZXWD_XMMdq_XMMq + u32 w dq + u16 r q + +INTRINSIC_XED_IFORM_PMOVZXWQ_XMMdq_MEMd + u64 w dq + u16 r d + +INTRINSIC_XED_IFORM_PMOVZXWQ_XMMdq_XMMd + u64 w dq + u16 r d + +INTRINSIC_XED_IFORM_PMOVZXDQ_XMMdq_MEMq + u64 w dq + u32 r q + +INTRINSIC_XED_IFORM_PMOVZXDQ_XMMdq_XMMq + u64 w dq + u32 r q + +INTRINSIC_XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb + i32 r dq + i32 r dq + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb + i32 r dq + i32 r dq + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb + i32 r dq + i32 r dq + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb + i32 r dq + i32 r dq + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb + i32 r dq + i32 r dq + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb + i32 r dq + i32 r dq + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XGETBV + INVALID r XED_REG_ECX + INVALID w XED_REG_EDX + INVALID w XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSETBV + INVALID r XED_REG_ECX + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID w XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSAVE_MEMmxsave + struct rw mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XRSTOR_MEMmxsave + struct r mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSAVE64_MEMmxsave + struct rw mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XRSTOR64_MEMmxsave + struct r mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_MOVBE_GPRv_MEMv + INVALID w GPRv_R + int r v + +INTRINSIC_XED_IFORM_MOVBE_MEMv_GPRv + int w v + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_GETSEC + INVALID rcw XED_REG_EAX + INVALID r XED_REG_EBX + +INTRINSIC_XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_AESENC_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESENC_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESENCLAST_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESENCLAST_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESDEC_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESDEC_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESDECLAST_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESDECLAST_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESIMC_XMMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_AESIMC_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_INVEPT_GPR64_MEMdq + INVALID r GPR64_R + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INVEPT_GPR32_MEMdq + INVALID r GPR32_R + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INVVPID_GPR64_MEMdq + INVALID r GPR64_R + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INVVPID_GPR32_MEMdq + INVALID r GPR32_R + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCHW_0F0Dr1 + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCHW_0F0Dr3 + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr4 + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr5 + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr6 + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr7 + i64 r mprefetch + +INTRINSIC_XED_IFORM_XSTORE + u8 w b + INVALID r OrCX + INVALID rw OrDX + INVALID w OrAX + +INTRINSIC_XED_IFORM_REP_XSTORE + u8 w b + INVALID rw OrCX + INVALID rw OrDX + INVALID w OrAX + +INTRINSIC_XED_IFORM_REP_XCRYPTECB + u8 w b + INVALID rw OrCX + INVALID r OrDX + INVALID r OrBX + u8 cr b + +INTRINSIC_XED_IFORM_REP_XCRYPTCBC + u8 w b + INVALID rw OrCX + INVALID r OrDX + INVALID r OrBX + INVALID r ArAX + u8 cr b + +INTRINSIC_XED_IFORM_REP_XCRYPTCTR + u8 w b + INVALID rw OrCX + INVALID r OrDX + INVALID r OrBX + INVALID r ArAX + u8 cr b + +INTRINSIC_XED_IFORM_REP_XCRYPTCFB + u8 w b + INVALID rw OrCX + INVALID r OrDX + INVALID r OrBX + INVALID r ArAX + u8 cr b + +INTRINSIC_XED_IFORM_REP_XCRYPTOFB + u8 w b + INVALID rw OrCX + INVALID r OrDX + INVALID r OrBX + INVALID r ArAX + u8 cr b + +INTRINSIC_XED_IFORM_REP_XSHA1 + INVALID rcw ArAX + INVALID rcw OrCX + u8 w b + u8 r b + +INTRINSIC_XED_IFORM_REP_XSHA256 + INVALID rcw ArAX + INVALID rcw OrCX + u8 w b + u8 r b + +INTRINSIC_XED_IFORM_REP_MONTMUL + INVALID rw XED_REG_EAX + INVALID rw XED_REG_ECX + INVALID w XED_REG_EDX + struct rw pmmsz16 + +INTRINSIC_XED_IFORM_FEMMS + +INTRINSIC_XED_IFORM_PI2FW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PI2FW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PI2FD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PI2FD_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PF2IW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PF2IW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PF2ID_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PF2ID_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFNACC_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFNACC_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFPNACC_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFPNACC_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFCMPGE_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFCMPGE_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFMIN_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFMIN_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRCP_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRCP_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRSQRT_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRSQRT_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFSUB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFSUB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFADD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFADD_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFCMPGT_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFCMPGT_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFMAX_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFMAX_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRCPIT1_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRCPIT1_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRSQIT1_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRSQIT1_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFSUBR_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFSUBR_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFACC_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFACC_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFCMPEQ_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFCMPEQ_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFMUL_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFMUL_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRCPIT2_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRCPIT2_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMULHRW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMULHRW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSWAPD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSWAPD_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PAVGUSB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PAVGUSB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_SYSCALL_AMD + INVALID w rIP + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SYSRET_AMD + INVALID w XED_REG_EIP + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMRUN_ArAX + INVALID r ArAX + +INTRINSIC_XED_IFORM_VMMCALL + +INTRINSIC_XED_IFORM_VMLOAD_ArAX + INVALID r ArAX + +INTRINSIC_XED_IFORM_VMSAVE + +INTRINSIC_XED_IFORM_STGI + +INTRINSIC_XED_IFORM_CLGI + +INTRINSIC_XED_IFORM_SKINIT_EAX + INVALID r XED_REG_EAX + +INTRINSIC_XED_IFORM_INVLPGA_ArAX_ECX + INVALID r ArAX + INVALID r XED_REG_ECX + +INTRINSIC_XED_IFORM_EXTRQ_XMMq_IMMb_IMMb + i64 w q + +INTRINSIC_XED_IFORM_EXTRQ_XMMq_XMMdq + i64 w q + i32 r dq + +INTRINSIC_XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_INSERTQ_XMMq_XMMdq + i64 w q + i32 r dq + +INTRINSIC_XED_IFORM_MOVNTSD_MEMq_XMMq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVNTSS_MEMd_XMMd + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_CLZERO + INVALID r ArAX + +INTRINSIC_XED_IFORM_MONITORX + INVALID r XED_REG_EAX + INVALID r XED_REG_ECX + INVALID r XED_REG_EDX + +INTRINSIC_XED_IFORM_MWAITX + INVALID rw XED_REG_EAX + INVALID r XED_REG_ECX + +INTRINSIC_XED_IFORM_MCOMMIT + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_RDPRU + i32 w d + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_PSMASH_RAX + INVALID rw XED_REG_RAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PVALIDATE_RAX_ECX_EDX + INVALID rw XED_REG_RAX + INVALID r XED_REG_ECX + INVALID r XED_REG_EDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_RMPADJUST_RAX_RCX_RDX + INVALID rw XED_REG_RAX + INVALID r XED_REG_RCX + INVALID r XED_REG_RDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_RMPUPDATE_RAX_RCX + INVALID rw XED_REG_RAX + INVALID r XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BNDMK_BND_AGEN + INVALID w BND_R + +INTRINSIC_XED_IFORM_BNDCL_BND_AGEN + INVALID r BND_R + +INTRINSIC_XED_IFORM_BNDCL_BND_GPR64 + INVALID r BND_R + INVALID r GPR64_B + +INTRINSIC_XED_IFORM_BNDCL_BND_GPR32 + INVALID r BND_R + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_BNDCU_BND_AGEN + INVALID r BND_R + +INTRINSIC_XED_IFORM_BNDCU_BND_GPR64 + INVALID r BND_R + INVALID r GPR64_B + +INTRINSIC_XED_IFORM_BNDCU_BND_GPR32 + INVALID r BND_R + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_BNDCN_BND_AGEN + INVALID r BND_R + +INTRINSIC_XED_IFORM_BNDCN_BND_GPR64 + INVALID r BND_R + INVALID r GPR64_B + +INTRINSIC_XED_IFORM_BNDCN_BND_GPR32 + INVALID r BND_R + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_BNDMOV_BND_BND + INVALID w BND_R + INVALID r BND_B + +INTRINSIC_XED_IFORM_BNDMOV_BND_MEMq + INVALID w BND_R + u32 r q + +INTRINSIC_XED_IFORM_BNDMOV_BND_MEMdq + INVALID w BND_R + u64 r dq + +INTRINSIC_XED_IFORM_BNDMOV_MEMq_BND + u32 w q + INVALID r BND_R + +INTRINSIC_XED_IFORM_BNDMOV_MEMdq_BND + u64 w dq + INVALID r BND_R + +INTRINSIC_XED_IFORM_BNDLDX_BND_MEMbnd32 + INVALID w BND_R + u32 r bnd32 + +INTRINSIC_XED_IFORM_BNDLDX_BND_MEMbnd64 + INVALID w BND_R + u64 r bnd64 + +INTRINSIC_XED_IFORM_BNDSTX_MEMbnd32_BND + u32 w bnd32 + INVALID r BND_R + +INTRINSIC_XED_IFORM_BNDSTX_MEMbnd64_BND + u64 w bnd64 + INVALID r BND_R + +INTRINSIC_XED_IFORM_CLRSSBSY_MEMu64 + u64 rw q + +INTRINSIC_XED_IFORM_ENDBR32 + +INTRINSIC_XED_IFORM_ENDBR64 + +INTRINSIC_XED_IFORM_INCSSPD_GPR32u8 + u8 r d + u64 rw u64 + +INTRINSIC_XED_IFORM_INCSSPQ_GPR64u8 + u8 r q + u64 rw u64 + +INTRINSIC_XED_IFORM_RDSSPD_GPR32u32 + u32 w d + u64 r u64 + +INTRINSIC_XED_IFORM_RDSSPQ_GPR64u64 + u64 w q + u64 r u64 + +INTRINSIC_XED_IFORM_RSTORSSP_MEMu64 + u64 rw q + u64 w u64 + +INTRINSIC_XED_IFORM_SAVEPREVSSP + u64 r u64 + +INTRINSIC_XED_IFORM_SETSSBSY + +INTRINSIC_XED_IFORM_WRSSD_MEMu32_GPR32u32 + u32 w d + u32 r d + +INTRINSIC_XED_IFORM_WRSSQ_MEMu64_GPR64u64 + u64 w q + u64 r q + +INTRINSIC_XED_IFORM_WRUSSD_MEMu32_GPR32u32 + u32 w d + u32 r d + +INTRINSIC_XED_IFORM_WRUSSQ_MEMu64_GPR64u64 + u64 w q + u64 r q + +INTRINSIC_XED_IFORM_RDRAND_GPRv + INVALID w GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA + i32 rw dq + i32 r dq + u8 r dq + +INTRINSIC_XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA + i32 rw dq + i32 r dq + u8 r dq + +INTRINSIC_XED_IFORM_XSAVEOPT_MEMmxsave + struct rw mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSAVEOPT64_MEMmxsave + struct rw mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSAVES_MEMmxsave + struct w mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSAVES64_MEMmxsave + struct w mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XRSTORS_MEMmxsave + struct r mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XRSTORS64_MEMmxsave + struct r mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSAVEC_MEMmxsave + struct w mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSAVEC64_MEMmxsave + struct w mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_CLFLUSHOPT_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_RDSEED_GPRv + INVALID w GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_RDFSBASE_GPRy + INVALID w GPRy_B + int r y + +INTRINSIC_XED_IFORM_RDGSBASE_GPRy + INVALID w GPRy_B + int r y + +INTRINSIC_XED_IFORM_WRFSBASE_GPRy + INVALID r GPRy_B + int w y + +INTRINSIC_XED_IFORM_WRGSBASE_GPRy + INVALID r GPRy_B + int w y + +INTRINSIC_XED_IFORM_CLAC + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_STAC + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ENCLU + INVALID r XED_REG_EAX + INVALID crw XED_REG_RBX + INVALID crw XED_REG_RCX + INVALID crw XED_REG_RDX + +INTRINSIC_XED_IFORM_ENCLS + INVALID r XED_REG_EAX + INVALID crw XED_REG_RBX + INVALID crw XED_REG_RCX + INVALID crw XED_REG_RDX + +INTRINSIC_XED_IFORM_RDPID_GPR32u32 + u32 w d + u32 r d + +INTRINSIC_XED_IFORM_RDPID_GPR64u64 + u64 w q + u32 r d + +INTRINSIC_XED_IFORM_PTWRITE_GPRy + INVALID r GPRy_B + +INTRINSIC_XED_IFORM_PTWRITE_MEMy + int r y + +INTRINSIC_XED_IFORM_MOVDIR64B_GPRa_MEM + INVALID r A_GPR_R + u32 r zd + i32 w zd + +INTRINSIC_XED_IFORM_MOVDIRI_MEMu32_GPR32u32 + u32 w d + u32 r d + +INTRINSIC_XED_IFORM_MOVDIRI_MEMu64_GPR64u64 + u64 w q + u64 r q + +INTRINSIC_XED_IFORM_TPAUSE_GPR32u32 + u32 r d + u32 r d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TPAUSE_GPR64u64 + u64 r q + u32 r d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_UMONITOR_GPRa + INVALID r A_GPR_B + +INTRINSIC_XED_IFORM_UMWAIT_GPR32 + u32 r d + u32 r d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_UMWAIT_GPR64 + u64 r q + u32 r d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CLDEMOTE_MEMu8 + u8 r b + +INTRINSIC_XED_IFORM_ENCLV + u32 r d + u64 crw q + u64 crw q + u64 crw q + +INTRINSIC_XED_IFORM_TZCNT_GPRv_MEMv + INVALID w GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TZCNT_GPRv_GPRv + INVALID w GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BSF_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BSF_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMFUNC + INVALID r XED_REG_EAX + +INTRINSIC_XED_IFORM_INVPCID_GPR64_MEMdq + INVALID r GPR64_R + i32 r dq + +INTRINSIC_XED_IFORM_INVPCID_GPR32_MEMdq + INVALID r GPR32_R + i32 r dq + +INTRINSIC_XED_IFORM_LZCNT_GPRv_MEMv + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LZCNT_GPRv_GPRv + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BSR_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BSR_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XBEGIN_RELBRz + INVALID rw rIP + INVALID cw XED_REG_EAX + +INTRINSIC_XED_IFORM_XEND + +INTRINSIC_XED_IFORM_XABORT_IMMb + INVALID rcw XED_REG_EAX + +INTRINSIC_XED_IFORM_XTEST + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR32d_GPR32d + i32 rw d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR32d_MEMd + i32 rw d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR64q_GPR64q + i64 rw q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR64q_MEMq + i64 rw q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR32d_GPR32d + i32 rw d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR32d_MEMd + i32 rw d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR64q_GPR64q + i64 rw q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR64q_MEMq + i64 rw q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RDPKRU + INVALID w XED_REG_EDX + INVALID w XED_REG_EAX + INVALID r XED_REG_ECX + +INTRINSIC_XED_IFORM_WRPKRU + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_ECX + +INTRINSIC_XED_IFORM_CLWB_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCHWT1_MEMu8 + u8 r b + +INTRINSIC_XED_IFORM_WBINVD + +INTRINSIC_XED_IFORM_WBNOINVD + +INTRINSIC_XED_IFORM_PCONFIG + u32 rw d + u32 crw d + u32 crw d + u32 crw d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8 + u8 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8 + u8 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8 + u8 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8 + u8 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_GF2P8MULB_XMMu8_XMMu8 + u8 rw dq + u8 r dq + +INTRINSIC_XED_IFORM_GF2P8MULB_XMMu8_MEMu8 + u8 rw dq + u8 r dq + +INTRINSIC_XED_IFORM_ENQCMD_GPRa_MEMu32 + INVALID r A_GPR_R + u32 r zd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ENQCMDS_GPRa_MEMu32 + INVALID r A_GPR_R + u32 r zd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XRESLDTRK + +INTRINSIC_XED_IFORM_XSUSLDTRK + +INTRINSIC_XED_IFORM_SERIALIZE + +INTRINSIC_XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i1 w dq + i1 r dq + i1 r dq + i1 r dq + +INTRINSIC_XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i1 w dq + i1 r dq + i1 r dq + i1 r dq + +INTRINSIC_XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + i1 w dq + i1 r dq + i1 r dq + i1 r dq + +INTRINSIC_XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + i1 w qq + i1 r qq + i1 r qq + i1 r qq + +INTRINSIC_XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + i1 w qq + i1 r qq + i1 r qq + i1 r qq + +INTRINSIC_XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + i1 w qq + i1 r qq + i1 r qq + i1 r qq + +INTRINSIC_XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb +VL128 + u8 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb +VL128 + u8 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb +VL128 + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb +VL128 + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb +VL128 + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb +VL128 + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb +VL128 + u64 w dq + u64 r dq + +INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb +VL128 + u64 w dq + u64 r dq + +INTRINSIC_XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VFRCZPS_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VFRCZPS_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VFRCZPS_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VFRCZPS_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VFRCZPD_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VFRCZPD_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VFRCZPD_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VFRCZPD_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VFRCZSS_XMMdq_MEMd +VL128 + f32 w dq + f32 r d + +INTRINSIC_XED_IFORM_VFRCZSS_XMMdq_XMMd +VL128 + f32 w dq + f32 r d + +INTRINSIC_XED_IFORM_VFRCZSD_XMMdq_MEMq +VL128 + f64 w dq + f64 r q + +INTRINSIC_XED_IFORM_VFRCZSD_XMMdq_XMMq +VL128 + f64 w dq + f64 r q + +INTRINSIC_XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPHADDBW_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHADDBW_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHADDBD_XMMdq_MEMdq +VL128 + i32 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHADDBD_XMMdq_XMMdq +VL128 + i32 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHADDBQ_XMMdq_MEMdq +VL128 + i64 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHADDBQ_XMMdq_XMMdq +VL128 + i64 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHADDWD_XMMdq_MEMdq +VL128 + i32 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDWD_XMMdq_XMMdq +VL128 + i32 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDWQ_XMMdq_MEMdq +VL128 + i64 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDWQ_XMMdq_XMMdq +VL128 + i64 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDUBW_XMMdq_MEMdq +VL128 + u16 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPHADDUBW_XMMdq_XMMdq +VL128 + u16 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPHADDUBD_XMMdq_MEMdq +VL128 + u32 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPHADDUBD_XMMdq_XMMdq +VL128 + u32 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPHADDUBQ_XMMdq_MEMdq +VL128 + u64 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPHADDUBQ_XMMdq_XMMdq +VL128 + u64 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPHADDUWD_XMMdq_MEMdq +VL128 + u32 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPHADDUWD_XMMdq_XMMdq +VL128 + u32 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPHADDUWQ_XMMdq_MEMdq +VL128 + u64 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPHADDUWQ_XMMdq_XMMdq +VL128 + u64 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPHSUBBW_XMMdq_MEMdq +VL128 + i16 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHSUBBW_XMMdq_XMMdq +VL128 + i16 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHSUBWD_XMMdq_MEMdq +VL128 + i32 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHSUBWD_XMMdq_XMMdq +VL128 + i32 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHSUBDQ_XMMdq_MEMdq +VL128 + i64 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPHSUBDQ_XMMdq_XMMdq +VL128 + i64 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPHADDDQ_XMMdq_MEMdq +VL128 + i64 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPHADDDQ_XMMdq_XMMdq +VL128 + i64 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPHADDUDQ_XMMdq_MEMdq +VL128 + u64 w dq + u32 r dq + +INTRINSIC_XED_IFORM_VPHADDUDQ_XMMdq_XMMdq +VL128 + u64 w dq + u32 r dq + +INTRINSIC_XED_IFORM_BEXTR_XOP_GPR32d_MEMd_IMMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_XOP_GPRyy_MEMy_IMMd +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_XOP_GPR32d_GPR32d_IMMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_XOP_GPRyy_GPRyy_IMMd +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCFILL_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCFILL_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCFILL_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCFILL_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSFILL_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSFILL_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSFILL_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSFILL_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCS_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCS_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCS_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCS_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TZMSK_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TZMSK_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TZMSK_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TZMSK_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCIC_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCIC_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCIC_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCIC_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSIC_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSIC_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSIC_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSIC_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_T1MSKC_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_T1MSKC_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_T1MSKC_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_T1MSKC_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCMSK_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCMSK_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCMSK_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCMSK_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCI_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCI_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCI_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCI_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LLWPCB_GPRyy +VL128 + int w y + +INTRINSIC_XED_IFORM_SLWPCB_GPRyy +VL128 + int w y + +INTRINSIC_XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd +VL128 + int w y + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LWPINS_VGPRyy_GPR32y_IMMd +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd +VL128 + int w y + i32 r d + +INTRINSIC_XED_IFORM_LWPVAL_VGPRyy_GPR32y_IMMd +VL128 + int w y + int r y + +INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VCOMISD_XMMq_MEMq + f64 r q + f64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCOMISD_XMMq_XMMq + f64 r q + f64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCOMISS_XMMd_MEMd + f32 r d + f32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCOMISS_XMMd_XMMd + f32 r d + f32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMdq_MEMq +VL128 + f64 w dq + i32 r q + +INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMdq_XMMq +VL128 + f64 w dq + i32 r q + +INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq +VL256 + f64 w qq + i32 r dq + +INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq +VL256 + f64 w qq + i32 r dq + +INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq +VL128 + f32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq +VL128 + f32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq +VL256 + f32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq +VL256 + f32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq +VL128 + i32 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq +VL128 + i32 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq +VL256 + i32 w dq + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq +VL256 + i32 w dq + f64 r qq + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq +VL128 + i32 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq +VL128 + i32 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq +VL256 + i32 w dq + f64 r qq + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq +VL256 + i32 w dq + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_MEMdq +VL128 + f32 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_XMMdq +VL128 + f32 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_MEMqq +VL256 + f32 w dq + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_YMMqq +VL256 + f32 w dq + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq +VL128 + i32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq +VL128 + i32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq +VL256 + i32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq +VL256 + i32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq +VL128 + i32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq +VL128 + i32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq +VL256 + i32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq +VL256 + i32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2PD_XMMdq_MEMq +VL128 + f64 w dq + f32 r q + +INTRINSIC_XED_IFORM_VCVTPS2PD_XMMdq_XMMq +VL128 + f64 w dq + f32 r q + +INTRINSIC_XED_IFORM_VCVTPS2PD_YMMqq_MEMdq +VL256 + f64 w qq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PD_YMMqq_XMMdq +VL256 + f64 w qq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32d_MEMq + i32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32d_XMMq + i32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64q_MEMq + i64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64q_XMMq + i64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32d_MEMq + i32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32d_XMMq + i32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64q_MEMq + i64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64q_XMMq + i64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32d_MEMd + i32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32d_XMMd + i32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64q_MEMd + i64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64q_XMMd + i64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32d_MEMd + i32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32d_XMMd + i32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64q_MEMd + i64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64q_XMMd + i64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq + f32 w dq + f32 r dq + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq + f32 w dq + f32 r dq + f64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd + f64 w dq + f64 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d + f64 w dq + f64 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q + f64 w dq + f64 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d + f32 w dq + f32 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq + f32 w dq + f32 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q + f32 w dq + f32 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd + f64 w dq + f64 r dq + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd + f64 w dq + f64 r dq + f32 r d + +INTRINSIC_XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb +VL256 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb +VL256 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb +VL128 + f32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb +VL128 + INVALID w GPR32_B + f32 r dq + +INTRINSIC_XED_IFORM_VZEROALL +VL256 + +INTRINSIC_XED_IFORM_VZEROUPPER +VL128 + +INTRINSIC_XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VBROADCASTSS_XMMdq_MEMd +VL128 + f32 w dq + f32 r d + +INTRINSIC_XED_IFORM_VBROADCASTSS_YMMqq_MEMd +VL256 + f32 w qq + f32 r d + +INTRINSIC_XED_IFORM_VBROADCASTSS_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTSS_YMMqq_XMMdq +VL256 + f32 w qq + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTSD_YMMqq_MEMq +VL256 + f64 w qq + f64 r q + +INTRINSIC_XED_IFORM_VBROADCASTSD_YMMqq_XMMdq +VL256 + f64 w qq + f64 r dq + +INTRINSIC_XED_IFORM_VBROADCASTF128_YMMqq_MEMdq +VL256 + f64 w qq + f64 r dq + +INTRINSIC_XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r dq + +INTRINSIC_XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r dq + +INTRINSIC_XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb +VL128 + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VLDDQU_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VLDDQU_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + i32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + i32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq +VL128 + f32 w dq + i32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq +VL256 + f32 w qq + i32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + u64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + u64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq +VL128 + f64 w dq + u64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq +VL256 + f64 w qq + u64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPTEST_XMMdq_MEMdq +VL128 + i32 r dq + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPTEST_XMMdq_XMMdq +VL128 + i32 r dq + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPTEST_YMMqq_MEMqq +VL256 + i32 r qq + i32 r qq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPTEST_YMMqq_YMMqq +VL256 + i32 r qq + i32 r qq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPS_XMMdq_MEMdq +VL128 + f32 r dq + f32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPS_XMMdq_XMMdq +VL128 + f32 r dq + f32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPS_YMMqq_MEMqq +VL256 + f32 r qq + f32 r qq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPS_YMMqq_YMMqq +VL256 + f32 r qq + f32 r qq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPD_XMMdq_MEMdq +VL128 + f64 r dq + f64 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPD_XMMdq_XMMdq +VL128 + f64 r dq + f64 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPD_YMMqq_MEMqq +VL256 + f64 r qq + f64 r qq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPD_YMMqq_YMMqq +VL256 + f64 r qq + f64 r qq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMOVAPD_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVAPD_XMMdq_XMMdq_28 +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVAPD_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVAPD_XMMdq_XMMdq_29 +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_YMMqq_28 +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVAPD_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_YMMqq_29 +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVAPS_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVAPS_XMMdq_XMMdq_28 +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVAPS_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVAPS_XMMdq_XMMdq_29 +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_YMMqq_28 +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVAPS_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_YMMqq_29 +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVD_XMMdq_MEMd +VL128 + i32 w dq + i32 r d + +INTRINSIC_XED_IFORM_VMOVD_XMMdq_GPR32d +VL128 + i32 w dq + i32 r d + +INTRINSIC_XED_IFORM_VMOVD_MEMd_XMMd +VL128 + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_VMOVD_GPR32d_XMMd +VL128 + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_VMOVQ_XMMdq_MEMq_6E +VL128 + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_VMOVQ_XMMdq_GPR64q +VL128 + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_VMOVQ_MEMq_XMMq_7E +VL128 + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_VMOVQ_GPR64q_XMMq +VL128 + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_VMOVQ_XMMdq_MEMq_7E +VL128 + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_VMOVQ_XMMdq_XMMq_7E +VL128 + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_VMOVQ_MEMq_XMMq_D6 +VL128 + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_VMOVQ_XMMdq_XMMq_D6 +VL128 + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_VMOVDDUP_XMMdq_MEMq +VL128 + f64 w dq + f64 r q + +INTRINSIC_XED_IFORM_VMOVDDUP_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVDDUP_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVDDUP_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVDQA_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQA_MEMdq_XMMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVDQA_MEMqq_YMMqq +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVDQU_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVDQU_MEMdq_XMMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQU_MEMqq_YMMqq +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVSHDUP_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSHDUP_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSHDUP_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVSHDUP_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVSLDUP_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSLDUP_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSLDUP_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVSLDUP_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPABSB_XMMdq_MEMdq +VL128 + u8 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPABSB_XMMdq_XMMdq +VL128 + u8 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPABSB_YMMqq_MEMqq +VL256 + u8 w qq + i8 r qq + +INTRINSIC_XED_IFORM_VPABSB_YMMqq_YMMqq +VL256 + u8 w qq + i8 r qq + +INTRINSIC_XED_IFORM_VPABSW_XMMdq_MEMdq +VL128 + u16 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPABSW_XMMdq_XMMdq +VL128 + u16 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPABSW_YMMqq_MEMqq +VL256 + u16 w qq + i16 r qq + +INTRINSIC_XED_IFORM_VPABSW_YMMqq_YMMqq +VL256 + u16 w qq + i16 r qq + +INTRINSIC_XED_IFORM_VPABSD_XMMdq_MEMdq +VL128 + u32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPABSD_XMMdq_XMMdq +VL128 + u32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPABSD_YMMqq_MEMqq +VL256 + u32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VPABSD_YMMqq_YMMqq +VL256 + u32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb +VL256 + u32 w qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb +VL256 + u32 w qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb +VL256 + u16 w qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb +VL256 + u16 w qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb +VL256 + u16 w qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb +VL256 + u16 w qq + u16 r qq + +INTRINSIC_XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb +VL128 + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq +VL256 + u16 w qq + u16 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq +VL256 + u16 w qq + u16 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb +VL256 + u16 w qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb +VL128 + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq +VL256 + u32 w qq + u32 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq +VL256 + u32 w qq + u32 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb +VL256 + u32 w qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb +VL128 + u64 w dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq +VL256 + u64 w qq + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq +VL256 + u64 w qq + u64 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb +VL256 + u64 w qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb +VL128 + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq +VL256 + u16 w qq + u16 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq +VL256 + u16 w qq + u16 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb +VL256 + u16 w qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb +VL128 + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq +VL256 + u32 w qq + u32 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq +VL256 + u32 w qq + u32 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb +VL256 + u32 w qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb +VL128 + u64 w dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq +VL256 + u64 w qq + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq +VL256 + u64 w qq + u64 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb +VL256 + u64 w qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb +VL128 + i16 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq +VL256 + i16 w qq + i16 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq +VL256 + i16 w qq + i16 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb +VL256 + i16 w qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq +VL256 + i32 w qq + i32 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq +VL256 + i32 w qq + i32 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq +VL256 + i64 w qq + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq +VL256 + i64 w qq + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq +VL256 + i64 w qq + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq +VL256 + i64 w qq + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq +VL256 + i64 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq +VL256 + i64 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq +VL256 + i64 w qq + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq +VL256 + i64 w qq + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb +VL128 + u128 w dq + u128 r dq + +INTRINSIC_XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb +VL256 + u128 w qq + u128 r qq + +INTRINSIC_XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb +VL128 + u128 w dq + u128 r dq + +INTRINSIC_XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb +VL256 + u128 w qq + u128 r qq + +INTRINSIC_XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq +VL128 + f32 w dq + f32 r q + f32 r q + +INTRINSIC_XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VRCPPS_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VRCPPS_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VRCPPS_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VRCPPS_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VRSQRTPS_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VRSQRTPS_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VRSQRTPS_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VRSQRTPS_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSQRTPD_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VSQRTPD_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VSQRTPD_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VSQRTPD_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VSQRTPS_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VSQRTPS_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VSQRTPS_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VSQRTPS_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + u8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + u8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + u8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + u8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u16 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u16 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb +VL256 + u16 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb +VL256 + u16 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VUCOMISD_XMMdq_MEMq + f64 r dq + f64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUCOMISD_XMMdq_XMMq + f64 r dq + f64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUCOMISS_XMMdq_MEMd + f32 r dq + f32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUCOMISS_XMMdq_XMMd + f32 r dq + f32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVSS_XMMdq_MEMd + f32 w dq + f32 r d + +INTRINSIC_XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10 + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMOVSS_MEMd_XMMd + f32 w d + f32 r d + +INTRINSIC_XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11 + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMOVSD_XMMdq_MEMq + f64 w dq + f64 r q + +INTRINSIC_XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10 + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMOVSD_MEMq_XMMq + f64 w q + f64 r q + +INTRINSIC_XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11 + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMOVUPD_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_XMMdq_XMMdq_10 +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_XMMdq_XMMdq_11 +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_YMMqq_10 +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVUPD_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_YMMqq_11 +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVUPS_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPS_XMMdq_XMMdq_10 +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPS_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPS_XMMdq_XMMdq_11 +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_YMMqq_10 +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVUPS_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_YMMqq_11 +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq +VL128 + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMOVLPD_MEMq_XMMq +VL128 + f64 w q + f64 r q + +INTRINSIC_XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq +VL128 + f32 w dq + f32 r dq + f32 r q + +INTRINSIC_XED_IFORM_VMOVLPS_MEMq_XMMq +VL128 + f32 w q + f32 r q + +INTRINSIC_XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq +VL128 + f64 w dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VMOVHPD_MEMq_XMMdq +VL128 + f64 w q + f64 r dq + +INTRINSIC_XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq +VL128 + f32 w dq + f32 r q + f32 r q + +INTRINSIC_XED_IFORM_VMOVHPS_MEMq_XMMdq +VL128 + f32 w q + f32 r dq + +INTRINSIC_XED_IFORM_VMOVMSKPD_GPR32d_XMMdq +VL128 + i32 w d + f64 r dq + +INTRINSIC_XED_IFORM_VMOVMSKPD_GPR32d_YMMqq +VL256 + i32 w d + f64 r qq + +INTRINSIC_XED_IFORM_VMOVMSKPS_GPR32d_XMMdq +VL128 + i32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VMOVMSKPS_GPR32d_YMMqq +VL256 + i32 w d + f32 r qq + +INTRINSIC_XED_IFORM_VPMOVMSKB_GPR32d_XMMdq +VL128 + u32 w d + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVMSKB_GPR32d_YMMqq +VL256 + u32 w d + i8 r qq + +INTRINSIC_XED_IFORM_VPMOVSXBW_XMMdq_XMMq +VL128 + i16 w dq + i8 r q + +INTRINSIC_XED_IFORM_VPMOVSXBW_XMMdq_MEMq +VL128 + i16 w dq + i8 r q + +INTRINSIC_XED_IFORM_VPMOVSXBW_YMMqq_XMMdq +VL256 + i16 w qq + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBW_YMMqq_MEMdq +VL256 + i16 w qq + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBD_XMMdq_XMMd +VL128 + i32 w dq + i8 r d + +INTRINSIC_XED_IFORM_VPMOVSXBD_XMMdq_MEMd +VL128 + i32 w dq + i8 r d + +INTRINSIC_XED_IFORM_VPMOVSXBD_YMMqq_XMMq +VL256 + i32 w qq + i8 r q + +INTRINSIC_XED_IFORM_VPMOVSXBD_YMMqq_MEMq +VL256 + i32 w qq + i8 r q + +INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMdq_XMMw +VL128 + i64 w dq + i8 r w + +INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMdq_MEMw +VL128 + i64 w dq + i8 r w + +INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMqq_XMMd +VL256 + i64 w qq + i8 r d + +INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMqq_MEMd +VL256 + i64 w qq + i8 r d + +INTRINSIC_XED_IFORM_VPMOVSXWD_XMMdq_XMMq +VL128 + i32 w dq + i16 r q + +INTRINSIC_XED_IFORM_VPMOVSXWD_XMMdq_MEMq +VL128 + i32 w dq + i16 r q + +INTRINSIC_XED_IFORM_VPMOVSXWD_YMMqq_XMMdq +VL256 + i32 w qq + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWD_YMMqq_MEMdq +VL256 + i32 w qq + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMdq_XMMd +VL128 + i64 w dq + i16 r d + +INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMdq_MEMd +VL128 + i64 w dq + i16 r d + +INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMqq_XMMq +VL256 + i64 w qq + i16 r q + +INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMqq_MEMq +VL256 + i64 w qq + i16 r q + +INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMdq_XMMq +VL128 + i64 w dq + i32 r q + +INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMdq_MEMq +VL128 + i64 w dq + i32 r q + +INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq +VL256 + i64 w qq + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq +VL256 + i64 w qq + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBW_XMMdq_XMMq +VL128 + u16 w dq + u8 r q + +INTRINSIC_XED_IFORM_VPMOVZXBW_XMMdq_MEMq +VL128 + u16 w dq + u8 r q + +INTRINSIC_XED_IFORM_VPMOVZXBW_YMMqq_XMMdq +VL256 + u16 w qq + u8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBW_YMMqq_MEMdq +VL256 + u16 w qq + u8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBD_XMMdq_XMMd +VL128 + u32 w dq + u8 r d + +INTRINSIC_XED_IFORM_VPMOVZXBD_XMMdq_MEMd +VL128 + u32 w dq + u8 r d + +INTRINSIC_XED_IFORM_VPMOVZXBD_YMMqq_XMMq +VL256 + u32 w qq + u8 r q + +INTRINSIC_XED_IFORM_VPMOVZXBD_YMMqq_MEMq +VL256 + u32 w qq + u8 r q + +INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMdq_XMMw +VL128 + u64 w dq + u8 r w + +INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMdq_MEMw +VL128 + u64 w dq + u8 r w + +INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMqq_XMMd +VL256 + u64 w qq + u8 r d + +INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMqq_MEMd +VL256 + u64 w qq + u8 r d + +INTRINSIC_XED_IFORM_VPMOVZXWD_XMMdq_XMMq +VL128 + u32 w dq + u16 r q + +INTRINSIC_XED_IFORM_VPMOVZXWD_XMMdq_MEMq +VL128 + u32 w dq + u16 r q + +INTRINSIC_XED_IFORM_VPMOVZXWD_YMMqq_XMMdq +VL256 + u32 w qq + u16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWD_YMMqq_MEMdq +VL256 + u32 w qq + u16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMdq_XMMd +VL128 + u64 w dq + u16 r d + +INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMdq_MEMd +VL128 + u64 w dq + u16 r d + +INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMqq_XMMq +VL256 + u64 w qq + u16 r q + +INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMqq_MEMq +VL256 + u64 w qq + u16 r q + +INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMdq_XMMq +VL128 + u64 w dq + u32 r q + +INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMdq_MEMq +VL128 + u64 w dq + u32 r q + +INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq +VL256 + u64 w qq + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq +VL256 + u64 w qq + u32 r dq + +INTRINSIC_XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb +VL128 + u8 w b + u8 r dq + +INTRINSIC_XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb +VL128 + i32 w d + u8 r dq + +INTRINSIC_XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb +VL128 + i16 w w + u16 r dq + +INTRINSIC_XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15 +VL128 + i32 w d + u16 r dq + +INTRINSIC_XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5 +VL128 + i32 w d + u16 r dq + +INTRINSIC_XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb +VL128 + i64 w q + u64 r dq + +INTRINSIC_XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb +VL128 + i64 w q + u64 r dq + +INTRINSIC_XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb +VL128 + i32 w d + u32 r dq + +INTRINSIC_XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb +VL128 + i32 w d + u32 r dq + +INTRINSIC_XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb +VL128 + u8 w dq + u8 r dq + u8 r b + +INTRINSIC_XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb +VL128 + u8 w dq + u8 r dq + u8 r d + +INTRINSIC_XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb +VL128 + u16 w dq + u16 r dq + u16 r w + +INTRINSIC_XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb +VL128 + u16 w dq + u16 r dq + u16 r d + +INTRINSIC_XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb +VL128 + u32 w dq + u32 r dq + u32 r d + +INTRINSIC_XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb +VL128 + u32 w dq + u32 r dq + u32 r d + +INTRINSIC_XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb +VL128 + u64 w dq + u64 r dq + u64 r q + +INTRINSIC_XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb +VL128 + u64 w dq + u64 r dq + u64 r q + +INTRINSIC_XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb +VL128 + i32 r dq + i32 r dq + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb +VL128 + i32 r dq + i32 r dq + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq +VL128 + u8 r dq + u8 r dq + u8 w dq + +INTRINSIC_XED_IFORM_VLDMXCSR_MEMd +VL128 + i32 r d + INVALID w XED_REG_MXCSR + +INTRINSIC_XED_IFORM_VSTMXCSR_MEMd +VL128 + i32 w d + INVALID r XED_REG_MXCSR + +INTRINSIC_XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VMOVNTDQA_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVNTDQA_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVNTDQ_MEMdq_XMMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVNTDQ_MEMqq_YMMqq +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVNTPD_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVNTPD_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVNTPS_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVNTPS_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESIMC_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESIMC_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u128 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u128 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 +VL256 + u128 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 +VL256 + u128 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VCVTPH2PS_XMMdq_MEMq +VL128 + f32 w dq + f16 r q + +INTRINSIC_XED_IFORM_VCVTPH2PS_XMMdq_XMMq +VL128 + f32 w dq + f16 r q + +INTRINSIC_XED_IFORM_VCVTPH2PS_YMMqq_MEMdq +VL256 + f32 w qq + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2PS_YMMqq_XMMdq +VL256 + f32 w qq + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb +VL128 + f16 w q + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb +VL128 + f16 w q + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb +VL256 + f16 w dq + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb +VL256 + f16 w dq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 +VL256 + f64 crw qq + f64 r q + i64 rw qq + +INTRINSIC_XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 +VL128 + f64 crw dq + f64 r q + i64 rw dq + +INTRINSIC_XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 +VL256 + f32 crw qq + f32 r d + i32 rw qq + +INTRINSIC_XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 +VL128 + f32 crw dq + f32 r d + i32 rw dq + +INTRINSIC_XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 +VL256 + f64 crw qq + f64 r q + i64 rw qq + +INTRINSIC_XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 +VL128 + f64 crw dq + f64 r q + i64 rw dq + +INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 +VL256 + f32 crw dq + f32 r d + i32 rw dq + +INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 +VL128 + f32 crw q + f32 r d + i32 rw q + +INTRINSIC_XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 +VL256 + u64 crw qq + u64 r q + i64 rw qq + +INTRINSIC_XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 +VL128 + u64 crw dq + u64 r q + i64 rw dq + +INTRINSIC_XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 +VL256 + u32 crw qq + u32 r d + i32 rw qq + +INTRINSIC_XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 +VL128 + u32 crw dq + u32 r d + i32 rw dq + +INTRINSIC_XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 +VL256 + u64 crw qq + u64 r q + i64 rw qq + +INTRINSIC_XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 +VL128 + u64 crw dq + u64 r q + i64 rw dq + +INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 +VL256 + u32 crw dq + u32 r d + i32 rw dq + +INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 +VL128 + u32 crw q + u32 r d + i32 rw q + +INTRINSIC_XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb +VL256 + u128 w qq + u128 r qq + u128 r dq + +INTRINSIC_XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb +VL256 + u128 w qq + u128 r qq + u128 r dq + +INTRINSIC_XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb +VL256 + u128 w dq + u128 r qq + +INTRINSIC_XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb +VL256 + u128 w dq + u128 r qq + +INTRINSIC_XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb +VL256 + u64 w qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb +VL256 + u64 w qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPBROADCASTB_XMMdq_MEMb +VL128 + u8 w dq + u8 r b + +INTRINSIC_XED_IFORM_VPBROADCASTB_XMMdq_XMMb +VL128 + u8 w dq + u8 r b + +INTRINSIC_XED_IFORM_VPBROADCASTB_YMMqq_MEMb +VL256 + u8 w qq + u8 r b + +INTRINSIC_XED_IFORM_VPBROADCASTB_YMMqq_XMMb +VL256 + u8 w qq + u8 r b + +INTRINSIC_XED_IFORM_VPBROADCASTW_XMMdq_MEMw +VL128 + u16 w dq + u16 r w + +INTRINSIC_XED_IFORM_VPBROADCASTW_XMMdq_XMMw +VL128 + u16 w dq + u16 r w + +INTRINSIC_XED_IFORM_VPBROADCASTW_YMMqq_MEMw +VL256 + u16 w qq + u16 r w + +INTRINSIC_XED_IFORM_VPBROADCASTW_YMMqq_XMMw +VL256 + u16 w qq + u16 r w + +INTRINSIC_XED_IFORM_VPBROADCASTD_XMMdq_MEMd +VL128 + u32 w dq + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_XMMdq_XMMd +VL128 + u32 w dq + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_YMMqq_MEMd +VL256 + u32 w qq + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_YMMqq_XMMd +VL256 + u32 w qq + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMdq_MEMq +VL128 + u64 w dq + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMdq_XMMq +VL128 + u64 w dq + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMqq_MEMq +VL256 + u64 w qq + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMqq_XMMq +VL256 + u64 w qq + u64 r q + +INTRINSIC_XED_IFORM_VBROADCASTI128_YMMqq_MEMdq +VL256 + u128 w qq + u128 r dq + +INTRINSIC_XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSR_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSR_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSR_VGPR64q_MEMq +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSR_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSMSK_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSMSK_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSMSK_VGPR64q_MEMq +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSMSK_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSI_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSI_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSI_VGPR64q_MEMq +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSI_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 w d + i32 r d + INVALID r XED_REG_EDX + +INTRINSIC_XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd +VL128 + i32 w d + i32 w d + i32 r d + INVALID r XED_REG_EDX + +INTRINSIC_XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 w q + i64 r q + INVALID r XED_REG_RDX + +INTRINSIC_XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq +VL128 + i64 w q + i64 w q + i64 r q + INVALID r XED_REG_RDX + +INTRINSIC_XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb +VL128 + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_RORX_VGPR32d_MEMd_IMMb +VL128 + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb +VL128 + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_RORX_VGPR64q_MEMq_IMMb +VL128 + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512 +VL128 + i1 w mskw + u16 r mskw + +INTRINSIC_XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512 +VL128 + i1 w mskw + u16 r wrd + +INTRINSIC_XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512 +VL128 + u16 w wrd + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512 +VL128 + i1 w mskw + u32 r d + +INTRINSIC_XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512 +VL128 + u32 w d + i1 r mskw + +INTRINSIC_XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512 +VL128 + i1 w mskw + u8 r mskw + +INTRINSIC_XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512 +VL128 + i1 w mskw + u8 r b + +INTRINSIC_XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512 +VL128 + u8 w b + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512 +VL128 + i1 w mskw + u32 r d + +INTRINSIC_XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512 +VL128 + u32 w d + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512 +VL128 + i1 w mskw + u32 r mskw + +INTRINSIC_XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512 +VL128 + i1 w mskw + u32 r d + +INTRINSIC_XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512 +VL128 + u32 w d + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512 +VL128 + i1 w mskw + u32 r d + +INTRINSIC_XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512 +VL128 + u32 w d + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512 +VL128 + i1 w mskw + u64 r mskw + +INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512 +VL128 + i1 w mskw + u64 r q + +INTRINSIC_XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512 +VL128 + u64 w q + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512 +VL128 + i1 w mskw + u64 r q + +INTRINSIC_XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512 +VL128 + u64 w q + i1 r mskw + +INTRINSIC_XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8 +VL128 + u8 w dq + u8 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 +VL128 + u8 w dq + u8 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 +VL256 + u8 w qq + u8 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 +VL256 + u8 w qq + u8 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 +VL128 + u8 w dq + u8 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 +VL128 + u8 w dq + u8 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 +VL256 + u8 w qq + u8 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 +VL256 + u8 w qq + u8 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8 +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8 +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8 +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8 +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + u8 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + u8 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + u8 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + u8 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + u8 r zu8 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + u8 r zu8 + u32 r vv + +INTRINSIC_XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + u8 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + u8 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + u8 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + u8 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + u8 r zu8 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + u8 r zu8 + u32 r vv + +INTRINSIC_XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + i16 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + i16 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + i16 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + i16 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + i16 r zi16 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + i16 r zi16 + u32 r vv + +INTRINSIC_XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + i16 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + i16 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + i16 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + i16 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + i16 r zi16 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + i16 r zi16 + u32 r vv + +INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + bf16 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128 +VL128 + bf16 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + bf16 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256 +VL256 + bf16 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + bf16 w zbf16 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512 +VL512 + bf16 w zbf16 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512 +VL128 + bf16 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128 +VL128 + bf16 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512 +VL256 + bf16 w dq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256 +VL256 + bf16 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512 +VL512 + bf16 w qq + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512 +VL512 + bf16 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + f32 rw dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + f32 rw dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + f32 rw qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + f32 rw qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r dq + +INTRINSIC_XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r dq + +INTRINSIC_XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + i16 r zi16 + u32 r dq + +INTRINSIC_XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + i16 r zi16 + u32 r dq + +INTRINSIC_XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r q + +INTRINSIC_XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r q + +INTRINSIC_XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r d + +INTRINSIC_XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r d + +INTRINSIC_XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r d + +INTRINSIC_XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 + i1 w mskw + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 + i1 w mskw + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 + i1 w mskw + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 + i1 w mskw + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512 + f64 r dq + f64 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512 + f64 r dq + f64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512 + f32 r dq + f32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512 + f32 r dq + f32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zd + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zd + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 +VL512 + f64 w zf64 + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 +VL512 + f64 w zf64 + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 +VL128 + f64 w dq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 +VL128 + f64 w dq + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 +VL256 + f64 w qq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 +VL256 + f64 w qq + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + i32 r zi32 + +INTRINSIC_XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 +VL128 + f32 w dq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 +VL128 + f32 w dq + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 +VL256 + f32 w qq + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 +VL256 + f32 w qq + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +VL512 + i32 w qq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 +VL512 + i32 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 +VL128 + i32 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 +VL128 + i32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 +VL256 + i32 w dq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 +VL256 + i32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 +VL512 + f32 w qq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 +VL512 + f32 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 +VL128 + f32 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 +VL128 + f32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 +VL256 + f32 w dq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 +VL256 + f32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +VL512 + u32 w qq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 +VL512 + u32 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 +VL128 + u32 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 +VL128 + u32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 +VL256 + u32 w dq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 +VL256 + u32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 +VL128 + f32 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 +VL128 + f32 w dq + i1 r mskw + f16 r q + +INTRINSIC_XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 +VL256 + f32 w qq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 +VL256 + f32 w qq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 +VL128 + i32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 +VL128 + i32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 +VL256 + i32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 +VL256 + i32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 +VL128 + f64 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 +VL128 + f64 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 +VL256 + f64 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 +VL256 + f64 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f16 w qq + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f16 w qq + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 +VL128 + f16 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 +VL128 + f16 w q + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f16 w dq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f16 w dq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 +VL128 + u32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 +VL128 + u32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 +VL256 + u32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 +VL256 + u32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512 + i32 w d + f64 r dq + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512 + i32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512 + i64 w q + f64 r dq + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512 + i64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 + f32 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 + f32 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512 + u32 w d + f64 r dq + +INTRINSIC_XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512 + u32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512 + u64 w q + f64 r dq + +INTRINSIC_XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512 + u64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 + f64 w dq + f64 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 + f64 w dq + f64 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 + f64 w dq + f64 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 + f64 w dq + f64 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 + f32 w dq + f32 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 + f32 w dq + f32 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 + f32 w dq + f32 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 + f32 w dq + f32 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 + f64 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 + f64 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512 + i32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512 + i32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512 + i64 w q + f32 r dq + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512 + i64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512 + u32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512 + u32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512 + u64 w q + f32 r dq + +INTRINSIC_XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512 + u64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +VL512 + i32 w qq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 +VL512 + i32 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 +VL128 + i32 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 +VL128 + i32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 +VL256 + i32 w dq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 +VL256 + i32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +VL512 + u32 w qq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 +VL512 + u32 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 +VL128 + u32 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 +VL128 + u32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 +VL256 + u32 w dq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 +VL256 + u32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 +VL128 + i32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 +VL128 + i32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 +VL256 + i32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 +VL256 + i32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 +VL128 + u32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 +VL128 + u32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 +VL256 + u32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 +VL256 + u32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512 + i32 w d + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512 + i32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512 + i64 w q + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512 + i64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512 + u32 w d + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512 + u32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512 + u64 w q + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512 + u64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512 + i32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512 + i32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512 + i64 w q + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512 + i64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512 + u32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512 + u32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512 + u64 w q + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512 + u64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 +VL512 + f64 w zf64 + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 +VL512 + f64 w zf64 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 +VL128 + f64 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 +VL128 + f64 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 +VL256 + f64 w qq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 +VL256 + f64 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 +VL128 + f32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 +VL128 + f32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 +VL256 + f32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 +VL256 + f32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 + f64 w dq + f64 r dq + u32 r d + +INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 + f64 w dq + f64 r dq + u32 r d + +INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 + f64 w dq + f64 r dq + u64 r q + +INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 + f64 w dq + f64 r dq + u64 r q + +INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 + f32 w dq + f32 r dq + u32 r d + +INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 + f32 w dq + f32 r dq + u32 r d + +INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 + f32 w dq + f32 r dq + u64 r q + +INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 + f32 w dq + f32 r dq + u64 r q + +INTRINSIC_XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zd + +INTRINSIC_XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zd + +INTRINSIC_XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w dq + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w dq + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f32 w dq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f32 w dq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w qq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w qq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w dq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w dq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 +VL128 + f32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 +VL128 + f32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 +VL512 + f64 w zf64 + i1 rw mskw + f64 r q + +INTRINSIC_XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 +VL128 + f64 w dq + i1 rw mskw + f64 r q + +INTRINSIC_XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 +VL256 + f64 w qq + i1 rw mskw + f64 r q + +INTRINSIC_XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 +VL512 + f32 w zf32 + i1 rw mskw + f32 r d + +INTRINSIC_XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 +VL128 + f32 w dq + i1 rw mskw + f32 r d + +INTRINSIC_XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 +VL256 + f32 w qq + i1 rw mskw + f32 r d + +INTRINSIC_XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 +VL512 + f64 w zf64 + i1 rw mskw + f64 r q + +INTRINSIC_XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 +VL128 + f64 w dq + i1 rw mskw + f64 r q + +INTRINSIC_XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 +VL256 + f64 w qq + i1 rw mskw + f64 r q + +INTRINSIC_XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 +VL512 + f32 w qq + i1 rw mskw + f32 r d + +INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 +VL128 + f32 w dq + i1 rw mskw + f32 r d + +INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 +VL256 + f32 w dq + i1 rw mskw + f32 r d + +INTRINSIC_XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r dq + +INTRINSIC_XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r dq + +INTRINSIC_XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r dq + +INTRINSIC_XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r dq + +INTRINSIC_XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r qq + +INTRINSIC_XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r qq + +INTRINSIC_XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r qq + +INTRINSIC_XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r qq + +INTRINSIC_XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 +VL128 + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zd + +INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zd + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zd + +INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zd + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512 +VL128 + u32 w dq + u32 r d + +INTRINSIC_XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + u32 r d + +INTRINSIC_XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512 +VL128 + u32 w d + u32 r dq + +INTRINSIC_XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512 +VL128 + u32 w d + u32 r dq + +INTRINSIC_XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zd + +INTRINSIC_XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r q + +INTRINSIC_XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zd + +INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zd + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zd + +INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zd + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zd + +INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zd + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zd + +INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zd + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512 +VL128 + f64 w q + f64 r dq + +INTRINSIC_XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + f32 r q + f32 r q + +INTRINSIC_XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512 +VL128 + f32 w q + f32 r dq + +INTRINSIC_XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + f32 r q + f32 r q + +INTRINSIC_XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512 +VL128 + f64 w q + f64 r q + +INTRINSIC_XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + f32 r dq + f32 r q + +INTRINSIC_XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512 +VL128 + f32 w q + f32 r q + +INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512 +VL512 + u32 w zd + u32 r zu32 + +INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512 +VL128 + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512 +VL256 + u32 w qq + u32 r qq + +INTRINSIC_XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + u32 r zd + +INTRINSIC_XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + u32 r qq + +INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512 +VL512 + f64 w zd + f64 r zf64 + +INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512 +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512 +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512 +VL512 + f32 w zd + f32 r zf32 + +INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512 +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512 +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512 +VL128 + u64 w dq + u64 r q + +INTRINSIC_XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + u64 r q + +INTRINSIC_XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512 +VL128 + u64 w q + u64 r dq + +INTRINSIC_XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512 +VL128 + u64 w q + u64 r dq + +INTRINSIC_XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + u64 r dq + +INTRINSIC_XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r q + +INTRINSIC_XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 + f64 w q + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zd + +INTRINSIC_XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zd + +INTRINSIC_XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r d + +INTRINSIC_XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 + f32 w d + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zd + +INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zd + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zd + +INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zd + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i32 r zi32 + +INTRINSIC_XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 +VL128 + i32 w dq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 +VL128 + i32 w dq + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 +VL256 + i32 w qq + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 +VL256 + i32 w qq + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r zi64 + +INTRINSIC_XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r vv + +INTRINSIC_XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r dq + +INTRINSIC_XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r vv + +INTRINSIC_XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r qq + +INTRINSIC_XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r vv + +INTRINSIC_XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r q + +INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i32 r zi32 + i32 r zi32 + +INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i32 r zi32 + i32 r vv + +INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i32 r dq + i32 r vv + +INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i32 r qq + i32 r vv + +INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 +VL512 + i1 w mskw + i1 r mskw + i32 r zi32 + i32 r zi32 + +INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 +VL512 + i1 w mskw + i1 r mskw + i32 r zi32 + i32 r vv + +INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 +VL128 + i1 w mskw + i1 r mskw + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 +VL128 + i1 w mskw + i1 r mskw + i32 r dq + i32 r vv + +INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 +VL256 + i1 w mskw + i1 r mskw + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 +VL256 + i1 w mskw + i1 r mskw + i32 r qq + i32 r vv + +INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 +VL512 + i1 w mskw + i1 r mskw + i64 r zi64 + i64 r zi64 + +INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 +VL512 + i1 w mskw + i1 r mskw + i64 r zi64 + i64 r vv + +INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 +VL128 + i1 w mskw + i1 r mskw + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 +VL128 + i1 w mskw + i1 r mskw + i64 r dq + i64 r vv + +INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 +VL256 + i1 w mskw + i1 r mskw + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 +VL256 + i1 w mskw + i1 r mskw + i64 r qq + i64 r vv + +INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i64 r zi64 + i64 r zi64 + +INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i64 r zi64 + i64 r vv + +INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i64 r dq + i64 r vv + +INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i64 r qq + i64 r vv + +INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zd + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zd + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zd + +INTRINSIC_XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zd + +INTRINSIC_XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 +VL512 + u32 w zu32 + i1 rw mskw + u32 r d + +INTRINSIC_XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 +VL128 + u32 w dq + i1 rw mskw + u32 r d + +INTRINSIC_XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 +VL256 + u32 w qq + i1 rw mskw + u32 r d + +INTRINSIC_XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 +VL512 + u64 w zu64 + i1 rw mskw + u64 r q + +INTRINSIC_XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 +VL128 + u64 w dq + i1 rw mskw + u64 r q + +INTRINSIC_XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 +VL256 + u64 w qq + i1 rw mskw + u64 r q + +INTRINSIC_XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 +VL512 + u32 w qq + i1 rw mskw + u32 r d + +INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 +VL128 + u32 w dq + i1 rw mskw + u32 r d + +INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 +VL256 + u32 w dq + i1 rw mskw + u32 r d + +INTRINSIC_XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 +VL512 + u64 w zu64 + i1 rw mskw + u64 r q + +INTRINSIC_XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 +VL128 + u64 w dq + i1 rw mskw + u64 r q + +INTRINSIC_XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 +VL256 + u64 w qq + i1 rw mskw + u64 r q + +INTRINSIC_XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i32 r zi32 + i32 r zi32 + +INTRINSIC_XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i32 r zi32 + i32 r vv + +INTRINSIC_XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 +VL128 + i32 w dq + i1 r mskw + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 +VL128 + i32 w dq + i1 r mskw + i32 r dq + i32 r vv + +INTRINSIC_XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 +VL256 + i32 w qq + i1 r mskw + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 +VL256 + i32 w qq + i1 r mskw + i32 r qq + i32 r vv + +INTRINSIC_XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r zi64 + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r zi64 + i64 r vv + +INTRINSIC_XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r dq + i64 r vv + +INTRINSIC_XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r qq + i64 r vv + +INTRINSIC_XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i32 r zi32 + i32 r zi32 + +INTRINSIC_XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i32 r zi32 + i32 r vv + +INTRINSIC_XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 +VL128 + i32 w dq + i1 r mskw + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 +VL128 + i32 w dq + i1 r mskw + i32 r dq + i32 r vv + +INTRINSIC_XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 +VL256 + i32 w qq + i1 r mskw + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 +VL256 + i32 w qq + i1 r mskw + i32 r qq + i32 r vv + +INTRINSIC_XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r zi64 + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r zi64 + i64 r vv + +INTRINSIC_XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r dq + i64 r vv + +INTRINSIC_XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r qq + i64 r vv + +INTRINSIC_XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 +VL512 + u8 w dq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 +VL512 + u8 w dq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 +VL128 + u8 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 +VL128 + u8 w d + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 +VL256 + u8 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 +VL256 + u8 w q + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 +VL512 + u16 w qq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 +VL512 + u16 w qq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 +VL128 + u16 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 +VL128 + u16 w q + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 +VL256 + u16 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 +VL256 + u16 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 +VL512 + u8 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 +VL512 + u8 w q + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 +VL128 + u8 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 +VL128 + u8 w wrd + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 +VL256 + u8 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 +VL256 + u8 w d + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 +VL512 + u32 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 +VL512 + u32 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 +VL128 + u32 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 +VL128 + u32 w q + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 +VL256 + u32 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 +VL256 + u32 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 +VL512 + u16 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 +VL512 + u16 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 +VL128 + u16 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 +VL128 + u16 w d + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 +VL256 + u16 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 +VL256 + u16 w q + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 +VL512 + i8 w dq + i1 r mskw + i32 r zi32 + +INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 +VL512 + i8 w dq + i1 r mskw + i32 r zi32 + +INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 +VL128 + i8 w dq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 +VL128 + i8 w d + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 +VL256 + i8 w dq + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 +VL256 + i8 w q + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 +VL512 + i16 w qq + i1 r mskw + i32 r zi32 + +INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 +VL512 + i16 w qq + i1 r mskw + i32 r zi32 + +INTRINSIC_XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 +VL128 + i16 w dq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 +VL128 + i16 w q + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 +VL256 + i16 w dq + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 +VL256 + i16 w dq + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 +VL512 + i8 w dq + i1 r mskw + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 +VL512 + i8 w q + i1 r mskw + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 +VL128 + i8 w dq + i1 r mskw + i64 r dq + +INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 +VL128 + i8 w wrd + i1 r mskw + i64 r dq + +INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 +VL256 + i8 w dq + i1 r mskw + i64 r qq + +INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 +VL256 + i8 w d + i1 r mskw + i64 r qq + +INTRINSIC_XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 +VL512 + i32 w qq + i1 r mskw + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 +VL512 + i32 w qq + i1 r mskw + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 +VL128 + i32 w dq + i1 r mskw + i64 r dq + +INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 +VL128 + i32 w q + i1 r mskw + i64 r dq + +INTRINSIC_XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 +VL256 + i32 w dq + i1 r mskw + i64 r qq + +INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 +VL256 + i32 w dq + i1 r mskw + i64 r qq + +INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 +VL512 + i16 w dq + i1 r mskw + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 +VL512 + i16 w dq + i1 r mskw + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 +VL128 + i16 w dq + i1 r mskw + i64 r dq + +INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 +VL128 + i16 w d + i1 r mskw + i64 r dq + +INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 +VL256 + i16 w dq + i1 r mskw + i64 r qq + +INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 +VL256 + i16 w q + i1 r mskw + i64 r qq + +INTRINSIC_XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 +VL128 + i32 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 +VL128 + i32 w dq + i1 r mskw + i8 r d + +INTRINSIC_XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 +VL256 + i32 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 +VL256 + i32 w qq + i1 r mskw + i8 r q + +INTRINSIC_XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i8 r q + +INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 +VL128 + i64 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 +VL128 + i64 w dq + i1 r mskw + i8 r wrd + +INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 +VL256 + i64 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 +VL256 + i64 w qq + i1 r mskw + i8 r d + +INTRINSIC_XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 +VL128 + i64 w dq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 +VL128 + i64 w dq + i1 r mskw + i32 r q + +INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 +VL256 + i64 w qq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 +VL256 + i64 w qq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 +VL128 + i32 w dq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 +VL128 + i32 w dq + i1 r mskw + i16 r q + +INTRINSIC_XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 +VL256 + i32 w qq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 +VL256 + i32 w qq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 +VL128 + i64 w dq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 +VL128 + i64 w dq + i1 r mskw + i16 r d + +INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 +VL256 + i64 w qq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 +VL256 + i64 w qq + i1 r mskw + i16 r q + +INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 +VL512 + u8 w dq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 +VL512 + u8 w dq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 +VL128 + u8 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 +VL128 + u8 w d + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 +VL256 + u8 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 +VL256 + u8 w q + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 +VL512 + u16 w qq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 +VL512 + u16 w qq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 +VL128 + u16 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 +VL128 + u16 w q + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 +VL256 + u16 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 +VL256 + u16 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 +VL512 + u8 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 +VL512 + u8 w q + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 +VL128 + u8 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 +VL128 + u8 w wrd + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 +VL256 + u8 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 +VL256 + u8 w d + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 +VL512 + u32 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 +VL512 + u32 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 +VL128 + u32 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 +VL128 + u32 w q + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 +VL256 + u32 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 +VL256 + u32 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 +VL512 + u16 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 +VL512 + u16 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 +VL128 + u16 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 +VL128 + u16 w d + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 +VL256 + u16 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 +VL256 + u16 w q + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 +VL128 + i32 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 +VL128 + i32 w dq + i1 r mskw + i8 r d + +INTRINSIC_XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 +VL256 + i32 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 +VL256 + i32 w qq + i1 r mskw + i8 r q + +INTRINSIC_XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i8 r q + +INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 +VL128 + i64 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 +VL128 + i64 w dq + i1 r mskw + i8 r wrd + +INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 +VL256 + i64 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 +VL256 + i64 w qq + i1 r mskw + i8 r d + +INTRINSIC_XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 +VL128 + i64 w dq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 +VL128 + i64 w dq + i1 r mskw + i32 r q + +INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 +VL256 + i64 w qq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 +VL256 + i64 w qq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 +VL128 + i32 w dq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 +VL128 + i32 w dq + i1 r mskw + i16 r q + +INTRINSIC_XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 +VL256 + i32 w qq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 +VL256 + i32 w qq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 +VL128 + i64 w dq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 +VL128 + i64 w dq + i1 r mskw + i16 r d + +INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 +VL256 + i64 w qq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 +VL256 + i64 w qq + i1 r mskw + i16 r q + +INTRINSIC_XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r zi64 + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r zi64 + i64 r vv + +INTRINSIC_XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r dq + i64 r vv + +INTRINSIC_XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r qq + i64 r vv + +INTRINSIC_XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 +VL512 + u32 w d + i1 rw mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 +VL128 + u32 w d + i1 rw mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 +VL256 + u32 w d + i1 rw mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 +VL512 + u64 w q + i1 rw mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 +VL128 + u64 w q + i1 rw mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 +VL256 + u64 w q + i1 rw mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 +VL512 + u32 w d + i1 rw mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 +VL128 + u32 w d + i1 rw mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 +VL256 + u32 w d + i1 rw mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 +VL512 + u64 w q + i1 rw mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 +VL128 + u64 w q + i1 rw mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 +VL256 + u64 w q + i1 rw mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 +VL512 + f64 w q + i1 rw mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 +VL128 + f64 w q + i1 rw mskw + f64 r dq + +INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 +VL256 + f64 w q + i1 rw mskw + f64 r qq + +INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 +VL512 + f32 w d + i1 rw mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 +VL128 + f32 w d + i1 rw mskw + f32 r dq + +INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 +VL256 + f32 w d + i1 rw mskw + f32 r qq + +INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 +VL512 + f64 w q + i1 rw mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 +VL128 + f64 w q + i1 rw mskw + f64 r dq + +INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 +VL256 + f64 w q + i1 rw mskw + f64 r qq + +INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 +VL512 + f32 w d + i1 rw mskw + f32 r qq + +INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 +VL128 + f32 w d + i1 rw mskw + f32 r dq + +INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 +VL256 + f32 w d + i1 rw mskw + f32 r dq + +INTRINSIC_XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512 + f64 r dq + f64 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512 + f64 r dq + f64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512 + f32 r dq + f32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512 + f32 r dq + f32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD +VL512 + u64 w zu64 + u64 r mskw + +INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 +VL128 + u64 w dq + u64 r mskw + +INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 +VL256 + u64 w qq + u64 r mskw + +INTRINSIC_XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD +VL512 + u32 w zu32 + u32 r mskw + +INTRINSIC_XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 +VL128 + u32 w dq + u32 r mskw + +INTRINSIC_XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 +VL256 + u32 w qq + u32 r mskw + +INTRINSIC_XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r q + +INTRINSIC_XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r q + +INTRINSIC_XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r q + +INTRINSIC_XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r q + +INTRINSIC_XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r q + +INTRINSIC_XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 +VL128 + i64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 +VL128 + i64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 +VL256 + i64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 +VL256 + i64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 +VL128 + u64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 +VL128 + u64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 +VL256 + u64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 +VL256 + u64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 +VL128 + i64 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 +VL128 + i64 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 +VL256 + i64 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 +VL256 + i64 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 +VL128 + u64 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 +VL128 + u64 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 +VL256 + u64 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 +VL256 + u64 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 +VL128 + i64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 +VL128 + i64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 +VL256 + i64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 +VL256 + i64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 +VL128 + f32 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 +VL128 + f32 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 +VL256 + f32 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 +VL256 + f32 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +VL512 + f32 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 +VL512 + f32 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 +VL128 + i64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 +VL128 + i64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 +VL256 + i64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 +VL256 + i64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 +VL128 + u64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 +VL128 + u64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 +VL256 + u64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 +VL256 + u64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 +VL128 + i64 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 +VL128 + i64 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 +VL256 + i64 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 +VL256 + i64 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 +VL128 + u64 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 +VL128 + u64 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 +VL256 + u64 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 +VL256 + u64 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 +VL128 + f64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 +VL128 + f64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 +VL256 + f64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 +VL256 + f64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 +VL128 + f32 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 +VL128 + f32 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 +VL256 + f32 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 +VL256 + f32 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +VL512 + f32 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 +VL512 + f32 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w qq + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w qq + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + f64 w dq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + f64 w dq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w dq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w dq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w qq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w qq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 +VL128 + i1 w mskw + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 +VL256 + i1 w mskw + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 +VL512 + i1 w mskw + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 +VL128 + i1 w mskw + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 +VL256 + i1 w mskw + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 +VL512 + i1 w mskw + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 + i1 w mskw + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 + i1 w mskw + i1 r mskw + f64 r q + +INTRINSIC_XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 + i1 w mskw + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 + i1 w mskw + i1 r mskw + f32 r d + +INTRINSIC_XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r qq + +INTRINSIC_XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r qq + +INTRINSIC_XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r dq + +INTRINSIC_XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r dq + +INTRINSIC_XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r dq + +INTRINSIC_XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r dq + +INTRINSIC_XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r qq + +INTRINSIC_XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r qq + +INTRINSIC_XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 +VL512 + u16 w zd + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + +INTRINSIC_XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zd + +INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 +VL512 + u8 w zd + i1 r mskw + u8 r zu8 + +INTRINSIC_XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + +INTRINSIC_XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + +INTRINSIC_XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + +INTRINSIC_XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zd + +INTRINSIC_XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + +INTRINSIC_XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zd + +INTRINSIC_XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 +VL128 + i16 w dq + i1 r mskw + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 +VL128 + i16 w dq + i1 r mskw + i32 r dq + i32 r vv + +INTRINSIC_XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 +VL256 + i16 w qq + i1 r mskw + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 +VL256 + i16 w qq + i1 r mskw + i32 r qq + i32 r vv + +INTRINSIC_XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i32 r zi32 + i32 r zi32 + +INTRINSIC_XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i32 r zi32 + i32 r vv + +INTRINSIC_XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i8 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i8 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i8 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i8 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u16 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u16 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u16 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u16 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u8 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u8 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u8 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u8 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zi8 + +INTRINSIC_XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zd + +INTRINSIC_XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r b + +INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r d + +INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r b + +INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r d + +INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r b + +INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r d + +INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r wrd + +INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r d + +INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r wrd + +INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r d + +INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r wrd + +INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r d + +INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i8 r zi8 + i8 r zi8 + +INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i8 r zi8 + i8 r zd + +INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 +VL128 + u8 w d + u8 r dq + +INTRINSIC_XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 +VL128 + u8 w b + u8 r dq + +INTRINSIC_XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 +VL128 + u32 w d + u32 r dq + +INTRINSIC_XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 +VL128 + u32 w d + u32 r dq + +INTRINSIC_XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 +VL128 + u64 w q + u64 r dq + +INTRINSIC_XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 +VL128 + u64 w q + u64 r dq + +INTRINSIC_XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 +VL128 + u16 w d + u16 r dq + +INTRINSIC_XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 +VL128 + u16 w wrd + u16 r dq + +INTRINSIC_XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 +VL128 + u16 w d + u16 r dq + +INTRINSIC_XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 +VL128 + u8 w dq + u8 r dq + u8 r d + +INTRINSIC_XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 +VL128 + u8 w dq + u8 r dq + u8 r b + +INTRINSIC_XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 +VL128 + u32 w dq + u32 r dq + u32 r d + +INTRINSIC_XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + u32 r dq + u32 r d + +INTRINSIC_XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 +VL128 + u64 w dq + u64 r dq + u64 r q + +INTRINSIC_XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + u64 r dq + u64 r q + +INTRINSIC_XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 +VL128 + u16 w dq + u16 r dq + u16 r d + +INTRINSIC_XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + u16 r dq + u16 r wrd + +INTRINSIC_XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i32 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i32 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i32 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i32 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zi8 + +INTRINSIC_XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zd + +INTRINSIC_XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zi8 + +INTRINSIC_XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zd + +INTRINSIC_XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512 +VL128 + i1 w mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512 +VL256 + i1 w mskw + u8 r qq + +INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512 +VL512 + i1 w mskw + u8 r zu8 + +INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512 +VL128 + i1 w mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512 +VL256 + i1 w mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512 +VL512 + i1 w mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512 +VL128 + u8 w dq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512 +VL256 + u8 w qq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512 +VL512 + u8 w zu8 + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512 +VL128 + u32 w dq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512 +VL256 + u32 w qq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512 +VL512 + u32 w zu32 + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512 +VL128 + u64 w dq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512 +VL256 + u64 w qq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512 +VL512 + u64 w zu64 + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512 +VL128 + u16 w dq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512 +VL256 + u16 w qq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512 +VL512 + u16 w zu16 + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512 +VL128 + i1 w mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512 +VL256 + i1 w mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512 +VL512 + i1 w mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 +VL128 + i8 w dq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 +VL128 + i8 w q + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 +VL256 + i8 w dq + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 +VL256 + i8 w dq + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 +VL512 + i8 w qq + i1 r mskw + i16 r zi16 + +INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 +VL512 + i8 w qq + i1 r mskw + i16 r zi16 + +INTRINSIC_XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 +VL128 + i16 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 +VL128 + i16 w dq + i1 r mskw + i8 r q + +INTRINSIC_XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 +VL256 + i16 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 +VL256 + i16 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i8 r qq + +INTRINSIC_XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i8 r qq + +INTRINSIC_XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 +VL128 + u8 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 +VL128 + u8 w q + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 +VL256 + u8 w dq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 +VL256 + u8 w dq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 +VL512 + u8 w qq + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 +VL512 + u8 w qq + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512 +VL128 + i1 w mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512 +VL256 + i1 w mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512 +VL512 + i1 w mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 +VL128 + u8 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 +VL128 + u8 w q + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 +VL256 + u8 w dq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 +VL256 + u8 w dq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 +VL512 + u8 w qq + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 +VL512 + u8 w qq + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 +VL128 + i16 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 +VL128 + i16 w dq + i1 r mskw + i8 r q + +INTRINSIC_XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 +VL256 + i16 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 +VL256 + i16 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i8 r qq + +INTRINSIC_XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i8 r qq + +INTRINSIC_XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 +VL128 + u16 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 +VL128 + u16 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 +VL256 + u16 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 +VL256 + u16 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 +VL512 + u16 w zu16 + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 +VL512 + u16 w zu16 + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 +VL128 + u8 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 +VL128 + u8 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 +VL256 + u8 w qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 +VL256 + u8 w qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 +VL512 + u8 w zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 +VL512 + u8 w zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 +VL128 + u8 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 +VL128 + u8 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 +VL256 + u8 w qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 +VL256 + u8 w qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 +VL512 + u8 w zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 +VL512 + u8 w zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zi8 + +INTRINSIC_XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zd + +INTRINSIC_XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 rw dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 rw dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 rw qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 rw qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 rw zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 rw zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 rw dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 rw dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 rw qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 rw qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 rw zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 rw zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u64 r vv + +INTRINSIC_XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + +INTRINSIC_XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zd + +INTRINSIC_XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u8 r zd + +INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512 +VL512 + u8 w zd + i1 r mskw + u8 r zu8 + +INTRINSIC_XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + +INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512 +VL512 + u16 w zd + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zd + +INTRINSIC_XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + +INTRINSIC_XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u64 r zu64 + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u64 r vv + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u64 r zu64 + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u64 r vv + +INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zu128 + +INTRINSIC_XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zd + +INTRINSIC_XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zu128 + +INTRINSIC_XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zd + +INTRINSIC_XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zu128 + +INTRINSIC_XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zd + +INTRINSIC_XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zu128 + +INTRINSIC_XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zd + +INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512 +VL128 + u128 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 +VL128 + u128 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 +VL256 + u128 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 +VL256 + u128 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 +VL512 + u128 w zu128 + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u128 w zu128 + u64 r zu64 + u64 r zd + +INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + i1 w mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + i1 w mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + i1 w mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + i1 w mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + i1 w mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + i1 w mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + i1 w mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + i1 w mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + i1 w mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + i1 w mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + i1 w mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + i1 w mskw + u64 r zu64 + u64 r vv + diff --git a/arch/x86/code_generator/parse-iform-types.py b/arch/x86/code_generator/parse-iform-types.py new file mode 100755 index 00000000..27631d2a --- /dev/null +++ b/arch/x86/code_generator/parse-iform-types.py @@ -0,0 +1,452 @@ +#!/usr/bin/env python3 + +# These are not real registers and should be excluded from the intrinsic types +XED_INVALID_OPERAND_REGISTERS = { + 'XED_REG_INVALID', + 'XED_REG_MSRS', + 'XED_REG_STACKPUSH', + 'XED_REG_STACKPOP', + 'XED_REG_ERROR', + 'XED_REG_LAST', +} + +class TypeCacher(): + + def __init__(self, name): + self.cached_types = [] + self.name = name + + def get_cached_type_str(self, type_str): + try: + cached_type_str = 'X86CommonArchitecture::cached_%s_types[%d]' % (self.name, self.cached_types.index(type_str)) + except: + self.cached_types.append(type_str) + cached_type_str = 'X86CommonArchitecture::cached_%s_types[%d]' % (self.name, len(self.cached_types) - 1) + + return cached_type_str + + def dump_to_file(self, decl_path): + with open(decl_path, 'w') as output: + output.write('// Generated file, please do not edit directly\n\n') + type_id_str = self.cached_types[0].split(' ')[0] + n = len(self.cached_types) + output.write(f'X86CommonArchitecture::cached_{self.name}_types = new {type_id_str}[{n}];\n') + for idx, cached_type in enumerate(self.cached_types): + output.write(f'X86CommonArchitecture::cached_{self.name}_types[{idx}] = {cached_type};\n') + +class CodeGenerator(): + + def __init__(self, path, vector_element_name, enclose_element_with, name, rw): + self.file = open(path, 'w') + self.write_header() + self.vector_element_name = vector_element_name + self.enclose_element_with = enclose_element_with + self.rw = rw + self.name = name + self.type_cacher = TypeCacher(name) + # if you do not exclude these, when you run code like `Architecture['x86_64']`, + # if will create integer of size 576 + self.excluded_intrinsics = [ + 'INTRINSIC_XED_IFORM_XSAVE_MEMmxsave', + 'INTRINSIC_XED_IFORM_XSAVE64_MEMmxsave', + 'INTRINSIC_XED_IFORM_XSAVEOPT_MEMmxsave', + 'INTRINSIC_XED_IFORM_XSAVEOPT64_MEMmxsave', + 'INTRINSIC_XED_IFORM_XSAVES_MEMmxsave', + 'INTRINSIC_XED_IFORM_XSAVES64_MEMmxsave', + 'INTRINSIC_XED_IFORM_XSAVEC_MEMmxsave', + 'INTRINSIC_XED_IFORM_XSAVEC64_MEMmxsave', + 'INTRINSIC_XED_IFORM_XRSTOR_MEMmxsave', + 'INTRINSIC_XED_IFORM_XRSTOR64_MEMmxsave', + 'INTRINSIC_XED_IFORM_XRSTORS_MEMmxsave', + 'INTRINSIC_XED_IFORM_XRSTORS64_MEMmxsave', + ] + + def clean_up(self): + self.file.close() + + def write_header(self): + self.file.write('// Generated file, please do not edit directly\n\n') + + def generate_intrinsic(self, ins): + + if ins.iform in self.excluded_intrinsics: + return + + s = 'case %s:' % ins.iform + s += '\n\treturn ' + return_str = 'vector<%s> ' % self.vector_element_name + return_str += '{ ' + for operand in ins.operands: + if not self.rw in operand.rw: + continue + + op_str = operand.generate_str() + + if self.enclose_element_with == '': + return_str += '%s, ' % op_str + else: + return_str += '%s(%s), ' % (self.enclose_element_with, op_str) + + if return_str.endswith(', '): + return_str = return_str[:-2] + + return_str += ' }' + return_str = self.type_cacher.get_cached_type_str(return_str) + s += return_str + s += ';\n' + self.file.write(s) + + def dump_cached_types(self): + self.type_cacher.dump_to_file(f'../x86_intrinsic_cached_{self.name}_types.include') + +class Intrinsic(): + def __init__(self): + self.iform = '' + self.operands = [] + self.vl = None + + def reset(self): + self.iform = '' + self.operands = [] + self.vl = None + + def set_iform(self, iform): + self.iform = iform + + def set_VL(self, vl): + self.vl = vl + + def add_operand(self, operand): + if operand.oc2 == 'vv': + if self.vl is None: + print('cannot determine number of elements') + # more info goes here + else: + operand.oc2 = self.vl + elif operand.oc2 in XED_INVALID_OPERAND_REGISTERS: + # These are not real registers + return + + operand.parse() + self.operands.append(operand) + +class Operand(): + + def __init__(self, xtype, rw, oc2): + self.xtype = xtype + self.rw = rw + self.oc2 = oc2 + + def parse(self): + # from build/obj/dgen/all-element-types.txt + # #XTYPE TYPE BITS-PER-ELEM + # # + # var VARIABLE 0 # instruction must set NELEM and ELEMENT_SIZE + # struct STRUCT 0 # many elements of different widths + # int INT 0 # one element, all the bits, width varies + # uint UINT 0 # one element, all the bits, width varies + # # + # i1 INT 1 + # i8 INT 8 + # i16 INT 16 + # i32 INT 32 + # i64 INT 64 + # u8 UINT 8 + # u16 UINT 16 + # u32 UINT 32 + # u64 UINT 64 + # u128 UINT 128 + # u256 UINT 256 + # f32 SINGLE 32 + # f64 DOUBLE 64 + # f80 LONGDOUBLE 80 + # b80 LONGBCD 80 + + self.signed = (self.xtype[0] == 'i') + + if self.xtype[0] == 'f': + self.type = 'float' + elif self.xtype == 'i1': + self.type = 'boolean' + else: + self.type = 'int' + + # thse lengths are obtained from A.2.2 Codes for Operand Type + # of the Intel Dev Manual Volume 2 + # See comment inside for varying sizes + size_mapping = { + 'f80': 80, + 'mem32real': 32, + 'mem64real': 64, + 'mem80real': 80, + 'm32real': 32, + 'm32int': 32, + 'm64real': 64, + 'm64int': 32, + 'm80real': 80, + 'mskw': 1, + 'mem14': 14 * 8, + 'mem28': 28 * 8, + 'mem16': 16 * 8, + 'mem94': 94 * 8, + 'mem108': 108 * 8, + 'mem32int': 32, + 'mem16int': 16, + "mem80dec": 80, + 'b': 8, + 'w': 16, + 'd': 32, + 'q': 64, + 'u64': 64, + 'dq': 128, + 'qq': 256, + 'zd': 512, + 'zu8': 512, + 'zi8': 512, + 'zi16': 512, + 'zu16': 512, + 'zuf64': 512, + 'zuf32': 512, + 'zf32': 512, + 'zf64': 512, + 'zi64': 512, + 'zu64': 512, + 'zu128': 512, + 'zi32': 512, + 'zu32': 512, + 'VL512': 512, + 'VL256': 256, + 'VL128': 128, + 'ss': 128, + 'sd': 128, + 'ps': 128, + 'pd': 128, + 'zbf16': 16, + 's': 80, + 's64': 64, + 'a16': 16, + 'a32': 32, + 'xud': 128, + 'xuq': 128, + + # The specifiers below actually map to variable sizes, e.g., v can be + # "Word, doubleword or quadword (in 64-bit mode), depending on operand-size attribute". + # However, instructions that contain such operands are mostly covered by explicit liftings, + # for example, add, sub, and mov, etc. So they do not mess up the types + # Excpetions are lzcnt, tzcnt, popcnt, and crc32, + # which have to be further splitted into various finer-grained intrinsics + 'v': 32, + 'z': 32, + 'y': 64, + + # below specifiers are not found in the list, their size are determined manually + 'spw': 32, + 'spw8': 32, + 'spw2': 32, + 'spw3': 32, + 'spw5': 32, + 'wrd': 16, + 'bnd32': 32, + 'bnd64': 64, + 'p': 64, + 'p2': 64, + 'mfpxenv': 512 * 8, + 'mxsave': 576 * 8, + 'mprefetch': 64, + 'pmmsz16': 14 * 8, + 'pmmsz32': 24 * 8, + + 'rFLAGS': 64, + 'eFLAGS': 32, + 'GPR64_R': 64, + 'GPR64_B': 64, + 'GPRv_R': 64, + 'GPRv_B': 64, + 'GPR32_R': 32, + 'GPR32_B': 32, + 'GPR16_R': 16, + 'GPR16_B': 16, + 'GPR8_R': 8, + 'GPR8_B': 8, + 'GPRy_B': 64, + 'GPRz_B': 64, + 'GPRz_R': 64, + 'GPR8_SB': 64, + 'A_GPR_R': 64, + 'A_GPR_B': 64, + 'GPRv_SB': 64, + 'BND_R': 64, + 'BND_B': 64, + 'OeAX': 16, + 'OrAX': 16, + 'OrBX': 16, + 'OrCX': 16, + 'OrDX': 16, + 'OrBP': 16, + 'OrSP': 16, + 'ArAX': 16, + 'ArBX': 16, + 'ArCX': 16, + 'ArDI': 16, + 'ArSI': 16, + 'ArBP': 16, + 'FINAL_SSEG0': 16, + 'FINAL_SSEG1': 16, + 'FINAL_DSEG': 16, + 'FINAL_DSEG0': 16, + 'FINAL_DSEG1': 16, + 'FINAL_ESEG': 16, + 'FINAL_ESEG1': 16, + 'SEG': 16, + 'SEG_MOV': 16, + 'SrSP': 64, + 'rIP': 64, + 'CR_R': 32, + 'DR_R': 32, + 'XED_REG_AL': 8, + 'XED_REG_AH': 8, + 'XED_REG_BL': 8, + 'XED_REG_BH': 8, + 'XED_REG_CL': 8, + 'XED_REG_DL': 8, + + 'XED_REG_AX': 16, + 'XED_REG_BX': 16, + 'XED_REG_CX': 16, + 'XED_REG_DX': 16, + 'XED_REG_BP': 16, + 'XED_REG_SP': 16, + 'XED_REG_SI': 16, + 'XED_REG_DI': 16, + 'XED_REG_SS': 16, + 'XED_REG_DS': 16, + 'XED_REG_ES': 16, + 'XED_REG_IP': 16, + 'XED_REG_FS': 16, + 'XED_REG_GS': 16, + 'XED_REG_CS': 16, + + 'XED_REG_EAX': 32, + 'XED_REG_EBX': 32, + 'XED_REG_ECX': 32, + 'XED_REG_EDX': 32, + 'XED_REG_EIP': 32, + 'XED_REG_ESP': 32, + 'XED_REG_EBP': 32, + 'XED_REG_ESI': 32, + 'XED_REG_EDI': 32, + + 'XED_REG_RAX': 64, + 'XED_REG_RBX': 64, + 'XED_REG_RCX': 64, + 'XED_REG_RDX': 64, + 'XED_REG_RIP': 64, + 'XED_REG_RSP': 64, + 'XED_REG_RBP': 64, + 'XED_REG_RSI': 64, + 'XED_REG_RDI': 64, + 'XED_REG_R11': 64, + + 'XED_REG_X87STATUS': 16, + 'XED_REG_X87CONTROL': 16, + 'XED_REG_X87TAG': 16, + 'XED_REG_X87PUSH': 64, + 'XED_REG_X87POP': 64, + 'XED_REG_X87POP2': 64, + + 'XED_REG_CR0': 64, + 'XED_REG_XCR0': 64, + 'XED_REG_MXCSR': 32, + + 'XED_REG_GDTR': 48, + 'XED_REG_LDTR': 48, + 'XED_REG_IDTR': 48, + + 'XED_REG_TR': 64, + 'XED_REG_TSC': 64, + 'XED_REG_TSCAUX': 64, + 'XED_REG_MSRS': 64, + } + + # if '_' in self.oc2: + # self.oc2 = self.oc2.split('_')[0] + + try: + self.width = size_mapping[self.oc2] + except: + print('I do not know the width of oc2: %s' % self.oc2) + self.width = 8 + + if self.xtype == 'struct' or self.xtype == 'INVALID': + self.element_size = self.width + elif self.xtype == 'int': + self.element_size = 32 + elif self.xtype == 'bf16': + self.element_size = 16 + else: + size_str = self.xtype[1:] + self.element_size = int(size_str) + + self.element_size_byte = int((self.element_size + 7) / 8) + + n = int((self.width + 7) / 8) / self.element_size_byte + n = int(n) + + if n < 1: + n = 1 + + self.n_element = n + + def generate_str(self): + array = False + if self.element_size > 1: + array = True + + inner_str = '' + if self.type == 'float': + inner_str = 'Type::FloatType(%d)' % self.element_size_byte + elif self.type == 'int': + signed_str = 'true' if self.signed else 'false' + inner_str = 'Type::IntegerType(%d, %s)' % (self.element_size_byte, signed_str) + else: + inner_str = 'Type::BoolType()' + + if self.n_element > 1: + s = 'Type::ArrayType(%s, %d)' % (inner_str, self.n_element) + else: + s = inner_str + + return s + +def main(): + intrinsic_input = CodeGenerator('../x86_intrinsic_input_type.include', 'NameAndType', 'NameAndType', 'input', 'r') + intrinsic_output = CodeGenerator('../x86_intrinsic_output_type.include', 'Confidence<Ref<Type>>', '', 'output', 'w') + with open('iform-type-dump.txt', 'r') as f: + ins = Intrinsic() + for line in f: + if line.strip() == '': + intrinsic_input.generate_intrinsic(ins) + intrinsic_output.generate_intrinsic(ins) + ins.reset() + continue + + if line.startswith('INTRINSIC_XED_IFORM_'): + ins.set_iform(line.strip()) + elif line.startswith('VL'): + ins.set_VL(line.strip()) + elif line.startswith('\t'): + fields = line.strip().split('\t') + op = Operand(fields[0], fields[1], fields[2]) + ins.add_operand(op) + else: + print('unexpected line! I do not know what to do with it') + print(line) + + intrinsic_input.dump_cached_types() + intrinsic_output.dump_cached_types() + + intrinsic_input.clean_up() + intrinsic_output.clean_up() + +if __name__ == '__main__': + main() diff --git a/arch/x86/code_generator/patch.diff b/arch/x86/code_generator/patch.diff new file mode 100644 index 00000000..1b22e5b6 --- /dev/null +++ b/arch/x86/code_generator/patch.diff @@ -0,0 +1,43 @@ +diff --git a/pysrc/generator.py b/pysrc/generator.py +index f2fcd93..fff7e6b 100755 +--- a/pysrc/generator.py ++++ b/pysrc/generator.py +@@ -6342,6 +6342,38 @@ def main(): + agi.close_output_files() + agi.dump_generated_files() + ++ generated_iforms = set() ++ with open('iform-type-dump.txt', 'w') as f: ++ for generator in agi.generator_list: ++ ii = generator.parser_output.instructions[0] ++ if not field_check(ii,'iclass'): ++ continue ++ for ii in generator.parser_output.instructions: ++ ++ if ii.iform_enum in generated_iforms: ++ continue ++ else: ++ generated_iforms.add(ii.iform_enum) ++ ++ f.write('INTRINSIC_XED_IFORM_' + ii.iform_enum) ++ f.write('\n') ++ s = str(ii.ipattern_input) ++ for field in s.split(' '): ++ if field.startswith('VL'): ++ f.write(field + '\n') ++ ++ for operand in ii.operands: ++ # if operand.xtype != None and operand.xtype != 'INVALID': ++ if operand.xtype != None: ++ width_hint = '' ++ if operand.oc2 != None: ++ width_hint = str(operand.oc2) ++ elif operand.lookupfn_name != None: ++ width_hint = str(operand.lookupfn_name) ++ if width_hint != '': ++ f.write('\t' + str(operand.xtype) + '\t' + operand.rw + '\t' + width_hint + '\n') ++ f.write('\n') ++ + ################################################ + + if __name__ == '__main__': |