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authorJordan Wiens <jordan@psifertex.com>2025-03-21 12:27:16 -0400
committerJordan Wiens <jordan@psifertex.com>2025-03-21 12:27:16 -0400
commitfc872ffdd8472d3f050272920d53ed73a1b535e0 (patch)
tree3b5b4f64333eb06c060fc5da133e2500a1dabab2 /arch/x86
parentc42efff0040a3dc62b350bc7157f4e84ff5273d8 (diff)
fix x86 settings text and use proper raw string marker
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/arch_x86.cpp18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/x86/arch_x86.cpp b/arch/x86/arch_x86.cpp
index 1e6044ea..eb1b710d 100644
--- a/arch/x86/arch_x86.cpp
+++ b/arch/x86/arch_x86.cpp
@@ -4761,7 +4761,7 @@ static void InitX86Settings()
{
Ref<Settings> settings = Settings::Instance();
settings->RegisterSetting("arch.x86.disassembly.syntax",
- R"({
+ R"~({
"title" : "x86 Disassembly Syntax",
"type" : "string",
"default" : "BN_INTEL",
@@ -4769,31 +4769,31 @@ static void InitX86Settings()
"description" : "Specify disassembly syntax for the x86/x86_64 architectures.",
"enum" : ["BN_INTEL", "INTEL", "AT&T"],
"enumDescriptions" : [
- "Sets the disassembly syntax to a simplified Intel format. (TBD) ",
- "Sets the disassembly syntax to Intel format. (Destination on the left) ",
- "Sets the disassembly syntax to AT&T format. (Destination on the right) "],
+ "Sets the disassembly syntax to a simplified Intel format.",
+ "Sets the disassembly syntax to Intel format. (Destination on the left)",
+ "Sets the disassembly syntax to AT&T format. (Destination on the right)"],
"ignore" : ["SettingsProjectScope", "SettingsResourceScope"]
- })");
+ })~");
settings->RegisterSetting("arch.x86.disassembly.separator",
- R"({
+ R"~({
"title" : "x86 Disassembly Separator",
"type" : "string",
"default" : ", ",
"aliases" : ["arch.x86.disassemblySeperator", "arch.x86.disassemblySeparator"],
"description" : "Specify the token separator between operands.",
"ignore" : ["SettingsProjectScope", "SettingsResourceScope"]
- })");
+ })~");
settings->RegisterSetting("arch.x86.disassembly.lowercase",
- R"({
+ R"~({
"title" : "x86 Disassembly Case",
"type" : "boolean",
"default" : true,
"aliases" : ["arch.x86.disassemblyLowercase"],
"description" : "Specify the case for opcodes, operands, and registers.",
"ignore" : ["SettingsProjectScope", "SettingsResourceScope"]
- })");
+ })~");
}