Fix many of the warnings that show up when compiling with GCC 15.2

12 files changed, 77 insertions, 74 deletions

diff --git a/arch/arm64/disassembler/decode_scratchpad.c b/arch/arm64/disassembler/decode_scratchpad.c
index f869889f..d1160980 100644
--- a/arch/arm64/disassembler/decode_scratchpad.c
+++ b/arch/arm64/disassembler/decode_scratchpad.c
@@ -1086,9 +1086,12 @@ static const char* const reg_lookup_c[16] = {"c0", "c1", "c2", "c3", "c4", "c5",
 	i++;
 
 #define ADD_OPERAND_FLOAT32(VALUE) \
-	instr->operands[i].operandClass = FIMM32; \
-	*(float*)&(instr->operands[i].immediate) = VALUE; \
-	i++;
+	do { \
+		float value = VALUE; \
+		instr->operands[i].operandClass = FIMM32; \
+		memcpy(&instr->operands[i].immediate, &value, sizeof(float)); \
+		i++; \
+	} while (0)
 
 #define ADD_OPERAND_CONST  ADD_OPERAND_IMM64(const_, 0)
 #define ADD_OPERAND_FBITS  ADD_OPERAND_IMM32(fbits, 0)
diff --git a/arch/arm64/disassembler/format.c b/arch/arm64/disassembler/format.c
index 0db5ffbc..73f82a6f 100644
--- a/arch/arm64/disassembler/format.c
+++ b/arch/arm64/disassembler/format.c
@@ -383,7 +383,8 @@ uint32_t get_shifted_immediate(const InstructionOperand *instructionOperand, cha
 	}
 	if (type == FIMM32)
 	{
-		float f = *(const float*)&instructionOperand->immediate;
+		float f = 0.0f;
+		memcpy(&f, &instructionOperand->immediate, sizeof(float));
 		if (snprintf(outBuffer, outBufferSize, "#%.08f%s", f, shiftBuff) >= outBufferSize)
 			return FAILED_TO_DISASSEMBLE_OPERAND;
 	}
diff --git a/arch/arm64/disassembler/pcode.c b/arch/arm64/disassembler/pcode.c
index 7993e312..46ffdcec 100644
--- a/arch/arm64/disassembler/pcode.c
+++ b/arch/arm64/disassembler/pcode.c
@@ -584,37 +584,29 @@ uint64_t Replicate(uint64_t val, uint8_t times, uint64_t width)
   https://github.com/Siguza/iometa/blob/master/src/a64.c */
 uint64_t AdvSIMDExpandImm(uint8_t op, uint8_t cmode, uint64_t imm8)
 {
-	uint64_t imm64;
 	switch ((cmode >> 1) & 0b111)
 	{
 	case 0b000:
-		imm64 = Replicate(imm8, 2, 32);
-		break;
+		return Replicate(imm8, 2, 32);
 	case 0b001:
-		imm64 = Replicate(imm8 << 8, 2, 32);
-		break;
+		return Replicate(imm8 << 8, 2, 32);
 	case 0b010:
-		imm64 = Replicate(imm8 << 16, 2, 32);
-		break;
+		return Replicate(imm8 << 16, 2, 32);
 	case 0b011:
-		imm64 = Replicate(imm8 << 24, 2, 32);
-		break;
+		return Replicate(imm8 << 24, 2, 32);
 	case 0b100:
-		imm64 = Replicate(imm8, 4, 16);
-		break;
+		return Replicate(imm8, 4, 16);
 	case 0b101:
-		imm64 = Replicate(imm8 << 8, 4, 16);
-		break;
+		return Replicate(imm8 << 8, 4, 16);
 	case 0b110:
-		imm64 = Replicate(imm8 << (8 << (cmode & 0b1)), 2, 32);
-		break;
+		return Replicate(imm8 << (8 << (cmode & 0b1)), 2, 32);
 	case 0b111:
 		switch (((cmode & 0b1) << 1) | op)
 		{
 		case 0b00:
-			imm64 = Replicate(imm8, 8, 8);
-			break;
+			return Replicate(imm8, 8, 8);
 		case 0b01:
+		{
 #if 0
 					imm8a = Replicate((imm8 >> 7) & 0b1, 8, 1);
 					imm8b = Replicate((imm8 >> 6) & 0b1, 8, 1);
@@ -626,26 +618,24 @@ uint64_t AdvSIMDExpandImm(uint8_t op, uint8_t cmode, uint64_t imm8)
 					imm8h = Replicate((imm8	 ) & 0b1, 8, 1);
 					imm64 = (imm8a << 0x38) | (imm8b << 0x30) | (imm8c << 0x28) | (imm8d << 0x20) | (imm8e << 0x18) | (imm8f << 0x10) | (imm8g << 0x08) | imm8h;
 #else
-			imm64 = imm8 | (imm8 << (0x08 - 1)) | (imm8 << (0x10 - 2)) | (imm8 << (0x18 - 3)) |
+			uint64_t imm64 = imm8 | (imm8 << (0x08 - 1)) | (imm8 << (0x10 - 2)) | (imm8 << (0x18 - 3)) |
 			        (imm8 << (0x20 - 4)) | (imm8 << (0x28 - 5)) | (imm8 << (0x30 - 6)) |
 			        (imm8 << (0x38 - 7));
 			imm64 &= 0x0101010101010101;
-			imm64 = Replicate(imm64, 8, 1);
+			return Replicate(imm64, 8, 1);
 #endif
-			break;
+		}
 		case 0b10:
-			imm64 = Replicate((((imm8 & 0xc0) ^ 0x80) << 24) |
+			return Replicate((((imm8 & 0xc0) ^ 0x80) << 24) |
 			                      (Replicate((imm8 >> 6) & 0b1, 5, 1) << 25) | ((imm8 & 0x3f) << 19),
 			    2, 32);
-			break;
 		case 0b11:
-			imm64 = (((imm8 & 0xc0) ^ 0x80) << 56) | (Replicate((imm8 >> 6) & 0b1, 8, 1) << 54) |
+			return (((imm8 & 0xc0) ^ 0x80) << 56) | (Replicate((imm8 >> 6) & 0b1, 8, 1) << 54) |
 			        ((imm8 & 0x3f) << 48);
-			break;
 		}
 		break;
 	}
-	return imm64;
+	return 0;
 }
 
 bool BTypeCompatible_BTI(uint8_t hintcode, uint8_t pstate_btype)
diff --git a/arch/arm64/il.cpp b/arch/arm64/il.cpp
index bbec5959..f02cdd2d 100644
--- a/arch/arm64/il.cpp
+++ b/arch/arm64/il.cpp
@@ -174,9 +174,9 @@ static ExprId GetFloat(LowLevelILFunction& il, InstructionOperand& operand, int
 		case 2:
 			return il.FloatConstRaw(2, operand.immediate);
 		case 4:
-			return il.FloatConstSingle(*(float*)&(operand.immediate));
+			return il.FloatConstSingle(std::bit_cast<float>(static_cast<uint32_t>(operand.immediate)));
 		case 8:
-			return il.FloatConstDouble(*(float*)&(operand.immediate));
+			return il.FloatConstDouble(std::bit_cast<double>(operand.immediate));
 		default:
 			break;
 		}
@@ -851,7 +851,7 @@ static void LoadStoreVector(
 		for (int i = 0; i < regs_n; ++i)
 		{
 			int reg_spec_base = (oper0.reg[0] + i - REG_V0) * (16 / arrspec_size) + lane;
-			Register reg;
+			Register reg = REG_NONE;
 			switch (arrspec_size)
 			{
 			case 1:
@@ -1343,7 +1343,7 @@ bool GetLowLevelILForInstruction(
 		case ENC_ADD_Z_ZZ_:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-				return true;
+			return true;
 		default: break;
 		}
 	case ARM64_ADDS:
@@ -1372,7 +1372,7 @@ bool GetLowLevelILForInstruction(
 		case ENC_ANDS_P_P_PP_Z:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-				return true;
+			return true;
 		default: break;
 		}
 		il.AddInstruction(
@@ -1387,7 +1387,7 @@ bool GetLowLevelILForInstruction(
 		case ENC_ADR_Z_AZ_D_U32_SCALED:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-					return true;
+			return true;
 		default: break;
 		}
 	case ARM64_ADRP:
@@ -1403,7 +1403,7 @@ bool GetLowLevelILForInstruction(
 		case ENC_ASR_Z_ZW_:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-				return true;
+			return true;
 		default: break;
 		}
 		il.AddInstruction(ILSETREG_O(operand1, il.ArithShiftRight(REGSZ_O(operand2), ILREG_O(operand2),
@@ -1415,7 +1415,7 @@ bool GetLowLevelILForInstruction(
 		case ENC_AESD_Z_ZZ_:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-				return true;
+			return true;
 		default: break;
 		}
 		il.AddInstruction(il.Intrinsic({RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_AESD,
@@ -1427,8 +1427,8 @@ bool GetLowLevelILForInstruction(
 		case ENC_AESE_Z_ZZ_:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-					return true;
-			default: break;
+			return true;
+		default: break;
 		}
 		il.AddInstruction(il.Intrinsic({RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_AESE,
 		    {ILREG_O(operand1), ILREG_O(operand2)}));
@@ -1439,8 +1439,8 @@ bool GetLowLevelILForInstruction(
 		case ENC_AESIMC_Z_Z_:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-					return true;
-			default: break;
+			return true;
+		default: break;
 		}
 		il.AddInstruction(il.Intrinsic({RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_AESIMC,
 		    {ILREG_O(operand1), ILREG_O(operand2)}));
@@ -1451,8 +1451,8 @@ bool GetLowLevelILForInstruction(
 		case ENC_AESMC_Z_Z_:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-					return true;
-			default: break;
+			return true;
+		default: break;
 		}
 		il.AddInstruction(il.Intrinsic({RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_AESMC,
 		    {ILREG_O(operand1), ILREG_O(operand2)}));
@@ -1571,7 +1571,7 @@ bool GetLowLevelILForInstruction(
 		case ENC_BICS_P_P_PP_Z:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-				return true;
+			return true;
 		case ENC_BIC_ASIMDIMM_L_HL:
 		case ENC_BIC_ASIMDIMM_L_SL:
 			il.AddInstruction(ILSETREG_O(operand1,
@@ -2962,9 +2962,9 @@ bool GetLowLevelILForInstruction(
 		case ENC_NEG_ASIMDMISC_R:
 		case ENC_NEG_Z_P_Z_M:
 		case ENC_NEG_Z_P_Z_Z:
-		if (!preferIntrinsics())
-			il.AddInstruction(il.Unimplemented());
-				return true;
+			if (!preferIntrinsics())
+				il.AddInstruction(il.Unimplemented());
+			return true;
 		default: break;
 		}
 	case ARM64_NEGS:
@@ -3098,8 +3098,8 @@ bool GetLowLevelILForInstruction(
 		{
 		case ENC_ORN_Z_ZI__ORR_Z_ZI_:
 		case ENC_ORN_P_P_PP_Z:
-		if (!preferIntrinsics())
-				il.AddInstruction(il.Unimplemented());
+			if (!preferIntrinsics())
+					il.AddInstruction(il.Unimplemented());
 			return true;
 		default: break;
 		}
@@ -3588,11 +3588,11 @@ bool GetLowLevelILForInstruction(
 	case ARM64_STR:
 		switch (instr.encoding)
 		{
-	case ENC_STR_P_BI_:
-	case ENC_STR_Z_BI_:
-	case ENC_STR_ZA_RI_:
-		if (!preferIntrinsics())
-				il.AddInstruction(il.Unimplemented());
+		case ENC_STR_P_BI_:
+		case ENC_STR_Z_BI_:
+		case ENC_STR_ZA_RI_:
+			if (!preferIntrinsics())
+					il.AddInstruction(il.Unimplemented());
 			return true;
 		default: break;
 		}
@@ -3619,9 +3619,9 @@ bool GetLowLevelILForInstruction(
 		case ENC_SUB_Z_P_ZZ_:
 		case ENC_SUB_Z_ZI_:
 		case ENC_SUB_Z_ZZ_:
-		if (!preferIntrinsics())
-			il.AddInstruction(il.Unimplemented());
-				return true;
+			if (!preferIntrinsics())
+				il.AddInstruction(il.Unimplemented());
+			return true;
 		default: break;
 		}
 	case ARM64_SUBS:
diff --git a/arch/armv7/CMakeLists.txt b/arch/armv7/CMakeLists.txt
index 802bcf6a..25847dfe 100644
--- a/arch/armv7/CMakeLists.txt
+++ b/arch/armv7/CMakeLists.txt
@@ -43,3 +43,10 @@ if(BN_INTERNAL_BUILD)
 		LIBRARY_OUTPUT_DIRECTORY ${BN_CORE_PLUGIN_DIR}
 		RUNTIME_OUTPUT_DIRECTORY ${BN_CORE_PLUGIN_DIR})
 endif()
+
+if(CMAKE_CXX_COMPILER_ID MATCHES "GNU")
+	target_compile_options(arch_armv7 PRIVATE
+		$<$<COMPILE_LANGUAGE:CXX>:-Wno-deprecated-enum-enum-conversion>
+	)
+endif()
+
diff --git a/arch/armv7/il.cpp b/arch/armv7/il.cpp
index 0d79bcf6..5e2ee010 100644
--- a/arch/armv7/il.cpp
+++ b/arch/armv7/il.cpp
@@ -906,7 +906,7 @@ bool GetLowLevelILForArmInstruction(Architecture* arch, uint64_t addr, LowLevelI
 					}
 					if (op1.flags.wb)
 					{
-						ExprId wb;
+						ExprId wb = BN_INVALID_OPERAND;
 						switch (instr.operation)
 						{
 						case ARMV7_LDM:
diff --git a/arch/mips/arch_mips.cpp b/arch/mips/arch_mips.cpp
index 0853f9fb..83d7a98d 100644
--- a/arch/mips/arch_mips.cpp
+++ b/arch/mips/arch_mips.cpp
@@ -811,6 +811,7 @@ public:
 		if (operation_name == NULL)
 			return false;
 		strncpy(operation, operation_name, sizeof(operation));
+		operation[sizeof(operation) - 1] = '\0';
 
 		if (instr.operands[0].operandClass == V_DEST)
 		{
@@ -3574,7 +3575,7 @@ public:
 				break;
 			default:
 				result[i].type = UnhandledRelocation;
-				LogWarn("Unsupported relocation type: %llu (%s) @0x%llX", result[i].nativeType,
+				LogWarn("Unsupported relocation type: %" PRIu64 " (%s) @0x%" PRIx64, result[i].nativeType,
 					GetRelocationString((ElfMipsRelocationType)result[i].nativeType), result[i].address);
 			}
 		}
diff --git a/arch/mips/il.cpp b/arch/mips/il.cpp
index 5700acbc..1d10d9dd 100644
--- a/arch/mips/il.cpp
+++ b/arch/mips/il.cpp
@@ -3176,7 +3176,7 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
 		case MIPS_LDC2:
 		case MIPS_LDC3:
 		{
-			unsigned cop;
+			unsigned cop = 0;
 			switch (instr.operation)
 			{
 				case MIPS_LDC1: cop = 1; break;
diff --git a/arch/mips/mips/mips.c b/arch/mips/mips/mips.c
index ee323f9d..37c56513 100644
--- a/arch/mips/mips/mips.c
+++ b/arch/mips/mips/mips.c
@@ -3580,6 +3580,7 @@ uint32_t mips_disassemble(
 	const char* reg = NULL;
 
 	strncpy(operation, OperationStrings[instruction->operation], sizeof(operation));
+	operation[sizeof(operation) - 1] = '\0';
 	if (instruction->operands[0].operandClass == V_DEST)
 	{
 		char* p = dest;
@@ -3744,7 +3745,7 @@ uint32_t mips_decompose(
 		const uint32_t* instructionValue,
 		size_t size,
 		Instruction* restrict instruction,
-		uint32_t version,
+		MipsVersion version,
 		uint64_t address,
 		uint32_t endianBig,
 		uint32_t flags)
diff --git a/arch/mips/mips/test.c b/arch/mips/mips/test.c
index 339126e0..00034142 100644
--- a/arch/mips/mips/test.c
+++ b/arch/mips/mips/test.c
@@ -110,11 +110,11 @@ int main(int ac, char **av)
 		baseaddr = 0;
 		if (0 == disassemble(insword, baseaddr, version, flags, instxt))
 		{
-			printf("%08llX: %08X %s\n", baseaddr, insword, instxt);
+			printf("%08" PRIX64 ": %08X %s\n", baseaddr, insword, instxt);
 		}
 		else
 		{
-			printf("%08llX: %08X ??\n", baseaddr, insword);
+			printf("%08" PRIX64 ": %08X ??\n", baseaddr, insword);
 		}
 		// disassemble(0x14E00003, 0, version, flags, instxt);
 		if (version < MIPS_32)
@@ -124,11 +124,11 @@ int main(int ac, char **av)
 		baseaddr = 0x405a58;
 		if (0 == disassemble(insword, baseaddr, version, flags, instxt))
 		{
-			printf("%08llX: %08X %s\n", baseaddr, insword, instxt);
+			printf("%08" PRIX64 ": %08X %s\n", baseaddr, insword, instxt);
 		}
 		else
 		{
-			printf("%08llX: %08X ??\n", baseaddr, insword);
+			printf("%08" PRIX64 ": %08X ??\n", baseaddr, insword);
 		}
 		// disassemble(0x14E00003, 4, version, flags, instxt);
 		if (version < MIPS_32)
@@ -186,11 +186,11 @@ int main(int ac, char **av)
 #endif
 			if (0 == disassemble(insword, baseaddr, version, flags, instxt))
 			{
-				printf("%08llX: %08X %s\n", baseaddr, insword, instxt);
+				printf("%08" PRIX64 ": %08X %s\n", baseaddr, insword, instxt);
 			}
 			else
 			{
-				printf("%08llX: %08X ??\n", baseaddr, insword);
+				printf("%08" PRIX64 ": %08X ??\n", baseaddr, insword);
 			}
 			baseaddr += 4;
 			p += 8;
@@ -202,3 +202,4 @@ int main(int ac, char **av)
 cleanup:
 	return result;
 }
+
diff --git a/arch/powerpc/arch_ppc.cpp b/arch/powerpc/arch_ppc.cpp
index f10757d5..a1605923 100644
--- a/arch/powerpc/arch_ppc.cpp
+++ b/arch/powerpc/arch_ppc.cpp
@@ -517,14 +517,14 @@ class PowerpcArchitecture: public Architecture
 
 			case PPC_OP_SIMM:
 				if (op->simm < 0 && op->simm > -0x10000)
-					snprintf(buf, sizeof(buf), "-0x%llx", -op->simm);
+					snprintf(buf, sizeof(buf), "-0x%" PRIx64, -op->simm);
 				else
-					snprintf(buf, sizeof(buf), "0x%llx", op->simm);
+					snprintf(buf, sizeof(buf), "0x%" PRIx64, op->simm);
 				result.emplace_back(IntegerToken, buf, op->simm, 4);
 				break;
 
 			case PPC_OP_LABEL:
-				snprintf(buf, sizeof(buf), "0x%llx", op->label);
+				snprintf(buf, sizeof(buf), "0x%" PRIx64, op->label);
 				result.emplace_back(CodeRelativeAddressToken, buf, op->label, 4);
 				break;
 
diff --git a/arch/powerpc/disassembler.cpp b/arch/powerpc/disassembler.cpp
index 54e3c87c..e24f273b 100644
--- a/arch/powerpc/disassembler.cpp
+++ b/arch/powerpc/disassembler.cpp
@@ -1,7 +1,6 @@
 
 
 #include <string>
-#include <vector>
 
 #include "binaryninjaapi.h"
 
@@ -98,14 +97,14 @@ bool PushOperandTokens(string& result, const Operand* op)
 
 		case PPC_OP_SIMM:
 			if (op->simm < 0 && op->simm > -0x10000)
-				snprintf(buf, sizeof(buf), "-0x%llx", -op->simm);
+				snprintf(buf, sizeof(buf), "-0x%" PRIx64, -op->simm);
 			else
-				snprintf(buf, sizeof(buf), "0x%llx", op->simm);
+				snprintf(buf, sizeof(buf), "0x%" PRIx64, op->simm);
 			result += buf;
 			break;
 
 		case PPC_OP_LABEL:
-			snprintf(buf, sizeof(buf), "0x%llx", op->label);
+			snprintf(buf, sizeof(buf), "0x%" PRIx64, op->label);
 			result += buf;
 			break;