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authorMark Rowe <mark@vector35.com>2026-06-03 21:25:55 -0700
committerMark Rowe <mark@vector35.com>2026-06-04 14:31:09 -0700
commitd592ed6dafbb134553bf3a0b8ee70ff7f2049aba (patch)
tree1bfe7e335e5b4e21371cde4bf8858c6439bc3f18 /docs
parent9987102015875991813200116558306851763009 (diff)
Add bswap, popcnt, clz, ctz, cls, and rbit instructions
Diffstat (limited to 'docs')
-rw-r--r--docs/dev/bnil-hlil.md6
-rw-r--r--docs/dev/bnil-llil.md6
-rw-r--r--docs/dev/bnil-mlil.md6
3 files changed, 18 insertions, 0 deletions
diff --git a/docs/dev/bnil-hlil.md b/docs/dev/bnil-hlil.md
index 03447eab..1b2754e1 100644
--- a/docs/dev/bnil-hlil.md
+++ b/docs/dev/bnil-hlil.md
@@ -111,6 +111,12 @@ There are a number of properties that can be queried on the [`HighLevelILInstruc
* `HLIL_MODS_DP` - Signed double-precision modulus of `left` expression by the `right` expression
* `HLIL_NEG` - Sign inversion of `src` expression
* `HLIL_NOT` - Bitwise inversion of `src` expression
+* `HLIL_BSWAP` - Reverse the byte order of `src` expression
+* `HLIL_POPCNT` - Population count (number of set bits) of `src` expression
+* `HLIL_CLZ` - Count leading zero bits of `src` expression; the result is `8 * size` when `src` is zero
+* `HLIL_CTZ` - Count trailing zero bits of `src` expression; the result is `8 * size` when `src` is zero
+* `HLIL_RBIT` - Reverse the bit order of `src` expression
+* `HLIL_CLS` - Count leading sign bits of `src` expression (the number of bits below the sign bit that match it)
* `HLIL_FADD` - IEEE754 floating point addition of `left` expression with `right` expression
* `HLIL_FSUB` - IEEE754 floating point subtraction of `left` expression with `right` expression
* `HLIL_FMUL` - IEEE754 floating point multiplication of `left` expression with `right` expression
diff --git a/docs/dev/bnil-llil.md b/docs/dev/bnil-llil.md
index 5509151e..b3a4f906 100644
--- a/docs/dev/bnil-llil.md
+++ b/docs/dev/bnil-llil.md
@@ -257,6 +257,12 @@ The double precision instruction multiply, divide, modulus instructions are part
* `LLIL_MODS_DP` - Signed modulus double precision
* `LLIL_NEG` - Sign negation
* `LLIL_NOT` - Bitwise complement
+* `LLIL_BSWAP` - Reverse the byte order of `src`
+* `LLIL_POPCNT` - Population count (number of set bits) of `src`
+* `LLIL_CLZ` - Count leading zero bits of `src`; the result is `8 * size` when `src` is zero
+* `LLIL_CTZ` - Count trailing zero bits of `src`; the result is `8 * size` when `src` is zero
+* `LLIL_RBIT` - Reverse the bit order of `src`
+* `LLIL_CLS` - Count leading sign bits of `src` (the number of bits below the sign bit that match it)
* `LLIL_TEST_BIT ` - Test if bit `right` in expression `left` is set
* `LLIL_BOOL_TO_INT ` - Converts a bool `src` to an integer
diff --git a/docs/dev/bnil-mlil.md b/docs/dev/bnil-mlil.md
index 51028131..8e796ec8 100644
--- a/docs/dev/bnil-mlil.md
+++ b/docs/dev/bnil-mlil.md
@@ -348,6 +348,12 @@ The parameter list can be accessed through the `params` property:
* `MLIL_MODS_DP` - Signed double-precision modulus of `left` expression by the `right` expression
* `MLIL_NEG` - Sign inversion of `src` expression
* `MLIL_NOT` - Bitwise inversion of `src` expression
+* `MLIL_BSWAP` - Reverse the byte order of `src` expression
+* `MLIL_POPCNT` - Population count (number of set bits) of `src` expression
+* `MLIL_CLZ` - Count leading zero bits of `src` expression; the result is `8 * size` when `src` is zero
+* `MLIL_CTZ` - Count trailing zero bits of `src` expression; the result is `8 * size` when `src` is zero
+* `MLIL_RBIT` - Reverse the bit order of `src` expression
+* `MLIL_CLS` - Count leading sign bits of `src` expression (the number of bits below the sign bit that match it)
* `MLIL_FADD` - IEEE754 floating point addition of `left` expression with `right` expression
* `MLIL_FSUB` - IEEE754 floating point subtraction of `left` expression with `right` expression
* `MLIL_FMUL` - IEEE754 floating point multiplication of `left` expression with `right` expression