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authorPeter LaFosse <peter@vector35.com>2021-06-24 09:19:08 -0400
committerPeter LaFosse <peter@vector35.com>2021-09-05 10:08:09 -0400
commitd37f7abfe4c1b23426b0fbdc85ae31788602ff28 (patch)
treeff106d8d52afc7cb4d85a1378a41e5c72a288c7d /python/architecture.py
parente0389d244e6211126267e060a9c61a1e75481b76 (diff)
Don't inherit from object anymore
Diffstat (limited to 'python/architecture.py')
-rw-r--r--python/architecture.py12
1 files changed, 6 insertions, 6 deletions
diff --git a/python/architecture.py b/python/architecture.py
index a6bac57b..3a37b5b6 100644
--- a/python/architecture.py
+++ b/python/architecture.py
@@ -63,7 +63,7 @@ IntrinsicType = Union[IntrinsicName, 'lowlevelil.ILIntrinsic', IntrinsicIndex]
@dataclass(frozen=False)
-class RegisterInfo(object):
+class RegisterInfo:
full_width_reg:RegisterName
offset:int
size:int = 0
@@ -81,7 +81,7 @@ class RegisterInfo(object):
@dataclass(frozen=False)
-class RegisterStackInfo(object):
+class RegisterStackInfo:
storage_regs:List[RegisterName]
top_relative_regs:List[RegisterName]
stack_top_reg:RegisterName
@@ -92,7 +92,7 @@ class RegisterStackInfo(object):
@dataclass(frozen=True)
-class IntrinsicInput(object):
+class IntrinsicInput:
type:'types.Type'
name:str = ""
@@ -103,7 +103,7 @@ class IntrinsicInput(object):
@dataclass(frozen=True)
-class IntrinsicInfo(object):
+class IntrinsicInfo:
inputs:List[IntrinsicInput]
outputs:List['types.Type']
index:Optional[int] = None
@@ -113,7 +113,7 @@ class IntrinsicInfo(object):
@dataclass(frozen=True)
-class InstructionBranch(object):
+class InstructionBranch:
type:BranchType
target:int
arch:'Architecture'
@@ -125,7 +125,7 @@ class InstructionBranch(object):
@dataclass(frozen=False)
-class InstructionInfo(object):
+class InstructionInfo:
length:int = 0
arch_transition_by_target_addr:bool = False
branch_delay:bool = False