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| author | Pete Dietl <petedietl@gmail.com> | 2024-02-18 13:58:38 -0800 |
|---|---|---|
| committer | Rusty Wagner <rusty.wagner@gmail.com> | 2024-03-08 17:49:09 -0500 |
| commit | a542d0c9cd33fed5919c3cd9d598bb8d1a300ae8 (patch) | |
| tree | 93019642e1d3bd4abde648b09e8c3ba40c4eaedd /python/mainthread.py | |
| parent | b25a2b9fadddd07cdd85d69264d7be9de16b2537 (diff) | |
Fix RISC-V CSRRW, CSRRS, and CSRRC instr disass
Make the CSR instructions show the CSR 12-bit immediate
operand as an unsigned integer.
This is a special case of the I-instruction format, where
it is same except that the 12-bit immediate is treated as
unsigned rather than signed.
Diffstat (limited to 'python/mainthread.py')
0 files changed, 0 insertions, 0 deletions