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| author | Rusty Wagner <rusty@vector35.com> | 2018-02-09 17:17:53 -0500 |
|---|---|---|
| committer | Rusty Wagner <rusty@vector35.com> | 2018-02-09 17:17:53 -0500 |
| commit | 79b5bdcf42f6abf1c8b2c4bda4c30b41319c4aa5 (patch) | |
| tree | 7d20b2c03b44ccd65eff337a72fd700c075b42d5 /python/mediumlevelil.py | |
| parent | 83c9c2bceeb354dcf53e338e9411c6636f418123 (diff) | |
Add instructions for tracking freed register stack slots
Diffstat (limited to 'python/mediumlevelil.py')
| -rw-r--r-- | python/mediumlevelil.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/python/mediumlevelil.py b/python/mediumlevelil.py index a842c3c4..caf19e8e 100644 --- a/python/mediumlevelil.py +++ b/python/mediumlevelil.py @@ -152,6 +152,8 @@ class MediumLevelILInstruction(object): MediumLevelILOperation.MLIL_TRAP: [("vector", "int")], MediumLevelILOperation.MLIL_INTRINSIC: [("output", "var_list"), ("intrinsic", "intrinsic"), ("params", "expr_list")], MediumLevelILOperation.MLIL_INTRINSIC_SSA: [("output", "var_ssa_list"), ("intrinsic", "intrinsic"), ("params", "expr_list")], + MediumLevelILOperation.MLIL_FREE_VAR_SLOT: [("dest", "var")], + MediumLevelILOperation.MLIL_FREE_VAR_SLOT_SSA: [("prev", "var_ssa_dest_and_src")], MediumLevelILOperation.MLIL_UNDEF: [], MediumLevelILOperation.MLIL_UNIMPL: [], MediumLevelILOperation.MLIL_UNIMPL_MEM: [("src", "expr")], |