diff options
| author | Rusty Wagner <rusty@vector35.com> | 2017-10-03 23:07:48 -0400 |
|---|---|---|
| committer | Rusty Wagner <rusty@vector35.com> | 2017-10-06 17:28:35 -0400 |
| commit | 95a7be141a07a20b8465981b01116fcafb6b5f41 (patch) | |
| tree | e64cf2b30fe37eedf67d8d6111f240295992b020 /python/mediumlevelil.py | |
| parent | 1c6f11277096534479c958b6d9fc5265d318ca2a (diff) | |
Adding support for register stacks in IL (for x87)
Diffstat (limited to 'python/mediumlevelil.py')
| -rw-r--r-- | python/mediumlevelil.py | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/python/mediumlevelil.py b/python/mediumlevelil.py index 05b558d2..144c7e0b 100644 --- a/python/mediumlevelil.py +++ b/python/mediumlevelil.py @@ -27,6 +27,7 @@ import function import basicblock import lowlevelil import types +import struct class SSAVariable(object): @@ -90,6 +91,7 @@ class MediumLevelILInstruction(object): MediumLevelILOperation.MLIL_ADDRESS_OF_FIELD: [("src", "var"), ("offset", "int")], MediumLevelILOperation.MLIL_CONST: [("constant", "int")], MediumLevelILOperation.MLIL_CONST_PTR: [("constant", "int")], + MediumLevelILOperation.MLIL_FLOAT_CONST: [("constant", "float")], MediumLevelILOperation.MLIL_IMPORT: [("constant", "int")], MediumLevelILOperation.MLIL_ADD: [("left", "expr"), ("right", "expr")], MediumLevelILOperation.MLIL_ADC: [("left", "expr"), ("right", "expr"), ("carry", "expr")], @@ -211,6 +213,13 @@ class MediumLevelILInstruction(object): name, operand_type = operand if operand_type == "int": value = instr.operands[i] + elif operand_type == "float": + if instr.size == 4: + value = struct.unpack("f", struct.pack("I", instr.operands[i] & 0xffffffff))[0] + elif instr.size == 8: + value = struct.unpack("d", struct.pack("Q", instr.operands[i]))[0] + else: + value = instr.operands[i] elif operand_type == "expr": value = MediumLevelILInstruction(func, instr.operands[i]) elif operand_type == "var": |