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| author | Rusty Wagner <rusty@vector35.com> | 2018-02-09 17:17:53 -0500 |
|---|---|---|
| committer | Peter LaFosse <peter@vector35.com> | 2018-03-23 17:10:06 -0400 |
| commit | a77b7ddc28706da689727a82f5a67ae1e9c61693 (patch) | |
| tree | 9f1a0fd2b15d5d8bcc5d02a90449f0a7a3d6abc3 /python/mediumlevelil.py | |
| parent | eb2a6a07df889537e25c647d9b3c71c30c836961 (diff) | |
Add instructions for tracking freed register stack slots
Diffstat (limited to 'python/mediumlevelil.py')
| -rw-r--r-- | python/mediumlevelil.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/python/mediumlevelil.py b/python/mediumlevelil.py index a842c3c4..caf19e8e 100644 --- a/python/mediumlevelil.py +++ b/python/mediumlevelil.py @@ -152,6 +152,8 @@ class MediumLevelILInstruction(object): MediumLevelILOperation.MLIL_TRAP: [("vector", "int")], MediumLevelILOperation.MLIL_INTRINSIC: [("output", "var_list"), ("intrinsic", "intrinsic"), ("params", "expr_list")], MediumLevelILOperation.MLIL_INTRINSIC_SSA: [("output", "var_ssa_list"), ("intrinsic", "intrinsic"), ("params", "expr_list")], + MediumLevelILOperation.MLIL_FREE_VAR_SLOT: [("dest", "var")], + MediumLevelILOperation.MLIL_FREE_VAR_SLOT_SSA: [("prev", "var_ssa_dest_and_src")], MediumLevelILOperation.MLIL_UNDEF: [], MediumLevelILOperation.MLIL_UNIMPL: [], MediumLevelILOperation.MLIL_UNIMPL_MEM: [("src", "expr")], |