diff options
| author | Peter LaFosse <peter@vector35.com> | 2022-02-15 20:56:39 -0500 |
|---|---|---|
| committer | Peter LaFosse <peter@vector35.com> | 2022-02-17 08:43:04 -0500 |
| commit | 159bda74c5b5b8e7c1898cbe707d90e01cb09101 (patch) | |
| tree | d479ad62fde41e4859392b1e984539eec91938ec /python | |
| parent | 3283cc159af2c04b93679cc1f78fd6b8f39e372a (diff) | |
Add some additional type hints to architecture.py and lowlevelil.py
Diffstat (limited to 'python')
| -rw-r--r-- | python/architecture.py | 10 | ||||
| -rw-r--r-- | python/lowlevelil.py | 16 |
2 files changed, 13 insertions, 13 deletions
diff --git a/python/architecture.py b/python/architecture.py index ff598a35..65f1f455 100644 --- a/python/architecture.py +++ b/python/architecture.py @@ -202,7 +202,7 @@ class Architecture(metaclass=_ArchitectureMetaClass): instr_alignment = 1 max_instr_length = 16 opcode_display_length = 8 - regs = {} + regs: Dict[RegisterName, RegisterInfo] = {} stack_pointer = None link_reg = None global_regs = [] @@ -217,7 +217,7 @@ class Architecture(metaclass=_ArchitectureMetaClass): flag_conditions_for_semantic_flag_group = {} flags_written_by_flag_write_type = {} semantic_class_for_flag_write_type = {} - reg_stacks = {} + reg_stacks: Dict[RegisterStackName, RegisterStackInfo] = {} intrinsics = {} next_address = 0 @@ -1376,7 +1376,7 @@ class Architecture(metaclass=_ArchitectureMetaClass): """ raise NotImplementedError - def get_instruction_text(self, data: bytes, addr: int) -> Tuple[List['function.InstructionTextToken'], int]: + def get_instruction_text(self, data: bytes, addr: int) -> Optional[Tuple[List['function.InstructionTextToken'], int]]: """ ``get_instruction_text`` returns a tuple containing a list of decoded InstructionTextToken objects and the bytes used at the given virtual address ``addr`` with data ``data``. @@ -1398,7 +1398,7 @@ class Architecture(metaclass=_ArchitectureMetaClass): self.get_instruction_low_level_il(data, addr, il) return il[0] - def get_instruction_low_level_il(self, data: bytes, addr: int, il: 'lowlevelil.LowLevelILFunction') -> int: + def get_instruction_low_level_il(self, data: bytes, addr: int, il: lowlevelil.LowLevelILFunction) -> Optional[int]: """ ``get_instruction_low_level_il`` appends lowlevelil.ExpressionIndex objects to ``il`` for the instruction at the given virtual address ``addr`` with data ``data``. @@ -2332,7 +2332,7 @@ class CoreArchitecture(Architecture): result.add_branch(BranchType(info.branchType[i]), target, arch) return result - def get_instruction_text(self, data: bytes, addr: int) -> Tuple[List['function.InstructionTextToken'], int]: + def get_instruction_text(self, data: bytes, addr: int) -> Optional[Tuple[List['function.InstructionTextToken'], int]]: """ ``get_instruction_text`` returns a list of InstructionTextToken objects for the instruction at the given virtual address ``addr`` with data ``data``. diff --git a/python/lowlevelil.py b/python/lowlevelil.py index 2849c2bf..067c937f 100644 --- a/python/lowlevelil.py +++ b/python/lowlevelil.py @@ -59,7 +59,7 @@ LowLevelILOperandType = Union['LowLevelILOperationAndSize', 'ILRegister', 'ILFla class LowLevelILLabel: - def __init__(self, handle: core.BNLowLevelILLabel = None): + def __init__(self, handle: Optional[core.BNLowLevelILLabel] = None): if handle is None: self.handle = (core.BNLowLevelILLabel * 1)() core.BNLowLevelILInitLabel(self.handle) @@ -81,7 +81,7 @@ class ILRegister: def __int__(self): return self.index - def __eq__(self, other): + def __eq__(self, other: Union[str, 'ILRegister']): if isinstance(other, str) and other in self.arch.regs: index = self.arch.regs[architecture.RegisterName(other)].index assert index is not None @@ -2699,11 +2699,11 @@ class LowLevelILFunction: def __hash__(self): return hash(ctypes.addressof(self.handle.contents)) - def __getitem__(self, i): + def __getitem__(self, i:ExpressionIndex) -> LowLevelILInstruction: if isinstance(i, slice) or isinstance(i, tuple): raise IndexError("expected integer instruction index") if i < -len(self) or i >= len(self): - raise IndexError("index out of range") + raise IndexError(f"index {i} out of range (-{len(self)}, {len(self)})") if i < 0: i = len(self) + i return LowLevelILInstruction.create( @@ -3014,9 +3014,9 @@ class LowLevelILFunction: core.BNLowLevelILSetIndirectBranches(self.handle, branch_list, len(branches)) def expr( - self, operation, a: int = 0, b: int = 0, c: int = 0, d: int = 0, size: int = 0, + self, operation, a: ExpressionIndex = 0, b: ExpressionIndex = 0, c: ExpressionIndex = 0, d: ExpressionIndex = 0, size: int = 0, flags: Union['architecture.FlagWriteTypeName', 'architecture.FlagType', 'architecture.FlagIndex'] = None - ): + ) -> ExpressionIndex: _flags = architecture.FlagIndex(0) if isinstance(operation, str): operation = LowLevelILOperation[operation] @@ -4737,8 +4737,8 @@ class LowLevelILBasicBlock(basicblock.BasicBlock): return self._il_function -def LLIL_TEMP(n: Union[ILRegister, int]) -> int: - return int(n) | 0x80000000 +def LLIL_TEMP(n: Union[ILRegister, int]) -> 'architecture.RegisterIndex': + return architecture.RegisterIndex(int(n) | 0x80000000) def LLIL_REG_IS_TEMP(n: Union[ILRegister, int]) -> bool: |
