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| author | Glenn Smith <glenn@vector35.com> | 2022-02-28 16:13:51 -0500 |
|---|---|---|
| committer | Glenn Smith <glenn@vector35.com> | 2022-02-28 16:13:51 -0500 |
| commit | a27c6ceeae96a525ba14d4e4f7504928c136ffbb (patch) | |
| tree | 69ea6bc6c6a2ba2c8ec2861d03944f1266589979 /python | |
| parent | 6ef005037faa53d82ea20413e2f6d0e5b58ae8eb (diff) | |
il.intrinsic(): Support ILRegister/ILFlag as well
Diffstat (limited to 'python')
| -rw-r--r-- | python/lowlevelil.py | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/python/lowlevelil.py b/python/lowlevelil.py index ea9e087f..eac78bd9 100644 --- a/python/lowlevelil.py +++ b/python/lowlevelil.py @@ -4063,7 +4063,7 @@ class LowLevelILFunction: return self.expr(LowLevelILOperation.LLIL_SYSCALL) def intrinsic( - self, outputs: List[Union['architecture.FlagIndex', 'architecture.RegisterIndex']], intrinsic: 'architecture.IntrinsicType', + self, outputs: List[Union['architecture.FlagIndex', 'architecture.RegisterIndex', 'ILRegister', 'ILFlag']], intrinsic: 'architecture.IntrinsicType', params: List[ExpressionIndex], flags: 'architecture.FlagType' = None ): """ @@ -4076,8 +4076,12 @@ class LowLevelILFunction: for output in outputs: if isinstance(output, architecture.FlagIndex): output_list.append((1 << 32) | int(output)) + elif isinstance(output, ILFlag): + output_list.append((1 << 32) | int(output.index)) + elif isinstance(output, ILRegister): + output_list.append(int(output.index)) else: - output_list.append(output) + output_list.append(int(output)) param_list = [] for param in params: param_list.append(param) |
