diff options
| author | Fabian Freyer <fabian.freyer@physik.tu-berlin.de> | 2022-04-05 03:42:59 +0200 |
|---|---|---|
| committer | Peter LaFosse <peter@vector35.com> | 2022-04-24 10:04:58 -0400 |
| commit | d5302fd05f40e606f93aeb4a0aa98cfc2029fa51 (patch) | |
| tree | 57431619f39823c6a3432fcc85471ee80f1e859c /python | |
| parent | a54d37aa45a915a1223476e58331a020ee5a3154 (diff) | |
Add commonil class for intrinsics
Diffstat (limited to 'python')
| -rw-r--r-- | python/commonil.py | 5 | ||||
| -rw-r--r-- | python/highlevelil.py | 2 | ||||
| -rw-r--r-- | python/lowlevelil.py | 2 | ||||
| -rw-r--r-- | python/mediumlevelil.py | 2 |
4 files changed, 8 insertions, 3 deletions
diff --git a/python/commonil.py b/python/commonil.py index 7517574d..b2ca71fb 100644 --- a/python/commonil.py +++ b/python/commonil.py @@ -184,3 +184,8 @@ class StackOperation(BaseILInstruction): @dataclass(frozen=True, repr=False, eq=False) class SetReg: pass + + +@dataclass(frozen=True, repr=False, eq=False) +class Intrinsic(BaseILInstruction): + pass diff --git a/python/highlevelil.py b/python/highlevelil.py index e2a53bb5..c35fdd12 100644 --- a/python/highlevelil.py +++ b/python/highlevelil.py @@ -1746,7 +1746,7 @@ class HighLevelILTrap(HighLevelILInstruction, Terminal): @dataclass(frozen=True, repr=False, eq=False) -class HighLevelILIntrinsic(HighLevelILInstruction): +class HighLevelILIntrinsic(HighLevelILInstruction, Intrinsic): @property def intrinsic(self) -> 'lowlevelil.ILIntrinsic': return self.get_intrinsic(0) diff --git a/python/lowlevelil.py b/python/lowlevelil.py index bf984b2d..cdcd1138 100644 --- a/python/lowlevelil.py +++ b/python/lowlevelil.py @@ -2210,7 +2210,7 @@ class LowLevelILIf(LowLevelILInstruction, ControlFlow): @dataclass(frozen=True, repr=False, eq=False) -class LowLevelILIntrinsic(LowLevelILInstruction): +class LowLevelILIntrinsic(LowLevelILInstruction, Intrinsic): @property def output(self) -> List[Union[ILFlag, ILRegister]]: return self._get_reg_or_flag_list(0) diff --git a/python/mediumlevelil.py b/python/mediumlevelil.py index 89e50f15..7a8a92d4 100644 --- a/python/mediumlevelil.py +++ b/python/mediumlevelil.py @@ -1840,7 +1840,7 @@ class MediumLevelILSyscallUntyped(MediumLevelILCallBase, Syscall): @dataclass(frozen=True, repr=False, eq=False) -class MediumLevelILIntrinsic(MediumLevelILInstruction): +class MediumLevelILIntrinsic(MediumLevelILInstruction, Intrinsic): @property def output(self) -> List[variable.Variable]: return self._get_var_list(0, 1) |