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authorMason Reed <mason@vector35.com>2025-04-30 17:38:40 -0400
committerMason Reed <35282038+emesare@users.noreply.github.com>2025-05-12 17:45:24 -0400
commitc3fdda9727f5507818e3f55576ad32215a22b0f9 (patch)
treed522025055eb7253c7f2cb94732402aacf2afbfc /rust/tests
parentc3f344a38ca4b027b4e69b0f82d3184622d6da79 (diff)
[Rust] Remove Architecture trait bound on LLIL related structures
Diffstat (limited to 'rust/tests')
-rw-r--r--rust/tests/low_level_il.rs14
1 files changed, 7 insertions, 7 deletions
diff --git a/rust/tests/low_level_il.rs b/rust/tests/low_level_il.rs
index b9d7d203..88d915dc 100644
--- a/rust/tests/low_level_il.rs
+++ b/rust/tests/low_level_il.rs
@@ -7,7 +7,7 @@ use binaryninja::low_level_il::expression::{
use binaryninja::low_level_il::instruction::{
InstructionHandler, LowLevelILInstructionKind, LowLevelInstructionIndex,
};
-use binaryninja::low_level_il::{LowLevelILRegister, VisitorAction};
+use binaryninja::low_level_il::{LowLevelILRegisterKind, VisitorAction};
use std::path::PathBuf;
#[test]
@@ -34,7 +34,7 @@ fn test_llil_info() {
LowLevelILInstructionKind::SetReg(op) => {
assert_eq!(op.size(), 4);
match op.dest_reg() {
- LowLevelILRegister::ArchReg(reg) => assert_eq!(reg.name(), "edi"),
+ LowLevelILRegisterKind::Arch(reg) => assert_eq!(reg.name(), "edi"),
_ => panic!("Expected Register::ArchReg"),
}
assert_eq!(op.source_expr().index, LowLevelExpressionIndex(0));
@@ -55,7 +55,7 @@ fn test_llil_info() {
LowLevelILExpressionKind::Reg(op) => {
assert_eq!(op.size(), 4);
match op.source_reg() {
- LowLevelILRegister::ArchReg(reg) => assert_eq!(reg.name(), "ebp"),
+ LowLevelILRegisterKind::Arch(reg) => assert_eq!(reg.name(), "ebp"),
_ => panic!("Expected Register::ArchReg"),
}
}
@@ -73,7 +73,7 @@ fn test_llil_info() {
LowLevelILInstructionKind::SetReg(op) => {
assert_eq!(op.size(), 4);
match op.dest_reg() {
- LowLevelILRegister::ArchReg(reg) => assert_eq!(reg.name(), "ebp"),
+ LowLevelILRegisterKind::Arch(reg) => assert_eq!(reg.name(), "ebp"),
_ => panic!("Expected Register::ArchReg"),
}
assert_eq!(op.source_expr().index, LowLevelExpressionIndex(4));
@@ -89,7 +89,7 @@ fn test_llil_info() {
LowLevelILInstructionKind::SetReg(op) => {
assert_eq!(op.size(), 4);
match op.dest_reg() {
- LowLevelILRegister::ArchReg(reg) => assert_eq!(reg.name(), "eax"),
+ LowLevelILRegisterKind::Arch(reg) => assert_eq!(reg.name(), "eax"),
_ => panic!("Expected Register::ArchReg"),
}
assert_eq!(op.source_expr().index, LowLevelExpressionIndex(9));
@@ -128,7 +128,7 @@ fn test_llil_info() {
LowLevelILInstructionKind::SetReg(op) => {
assert_eq!(op.size(), 4);
match op.dest_reg() {
- LowLevelILRegister::ArchReg(reg) => assert_eq!(reg.name(), "esp"),
+ LowLevelILRegisterKind::Arch(reg) => assert_eq!(reg.name(), "esp"),
_ => panic!("Expected Register::ArchReg"),
}
assert_eq!(op.source_expr().index, LowLevelExpressionIndex(17));
@@ -144,7 +144,7 @@ fn test_llil_info() {
LowLevelILInstructionKind::SetReg(op) => {
assert_eq!(op.size(), 4);
match op.dest_reg() {
- LowLevelILRegister::ArchReg(reg) => assert_eq!(reg.name(), "ebp"),
+ LowLevelILRegisterKind::Arch(reg) => assert_eq!(reg.name(), "ebp"),
_ => panic!("Expected Register::ArchReg"),
}
assert_eq!(op.source_expr().index, LowLevelExpressionIndex(19));