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| author | Mark Rowe <mark@vector35.com> | 2025-09-18 11:46:39 -0700 |
|---|---|---|
| committer | Mark Rowe <mark@vector35.com> | 2025-09-25 08:41:48 -0700 |
| commit | 6e1306923c60b3d6c1cefb1fcc240f1a064d6f20 (patch) | |
| tree | 57fb65f74fecfa95dd394ecc5b664512d8f87609 /typeparser.cpp | |
| parent | 0deeb4a61749737b98f7946ec88b693068180e28 (diff) | |
[AArch64] Update disassembler based on 2025-06 ARM ISA data
Alongside this I also added support for decoding:
* LDR / STR (table)
* PMULLB / PMULLT
* ABS / CNT / CTZ
* SMIN / SMAX / UMIN / UMAX
* RPRFM
* PSEL
Note that while these instructions will now be disassembled, they are
not yet lifted to LLIL.
Additionally, I fixed a number of errors in the decoding of some less
commonly occurring instructions.
Diffstat (limited to 'typeparser.cpp')
0 files changed, 0 insertions, 0 deletions