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-rw-r--r--arch/riscv/src/lib.rs35
1 files changed, 17 insertions, 18 deletions
diff --git a/arch/riscv/src/lib.rs b/arch/riscv/src/lib.rs
index dbc4ed78..645bb45a 100644
--- a/arch/riscv/src/lib.rs
+++ b/arch/riscv/src/lib.rs
@@ -34,7 +34,6 @@ use binaryninja::{
CoreRelocationHandler, CustomRelocationHandlerHandle, RelocationHandler, RelocationInfo,
RelocationType,
},
- string::BnString,
symbol::{Symbol, SymbolType},
types::{max_confidence, min_confidence, Conf, NameAndType, Type},
};
@@ -969,20 +968,20 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo
_ => (),
}
- res.push(InstructionTextToken::new(BnString::new(mnem), Instruction));
+ res.push(InstructionTextToken::new(&mnem, Instruction));
for (i, oper) in operands.iter().enumerate() {
if i == 0 {
res.push(InstructionTextToken::new(
- BnString::new(format!("{:1$}", " ", pad_len)),
+ &format!("{:1$}", " ", pad_len),
Text,
));
} else {
res.push(InstructionTextToken::new(
- BnString::new(","),
+ ",",
OperandSeparator,
));
- res.push(InstructionTextToken::new(BnString::new(" "), Text));
+ res.push(InstructionTextToken::new(" ", Text));
}
match *oper {
@@ -990,7 +989,7 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo
let reg = self::Register::from(r);
res.push(InstructionTextToken::new(
- BnString::new(&reg.name()),
+ &reg.name(),
Register,
));
}
@@ -998,7 +997,7 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo
let reg = self::Register::from(r);
res.push(InstructionTextToken::new(
- BnString::new(&reg.name()),
+ &reg.name(),
Register,
));
}
@@ -1015,16 +1014,16 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo
let target = addr.wrapping_add(i as i64 as u64);
res.push(InstructionTextToken::new(
- BnString::new(format!("0x{:x}", target)),
+ &format!("0x{:x}", target),
CodeRelativeAddress(target),
));
}
_ => {
res.push(InstructionTextToken::new(
- BnString::new(match i {
+ &match i {
-0x8_0000..=-1 => format!("-0x{:x}", -i),
_ => format!("0x{:x}", i),
- }),
+ },
Integer(i as u64),
));
}
@@ -1034,31 +1033,31 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo
let reg = self::Register::from(b);
res.push(InstructionTextToken::new(
- BnString::new(""),
+ "",
BeginMemoryOperand,
));
res.push(InstructionTextToken::new(
- BnString::new(if i < 0 {
+ &if i < 0 {
format!("-0x{:x}", -i)
} else {
format!("0x{:x}", i)
- }),
+ },
Integer(i as u64),
));
- res.push(InstructionTextToken::new(BnString::new("("), Brace));
+ res.push(InstructionTextToken::new("(", Brace));
res.push(InstructionTextToken::new(
- BnString::new(&reg.name()),
+ &reg.name(),
Register,
));
- res.push(InstructionTextToken::new(BnString::new(")"), Brace));
+ res.push(InstructionTextToken::new(")", Brace));
res.push(InstructionTextToken::new(
- BnString::new(""),
+ "",
EndMemoryOperand,
));
}
Operand::RM(r) => {
- res.push(InstructionTextToken::new(BnString::new(r.name()), Register));
+ res.push(InstructionTextToken::new(r.name(), Register));
}
}
}