diff options
| -rw-r--r-- | arch/msp430/src/architecture.rs | 1 | ||||
| -rw-r--r-- | arch/riscv/disasm/src/lib.rs | 5 | ||||
| -rw-r--r-- | arch/riscv/src/lib.rs | 41 | ||||
| -rw-r--r-- | rust/src/architecture.rs | 3 | ||||
| -rw-r--r-- | rust/src/low_level_il/expression.rs | 10 | ||||
| -rw-r--r-- | rust/src/low_level_il/function.rs | 6 |
6 files changed, 35 insertions, 31 deletions
diff --git a/arch/msp430/src/architecture.rs b/arch/msp430/src/architecture.rs index 938e9ec5..ccc5ce80 100644 --- a/arch/msp430/src/architecture.rs +++ b/arch/msp430/src/architecture.rs @@ -25,6 +25,7 @@ use log::error; const MIN_MNEMONIC: usize = 9; +#[derive(Debug)] pub struct Msp430 { handle: CoreArchitecture, custom_handle: CustomArchitectureHandle<Msp430>, diff --git a/arch/riscv/disasm/src/lib.rs b/arch/riscv/disasm/src/lib.rs index a25516a6..959952ee 100644 --- a/arch/riscv/disasm/src/lib.rs +++ b/arch/riscv/disasm/src/lib.rs @@ -291,7 +291,7 @@ impl FloatRegType for () {} impl FloatRegType for f32 {} impl FloatRegType for f64 {} -pub trait RegFile: Debug + Sized + Copy + Clone { +pub trait RegFile: Debug + Sized + Copy + Clone + Send + Sync + 'static { type Int: IntRegType; type Float: FloatRegType; @@ -2331,7 +2331,7 @@ impl StandardExtension for ExtensionSupported { } } -pub trait RiscVDisassembler: Debug + Sized + Copy + Clone { +pub trait RiscVDisassembler: 'static + Debug + Sized + Copy + Clone + Send + Sync { type RegFile: RegFile; type MulDivExtension: StandardExtension; type AtomicExtension: StandardExtension; @@ -3175,6 +3175,7 @@ pub trait RiscVDisassembler: Debug + Sized + Copy + Clone { #[derive(Copy, Clone, Debug)] pub struct RiscVIMACDisassembler<RF: RegFile>(PhantomData<RF>); + impl<RF: RegFile> RiscVDisassembler for RiscVIMACDisassembler<RF> { type RegFile = RF; type MulDivExtension = ExtensionSupported; diff --git a/arch/riscv/src/lib.rs b/arch/riscv/src/lib.rs index 1abce973..6df34fd7 100644 --- a/arch/riscv/src/lib.rs +++ b/arch/riscv/src/lib.rs @@ -88,18 +88,18 @@ enum Intrinsic { } #[derive(Copy, Clone)] -struct Register<D: 'static + RiscVDisassembler> { +struct Register<D: RiscVDisassembler> { id: RegisterId, _dis: PhantomData<D>, } #[derive(Debug, Copy, Clone)] -struct RiscVIntrinsic<D: 'static + RiscVDisassembler> { +struct RiscVIntrinsic<D: RiscVDisassembler> { id: Intrinsic, _dis: PhantomData<D>, } -impl<D: 'static + RiscVDisassembler> Register<D> { +impl<D: RiscVDisassembler> Register<D> { fn new(id: RegisterId) -> Self { Self { id, @@ -118,7 +118,7 @@ impl<D: 'static + RiscVDisassembler> Register<D> { } } -impl<D: 'static + RiscVDisassembler> From<riscv_dis::IntReg<D>> for Register<D> { +impl<D: RiscVDisassembler> From<riscv_dis::IntReg<D>> for Register<D> { fn from(reg: riscv_dis::IntReg<D>) -> Self { Self { id: RegisterId(reg.id()), @@ -127,7 +127,7 @@ impl<D: 'static + RiscVDisassembler> From<riscv_dis::IntReg<D>> for Register<D> } } -impl<D: 'static + RiscVDisassembler> From<FloatReg<D>> for Register<D> { +impl<D: RiscVDisassembler> From<FloatReg<D>> for Register<D> { fn from(reg: FloatReg<D>) -> Self { let int_reg_count = <D::RegFile as RegFile>::int_reg_count(); @@ -138,13 +138,13 @@ impl<D: 'static + RiscVDisassembler> From<FloatReg<D>> for Register<D> { } } -impl<D: 'static + RiscVDisassembler> From<Register<D>> for LowLevelILRegister<Register<D>> { +impl<D: RiscVDisassembler> From<Register<D>> for LowLevelILRegister<Register<D>> { fn from(reg: Register<D>) -> Self { LowLevelILRegister::ArchReg(reg) } } -impl<D: 'static + RiscVDisassembler> RegisterInfo for Register<D> { +impl<D: RiscVDisassembler> RegisterInfo for Register<D> { type RegType = Self; fn parent(&self) -> Option<Self> { @@ -166,7 +166,7 @@ impl<D: 'static + RiscVDisassembler> RegisterInfo for Register<D> { } } -impl<D: 'static + RiscVDisassembler> architecture::Register for Register<D> { +impl<D: RiscVDisassembler> architecture::Register for Register<D> { type InfoType = Self; fn name(&self) -> Cow<str> { @@ -204,7 +204,7 @@ impl<D: 'static + RiscVDisassembler> architecture::Register for Register<D> { } } -impl<'a, D: 'static + RiscVDisassembler + Send + Sync> LiftableLowLevelIL<'a, RiscVArch<D>> +impl<'a, D: RiscVDisassembler> LiftableLowLevelIL<'a, RiscVArch<D>> for Register<D> { type Result = ValueExpr; @@ -221,7 +221,7 @@ impl<'a, D: 'static + RiscVDisassembler + Send + Sync> LiftableLowLevelIL<'a, Ri } } -impl<'a, D: 'static + RiscVDisassembler + Send + Sync> LiftableLowLevelILWithSize<'a, RiscVArch<D>> +impl<'a, D: RiscVDisassembler> LiftableLowLevelILWithSize<'a, RiscVArch<D>> for Register<D> { fn lift_with_size( @@ -257,21 +257,21 @@ impl<'a, D: 'static + RiscVDisassembler + Send + Sync> LiftableLowLevelILWithSiz } } -impl<D: 'static + RiscVDisassembler> Hash for Register<D> { +impl<D: RiscVDisassembler> Hash for Register<D> { fn hash<H: std::hash::Hasher>(&self, state: &mut H) { self.id.hash(state); } } -impl<D: 'static + RiscVDisassembler> PartialEq for Register<D> { +impl<D: RiscVDisassembler> PartialEq for Register<D> { fn eq(&self, other: &Self) -> bool { self.id == other.id } } -impl<D: 'static + RiscVDisassembler> Eq for Register<D> {} +impl<D: RiscVDisassembler> Eq for Register<D> {} -impl<D: 'static + RiscVDisassembler> fmt::Debug for Register<D> { +impl<D: RiscVDisassembler> fmt::Debug for Register<D> { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.write_str(self.name().as_ref()) } @@ -636,13 +636,14 @@ impl<D: RiscVDisassembler> architecture::Intrinsic for RiscVIntrinsic<D> { } } -struct RiscVArch<D: 'static + RiscVDisassembler + Send + Sync> { +#[derive(Debug)] +struct RiscVArch<D: RiscVDisassembler> { handle: CoreArchitecture, custom_handle: CustomArchitectureHandle<RiscVArch<D>>, _dis: PhantomData<D>, } -impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture for RiscVArch<D> { +impl<D: RiscVDisassembler> Architecture for RiscVArch<D> { type Handle = CustomArchitectureHandle<Self>; type RegisterInfo = Register<D>; @@ -2652,7 +2653,7 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> RelocationHandler } } -impl<D: 'static + RiscVDisassembler + Send + Sync> AsRef<CoreRelocationHandler> +impl<D: RiscVDisassembler> AsRef<CoreRelocationHandler> for RiscVELFRelocationHandler<D> { fn as_ref(&self) -> &CoreRelocationHandler { @@ -2660,17 +2661,17 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> AsRef<CoreRelocationHandler> } } -struct RiscVCC<D: 'static + RiscVDisassembler + Send + Sync> { +struct RiscVCC<D: RiscVDisassembler> { _dis: PhantomData<D>, } -impl<D: 'static + RiscVDisassembler + Send + Sync> RiscVCC<D> { +impl<D: RiscVDisassembler> RiscVCC<D> { fn new() -> Self { RiscVCC { _dis: PhantomData } } } -impl<D: 'static + RiscVDisassembler + Send + Sync> CallingConvention for RiscVCC<D> { +impl<D: RiscVDisassembler> CallingConvention for RiscVCC<D> { fn caller_saved_registers(&self) -> Vec<RegisterId> { let mut regs = Vec::with_capacity(36); let int_reg_count = <D::RegFile as RegFile>::int_reg_count(); diff --git a/rust/src/architecture.rs b/rust/src/architecture.rs index 3573f1fb..7ad10dfb 100644 --- a/rust/src/architecture.rs +++ b/rust/src/architecture.rs @@ -418,7 +418,7 @@ pub trait Intrinsic: Debug + Sized + Clone + Copy { fn outputs(&self) -> Vec<Conf<Ref<Type>>>; } -pub trait Architecture: 'static + Sized + AsRef<CoreArchitecture> { +pub trait Architecture: 'static + Sized + AsRef<CoreArchitecture> + Debug { type Handle: Borrow<Self> + Clone; type RegisterInfo: RegisterInfo<RegType = Self::Register>; @@ -3234,6 +3234,7 @@ where } } +#[derive(Debug)] pub struct CustomArchitectureHandle<A> where A: 'static + Architecture<Handle = CustomArchitectureHandle<A>> + Send + Sync, diff --git a/rust/src/low_level_il/expression.rs b/rust/src/low_level_il/expression.rs index fd403c76..f8fcf9f7 100644 --- a/rust/src/low_level_il/expression.rs +++ b/rust/src/low_level_il/expression.rs @@ -21,7 +21,7 @@ use super::VisitorAction; use super::*; use crate::architecture::Architecture; use std::fmt; -use std::fmt::{Display, Formatter}; +use std::fmt::{Debug, Display, Formatter}; use std::marker::PhantomData; /// Used as a marker for an [`LowLevelILExpression`] that **can** produce a value. @@ -32,7 +32,7 @@ pub struct ValueExpr; #[derive(Copy, Clone, Debug)] pub struct VoidExpr; -pub trait ExpressionResultType: 'static {} +pub trait ExpressionResultType: 'static + Debug {} impl ExpressionResultType for ValueExpr {} impl ExpressionResultType for VoidExpr {} @@ -102,9 +102,9 @@ where R: ExpressionResultType, { fn fmt(&self, f: &mut Formatter) -> fmt::Result { - f.debug_struct("Expression") - .field("index", &self.index) - .finish() + let op = unsafe { BNGetLowLevelILByIndex(self.function.handle, self.index.0) }; + let t = unsafe { LowLevelILExpressionKind::from_raw(self.function, op) }; + t.fmt(f) } } diff --git a/rust/src/low_level_il/function.rs b/rust/src/low_level_il/function.rs index 85037632..301c3f09 100644 --- a/rust/src/low_level_il/function.rs +++ b/rust/src/low_level_il/function.rs @@ -35,7 +35,7 @@ pub struct Mutable; #[derive(Copy, Clone, Debug)] pub struct Finalized; -pub trait FunctionMutability: 'static {} +pub trait FunctionMutability: 'static + Debug {} impl FunctionMutability for Mutable {} impl FunctionMutability for Finalized {} @@ -44,7 +44,7 @@ pub struct LiftedNonSSA; #[derive(Copy, Clone, Debug)] pub struct RegularNonSSA; -pub trait NonSSAVariant: 'static {} +pub trait NonSSAVariant: 'static + Debug {} impl NonSSAVariant for LiftedNonSSA {} impl NonSSAVariant for RegularNonSSA {} @@ -53,7 +53,7 @@ pub struct SSA; #[derive(Copy, Clone, Debug)] pub struct NonSSA<V: NonSSAVariant>(V); -pub trait FunctionForm: 'static {} +pub trait FunctionForm: 'static + Debug {} impl FunctionForm for SSA {} impl<V: NonSSAVariant> FunctionForm for NonSSA<V> {} |