1 files changed, 13 insertions, 16 deletions

diff --git a/arch/riscv/disasm/src/lib.rs b/arch/riscv/disasm/src/lib.rs
index ad612e7a..a25516a6 100644
--- a/arch/riscv/disasm/src/lib.rs
+++ b/arch/riscv/disasm/src/lib.rs
@@ -4,10 +4,9 @@
 // finish transition to from_instr32 from 'new'
 // make the various component structs smaller (8 bit IntReg/FloatReg etc.)
 
-extern crate byteorder;
-
 use std::borrow::Cow;
 use std::fmt;
+use std::fmt::Debug;
 use std::marker::PhantomData;
 use std::mem;
 
@@ -292,7 +291,7 @@ impl FloatRegType for () {}
 impl FloatRegType for f32 {}
 impl FloatRegType for f64 {}
 
-pub trait RegFile: Sized + Copy + Clone {
+pub trait RegFile: Debug + Sized + Copy + Clone {
     type Int: IntRegType;
     type Float: FloatRegType;
 
@@ -345,21 +344,21 @@ pub enum Operand<D: RiscVDisassembler> {
 
 impl<D: RiscVDisassembler> fmt::Display for Operand<D> {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        match self {
-            &Operand::R(ref r) => write!(f, "x{}", r.id()),
-            &Operand::F(ref r) => write!(f, "f{}", r.id()),
-            &Operand::I(i) => match i {
+        match *self {
+            Operand::R(r) => write!(f, "x{}", r.id()),
+            Operand::F(r) => write!(f, "f{}", r.id()),
+            Operand::I(i) => match i {
                 -0x80000..=-1 => write!(f, "-{:x}", -i),
                 _ => write!(f, "{:x}", i),
             },
-            &Operand::M(i, ref r) => {
+            Operand::M(i, r) => {
                 if i < 0 {
                     write!(f, "-{:x}(x{})", -i, r.id())
                 } else {
                     write!(f, "{:x}(x{})", i, r.id())
                 }
             }
-            &Operand::RM(ref r) => write!(f, "{}", r.name()),
+            Operand::RM(r) => write!(f, "{}", r.name()),
         }
     }
 }
@@ -1777,7 +1776,7 @@ pub enum Instr<D: RiscVDisassembler> {
 
 impl<D: RiscVDisassembler> Instr<D> {
     pub fn mnem(&self) -> Mnem<D> {
-        Mnem(&self)
+        Mnem(self)
     }
 
     pub fn operands(&self) -> Vec<Operand<D>> {
@@ -2300,7 +2299,7 @@ impl<'a, D: RiscVDisassembler + 'a> Mnem<'a, D> {
     }
 }
 
-impl<'a, D: RiscVDisassembler> fmt::Display for Mnem<'a, D> {
+impl<D: RiscVDisassembler> fmt::Display for Mnem<'_, D> {
     fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
         match (self.mnem(), self.suffix()) {
             (m, None) => f.pad(m),
@@ -2332,7 +2331,7 @@ impl StandardExtension for ExtensionSupported {
     }
 }
 
-pub trait RiscVDisassembler: Sized + Copy + Clone {
+pub trait RiscVDisassembler: Debug + Sized + Copy + Clone {
     type RegFile: RegFile;
     type MulDivExtension: StandardExtension;
     type AtomicExtension: StandardExtension;
@@ -3141,9 +3140,7 @@ pub trait RiscVDisassembler: Sized + Copy + Clone {
                                     f if (f & 0xfe0) == 0x120 => {
                                         Op::SfenceVma(RTypeIntInst::new(inst)?)
                                     }
-                                    0x104 => {
-                                        Op::SfenceVm(RTypeIntInst::new(inst)?)
-                                    }
+                                    0x104 => Op::SfenceVm(RTypeIntInst::new(inst)?),
 
                                     0x000 => Op::Ecall,
                                     0x001 => Op::Ebreak,
@@ -3171,7 +3168,7 @@ pub trait RiscVDisassembler: Sized + Copy + Clone {
 
                 Ok(Instr::Rv32(decoded))
             }
-            _ => return Err(TooShort),
+            _ => Err(TooShort),
         }
     }
 }