2 files changed, 4 insertions, 4 deletions
diff --git a/arch/riscv/disasm/src/lib.rs b/arch/riscv/disasm/src/lib.rs
index 152817c6..c35e76d3 100644
--- a/arch/riscv/disasm/src/lib.rs
+++ b/arch/riscv/disasm/src/lib.rs
@@ -1775,7 +1775,7 @@ pub enum Instr<D: RiscVDisassembler> {
 }
 
 impl<D: RiscVDisassembler> Instr<D> {
-    pub fn mnem(&self) -> Mnem<D> {
+    pub fn mnem(&self) -> Mnem<'_, D> {
         Mnem(self)
     }
 
@@ -2116,7 +2116,7 @@ impl<'a, D: RiscVDisassembler + 'a> Mnem<'a, D> {
         }
     }
 
-    fn suffix(&self) -> Option<Cow<str>> {
+    fn suffix(&self) -> Option<Cow<'_, str>> {
         match self.0 {
             // &Instr::Rv16(_) => None,
             &Instr::Rv32(ref op) | &Instr::Rv16(ref op) => match *op {
diff --git a/arch/riscv/src/lib.rs b/arch/riscv/src/lib.rs
index f59e1ebb..ef9e12e1 100644
--- a/arch/riscv/src/lib.rs
+++ b/arch/riscv/src/lib.rs
@@ -169,7 +169,7 @@ impl<D: RiscVDisassembler> RegisterInfo for Register<D> {
 impl<D: RiscVDisassembler> architecture::Register for Register<D> {
     type InfoType = Self;
 
-    fn name(&self) -> Cow<str> {
+    fn name(&self) -> Cow<'_, str> {
         match self.reg_type() {
             RegType::Integer(id) => match id {
                 0 => "zero".into(),
@@ -393,7 +393,7 @@ impl<D: RiscVDisassembler> From<Intrinsic> for RiscVIntrinsic<D> {
 }
 
 impl<D: RiscVDisassembler> architecture::Intrinsic for RiscVIntrinsic<D> {
-    fn name(&self) -> Cow<str> {
+    fn name(&self) -> Cow<'_, str> {
         match self.id {
             Intrinsic::Uret => "_uret".into(),
             Intrinsic::Sret => "_sret".into(),