diff options
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/.gitignore | 10 | ||||
| -rw-r--r-- | arch/x86/CMakeLists.txt | 73 | ||||
| -rw-r--r-- | arch/x86/LICENSE | 13 | ||||
| -rw-r--r-- | arch/x86/README.md | 44 | ||||
| -rw-r--r-- | arch/x86/arch_x86.cpp | 4880 | ||||
| -rw-r--r-- | arch/x86/arch_x86_common_architecture.h | 110 | ||||
| -rw-r--r-- | arch/x86/arch_x86_intrinsics.cpp | 5260 | ||||
| -rw-r--r-- | arch/x86/code_generator/README.md | 11 | ||||
| -rw-r--r-- | arch/x86/code_generator/iform-type-dump.txt | 35791 | ||||
| -rwxr-xr-x | arch/x86/code_generator/parse-iform-types.py | 452 | ||||
| -rw-r--r-- | arch/x86/code_generator/patch.diff | 43 | ||||
| -rw-r--r-- | arch/x86/il.cpp | 4195 | ||||
| -rw-r--r-- | arch/x86/il.h | 6481 | ||||
| m--------- | arch/x86/mbuild | 0 | ||||
| -rwxr-xr-x | arch/x86/test_lifting.py | 127 | ||||
| -rw-r--r-- | arch/x86/x86_intrinsic_cached_input_types.include | 430 | ||||
| -rw-r--r-- | arch/x86/x86_intrinsic_cached_output_types.include | 151 | ||||
| -rw-r--r-- | arch/x86/x86_intrinsic_input_type.include | 12670 | ||||
| -rw-r--r-- | arch/x86/x86_intrinsic_output_type.include | 12670 | ||||
| m--------- | arch/x86/xed | 0 | ||||
| -rw-r--r-- | arch/x86/xed-mbuild.patch | 57 | ||||
| m--------- | arch/x86/yasm | 0 |
22 files changed, 83468 insertions, 0 deletions
diff --git a/arch/x86/.gitignore b/arch/x86/.gitignore new file mode 100644 index 00000000..cfea9be5 --- /dev/null +++ b/arch/x86/.gitignore @@ -0,0 +1,10 @@ +CMakeFiles +CMakeCache.txt +cmake_install.cmake +Makefile +api +build +libarch_* +arch_*.dll +lib/libxed_macos_arm64.a +lib/libxed_macos_x86_64.a diff --git a/arch/x86/CMakeLists.txt b/arch/x86/CMakeLists.txt new file mode 100644 index 00000000..574969c0 --- /dev/null +++ b/arch/x86/CMakeLists.txt @@ -0,0 +1,73 @@ +cmake_minimum_required(VERSION 3.13 FATAL_ERROR) + +project(arch_x86) + +OPTION(BUILD_SHARED_LIBS "Build shared libraries" OFF) +OPTION(YASM_BUILD_TESTS "Enable building of tests" OFF) +add_subdirectory(yasm) + +set(XED_CONFIGURE_ARGS --no-encoder just-gen) +if(WIN32) + execute_process(COMMAND ${CMAKE_COMMAND} -E env OS=Windows_NT PYTHONPATH=${PROJECT_SOURCE_DIR}/mbuild + py -3 ${PROJECT_SOURCE_DIR}/xed/mfile.py ${XED_CONFIGURE_ARGS} + WORKING_DIRECTORY ${PROJECT_BINARY_DIR}) +else() + execute_process(COMMAND python3 ${PROJECT_SOURCE_DIR}/xed/mfile.py ${XED_CONFIGURE_ARGS} + WORKING_DIRECTORY ${PROJECT_BINARY_DIR}) +endif() + +if(NOT BN_INTERNAL_BUILD) + add_subdirectory(${PROJECT_SOURCE_DIR}/../.. ${PROJECT_BINARY_DIR}/api) +endif() + +file(GLOB SOURCES *.cpp *.h + ${PROJECT_SOURCE_DIR}/xed/src/common/*.c + ${PROJECT_SOURCE_DIR}/xed/src/dec/*.c + ${PROJECT_BINARY_DIR}/obj/*.c) + +# This accounts for the source code file replacement in +# https://github.com/intelxed/xed/blob/d41e876ba1bda5e53af2db74700216da29752fd7/datafiles/knc/files-no-avx512f.cfg#L58-L59 +# See https://github.com/Vector35/binaryninja-api/issues/4617 for more details +# Note to who updates xed: the path replacement file may change, search for its name in the xed directory to find its +# newest location +list(REMOVE_ITEM SOURCES ${PROJECT_SOURCE_DIR}/xed/src/common/xed-operand-values-interface-repl.c) +list(APPEND SOURCES ${PROJECT_SOURCE_DIR}/xed/datafiles/knc/xed-operand-values-interface-uisa.c) + +if(DEMO) + add_library(arch_x86 STATIC ${SOURCES}) +else() + add_library(arch_x86 SHARED ${SOURCES}) +endif() + +target_include_directories(arch_x86 + PRIVATE ${PROJECT_SOURCE_DIR} + PRIVATE ${PROJECT_SOURCE_DIR}/xed/include/public/xed + PRIVATE ${PROJECT_SOURCE_DIR}/xed/include/private + PRIVATE ${PROJECT_BINARY_DIR}/obj + PRIVATE ${PROJECT_BINARY_DIR}/obj/include-private) + +add_compile_definitions(XED_DECODER XED_AMD_ENABLED XED_VIA_ENABLED XED_AVX XED_SUPPORTS_AVX512 + XED_MPX XED_CET XED_SUPPORTS_SHA XED_SUPPORTS_WBNOINVD) + +target_link_libraries(arch_x86 binaryninjaapi) + +if(UNIX AND NOT APPLE) + target_link_options(arch_x86 PRIVATE "LINKER:--exclude-libs,ALL") +endif() + +set_target_properties(arch_x86 PROPERTIES + CXX_STANDARD 17 + CXX_VISIBILITY_PRESET hidden + CXX_STANDARD_REQUIRED ON + C_STANDARD 11 + VISIBILITY_INLINES_HIDDEN ON + POSITION_INDEPENDENT_CODE ON) + +if(BN_INTERNAL_BUILD) + plugin_rpath(arch_x86) + set_target_properties(arch_x86 PROPERTIES + LIBRARY_OUTPUT_DIRECTORY ${BN_CORE_PLUGIN_DIR} + RUNTIME_OUTPUT_DIRECTORY ${BN_CORE_PLUGIN_DIR}) + add_custom_command(TARGET arch_x86 POST_BUILD + COMMAND ${CMAKE_COMMAND} -E copy $<TARGET_FILE:yasm> ${BN_CORE_PLUGIN_DIR}) +endif() diff --git a/arch/x86/LICENSE b/arch/x86/LICENSE new file mode 100644 index 00000000..af67d90c --- /dev/null +++ b/arch/x86/LICENSE @@ -0,0 +1,13 @@ +Copyright 2020-2024 Vector 35 Inc. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/arch/x86/README.md b/arch/x86/README.md new file mode 100644 index 00000000..a3955bd8 --- /dev/null +++ b/arch/x86/README.md @@ -0,0 +1,44 @@ +# arch-x86 +This is the x86/x64 plugin that ships with Binary Ninja. + +## Contributing + +If you're interested in contributing when you submit your first PR, you'll receive a notice from [CLA Assistant](https://cla-assistant.io/) that allows you to sign our [Contribution License Agreement](https://binary.ninja/cla.pdf) online. + +## Building + +Building the architecture plugin requires `cmake` 3.13 or above. You will also need the +[Binary Ninja API source](https://github.com/Vector35/binaryninja-api). + +Run `cmake`. This can be done either from a separate build directory or from the source +directory. Once that is complete, run `make` in the build directory to compile the plugin. + +The plugin can be found in the root of the build directory as `libarch_x86.so`, +`libarch_x86.dylib` or `arch_x86.dll` depending on your platform. + +To install the plugin, first launch Binary Ninja and uncheck the "x86 architecture plugin" +option in the "Core Plugins" section. This will cause Binary Ninja to stop loading the +bundled plugin so that its replacement can be loaded. Once this is complete, you can copy +the plugin into the user plugins directory (you can locate this by using the "Open Plugin Folder" +option in the Binary Ninja UI). + +**Do not replace the architecture plugin in the Binary Ninja install directory. This will +be overwritten every time there is a Binary Ninja update. Use the above process to ensure that +updates do not automatically uninstall your custom build.** + +## XED + +XED is at commit afbb851b5f2f2ac6cdb6e6d9bebbaf2d4e77286d (April 15 2020) + +To update XED, first run `make download` to download the latest source and make necessary patches to it. Then run `make <platform>` to build xed for the selected platform. If everything works out, run `make clean_repo` to remove the downloaded mbuild and xed source. + +Update July 2020: + +Commit 9bdeca6d77065e5f1b23891655a26e510ffae74a changes the order of segement registers in the generated xed-reg-enum.h. If left unattended, this will cause database descrepency. Currently, we revert the commit 9bdeca6d77065e5f1b23891655a26e510ffae74a before building xed. This does not affect the xed's own functionality since the xed tests still pass without any issue. + +## License + +This repository itself is released under an [Apache 2.0](./license) license. Note that it relies on the following additional libraries each available under their respective licenses: + +- [Intel XED](https://intelxed.github.io/): [Apache 2.0](https://github.com/intelxed/xed/blob/master/LICENSE) +- [YASM](https://yasm.tortall.net/): ["new" BSD License](http://github.com/yasm/yasm/blob/master/BSD.txt) (inside of [./yasm/](yasm/)) diff --git a/arch/x86/arch_x86.cpp b/arch/x86/arch_x86.cpp new file mode 100644 index 00000000..e19fbef0 --- /dev/null +++ b/arch/x86/arch_x86.cpp @@ -0,0 +1,4880 @@ +#define _CRT_SECURE_NO_WARNINGS +#include <inttypes.h> +#include <stdio.h> +#include <string.h> +#include <sstream> +#include "binaryninjaapi.h" +#include "il.h" +extern "C" { + #include "xed-interface.h" +} +#include "arch_x86_common_architecture.h" + +using namespace BinaryNinja; +using namespace std; + +enum Elfx86RelocationType : uint32_t +{ + R_386_NONE = 0, // No relocation. + R_386_32 = 1, // Add symbol value. + R_386_PC32 = 2, // Add PC-relative symbol value. + R_386_GOT32 = 3, // Add PC-relative GOT offset. + R_386_PLT32 = 4, // Add PC-relative PLT offset. + R_386_COPY = 5, // Copy data from shared object. + R_386_GLOB_DAT = 6, // Set GOT entry to data address. + R_386_JUMP_SLOT = 7, // Set GOT entry to code address. + R_386_RELATIVE = 8, // Add load address of shared object. + R_386_GOTOFF = 9, // Add GOT-relative symbol address. + R_386_GOTPC = 10, // Add PC-relative GOT table address. + R_386_TLS_TPOFF = 14, // Negative offset in static TLS block + R_386_TLS_IE = 15, // Absolute address of GOT for -ve static TLS + R_386_TLS_GOTIE = 16, // GOT entry for negative static TLS block + R_386_TLS_LE = 17, // Negative offset relative to static TLS + R_386_TLS_GD = 18, // 32 bit offset to GOT (index,off) pair + R_386_TLS_LDM = 19, // 32 bit offset to GOT (index,zero) pair + R_386_16 = 20, // + R_386_PC16 = 21, // + R_386_8 = 22, // + R_386_PC8 = 23, // + R_386_TLS_GD_32 = 24, // 32 bit offset to GOT (index,off) pair + R_386_TLS_GD_PUSH = 25, // pushl instruction for Sun ABI GD sequence + R_386_TLS_GD_CALL = 26, // call instruction for Sun ABI GD sequence + R_386_TLS_GD_POP = 27, // popl instruction for Sun ABI GD sequence + R_386_TLS_LDM_32 = 28, // 32 bit offset to GOT (index,zero) pair + R_386_TLS_LDM_PUSH = 29, // pushl instruction for Sun ABI LD sequence + R_386_TLS_LDM_CALL = 30, // call instruction for Sun ABI LD sequence + R_386_TLS_LDM_POP = 31, // popl instruction for Sun ABI LD sequence + R_386_TLS_LDO_32 = 32, // 32 bit offset from start of TLS block + R_386_TLS_IE_32 = 33, // 32 bit offset to GOT static TLS offset entry + R_386_TLS_LE_32 = 34, // 32 bit offset within static TLS block + R_386_TLS_DTPMOD32 = 35, // GOT entry containing TLS index + R_386_TLS_DTPOFF32 = 36, // GOT entry containing TLS offset + R_386_TLS_TPOFF32 = 37, // GOT entry of -ve static TLS offset + R_386_SIZE32 = 38, // + R_386_TLS_GOTDESC = 39, // + R_386_TLS_DESC_CALL = 40, // + R_386_TLS_DESC = 41, // + R_386_IRELATIVE = 42, // PLT entry resolved indirectly at runtime + MAX_ELF_X86_RELOCATION +}; + +enum Elfx64RelocationType : uint32_t +{ + R_X86_64_NONE = 0, // No reloc + R_X86_64_64 = 1, // Direct 64 bit + R_X86_64_PC32 = 2, // PC relative 32 bit signed + R_X86_64_GOT32 = 3, // 32 bit GOT entry + R_X86_64_PLT32 = 4, // 32 bit PLT address + R_X86_64_COPY = 5, // Copy symbol at runtime + R_X86_64_GLOB_DAT = 6, // Create GOT entry + R_X86_64_JUMP_SLOT = 7, // Create PLT entry + R_X86_64_RELATIVE = 8, // Adjust by program base + R_X86_64_GOTPCREL = 9, // 32 bit signed pc relative offset to GOT + R_X86_64_32 = 10, // Direct 32 bit zero extended + R_X86_64_32S = 11, // Direct 32 bit sign extended + R_X86_64_16 = 12, // Direct 16 bit zero extended + R_X86_64_PC16 = 13, // 16 bit sign extended pc relative + R_X86_64_8 = 14, // Direct 8 bit sign extended + R_X86_64_PC8 = 15, // 8 bit sign extended pc relative + R_X86_64_DTPMOD64 = 16, + R_X86_64_DTPOFF64 = 17, + R_X86_64_TPOFF64 = 18, + R_X86_64_TLSGD = 19, + R_X86_64_TLSLD = 20, + R_X86_64_DTPOFF32 = 21, + R_X86_64_GOTTPOFF = 22, + R_X86_64_TPOFF32 = 23, + R_X86_64_PC64 = 24, + R_X86_64_GOTOFF64 = 25, + R_X86_64_GOTPC32 = 26, + R_X86_64_UNKNOWN27 = 27, + R_X86_64_UNKNOWN28 = 28, + R_X86_64_UNKNOWN29 = 29, + R_X86_64_UNKNOWN30 = 30, + R_X86_64_UNKNOWN31 = 31, + R_X86_64_SIZE32 = 32, + R_X86_64_SIZE64 = 33, + R_X86_64_GOTPC32_TLSDESC = 34, + R_X86_64_TLSDESC_CALL = 35, + R_X86_64_TLSDESC = 36, + R_X86_64_IRELATIVE = 37, + R_X86_64_RELATIVE64 = 38, + R_X86_64_PC32_BND = 39, + R_X86_64_PLT32_BND = 40, + R_X86_64_GOTPCRELX = 41, + R_X86_64_REX_GOTPCRELX = 42, + MAX_ELF_X64_RELOCATION +}; + +enum Machox86RelocationType : uint32_t +{ + GENERIC_RELOC_VANILLA = 0, + GENERIC_RELOC_PAIR = 1, + GENERIC_RELOC_SECTDIFF = 2, + GENERIC_RELOC_PB_LA_PTR = 3, + GENERIC_RELOC_LOCAL_SECTDIFF = 4, + GENERIC_RELOC_TLV = 5, + MACHO_MAX_X86_RELOCATION +}; + +enum Machox64RelocationType : uint32_t +{ + X86_64_RELOC_UNSIGNED = 0, + X86_64_RELOC_SIGNED = 1, + X86_64_RELOC_BRANCH = 2, + X86_64_RELOC_GOT_LOAD = 3, + X86_64_RELOC_GOT = 4, + X86_64_RELOC_SUBTRACTOR = 5, + X86_64_RELOC_SIGNED_1 = 6, + X86_64_RELOC_SIGNED_2 = 7, + X86_64_RELOC_SIGNED_4 = 8, + X86_64_RELOC_TLV = 9, + MACHO_MAX_X86_64_RELOCATION +}; + +enum COFFx86RelocationType : uint32_t +{ + PE_IMAGE_REL_I386_ABSOLUTE = 0x0000, // The relocation is ignored. + PE_IMAGE_REL_I386_DIR16 = 0x0001, // Not supported. + PE_IMAGE_REL_I386_REL16 = 0x0002, // Not supported. + PE_IMAGE_REL_I386_DIR32 = 0x0006, // The target's 32-bit VA. + PE_IMAGE_REL_I386_DIR32NB = 0x0007, // The target's 32-bit RVA. + PE_IMAGE_REL_I386_SEG12 = 0x0009, // Not supported. + PE_IMAGE_REL_I386_SECTION = 0x000A, // The 16-bit section index of the section that contains the target. This is used to support debugging information. + PE_IMAGE_REL_I386_SECREL = 0x000B, // The 32-bit offset of the target from the beginning of its section. This is used to support debugging information and static thread local storage. + PE_IMAGE_REL_I386_TOKEN = 0x000C, // The CLR token. + PE_IMAGE_REL_I386_SECREL7 = 0x000D, // A 7-bit offset from the base of the section that contains the target. + PE_IMAGE_REL_I386_REL32 = 0x0014, // The 32-bit relative displacement to the target. This supports the x86 relative branch and call instructions. + MAX_PE_X86_RELOCATION +}; + +enum COFFx64RelocationType : uint32_t +{ + PE_IMAGE_REL_AMD64_ABSOLUTE = 0x0000, // The relocation is ignored. + PE_IMAGE_REL_AMD64_ADDR64 = 0x0001, // The 64-bit VA of the relocation target. + PE_IMAGE_REL_AMD64_ADDR32 = 0x0002, // The 32-bit VA of the relocation target. + PE_IMAGE_REL_AMD64_ADDR32NB = 0x0003, // The 32-bit address without an image base (RVA). + PE_IMAGE_REL_AMD64_REL32 = 0x0004, // The 32-bit relative address from the byte following the relocation. + PE_IMAGE_REL_AMD64_REL32_1 = 0x0005, // The 32-bit address relative to byte distance 1 from the relocation. + PE_IMAGE_REL_AMD64_REL32_2 = 0x0006, // The 32-bit address relative to byte distance 2 from the relocation. + PE_IMAGE_REL_AMD64_REL32_3 = 0x0007, // The 32-bit address relative to byte distance 3 from the relocation. + PE_IMAGE_REL_AMD64_REL32_4 = 0x0008, // The 32-bit address relative to byte distance 4 from the relocation. + PE_IMAGE_REL_AMD64_REL32_5 = 0x0009, // The 32-bit address relative to byte distance 5 from the relocation. + PE_IMAGE_REL_AMD64_SECTION = 0x000A, // The 16-bit section index of the section that contains the target. This is used to support debugging information. + PE_IMAGE_REL_AMD64_SECREL = 0x000B, // The 32-bit offset of the target from the beginning of its section. This is used to support debugging information and static thread local storage. + PE_IMAGE_REL_AMD64_SECREL7 = 0x000C, // A 7-bit unsigned offset from the base of the section that contains the target. + PE_IMAGE_REL_AMD64_TOKEN = 0x000D, // CLR tokens. + PE_IMAGE_REL_AMD64_SREL32 = 0x000E, // A 32-bit signed span-dependent value emitted into the object. + PE_IMAGE_REL_AMD64_PAIR = 0x000F, // A pair that must immediately follow every span-dependent value. + PE_IMAGE_REL_AMD64_SSPAN32 = 0x0010, // A 32-bit signed span-dependent value that is applied at link time. + MAX_PE_X64_RELOCATION +}; + +enum PeRelocationType : uint32_t +{ + PE_IMAGE_USER_DEFINED = 0xffffffff, // User defined relocation type for synthesized relocations at IAT sites. + PE_IMAGE_REL_BASED_ABSOLUTE = 0, // The base relocation is skipped. This type can be used to pad a block. + PE_IMAGE_REL_BASED_HIGH = 1, // The base relocation adds the high 16 bits of the difference to the 16-bit field at offset. The 16-bit field represents the high value of a 32-bit word. + PE_IMAGE_REL_BASED_LOW = 2, // The base relocation adds the low 16 bits of the difference to the 16-bit field at offset. The 16-bit field represents the low half of a 32-bit word. + PE_IMAGE_REL_BASED_HIGHLOW = 3, // The base relocation applies all 32 bits of the difference to the 32-bit field at offset. + PE_IMAGE_REL_BASED_HIGHADJ = 4, // The base relocation adds the high 16 bits of the difference to the 16-bit field at offset. The 16-bit field represents the high value of a 32-bit word. The low 16 bits of the 32-bit value are stored in the 16-bit word that follows this base relocation. This means that this base relocation occupies two slots. + PE_IMAGE_REL_BASED_MIPS_JMPADDR = 5, // The relocation interpretation is dependent on the machine type. When the machine type is MIPS, the base relocation applies to a MIPS jump instruction. + PE_IMAGE_REL_BASED_ARM_MOV32 = 5, // This relocation is meaningful only when the machine type is ARM or Thumb. The base relocation applies the 32-bit address of a symbol across a consecutive MOVW/MOVT instruction pair. + PE_IMAGE_REL_BASED_RISCV_HIGH20 = 5, // This relocation is only meaningful when the machine type is RISC-V. The base relocation applies to the high 20 bits of a 32-bit absolute address. + PE_IMAGE_REL_BASE_RESERVED = 6, // Reserved, must be zero. + PE_IMAGE_REL_BASED_THUMB_MOV32 = 7, // This relocation is meaningful only when the machine type is Thumb. The base relocation applies the 32-bit address of a symbol to a consecutive MOVW/MOVT instruction pair. + PE_IMAGE_REL_BASED_RISCV_LOW12I = 7, // This relocation is only meaningful when the machine type is RISC-V. The base relocation applies to the low 12 bits of a 32-bit absolute address formed in RISC-V I-type instruction format. + PE_IMAGE_REL_BASED_RISCV_LOW12S = 8, // This relocation is only meaningful when the machine type is RISC-V. The base relocation applies to the low 12 bits of a 32-bit absolute address formed in RISC-V S-type instruction format. + PE_IMAGE_REL_BASED_MIPS_JMPADDR16 = 9, // The relocation is only meaningful when the machine type is MIPS. The base relocation applies to a MIPS16 jump instruction. + PE_IMAGE_REL_BASED_DIR64 = 10, // The base relocation applies the difference to the 64-bit field at offset. + MAX_PE_RELOCATION +}; + + +static const char* GetRelocationString(PeRelocationType relocType) +{ + static const char* relocTable[] = + { + "PE_IMAGE_REL_BASED_ABSOLUTE", + "PE_IMAGE_REL_BASED_HIGH", + "PE_IMAGE_REL_BASED_LOW", + "PE_IMAGE_REL_BASED_HIGHLOW", + "PE_IMAGE_REL_BASED_HIGHADJ", + "PE_IMAGE_REL_BASED_MIPS_JMPADDR", + "PE_IMAGE_REL_BASED_ARM_MOV32", + "PE_IMAGE_REL_BASED_RISCV_HIGH20", + "PE_IMAGE_REL_BASE_RESERVED", + "PE_IMAGE_REL_BASED_THUMB_MOV32", + "PE_IMAGE_REL_BASED_RISCV_LOW12I", + "PE_IMAGE_REL_BASED_RISCV_LOW12S", + "PE_IMAGE_REL_BASED_MIPS_JMPADDR16", + "PE_IMAGE_REL_BASED_DIR64" + }; + + if (relocType < MAX_PE_RELOCATION) + return relocTable[relocType]; + return "Unknown relocation"; +} + + +static const char* GetRelocationString(COFFx86RelocationType relocType) +{ + static const char* relocTable[] = + { + "PE_IMAGE_REL_I386_ABSOLUTE", + "PE_IMAGE_REL_I386_DIR16", + "PE_IMAGE_REL_I386_REL16", + "", "", "", + "PE_IMAGE_REL_I386_DIR32", + "PE_IMAGE_REL_I386_DIR32NB", + "", + "PE_IMAGE_REL_I386_SEG12", + "PE_IMAGE_REL_I386_SECTION", + "PE_IMAGE_REL_I386_SECREL", + "PE_IMAGE_REL_I386_TOKEN", + "PE_IMAGE_REL_I386_SECREL7", + "", "", "", "", "", "", + "PE_IMAGE_REL_I386_REL32", + }; + + if (relocType < MAX_PE_X86_RELOCATION) + return relocTable[relocType]; + return "Unknown x86 relocation"; +} + + +static const char* GetRelocationString(COFFx64RelocationType relocType) +{ + static const char* relocTable[] = + { + "PE_IMAGE_REL_AMD64_ABSOLUTE", + "PE_IMAGE_REL_AMD64_ADDR64", + "PE_IMAGE_REL_AMD64_ADDR32", + "PE_IMAGE_REL_AMD64_ADDR32NB", + "PE_IMAGE_REL_AMD64_REL32", + "PE_IMAGE_REL_AMD64_REL32_1", + "PE_IMAGE_REL_AMD64_REL32_2", + "PE_IMAGE_REL_AMD64_REL32_3", + "PE_IMAGE_REL_AMD64_REL32_4", + "PE_IMAGE_REL_AMD64_REL32_5", + "PE_IMAGE_REL_AMD64_SECTION", + "PE_IMAGE_REL_AMD64_SECREL", + "PE_IMAGE_REL_AMD64_SECREL7", + "PE_IMAGE_REL_AMD64_TOKEN", + "PE_IMAGE_REL_AMD64_SREL32", + "PE_IMAGE_REL_AMD64_PAIR", + "PE_IMAGE_REL_AMD64_SSPAN32", + }; + + if (relocType < MAX_PE_X64_RELOCATION) + return relocTable[relocType]; + return "Unknown x86_64 relocation"; +} + + +static const char* GetRelocationString(Elfx86RelocationType relocType) +{ + static const char* relocTable[] = + { + "R_386_NONE", + "R_386_32", + "R_386_PC32", + "R_386_GOT32", + "R_386_PLT32", + "R_386_COPY", + "R_386_GLOB_DAT", + "R_386_JUMP_SLOT", + "R_386_RELATIVE", + "R_386_GOTOFF", + "R_386_GOTPC", + "", + "", + "", + "R_386_TLS_TPOFF", + "R_386_TLS_IE", + "R_386_TLS_GOTIE", + "R_386_TLS_LE", + "R_386_TLS_GD", + "R_386_TLS_LDM", + "R_386_16", + "R_386_PC16", + "R_386_8", + "R_386_PC8", + "R_386_TLS_GD_32", + "R_386_TLS_GD_PUSH", + "R_386_TLS_GD_CALL", + "R_386_TLS_GD_POP", + "R_386_TLS_LDM_32", + "R_386_TLS_LDM_PUSH", + "R_386_TLS_LDM_CALL", + "R_386_TLS_LDM_POP", + "R_386_TLS_LDO_32", + "R_386_TLS_IE_32", + "R_386_TLS_LE_32", + "R_386_TLS_DTPMOD32", + "R_386_TLS_DTPOFF32", + "R_386_TLS_TPOFF32", + "R_386_SIZE32", + "R_386_TLS_GOTDESC", + "R_386_TLS_DESC_CALL", + "R_386_TLS_DESC", + "R_386_IRELATIVE", + }; + if (relocType < MAX_ELF_X86_RELOCATION) + return relocTable[relocType]; + return "Unknown x86 relocation"; +} + +static const char* GetRelocationString(Elfx64RelocationType relocType) +{ + static const char* relocTable[] = { + "R_X86_64_NONE", + "R_X86_64_64", + "R_X86_64_PC32", + "R_X86_64_GOT32", + "R_X86_64_PLT32", + "R_X86_64_COPY", + "R_X86_64_GLOB_DAT", + "R_X86_64_JUMP_SLOT", + "R_X86_64_RELATIVE", + "R_X86_64_GOTPCREL", + "R_X86_64_32", + "R_X86_64_32S", + "R_X86_64_16", + "R_X86_64_PC16", + "R_X86_64_8", + "R_X86_64_PC8", + "R_X86_64_DTPMOD64", + "R_X86_64_DTPOFF64", + "R_X86_64_TPOFF64", + "R_X86_64_TLSGD", + "R_X86_64_TLSLD", + "R_X86_64_DTPOFF32", + "R_X86_64_GOTTPOFF", + "R_X86_64_TPOFF32", + "R_X86_64_PC64", + "R_X86_64_GOTOFF64", + "R_X86_64_GOTPC32", + "R_X86_64_UNKNOWN27", + "R_X86_64_UNKNOWN28", + "R_X86_64_UNKNOWN29", + "R_X86_64_UNKNOWN30", + "R_X86_64_UNKNOWN31", + "R_X86_64_SIZE32", + "R_X86_64_SIZE64", + "R_X86_64_GOTPC32_TLSDESC", + "R_X86_64_TLSDESC_CALL", + "R_X86_64_TLSDESC", + "R_X86_64_IRELATIVE", + "R_X86_64_RELATIVE64", + "R_X86_64_PC32_BND", + "R_X86_64_PLT32_BND", + "R_X86_64_GOTPCRELX", + "R_X86_64_REX_GOTPCRELX"}; + if (relocType < MAX_ELF_X64_RELOCATION) + return relocTable[relocType]; + return "Unknown x86_64 relocation"; +} + +static const char* GetRelocationString(Machox86RelocationType relocType) +{ + static const char* relocTable[] = { + "GENERIC_RELOC_VANILLA", + "GENERIC_RELOC_PAIR", + "GENERIC_RELOC_SECTDIFF", + "GENERIC_RELOC_PB_LA_PTR", + "GENERIC_RELOC_LOCAL_SECTDIFF", + "GENERIC_RELOC_TLV", + }; + if (relocType < MACHO_MAX_X86_RELOCATION) + return relocTable[relocType]; + return "Unknown x86 relocation"; +} + +static const char* GetRelocationString(Machox64RelocationType relocType) +{ + static const char* relocTable[] = { + "X86_64_RELOC_UNSIGNED", + "X86_64_RELOC_SIGNED", + "X86_64_RELOC_BRANCH", + "X86_64_RELOC_GOT_LOAD", + "X86_64_RELOC_GOT", + "X86_64_RELOC_SUBTRACTOR", + "X86_64_RELOC_SIGNED_1", + "X86_64_RELOC_SIGNED_2", + "X86_64_RELOC_SIGNED_4", + "X86_64_RELOC_TLV" + }; + if (relocType < MACHO_MAX_X86_64_RELOCATION) + return relocTable[relocType]; + return "Unknown x64 relocation"; +} + + +bool X86CommonArchitecture::Decode(const uint8_t* data, size_t len, xed_decoded_inst_t* xedd) +{ + // Zero out structure data, and keep the current destructuring mode (32/64/etc) + xed_decoded_inst_zero_keep_mode(xedd); + + xed3_operand_set_cet(xedd, 1); + xed3_operand_set_mpxmode(xedd, 1); + + // Decode the data and check for errors + xed_error_enum_t xed_error = xed_decode(xedd, data, (unsigned)len); + switch(xed_error) + { + case XED_ERROR_NONE: + return true; + default: + return false; + } +} + +size_t X86CommonArchitecture::GetAddressSizeBits() const +{ + return GetAddressSize() * 8; +} + +uint64_t X86CommonArchitecture::GetAddressMask() const +{ + if (GetAddressSizeBits() == 64) + return (uint64_t)-1; + return (((uint64_t)1) << GetAddressSizeBits()) - 1; +} + +void X86CommonArchitecture::SetInstructionInfoForInstruction(uint64_t addr, InstructionInfo& result, xed_decoded_inst_t* xedd) +{ + result.length = xed_decoded_inst_get_length(xedd); + + const uint64_t abs_br = xed_decoded_inst_get_branch_displacement(xedd) + addr + xed_decoded_inst_get_length(xedd); + const xed_iform_enum_t xedd_iForm = xed_decoded_inst_get_iform_enum(xedd); + const xed_iclass_enum_t xedd_iClass = xed_decoded_inst_get_iclass(xedd); + const uint64_t immediateOne = xed_decoded_inst_get_unsigned_immediate(xedd); + // 1. First parse 'generally', by instruction category, then + // 2. break down to special cases and impliment iclass and possibly iform-specific cases + + switch (xed_decoded_inst_get_category(xedd)) + { + case XED_CATEGORY_CALL: + // CALL instruction with an immediate as the first operand and it's not the next instruction + if ((abs_br != addr+result.length) && ((xedd_iForm == XED_IFORM_CALL_NEAR_RELBRz) || (xedd_iForm == XED_IFORM_CALL_NEAR_RELBRd))) + result.AddBranch(CallDestination, abs_br); + break; + + case XED_CATEGORY_UNCOND_BR: + if (xed_operand_name(xed_inst_operand(xed_decoded_inst_inst(xedd), 0)) == XED_OPERAND_RELBR) + result.AddBranch(UnconditionalBranch, abs_br); + else + result.AddBranch(UnresolvedBranch); + break; + + case XED_CATEGORY_COND_BR: + result.AddBranch(TrueBranch, abs_br); + result.AddBranch(FalseBranch, addr + result.length); + break; + + case XED_CATEGORY_INTERRUPT: + if (xed_decoded_inst_get_unsigned_immediate(xedd) == 0x80) + result.AddBranch(SystemCall); + else if (xedd_iClass == XED_ICLASS_INT3 || (xedd_iClass == XED_ICLASS_INT && immediateOne == 0x29)) + result.AddBranch(ExceptionBranch); + break; + + case XED_CATEGORY_SYSCALL: + result.AddBranch(SystemCall); + break; + + case XED_CATEGORY_SYSRET: + result.AddBranch(FunctionReturn); + break; + + case XED_CATEGORY_RET: + result.AddBranch(FunctionReturn); + break; + + default: + switch (xedd_iClass) + { + // case XED_ICLASS_UD0: + // case XED_ICLASS_UD1: + case XED_ICLASS_UD2: + case XED_ICLASS_HLT: + result.AddBranch(ExceptionBranch); + break; + + default: + break; + } + break; + } +} + +bool X86CommonArchitecture::IsConditionalJump(xed_decoded_inst_t* xedd) +{ + return (xed_decoded_inst_get_category(xedd) == XED_CATEGORY_COND_BR); +} + +string X86CommonArchitecture::GetSizeString(const size_t size) const +{ + switch (size) + { + case 1: + return "byte "; + case 2: + return "word "; + case 4: + return "dword "; + case 8: + return "qword "; + case 10: + return "tword "; + case 16: + return "oword "; + default: + return ""; + } +} + +BNRegisterInfo X86CommonArchitecture::RegisterInfo(xed_reg_enum_t fullWidthReg, size_t offset, size_t size, bool zeroExtend) +{ + BNRegisterInfo result; + result.fullWidthRegister = fullWidthReg; + result.offset = offset; + result.size = size; + result.extend = zeroExtend ? ZeroExtendToFullWidth : NoExtend; + return result; +} + +void X86CommonArchitecture::GetAddressSizeToken(const short bytes, vector<InstructionTextToken>& result, const bool lowerCase) +{ + // Size + switch (bytes) + { + case 1: + if (lowerCase) + result.emplace_back(BeginMemoryOperandToken,"byte "); + else + result.emplace_back(BeginMemoryOperandToken,"BYTE "); + break; + case 2: + if (lowerCase) + result.emplace_back(BeginMemoryOperandToken,"word "); + else + result.emplace_back(BeginMemoryOperandToken,"WORD "); + break; + case 4: + if (lowerCase) + result.emplace_back(BeginMemoryOperandToken,"dword "); + else + result.emplace_back(BeginMemoryOperandToken,"DWORD "); + break; + case 8: + if (lowerCase) + result.emplace_back(BeginMemoryOperandToken,"qword "); + else + result.emplace_back(BeginMemoryOperandToken,"QWORD "); + break; + case 10: + if (lowerCase) + result.emplace_back(BeginMemoryOperandToken,"tword "); + else + result.emplace_back(BeginMemoryOperandToken,"TWORD "); + break; + case 16: + if (lowerCase) + result.emplace_back(BeginMemoryOperandToken,"xmmword "); + else + result.emplace_back(BeginMemoryOperandToken,"XMMWORD "); + break; + case 32: + if (lowerCase) + result.emplace_back(BeginMemoryOperandToken,"ymmword "); + else + result.emplace_back(BeginMemoryOperandToken,"YMMWORD "); + break; + case 64: + if (lowerCase) + result.emplace_back(BeginMemoryOperandToken,"zmmword "); + else + result.emplace_back(BeginMemoryOperandToken,"ZMMWORD "); + break; + default: + break; + } +} + +unsigned short X86CommonArchitecture::GetInstructionOpcode(const xed_decoded_inst_t* const xedd, const xed_operand_values_t* const ov, vector<InstructionTextToken>& result) const +{ + string opcode = ""; + if (xed_decoded_inst_has_mpx_prefix(xedd)) + opcode += "BND "; + if (xed_decoded_inst_is_xacquire(xedd)) + opcode += "XACQUIRE "; + if (xed_decoded_inst_is_xrelease(xedd)) + opcode += "XRELEASE "; + if (xed_operand_values_has_lock_prefix(ov)) + opcode += "LOCK "; + if (xed_operand_values_has_real_rep(ov)) + { + if (xed_operand_values_has_rep_prefix(ov)) + opcode += "REP "; + if (xed_operand_values_has_repne_prefix(ov)) + opcode += "REPNE "; + } + else if (xed_operand_values_branch_not_taken_hint(ov)) + opcode += "HINT-NOT-TAKEN "; + else if (xed_operand_values_branch_taken_hint(ov)) + opcode += "HINT-TAKEN "; + + switch (m_disassembly_options.df) + { + case DF_INTEL: + opcode += string(xed_iform_to_iclass_string_intel(xed_decoded_inst_get_iform_enum(xedd))); + break; + case DF_BN_INTEL: + // To match asmx86 disassembly + switch (xed_decoded_inst_get_iclass(xedd)) + { + case XED_ICLASS_RET_NEAR: + opcode += "RETN"; + break; + case XED_ICLASS_JZ: + opcode += "JE"; + break; + case XED_ICLASS_JNZ: + opcode += "JNE"; + break; + case XED_ICLASS_JNB: + opcode += "JAE"; + break; + case XED_ICLASS_JNBE: + opcode += "JA"; + break; + case XED_ICLASS_JP: + opcode += "JPE"; + break; + case XED_ICLASS_JNP: + opcode += "JPO"; + break; + case XED_ICLASS_JNL: + opcode += "JGE"; + break; + case XED_ICLASS_JNLE: + opcode += "JG"; + break; + + case XED_ICLASS_SETNB: + opcode += "SETAE"; + break; + case XED_ICLASS_SETZ: + opcode += "SETE"; + break; + case XED_ICLASS_SETNZ: + opcode += "SETNE"; + break; + case XED_ICLASS_SETNBE: + opcode += "SETA"; + break; + case XED_ICLASS_SETP: + opcode += "SETPE"; + break; + case XED_ICLASS_SETNP: + opcode += "SETPO"; + break; + case XED_ICLASS_SETNL: + opcode += "SETGE"; + break; + case XED_ICLASS_SETNLE: + opcode += "SETG"; + break; + + case XED_ICLASS_CMOVNB: + opcode += "CMOVAE"; + break; + case XED_ICLASS_CMOVZ: + opcode += "CMOVE"; + break; + case XED_ICLASS_CMOVNZ: + opcode += "CMOVNE"; + break; + case XED_ICLASS_CMOVNBE: + opcode += "CMOVA"; + break; + case XED_ICLASS_CMOVP: + opcode += "CMOVPE"; + break; + case XED_ICLASS_CMOVNP: + opcode += "CMOVPO"; + break; + case XED_ICLASS_CMOVNL: + opcode += "CMOVGE"; + break; + case XED_ICLASS_CMOVNLE: + opcode += "CMOVG"; + break; + + default: + opcode += string(xed_iform_to_iclass_string_intel(xed_decoded_inst_get_iform_enum(xedd))); + } + break; + case DF_ATT: + opcode += string(xed_iform_to_iclass_string_att(xed_decoded_inst_get_iform_enum(xedd))); + break; + case DF_XED: + opcode += string(xed_iclass_enum_t2str(xed_decoded_inst_get_iclass(xedd))); + break; + default: + LogError("Invalid Disassembly Flavor"); + } + + if (m_disassembly_options.lowerCase) + for (char& c : opcode) + c = tolower(c); + else + for (char& c : opcode) + c = toupper(c); + + result.emplace_back(InstructionToken, opcode); + + return (unsigned short)opcode.length(); +} + +void X86CommonArchitecture::GetInstructionPadding(const unsigned int instruction_name_length, vector<InstructionTextToken>& result) const +{ + string padding = ""; + const short min = 7 < instruction_name_length ? 7 : instruction_name_length; + for (unsigned short delim = 0; delim < (8 - min); ++delim) + padding += ' '; + result.emplace_back(TextToken, padding); +} + +// (in theory) Exactly how XED wants the world to see x86 +void X86CommonArchitecture::GetOperandTextIntel(const xed_decoded_inst_t* const xedd, const uint64_t addr, const size_t len, const xed_operand_values_t* const ov, const xed_inst_t* const xi, vector<InstructionTextToken>& result) const +{ + xed_reg_enum_t extra_index_operand = XED_REG_INVALID; + + // Get operands + for (unsigned int opIndex = 0; opIndex < xed_inst_noperands(xi); ++opIndex) + { + const xed_operand_t* op = xed_inst_operand(xi, opIndex); + const xed_operand_enum_t op_name = xed_operand_name(op); + + // XED's suppressed operands shouln't be represented in Intel syntax + if (xed_operand_operand_visibility(op) == XED_OPVIS_SUPPRESSED) + { + if ((xed_decoded_inst_get_category(xedd) == XED_CATEGORY_STRINGOP) && + (op_name == XED_OPERAND_MEM0 || op_name == XED_OPERAND_MEM1)) + { + if (op_name == XED_OPERAND_MEM1) + result.emplace_back(OperandSeparatorToken, m_disassembly_options.separator); + } + else + continue; + } + + switch(op_name) + { + case XED_OPERAND_REG0: + case XED_OPERAND_REG1: + case XED_OPERAND_REG2: + case XED_OPERAND_REG3: + case XED_OPERAND_REG4: + case XED_OPERAND_REG5: + case XED_OPERAND_REG6: + case XED_OPERAND_REG7: + case XED_OPERAND_REG8: + { + string reg = ""; + + const xed_reg_enum_t xedReg = xed_decoded_inst_get_reg(xedd, op_name); + if ((xedReg >= XED_REG_X87_FIRST) && (xedReg <= XED_REG_X87_LAST)) + { + reg += "ST"; + reg += ('0' + (xedReg-XED_REG_X87_FIRST)); + } + else + { + reg += xed_reg_enum_t2str(xedReg); + } + if (m_disassembly_options.lowerCase) + for (char& c : reg) + c = tolower(c); + result.emplace_back(RegisterToken, reg); + break; + } + case XED_OPERAND_AGEN: + case XED_OPERAND_MEM0: + { + GetAddressSizeToken(xed_decoded_inst_operand_length_bits(xedd, opIndex) / 8, result, m_disassembly_options.lowerCase); + + if (m_disassembly_options.lowerCase) + result.emplace_back(TextToken, "ptr "); + else + result.emplace_back(TextToken, "PTR "); + result.emplace_back(TextToken, "["); + + // Segment + const xed_reg_enum_t seg = xed_decoded_inst_get_seg_reg(xedd, 0); + const bool validSegment = (seg != XED_REG_INVALID && !xed_operand_values_using_default_segment(ov, 0)); + if (validSegment) + { + string seg_str(xed_reg_enum_t2str(seg)); + if (m_disassembly_options.lowerCase) + for (char& c : seg_str) + c = tolower(c); + result.emplace_back(RegisterToken, seg_str); + result.emplace_back(TextToken, ":"); + } + + bool started = false; + const xed_reg_enum_t base = xed_decoded_inst_get_base_reg(xedd, 0); + + int64_t disp = xed_decoded_inst_get_memory_displacement(xedd, 0); + + if ((base != XED_REG_INVALID) && !((base == XED_REG_RIP) || (base == XED_REG_EIP) || (base == XED_REG_IP))) + { + string base_str(xed_reg_enum_t2str(base)); + if (m_disassembly_options.lowerCase) + for (char& c : base_str) + c = tolower(c); + result.emplace_back(RegisterToken, base_str); + started = true; + } + else if ((base == XED_REG_RIP) || (base == XED_REG_EIP) || (base == XED_REG_IP)) + { + if (xed_operand_values_has_memory_displacement(ov)) + disp += addr + len; + else + disp = addr + len; + + stringstream sstream; + if (m_disassembly_options.lowerCase) + sstream << "0x" << hex << nouppercase << disp; + else + sstream << "0x" << hex << uppercase << disp; + + result.emplace_back(CodeRelativeAddressToken, sstream.str(), disp, GetAddressSize()); + + result.emplace_back(EndMemoryOperandToken, "]"); + break; + } + + const xed_reg_enum_t index = xed_decoded_inst_get_index_reg(xedd, 0); + if (index != XED_REG_INVALID) + { + if (xed_decoded_inst_get_attribute(xedd, XED_ATTRIBUTE_INDEX_REG_IS_POINTER)) + { + // MPX BNDLDX/BNDSTX instr are unusual in that they use + // the index reg as distinct operand. + extra_index_operand = index; + } + else // normal path + { + if (started) + result.emplace_back(TextToken, "+"); + started = true; + + string index_str(xed_reg_enum_t2str(index)); + if (m_disassembly_options.lowerCase) + for (char& c : index_str) + c = tolower(c); + + result.emplace_back(RegisterToken, index_str); + + const unsigned int scale = xed_decoded_inst_get_scale(xedd, 0); + if (scale != 1) + { + result.emplace_back(TextToken, "*"); + stringstream sstream; + sstream << scale; + result.emplace_back(IntegerToken, sstream.str(), scale, 1); + } + } + } + + const unsigned short disp_bytes = xed_decoded_inst_get_memory_displacement_width_bits(xedd, 0) / 8; + + if (xed_operand_values_has_memory_displacement(ov) && + ((disp != 0) || (!started && validSegment))) + { + stringstream sstream; + sstream << "0x" << hex; + if (m_disassembly_options.lowerCase) + sstream << nouppercase; + else + sstream << uppercase; + + if (started) + { + if (disp < 0) + { + result.emplace_back(TextToken, "-"); + disp = -disp; + } + else + result.emplace_back(TextToken, "+"); + + if (disp_bytes == 2) + sstream << (uint16_t)disp; + else if (disp_bytes == 4) + sstream << (uint32_t)disp; + else if (disp_bytes == 8) + sstream << (uint64_t)disp; + else + sstream << disp; + result.emplace_back(IntegerToken, sstream.str(), disp, disp_bytes); + } + else + { + sstream << disp; + + if (validSegment) + result.emplace_back(IntegerToken, sstream.str(), disp, GetAddressSize()); + else + result.emplace_back(PossibleAddressToken, sstream.str(), disp, GetAddressSize()); + } + } + else if (xed_operand_values_has_memory_displacement(ov) && + ((disp == 0) && (!started))) + { + result.emplace_back(IntegerToken, "0x0", disp, GetAddressSize()); + } + result.emplace_back(EndMemoryOperandToken, "]"); + + break; + } + case XED_OPERAND_MEM1: + { + GetAddressSizeToken(xed_decoded_inst_operand_length_bits(xedd, opIndex) / 8, result, m_disassembly_options.lowerCase); + + if (m_disassembly_options.lowerCase) + result.emplace_back(TextToken, "ptr "); + else + result.emplace_back(TextToken, "PTR "); + + // Segment + const xed_reg_enum_t seg = xed_decoded_inst_get_seg_reg(xedd, 1); + if (seg != XED_REG_INVALID && !xed_operand_values_using_default_segment(ov, 1)) + { + string seg_str(xed_reg_enum_t2str(seg)); + if (m_disassembly_options.lowerCase) + for (char& c : seg_str) + c = tolower(c); + result.emplace_back(RegisterToken, seg_str); + + result.emplace_back(TextToken, ":"); + } + + result.emplace_back(TextToken, "["); + const xed_reg_enum_t base = xed_decoded_inst_get_base_reg(xedd, 1); + if (base != XED_REG_INVALID) + { + string base_str(xed_reg_enum_t2str(base)); + if (m_disassembly_options.lowerCase) + for (char& c : base_str) + c = tolower(c); + result.emplace_back(RegisterToken, base_str); + } + result.emplace_back(EndMemoryOperandToken, "]"); + + break; + } + case XED_OPERAND_IMM0: + { + const size_t addrSize = xed_decoded_inst_get_machine_mode_bits(xedd) / 8; + const unsigned int immediateSize = xed_decoded_inst_get_operand_width(xedd) / 8; + + stringstream sstream; + sstream << "0x" << hex; + if (m_disassembly_options.lowerCase) + sstream << nouppercase; + else + sstream << uppercase; + + if (xed_decoded_inst_get_immediate_is_signed(xedd) && (immediateSize != 1)) + { + const int64_t immediateValue = xed_decoded_inst_get_signed_immediate(xedd); + + if (immediateValue >= 0) + sstream << immediateValue; // Don't zero extend + else + { + // I'm not proud of this switch statement... It was the product of a lot of pain. + switch (immediateSize) // For sign extentions + { + case 1: + sstream << (int8_t)immediateValue; + break; + case 2: + sstream << (int16_t)immediateValue; + break; + case 4: + sstream << (int32_t)immediateValue; + break; + default: + sstream << (int64_t)immediateValue; + } + } + + if (immediateSize == addrSize) + result.emplace_back(PossibleAddressToken, sstream.str(), immediateValue, immediateSize); + else + result.emplace_back(IntegerToken, sstream.str(), immediateValue, immediateSize); + } + else + { + const uint64_t immediateValue = xed_decoded_inst_get_unsigned_immediate(xedd); + sstream << immediateValue; + if (immediateSize == addrSize) + result.emplace_back(PossibleAddressToken, sstream.str(), immediateValue, immediateSize); + else + result.emplace_back(IntegerToken, sstream.str(), immediateValue, immediateSize); + } + break; + } + case XED_OPERAND_IMM1: // The ENTER instruction + { + stringstream sstream; + sstream << "0x" << hex; + if (m_disassembly_options.lowerCase) + sstream << nouppercase; + else + sstream << uppercase; + + sstream << (uint16_t)xed_decoded_inst_get_second_immediate(xedd); + result.emplace_back(IntegerToken, sstream.str(), xed_decoded_inst_get_second_immediate(xedd), 1); + break; + } + case XED_OPERAND_PTR: // TODO...remove? + { + stringstream sstream; + sstream << "0x" << hex; + if (m_disassembly_options.lowerCase) + sstream << nouppercase; + else + sstream << uppercase; + + sstream << xed_decoded_inst_get_branch_displacement(xedd); + result.emplace_back(PossibleAddressToken, sstream.str(), xed_decoded_inst_get_branch_displacement(xedd), 8); + break; + } + case XED_OPERAND_RELBR: + { + const int64_t relbr = xed_decoded_inst_get_branch_displacement(xedd) + addr + xed_decoded_inst_get_length(xedd); + + stringstream sstream; + sstream << "0x" << hex; + if (m_disassembly_options.lowerCase) + sstream << nouppercase; + else + sstream << uppercase; + + sstream << relbr; + result.emplace_back(CodeRelativeAddressToken, sstream.str(), relbr, 8); + break; + } + default: + { + result.emplace_back(TextToken, "unimplimented"); + } // default case of outer switch + } // outer switch + + // If there is another operand and it is visable, print delimiter + if ((opIndex != xed_inst_noperands(xi)-1) && + ((xed_operand_operand_visibility(xed_inst_operand(xi, opIndex+1)) == XED_OPVIS_EXPLICIT) || + (xed_operand_operand_visibility(xed_inst_operand(xi, opIndex+1)) == XED_OPVIS_IMPLICIT))) + result.emplace_back(OperandSeparatorToken, m_disassembly_options.separator); + } + + if (extra_index_operand != XED_REG_INVALID) + { + result.emplace_back(OperandSeparatorToken, m_disassembly_options.separator); + string reg = xed_reg_enum_t2str(extra_index_operand); + if (m_disassembly_options.lowerCase) + for (char& c : reg) + c = tolower(c); + result.emplace_back(RegisterToken, reg); + } +} + +// The syntax used by asmx86, that users are used to (also the only one that should be garenteed to roundtrip with asm) +void X86CommonArchitecture::GetOperandTextBNIntel(const xed_decoded_inst_t* const xedd, const uint64_t addr, const size_t len, const xed_operand_values_t* const ov, const xed_inst_t* const xi, vector<InstructionTextToken>& result) const +{ + xed_reg_enum_t extra_index_operand = XED_REG_INVALID; + + // Get operands + for (unsigned int opIndex = 0; opIndex < xed_inst_noperands(xi); ++opIndex) + { + const xed_operand_t* op = xed_inst_operand(xi, opIndex); + const xed_operand_enum_t op_name = xed_operand_name(op); + + // XED's suppressed operands shouln't be represented in Intel syntax + if (xed_operand_operand_visibility(op) == XED_OPVIS_SUPPRESSED) + { + if ((xed_decoded_inst_get_category(xedd) == XED_CATEGORY_STRINGOP) && + (op_name == XED_OPERAND_MEM0 || op_name == XED_OPERAND_MEM1)) + { + if (op_name == XED_OPERAND_MEM1) + result.emplace_back(OperandSeparatorToken, m_disassembly_options.separator); + } + else + continue; + } + + switch(op_name) + { + case XED_OPERAND_REG0: + case XED_OPERAND_REG1: + case XED_OPERAND_REG2: + case XED_OPERAND_REG3: + case XED_OPERAND_REG4: + case XED_OPERAND_REG5: + case XED_OPERAND_REG6: + case XED_OPERAND_REG7: + case XED_OPERAND_REG8: + { + string reg = ""; + + const xed_reg_enum_t xedReg = xed_decoded_inst_get_reg(xedd, op_name); + if ((xedReg >= XED_REG_X87_FIRST) && (xedReg <= XED_REG_X87_LAST)) + { + reg += "ST"; + reg += ('0' + (xedReg - XED_REG_X87_FIRST)); + } + // As of July 2020, the XED now outputs these registers as mm0, etc. + // However, to maintain backward-compatibility, we need to make them mmx0, etc, + // as they previously are + else if ((xedReg >= XED_REG_MMX0) && (xedReg <= XED_REG_MMX1)) + { + reg += "MMX"; + reg += ('0' + (xedReg - XED_REG_MMX0)); + } + else + { + reg += xed_reg_enum_t2str(xedReg); + } + + if (m_disassembly_options.lowerCase) + for (char& c : reg) + c = tolower(c); + + result.emplace_back(RegisterToken, reg); + + // handle the {z} modifier + if (XED_REG_K1 <= xedReg && xedReg <= XED_REG_K7) + { + if(xed_decoded_inst_zeroing(xedd)) + { + if (m_disassembly_options.lowerCase) + result.emplace_back(TextToken, " {z}"); + else + result.emplace_back(TextToken, " {Z}"); + } + } + + break; + } + case XED_OPERAND_AGEN: + case XED_OPERAND_MEM0: + { + // Size + if (xed_inst_iclass(xi) != XED_ICLASS_LEA) + GetAddressSizeToken(xed_decoded_inst_operand_length_bits(xedd, opIndex) / 8, result, m_disassembly_options.lowerCase); + + result.emplace_back(TextToken, "["); + // Segment + const xed_reg_enum_t seg = xed_decoded_inst_get_seg_reg(xedd, 0); + const bool validSegment = (seg != XED_REG_INVALID && !xed_operand_values_using_default_segment(ov, 0)); + if (validSegment) + { + string seg_str(xed_reg_enum_t2str(seg)); + if (m_disassembly_options.lowerCase) + for (char& c : seg_str) + c = tolower(c); + result.emplace_back(RegisterToken, seg_str); + result.emplace_back(TextToken, ":"); + } + + bool started = false; + xed_reg_enum_t base = xed_decoded_inst_get_base_reg(xedd, 0); + + int64_t disp = xed_decoded_inst_get_memory_displacement(xedd, 0); + + if ((base != XED_REG_INVALID) && !((base == XED_REG_RIP) || (base == XED_REG_EIP) || (base == XED_REG_IP))) + { + string base_str(xed_reg_enum_t2str(base)); + if (m_disassembly_options.lowerCase) + for (char& c : base_str) + c = tolower(c); + result.emplace_back(RegisterToken, base_str); + started = true; + } + else if ((base == XED_REG_RIP) || (base == XED_REG_EIP) || (base == XED_REG_IP)) + { + if (m_disassembly_options.lowerCase) + result.emplace_back(TextToken, "rel "); + else + result.emplace_back(TextToken, "REL "); + + if (xed_operand_values_has_memory_displacement(ov)) + disp += addr + len; + else + disp = addr + len; + + stringstream sstream; + if (m_disassembly_options.lowerCase) + sstream << "0x" << hex << nouppercase << disp; + else + sstream << "0x" << hex << uppercase << disp; + + result.emplace_back(CodeRelativeAddressToken, sstream.str(), disp, GetAddressSize()); + + result.emplace_back(EndMemoryOperandToken, "]"); + break; + } + + const xed_reg_enum_t index = xed_decoded_inst_get_index_reg(xedd, 0); + if (index != XED_REG_INVALID) + { + if (xed_decoded_inst_get_attribute(xedd, XED_ATTRIBUTE_INDEX_REG_IS_POINTER)) + { + // MPX BNDLDX/BNDSTX instr are unusual in that they use + // the index reg as distinct operand. + extra_index_operand = index; + } + else // normal path + { + if (started) + result.emplace_back(TextToken, "+"); + started = true; + + string index_str(xed_reg_enum_t2str(index)); + if (m_disassembly_options.lowerCase) + for (char& c : index_str) + c = tolower(c); + + result.emplace_back(RegisterToken, index_str); + + const unsigned int scale = xed_decoded_inst_get_scale(xedd, 0); + if (scale != 1) + { + result.emplace_back(TextToken, "*"); + stringstream sstream; + sstream << scale; + result.emplace_back(IntegerToken, sstream.str(), scale, 1); + } + } + } + + const unsigned short disp_bytes = xed_decoded_inst_get_memory_displacement_width_bits(xedd, 0) / 8; + + if (xed_operand_values_has_memory_displacement(ov) && + ((disp != 0) || (!started && validSegment))) + { + stringstream sstream; + sstream << "0x" << hex; + if (m_disassembly_options.lowerCase) + sstream << nouppercase; + else + sstream << uppercase; + + if (started) + { + if (disp < 0) + { + result.emplace_back(TextToken, "-"); + disp = -disp; + } + else + result.emplace_back(TextToken, "+"); + + if (disp_bytes == 2) + sstream << (uint16_t)disp; + else if (disp_bytes == 4) + sstream << (uint32_t)disp; + else if (disp_bytes == 8) + sstream << (uint64_t)disp; + else + sstream << disp; + result.emplace_back(IntegerToken, sstream.str(), disp, disp_bytes); + } + else + { + sstream << disp; + + if (validSegment) + result.emplace_back(IntegerToken, sstream.str(), disp, GetAddressSize()); + else + result.emplace_back(PossibleAddressToken, sstream.str(), disp, GetAddressSize()); + } + } + else if (xed_operand_values_has_memory_displacement(ov) && + ((disp == 0) && (!started))) + { + result.emplace_back(IntegerToken, "0x0", disp, GetAddressSize()); + } + + result.emplace_back(EndMemoryOperandToken, "]"); + + break; + } + case XED_OPERAND_MEM1: + { + + + // Segment + const xed_reg_enum_t seg = xed_decoded_inst_get_seg_reg(xedd, 1); + if (seg != XED_REG_INVALID && !xed_operand_values_using_default_segment(ov, 1)) + { + string seg_str(xed_reg_enum_t2str(seg)); + if (m_disassembly_options.lowerCase) + for (char& c : seg_str) + c = tolower(c); + result.emplace_back(RegisterToken, seg_str); + + result.emplace_back(TextToken, ":"); + } + + result.emplace_back(TextToken, "["); + const xed_reg_enum_t base = xed_decoded_inst_get_base_reg(xedd, 1); + if (base != XED_REG_INVALID) + { + string base_str(xed_reg_enum_t2str(base)); + if (m_disassembly_options.lowerCase) + for (char& c : base_str) + c = tolower(c); + result.emplace_back(RegisterToken, base_str); + } + result.emplace_back(EndMemoryOperandToken, "]"); + + break; + } + case XED_OPERAND_IMM0: + { + const size_t addrSize = xed_decoded_inst_get_machine_mode_bits(xedd) / 8; + const unsigned int immediateSize = xed_decoded_inst_get_operand_width(xedd) / 8; + + stringstream sstream; + sstream << "0x" << hex; + if (m_disassembly_options.lowerCase) + sstream << nouppercase; + else + sstream << uppercase; + + if (xed_decoded_inst_get_immediate_is_signed(xedd) && (immediateSize != 1)) + { + const int64_t immediateValue = xed_decoded_inst_get_signed_immediate(xedd); + + if (immediateValue >= 0) + sstream << immediateValue; // Don't zero extend + else + { + // I'm not proud of this switch statement... It was the product of a lot of pain. + switch (immediateSize) // For sign extentions + { + case 1: + sstream << (int8_t)immediateValue; + break; + case 2: + sstream << (int16_t)immediateValue; + break; + case 4: + sstream << (int32_t)immediateValue; + break; + default: + sstream << (int64_t)immediateValue; + } + } + + if (immediateSize == addrSize) + result.emplace_back(PossibleAddressToken, sstream.str(), immediateValue, immediateSize); + else + result.emplace_back(IntegerToken, sstream.str(), immediateValue, immediateSize); + } + else + { + const uint64_t immediateValue = xed_decoded_inst_get_unsigned_immediate(xedd); + sstream << immediateValue; + if (immediateSize == addrSize) + result.emplace_back(PossibleAddressToken, sstream.str(), immediateValue, immediateSize); + else + result.emplace_back(IntegerToken, sstream.str(), immediateValue, immediateSize); + } + break; + } + case XED_OPERAND_IMM1: // The ENTER instruction + { + stringstream sstream; + sstream << "0x" << hex; + if (m_disassembly_options.lowerCase) + sstream << nouppercase; + else + sstream << uppercase; + + sstream << (uint16_t)xed_decoded_inst_get_second_immediate(xedd); + result.emplace_back(IntegerToken, sstream.str(), xed_decoded_inst_get_second_immediate(xedd), 1); + break; + } + case XED_OPERAND_PTR: + { + stringstream sstream; + sstream << "0x" << hex; + if (m_disassembly_options.lowerCase) + sstream << nouppercase; + else + sstream << uppercase; + + sstream << xed_decoded_inst_get_branch_displacement(xedd); + result.emplace_back(PossibleAddressToken, sstream.str(), xed_decoded_inst_get_branch_displacement(xedd), 8); + break; + } + case XED_OPERAND_RELBR: + { + const int64_t relbr = xed_decoded_inst_get_branch_displacement(xedd) + addr + xed_decoded_inst_get_length(xedd); + + stringstream sstream; + if ((xed_decoded_inst_get_iclass(xedd) == XED_ICLASS_CALL_NEAR) && (relbr == (int64_t)(addr + xed_decoded_inst_get_length(xedd)))) + { + sstream << "$+" << xed_decoded_inst_get_length(xedd); + result.emplace_back(TextToken, sstream.str()); + break; + } + + sstream << "0x" << hex; + if (m_disassembly_options.lowerCase) + sstream << nouppercase; + else + sstream << uppercase; + + sstream << relbr; + result.emplace_back(CodeRelativeAddressToken, sstream.str(), relbr, 8); + break; + } + default: + { + if (m_disassembly_options.lowerCase) + result.emplace_back(TextToken, "unimplimented "); + else + result.emplace_back(TextToken, "UNIMPLIMENTED "); + } // default case of outer switch + } // outer switch + + // If there is another operand and it is visable, print delimiter + if ((opIndex != xed_inst_noperands(xi)-1) && + ((xed_operand_operand_visibility(xed_inst_operand(xi, opIndex+1)) == XED_OPVIS_EXPLICIT) || + (xed_operand_operand_visibility(xed_inst_operand(xi, opIndex+1)) == XED_OPVIS_IMPLICIT))) + result.emplace_back(OperandSeparatorToken, m_disassembly_options.separator); + } + + if (extra_index_operand != XED_REG_INVALID) + { + result.emplace_back(OperandSeparatorToken, m_disassembly_options.separator); + string reg = xed_reg_enum_t2str(extra_index_operand); + if (m_disassembly_options.lowerCase) + for (char& c : reg) + c = tolower(c); + result.emplace_back(RegisterToken, reg); + } +} + +void X86CommonArchitecture::GetOperandTextATT(const xed_decoded_inst_t* const xedd, const uint64_t addr, const size_t len, const xed_operand_values_t* const ov, const xed_inst_t* const xi, vector<InstructionTextToken>& result) const +{ + unsigned i,j; + unsigned noperands = xed_inst_noperands(xi); + + bool intel_way = false; + + if (xed_inst_get_attribute(xi, XED_ATTRIBUTE_ATT_OPERAND_ORDER_EXCEPTION)) + intel_way = true; + + // if (xed_decoded_inst_get_attribute(xedd, XED_ATTRIBUTE_INDEX_REG_IS_POINTER)) + // { + // for(j=0; j<noperands; ++j) + // { + // i = noperands - j - 1; // never intel_way + + // if(xed_operand_name(xed_inst_operand(xi,i)) == XED_OPERAND_MEM0) + // cout << "%" + xed_reg_enum_t2str(xed3_operand_get_index(xedd)); + // } + // } + + for(j=0; j<noperands; ++j) + { + if (intel_way) + i = j; + else + i = noperands - j - 1; + + const xed_operand_t* op = xed_inst_operand(xi, i); + const xed_operand_enum_t op_name = xed_operand_name(op); + + // XED's suppressed operands shouln't be represented in Intel syntax + if (xed_operand_operand_visibility(op) == XED_OPVIS_SUPPRESSED) + { + if ((xed_decoded_inst_get_category(xedd) == XED_CATEGORY_STRINGOP) && + (op_name == XED_OPERAND_MEM0 || op_name == XED_OPERAND_MEM1)) + { + if (op_name == XED_OPERAND_MEM1) + result.emplace_back(OperandSeparatorToken, m_disassembly_options.separator); + } + else + { + continue; + } + } + + switch(xed_operand_name(op)) + { + case XED_OPERAND_REG0: + case XED_OPERAND_REG1: + case XED_OPERAND_REG2: + case XED_OPERAND_REG3: + case XED_OPERAND_REG4: + case XED_OPERAND_REG5: + case XED_OPERAND_REG6: + case XED_OPERAND_REG7: + case XED_OPERAND_REG8: + { + string reg = "%"; + + const xed_reg_enum_t xedReg = xed_decoded_inst_get_reg(xedd, op_name); + if ((xedReg >= XED_REG_X87_FIRST) && (xedReg <= XED_REG_X87_LAST)) + { + reg += "ST"; + reg += ('0' + (xedReg-XED_REG_X87_FIRST)); + } + else + { + reg += xed_reg_enum_t2str(xedReg); + } + if (m_disassembly_options.lowerCase) + for (char& c : reg) + c = tolower(c); + result.emplace_back(RegisterToken, reg); + break; + } + case XED_OPERAND_AGEN: + case XED_OPERAND_MEM0: + { + GetAddressSizeToken(xed_decoded_inst_operand_length_bits(xedd, i) / 8, result, m_disassembly_options.lowerCase); + + if (m_disassembly_options.lowerCase) + result.emplace_back(TextToken, "ptr "); + else + result.emplace_back(TextToken, "PTR "); + result.emplace_back(TextToken, "["); + + // Segment + const xed_reg_enum_t seg = xed_decoded_inst_get_seg_reg(xedd, 0); + const bool validSegment = (seg != XED_REG_INVALID && !xed_operand_values_using_default_segment(ov, 0)); + if (validSegment) + { + string seg_str(xed_reg_enum_t2str(seg)); + seg_str = "%" + seg_str; + if (m_disassembly_options.lowerCase) + for (char& c : seg_str) + c = tolower(c); + result.emplace_back(RegisterToken, seg_str); + result.emplace_back(TextToken, ":"); + } + + bool started = false; + xed_reg_enum_t base = xed_decoded_inst_get_base_reg(xedd, 0); + + int64_t disp = xed_decoded_inst_get_memory_displacement(xedd, 0); + + if ((base != XED_REG_INVALID) && !((base == XED_REG_RIP) || (base == XED_REG_EIP) || (base == XED_REG_IP))) + { + string base_str(xed_reg_enum_t2str(base)); + base_str = "%" + base_str; + if (m_disassembly_options.lowerCase) + for (char& c : base_str) + c = tolower(c); + result.emplace_back(RegisterToken, base_str); + started = true; + } + else if ((base == XED_REG_RIP) || (base == XED_REG_EIP) || (base == XED_REG_IP)) + { + if (xed_operand_values_has_memory_displacement(ov)) + disp += addr + len; + else + disp = addr + len; + + stringstream sstream; + if (m_disassembly_options.lowerCase) + sstream << "0x" << hex << nouppercase << disp; + else + sstream << "0x" << hex << uppercase << disp; + + result.emplace_back(CodeRelativeAddressToken, sstream.str(), disp, GetAddressSize()); + + result.emplace_back(EndMemoryOperandToken, "]"); + break; + } + + const xed_reg_enum_t index = xed_decoded_inst_get_index_reg(xedd, 0); + if (index != XED_REG_INVALID) + { + if (started) + result.emplace_back(TextToken, "+"); + started = true; + + string index_str(xed_reg_enum_t2str(index)); + index_str = "%" + index_str; + if (m_disassembly_options.lowerCase) + for (char& c : index_str) + c = tolower(c); + + result.emplace_back(RegisterToken, index_str); + + const unsigned int scale = xed_decoded_inst_get_scale(xedd, 0); + if (scale != 1) + { + result.emplace_back(TextToken, "*"); + stringstream sstream; + sstream << scale; + result.emplace_back(IntegerToken, sstream.str(), scale, 1); + } + } + + const unsigned short disp_bytes = xed_decoded_inst_get_memory_displacement_width_bits(xedd, 0) / 8; + + if (xed_operand_values_has_memory_displacement(ov) && + ((disp != 0) || (!started && validSegment))) + { + stringstream sstream; + sstream << "0x" << hex; + if (m_disassembly_options.lowerCase) + sstream << nouppercase; + else + sstream << uppercase; + + if (started) + { + if (disp < 0) + { + result.emplace_back(TextToken, "-"); + disp = -disp; + } + else + result.emplace_back(TextToken, "+"); + + if (disp_bytes == 2) + sstream << (uint16_t)disp; + else if (disp_bytes == 4) + sstream << (uint32_t)disp; + else if (disp_bytes == 8) + sstream << (uint64_t)disp; + else + sstream << disp; + result.emplace_back(IntegerToken, sstream.str(), disp, disp_bytes); + } + else + { + sstream << disp; + + if (validSegment) + result.emplace_back(IntegerToken, sstream.str(), disp, GetAddressSize()); + else + result.emplace_back(PossibleAddressToken, sstream.str(), disp, GetAddressSize()); + } + } + else if (xed_operand_values_has_memory_displacement(ov) && + ((disp == 0) && (!started))) + { + result.emplace_back(IntegerToken, "0x0", disp, GetAddressSize()); + } + result.emplace_back(EndMemoryOperandToken, "]"); + + break; + } + + case XED_OPERAND_MEM1: + { + GetAddressSizeToken(xed_decoded_inst_operand_length_bits(xedd, i) / 8, result, m_disassembly_options.lowerCase); + + if (m_disassembly_options.lowerCase) + result.emplace_back(TextToken, "ptr "); + else + result.emplace_back(TextToken, "PTR "); + + // Segment + const xed_reg_enum_t seg = xed_decoded_inst_get_seg_reg(xedd, 1); + if (seg != XED_REG_INVALID && !xed_operand_values_using_default_segment(ov, 1)) + { + string seg_str(xed_reg_enum_t2str(seg)); + seg_str = "%" + seg_str; + if (m_disassembly_options.lowerCase) + for (char& c : seg_str) + c = tolower(c); + result.emplace_back(RegisterToken, seg_str); + + result.emplace_back(TextToken, ":"); + } + + result.emplace_back(TextToken, "["); + const xed_reg_enum_t base = xed_decoded_inst_get_base_reg(xedd, 1); + if (base != XED_REG_INVALID) + { + string base_str(xed_reg_enum_t2str(base)); + base_str = "%" + base_str; + if (m_disassembly_options.lowerCase) + for (char& c : base_str) + c = tolower(c); + result.emplace_back(RegisterToken, base_str); + } + result.emplace_back(EndMemoryOperandToken, "]"); + + break; + } + + case XED_OPERAND_IMM0: + { + const size_t addrSize = xed_decoded_inst_get_machine_mode_bits(xedd) / 8; + const unsigned int immediateSize = xed_decoded_inst_get_operand_width(xedd) / 8; + + stringstream sstream; + sstream << "$0x" << hex; + if (m_disassembly_options.lowerCase) + sstream << nouppercase; + else + sstream << uppercase; + + if (xed_decoded_inst_get_immediate_is_signed(xedd) && (immediateSize != 1)) + { + const int64_t immediateValue = xed_decoded_inst_get_signed_immediate(xedd); + + if (immediateValue >= 0) + sstream << immediateValue; // Don't zero extend + else + { + // I'm not proud of this switch statement... It was the product of a lot of pain. + switch (immediateSize) // For sign extentions + { + case 1: + sstream << (int8_t)immediateValue; + break; + case 2: + sstream << (int16_t)immediateValue; + break; + case 4: + sstream << (int32_t)immediateValue; + break; + default: + sstream << (int64_t)immediateValue; + } + } + + if (immediateSize == addrSize) + result.emplace_back(PossibleAddressToken, sstream.str(), immediateValue, immediateSize); + else + result.emplace_back(IntegerToken, sstream.str(), immediateValue, immediateSize); + } + else + { + const uint64_t immediateValue = xed_decoded_inst_get_unsigned_immediate(xedd); + sstream << immediateValue; + if (immediateSize == addrSize) + result.emplace_back(PossibleAddressToken, sstream.str(), immediateValue, immediateSize); + else + result.emplace_back(IntegerToken, sstream.str(), immediateValue, immediateSize); + } + break; + } + + case XED_OPERAND_IMM1: + { + stringstream sstream; + sstream << "$0x" << hex; + if (m_disassembly_options.lowerCase) + sstream << nouppercase; + else + sstream << uppercase; + + sstream << (uint16_t)xed_decoded_inst_get_second_immediate(xedd); + result.emplace_back(IntegerToken, sstream.str(), xed_decoded_inst_get_second_immediate(xedd), 1); + break; + } + + case XED_OPERAND_PTR: + { + stringstream sstream; + sstream << "$0x" << hex; + if (m_disassembly_options.lowerCase) + sstream << nouppercase; + else + sstream << uppercase; + + sstream << xed_decoded_inst_get_branch_displacement(xedd); + result.emplace_back(PossibleAddressToken, sstream.str(), xed_decoded_inst_get_branch_displacement(xedd), 8); + break; + + } + + case XED_OPERAND_RELBR: + { + const int64_t relbr = xed_decoded_inst_get_branch_displacement(xedd) + addr + xed_decoded_inst_get_length(xedd); + + stringstream sstream; + sstream << "$0x" << hex; + if (m_disassembly_options.lowerCase) + sstream << nouppercase; + else + sstream << uppercase; + + sstream << relbr; + result.emplace_back(CodeRelativeAddressToken, sstream.str(), relbr, 8); + break; + } + + default: + { + result.emplace_back(TextToken, "unimplimented"); + } // default case of outer switch + } // outer switch + + // If there is another operand and it is visable, print delimiter + if (intel_way) + { + if ((i != (size_t)xed_inst_noperands(xi)-1) && + ((xed_operand_operand_visibility(xed_inst_operand(xi, i+1)) == XED_OPVIS_EXPLICIT) || + (xed_operand_operand_visibility(xed_inst_operand(xi, i+1)) == XED_OPVIS_IMPLICIT))) + { + result.emplace_back(OperandSeparatorToken, m_disassembly_options.separator); + } + } + else + { + if ((i != 0) && + ((xed_operand_operand_visibility(xed_inst_operand(xi, noperands - j - 2)) == XED_OPVIS_EXPLICIT) || + (xed_operand_operand_visibility(xed_inst_operand(xi, noperands - j - 2)) == XED_OPVIS_IMPLICIT))) + { + result.emplace_back(OperandSeparatorToken, m_disassembly_options.separator); + } + } + + } +} + +void X86CommonArchitecture::GetOperandTextXED(const xed_decoded_inst_t* const xedd, const uint64_t addr, const size_t, const xed_operand_values_t* const, const xed_inst_t* const, vector<InstructionTextToken>& result) const +{ + char out_buffer[100]; + if (!xed_format_context(XED_SYNTAX_XED, xedd, out_buffer, 100, addr, 0, 0)) + { + LogError("Can't disassemble"); + return; + } + + // Find space + int i = 0; + for (; ; ++i) + if ((out_buffer[i] == ' ') && (out_buffer[i+1] != ' ')) + break; + + // Convert To String + string outstring(out_buffer+i); + + result.emplace_back(TextToken, outstring); +} + +void X86CommonArchitecture::GetOperandText(const xed_decoded_inst_t* const xedd, const uint64_t addr, const size_t len, const xed_operand_values_t* const ov, const xed_inst_t* const xi, vector<InstructionTextToken>& result) const +{ + switch (m_disassembly_options.df) + { + case DF_INTEL: + GetOperandTextIntel(xedd, addr, len, ov, xi, result); + break; + + case DF_BN_INTEL: + GetOperandTextBNIntel(xedd, addr, len, ov, xi, result); + break; + + case DF_ATT: + GetOperandTextATT(xedd, addr, len, ov, xi, result); + break; + + case DF_XED: + GetOperandTextXED(xedd, addr, len, ov, xi, result); + break; + + default: + LogError("Invalid Disassembly Flavor"); + } +} + +X86CommonArchitecture::X86CommonArchitecture(const string& name, size_t bits): Architecture(name), m_bits(bits) +{ + Ref<Settings> settings = Settings::Instance(); + const bool lowercase = settings->Get<bool>("arch.x86.disassembly.lowercase"); + const string flavor = settings->Get<string>("arch.x86.disassembly.syntax"); + const string separator = settings->Get<string>("arch.x86.disassembly.separator"); + + DISASSEMBLY_FLAVOR_ENUM flavorEnum; + + if (flavor == "BN_INTEL") + flavorEnum = DF_BN_INTEL; + else if (flavor == "INTEL") + flavorEnum = DF_INTEL; + else if (flavor == "AT&T") + flavorEnum = DF_ATT; + // else if (flavor == "XED") + // flavorEnum = DF_XED; + else + flavorEnum = DF_BN_INTEL; + + m_disassembly_options = DISASSEMBLY_OPTIONS(flavorEnum, lowercase, separator); +} + +BNEndianness X86CommonArchitecture::GetEndianness() const +{ + return LittleEndian; +} + +vector<uint32_t> X86CommonArchitecture::GetGlobalRegisters() +{ + return vector< uint32_t> { + XED_REG_CS, + XED_REG_DS, + XED_REG_ES, + XED_REG_SS, + XED_REG_FS, + XED_REG_GS, + XED_REG_FSBASE, + XED_REG_GSBASE, + XED_REG_FLAGS, + XED_REG_EFLAGS, + XED_REG_RFLAGS + }; +} + +vector<uint32_t> X86CommonArchitecture::GetSystemRegisters() +{ + return vector< uint32_t> { + XED_REG_BND0, + XED_REG_BND1, + XED_REG_BND2, + XED_REG_BND3, + + XED_REG_CR0, + XED_REG_CR1, + XED_REG_CR2, + XED_REG_CR3, + XED_REG_CR4, + XED_REG_CR5, + XED_REG_CR6, + XED_REG_CR7, + XED_REG_CR8, + XED_REG_CR9, + XED_REG_CR10, + XED_REG_CR11, + XED_REG_CR12, + XED_REG_CR13, + XED_REG_CR14, + XED_REG_CR15, + + XED_REG_DR0, + XED_REG_DR1, + XED_REG_DR2, + XED_REG_DR3, + XED_REG_DR4, + XED_REG_DR5, + XED_REG_DR6, + XED_REG_DR7, + + XED_REG_GDTR, + XED_REG_LDTR, + XED_REG_IDTR, + XED_REG_TR, + + XED_REG_TSC, + XED_REG_TSCAUX, + XED_REG_MSRS + }; +} + +bool X86CommonArchitecture::GetInstructionInfo(const uint8_t* data, uint64_t addr, size_t maxLen, InstructionInfo& result) +{ + xed_decoded_inst_t xedd; + switch (m_bits) + { + case 64: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LONG_64, XED_ADDRESS_WIDTH_64b); + break; + case 32: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_32, XED_ADDRESS_WIDTH_32b); + break; + case 16: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_16, XED_ADDRESS_WIDTH_16b); + break; + default: + LogError("Invalid Processor Mode"); + return false; + } + if (!Decode(data, maxLen, &xedd)) + return false; + + SetInstructionInfoForInstruction(addr, result, &xedd); + return true; +} + + +bool X86CommonArchitecture::GetInstructionText(const uint8_t* data, uint64_t addr, size_t& len, vector<InstructionTextToken>& result) +{ + xed_decoded_inst_t xedd; + switch (m_bits) + { + case 64: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LONG_64, XED_ADDRESS_WIDTH_64b); + break; + case 32: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_32, XED_ADDRESS_WIDTH_32b); + break; + case 16: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_16, XED_ADDRESS_WIDTH_16b); + break; + default: + LogError("Invalid Processor Mode"); + return false; + } + + if (Decode(data, len, &xedd)) + { + len = xed_decoded_inst_get_length(&xedd); + + // If there's no instruction + const xed_inst_t* xi = xed_decoded_inst_inst(&xedd); + if (!xi) + return false; + + // Opcodes + const xed_operand_values_t* const ov = xed_decoded_inst_operands_const(&xedd); + unsigned short instruction_name_length = GetInstructionOpcode(&xedd, ov, result); + + // Padding + GetInstructionPadding(instruction_name_length, result); + + // Operands + GetOperandText(&xedd, addr, len, ov, xi, result); + + return true; + } + + return false; +} + +bool X86CommonArchitecture::GetInstructionLowLevelIL(const uint8_t* data, uint64_t addr, size_t& len, LowLevelILFunction& il) +{ + xed_decoded_inst_t xedd; + switch (m_bits) + { + case 64: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LONG_64, XED_ADDRESS_WIDTH_64b); + break; + case 32: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_32, XED_ADDRESS_WIDTH_32b); + break; + case 16: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_16, XED_ADDRESS_WIDTH_16b); + break; + default: + LogError("Invalid Processor Mode"); + return false; + } + if (!Decode(data, len, &xedd)) + { + il.AddInstruction(il.Undefined()); + return false; + } + + len = xed_decoded_inst_get_length(&xedd); + return GetLowLevelILForInstruction(this, addr, il, &xedd); +} + +size_t X86CommonArchitecture::GetFlagWriteLowLevelIL(BNLowLevelILOperation op, size_t size, uint32_t flagWriteType, + uint32_t flag, BNRegisterOrConstant* operands, size_t operandCount, LowLevelILFunction& il) +{ + switch (op) + { + case LLIL_NEG: + switch (flag) + { + case IL_FLAG_O: + return il.AddExpr(LLIL_CMP_E, size, 0, il.GetExprForRegisterOrConstantOperation(op, size, operands, operandCount), + il.AddExpr(LLIL_CONST, size, 0, (1LL << ((size * 8) - 1)))); + } + break; + case LLIL_XOR: + case LLIL_AND: + case LLIL_OR: + switch (flag) + { + case IL_FLAG_C: + case IL_FLAG_O: + return il.Const(0, 0); + case IL_FLAG_A: + return il.Undefined(); + } + break; + case LLIL_MULU_DP: + switch (flag) + { + case IL_FLAG_C: + case IL_FLAG_O: + return il.AddExpr(LLIL_CMP_NE, size * 2, 0, il.AddExpr(LLIL_LSR, size * 2, 0, + il.GetExprForRegisterOrConstantOperation(op, size, operands, operandCount), + il.AddExpr(LLIL_CONST, 1, 0, size * 8)), il.AddExpr(LLIL_CONST, size * 2, 0, 0)); + } + default: + break; + } + + if (flagWriteType == IL_FLAGWRITE_VCOMI) + { + switch (flag) + { + case IL_FLAG_S: + case IL_FLAG_O: + case IL_FLAG_A: + return il.Const(0, 0); + default: + break; + } + } + if (((flagWriteType == IL_FLAGWRITE_X87COM) || (flagWriteType == IL_FLAGWRITE_X87C1Z)) && (flag == IL_FLAG_C1)) + return il.Const(0, 0); + return Architecture::GetFlagWriteLowLevelIL(op, size, flagWriteType, flag, operands, operandCount, il); +} + +size_t X86CommonArchitecture::GetSemanticFlagGroupLowLevelIL(uint32_t semGroup, LowLevelILFunction& il) +{ + switch (semGroup) + { + case IL_FLAG_GROUP_E: + return GetFlagConditionLowLevelIL(LLFC_E, IL_FLAG_CLASS_INT, il); + case IL_FLAG_GROUP_NE: + return GetFlagConditionLowLevelIL(LLFC_NE, IL_FLAG_CLASS_INT, il); + case IL_FLAG_GROUP_LT: + return GetFlagConditionLowLevelIL(LLFC_ULT, IL_FLAG_CLASS_INT, il); + case IL_FLAG_GROUP_LE: + return GetFlagConditionLowLevelIL(LLFC_ULE, IL_FLAG_CLASS_INT, il); + case IL_FLAG_GROUP_GE: + return GetFlagConditionLowLevelIL(LLFC_UGE, IL_FLAG_CLASS_INT, il); + case IL_FLAG_GROUP_GT: + return GetFlagConditionLowLevelIL(LLFC_UGT, IL_FLAG_CLASS_INT, il); + case IL_FLAG_GROUP_PE: + return il.Flag(IL_FLAG_P); + case IL_FLAG_GROUP_PO: + return il.Not(0, il.Flag(IL_FLAG_P)); + default: + return il.Unimplemented(); + } +} + +string X86CommonArchitecture::GetRegisterName(uint32_t reg) +{ + string reg_str = ""; + if (m_disassembly_options.df == DF_ATT) + reg_str += "%"; + + if ((reg >= REG_X87_r(0)) && (reg <= REG_X87_r(7))) + reg_str += "X87_R" + to_string(reg - REG_X87_r(0)); + else if (reg == REG_X87_TOP) + reg_str += "TOP"; + else if ((reg >= XED_REG_X87_FIRST) && (reg <= XED_REG_X87_LAST)) + reg_str += "ST" + to_string(reg - XED_REG_X87_FIRST); + else + reg_str += xed_reg_enum_t2str((xed_reg_enum_t)reg); + + if (m_disassembly_options.lowerCase) + for (char& c : reg_str) + c = tolower(c); + + return reg_str; +} + +string X86CommonArchitecture::GetFlagName(uint32_t flag) +{ + char result[32]; + switch (flag) + { + case IL_FLAG_C: + return "c"; + case IL_FLAG_P: + return "p"; + case IL_FLAG_A: + return "a"; + case IL_FLAG_Z: + return "z"; + case IL_FLAG_S: + return "s"; + case IL_FLAG_D: + return "d"; + case IL_FLAG_O: + return "o"; + case IL_FLAG_C0: + return "c0"; + case IL_FLAG_C1: + return "c1"; + case IL_FLAG_C2: + return "c2"; + case IL_FLAG_C3: + return "c3"; + default: + snprintf(result, sizeof(result), "flag%" PRIu32, flag); + return result; + } +} + +vector<uint32_t> X86CommonArchitecture::GetAllFlags() +{ + return vector<uint32_t> {IL_FLAG_C, IL_FLAG_P, IL_FLAG_A, IL_FLAG_Z, IL_FLAG_S, IL_FLAG_D, IL_FLAG_O, + IL_FLAG_C0, IL_FLAG_C1, IL_FLAG_C2, IL_FLAG_C3}; +} + +string X86CommonArchitecture::GetSemanticFlagClassName(uint32_t semClass) +{ + switch (semClass) + { + case IL_FLAG_CLASS_X87COM: + return "x87com"; + case IL_FLAG_CLASS_X87COMI: + return "x87comi"; + case IL_FLAG_CLASS_VCOMI: + return "vcomi"; + default: + return ""; + } +} + +vector<uint32_t> X86CommonArchitecture::GetAllSemanticFlagClasses() +{ + return vector<uint32_t> {IL_FLAG_CLASS_X87COM, IL_FLAG_CLASS_X87COMI, IL_FLAG_CLASS_VCOMI}; +} + +string X86CommonArchitecture::GetSemanticFlagGroupName(uint32_t semGroup) +{ + switch (semGroup) + { + case IL_FLAG_GROUP_E: + return "e"; + case IL_FLAG_GROUP_NE: + return "ne"; + case IL_FLAG_GROUP_LT: + return "lt"; + case IL_FLAG_GROUP_LE: + return "le"; + case IL_FLAG_GROUP_GE: + return "ge"; + case IL_FLAG_GROUP_GT: + return "gt"; + case IL_FLAG_GROUP_PE: + return "pe"; + case IL_FLAG_GROUP_PO: + return "po"; + default: + return ""; + } +} + +vector<uint32_t> X86CommonArchitecture::GetAllSemanticFlagGroups() +{ + return vector<uint32_t> {IL_FLAG_GROUP_E, IL_FLAG_GROUP_NE, IL_FLAG_GROUP_LT, IL_FLAG_GROUP_LE, + IL_FLAG_GROUP_GE, IL_FLAG_GROUP_GT, IL_FLAG_GROUP_PE, IL_FLAG_GROUP_PO}; +} + +string X86CommonArchitecture::GetFlagWriteTypeName(uint32_t flags) +{ + switch (flags) + { + case IL_FLAGWRITE_ALL: + return "*"; + case IL_FLAGWRITE_NOCARRY: + return "!c"; + case IL_FLAGWRITE_CO: + return "co"; + case IL_FLAGWRITE_X87COM: + return "x87com"; + case IL_FLAGWRITE_X87COMI: + return "x87comi"; + case IL_FLAGWRITE_X87C1Z: + return "x87c1z"; + case IL_FLAGWRITE_X87RND: + return "x87rnd"; + case IL_FLAGWRITE_VCOMI: + return "vcomi"; + default: + return ""; + } +} + +uint32_t X86CommonArchitecture::GetSemanticClassForFlagWriteType(uint32_t writeType) +{ + switch (writeType) + { + case IL_FLAGWRITE_X87COM: + case IL_FLAGWRITE_X87C1Z: + case IL_FLAGWRITE_X87RND: + return IL_FLAG_CLASS_X87COM; + case IL_FLAGWRITE_X87COMI: + return IL_FLAG_CLASS_X87COMI; + case IL_FLAGWRITE_VCOMI: + return IL_FLAG_CLASS_VCOMI; + default: + return IL_FLAG_CLASS_INT; + } +} + +vector<uint32_t> X86CommonArchitecture::GetAllFlagWriteTypes() +{ + return vector<uint32_t> {IL_FLAGWRITE_ALL, IL_FLAGWRITE_NOCARRY, IL_FLAGWRITE_CO, + IL_FLAGWRITE_X87COM, IL_FLAGWRITE_X87COMI, IL_FLAGWRITE_X87C1Z, IL_FLAGWRITE_X87RND, + IL_FLAGWRITE_VCOMI}; +} + +BNFlagRole X86CommonArchitecture::GetFlagRole(uint32_t flag, uint32_t semClass) +{ + switch (semClass) + { + case IL_FLAG_CLASS_X87COM: + switch (flag) + { + case IL_FLAG_C0: + return CarryFlagRole; + case IL_FLAG_C2: + return UnorderedFlagRole; + case IL_FLAG_C3: + return ZeroFlagRole; + default: + return SpecialFlagRole; + } + + case IL_FLAG_CLASS_VCOMI: + switch (flag) + { + case IL_FLAG_C: + return CarryFlagRole; + case IL_FLAG_Z: + return ZeroFlagRole; + case IL_FLAG_P: + return UnorderedFlagRole; + default: + // O, A, S cleared + return SpecialFlagRole; + } + + default: + break; + } + + switch (flag) + { + case IL_FLAG_C: + return CarryFlagRole; + case IL_FLAG_P: + if (semClass == IL_FLAG_CLASS_X87COMI) + return UnorderedFlagRole; + return EvenParityFlagRole; + case IL_FLAG_A: + return HalfCarryFlagRole; + case IL_FLAG_Z: + return ZeroFlagRole; + case IL_FLAG_S: + return NegativeSignFlagRole; + case IL_FLAG_O: + return OverflowFlagRole; + default: + return SpecialFlagRole; + } +} + +vector<uint32_t> X86CommonArchitecture::GetFlagsRequiredForFlagCondition(BNLowLevelILFlagCondition cond, uint32_t semClass) +{ + if (semClass == IL_FLAG_CLASS_X87COM) + { + switch (cond) + { + case LLFC_FE: + case LLFC_FNE: + return vector<uint32_t>{ IL_FLAG_C3 }; + case LLFC_FLT: + case LLFC_FGE: + return vector<uint32_t>{ IL_FLAG_C0 }; + case LLFC_FLE: + case LLFC_FGT: + return vector<uint32_t>{ IL_FLAG_C0, IL_FLAG_C3 }; + case LLFC_FO: + case LLFC_FUO: + return vector<uint32_t>{ IL_FLAG_C2 }; + default: + return vector<uint32_t>(); + } + } + + switch (cond) + { + case LLFC_E: + case LLFC_NE: + case LLFC_FE: + case LLFC_FNE: + return vector<uint32_t>{ IL_FLAG_Z }; + case LLFC_SLT: + case LLFC_SGE: + return vector<uint32_t>{ IL_FLAG_S, IL_FLAG_O }; + case LLFC_ULT: + case LLFC_UGE: + case LLFC_FLT: + case LLFC_FGE: + return vector<uint32_t>{ IL_FLAG_C }; + case LLFC_SLE: + case LLFC_SGT: + return vector<uint32_t>{ IL_FLAG_Z, IL_FLAG_S, IL_FLAG_O }; + case LLFC_ULE: + case LLFC_UGT: + case LLFC_FLE: + case LLFC_FGT: + return vector<uint32_t>{ IL_FLAG_C, IL_FLAG_Z }; + case LLFC_NEG: + case LLFC_POS: + return vector<uint32_t>{ IL_FLAG_S }; + case LLFC_O: + case LLFC_NO: + return vector<uint32_t>{ IL_FLAG_O }; + case LLFC_FO: + case LLFC_FUO: + return vector<uint32_t>{ IL_FLAG_P }; + default: + return vector<uint32_t>(); + } +} + +vector<uint32_t> X86CommonArchitecture::GetFlagsRequiredForSemanticFlagGroup(uint32_t semGroup) +{ + switch (semGroup) + { + case IL_FLAG_GROUP_E: + case IL_FLAG_GROUP_NE: + return vector<uint32_t>{ IL_FLAG_Z }; + case IL_FLAG_GROUP_LT: + case IL_FLAG_GROUP_GE: + return vector<uint32_t>{ IL_FLAG_C }; + case IL_FLAG_GROUP_LE: + case IL_FLAG_GROUP_GT: + return vector<uint32_t>{ IL_FLAG_C, IL_FLAG_Z }; + case IL_FLAG_GROUP_PE: + case IL_FLAG_GROUP_PO: + return vector<uint32_t>{ IL_FLAG_P }; + default: + return vector<uint32_t>(); + } +} + +map<uint32_t, BNLowLevelILFlagCondition> X86CommonArchitecture::GetFlagConditionsForSemanticFlagGroup(uint32_t semGroup) +{ + switch (semGroup) + { + case IL_FLAG_GROUP_E: + return map<uint32_t, BNLowLevelILFlagCondition> { + {IL_FLAG_CLASS_INT, LLFC_E}, + {IL_FLAG_CLASS_X87COMI, LLFC_FE}, + {IL_FLAG_CLASS_VCOMI, LLFC_FE}, + }; + case IL_FLAG_GROUP_NE: + return map<uint32_t, BNLowLevelILFlagCondition> { + {IL_FLAG_CLASS_INT, LLFC_NE}, + {IL_FLAG_CLASS_X87COMI, LLFC_FNE}, + {IL_FLAG_CLASS_VCOMI, LLFC_FNE}, + }; + case IL_FLAG_GROUP_LT: + return map<uint32_t, BNLowLevelILFlagCondition> { + {IL_FLAG_CLASS_INT, LLFC_ULT}, + {IL_FLAG_CLASS_X87COMI, LLFC_FLT}, + {IL_FLAG_CLASS_VCOMI, LLFC_FLT}, + }; + case IL_FLAG_GROUP_LE: + return map<uint32_t, BNLowLevelILFlagCondition> { + {IL_FLAG_CLASS_INT, LLFC_ULE}, + {IL_FLAG_CLASS_X87COMI, LLFC_FLE}, + {IL_FLAG_CLASS_VCOMI, LLFC_FLE}, + }; + case IL_FLAG_GROUP_GE: + return map<uint32_t, BNLowLevelILFlagCondition> { + {IL_FLAG_CLASS_INT, LLFC_UGE}, + {IL_FLAG_CLASS_X87COMI, LLFC_FGE}, + {IL_FLAG_CLASS_VCOMI, LLFC_FGE}, + }; + case IL_FLAG_GROUP_GT: + return map<uint32_t, BNLowLevelILFlagCondition> { + {IL_FLAG_CLASS_INT, LLFC_UGT}, + {IL_FLAG_CLASS_X87COMI, LLFC_FGT}, + {IL_FLAG_CLASS_VCOMI, LLFC_FGT}, + }; + case IL_FLAG_GROUP_PE: + return map<uint32_t, BNLowLevelILFlagCondition> { + {IL_FLAG_CLASS_X87COMI, LLFC_FUO}, + {IL_FLAG_CLASS_VCOMI, LLFC_FUO}, + }; + case IL_FLAG_GROUP_PO: + return map<uint32_t, BNLowLevelILFlagCondition> { + {IL_FLAG_CLASS_X87COMI, LLFC_FO}, + {IL_FLAG_CLASS_VCOMI, LLFC_FO}, + }; + default: + return map<uint32_t, BNLowLevelILFlagCondition>(); + } +} + +vector<uint32_t> X86CommonArchitecture::GetFlagsWrittenByFlagWriteType(uint32_t writeType) +{ + switch (writeType) + { + case IL_FLAGWRITE_ALL: + return vector<uint32_t>{ IL_FLAG_C, IL_FLAG_P, IL_FLAG_A, IL_FLAG_Z, IL_FLAG_S, IL_FLAG_O }; + case IL_FLAGWRITE_NOCARRY: + return vector<uint32_t>{ IL_FLAG_P, IL_FLAG_A, IL_FLAG_Z, IL_FLAG_S, IL_FLAG_O }; + case IL_FLAGWRITE_CO: + return vector<uint32_t>{ IL_FLAG_C, IL_FLAG_O }; + case IL_FLAGWRITE_X87COM: + return vector<uint32_t>{ IL_FLAG_C0, IL_FLAG_C1, IL_FLAG_C2, IL_FLAG_C3 }; + case IL_FLAGWRITE_X87COMI: + return vector<uint32_t>{ IL_FLAG_C, IL_FLAG_Z, IL_FLAG_P }; + case IL_FLAGWRITE_X87C1Z: + case IL_FLAGWRITE_X87RND: + return vector<uint32_t>{ IL_FLAG_C1 }; + case IL_FLAGWRITE_VCOMI: + return vector<uint32_t>{ IL_FLAG_C, IL_FLAG_P, IL_FLAG_A, IL_FLAG_Z, IL_FLAG_S, IL_FLAG_O }; + default: + return vector<uint32_t>(); + } +} + +string X86CommonArchitecture::GetRegisterStackName(uint32_t regStack) +{ + if (regStack == REG_STACK_X87) + return "x87"; + return ""; +} + +vector<uint32_t> X86CommonArchitecture::GetAllRegisterStacks() +{ + return vector<uint32_t>{REG_STACK_X87}; +} + +BNRegisterStackInfo X86CommonArchitecture::GetRegisterStackInfo(uint32_t regStack) +{ + if (regStack == REG_STACK_X87) + { + BNRegisterStackInfo result; + result.firstStorageReg = REG_X87_r(0); + result.storageCount = 8; + result.firstTopRelativeReg = XED_REG_ST0; + result.topRelativeCount = 8; + result.stackTopReg = REG_X87_TOP; + return result; + } + return Architecture::GetRegisterStackInfo(regStack); +} + +bool X86CommonArchitecture::CanAssemble() +{ + return true; +} + +bool X86CommonArchitecture::Assemble(const string& code, uint64_t addr, DataBuffer& result, string& errors) +{ + string finalCode; + + if (GetAddressSizeBits() == 32) + finalCode = "\tsection .text align=1\n\tbits 32\n"; + else + finalCode = "\tsection .text align=1\n\tbits 64\n"; + + char orgStr[32]; + snprintf(orgStr, sizeof(orgStr), "\torg 0x%" PRIx64 "\n", addr); + finalCode += orgStr; + + finalCode += "%line 0 input\n"; + finalCode += code; + + Ref<TemporaryFile> inputFile = new TemporaryFile(finalCode); + Ref<TemporaryFile> outputFile = new TemporaryFile(); + if (!inputFile->IsValid()) + { + errors = "Unable to create temporary file for input\n"; + return false; + } + if (!outputFile->IsValid()) + { + errors = "Unable to create temporary file for output\n"; + return false; + } + + #ifdef WIN32 + string yasmPath = GetPathRelativeToBundledPluginDirectory("yasm.exe"); + #else + string yasmPath = GetPathRelativeToBundledPluginDirectory("yasm"); + #endif + + string inputPath = inputFile->GetPath(); + string outputPath = outputFile->GetPath(); + + vector<string> args = vector<string> { yasmPath, "-fbin", "-w", "-Worphan-labels", "-Werror", "-o", outputPath, inputPath }; + + string output; + bool ok = ExecuteWorkerProcess(yasmPath, args, DataBuffer(), + output, // _binary_ stdout is ignored + errors, // _text_ stderr becomes the error message + false, // yasm stdout is ignored (stay with default: no newline translate) + true // yasm stderr is known to be text (translate newlines) + ); + + if(!ok) + { + /* when there was a problem creating the yasm process + OR the yasm process return code was nonzero */ + if(errors.size() == 0) + { + errors = yasmPath + " returned nonzero\n"; + } + } + else + { + result = outputFile->GetContents(); /* assembled bytes */ + if(result.GetLength() == 0) + { + errors = "Empty output from assembler\n"; + ok = false; + } + } + + return ok; +} + +bool X86CommonArchitecture::IsNeverBranchPatchAvailable(const uint8_t* data, uint64_t, size_t len) +{ + xed_decoded_inst_t xedd; + switch (m_bits) + { + case 64: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LONG_64, XED_ADDRESS_WIDTH_64b); + break; + case 32: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_32, XED_ADDRESS_WIDTH_32b); + break; + case 16: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_16, XED_ADDRESS_WIDTH_16b); + break; + default: + LogError("Invalid Processor Mode"); + return false; + } + + if (!Decode(data, len, &xedd)) + return false; + return IsConditionalJump(&xedd); +} + +bool X86CommonArchitecture::IsAlwaysBranchPatchAvailable(const uint8_t* data, uint64_t, size_t len) +{ + xed_decoded_inst_t xedd; + switch (m_bits) + { + case 64: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LONG_64, XED_ADDRESS_WIDTH_64b); + break; + case 32: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_32, XED_ADDRESS_WIDTH_32b); + break; + case 16: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_16, XED_ADDRESS_WIDTH_16b); + break; + default: + LogError("Invalid Processor Mode"); + return false; + } + if (!Decode(data, len, &xedd)) + return false; + return IsConditionalJump(&xedd); +} + +bool X86CommonArchitecture::IsInvertBranchPatchAvailable(const uint8_t* data, uint64_t, size_t len) +{ + xed_decoded_inst_t xedd; + switch (m_bits) + { + case 64: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LONG_64, XED_ADDRESS_WIDTH_64b); + break; + case 32: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_32, XED_ADDRESS_WIDTH_32b); + break; + case 16: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_16, XED_ADDRESS_WIDTH_16b); + break; + default: + LogError("Invalid Processor Mode"); + return false; + } + if (!Decode(data, len, &xedd)) + return false; + return IsConditionalJump(&xedd); +} + +bool X86CommonArchitecture::IsSkipAndReturnZeroPatchAvailable(const uint8_t* data, uint64_t, size_t len) +{ + xed_decoded_inst_t xedd; + switch (m_bits) + { + case 64: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LONG_64, XED_ADDRESS_WIDTH_64b); + break; + case 32: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_32, XED_ADDRESS_WIDTH_32b); + break; + case 16: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_16, XED_ADDRESS_WIDTH_16b); + break; + default: + LogError("Invalid Processor Mode"); + return false; + } + if (!Decode(data, len, &xedd)) + return false; + return xed_decoded_inst_get_category(&xedd) == XED_CATEGORY_CALL; +} + +bool X86CommonArchitecture::IsSkipAndReturnValuePatchAvailable(const uint8_t* data, uint64_t, size_t len) +{ + xed_decoded_inst_t xedd; + switch (m_bits) + { + case 64: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LONG_64, XED_ADDRESS_WIDTH_64b); + break; + case 32: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_32, XED_ADDRESS_WIDTH_32b); + break; + case 16: + xed_decoded_inst_set_mode(&xedd, XED_MACHINE_MODE_LEGACY_16, XED_ADDRESS_WIDTH_16b); + break; + default: + LogError("Invalid Processor Mode"); + return false; + } + if (!Decode(data, len, &xedd)) + return false; + return (xed_decoded_inst_get_category(&xedd) == XED_CATEGORY_CALL) && (xed_decoded_inst_get_length(&xedd) >= 5); +} + +bool X86CommonArchitecture::ConvertToNop(uint8_t* data, uint64_t, size_t len) +{ + memset(data, 0x90, len); + return true; +} + +size_t X86CommonArchitecture::FindOpcodeOffset(const uint8_t* data, size_t len) +{ + size_t i; + for (i = 0; i < len; i++) + { + if ((data[0] >= 0x26) && (data[0] <= 0x3e) && ((data[0] & 7) == 6)) // Segment prefix + continue; + if ((data[0] >= 0x64) && (data[0] <= 0x67)) // FS/GS prefix and size overrides + continue; + if (data[0] == 0xf0) // Lock prefix + continue; + if ((data[0] == 0xf2) || (data[0] == 0xf3)) // Rep prefixes + continue; + if ((GetAddressSizeBits() == 64) && (data[0] >= 0x40) && (data[0] <= 0x4f)) // REX prefix + continue; + break; + } + return i; +} + +bool X86CommonArchitecture::AlwaysBranch(uint8_t* data, uint64_t, size_t len) +{ + size_t i = FindOpcodeOffset(data, len); + if (i >= len) + return false; + + if ((len - i) == 2) + { + data[i] = 0xeb; + return true; + } + + if ((len - i) == 5) + { + data[i] = 0xe9; + return true; + } + + if ((len - i) > 5) + { + memmove(&data[(len - i) - 5], data, i); + memset(data, 0x90, (len - i) - 5); + data[len - 5] = 0xe9; + return true; + } + + return false; +} + +bool X86CommonArchitecture::InvertBranch(uint8_t* data, uint64_t, size_t len) +{ + size_t i = FindOpcodeOffset(data, len); + if (i >= len) + return false; + + if (data[i] == 0x0f) + { + if ((i + 1) >= len) + return false; + data[i + 1] ^= 1; + return true; + } + + data[i] ^= 1; + return true; +} + +bool X86CommonArchitecture::SkipAndReturnValue(uint8_t* data, uint64_t, size_t len, uint64_t value) +{ + if (len >= 5) + { + data[0] = 0xb8; + *(uint32_t*)&data[1] = (uint32_t)value; + memset(&data[5], 0x90, len - 5); + return true; + } + + if ((value == 0) && (len >= 2)) + { + // xor eax, eax + data[0] = 0x31; + data[1] = 0xc0; + memset(&data[2], 0x90, len - 2); + return true; + } + + return false; +} + + +class X86Architecture: public X86CommonArchitecture +{ +protected: + virtual size_t GetAddressSize() const override + { + return 4; + } + +public: + X86Architecture(): X86CommonArchitecture("x86", 32) + {} + + virtual vector<uint32_t> GetFullWidthRegisters() override + { + return vector<uint32_t>{ + // 16-Bit + XED_REG_CS, XED_REG_DS, XED_REG_ES, XED_REG_SS, XED_REG_FS, XED_REG_GS, XED_REG_FSBASE, XED_REG_GSBASE, // 16+ + + // 32-Bit + XED_REG_EIP, // 32+ + XED_REG_ESP, XED_REG_EBP, XED_REG_ESI, XED_REG_EDI, // 32+ + XED_REG_EFLAGS, // 32+ + + XED_REG_EAX, XED_REG_ECX, XED_REG_EDX, XED_REG_EBX, // 32+ + + XED_REG_TSC, XED_REG_TSCAUX, // 32+ (32 on 32, 64 on 64) Timestamp Counters + XED_REG_TR, // 16+ (16 on 16, 32 on 32, 64 on 64) Task Register + + XED_REG_CR0, XED_REG_CR1, XED_REG_CR2, XED_REG_CR3, XED_REG_CR4, XED_REG_CR5, XED_REG_CR6, XED_REG_CR7, XED_REG_CR8, XED_REG_CR9, XED_REG_CR10, XED_REG_CR11, XED_REG_CR12, XED_REG_CR13, XED_REG_CR14, XED_REG_CR15, // 32+ (32 on 32, 64 on 64) Control Registers + XED_REG_DR0, XED_REG_DR1, XED_REG_DR2, XED_REG_DR3, XED_REG_DR4, XED_REG_DR5, XED_REG_DR6, XED_REG_DR7, // 32+ (starting in later revisions of 32) (32 on 32, 64 on 64) Debug registers + + XED_REG_MXCSR, // 32+ SSE (MMX) Control Reg (32 on 32, 64 on 64) + + // x87 FPU related + REG_X87_TOP, XED_REG_X87CONTROL, XED_REG_X87STATUS, XED_REG_X87TAG, XED_REG_X87OPCODE, XED_REG_X87LASTCS, + XED_REG_X87LASTDS, XED_REG_X87LASTIP, XED_REG_X87LASTDP, XED_REG_X87PUSH, XED_REG_X87POP, XED_REG_X87POP2, + + // 48-Bit (All 32+) + XED_REG_GDTR, // Global Descriptor Table Register + XED_REG_LDTR, // Local Descriptor Table Register + XED_REG_IDTR, // Interrupt Descriptor Table Register + + // 64-Bit + XED_REG_XCR0, // 32+ (64 on 32, 64 on 64) + + XED_REG_MSRS, + + // 80-Bit + XED_REG_ST0, XED_REG_ST1, XED_REG_ST2, XED_REG_ST3, XED_REG_ST4, XED_REG_ST5, XED_REG_ST6, XED_REG_ST7, // 32+ Floating point + REG_X87_r(0), REG_X87_r(1), REG_X87_r(2), REG_X87_r(3), REG_X87_r(4), REG_X87_r(5), REG_X87_r(6), REG_X87_r(7), + + // 128-Bit + XED_REG_XMM0, XED_REG_XMM1, XED_REG_XMM2, XED_REG_XMM3, XED_REG_XMM4, XED_REG_XMM5, XED_REG_XMM6, XED_REG_XMM7, // 32+ SSE + }; + } + + virtual vector<uint32_t> GetAllRegisters() override + { + return vector<uint32_t>{ + // 8-Bit + XED_REG_AH, XED_REG_CH, XED_REG_DH, XED_REG_BH, XED_REG_AL, XED_REG_CL, XED_REG_DL, XED_REG_BL, // 16+ + + // 16-Bit + XED_REG_IP, // 16+ + XED_REG_CS, XED_REG_DS, XED_REG_ES, XED_REG_SS, XED_REG_FS, XED_REG_GS, XED_REG_FSBASE, XED_REG_GSBASE, // 16+ + XED_REG_SP, XED_REG_BP, XED_REG_SI, XED_REG_DI, // 16+ + XED_REG_FLAGS, // 16+ + + XED_REG_AX, XED_REG_CX, XED_REG_DX, XED_REG_BX, // 16+ + + REG_X87_TOP, // 32+ + XED_REG_X87CONTROL, XED_REG_X87STATUS, XED_REG_X87TAG, XED_REG_X87PUSH, XED_REG_X87POP, + XED_REG_X87POP2, XED_REG_X87OPCODE, XED_REG_X87LASTCS, XED_REG_X87LASTIP, XED_REG_X87LASTDS, XED_REG_X87LASTDP, + + // 32-Bit + XED_REG_EIP, // 32+ + XED_REG_ESP, XED_REG_EBP, XED_REG_ESI, XED_REG_EDI, // 32+ + XED_REG_EFLAGS, // 32+ + + XED_REG_EAX, XED_REG_ECX, XED_REG_EDX, XED_REG_EBX, // 32+ + + XED_REG_TSC, XED_REG_TSCAUX, // 32+ (32 on 32, 64 on 64) Timestamp Counters + XED_REG_TR, // 16+ (16 on 16, 32 on 32, 64 on 64) Task Register + + XED_REG_CR0, XED_REG_CR1, XED_REG_CR2, XED_REG_CR3, XED_REG_CR4, XED_REG_CR5, XED_REG_CR6, XED_REG_CR7, XED_REG_CR8, XED_REG_CR9, XED_REG_CR10, XED_REG_CR11, XED_REG_CR12, XED_REG_CR13, XED_REG_CR14, XED_REG_CR15, // 32+ (32 on 32, 64 on 64) Control Registers + XED_REG_DR0, XED_REG_DR1, XED_REG_DR2, XED_REG_DR3, XED_REG_DR4, XED_REG_DR5, XED_REG_DR6, XED_REG_DR7, // 32+ (starting in later revisions of 32) (32 on 32, 64 on 64) Debug registers + + XED_REG_MXCSR, // 32+ SSE (MMX) Control Reg (32 on 32, 64 on 64) + + // 48-Bit (All 32+) + XED_REG_GDTR, // Global Descriptor Table Register + XED_REG_LDTR, // Local Descriptor Table Register + XED_REG_IDTR, // Interrupt Descriptor Table Register + + // 64-Bit + XED_REG_MMX0, XED_REG_MMX1, XED_REG_MMX2, XED_REG_MMX3, XED_REG_MMX4, XED_REG_MMX5, XED_REG_MMX6, XED_REG_MMX7, // 32+ Floating point, bottom of st regs + XED_REG_XCR0, // 32+ (64 on 32, 64 on 64) + + XED_REG_RFLAGS, + + XED_REG_MSRS, + + // 80-Bit + XED_REG_ST0, XED_REG_ST1, XED_REG_ST2, XED_REG_ST3, XED_REG_ST4, XED_REG_ST5, XED_REG_ST6, XED_REG_ST7, // 32+ Floating point + REG_X87_r(0), REG_X87_r(1), REG_X87_r(2), REG_X87_r(3), REG_X87_r(4), REG_X87_r(5), REG_X87_r(6), REG_X87_r(7), + + // 128-Bit + XED_REG_XMM0, XED_REG_XMM1, XED_REG_XMM2, XED_REG_XMM3, XED_REG_XMM4, XED_REG_XMM5, XED_REG_XMM6, XED_REG_XMM7, // 32+ SSE + + XED_REG_BND0, XED_REG_BND1, XED_REG_BND2, XED_REG_BND3, + }; + } + + virtual BNRegisterInfo GetRegisterInfo(const uint32_t reg) override + { + switch (reg) + { + // 8-Bit + case XED_REG_AH: return RegisterInfo(XED_REG_EAX, 1, 1); + case XED_REG_CH: return RegisterInfo(XED_REG_ECX, 1, 1); + case XED_REG_DH: return RegisterInfo(XED_REG_EDX, 1, 1); + case XED_REG_BH: return RegisterInfo(XED_REG_EBX, 1, 1); + case XED_REG_AL: return RegisterInfo(XED_REG_EAX, 0, 1); + case XED_REG_CL: return RegisterInfo(XED_REG_ECX, 0, 1); + case XED_REG_DL: return RegisterInfo(XED_REG_EDX, 0, 1); + case XED_REG_BL: return RegisterInfo(XED_REG_EBX, 0, 1); + + // 16-Bit + case XED_REG_IP: return RegisterInfo(XED_REG_EIP, 0, 2); + + case XED_REG_CS: return RegisterInfo(XED_REG_CS, 0, 2); + case XED_REG_DS: return RegisterInfo(XED_REG_DS, 0, 2); + case XED_REG_ES: return RegisterInfo(XED_REG_ES, 0, 2); + case XED_REG_SS: return RegisterInfo(XED_REG_SS, 0, 2); + case XED_REG_FS: return RegisterInfo(XED_REG_FS, 0, 2); + case XED_REG_GS: return RegisterInfo(XED_REG_GS, 0, 2); + + case XED_REG_SP: return RegisterInfo(XED_REG_ESP, 0, 2); + case XED_REG_BP: return RegisterInfo(XED_REG_EBP, 0, 2); + case XED_REG_SI: return RegisterInfo(XED_REG_ESI, 0, 2); + case XED_REG_DI: return RegisterInfo(XED_REG_EDI, 0, 2); + + case XED_REG_FLAGS: return RegisterInfo(XED_REG_EFLAGS, 0, 2); + + case XED_REG_AX: return RegisterInfo(XED_REG_EAX, 0, 2); + case XED_REG_CX: return RegisterInfo(XED_REG_ECX, 0, 2); + case XED_REG_DX: return RegisterInfo(XED_REG_EDX, 0, 2); + case XED_REG_BX: return RegisterInfo(XED_REG_EBX, 0, 2); + + // 32-Bit + case XED_REG_EIP: return RegisterInfo(XED_REG_EIP, 0, 4); + case XED_REG_FSBASE: return RegisterInfo(XED_REG_FSBASE, 0, 4); + case XED_REG_GSBASE: return RegisterInfo(XED_REG_GSBASE, 0, 4); + + case XED_REG_ESP: return RegisterInfo(XED_REG_ESP, 0, 4); + case XED_REG_EBP: return RegisterInfo(XED_REG_EBP, 0, 4); + case XED_REG_ESI: return RegisterInfo(XED_REG_ESI, 0, 4); + case XED_REG_EDI: return RegisterInfo(XED_REG_EDI, 0, 4); + + case XED_REG_EFLAGS: return RegisterInfo(XED_REG_EFLAGS, 0, 4); + + case XED_REG_EAX: return RegisterInfo(XED_REG_EAX, 0, 4); + case XED_REG_ECX: return RegisterInfo(XED_REG_ECX, 0, 4); + case XED_REG_EDX: return RegisterInfo(XED_REG_EDX, 0, 4); + case XED_REG_EBX: return RegisterInfo(XED_REG_EBX, 0, 4); + + case XED_REG_TSC: return RegisterInfo(XED_REG_TSC, 0, 4); + case XED_REG_TSCAUX: return RegisterInfo(XED_REG_TSCAUX, 0, 4); + + case XED_REG_TR: return RegisterInfo(XED_REG_TR, 0, 4); + + case REG_X87_TOP: return RegisterInfo((xed_reg_enum_t)REG_X87_TOP, 0, 2); + case XED_REG_X87CONTROL: return RegisterInfo(XED_REG_X87CONTROL, 0, 2); + case XED_REG_X87STATUS: return RegisterInfo(XED_REG_X87STATUS, 0, 2); + case XED_REG_X87TAG: return RegisterInfo(XED_REG_X87TAG, 0, 2); + case XED_REG_X87OPCODE: return RegisterInfo(XED_REG_X87OPCODE, 0, 2); + case XED_REG_X87LASTCS: return RegisterInfo(XED_REG_X87LASTCS, 0, 2); + case XED_REG_X87LASTDS: return RegisterInfo(XED_REG_X87LASTDS, 0, 2); + case XED_REG_X87LASTIP: return RegisterInfo(XED_REG_X87LASTIP, 0, 4); + case XED_REG_X87LASTDP: return RegisterInfo(XED_REG_X87LASTDP, 0, 4); + case XED_REG_X87PUSH: return RegisterInfo(XED_REG_X87PUSH, 0, 4); + case XED_REG_X87POP: return RegisterInfo(XED_REG_X87POP, 0, 4); + case XED_REG_X87POP2: return RegisterInfo(XED_REG_X87POP2, 0, 4); + + case XED_REG_CR0: return RegisterInfo(XED_REG_CR0, 0, 4); + case XED_REG_CR1: return RegisterInfo(XED_REG_CR1, 0, 4); + case XED_REG_CR2: return RegisterInfo(XED_REG_CR2, 0, 4); + case XED_REG_CR3: return RegisterInfo(XED_REG_CR3, 0, 4); + case XED_REG_CR4: return RegisterInfo(XED_REG_CR4, 0, 4); + case XED_REG_CR5: return RegisterInfo(XED_REG_CR5, 0, 4); + case XED_REG_CR6: return RegisterInfo(XED_REG_CR6, 0, 4); + case XED_REG_CR7: return RegisterInfo(XED_REG_CR7, 0, 4); + case XED_REG_CR8: return RegisterInfo(XED_REG_CR8, 0, 4); + case XED_REG_CR9: return RegisterInfo(XED_REG_CR9, 0, 4); + case XED_REG_CR10: return RegisterInfo(XED_REG_CR10, 0, 4); + case XED_REG_CR11: return RegisterInfo(XED_REG_CR11, 0, 4); + case XED_REG_CR12: return RegisterInfo(XED_REG_CR12, 0, 4); + case XED_REG_CR13: return RegisterInfo(XED_REG_CR13, 0, 4); + case XED_REG_CR14: return RegisterInfo(XED_REG_CR14, 0, 4); + case XED_REG_CR15: return RegisterInfo(XED_REG_CR15, 0, 4); + + case XED_REG_DR0: return RegisterInfo(XED_REG_DR0, 0, 4); + case XED_REG_DR1: return RegisterInfo(XED_REG_DR1, 0, 4); + case XED_REG_DR2: return RegisterInfo(XED_REG_DR2, 0, 4); + case XED_REG_DR3: return RegisterInfo(XED_REG_DR3, 0, 4); + case XED_REG_DR4: return RegisterInfo(XED_REG_DR4, 0, 4); + case XED_REG_DR5: return RegisterInfo(XED_REG_DR5, 0, 4); + case XED_REG_DR6: return RegisterInfo(XED_REG_DR6, 0, 4); + case XED_REG_DR7: return RegisterInfo(XED_REG_DR7, 0, 4); + + case XED_REG_MXCSR: return RegisterInfo(XED_REG_MXCSR, 0, 4); + + // 48-Bit + case XED_REG_GDTR: return RegisterInfo(XED_REG_GDTR, 0, 6); + case XED_REG_LDTR: return RegisterInfo(XED_REG_LDTR, 0, 6); + case XED_REG_IDTR: return RegisterInfo(XED_REG_IDTR, 0, 6); + + // 64-Bit + case XED_REG_MMX0: return RegisterInfo(XED_REG_ST0, 0, 8); + case XED_REG_MMX1: return RegisterInfo(XED_REG_ST1, 0, 8); + case XED_REG_MMX2: return RegisterInfo(XED_REG_ST2, 0, 8); + case XED_REG_MMX3: return RegisterInfo(XED_REG_ST3, 0, 8); + case XED_REG_MMX4: return RegisterInfo(XED_REG_ST4, 0, 8); + case XED_REG_MMX5: return RegisterInfo(XED_REG_ST5, 0, 8); + case XED_REG_MMX6: return RegisterInfo(XED_REG_ST6, 0, 8); + case XED_REG_MMX7: return RegisterInfo(XED_REG_ST7, 0, 8); + + case XED_REG_XCR0: return RegisterInfo(XED_REG_XCR0, 0, 8); + + case XED_REG_RFLAGS: return RegisterInfo(XED_REG_RFLAGS, 0, 8); + + case XED_REG_MSRS: return RegisterInfo(XED_REG_MSRS, 0, 8); + + // 80-Bit + case XED_REG_ST0: return RegisterInfo(XED_REG_ST0, 0, 10); + case XED_REG_ST1: return RegisterInfo(XED_REG_ST1, 0, 10); + case XED_REG_ST2: return RegisterInfo(XED_REG_ST2, 0, 10); + case XED_REG_ST3: return RegisterInfo(XED_REG_ST3, 0, 10); + case XED_REG_ST4: return RegisterInfo(XED_REG_ST4, 0, 10); + case XED_REG_ST5: return RegisterInfo(XED_REG_ST5, 0, 10); + case XED_REG_ST6: return RegisterInfo(XED_REG_ST6, 0, 10); + case XED_REG_ST7: return RegisterInfo(XED_REG_ST7, 0, 10); + + case REG_X87_r(0): return RegisterInfo((xed_reg_enum_t)REG_X87_r(0), 0, 10); + case REG_X87_r(1): return RegisterInfo((xed_reg_enum_t)REG_X87_r(1), 0, 10); + case REG_X87_r(2): return RegisterInfo((xed_reg_enum_t)REG_X87_r(2), 0, 10); + case REG_X87_r(3): return RegisterInfo((xed_reg_enum_t)REG_X87_r(3), 0, 10); + case REG_X87_r(4): return RegisterInfo((xed_reg_enum_t)REG_X87_r(4), 0, 10); + case REG_X87_r(5): return RegisterInfo((xed_reg_enum_t)REG_X87_r(5), 0, 10); + case REG_X87_r(6): return RegisterInfo((xed_reg_enum_t)REG_X87_r(6), 0, 10); + case REG_X87_r(7): return RegisterInfo((xed_reg_enum_t)REG_X87_r(7), 0, 10); + + // 128-Bit + case XED_REG_XMM0: return RegisterInfo(XED_REG_XMM0, 0, 16); + case XED_REG_XMM1: return RegisterInfo(XED_REG_XMM1, 0, 16); + case XED_REG_XMM2: return RegisterInfo(XED_REG_XMM2, 0, 16); + case XED_REG_XMM3: return RegisterInfo(XED_REG_XMM3, 0, 16); + case XED_REG_XMM4: return RegisterInfo(XED_REG_XMM4, 0, 16); + case XED_REG_XMM5: return RegisterInfo(XED_REG_XMM5, 0, 16); + case XED_REG_XMM6: return RegisterInfo(XED_REG_XMM6, 0, 16); + case XED_REG_XMM7: return RegisterInfo(XED_REG_XMM7, 0, 16); + + case XED_REG_BND0: return RegisterInfo(XED_REG_BND0, 0, 16); + case XED_REG_BND1: return RegisterInfo(XED_REG_BND1, 0, 16); + case XED_REG_BND2: return RegisterInfo(XED_REG_BND2, 0, 16); + case XED_REG_BND3: return RegisterInfo(XED_REG_BND3, 0, 16); + + default: + return RegisterInfo(XED_REG_INVALID, 0, 0); + } + } + + virtual uint32_t GetStackPointerRegister() override + { + return XED_REG_ESP; + } +}; + + +class X16Architecture: public X86CommonArchitecture +{ +protected: + virtual size_t GetAddressSize() const override + { + return 2; + } + +public: + X16Architecture(): X86CommonArchitecture("x86_16", 16) + {} + + virtual vector<uint32_t> GetFullWidthRegisters() override + { + return vector<uint32_t> { + // 16-Bit + XED_REG_IP, // 16+ + XED_REG_CS, XED_REG_DS, XED_REG_ES, XED_REG_SS, XED_REG_FS, XED_REG_GS, XED_REG_FSBASE, XED_REG_GSBASE, // 16+ + XED_REG_SP, XED_REG_BP, XED_REG_SI, XED_REG_DI, // 16+ + XED_REG_FLAGS, // 16+ + + XED_REG_AX, XED_REG_CX, XED_REG_DX, XED_REG_BX, // 16+ + + XED_REG_TR, // 16+ (16 on 16, 32 on 32, 64 on 64) Task Register + }; + } + + virtual vector<uint32_t> GetAllRegisters() override + { + return vector<uint32_t>{ + // 8-Bit + XED_REG_AH, XED_REG_CH, XED_REG_DH, XED_REG_BH, XED_REG_AL, XED_REG_CL, XED_REG_DL, XED_REG_BL, // 16+ + + // 16-Bit + XED_REG_IP, // 16+ + XED_REG_CS, XED_REG_DS, XED_REG_ES, XED_REG_SS, XED_REG_FS, XED_REG_GS, XED_REG_FSBASE, XED_REG_GSBASE, // 16+ + XED_REG_SP, XED_REG_BP, XED_REG_SI, XED_REG_DI, // 16+ + XED_REG_FLAGS, // 16+ + + XED_REG_AX, XED_REG_CX, XED_REG_DX, XED_REG_BX, // 16+ + + XED_REG_TR, // 16+ (16 on 16, 32 on 32, 64 on 64) Task Register + }; + } + + virtual BNRegisterInfo GetRegisterInfo(const uint32_t reg) override + { + switch (reg) + { + // 8-Bit + case XED_REG_AH: return RegisterInfo(XED_REG_AX, 1, 1); + case XED_REG_CH: return RegisterInfo(XED_REG_CX, 1, 1); + case XED_REG_DH: return RegisterInfo(XED_REG_DX, 1, 1); + case XED_REG_BH: return RegisterInfo(XED_REG_BX, 1, 1); + case XED_REG_AL: return RegisterInfo(XED_REG_AX, 0, 1); + case XED_REG_CL: return RegisterInfo(XED_REG_CX, 0, 1); + case XED_REG_DL: return RegisterInfo(XED_REG_DX, 0, 1); + case XED_REG_BL: return RegisterInfo(XED_REG_BX, 0, 1); + + // 16-Bit + case XED_REG_IP: return RegisterInfo(XED_REG_IP, 0, 2); + case XED_REG_CS: return RegisterInfo(XED_REG_CS, 0, 2); + case XED_REG_DS: return RegisterInfo(XED_REG_DS, 0, 2); + case XED_REG_ES: return RegisterInfo(XED_REG_ES, 0, 2); + case XED_REG_SS: return RegisterInfo(XED_REG_SS, 0, 2); + case XED_REG_FS: return RegisterInfo(XED_REG_FS, 0, 2); + case XED_REG_GS: return RegisterInfo(XED_REG_GS, 0, 2); + case XED_REG_FSBASE: return RegisterInfo(XED_REG_FSBASE, 0, 2); + case XED_REG_GSBASE: return RegisterInfo(XED_REG_GSBASE, 0, 2); + case XED_REG_SP: return RegisterInfo(XED_REG_SP, 0, 2); + case XED_REG_BP: return RegisterInfo(XED_REG_BP, 0, 2); + case XED_REG_SI: return RegisterInfo(XED_REG_SI, 0, 2); + case XED_REG_DI: return RegisterInfo(XED_REG_DI, 0, 2); + case XED_REG_FLAGS: return RegisterInfo(XED_REG_FLAGS, 0, 2); + case XED_REG_AX: return RegisterInfo(XED_REG_AX, 0, 2); + case XED_REG_CX: return RegisterInfo(XED_REG_CX, 0, 2); + case XED_REG_DX: return RegisterInfo(XED_REG_DX, 0, 2); + case XED_REG_BX: return RegisterInfo(XED_REG_BX, 0, 2); + case XED_REG_TR: return RegisterInfo(XED_REG_TR, 0, 2); + + default: return RegisterInfo(XED_REG_INVALID, 0, 0); + } + } + + virtual uint32_t GetStackPointerRegister() override + { + return XED_REG_SP; + } +}; + + +class X64Architecture: public X86CommonArchitecture +{ +protected: + virtual size_t GetAddressSize() const override + { + return 8; + } + +public: + X64Architecture(): X86CommonArchitecture("x86_64", 64) + {} + + virtual vector<uint32_t> GetFullWidthRegisters() override + { + return vector< uint32_t> { + // 16-Bit + XED_REG_CS, XED_REG_DS, XED_REG_ES, XED_REG_SS, XED_REG_FS, XED_REG_GS, XED_REG_FSBASE, XED_REG_GSBASE, // 16+ + XED_REG_SP, XED_REG_BP, XED_REG_SI, XED_REG_DI, // 16+ + + // x87 FPU related + REG_X87_TOP, XED_REG_X87CONTROL, XED_REG_X87STATUS, XED_REG_X87TAG, XED_REG_X87OPCODE, XED_REG_X87LASTCS, + XED_REG_X87LASTDS, XED_REG_X87LASTIP, XED_REG_X87LASTDP, XED_REG_X87PUSH, XED_REG_X87POP, XED_REG_X87POP2, + + // 48-Bit (All 32+) + XED_REG_GDTR, // Global Descriptor Table Register + XED_REG_LDTR, // Local Descriptor Table Register + XED_REG_IDTR, // Interrupt Descriptor Table Register + + // 64-Bit + XED_REG_TR, // 16+ (16 on 16, 32 on 32, 64 on 64) Task Register + XED_REG_TSC, XED_REG_TSCAUX, // 32+ (32 on 32, 64 on 64) Timestamp Counters + XED_REG_RIP, // 64+ + XED_REG_RSP, XED_REG_RBP, XED_REG_RSI, XED_REG_RDI, // 64+ + XED_REG_RFLAGS, // 64+ + XED_REG_MXCSR, // 32+ SSE (MMX) Control Reg (32 on 32, 64 on 64) + XED_REG_XCR0, // 32+ (64 on 32, 64 on 64) + XED_REG_SSP, // 64+ Shadow Stack Reg + + XED_REG_RAX, XED_REG_RCX, XED_REG_RDX, XED_REG_RBX, // 64+ + XED_REG_R8, XED_REG_R9, XED_REG_R10, XED_REG_R11, XED_REG_R12, XED_REG_R13, XED_REG_R14, XED_REG_R15, // 64+ + + XED_REG_BNDCFGU, XED_REG_BNDSTATUS, // 64 briefly. MPX control registers + XED_REG_K0, XED_REG_K1, XED_REG_K2, XED_REG_K3, XED_REG_K4, XED_REG_K5, XED_REG_K6, XED_REG_K7, // 64+ AVX bit-masking registers (also not confident in size) + + XED_REG_MSRS, + + XED_REG_CR0, XED_REG_CR1, XED_REG_CR2, XED_REG_CR3, XED_REG_CR4, XED_REG_CR5, XED_REG_CR6, XED_REG_CR7, XED_REG_CR8, XED_REG_CR9, XED_REG_CR10, XED_REG_CR11, XED_REG_CR12, XED_REG_CR13, XED_REG_CR14, XED_REG_CR15, // 32+ (32 on 32, 64 on 64) Control Registers + XED_REG_DR0, XED_REG_DR1, XED_REG_DR2, XED_REG_DR3, XED_REG_DR4, XED_REG_DR5, XED_REG_DR6, XED_REG_DR7, // 32+ (starting in later revisions of 32) (32 on 32, 64 on 64) Debug registers + + // 80-Bit + XED_REG_ST0, XED_REG_ST1, XED_REG_ST2, XED_REG_ST3, XED_REG_ST4, XED_REG_ST5, XED_REG_ST6, XED_REG_ST7, // 32+ Floating point + REG_X87_r(0), REG_X87_r(1), REG_X87_r(2), REG_X87_r(3), REG_X87_r(4), REG_X87_r(5), REG_X87_r(6), REG_X87_r(7), + + // 128-Bit + XED_REG_BND0, XED_REG_BND1, XED_REG_BND2, XED_REG_BND3, // 64 briefly. MPX registers + + // 512-Bit + XED_REG_ZMM0, XED_REG_ZMM1, XED_REG_ZMM2, XED_REG_ZMM3, XED_REG_ZMM4, XED_REG_ZMM5, XED_REG_ZMM6, XED_REG_ZMM7, XED_REG_ZMM8, XED_REG_ZMM9, XED_REG_ZMM10, XED_REG_ZMM11, XED_REG_ZMM12, XED_REG_ZMM13, XED_REG_ZMM14, XED_REG_ZMM15, XED_REG_ZMM16, XED_REG_ZMM17, XED_REG_ZMM18, XED_REG_ZMM19, XED_REG_ZMM20, XED_REG_ZMM21, XED_REG_ZMM22, XED_REG_ZMM23, XED_REG_ZMM24, XED_REG_ZMM25, XED_REG_ZMM26, XED_REG_ZMM27, XED_REG_ZMM28, XED_REG_ZMM29, XED_REG_ZMM30, XED_REG_ZMM31 // 64+ AVX + }; + } + + virtual vector<uint32_t> GetAllRegisters() override + { + return vector< uint32_t> { + // 8-Bit + XED_REG_AH, XED_REG_CH, XED_REG_DH, XED_REG_BH, XED_REG_AL, XED_REG_CL, XED_REG_DL, XED_REG_BL, // 16+ + XED_REG_SPL, XED_REG_BPL, XED_REG_SIL, XED_REG_DIL, // 64+ + XED_REG_R8B, XED_REG_R9B, XED_REG_R10B, XED_REG_R11B, XED_REG_R12B, XED_REG_R13B, XED_REG_R14B, XED_REG_R15B, // 64+ + + // 16-Bit + XED_REG_IP, // 16+ + XED_REG_CS, XED_REG_DS, XED_REG_ES, XED_REG_SS, XED_REG_FS, XED_REG_GS, XED_REG_FSBASE, XED_REG_GSBASE, // 16+ + XED_REG_SP, XED_REG_BP, XED_REG_SI, XED_REG_DI, // 16+ + XED_REG_FLAGS, // 16+ + + REG_X87_TOP, // 32+ + XED_REG_X87CONTROL, XED_REG_X87STATUS, XED_REG_X87TAG, XED_REG_X87PUSH, XED_REG_X87POP, + XED_REG_X87POP2, XED_REG_X87OPCODE, XED_REG_X87LASTCS, XED_REG_X87LASTIP, XED_REG_X87LASTDS, XED_REG_X87LASTDP, + + XED_REG_AX, XED_REG_CX, XED_REG_DX, XED_REG_BX, // 16+ + XED_REG_R8W, XED_REG_R9W, XED_REG_R10W, XED_REG_R11W, XED_REG_R12W, XED_REG_R13W, XED_REG_R14W, XED_REG_R15W, // 64+ + + // 32-Bit + XED_REG_EIP, // 32+ + XED_REG_ESP, XED_REG_EBP, XED_REG_ESI, XED_REG_EDI, // 32+ + XED_REG_EFLAGS, // 32+ + + XED_REG_EAX, XED_REG_ECX, XED_REG_EDX, XED_REG_EBX, // 32+ + XED_REG_R8D, XED_REG_R9D, XED_REG_R10D, XED_REG_R11D, XED_REG_R12D, XED_REG_R13D, XED_REG_R14D, XED_REG_R15D, // 64+ + + // 48-Bit (All 32+) + XED_REG_GDTR, // Global Descriptor Table Register + XED_REG_LDTR, // Local Descriptor Table Register + XED_REG_IDTR, // Interrupt Descriptor Table Register + + // 64-Bit + XED_REG_TR, // 16+ (16 on 16, 32 on 32, 64 on 64) Task Register + XED_REG_TSC, XED_REG_TSCAUX, // 32+ (32 on 32, 64 on 64) Timestamp Counters + XED_REG_MMX0, XED_REG_MMX1, XED_REG_MMX2, XED_REG_MMX3, XED_REG_MMX4, XED_REG_MMX5, XED_REG_MMX6, XED_REG_MMX7, // 32+ Floating point, bottom of st regs + XED_REG_RIP, // 64+ + XED_REG_RSP, XED_REG_RBP, XED_REG_RSI, XED_REG_RDI, // 64+ + XED_REG_RFLAGS, // 64+ + XED_REG_MXCSR, // 32+ SSE (MMX) Control Reg (32 on 32, 64 on 64) + XED_REG_XCR0, // 32+ (64 on 32, 64 on 64) + XED_REG_SSP, // 64+ Shadow Stack Reg + + XED_REG_RAX, XED_REG_RCX, XED_REG_RDX, XED_REG_RBX, // 64+ + XED_REG_R8, XED_REG_R9, XED_REG_R10, XED_REG_R11, XED_REG_R12, XED_REG_R13, XED_REG_R14, XED_REG_R15, // 64+ + + XED_REG_BNDCFGU, XED_REG_BNDSTATUS, // 64 briefly. MPX control registers + XED_REG_K0, XED_REG_K1, XED_REG_K2, XED_REG_K3, XED_REG_K4, XED_REG_K5, XED_REG_K6, XED_REG_K7, // 64+ AVX bit-masking registers (also not confident in size) + + XED_REG_MSRS, + + XED_REG_CR0, XED_REG_CR1, XED_REG_CR2, XED_REG_CR3, XED_REG_CR4, XED_REG_CR5, XED_REG_CR6, XED_REG_CR7, XED_REG_CR8, XED_REG_CR9, XED_REG_CR10, XED_REG_CR11, XED_REG_CR12, XED_REG_CR13, XED_REG_CR14, XED_REG_CR15, // 32+ (32 on 32, 64 on 64) Control Registers + XED_REG_DR0, XED_REG_DR1, XED_REG_DR2, XED_REG_DR3, XED_REG_DR4, XED_REG_DR5, XED_REG_DR6, XED_REG_DR7, // 32+ (starting in later revisions of 32) (32 on 32, 64 on 64) Debug registers + + // 80-Bit + XED_REG_ST0, XED_REG_ST1, XED_REG_ST2, XED_REG_ST3, XED_REG_ST4, XED_REG_ST5, XED_REG_ST6, XED_REG_ST7, // 32+ Floating point + REG_X87_r(0), REG_X87_r(1), REG_X87_r(2), REG_X87_r(3), REG_X87_r(4), REG_X87_r(5), REG_X87_r(6), REG_X87_r(7), + + // 128-Bit + XED_REG_XMM0, XED_REG_XMM1, XED_REG_XMM2, XED_REG_XMM3, XED_REG_XMM4, XED_REG_XMM5, XED_REG_XMM6, XED_REG_XMM7, // 32+ SSE + XED_REG_XMM8, XED_REG_XMM9, XED_REG_XMM10, XED_REG_XMM11, XED_REG_XMM12, XED_REG_XMM13, XED_REG_XMM14, XED_REG_XMM15, // 64+ SSE + XED_REG_XMM16, XED_REG_XMM17, XED_REG_XMM18, XED_REG_XMM19, XED_REG_XMM20, XED_REG_XMM21, XED_REG_XMM22, XED_REG_XMM23, XED_REG_XMM24, XED_REG_XMM25, XED_REG_XMM26, XED_REG_XMM27, XED_REG_XMM28, XED_REG_XMM29, XED_REG_XMM30, XED_REG_XMM31, // 64+ AVX + XED_REG_BND0, XED_REG_BND1, XED_REG_BND2, XED_REG_BND3, // 64 briefly. MPX registers + + // 256-Bit + XED_REG_YMM0, XED_REG_YMM1, XED_REG_YMM2, XED_REG_YMM3, XED_REG_YMM4, XED_REG_YMM5, XED_REG_YMM6, XED_REG_YMM7, XED_REG_YMM8, XED_REG_YMM9, XED_REG_YMM10, XED_REG_YMM11, XED_REG_YMM12, XED_REG_YMM13, XED_REG_YMM14, XED_REG_YMM15, XED_REG_YMM16, XED_REG_YMM17, XED_REG_YMM18, XED_REG_YMM19, XED_REG_YMM20, XED_REG_YMM21, XED_REG_YMM22, XED_REG_YMM23, XED_REG_YMM24, XED_REG_YMM25, XED_REG_YMM26, XED_REG_YMM27, XED_REG_YMM28, XED_REG_YMM29, XED_REG_YMM30, XED_REG_YMM31, // 64+ AVX + + // 512-Bit + XED_REG_ZMM0, XED_REG_ZMM1, XED_REG_ZMM2, XED_REG_ZMM3, XED_REG_ZMM4, XED_REG_ZMM5, XED_REG_ZMM6, XED_REG_ZMM7, XED_REG_ZMM8, XED_REG_ZMM9, XED_REG_ZMM10, XED_REG_ZMM11, XED_REG_ZMM12, XED_REG_ZMM13, XED_REG_ZMM14, XED_REG_ZMM15, XED_REG_ZMM16, XED_REG_ZMM17, XED_REG_ZMM18, XED_REG_ZMM19, XED_REG_ZMM20, XED_REG_ZMM21, XED_REG_ZMM22, XED_REG_ZMM23, XED_REG_ZMM24, XED_REG_ZMM25, XED_REG_ZMM26, XED_REG_ZMM27, XED_REG_ZMM28, XED_REG_ZMM29, XED_REG_ZMM30, XED_REG_ZMM31 // 64+ AVX + }; + } + + virtual BNRegisterInfo GetRegisterInfo(const uint32_t reg) override + { + switch (reg) + { + // 8-Bit + case XED_REG_AH: return RegisterInfo(XED_REG_RAX, 1, 1); + case XED_REG_CH: return RegisterInfo(XED_REG_RCX, 1, 1); + case XED_REG_DH: return RegisterInfo(XED_REG_RDX, 1, 1); + case XED_REG_BH: return RegisterInfo(XED_REG_RBX, 1, 1); + case XED_REG_AL: return RegisterInfo(XED_REG_RAX, 0, 1); + case XED_REG_CL: return RegisterInfo(XED_REG_RCX, 0, 1); + case XED_REG_DL: return RegisterInfo(XED_REG_RDX, 0, 1); + case XED_REG_BL: return RegisterInfo(XED_REG_RBX, 0, 1); + + case XED_REG_SPL: return RegisterInfo(XED_REG_RSP, 0, 1); + case XED_REG_BPL: return RegisterInfo(XED_REG_RBP, 0, 1); + case XED_REG_SIL: return RegisterInfo(XED_REG_RSI, 0, 1); + case XED_REG_DIL: return RegisterInfo(XED_REG_RDI, 0, 1); + + case XED_REG_R8B: return RegisterInfo(XED_REG_R8, 0, 1); + case XED_REG_R9B: return RegisterInfo(XED_REG_R9, 0, 1); + case XED_REG_R10B: return RegisterInfo(XED_REG_R10, 0, 1); + case XED_REG_R11B: return RegisterInfo(XED_REG_R11, 0, 1); + case XED_REG_R12B: return RegisterInfo(XED_REG_R12, 0, 1); + case XED_REG_R13B: return RegisterInfo(XED_REG_R13, 0, 1); + case XED_REG_R14B: return RegisterInfo(XED_REG_R14, 0, 1); + case XED_REG_R15B: return RegisterInfo(XED_REG_R15, 0, 1); + + // 16-Bit + case XED_REG_IP: return RegisterInfo(XED_REG_RIP, 0, 2); + + case XED_REG_CS: return RegisterInfo(XED_REG_CS, 0, 2); + case XED_REG_DS: return RegisterInfo(XED_REG_DS, 0, 2); + case XED_REG_ES: return RegisterInfo(XED_REG_ES, 0, 2); + case XED_REG_SS: return RegisterInfo(XED_REG_SS, 0, 2); + case XED_REG_FS: return RegisterInfo(XED_REG_FS, 0, 2); + case XED_REG_GS: return RegisterInfo(XED_REG_GS, 0, 2); + + case XED_REG_SP: return RegisterInfo(XED_REG_RSP, 0, 2); + case XED_REG_BP: return RegisterInfo(XED_REG_RBP, 0, 2); + case XED_REG_SI: return RegisterInfo(XED_REG_RSI, 0, 2); + case XED_REG_DI: return RegisterInfo(XED_REG_RDI, 0, 2); + + case XED_REG_FLAGS: return RegisterInfo(XED_REG_RFLAGS, 0, 2); + + case XED_REG_AX: return RegisterInfo(XED_REG_RAX, 0, 2); + case XED_REG_CX: return RegisterInfo(XED_REG_RCX, 0, 2); + case XED_REG_DX: return RegisterInfo(XED_REG_RDX, 0, 2); + case XED_REG_BX: return RegisterInfo(XED_REG_RBX, 0, 2); + case XED_REG_R8W: return RegisterInfo(XED_REG_R8, 0, 2); + case XED_REG_R9W: return RegisterInfo(XED_REG_R9, 0, 2); + case XED_REG_R10W: return RegisterInfo(XED_REG_R10, 0, 2); + case XED_REG_R11W: return RegisterInfo(XED_REG_R11, 0, 2); + case XED_REG_R12W: return RegisterInfo(XED_REG_R12, 0, 2); + case XED_REG_R13W: return RegisterInfo(XED_REG_R13, 0, 2); + case XED_REG_R14W: return RegisterInfo(XED_REG_R14, 0, 2); + case XED_REG_R15W: return RegisterInfo(XED_REG_R15, 0, 2); + + // 32-Bit + case XED_REG_EIP: return RegisterInfo(XED_REG_RIP, 0, 4); + + case XED_REG_ESP: return RegisterInfo(XED_REG_RSP, 0, 4, true); + case XED_REG_EBP: return RegisterInfo(XED_REG_RBP, 0, 4, true); + case XED_REG_ESI: return RegisterInfo(XED_REG_RSI, 0, 4, true); + case XED_REG_EDI: return RegisterInfo(XED_REG_RDI, 0, 4, true); + + case REG_X87_TOP: return RegisterInfo((xed_reg_enum_t)REG_X87_TOP, 0, 2); + case XED_REG_X87CONTROL: return RegisterInfo(XED_REG_X87CONTROL, 0, 2); + case XED_REG_X87STATUS: return RegisterInfo(XED_REG_X87STATUS, 0, 2); + case XED_REG_X87TAG: return RegisterInfo(XED_REG_X87TAG, 0, 2); + case XED_REG_X87OPCODE: return RegisterInfo(XED_REG_X87OPCODE, 0, 2); + case XED_REG_X87LASTCS: return RegisterInfo(XED_REG_X87LASTCS, 0, 2); + case XED_REG_X87LASTDS: return RegisterInfo(XED_REG_X87LASTDS, 0, 2); + case XED_REG_X87LASTIP: return RegisterInfo(XED_REG_X87LASTIP, 0, 8); + case XED_REG_X87LASTDP: return RegisterInfo(XED_REG_X87LASTDP, 0, 8); + case XED_REG_X87PUSH: return RegisterInfo(XED_REG_X87PUSH, 0, 8); + case XED_REG_X87POP: return RegisterInfo(XED_REG_X87POP, 0, 8); + case XED_REG_X87POP2: return RegisterInfo(XED_REG_X87POP2, 0, 8); + + case XED_REG_EFLAGS: return RegisterInfo(XED_REG_RFLAGS, 0, 4, true); + + case XED_REG_EAX: return RegisterInfo(XED_REG_RAX, 0, 4, true); + case XED_REG_ECX: return RegisterInfo(XED_REG_RCX, 0, 4, true); + case XED_REG_EDX: return RegisterInfo(XED_REG_RDX, 0, 4, true); + case XED_REG_EBX: return RegisterInfo(XED_REG_RBX, 0, 4, true); + + case XED_REG_R8D: return RegisterInfo(XED_REG_R8, 0, 4, true); + case XED_REG_R9D: return RegisterInfo(XED_REG_R9, 0, 4, true); + case XED_REG_R10D: return RegisterInfo(XED_REG_R10, 0, 4, true); + case XED_REG_R11D: return RegisterInfo(XED_REG_R11, 0, 4, true); + case XED_REG_R12D: return RegisterInfo(XED_REG_R12, 0, 4, true); + case XED_REG_R13D: return RegisterInfo(XED_REG_R13, 0, 4, true); + case XED_REG_R14D: return RegisterInfo(XED_REG_R14, 0, 4, true); + case XED_REG_R15D: return RegisterInfo(XED_REG_R15, 0, 4, true); + + // 48-Bit + case XED_REG_GDTR: return RegisterInfo(XED_REG_GDTR, 0, 6); + case XED_REG_LDTR: return RegisterInfo(XED_REG_LDTR, 0, 6); + case XED_REG_IDTR: return RegisterInfo(XED_REG_IDTR, 0, 6); + + // 64-Bit + case XED_REG_FSBASE: return RegisterInfo(XED_REG_FSBASE, 0, 8); + case XED_REG_GSBASE: return RegisterInfo(XED_REG_GSBASE, 0, 8); + case XED_REG_TSC: return RegisterInfo(XED_REG_TSC, 0, 8); + case XED_REG_TSCAUX: return RegisterInfo(XED_REG_TSCAUX, 0, 8); + case XED_REG_TR: return RegisterInfo(XED_REG_TR, 0, 8); + + case XED_REG_MMX0: return RegisterInfo(XED_REG_ST0, 0, 8); + case XED_REG_MMX1: return RegisterInfo(XED_REG_ST1, 0, 8); + case XED_REG_MMX2: return RegisterInfo(XED_REG_ST2, 0, 8); + case XED_REG_MMX3: return RegisterInfo(XED_REG_ST3, 0, 8); + case XED_REG_MMX4: return RegisterInfo(XED_REG_ST4, 0, 8); + case XED_REG_MMX5: return RegisterInfo(XED_REG_ST5, 0, 8); + case XED_REG_MMX6: return RegisterInfo(XED_REG_ST6, 0, 8); + case XED_REG_MMX7: return RegisterInfo(XED_REG_ST7, 0, 8); + + case XED_REG_RIP: return RegisterInfo(XED_REG_RIP, 0, 8); + + case XED_REG_RSP: return RegisterInfo(XED_REG_RSP, 0, 8); + case XED_REG_RBP: return RegisterInfo(XED_REG_RBP, 0, 8); + case XED_REG_RSI: return RegisterInfo(XED_REG_RSI, 0, 8); + case XED_REG_RDI: return RegisterInfo(XED_REG_RDI, 0, 8); + + case XED_REG_RFLAGS: return RegisterInfo(XED_REG_RFLAGS, 0, 8); + + case XED_REG_MXCSR: return RegisterInfo(XED_REG_MXCSR, 0, 8); + case XED_REG_XCR0: return RegisterInfo(XED_REG_XCR0, 0, 8); + case XED_REG_SSP: return RegisterInfo(XED_REG_SSP, 0, 8); + + case XED_REG_RAX: return RegisterInfo(XED_REG_RAX, 0, 8); + case XED_REG_RCX: return RegisterInfo(XED_REG_RCX, 0, 8); + case XED_REG_RDX: return RegisterInfo(XED_REG_RDX, 0, 8); + case XED_REG_RBX: return RegisterInfo(XED_REG_RBX, 0, 8); + case XED_REG_R8: return RegisterInfo(XED_REG_R8, 0, 8); + case XED_REG_R9: return RegisterInfo(XED_REG_R9, 0, 8); + case XED_REG_R10: return RegisterInfo(XED_REG_R10, 0, 8); + case XED_REG_R11: return RegisterInfo(XED_REG_R11, 0, 8); + case XED_REG_R12: return RegisterInfo(XED_REG_R12, 0, 8); + case XED_REG_R13: return RegisterInfo(XED_REG_R13, 0, 8); + case XED_REG_R14: return RegisterInfo(XED_REG_R14, 0, 8); + case XED_REG_R15: return RegisterInfo(XED_REG_R15, 0, 8); + + case XED_REG_BNDCFGU: return RegisterInfo(XED_REG_BNDCFGU, 0, 8); + case XED_REG_BNDSTATUS: return RegisterInfo(XED_REG_BNDSTATUS, 0, 8); + + case XED_REG_K0: return RegisterInfo(XED_REG_K0, 0, 8); + case XED_REG_K1: return RegisterInfo(XED_REG_K1, 0, 8); + case XED_REG_K2: return RegisterInfo(XED_REG_K2, 0, 8); + case XED_REG_K3: return RegisterInfo(XED_REG_K3, 0, 8); + case XED_REG_K4: return RegisterInfo(XED_REG_K4, 0, 8); + case XED_REG_K5: return RegisterInfo(XED_REG_K5, 0, 8); + case XED_REG_K6: return RegisterInfo(XED_REG_K6, 0, 8); + case XED_REG_K7: return RegisterInfo(XED_REG_K7, 0, 8); + + case XED_REG_CR0: return RegisterInfo(XED_REG_CR0, 0, 8); + case XED_REG_CR1: return RegisterInfo(XED_REG_CR1, 0, 8); + case XED_REG_CR2: return RegisterInfo(XED_REG_CR2, 0, 8); + case XED_REG_CR3: return RegisterInfo(XED_REG_CR3, 0, 8); + case XED_REG_CR4: return RegisterInfo(XED_REG_CR4, 0, 8); + case XED_REG_CR5: return RegisterInfo(XED_REG_CR5, 0, 8); + case XED_REG_CR6: return RegisterInfo(XED_REG_CR6, 0, 8); + case XED_REG_CR7: return RegisterInfo(XED_REG_CR7, 0, 8); + case XED_REG_CR8: return RegisterInfo(XED_REG_CR8, 0, 8); + case XED_REG_CR9: return RegisterInfo(XED_REG_CR9, 0, 8); + case XED_REG_CR10: return RegisterInfo(XED_REG_CR10, 0, 8); + case XED_REG_CR11: return RegisterInfo(XED_REG_CR11, 0, 8); + case XED_REG_CR12: return RegisterInfo(XED_REG_CR12, 0, 8); + case XED_REG_CR13: return RegisterInfo(XED_REG_CR13, 0, 8); + case XED_REG_CR14: return RegisterInfo(XED_REG_CR14, 0, 8); + case XED_REG_CR15: return RegisterInfo(XED_REG_CR15, 0, 8); + + case XED_REG_DR0: return RegisterInfo(XED_REG_DR0, 0, 8); + case XED_REG_DR1: return RegisterInfo(XED_REG_DR1, 0, 8); + case XED_REG_DR2: return RegisterInfo(XED_REG_DR2, 0, 8); + case XED_REG_DR3: return RegisterInfo(XED_REG_DR3, 0, 8); + case XED_REG_DR4: return RegisterInfo(XED_REG_DR4, 0, 8); + case XED_REG_DR5: return RegisterInfo(XED_REG_DR5, 0, 8); + case XED_REG_DR6: return RegisterInfo(XED_REG_DR6, 0, 8); + case XED_REG_DR7: return RegisterInfo(XED_REG_DR7, 0, 8); + + case XED_REG_MSRS: return RegisterInfo(XED_REG_MSRS, 0, 8); + + // 80-Bit + case XED_REG_ST0: return RegisterInfo(XED_REG_ST0, 0, 10); + case XED_REG_ST1: return RegisterInfo(XED_REG_ST1, 0, 10); + case XED_REG_ST2: return RegisterInfo(XED_REG_ST2, 0, 10); + case XED_REG_ST3: return RegisterInfo(XED_REG_ST3, 0, 10); + case XED_REG_ST4: return RegisterInfo(XED_REG_ST4, 0, 10); + case XED_REG_ST5: return RegisterInfo(XED_REG_ST5, 0, 10); + case XED_REG_ST6: return RegisterInfo(XED_REG_ST6, 0, 10); + case XED_REG_ST7: return RegisterInfo(XED_REG_ST7, 0, 10); + + case REG_X87_r(0): return RegisterInfo((xed_reg_enum_t)REG_X87_r(0), 0, 10); + case REG_X87_r(1): return RegisterInfo((xed_reg_enum_t)REG_X87_r(1), 0, 10); + case REG_X87_r(2): return RegisterInfo((xed_reg_enum_t)REG_X87_r(2), 0, 10); + case REG_X87_r(3): return RegisterInfo((xed_reg_enum_t)REG_X87_r(3), 0, 10); + case REG_X87_r(4): return RegisterInfo((xed_reg_enum_t)REG_X87_r(4), 0, 10); + case REG_X87_r(5): return RegisterInfo((xed_reg_enum_t)REG_X87_r(5), 0, 10); + case REG_X87_r(6): return RegisterInfo((xed_reg_enum_t)REG_X87_r(6), 0, 10); + case REG_X87_r(7): return RegisterInfo((xed_reg_enum_t)REG_X87_r(7), 0, 10); + + // 128-Bit + case XED_REG_XMM0: return RegisterInfo(XED_REG_ZMM0, 0, 16); + case XED_REG_XMM1: return RegisterInfo(XED_REG_ZMM1, 0, 16); + case XED_REG_XMM2: return RegisterInfo(XED_REG_ZMM2, 0, 16); + case XED_REG_XMM3: return RegisterInfo(XED_REG_ZMM3, 0, 16); + case XED_REG_XMM4: return RegisterInfo(XED_REG_ZMM4, 0, 16); + case XED_REG_XMM5: return RegisterInfo(XED_REG_ZMM5, 0, 16); + case XED_REG_XMM6: return RegisterInfo(XED_REG_ZMM6, 0, 16); + case XED_REG_XMM7: return RegisterInfo(XED_REG_ZMM7, 0, 16); + case XED_REG_XMM8: return RegisterInfo(XED_REG_ZMM8, 0, 16); + case XED_REG_XMM9: return RegisterInfo(XED_REG_ZMM9, 0, 16); + case XED_REG_XMM10: return RegisterInfo(XED_REG_ZMM10, 0, 16); + case XED_REG_XMM11: return RegisterInfo(XED_REG_ZMM11, 0, 16); + case XED_REG_XMM12: return RegisterInfo(XED_REG_ZMM12, 0, 16); + case XED_REG_XMM13: return RegisterInfo(XED_REG_ZMM13, 0, 16); + case XED_REG_XMM14: return RegisterInfo(XED_REG_ZMM14, 0, 16); + case XED_REG_XMM15: return RegisterInfo(XED_REG_ZMM15, 0, 16); + case XED_REG_XMM16: return RegisterInfo(XED_REG_ZMM16, 0, 16); + case XED_REG_XMM17: return RegisterInfo(XED_REG_ZMM17, 0, 16); + case XED_REG_XMM18: return RegisterInfo(XED_REG_ZMM18, 0, 16); + case XED_REG_XMM19: return RegisterInfo(XED_REG_ZMM19, 0, 16); + case XED_REG_XMM20: return RegisterInfo(XED_REG_ZMM20, 0, 16); + case XED_REG_XMM21: return RegisterInfo(XED_REG_ZMM21, 0, 16); + case XED_REG_XMM22: return RegisterInfo(XED_REG_ZMM22, 0, 16); + case XED_REG_XMM23: return RegisterInfo(XED_REG_ZMM23, 0, 16); + case XED_REG_XMM24: return RegisterInfo(XED_REG_ZMM24, 0, 16); + case XED_REG_XMM25: return RegisterInfo(XED_REG_ZMM25, 0, 16); + case XED_REG_XMM26: return RegisterInfo(XED_REG_ZMM26, 0, 16); + case XED_REG_XMM27: return RegisterInfo(XED_REG_ZMM27, 0, 16); + case XED_REG_XMM28: return RegisterInfo(XED_REG_ZMM28, 0, 16); + case XED_REG_XMM29: return RegisterInfo(XED_REG_ZMM29, 0, 16); + case XED_REG_XMM30: return RegisterInfo(XED_REG_ZMM30, 0, 16); + case XED_REG_XMM31: return RegisterInfo(XED_REG_ZMM31, 0, 16); + + case XED_REG_BND0: return RegisterInfo(XED_REG_BND0, 0, 16); + case XED_REG_BND1: return RegisterInfo(XED_REG_BND1, 0, 16); + case XED_REG_BND2: return RegisterInfo(XED_REG_BND2, 0, 16); + case XED_REG_BND3: return RegisterInfo(XED_REG_BND3, 0, 16); + + // 256-Bit + case XED_REG_YMM0: return RegisterInfo(XED_REG_ZMM0, 0, 32); + case XED_REG_YMM1: return RegisterInfo(XED_REG_ZMM1, 0, 32); + case XED_REG_YMM2: return RegisterInfo(XED_REG_ZMM2, 0, 32); + case XED_REG_YMM3: return RegisterInfo(XED_REG_ZMM3, 0, 32); + case XED_REG_YMM4: return RegisterInfo(XED_REG_ZMM4, 0, 32); + case XED_REG_YMM5: return RegisterInfo(XED_REG_ZMM5, 0, 32); + case XED_REG_YMM6: return RegisterInfo(XED_REG_ZMM6, 0, 32); + case XED_REG_YMM7: return RegisterInfo(XED_REG_ZMM7, 0, 32); + case XED_REG_YMM8: return RegisterInfo(XED_REG_ZMM8, 0, 32); + case XED_REG_YMM9: return RegisterInfo(XED_REG_ZMM9, 0, 32); + case XED_REG_YMM10: return RegisterInfo(XED_REG_ZMM10, 0, 32); + case XED_REG_YMM11: return RegisterInfo(XED_REG_ZMM11, 0, 32); + case XED_REG_YMM12: return RegisterInfo(XED_REG_ZMM12, 0, 32); + case XED_REG_YMM13: return RegisterInfo(XED_REG_ZMM13, 0, 32); + case XED_REG_YMM14: return RegisterInfo(XED_REG_ZMM14, 0, 32); + case XED_REG_YMM15: return RegisterInfo(XED_REG_ZMM15, 0, 32); + case XED_REG_YMM16: return RegisterInfo(XED_REG_ZMM16, 0, 32); + case XED_REG_YMM17: return RegisterInfo(XED_REG_ZMM17, 0, 32); + case XED_REG_YMM18: return RegisterInfo(XED_REG_ZMM18, 0, 32); + case XED_REG_YMM19: return RegisterInfo(XED_REG_ZMM19, 0, 32); + case XED_REG_YMM20: return RegisterInfo(XED_REG_ZMM20, 0, 32); + case XED_REG_YMM21: return RegisterInfo(XED_REG_ZMM21, 0, 32); + case XED_REG_YMM22: return RegisterInfo(XED_REG_ZMM22, 0, 32); + case XED_REG_YMM23: return RegisterInfo(XED_REG_ZMM23, 0, 32); + case XED_REG_YMM24: return RegisterInfo(XED_REG_ZMM24, 0, 32); + case XED_REG_YMM25: return RegisterInfo(XED_REG_ZMM25, 0, 32); + case XED_REG_YMM26: return RegisterInfo(XED_REG_ZMM26, 0, 32); + case XED_REG_YMM27: return RegisterInfo(XED_REG_ZMM27, 0, 32); + case XED_REG_YMM28: return RegisterInfo(XED_REG_ZMM28, 0, 32); + case XED_REG_YMM29: return RegisterInfo(XED_REG_ZMM29, 0, 32); + case XED_REG_YMM30: return RegisterInfo(XED_REG_ZMM30, 0, 32); + case XED_REG_YMM31: return RegisterInfo(XED_REG_ZMM31, 0, 32); + + // 512-Bit + case XED_REG_ZMM0: return RegisterInfo(XED_REG_ZMM0, 0, 64); + case XED_REG_ZMM1: return RegisterInfo(XED_REG_ZMM1, 0, 64); + case XED_REG_ZMM2: return RegisterInfo(XED_REG_ZMM2, 0, 64); + case XED_REG_ZMM3: return RegisterInfo(XED_REG_ZMM3, 0, 64); + case XED_REG_ZMM4: return RegisterInfo(XED_REG_ZMM4, 0, 64); + case XED_REG_ZMM5: return RegisterInfo(XED_REG_ZMM5, 0, 64); + case XED_REG_ZMM6: return RegisterInfo(XED_REG_ZMM6, 0, 64); + case XED_REG_ZMM7: return RegisterInfo(XED_REG_ZMM7, 0, 64); + case XED_REG_ZMM8: return RegisterInfo(XED_REG_ZMM8, 0, 64); + case XED_REG_ZMM9: return RegisterInfo(XED_REG_ZMM9, 0, 64); + case XED_REG_ZMM10: return RegisterInfo(XED_REG_ZMM10, 0, 64); + case XED_REG_ZMM11: return RegisterInfo(XED_REG_ZMM11, 0, 64); + case XED_REG_ZMM12: return RegisterInfo(XED_REG_ZMM12, 0, 64); + case XED_REG_ZMM13: return RegisterInfo(XED_REG_ZMM13, 0, 64); + case XED_REG_ZMM14: return RegisterInfo(XED_REG_ZMM14, 0, 64); + case XED_REG_ZMM15: return RegisterInfo(XED_REG_ZMM15, 0, 64); + case XED_REG_ZMM16: return RegisterInfo(XED_REG_ZMM16, 0, 64); + case XED_REG_ZMM17: return RegisterInfo(XED_REG_ZMM17, 0, 64); + case XED_REG_ZMM18: return RegisterInfo(XED_REG_ZMM18, 0, 64); + case XED_REG_ZMM19: return RegisterInfo(XED_REG_ZMM19, 0, 64); + case XED_REG_ZMM20: return RegisterInfo(XED_REG_ZMM20, 0, 64); + case XED_REG_ZMM21: return RegisterInfo(XED_REG_ZMM21, 0, 64); + case XED_REG_ZMM22: return RegisterInfo(XED_REG_ZMM22, 0, 64); + case XED_REG_ZMM23: return RegisterInfo(XED_REG_ZMM23, 0, 64); + case XED_REG_ZMM24: return RegisterInfo(XED_REG_ZMM24, 0, 64); + case XED_REG_ZMM25: return RegisterInfo(XED_REG_ZMM25, 0, 64); + case XED_REG_ZMM26: return RegisterInfo(XED_REG_ZMM26, 0, 64); + case XED_REG_ZMM27: return RegisterInfo(XED_REG_ZMM27, 0, 64); + case XED_REG_ZMM28: return RegisterInfo(XED_REG_ZMM28, 0, 64); + case XED_REG_ZMM29: return RegisterInfo(XED_REG_ZMM29, 0, 64); + case XED_REG_ZMM30: return RegisterInfo(XED_REG_ZMM30, 0, 64); + case XED_REG_ZMM31: return RegisterInfo(XED_REG_ZMM31, 0, 64); + + default: return RegisterInfo(XED_REG_INVALID, 0, 0); + } + } + + virtual uint32_t GetStackPointerRegister() override + { + return XED_REG_RSP; + } +}; + + +class X86BaseCallingConvention: public CallingConvention +{ +public: + X86BaseCallingConvention(Architecture* arch, const string& name): CallingConvention(arch, name) + { + } + + virtual vector<uint32_t> GetCallerSavedRegisters() override + { + return vector<uint32_t>{ XED_REG_EAX, XED_REG_ECX, XED_REG_EDX }; + } + + virtual vector<uint32_t> GetCalleeSavedRegisters() override + { + return vector<uint32_t>{ XED_REG_EBX, XED_REG_EBP, XED_REG_ESI, XED_REG_EDI }; + } + + virtual uint32_t GetGlobalPointerRegister() override + { + return XED_REG_EBX; + } + + virtual uint32_t GetIntegerReturnValueRegister() override + { + return XED_REG_EAX; + } + + virtual uint32_t GetHighIntegerReturnValueRegister() override + { + return XED_REG_EDX; + } + + virtual uint32_t GetFloatReturnValueRegister() override + { + return XED_REG_ST0; + } + + virtual RegisterValue GetIncomingFlagValue(uint32_t flag, Function*) override + { + RegisterValue result; + if (flag == IL_FLAG_D) + { + result.state = ConstantValue; + result.value = 0; + } + return result; + } +}; + + +class X86CdeclCallingConvention: public X86BaseCallingConvention +{ +public: + X86CdeclCallingConvention(Architecture* arch): X86BaseCallingConvention(arch, "cdecl") + { + } +}; + + +class X86StdcallCallingConvention: public X86BaseCallingConvention +{ +public: + X86StdcallCallingConvention(Architecture* arch): X86BaseCallingConvention(arch, "stdcall") + { + } + + virtual bool IsStackAdjustedOnReturn() override + { + return true; + } +}; + + +class X86RegParmCallingConvention: public X86BaseCallingConvention +{ +public: + X86RegParmCallingConvention(Architecture* arch): X86BaseCallingConvention(arch, "regparm") + { + } + + virtual vector<uint32_t> GetIntegerArgumentRegisters() override + { + return vector<uint32_t>{ XED_REG_EAX, XED_REG_EDX, XED_REG_ECX }; + } +}; + + +class X86FastcallCallingConvention: public X86BaseCallingConvention +{ +public: + X86FastcallCallingConvention(Architecture* arch): X86BaseCallingConvention(arch, "fastcall") + { + } + + virtual vector<uint32_t> GetIntegerArgumentRegisters() override + { + return vector<uint32_t>{ XED_REG_ECX, XED_REG_EDX }; + } + + virtual bool IsStackAdjustedOnReturn() override + { + return true; + } +}; + + +class X86ThiscallCallingConvention: public X86BaseCallingConvention +{ +public: + X86ThiscallCallingConvention(Architecture* arch): X86BaseCallingConvention(arch, "thiscall") + { + } + + virtual vector<uint32_t> GetIntegerArgumentRegisters() override + { + return vector<uint32_t>{ XED_REG_ECX }; + } + + virtual bool IsStackAdjustedOnReturn() override + { + return true; + } +}; + + +class X86LinuxSystemCallConvention: public CallingConvention +{ +public: + X86LinuxSystemCallConvention(Architecture* arch): CallingConvention(arch, "linux-syscall") + { + } + + virtual vector<uint32_t> GetIntegerArgumentRegisters() override + { + return vector<uint32_t> { XED_REG_EAX, XED_REG_EBX, XED_REG_ECX, XED_REG_EDX, XED_REG_ESI, XED_REG_EDI, XED_REG_EBP }; + } + + virtual vector<uint32_t> GetCallerSavedRegisters() override + { + return vector<uint32_t> { XED_REG_EAX, XED_REG_EDX }; + } + + virtual vector<uint32_t> GetCalleeSavedRegisters() override + { + return vector<uint32_t> { XED_REG_EBX, XED_REG_EBP, XED_REG_ESI, XED_REG_EDI }; + } + + virtual uint32_t GetIntegerReturnValueRegister() override + { + return XED_REG_EAX; + } + + virtual uint32_t GetHighIntegerReturnValueRegister() override + { + return XED_REG_EDX; + } + + virtual uint32_t GetFloatReturnValueRegister() override + { + return XED_REG_ST0; + } + + virtual bool IsEligibleForHeuristics() override + { + return false; + } +}; + + +class X64BaseCallingConvention: public CallingConvention +{ +public: + X64BaseCallingConvention(Architecture* arch, const string& name): CallingConvention(arch, name) + { + } + + virtual uint32_t GetIntegerReturnValueRegister() override + { + return XED_REG_RAX; + } + + virtual uint32_t GetFloatReturnValueRegister() override + { + return XED_REG_ZMM0; + } + + virtual RegisterValue GetIncomingFlagValue(uint32_t flag, Function*) override + { + RegisterValue result; + if (flag == IL_FLAG_D) + { + result.state = ConstantValue; + result.value = 0; + } + return result; + } +}; + + +class X64SystemVCallingConvention: public X64BaseCallingConvention +{ +public: + X64SystemVCallingConvention(Architecture* arch): X64BaseCallingConvention(arch, "sysv") + { + } + + virtual vector<uint32_t> GetIntegerArgumentRegisters() override + { + return vector<uint32_t> { XED_REG_RDI, XED_REG_RSI, XED_REG_RDX, XED_REG_RCX, XED_REG_R8, XED_REG_R9 }; + } + + virtual vector<uint32_t> GetFloatArgumentRegisters() override + { + return vector<uint32_t> { XED_REG_ZMM0, XED_REG_ZMM1, XED_REG_ZMM2, XED_REG_ZMM3, XED_REG_ZMM4, XED_REG_ZMM5, XED_REG_ZMM6, XED_REG_ZMM7 }; + } + + virtual vector<uint32_t> GetCallerSavedRegisters() override + { + return vector<uint32_t> { + XED_REG_RAX, XED_REG_RCX, XED_REG_RDX, + XED_REG_RSI, XED_REG_RDI, + XED_REG_R8, XED_REG_R9, XED_REG_R10, XED_REG_R11, + XED_REG_ZMM0, XED_REG_ZMM1, XED_REG_ZMM2, XED_REG_ZMM3, XED_REG_ZMM4, XED_REG_ZMM5, XED_REG_ZMM6, XED_REG_ZMM7, XED_REG_ZMM8, XED_REG_ZMM9, XED_REG_ZMM10, XED_REG_ZMM11, XED_REG_ZMM12, XED_REG_ZMM13, XED_REG_ZMM14, XED_REG_ZMM15 }; + } + + virtual vector<uint32_t> GetCalleeSavedRegisters() override + { + return vector<uint32_t> { + XED_REG_RBX, XED_REG_RBP, + XED_REG_R12, XED_REG_R13, XED_REG_R14, XED_REG_R15 }; + } +}; + + +class X64WindowsCallingConvention: public X64BaseCallingConvention +{ +public: + X64WindowsCallingConvention(Architecture* arch): X64BaseCallingConvention(arch, "win64") + { + } + + virtual vector<uint32_t> GetIntegerArgumentRegisters() override + { + return vector<uint32_t> { XED_REG_RCX, XED_REG_RDX, XED_REG_R8, XED_REG_R9 }; + } + + virtual vector<uint32_t> GetFloatArgumentRegisters() override + { + return vector<uint32_t> { XED_REG_ZMM0, XED_REG_ZMM1, XED_REG_ZMM2, XED_REG_ZMM3 }; + } + + virtual vector<uint32_t> GetCallerSavedRegisters() override + { + return vector<uint32_t> { + XED_REG_RAX, XED_REG_RCX, XED_REG_RDX, + XED_REG_R8, XED_REG_R9, XED_REG_R10, XED_REG_R11, + XED_REG_ZMM4, XED_REG_ZMM5 }; + } + + virtual vector<uint32_t> GetCalleeSavedRegisters() override + { + return vector<uint32_t> { + XED_REG_RBX, XED_REG_RBP, XED_REG_RSI, XED_REG_RDI, + XED_REG_R12, XED_REG_R13, XED_REG_R14, XED_REG_R15 }; + } + + virtual bool AreArgumentRegistersSharedIndex() override + { + return true; + } + + virtual bool IsStackReservedForArgumentRegisters() override + { + return true; + } +}; + + +class X64LinuxSystemCallConvention: public CallingConvention +{ +public: + X64LinuxSystemCallConvention(Architecture* arch): CallingConvention(arch, "linux-syscall") + { + } + + virtual vector<uint32_t> GetIntegerArgumentRegisters() override + { + return vector<uint32_t> { XED_REG_RAX, XED_REG_RDI, XED_REG_RSI, XED_REG_RDX, XED_REG_R10, XED_REG_R8, XED_REG_R9 }; + } + + virtual vector<uint32_t> GetCallerSavedRegisters() override + { + return vector<uint32_t> { XED_REG_RAX, XED_REG_RCX, XED_REG_R11 }; + } + + virtual vector<uint32_t> GetCalleeSavedRegisters() override + { + return vector<uint32_t> { XED_REG_RBX, XED_REG_RBP, XED_REG_RSI, XED_REG_RDI, + XED_REG_R12, XED_REG_R13, XED_REG_R14, XED_REG_R15 }; + } + + virtual uint32_t GetIntegerReturnValueRegister() override + { + return XED_REG_RAX; + } + + virtual bool IsEligibleForHeuristics() override + { + return false; + } +}; + + +class x86MachoRelocationHandler: public RelocationHandler +{ +public: + + virtual bool ApplyRelocation(Ref<BinaryView> view, Ref<Architecture> arch, Ref<Relocation> reloc, uint8_t* dest, + size_t len) override + { + (void)view; + (void)arch; + (void)len; + auto info = reloc->GetInfo(); + uint64_t pcRelAddr = info.pcRelative ? reloc->GetAddress() : 0; + // TODO these need tested + // uint8_t* dest8 = (uint8_t*)dest; + // uint16_t* dest16 = (uint16_t*)dest; + uint32_t* dest32 = (uint32_t*)dest; + uint32_t target = (uint32_t)reloc->GetTarget(); + + switch (info.nativeType) + { + case (uint64_t)-1: // Magic number defined in MachOView.cpp + // We need to write a jump absolute `jmp target` + dest[0] = '\xe9'; + ((uint32_t*)&dest[1])[0] = target - (uint32_t)reloc->GetAddress() - 5; + break; + case (uint64_t)-2: // Magic number defined in MachOView.cpp + dest32[0] = target; + break; + case GENERIC_RELOC_VANILLA: + switch (info.size) + { + // TODO these need tested + // case 1: *dest8 = target - pcRelAddr; break; + // case 2: *dest16 = target - pcRelAddr; break; + case 4: *dest32 = (uint32_t)(target - pcRelAddr); break; + default: break; + } + // TODO rebasing + break; + + default: + break; + } + + return true; + } + + virtual bool GetRelocationInfo(Ref<BinaryView> view, Ref<Architecture> arch, vector<BNRelocationInfo>& result) override + { + (void)view; (void)arch; + set<uint64_t> relocTypes; + for (size_t i = 0; i < result.size(); i++) + { + result[i].type = StandardRelocationType; + switch (result[i].nativeType) + { + case GENERIC_RELOC_VANILLA: + if (result[i].size != 4) + { + result[i].type = IgnoredRelocation; + relocTypes.insert(result[i].nativeType); + } + break; + default: + result[i].type = UnhandledRelocation; + relocTypes.insert(result[i].nativeType); + break; + } + } + + for (auto& reloc : relocTypes) + LogWarn("Unsupported Mach-O relocation type: %s", GetRelocationString((Machox86RelocationType)reloc)); + return true; + } +}; + +class x86ElfRelocationHandler: public RelocationHandler +{ +public: + virtual bool GetRelocationInfo(Ref<BinaryView> view, Ref<Architecture> arch, vector<BNRelocationInfo>& result) override + { + (void)view; (void)arch; + set<uint64_t> relocTypes; + for (auto& reloc : result) + { + reloc.type = StandardRelocationType; + switch (reloc.nativeType) + { + case R_386_NONE: + reloc.type = IgnoredRelocation; + break; + case R_386_32: + reloc.pcRelative = false; + reloc.baseRelative = false; + reloc.hasSign = false; + reloc.size = 4; + reloc.truncateSize = 4; + break; + case R_386_PC32: + case R_386_GOT32: + case R_386_PLT32: + reloc.pcRelative = true; + reloc.baseRelative = false; + reloc.hasSign = false; + reloc.size = 4; + reloc.truncateSize = 4; + break; + case R_386_RELATIVE: + reloc.pcRelative = false; + reloc.baseRelative = true; + reloc.hasSign = false; + reloc.size = 4; + reloc.truncateSize = 4; + reloc.implicitAddend = true; + reloc.addend = 0; + break; + case R_386_COPY: + reloc.type = ELFCopyRelocationType; + reloc.pcRelative = false; + reloc.baseRelative = false; + reloc.size = 4; + reloc.truncateSize = 4; + break; + case R_386_GLOB_DAT: + reloc.type = ELFGlobalRelocationType; + reloc.pcRelative = false; + reloc.baseRelative = false; + reloc.size = 4; + reloc.truncateSize = 4; + reloc.implicitAddend = false; + break; + case R_386_JUMP_SLOT: + reloc.type = ELFJumpSlotRelocationType; + reloc.pcRelative = false; + reloc.baseRelative = false; + reloc.size = 4; + reloc.truncateSize = 4; + reloc.implicitAddend = false; + break; + default: + reloc.type = UnhandledRelocation; + relocTypes.insert(reloc.nativeType); + } + } + for (auto& reloc : relocTypes) + LogWarn("Unsupported ELF relocation type: %s", GetRelocationString((Elfx86RelocationType)reloc)); + return true; + } +}; + +class x64MachoRelocationHandler: public RelocationHandler +{ +public: + virtual bool ApplyRelocation(Ref<BinaryView> view, Ref<Architecture> arch, Ref<Relocation> reloc, uint8_t* dest, size_t len) override + { + (void)view; + (void)arch; + auto info = reloc->GetInfo(); + uint64_t pcRelAddr = info.pcRelative ? reloc->GetAddress() : 0; + if (len < info.size) + return false; + uint32_t target = (uint32_t)info.target; + uint32_t* dest32 = (uint32_t*)dest; + uint64_t* dest64 = (uint64_t*)dest; + switch (info.nativeType) + { + case X86_64_RELOC_BRANCH: + if (info.size == 4) + dest32[0] = dest32[0] - 4 + target - (uint32_t)pcRelAddr; + break; + case X86_64_RELOC_GOT_LOAD: + dest32[0] = dest32[0] - 4 + target - (uint32_t)pcRelAddr; + break; + case X86_64_RELOC_SIGNED: + dest32[0] = dest32[0] + target - (uint32_t)pcRelAddr; + break; + case X86_64_RELOC_SIGNED_1: + dest32[0] = dest32[0] + 1 + target - (uint32_t)pcRelAddr; + break; + case X86_64_RELOC_SIGNED_2: + dest32[0] = dest32[0] + 2 + target - (uint32_t)pcRelAddr; + break; + case X86_64_RELOC_SIGNED_4: + dest32[0] = dest32[0] + 4 + target - (uint32_t)pcRelAddr; + break; + case X86_64_RELOC_GOT: + dest32[0] = dest32[0] + target - (uint32_t)pcRelAddr; + break; + case X86_64_RELOC_UNSIGNED: + if (!info.external) + { + switch (info.size) + { + case 4: *dest32 += target - (uint32_t)pcRelAddr; break; + case 8: *dest64 += info.target - pcRelAddr; break; + default: break; + } + } + // TODO rebasing + break; + case X86_64_RELOC_SUBTRACTOR: + if (!info.next) + break; + dest64[0] = dest64[0] + info.next->target - target; + break; + case (uint64_t) -2: + dest64[0] = reloc->GetTarget(); + break; + } + return true; + } + + + virtual bool GetRelocationInfo(Ref<BinaryView> view, Ref<Architecture> arch, vector<BNRelocationInfo>& result) override + { + (void)view; (void)arch; + set<uint64_t> relocTypes; + for (size_t i = 0; i < result.size(); i++) + { + result[i].type = StandardRelocationType; + switch (result[i].nativeType) + { + case X86_64_RELOC_UNSIGNED: + result[i].hasSign = false; + break; + case X86_64_RELOC_BRANCH: + result[i].pcRelative = true; + result[i].size = 4; + result[i].implicitAddend = true; + break; + case X86_64_RELOC_GOT: + case X86_64_RELOC_GOT_LOAD: + result[i].pcRelative = true; + result[i].size = 4; + result[i].implicitAddend = true; + break; + case X86_64_RELOC_SIGNED: + result[i].implicitAddend = true; + result[i].size = 4; + result[i].hasSign = true; + break; + case X86_64_RELOC_SIGNED_1: + result[i].implicitAddend = true; + result[i].addend = 1; + result[i].size = 4; + result[i].hasSign = true; + break; + case X86_64_RELOC_SIGNED_2: + result[i].implicitAddend = true; + result[i].addend = 2; + result[i].size = 4; + result[i].hasSign = true; + break; + case X86_64_RELOC_SIGNED_4: + result[i].implicitAddend = true; + result[i].addend = 4; + result[i].size = 4; + result[i].hasSign = true; + break; + case X86_64_RELOC_SUBTRACTOR: + // X86_64_RELOC_SUBTRACTOR should always be followed by a X86_64_RELOC_UNSIGNED + if (i == result.size() - 1) + result[i].type = IgnoredRelocation; + else if ((Machox64RelocationType)result[i + 1].type != X86_64_RELOC_UNSIGNED) + result[i].type = IgnoredRelocation; + else + { + result[i].next = &result[i + 1]; + result[i + 1].type = IgnoredRelocation; + i++; + } + break; + default: + result[i].type = UnhandledRelocation; + relocTypes.insert(result[i].nativeType); + break; + } + } + + for (auto& reloc : relocTypes) + LogWarn("Unsupported Mach-O relocation: %s", GetRelocationString((Machox64RelocationType)reloc)); + return true; + } +}; + +class x64ElfRelocationHandler: public RelocationHandler +{ +public: + virtual bool ApplyRelocation(Ref<BinaryView> view, Ref<Architecture> arch, Ref<Relocation> reloc, uint8_t* dest, size_t len) override + { + BNRelocationInfo info = reloc->GetInfo(); + switch (info.nativeType) + { + case R_X86_64_REX_GOTPCRELX: { + // When we're actually applying this we don't need to change the 3 first bytes, + // just apply it to the immediate and it's fine. However, we track all seven + // variable bytes so we don't lie to the user. + dest += 3; + uint64_t pc = reloc->GetAddress() + 3; + uint64_t addend = 0; + if (info.implicitAddend && info.size < sizeof(addend)) + memcpy(&addend, dest, reloc->GetInfo().size); + else + addend = info.addend; + uint32_t write = (uint32_t)(reloc->GetTarget() + addend - pc); + memcpy(dest, (uint8_t*)&write, sizeof(uint32_t)); + return true; + } + case R_X86_64_IRELATIVE: { + // What??????? + uint64_t write = info.addend; + memcpy(dest, (uint8_t*)&write, sizeof(uint64_t)); + return true; + } + default: + return RelocationHandler::ApplyRelocation(view, arch, reloc, dest, len); + } + } + + virtual bool GetRelocationInfo(Ref<BinaryView> view, Ref<Architecture> arch, vector<BNRelocationInfo>& result) override + { + /* + From the Intel AMD64 ELF Linux ABI + A Represents the addend used to compute the value of the relocatable field. + B Represents the base address at which a shared object has been loaded into memory during execution. + Generally, a shared object is built with a 0 base virtual address, but the execution address will be different. + G Represents the offset into the global offset table at which the relocation entry’s symbol + will reside during execution. + GOT Represents the address of the global offset table. + L Represents the place (section offset or address) of the Procedure Linkage Table + entry for a symbol. + P Represents the place (section offset or address) of the storage unit being relocated (computed using r_offset). + S Represents the value of the symbol whose index resides in the relocation entry. + Z Represents the size of the symbol whose index resides in the relocation entry. + The AMD64 LP64 ABI architecture uses only Elf64_Rela relocation entries with explicit addends. Theg + r_addend member serves as the relocation addend. + The AMD64 ILP32 ABI architecture uses only Elf32_Rela relocation entries in relocatable files. Relocations + contained within executable files or shared objects may use either Elf32_Rela relocation or Elf32_Rel relocation. + */ + (void)view; (void)arch; + set<uint64_t> relocTypes; + for (auto& reloc : result) + { + reloc.type = StandardRelocationType; + switch (reloc.nativeType) + { + case R_X86_64_NONE: + reloc.type = IgnoredRelocation; + break; + case R_X86_64_COPY: + reloc.type = ELFCopyRelocationType; + reloc.pcRelative = false; + reloc.baseRelative = false; + reloc.size = 8; + reloc.truncateSize = 8; + break; + case R_X86_64_GLOB_DAT: + reloc.type = ELFGlobalRelocationType; + reloc.pcRelative = false; + reloc.baseRelative = false; + reloc.size = 8; + reloc.truncateSize = 8; + break; + case R_X86_64_JUMP_SLOT: + reloc.type = ELFJumpSlotRelocationType; + reloc.pcRelative = false; + reloc.baseRelative = false; + reloc.size = 8; + reloc.truncateSize = 8; + break; + case R_X86_64_8: + reloc.pcRelative = false; + reloc.baseRelative = false; + reloc.hasSign = false; + reloc.size = 1; + reloc.truncateSize = 1; + break; + case R_X86_64_16: + reloc.pcRelative = false; + reloc.baseRelative = false; + reloc.hasSign = false; + reloc.size = 2; + reloc.truncateSize = 2; + break; + case R_X86_64_32S: + reloc.pcRelative = false; + reloc.baseRelative = false; + reloc.hasSign = true; + reloc.size = 4; + reloc.truncateSize = 4; + break; + case R_X86_64_32: + case R_X86_64_GOT32: + reloc.pcRelative = false; + reloc.baseRelative = false; + reloc.hasSign = false; + reloc.size = 8; + reloc.truncateSize = 4; + break; + case R_X86_64_64: + reloc.pcRelative = false; + reloc.baseRelative = false; + reloc.hasSign = false; + reloc.size = 8; + reloc.truncateSize = 8; + break; + case R_X86_64_PC32: + case R_X86_64_PLT32: + case R_X86_64_GOTPCREL: + case R_X86_64_GOTPCRELX: + // These are pointers into .got and .plt sections which aren't present + // At some point in the future we may need to create these sections + reloc.pcRelative = true; + reloc.baseRelative = false; + reloc.hasSign = false; + reloc.size = 4; + reloc.truncateSize = 4; + break; + case R_X86_64_PC64: + reloc.pcRelative = true; + reloc.baseRelative = false; + reloc.hasSign = false; + reloc.size = 8; + reloc.truncateSize = 8; + break; + case R_X86_64_REX_GOTPCRELX: + // The 3 bytes before the immediate that specify the registers and operand + // encoding are variable!!! Example: 49c7c400000000 vs 4c8b25d5140000 + reloc.address -= 3; + reloc.pcRelative = true; + reloc.baseRelative = false; + reloc.hasSign = false; + reloc.size = 7; + reloc.truncateSize = 7; + break; + case R_X86_64_RELATIVE: + reloc.pcRelative = false; + reloc.baseRelative = true; + reloc.hasSign = false; + reloc.size = 8; + reloc.truncateSize = 8; + reloc.implicitAddend = true; + break; + case R_X86_64_PC16: + reloc.pcRelative = true; + reloc.baseRelative = false; + reloc.hasSign = false; + reloc.size = 8; + reloc.truncateSize = 2; + break; + case R_X86_64_PC8: + reloc.pcRelative = true; + reloc.baseRelative = false; + reloc.hasSign = false; + reloc.size = 8; + reloc.truncateSize = 1; + break; + case R_X86_64_IRELATIVE: + reloc.pcRelative = false; + reloc.baseRelative = false; + reloc.hasSign = false; + reloc.size = 8; + reloc.truncateSize = 8; + break; + default: + reloc.type = UnhandledRelocation; + relocTypes.insert(reloc.nativeType); + break; + } + } + for (auto& reloc : relocTypes) + LogWarn("Unsupported ELF relocation: %s", GetRelocationString((Elfx64RelocationType)reloc)); + return true; + } +}; + +class CoffRelocationHandler: public RelocationHandler +{ +public: + virtual bool ApplyRelocation(Ref<BinaryView> view, Ref<Architecture> arch, Ref<Relocation> reloc, uint8_t* dest, size_t len) override + { + // Note: info.base contains preferred base address and the base where the image is actually loaded + (void)view; + (void)arch; + (void)len; + uint64_t* data64 = (uint64_t*)dest; + uint32_t* data32 = (uint32_t*)dest; + uint16_t* data16 = (uint16_t*)dest; + auto info = reloc->GetInfo(); + uint64_t offset = 0; + + if (info.pcRelative) + { + int64_t relative_offset = info.target - info.address; + offset = (uint64_t) relative_offset; + } + else + offset = info.target; + + if (! info.implicitAddend && info.addend) + offset += info.addend; + + if (! info.baseRelative) + offset -= info.base; + + switch (info.nativeType) + { + // case PE_IMAGE_REL_I386_SECTION: + case PE_IMAGE_REL_AMD64_SECTION: + // TODO: test this implementation, but for now, just don't warn about it + data16[0] = info.sectionIndex + 1; + break; + // case PE_IMAGE_REL_I386_SECREL: + case PE_IMAGE_REL_AMD64_SECREL: + { + // TODO: test this implementation, but for now, just don't warn about it + auto sections = view->GetSectionsAt(info.target); + if (sections.size() > 0) + { + data32[0] = info.target - sections[0]->GetStart(); + } + break; + } + default: + if (info.size == 8) + { + // LogDebug("%s: address: %#" PRIx64 " target: %#" PRIx64 " base: %#" PRIx64 " offset: %#" PRIx64 " current: %#" PRIx64 " result: %#" PRIx64 "", __func__, info.address, info.target, info.base, offset, data64[0], data64[0] + offset); + data64[0] += offset; + } + else if (info.size == 4) + { + // LogDebug("%s: address: %#" PRIx64 " target: %#" PRIx64 " base: %#" PRIx64 " offset: %#" PRIx32 " %+" PRId32 " current: %#" PRIx32 " result: %#" PRIx32 "", __func__, info.address, info.target, info.base, (uint32_t)offset, (uint32_t)offset, data32[0], data32[0] + (uint32_t)offset); + data32[0] += (uint32_t)offset; + } + } + return true; + } + + virtual bool GetRelocationInfo(Ref<BinaryView> view, Ref<Architecture> arch, vector<BNRelocationInfo>& result) override + { + (void)view; (void)arch; + set<uint64_t> relocTypes; + for (auto& reloc : result) + { + if (arch->GetName() == "x86_64") + { + switch (reloc.nativeType) + { + case PE_IMAGE_REL_AMD64_ABSOLUTE: + reloc.type = IgnoredRelocation; + break; + case PE_IMAGE_REL_AMD64_ADDR64: + reloc.baseRelative = true; + reloc.size = 8; + break; + case PE_IMAGE_REL_AMD64_ADDR32NB: + reloc.baseRelative = false; + reloc.size = 4; + break; + case PE_IMAGE_REL_AMD64_ADDR32: + reloc.baseRelative = true; + reloc.size = 4; + break; + case PE_IMAGE_REL_AMD64_REL32_5: + case PE_IMAGE_REL_AMD64_REL32_4: + case PE_IMAGE_REL_AMD64_REL32_3: + case PE_IMAGE_REL_AMD64_REL32_2: + case PE_IMAGE_REL_AMD64_REL32_1: + // LogDebug("%s: %#" PRIx64 "(%#" PRIx64 ")->%#" PRIx64 " %s addend: %ld", __func__, reloc.address, reloc.target, reloc.address - reloc.target, GetRelocationString((COFFx64RelocationType)reloc.nativeType), (long) reloc.addend); + case PE_IMAGE_REL_AMD64_REL32: + // TODO: treat reloc.addend as offset of target from its section (see llvm/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldCOFFX86_64.h:67) + reloc.addend = -(4 + (reloc.nativeType - PE_IMAGE_REL_AMD64_REL32)); + reloc.baseRelative = false; + reloc.pcRelative = true; + reloc.size = 4; + break; + case PE_IMAGE_REL_AMD64_SECTION: + // The 16-bit section index of the section that contains the target. This is used to support debugging information. + reloc.baseRelative = false; + reloc.size = 2; + reloc.addend = 0; + case PE_IMAGE_REL_AMD64_SECREL: + // TODO: implement these, but for now, just don't warn about them + // The 32-bit offset of the target from the beginning of its section. This is used to support debugging information and static thread local storage. reloc.baseRelative = false; + reloc.baseRelative = false; + reloc.size = 4; + reloc.addend = 0; + break; + case PE_IMAGE_REL_AMD64_SECREL7: + // 7-bit offset from the base of the section that contains the target + case PE_IMAGE_REL_AMD64_TOKEN: + case PE_IMAGE_REL_AMD64_SREL32: + case PE_IMAGE_REL_AMD64_PAIR: + case PE_IMAGE_REL_AMD64_SSPAN32: + default: + // By default, PE relocations are correct when not rebased. + // Upon rebasing, support would need to be added to correctly process the relocation + reloc.type = UnhandledRelocation; + relocTypes.insert(reloc.nativeType); + } + for (auto& reloc : relocTypes) + LogWarn("Unsupported COFF relocation: %s", GetRelocationString((COFFx64RelocationType)reloc)); + } + else if (arch->GetName() == "x86") + { + switch (reloc.nativeType) + { + case PE_IMAGE_REL_I386_ABSOLUTE: + reloc.type = IgnoredRelocation; + break; + case PE_IMAGE_REL_I386_REL32: + reloc.baseRelative = false; + reloc.pcRelative = true; + reloc.size = 4; + reloc.addend = -4; + break; + case PE_IMAGE_REL_I386_DIR32NB: + reloc.baseRelative = false; + reloc.size = 4; + break; + case PE_IMAGE_REL_I386_DIR32: + reloc.baseRelative = true; + reloc.size = 4; + break; + case PE_IMAGE_REL_I386_SECTION: + // The 16-bit section index of the section that contains the target. This is used to support debugging information. + reloc.baseRelative = false; + reloc.size = 2; + reloc.addend = 0; + case PE_IMAGE_REL_I386_SECREL: + // The 32-bit offset of the target from the beginning of its section. This is used to support debugging information and static thread local storage. reloc.baseRelative = false; + reloc.baseRelative = false; + reloc.size = 4; + reloc.addend = 0; + break; + case PE_IMAGE_REL_I386_SEG12: + case PE_IMAGE_REL_I386_TOKEN: + case PE_IMAGE_REL_I386_SECREL7: + case PE_IMAGE_REL_I386_DIR16: + case PE_IMAGE_REL_I386_REL16: + default: + reloc.type = UnhandledRelocation; + relocTypes.insert(reloc.nativeType); + } + for (auto& reloc : relocTypes) + LogWarn("Unsupported COFF relocation: %s", GetRelocationString((COFFx86RelocationType)reloc)); + } + } + + return true; + } +}; + +class PeRelocationHandler: public RelocationHandler +{ +public: + virtual bool ApplyRelocation(Ref<BinaryView> view, Ref<Architecture> arch, Ref<Relocation> reloc, uint8_t* dest, size_t len) override + { + // Note: info.base contains preferred base address and the base where the image is actually loaded + (void)view; + (void)arch; + (void)len; + uint64_t* data64 = (uint64_t*)dest; + uint32_t* data32 = (uint32_t*)dest; + uint16_t* data16 = (uint16_t*)dest; + auto info = reloc->GetInfo(); + if ((uint32_t)info.nativeType == PE_IMAGE_USER_DEFINED) + { + if (info.size == 8) + { + data64[0] = info.target; + } + else if (info.size == 4) + { + data32[0] = (uint32_t)info.target; + } + } + else if (info.size == 8) + { + data64[0] += info.base; + } + else if (info.size == 4) + { + data32[0] += (uint32_t)info.base; + } + else if (info.size == 2) + { + if (info.nativeType == PE_IMAGE_REL_BASED_HIGH) + { + data16[0] = data16[0] + (uint16_t)(info.base >> 16); + } + else if (info.nativeType == PE_IMAGE_REL_BASED_LOW) + { + data16[0] = data16[0] + (uint16_t)(info.base & 0xffff); + } + } + return true; + } + + virtual bool GetRelocationInfo(Ref<BinaryView> view, Ref<Architecture> arch, vector<BNRelocationInfo>& result) override + { + (void)view; (void)arch; + set<uint64_t> relocTypes; + for (auto& reloc : result) + { + switch (reloc.nativeType) + { + case PE_IMAGE_REL_BASED_ABSOLUTE: + reloc.type = IgnoredRelocation; + break; + case PE_IMAGE_REL_BASED_HIGHLOW: + reloc.size = 4; + break; + case PE_IMAGE_REL_BASED_DIR64: + reloc.size = 8; + break; + case PE_IMAGE_REL_BASED_HIGH: + reloc.size = 2; + break; + case PE_IMAGE_REL_BASED_LOW: + reloc.size = 2; + break; + case PE_IMAGE_USER_DEFINED: + reloc.type = StandardRelocationType; + break; + default: + // By default, PE relocations are correct when not rebased. + // Upon rebasing, support would need to be added to correctly process the relocation + reloc.type = UnhandledRelocation; + relocTypes.insert(reloc.nativeType); + } + } + + for (auto& reloc : relocTypes) + LogWarn("Unsupported PE relocation: %s", GetRelocationString((PeRelocationType)reloc)); + return false; + } + + virtual size_t GetOperandForExternalRelocation(const uint8_t* data, uint64_t addr, size_t length, + Ref<LowLevelILFunction> il, Ref<Relocation> relocation) override + { + (void)data; + (void)addr; + (void)length; + (void)il; + (void)relocation; + return BN_AUTOCOERCE_EXTERN_PTR; + } +}; + + +static void InitX86Settings() +{ + Ref<Settings> settings = Settings::Instance(); + settings->RegisterSetting("arch.x86.disassembly.syntax", + R"({ + "title" : "x86 Disassembly Syntax", + "type" : "string", + "default" : "BN_INTEL", + "aliases" : ["arch.x86.disassemblyFlavor"], + "description" : "Specify disassembly syntax for the x86/x86_64 architectures.", + "enum" : ["BN_INTEL", "INTEL", "AT&T"], + "enumDescriptions" : [ + "Sets the disassembly syntax to a simplified Intel format. (TBD) ", + "Sets the disassembly syntax to Intel format. (Destination on the left) ", + "Sets the disassembly syntax to AT&T format. (Destination on the right) "], + "ignore" : ["SettingsProjectScope", "SettingsResourceScope"] + })"); + + settings->RegisterSetting("arch.x86.disassembly.separator", + R"({ + "title" : "x86 Disassembly Separator", + "type" : "string", + "default" : ", ", + "aliases" : ["arch.x86.disassemblySeperator", "arch.x86.disassemblySeparator"], + "description" : "Specify the token separator between operands.", + "ignore" : ["SettingsProjectScope", "SettingsResourceScope"] + })"); + + settings->RegisterSetting("arch.x86.disassembly.lowercase", + R"({ + "title" : "x86 Disassembly Case", + "type" : "boolean", + "default" : true, + "aliases" : ["arch.x86.disassemblyLowercase"], + "description" : "Specify the case for opcodes, operands, and registers.", + "ignore" : ["SettingsProjectScope", "SettingsResourceScope"] + })"); +} + + +extern "C" +{ + BN_DECLARE_CORE_ABI_VERSION + +#ifndef DEMO_VERSION + BINARYNINJAPLUGIN void CorePluginDependencies() + { + AddOptionalPluginDependency("view_elf"); + AddOptionalPluginDependency("view_macho"); + AddOptionalPluginDependency("view_pe"); + } +#endif + +#ifdef DEMO_VERSION + bool X86PluginInit() +#else + BINARYNINJAPLUGIN bool CorePluginInit() +#endif + { + InitX86Settings(); + + // XED Setup + xed_tables_init(); + X86CommonArchitecture::InitializeCachedTypes(); + + // Register the architectures in the global list of available architectures + Architecture* x16 = new X16Architecture(); + Architecture::Register(x16); + + Architecture* x86 = new X86Architecture(); + Architecture::Register(x86); + + Architecture* x64 = new X64Architecture(); + Architecture::Register(x64); + + // Register calling conventions + Ref<CallingConvention> conv; + conv = new X86CdeclCallingConvention(x86); + x86->RegisterCallingConvention(conv); + x86->SetDefaultCallingConvention(conv); + x86->SetCdeclCallingConvention(conv); + conv = new X86StdcallCallingConvention(x86); + x86->RegisterCallingConvention(conv); + x86->SetStdcallCallingConvention(conv); + conv = new X86RegParmCallingConvention(x86); + x86->RegisterCallingConvention(conv); + conv = new X86FastcallCallingConvention(x86); + x86->RegisterCallingConvention(conv); + conv = new X86ThiscallCallingConvention(x86); + x86->RegisterCallingConvention(conv); + conv = new X86LinuxSystemCallConvention(x86); + x86->RegisterCallingConvention(conv); + + x86->RegisterRelocationHandler("Mach-O", new x86MachoRelocationHandler()); + x86->RegisterRelocationHandler("ELF", new x86ElfRelocationHandler()); + x86->RegisterRelocationHandler("COFF", new CoffRelocationHandler()); + x86->RegisterRelocationHandler("PE", new PeRelocationHandler()); + + conv = new X64SystemVCallingConvention(x64); + x64->RegisterCallingConvention(conv); + x64->SetDefaultCallingConvention(conv); + x64->SetCdeclCallingConvention(conv); + x64->SetFastcallCallingConvention(conv); + x64->SetStdcallCallingConvention(conv); + conv = new X64WindowsCallingConvention(x64); + x64->RegisterCallingConvention(conv); + conv = new X64LinuxSystemCallConvention(x64); + x64->RegisterCallingConvention(conv); + + x64->RegisterRelocationHandler("Mach-O", new x64MachoRelocationHandler()); + x64->RegisterRelocationHandler("ELF", new x64ElfRelocationHandler()); + x64->RegisterRelocationHandler("COFF", new CoffRelocationHandler()); + x64->RegisterRelocationHandler("PE", new PeRelocationHandler()); + + // Register the architectures with the binary format parsers so that they know when to use + // these architectures for disassembling an executable file + BinaryViewType::RegisterArchitecture("ELF", 3, LittleEndian, x86); + BinaryViewType::RegisterArchitecture("COFF", 0x14c, LittleEndian, x86); + BinaryViewType::RegisterArchitecture("PE", 0x14c, LittleEndian, x86); + BinaryViewType::RegisterArchitecture("Mach-O", 0x00000007, LittleEndian, x86); + + BinaryViewType::RegisterArchitecture("ELF", 62, LittleEndian, x64); + BinaryViewType::RegisterArchitecture("COFF", 0x8664, LittleEndian, x64); + BinaryViewType::RegisterArchitecture("PE", 0x8664, LittleEndian, x64); + BinaryViewType::RegisterArchitecture("Mach-O", 0x01000007, LittleEndian, x64); + + return true; + } +} diff --git a/arch/x86/arch_x86_common_architecture.h b/arch/x86/arch_x86_common_architecture.h new file mode 100644 index 00000000..97e349ea --- /dev/null +++ b/arch/x86/arch_x86_common_architecture.h @@ -0,0 +1,110 @@ +#define _CRT_SECURE_NO_WARNINGS +#include <inttypes.h> +#include <stdio.h> +#include <string.h> +#include <sstream> +#include "binaryninjaapi.h" +#include "il.h" +extern "C" { + #include "xed-interface.h" +} + +using namespace BinaryNinja; +using namespace std; + +typedef struct +{ + vector<NameAndType> input; + vector<Confidence<Ref<Type>>> output; +} IntrinsicInputAndOuput; + +class X86CommonArchitecture: public Architecture +{ +protected: + const size_t m_bits; + DISASSEMBLY_OPTIONS m_disassembly_options; + + bool Decode(const uint8_t* data, size_t len, xed_decoded_inst_t* xedd); + + size_t GetAddressSizeBits() const; + uint64_t GetAddressMask() const; + + void SetInstructionInfoForInstruction(uint64_t addr, InstructionInfo& result, xed_decoded_inst_t* xedd); + bool IsConditionalJump(xed_decoded_inst_t* xedd); + string GetSizeString(const size_t size) const; + + BNRegisterInfo RegisterInfo(xed_reg_enum_t fullWidthReg, size_t offset, size_t size, bool zeroExtend = false); + static void GetAddressSizeToken(const short bytes, vector<InstructionTextToken>& result, const bool lowerCase); + unsigned short GetInstructionOpcode(const xed_decoded_inst_t* const xedd, + const xed_operand_values_t* const ov, vector<InstructionTextToken>& result) const; + void GetInstructionPadding(const unsigned int instruction_name_length, vector<InstructionTextToken>& result) const; + void GetOperandTextIntel(const xed_decoded_inst_t* const xedd, const uint64_t addr,const size_t len, + const xed_operand_values_t* const ov, const xed_inst_t* const xi, vector<InstructionTextToken>& result) const; + void GetOperandTextBNIntel(const xed_decoded_inst_t* const xedd, const uint64_t addr, const size_t len, + const xed_operand_values_t* const ov, const xed_inst_t* const xi, vector<InstructionTextToken>& result) const; + void GetOperandTextATT(const xed_decoded_inst_t* const xedd, const uint64_t addr, const size_t len, + const xed_operand_values_t* const ov, const xed_inst_t* const xi, vector<InstructionTextToken>& result) const; + void GetOperandTextXED(const xed_decoded_inst_t* const xedd, const uint64_t addr, const size_t, + const xed_operand_values_t* const, const xed_inst_t* const, vector<InstructionTextToken>& result) const; + void GetOperandText(const xed_decoded_inst_t* const xedd, const uint64_t addr, const size_t len, + const xed_operand_values_t* const ov, const xed_inst_t* const xi, vector<InstructionTextToken>& result) const; + + +public: + X86CommonArchitecture(const string& name, size_t bits); + virtual BNEndianness GetEndianness() const override; + virtual vector<uint32_t> GetGlobalRegisters() override; + virtual vector<uint32_t> GetSystemRegisters() override; + virtual bool GetInstructionInfo(const uint8_t* data, uint64_t addr, size_t maxLen, InstructionInfo& result) override; + virtual bool GetInstructionText(const uint8_t* data, uint64_t addr, size_t& len, vector<InstructionTextToken>& result) override; + + virtual bool GetInstructionLowLevelIL(const uint8_t* data, uint64_t addr, size_t& len, LowLevelILFunction& il) override; + virtual size_t GetFlagWriteLowLevelIL(BNLowLevelILOperation op, size_t size, uint32_t flagWriteType, + uint32_t flag, BNRegisterOrConstant* operands, size_t operandCount, LowLevelILFunction& il) override; + virtual size_t GetSemanticFlagGroupLowLevelIL(uint32_t semGroup, LowLevelILFunction& il) override; + + virtual string GetRegisterName(uint32_t reg) override; + virtual string GetFlagName(uint32_t flag) override; + virtual vector<uint32_t> GetAllFlags() override; + virtual string GetSemanticFlagClassName(uint32_t semClass) override; + virtual vector<uint32_t> GetAllSemanticFlagClasses() override; + virtual string GetSemanticFlagGroupName(uint32_t semGroup) override; + virtual vector<uint32_t> GetAllSemanticFlagGroups() override; + virtual string GetFlagWriteTypeName(uint32_t flags) override; + virtual uint32_t GetSemanticClassForFlagWriteType(uint32_t writeType) override; + virtual vector<uint32_t> GetAllFlagWriteTypes() override; + virtual BNFlagRole GetFlagRole(uint32_t flag, uint32_t semClass) override; + virtual vector<uint32_t> GetFlagsRequiredForFlagCondition(BNLowLevelILFlagCondition cond, uint32_t semClass) override; + virtual vector<uint32_t> GetFlagsRequiredForSemanticFlagGroup(uint32_t semGroup) override; + virtual map<uint32_t, BNLowLevelILFlagCondition> GetFlagConditionsForSemanticFlagGroup(uint32_t semGroup) override; + virtual vector<uint32_t> GetFlagsWrittenByFlagWriteType(uint32_t writeType) override; + virtual string GetRegisterStackName(uint32_t regStack) override; + virtual vector<uint32_t> GetAllRegisterStacks() override; + virtual BNRegisterStackInfo GetRegisterStackInfo(uint32_t regStack) override; + + virtual BNIntrinsicClass GetIntrinsicClass(uint32_t intrinsic) override; + virtual string GetIntrinsicName(uint32_t intrinsic) override; + virtual vector<uint32_t> GetAllIntrinsics() override; + virtual vector<NameAndType> GetIntrinsicInputs(uint32_t intrinsic) override; + virtual vector<Confidence<Ref<Type>>> GetIntrinsicOutputs(uint32_t intrinsic) override; + + virtual bool CanAssemble() override; + virtual bool Assemble(const string& code, uint64_t addr, DataBuffer& result, string& errors) override; + virtual bool IsNeverBranchPatchAvailable(const uint8_t* data, uint64_t, size_t len) override; + virtual bool IsAlwaysBranchPatchAvailable(const uint8_t* data, uint64_t, size_t len) override; + virtual bool IsInvertBranchPatchAvailable(const uint8_t* data, uint64_t, size_t len) override; + virtual bool IsSkipAndReturnZeroPatchAvailable(const uint8_t* data, uint64_t, size_t len) override; + virtual bool IsSkipAndReturnValuePatchAvailable(const uint8_t* data, uint64_t, size_t len) override; + virtual bool ConvertToNop(uint8_t* data, uint64_t, size_t len) override; + size_t FindOpcodeOffset(const uint8_t* data, size_t len); + virtual bool AlwaysBranch(uint8_t* data, uint64_t, size_t len) override; + virtual bool InvertBranch(uint8_t* data, uint64_t, size_t len) override; + virtual bool SkipAndReturnValue(uint8_t* data, uint64_t, size_t len, uint64_t value) override; + + static void InitializeCachedTypes(); + static void InitializeCachedInputTypes(); + static void InitializeCachedOutputTypes(); + + inline static vector<NameAndType> *cached_input_types; + inline static vector<Confidence<Ref<Type>>> *cached_output_types; +}; diff --git a/arch/x86/arch_x86_intrinsics.cpp b/arch/x86/arch_x86_intrinsics.cpp new file mode 100644 index 00000000..b229c7f6 --- /dev/null +++ b/arch/x86/arch_x86_intrinsics.cpp @@ -0,0 +1,5260 @@ +#define _CRT_SECURE_NO_WARNINGS +#include <inttypes.h> +#include <stdio.h> +#include <string.h> +#include <sstream> +#include "binaryninjaapi.h" +#include "il.h" +extern "C" { + #include "xed-interface.h" +} +#include "arch_x86_common_architecture.h" + +using namespace BinaryNinja; +using namespace std; + +BNIntrinsicClass X86CommonArchitecture::GetIntrinsicClass(uint32_t intrinsic) +{ + switch (intrinsic) + { + case INTRINSIC_XED_IFORM_REP_MOVSB: + case INTRINSIC_XED_IFORM_REP_MOVSW: + case INTRINSIC_XED_IFORM_REP_MOVSD: + case INTRINSIC_XED_IFORM_REP_MOVSQ: + case INTRINSIC_XED_IFORM_REP_STOSB: + case INTRINSIC_XED_IFORM_REP_STOSW: + case INTRINSIC_XED_IFORM_REP_STOSD: + case INTRINSIC_XED_IFORM_REP_STOSQ: + return MemoryIntrinsicClass; + default: + return GeneralIntrinsicClass; + } +} + +string X86CommonArchitecture::GetIntrinsicName(uint32_t intrinsic) +{ + switch (intrinsic) + { + case INTRINSIC_F2XM1: + return "__f2xm1"; + case INTRINSIC_FBLD: + return "__fbld"; + case INTRINSIC_FBST: + return "__fbst"; + case INTRINSIC_FSIN: + return "__fsin"; + case INTRINSIC_FCOS: + return "__fcos"; + case INTRINSIC_FSINCOS: + return "__fsincos"; + case INTRINSIC_FPATAN: + return "__fpatan"; + case INTRINSIC_FPREM: + return "__fprem"; + case INTRINSIC_FPREM1: + return "__fprem1"; + case INTRINSIC_FPTAN: + return "__fptan"; + case INTRINSIC_FSCALE: + return "__fscale"; + case INTRINSIC_FXAM: + return "__fxam"; + case INTRINSIC_FXTRACT: + return "__fxtract"; + case INTRINSIC_FYL2X: + return "__fyl2x"; + case INTRINSIC_FYL2XP1: + return "__fyl2xp1"; + case INTRINSIC_XED_IFORM_ADCX_GPR32d_GPR32d: + return "_addcarryx_u32"; + case INTRINSIC_XED_IFORM_ADOX_GPR32d_GPR32d: + return "_addcarryx_u32"; + case INTRINSIC_XED_IFORM_ADCX_GPR64q_GPR64q: + return "_addcarryx_u64"; + case INTRINSIC_XED_IFORM_ADOX_GPR64q_GPR64q: + return "_addcarryx_u64"; + case INTRINSIC_XED_IFORM_AESENC_XMMdq_XMMdq: + return "_mm_aesenc_si128"; + case INTRINSIC_XED_IFORM_AESENCLAST_XMMdq_XMMdq: + return "_mm_aesenclast_si128"; + case INTRINSIC_XED_IFORM_AESDEC_XMMdq_XMMdq: + return "_mm_aesdec_si128"; + case INTRINSIC_XED_IFORM_AESDECLAST_XMMdq_XMMdq: + return "_mm_aesdeclast_si128"; + case INTRINSIC_XED_IFORM_AESIMC_XMMdq_XMMdq: + return "_mm_aesimc_si128"; + case INTRINSIC_XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb: + return "_mm_aeskeygenassist_si128"; + // case INTRINSIC_XED_IFORM_TDPBF16PS_TMMf32_TMMu32_TMMu32: + // return "_tile_dpbf16ps"; + // case INTRINSIC_XED_IFORM_TDPBSUD_TMMi32_TMMu32_TMMu32: + // return "_tile_dpbsud"; + // case INTRINSIC_XED_IFORM_TDPBUSD_TMMi32_TMMu32_TMMu32: + // return "_tile_dpbusd"; + // case INTRINSIC_XED_IFORM_TDPBUUD_TMMu32_TMMu32_TMMu32: + // return "_tile_dpbuud"; + // case INTRINSIC_XED_IFORM_TDPBSSD_TMMi32_TMMu32_TMMu32: + // return "_tile_dpbssd"; + // case INTRINSIC_XED_IFORM_LDTILECFG_MEM: + // return "_tile_loadconfig"; + // case INTRINSIC_XED_IFORM_STTILECFG_MEM: + // return "_tile_storeconfig"; + // case INTRINSIC_XED_IFORM_TILELOADD_TMMu32_MEMu32: + // return "_tile_loadd"; + // case INTRINSIC_XED_IFORM_TILELOADDT1_TMMu32_MEMu32: + // return "_tile_stream_loadd"; + // case INTRINSIC_XED_IFORM_TILERELEASE: + // return "_tile_release"; + // case INTRINSIC_XED_IFORM_TILESTORED_MEMu32_TMMu32: + // return "_tile_stored"; + // case INTRINSIC_XED_IFORM_TILEZERO_TMMu32: + // return "_tile_zero"; + case INTRINSIC_XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq: + return "_mm256_add_pd"; + case INTRINSIC_XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq: + return "_mm256_add_ps"; + case INTRINSIC_XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq: + return "_mm256_addsub_pd"; + case INTRINSIC_XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq: + return "_mm256_addsub_ps"; + case INTRINSIC_XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq: + return "_mm256_and_pd"; + case INTRINSIC_XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq: + return "_mm256_and_ps"; + case INTRINSIC_XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq: + return "_mm256_andnot_pd"; + case INTRINSIC_XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq: + return "_mm256_andnot_ps"; + case INTRINSIC_XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb: + return "_mm256_blend_pd"; + case INTRINSIC_XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb: + return "_mm256_blend_ps"; + case INTRINSIC_XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq: + return "_mm256_blendv_pd"; + case INTRINSIC_XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq: + return "_mm256_blendv_ps"; + case INTRINSIC_XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq: + return "_mm256_div_pd"; + case INTRINSIC_XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq: + return "_mm256_div_ps"; + case INTRINSIC_XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb: + return "_mm256_dp_ps"; + case INTRINSIC_XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq: + return "_mm256_hadd_pd"; + case INTRINSIC_XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq: + return "_mm256_hadd_ps"; + case INTRINSIC_XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq: + return "_mm256_hsub_pd"; + case INTRINSIC_XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq: + return "_mm256_hsub_ps"; + case INTRINSIC_XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq: + return "_mm256_max_pd"; + case INTRINSIC_XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq: + return "_mm256_max_ps"; + case INTRINSIC_XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq: + return "_mm256_min_pd"; + case INTRINSIC_XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq: + return "_mm256_min_ps"; + case INTRINSIC_XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq: + return "_mm256_mul_pd"; + case INTRINSIC_XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq: + return "_mm256_mul_ps"; + case INTRINSIC_XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq: + return "_mm256_or_pd"; + case INTRINSIC_XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq: + return "_mm256_or_ps"; + case INTRINSIC_XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb: + return "_mm256_shuffle_pd"; + case INTRINSIC_XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb: + return "_mm256_shuffle_ps"; + case INTRINSIC_XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq: + return "_mm256_sub_pd"; + case INTRINSIC_XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq: + return "_mm256_sub_ps"; + case INTRINSIC_XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq: + return "_mm256_xor_pd"; + case INTRINSIC_XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq: + return "_mm256_xor_ps"; + case INTRINSIC_XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb: + return "_mm_cmp_pd"; + case INTRINSIC_XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb: + return "_mm256_cmp_pd"; + case INTRINSIC_XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb: + return "_mm_cmp_ps"; + case INTRINSIC_XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb: + return "_mm256_cmp_ps"; + case INTRINSIC_XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb: + return "_mm_cmp_sd"; + case INTRINSIC_XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb: + return "_mm_cmp_ss"; + case INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq: + return "_mm256_cvtepi32_pd"; + case INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq: + return "_mm256_cvtepi32_ps"; + case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_YMMqq: + return "_mm256_cvtpd_ps"; + case INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq: + return "_mm256_cvtps_epi32"; + case INTRINSIC_XED_IFORM_VCVTPS2PD_YMMqq_XMMdq: + return "_mm256_cvtps_pd"; + case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq: + return "_mm256_cvttpd_epi32"; + case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq: + return "_mm256_cvtpd_epi32"; + case INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq: + return "_mm256_cvttps_epi32"; + case INTRINSIC_XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb: + return "_mm256_extractf128_ps"; + case INTRINSIC_XED_IFORM_VZEROALL: + return "_mm256_zeroall"; + case INTRINSIC_XED_IFORM_VZEROUPPER: + return "_mm256_zeroupper"; + case INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq: + return "_mm256_permutevar_ps"; + case INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq: + return "_mm_permutevar_ps"; + case INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb: + return "_mm256_permute_ps"; + case INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb: + return "_mm_permute_ps"; + case INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq: + return "_mm256_permutevar_pd"; + case INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq: + return "_mm_permutevar_pd"; + case INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb: + return "_mm256_permute_pd"; + case INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb: + return "_mm_permute_pd"; + case INTRINSIC_XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb: + return "_mm256_permute2f128_ps"; + case INTRINSIC_XED_IFORM_VBROADCASTSS_YMMqq_MEMd: + return "_mm256_broadcast_ss"; + case INTRINSIC_XED_IFORM_VBROADCASTSS_XMMdq_MEMd: + return "_mm_broadcast_ss"; + case INTRINSIC_XED_IFORM_VBROADCASTSD_YMMqq_MEMq: + return "_mm256_broadcast_sd"; + case INTRINSIC_XED_IFORM_VBROADCASTF128_YMMqq_MEMdq: + return "_mm256_broadcast_ps"; + case INTRINSIC_XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb: + return "_mm256_insertf128_ps"; + case INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_MEMqq: + return "_mm256_load_pd"; + case INTRINSIC_XED_IFORM_VMOVAPD_MEMqq_YMMqq: + return "_mm256_store_pd"; + case INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_MEMqq: + return "_mm256_load_ps"; + case INTRINSIC_XED_IFORM_VMOVAPS_MEMqq_YMMqq: + return "_mm256_store_ps"; + case INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_MEMqq: + return "_mm256_loadu_pd"; + case INTRINSIC_XED_IFORM_VMOVUPD_MEMqq_YMMqq: + return "_mm256_storeu_pd"; + case INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_MEMqq: + return "_mm256_loadu_ps"; + case INTRINSIC_XED_IFORM_VMOVUPS_MEMqq_YMMqq: + return "_mm256_storeu_ps"; + case INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_MEMqq: + return "_mm256_load_si256"; + case INTRINSIC_XED_IFORM_VMOVDQA_MEMqq_YMMqq: + return "_mm256_store_si256"; + case INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_MEMqq: + return "_mm256_loadu_si256"; + case INTRINSIC_XED_IFORM_VMOVDQU_MEMqq_YMMqq: + return "_mm256_storeu_si256"; + case INTRINSIC_XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq: + return "_mm256_maskload_pd"; + case INTRINSIC_XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq: + return "_mm256_maskstore_pd"; + case INTRINSIC_XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq: + return "_mm_maskload_pd"; + case INTRINSIC_XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq: + return "_mm_maskstore_pd"; + case INTRINSIC_XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq: + return "_mm256_maskload_ps"; + case INTRINSIC_XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq: + return "_mm256_maskstore_ps"; + case INTRINSIC_XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq: + return "_mm_maskload_ps"; + case INTRINSIC_XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq: + return "_mm_maskstore_ps"; + case INTRINSIC_XED_IFORM_VMOVSHDUP_YMMqq_YMMqq: + return "_mm256_movehdup_ps"; + case INTRINSIC_XED_IFORM_VMOVSLDUP_YMMqq_YMMqq: + return "_mm256_moveldup_ps"; + case INTRINSIC_XED_IFORM_VMOVDDUP_YMMqq_YMMqq: + return "_mm256_movedup_pd"; + case INTRINSIC_XED_IFORM_VLDDQU_YMMqq_MEMqq: + return "_mm256_lddqu_si256"; + case INTRINSIC_XED_IFORM_VMOVNTDQ_MEMqq_YMMqq: + return "_mm256_stream_si256"; + case INTRINSIC_XED_IFORM_VMOVNTPD_MEMqq_YMMqq: + return "_mm256_stream_pd"; + case INTRINSIC_XED_IFORM_VMOVNTPS_MEMqq_YMMqq: + return "_mm256_stream_ps"; + case INTRINSIC_XED_IFORM_VRCPPS_YMMqq_YMMqq: + return "_mm256_rcp_ps"; + case INTRINSIC_XED_IFORM_VRSQRTPS_YMMqq_YMMqq: + return "_mm256_rsqrt_ps"; + case INTRINSIC_XED_IFORM_VSQRTPD_YMMqq_YMMqq: + return "_mm256_sqrt_pd"; + case INTRINSIC_XED_IFORM_VSQRTPS_YMMqq_YMMqq: + return "_mm256_sqrt_ps"; + case INTRINSIC_XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb: + return "_mm256_round_pd"; + case INTRINSIC_XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb: + return "_mm256_round_ps"; + case INTRINSIC_XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq: + return "_mm256_unpackhi_pd"; + case INTRINSIC_XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq: + return "_mm256_unpackhi_ps"; + case INTRINSIC_XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq: + return "_mm256_unpacklo_pd"; + case INTRINSIC_XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq: + return "_mm256_unpacklo_ps"; + case INTRINSIC_XED_IFORM_VPTEST_YMMqq_YMMqq: + return "_mm256_testz_si256"; + case INTRINSIC_XED_IFORM_VTESTPD_YMMqq_YMMqq: + return "_mm256_testz_pd"; + case INTRINSIC_XED_IFORM_VTESTPD_XMMdq_XMMdq: + return "_mm_testz_pd"; + case INTRINSIC_XED_IFORM_VTESTPS_YMMqq_YMMqq: + return "_mm256_testz_ps"; + case INTRINSIC_XED_IFORM_VTESTPS_XMMdq_XMMdq: + return "_mm_testz_ps"; + case INTRINSIC_XED_IFORM_VMOVMSKPD_GPR32d_YMMqq: + return "_mm256_movemask_pd"; + case INTRINSIC_XED_IFORM_VMOVMSKPS_GPR32d_YMMqq: + return "_mm256_movemask_ps"; + case INTRINSIC_XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq: + return "_mm256_setzero_si256"; + case INTRINSIC_XED_IFORM_VMOVSS_MEMd_XMMd: + return "_mm256_cvtss_f32"; + case INTRINSIC_XED_IFORM_VMOVSD_MEMq_XMMq: + return "_mm256_cvtsd_f64"; + case INTRINSIC_XED_IFORM_VMOVD_GPR32d_XMMd: + return "_mm256_cvtsi256_si32"; + case INTRINSIC_XED_IFORM_VPABSB_YMMqq_YMMqq: + return "_mm256_abs_epi8"; + case INTRINSIC_XED_IFORM_VPABSW_YMMqq_YMMqq: + return "_mm256_abs_epi16"; + case INTRINSIC_XED_IFORM_VPABSD_YMMqq_YMMqq: + return "_mm256_abs_epi32"; + case INTRINSIC_XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq: + return "_mm256_add_epi8"; + case INTRINSIC_XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq: + return "_mm256_add_epi16"; + case INTRINSIC_XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq: + return "_mm256_add_epi32"; + case INTRINSIC_XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq: + return "_mm256_add_epi64"; + case INTRINSIC_XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq: + return "_mm256_adds_epi8"; + case INTRINSIC_XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq: + return "_mm256_adds_epi16"; + case INTRINSIC_XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq: + return "_mm256_adds_epu8"; + case INTRINSIC_XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq: + return "_mm256_adds_epu16"; + case INTRINSIC_XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb: + return "_mm256_alignr_epi8"; + case INTRINSIC_XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq: + return "_mm256_and_si256"; + case INTRINSIC_XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq: + return "_mm256_andnot_si256"; + case INTRINSIC_XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq: + return "_mm256_avg_epu8"; + case INTRINSIC_XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq: + return "_mm256_avg_epu16"; + case INTRINSIC_XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb: + return "_mm256_blend_epi16"; + case INTRINSIC_XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb: + return "_mm_blend_epi32"; + case INTRINSIC_XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb: + return "_mm256_blend_epi32"; + case INTRINSIC_XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq: + return "_mm256_blendv_epi8"; + case INTRINSIC_XED_IFORM_VPBROADCASTB_XMMdq_XMMb: + return "_mm_broadcastb_epi8"; + case INTRINSIC_XED_IFORM_VPBROADCASTB_YMMqq_XMMb: + return "_mm256_broadcastb_epi8"; + case INTRINSIC_XED_IFORM_VPBROADCASTD_XMMdq_XMMd: + return "_mm_broadcastd_epi32"; + case INTRINSIC_XED_IFORM_VPBROADCASTD_YMMqq_XMMd: + return "_mm256_broadcastd_epi32"; + case INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMdq_XMMq: + return "_mm_broadcastq_epi64"; + case INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMqq_XMMq: + return "_mm256_broadcastq_epi64"; + case INTRINSIC_XED_IFORM_MOVDDUP_XMMdq_XMMq: + return "_mm_broadcastsd_pd"; + case INTRINSIC_XED_IFORM_VBROADCASTSD_YMMqq_XMMdq: + return "_mm256_broadcastsd_pd"; + case INTRINSIC_XED_IFORM_VBROADCASTI128_YMMqq_MEMdq: + return "_mm_broadcastsi128_si256"; + case INTRINSIC_XED_IFORM_VBROADCASTSS_XMMdq_XMMdq: + return "_mm_broadcastss_ps"; + case INTRINSIC_XED_IFORM_VBROADCASTSS_YMMqq_XMMdq: + return "_mm256_broadcastss_ps"; + case INTRINSIC_XED_IFORM_VPBROADCASTW_XMMdq_XMMw: + return "_mm_broadcastw_epi16"; + case INTRINSIC_XED_IFORM_VPBROADCASTW_YMMqq_XMMw: + return "_mm256_broadcastw_epi16"; + case INTRINSIC_XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq: + return "_mm256_cmpeq_epi8"; + case INTRINSIC_XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq: + return "_mm256_cmpeq_epi16"; + case INTRINSIC_XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq: + return "_mm256_cmpeq_epi32"; + case INTRINSIC_XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq: + return "_mm256_cmpeq_epi64"; + case INTRINSIC_XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq: + return "_mm256_cmpgt_epi8"; + case INTRINSIC_XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq: + return "_mm256_cmpgt_epi16"; + case INTRINSIC_XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq: + return "_mm256_cmpgt_epi32"; + case INTRINSIC_XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq: + return "_mm256_cmpgt_epi64"; + case INTRINSIC_XED_IFORM_VPMOVSXWD_YMMqq_XMMdq: + return "_mm256_cvtepi16_epi32"; + case INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMqq_XMMq: + return "_mm256_cvtepi16_epi64"; + case INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq: + return "_mm256_cvtepi32_epi64"; + case INTRINSIC_XED_IFORM_VPMOVSXBW_YMMqq_XMMdq: + return "_mm256_cvtepi8_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSXBD_YMMqq_XMMq: + return "_mm256_cvtepi8_epi32"; + case INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMqq_XMMd: + return "_mm256_cvtepi8_epi64"; + case INTRINSIC_XED_IFORM_VPMOVZXWD_YMMqq_XMMdq: + return "_mm256_cvtepu16_epi32"; + case INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMqq_XMMq: + return "_mm256_cvtepu16_epi64"; + case INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq: + return "_mm256_cvtepu32_epi64"; + case INTRINSIC_XED_IFORM_VPMOVZXBW_YMMqq_XMMdq: + return "_mm256_cvtepu8_epi16"; + case INTRINSIC_XED_IFORM_VPMOVZXBD_YMMqq_XMMq: + return "_mm256_cvtepu8_epi32"; + case INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMqq_XMMd: + return "_mm256_cvtepu8_epi64"; + case INTRINSIC_XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb: + return "_mm256_extracti128_si256"; + case INTRINSIC_XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq: + return "_mm256_hadd_epi16"; + case INTRINSIC_XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq: + return "_mm256_hadd_epi32"; + case INTRINSIC_XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq: + return "_mm256_hadds_epi16"; + case INTRINSIC_XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq: + return "_mm256_hsub_epi16"; + case INTRINSIC_XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq: + return "_mm256_hsub_epi32"; + case INTRINSIC_XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq: + return "_mm256_hsubs_epi16"; + case INTRINSIC_XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128: + return "_mm_i32gather_pd"; + case INTRINSIC_XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256: + return "_mm256_i32gather_pd"; + case INTRINSIC_XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128: + return "_mm_i32gather_ps"; + case INTRINSIC_XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256: + return "_mm256_i32gather_ps"; + case INTRINSIC_XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128: + return "_mm_i32gather_epi32"; + case INTRINSIC_XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256: + return "_mm256_i32gather_epi32"; + case INTRINSIC_XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128: + return "_mm_i32gather_epi64"; + case INTRINSIC_XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256: + return "_mm256_i32gather_epi64"; + case INTRINSIC_XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128: + return "_mm_i64gather_pd"; + case INTRINSIC_XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256: + return "_mm256_i64gather_pd"; + case INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128: + return "_mm_i64gather_ps"; + case INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256: + return "_mm256_i64gather_ps"; + case INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128: + return "_mm_i64gather_epi32"; + case INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256: + return "_mm256_i64gather_epi32"; + case INTRINSIC_XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128: + return "_mm_i64gather_epi64"; + case INTRINSIC_XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256: + return "_mm256_i64gather_epi64"; + case INTRINSIC_XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb: + return "_mm256_inserti128_si256"; + case INTRINSIC_XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq: + return "_mm256_madd_epi16"; + case INTRINSIC_XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq: + return "_mm256_maddubs_epi16"; + case INTRINSIC_XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq: + return "_mm_maskload_epi32"; + case INTRINSIC_XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq: + return "_mm256_maskload_epi32"; + case INTRINSIC_XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq: + return "_mm_maskload_epi64"; + case INTRINSIC_XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq: + return "_mm256_maskload_epi64"; + case INTRINSIC_XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq: + return "_mm_maskstore_epi32"; + case INTRINSIC_XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq: + return "_mm256_maskstore_epi32"; + case INTRINSIC_XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq: + return "_mm_maskstore_epi64"; + case INTRINSIC_XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq: + return "_mm256_maskstore_epi64"; + case INTRINSIC_XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq: + return "_mm256_max_epi8"; + case INTRINSIC_XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq: + return "_mm256_max_epi16"; + case INTRINSIC_XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq: + return "_mm256_max_epi32"; + case INTRINSIC_XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq: + return "_mm256_max_epu8"; + case INTRINSIC_XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq: + return "_mm256_max_epu16"; + case INTRINSIC_XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq: + return "_mm256_max_epu32"; + case INTRINSIC_XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq: + return "_mm256_min_epi8"; + case INTRINSIC_XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq: + return "_mm256_min_epi16"; + case INTRINSIC_XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq: + return "_mm256_min_epi32"; + case INTRINSIC_XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq: + return "_mm256_min_epu8"; + case INTRINSIC_XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq: + return "_mm256_min_epu16"; + case INTRINSIC_XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq: + return "_mm256_min_epu32"; + case INTRINSIC_XED_IFORM_VPMOVMSKB_GPR32d_YMMqq: + return "_mm256_movemask_epi8"; + case INTRINSIC_XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb: + return "_mm256_mpsadbw_epu8"; + case INTRINSIC_XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq: + return "_mm256_mul_epi32"; + case INTRINSIC_XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq: + return "_mm256_mul_epu32"; + case INTRINSIC_XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq: + return "_mm256_mulhi_epi16"; + case INTRINSIC_XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq: + return "_mm256_mulhi_epu16"; + case INTRINSIC_XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq: + return "_mm256_mulhrs_epi16"; + case INTRINSIC_XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq: + return "_mm256_mullo_epi16"; + case INTRINSIC_XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq: + return "_mm256_mullo_epi32"; + case INTRINSIC_XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq: + return "_mm256_or_si256"; + case INTRINSIC_XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq: + return "_mm256_packs_epi16"; + case INTRINSIC_XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq: + return "_mm256_packs_epi32"; + case INTRINSIC_XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq: + return "_mm256_packus_epi16"; + case INTRINSIC_XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq: + return "_mm256_packus_epi32"; + case INTRINSIC_XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb: + return "_mm256_permute2x128_si256"; + case INTRINSIC_XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb: + return "_mm256_permute4x64_epi64"; + case INTRINSIC_XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb: + return "_mm256_permute4x64_pd"; + case INTRINSIC_XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq: + return "_mm256_permutevar8x32_epi32"; + case INTRINSIC_XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq: + return "_mm256_permutevar8x32_ps"; + case INTRINSIC_XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq: + return "_mm256_sad_epu8"; + case INTRINSIC_XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb: + return "_mm256_shuffle_epi32"; + case INTRINSIC_XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq: + return "_mm256_shuffle_epi8"; + case INTRINSIC_XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb: + return "_mm256_shufflehi_epi16"; + case INTRINSIC_XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb: + return "_mm256_shufflelo_epi16"; + case INTRINSIC_XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq: + return "_mm256_sign_epi8"; + case INTRINSIC_XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq: + return "_mm256_sign_epi16"; + case INTRINSIC_XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq: + return "_mm256_sign_epi32"; + case INTRINSIC_XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb: + return "_mm256_slli_si256"; + case INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq: + return "_mm256_sll_epi16"; + case INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb: + return "_mm256_slli_epi16"; + case INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq: + return "_mm256_sll_epi32"; + case INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb: + return "_mm256_slli_epi32"; + case INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq: + return "_mm256_sll_epi64"; + case INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb: + return "_mm256_slli_epi64"; + case INTRINSIC_XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq: + return "_mm_sllv_epi32"; + case INTRINSIC_XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq: + return "_mm256_sllv_epi32"; + case INTRINSIC_XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq: + return "_mm_sllv_epi64"; + case INTRINSIC_XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq: + return "_mm256_sllv_epi64"; + case INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq: + return "_mm256_sra_epi16"; + case INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb: + return "_mm256_srai_epi16"; + case INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq: + return "_mm256_sra_epi32"; + case INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb: + return "_mm256_srai_epi32"; + case INTRINSIC_XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq: + return "_mm_srav_epi32"; + case INTRINSIC_XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq: + return "_mm256_srav_epi32"; + case INTRINSIC_XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb: + return "_mm256_srli_si256"; + case INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq: + return "_mm256_srl_epi16"; + case INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb: + return "_mm256_srli_epi16"; + case INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq: + return "_mm256_srl_epi32"; + case INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb: + return "_mm256_srli_epi32"; + case INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq: + return "_mm256_srl_epi64"; + case INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb: + return "_mm256_srli_epi64"; + case INTRINSIC_XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq: + return "_mm_srlv_epi32"; + case INTRINSIC_XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq: + return "_mm256_srlv_epi32"; + case INTRINSIC_XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq: + return "_mm_srlv_epi64"; + case INTRINSIC_XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq: + return "_mm256_srlv_epi64"; + case INTRINSIC_XED_IFORM_VMOVNTDQA_YMMqq_MEMqq: + return "_mm256_stream_load_si256"; + case INTRINSIC_XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq: + return "_mm256_sub_epi8"; + case INTRINSIC_XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq: + return "_mm256_sub_epi16"; + case INTRINSIC_XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq: + return "_mm256_sub_epi32"; + case INTRINSIC_XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq: + return "_mm256_sub_epi64"; + case INTRINSIC_XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq: + return "_mm256_subs_epi8"; + case INTRINSIC_XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq: + return "_mm256_subs_epi16"; + case INTRINSIC_XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq: + return "_mm256_subs_epu8"; + case INTRINSIC_XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq: + return "_mm256_subs_epu16"; + case INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq: + return "_mm256_unpackhi_epi8"; + case INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq: + return "_mm256_unpackhi_epi16"; + case INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq: + return "_mm256_unpackhi_epi32"; + case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq: + return "_mm256_unpackhi_epi64"; + case INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq: + return "_mm256_unpacklo_epi8"; + case INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq: + return "_mm256_unpacklo_epi16"; + case INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq: + return "_mm256_unpacklo_epi32"; + case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq: + return "_mm256_unpacklo_epi64"; + case INTRINSIC_XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_mm512_kunpackd"; + case INTRINSIC_XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_mm512_kunpackw"; + case INTRINSIC_XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512: + return "_mm256_dbsad_epu8"; + case INTRINSIC_XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512: + return "_mm512_dbsad_epu8"; + case INTRINSIC_XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512: + return "_mm_dbsad_epu8"; + case INTRINSIC_XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512: + return "_mm256_mask_loadu_epi16"; + case INTRINSIC_XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512: + return "_mm256_mask_mov_epi16"; + case INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512: + return "_mm256_mask_storeu_epi16"; + case INTRINSIC_XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512: + return "_mm512_mask_loadu_epi16"; + case INTRINSIC_XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512: + return "_mm512_mask_mov_epi16"; + case INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512: + return "_mm512_mask_storeu_epi16"; + case INTRINSIC_XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512: + return "_mm_mask_loadu_epi16"; + case INTRINSIC_XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512: + return "_mm_mask_mov_epi16"; + case INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512: + return "_mm_mask_storeu_epi16"; + case INTRINSIC_XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512: + return "_mm256_mask_loadu_epi8"; + case INTRINSIC_XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512: + return "_mm256_mask_mov_epi8"; + case INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512: + return "_mm256_mask_storeu_epi8"; + case INTRINSIC_XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512: + return "_mm512_mask_loadu_epi8"; + case INTRINSIC_XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512: + return "_mm512_mask_mov_epi8"; + case INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512: + return "_mm512_mask_storeu_epi8"; + case INTRINSIC_XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512: + return "_mm_mask_loadu_epi8"; + case INTRINSIC_XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512: + return "_mm_mask_mov_epi8"; + case INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512: + return "_mm_mask_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512: + return "_mm256_mask_abs_epi8"; + case INTRINSIC_XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512: + return "_mm512_abs_epi8"; + case INTRINSIC_XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512: + return "_mm_mask_abs_epi8"; + case INTRINSIC_XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512: + return "_mm256_mask_abs_epi16"; + case INTRINSIC_XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512: + return "_mm512_abs_epi16"; + case INTRINSIC_XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512: + return "_mm_mask_abs_epi16"; + case INTRINSIC_XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512: + return "_mm256_mask_packs_epi32"; + case INTRINSIC_XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512: + return "_mm512_mask_packs_epi32"; + case INTRINSIC_XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512: + return "_mm_mask_packs_epi32"; + case INTRINSIC_XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512: + return "_mm256_mask_packs_epi16"; + case INTRINSIC_XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512: + return "_mm512_mask_packs_epi16"; + case INTRINSIC_XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512: + return "_mm_mask_packs_epi16"; + case INTRINSIC_XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_packus_epi32"; + case INTRINSIC_XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_mask_packus_epi32"; + case INTRINSIC_XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_packus_epi32"; + case INTRINSIC_XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_packus_epi16"; + case INTRINSIC_XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_packus_epi16"; + case INTRINSIC_XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_packus_epi16"; + case INTRINSIC_XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_mask_add_epi8"; + case INTRINSIC_XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_add_epi8"; + case INTRINSIC_XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_mask_add_epi8"; + case INTRINSIC_XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + return "_mm256_mask_adds_epi8"; + case INTRINSIC_XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + return "_mm512_adds_epi8"; + case INTRINSIC_XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + return "_mm_mask_adds_epi8"; + case INTRINSIC_XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return "_mm256_mask_adds_epi16"; + case INTRINSIC_XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return "_mm512_adds_epi16"; + case INTRINSIC_XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return "_mm_mask_adds_epi16"; + case INTRINSIC_XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_mask_adds_epu8"; + case INTRINSIC_XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_adds_epu8"; + case INTRINSIC_XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_mask_adds_epu8"; + case INTRINSIC_XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_adds_epu16"; + case INTRINSIC_XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_adds_epu16"; + case INTRINSIC_XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_adds_epu16"; + case INTRINSIC_XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_add_epi16"; + case INTRINSIC_XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_add_epi16"; + case INTRINSIC_XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_add_epi16"; + case INTRINSIC_XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512: + return "_mm256_mask_alignr_epi8"; + case INTRINSIC_XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512: + return "_mm512_alignr_epi8"; + case INTRINSIC_XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512: + return "_mm_mask_alignr_epi8"; + case INTRINSIC_XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_mask_avg_epu8"; + case INTRINSIC_XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_avg_epu8"; + case INTRINSIC_XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_mask_avg_epu8"; + case INTRINSIC_XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_avg_epu16"; + case INTRINSIC_XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_avg_epu16"; + case INTRINSIC_XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_avg_epu16"; + case INTRINSIC_XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_mask_blend_epi8"; + case INTRINSIC_XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_mask_blend_epi8"; + case INTRINSIC_XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_mask_blend_epi8"; + case INTRINSIC_XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_blend_epi16"; + case INTRINSIC_XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_blend_epi16"; + case INTRINSIC_XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_blend_epi16"; + case INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512: + return "_mm256_mask_broadcastb_epi8"; + case INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512: + return "_mm256_mask_set1_epi8"; + case INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512: + return "_mm512_broadcastb_epi8"; + case INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512: + return "_mm512_mask_set1_epi8"; + case INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512: + return "_mm_mask_broadcastb_epi8"; + case INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512: + return "_mm_mask_set1_epi8"; + case INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512: + return "_mm256_mask_broadcastw_epi16"; + case INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512: + return "_mm256_mask_set1_epi16"; + case INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512: + return "_mm512_broadcastw_epi16"; + case INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512: + return "_mm512_mask_set1_epi16"; + case INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512: + return "_mm_mask_broadcastw_epi16"; + case INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512: + return "_mm_mask_set1_epi16"; + case INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512: + return "_mm256_cmp_epi8_mask"; + case INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512: + return "_mm512_cmp_epi8_mask"; + case INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512: + return "_mm_cmp_epi8_mask"; + case INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512: + return "_mm256_cmp_epu8_mask"; + case INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512: + return "_mm512_cmp_epu8_mask"; + case INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512: + return "_mm_cmp_epu8_mask"; + case INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512: + return "_mm256_cmp_epu16_mask"; + case INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512: + return "_mm512_cmp_epu16_mask"; + case INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512: + return "_mm_cmp_epu16_mask"; + case INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512: + return "_mm256_cmp_epi16_mask"; + case INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512: + return "_mm512_cmp_epi16_mask"; + case INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512: + return "_mm_cmp_epi16_mask"; + case INTRINSIC_XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask2_permutex2var_epi16"; + case INTRINSIC_XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_permutex2var_epi16"; + case INTRINSIC_XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask2_permutex2var_epi16"; + case INTRINSIC_XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_permutex2var_epi16"; + case INTRINSIC_XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask2_permutex2var_epi16"; + case INTRINSIC_XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_permutex2var_epi16"; + case INTRINSIC_XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_permutexvar_epi16"; + case INTRINSIC_XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_permutexvar_epi16"; + case INTRINSIC_XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_permutexvar_epi16"; + case INTRINSIC_XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return "_mm256_mask_maddubs_epi16"; + case INTRINSIC_XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return "_mm512_maddubs_epi16"; + case INTRINSIC_XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return "_mm_mask_maddubs_epi16"; + case INTRINSIC_XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512: + return "_mm256_mask_madd_epi16"; + case INTRINSIC_XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512: + return "_mm512_madd_epi16"; + case INTRINSIC_XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512: + return "_mm_mask_madd_epi16"; + case INTRINSIC_XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + return "_mm256_mask_max_epi8"; + case INTRINSIC_XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + return "_mm512_mask_max_epi8"; + case INTRINSIC_XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + return "_mm_mask_max_epi8"; + case INTRINSIC_XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return "_mm256_mask_max_epi16"; + case INTRINSIC_XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return "_mm512_mask_max_epi16"; + case INTRINSIC_XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return "_mm_mask_max_epi16"; + case INTRINSIC_XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_mask_max_epu8"; + case INTRINSIC_XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_mask_max_epu8"; + case INTRINSIC_XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_mask_max_epu8"; + case INTRINSIC_XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_max_epu16"; + case INTRINSIC_XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_max_epu16"; + case INTRINSIC_XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_max_epu16"; + case INTRINSIC_XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + return "_mm256_mask_min_epi8"; + case INTRINSIC_XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + return "_mm512_mask_min_epi8"; + case INTRINSIC_XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + return "_mm_mask_min_epi8"; + case INTRINSIC_XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return "_mm256_mask_min_epi16"; + case INTRINSIC_XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return "_mm512_mask_min_epi16"; + case INTRINSIC_XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return "_mm_mask_min_epi16"; + case INTRINSIC_XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_mask_min_epu8"; + case INTRINSIC_XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_mask_min_epu8"; + case INTRINSIC_XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_mask_min_epu8"; + case INTRINSIC_XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_min_epu16"; + case INTRINSIC_XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_min_epu16"; + case INTRINSIC_XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_min_epu16"; + case INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512: + return "_mm256_movepi8_mask"; + case INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512: + return "_mm512_movepi8_mask"; + case INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512: + return "_mm_movepi8_mask"; + case INTRINSIC_XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512: + return "_mm256_movm_epi8"; + case INTRINSIC_XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512: + return "_mm512_movm_epi8"; + case INTRINSIC_XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512: + return "_mm_movm_epi8"; + case INTRINSIC_XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512: + return "_mm256_movm_epi16"; + case INTRINSIC_XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512: + return "_mm512_movm_epi16"; + case INTRINSIC_XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512: + return "_mm_movm_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512: + return "_mm256_cvtsepi16_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512: + return "_mm256_mask_cvtsepi16_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512: + return "_mm512_cvtsepi16_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512: + return "_mm512_mask_cvtsepi16_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512: + return "_mm_cvtsepi16_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512: + return "_mm_mask_cvtsepi16_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512: + return "_mm256_mask_cvtepi8_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512: + return "_mm512_cvtepi8_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512: + return "_mm_mask_cvtepi8_epi16"; + case INTRINSIC_XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512: + return "_mm256_cvtusepi16_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512: + return "_mm256_mask_cvtusepi16_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512: + return "_mm512_cvtusepi16_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512: + return "_mm512_mask_cvtusepi16_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512: + return "_mm_cvtusepi16_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512: + return "_mm_mask_cvtusepi16_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512: + return "_mm256_movepi16_mask"; + case INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512: + return "_mm512_movepi16_mask"; + case INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512: + return "_mm_movepi16_mask"; + case INTRINSIC_XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512: + return "_mm256_cvtepi16_epi8"; + case INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512: + return "_mm256_mask_cvtepi16_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512: + return "_mm512_cvtepi16_epi8"; + case INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512: + return "_mm512_mask_cvtepi16_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512: + return "_mm_cvtepi16_epi8"; + case INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512: + return "_mm_mask_cvtepi16_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512: + return "_mm256_mask_cvtepu8_epi16"; + case INTRINSIC_XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512: + return "_mm512_cvtepu8_epi16"; + case INTRINSIC_XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512: + return "_mm_mask_cvtepu8_epi16"; + case INTRINSIC_XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return "_mm256_mask_mulhrs_epi16"; + case INTRINSIC_XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return "_mm512_mask_mulhrs_epi16"; + case INTRINSIC_XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return "_mm_mask_mulhrs_epi16"; + case INTRINSIC_XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_mulhi_epu16"; + case INTRINSIC_XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_mulhi_epu16"; + case INTRINSIC_XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_mulhi_epu16"; + case INTRINSIC_XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_mulhi_epi16"; + case INTRINSIC_XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_mulhi_epi16"; + case INTRINSIC_XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_mulhi_epi16"; + case INTRINSIC_XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_mullo_epi16"; + case INTRINSIC_XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_mullo_epi16"; + case INTRINSIC_XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_mullo_epi16"; + case INTRINSIC_XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512: + return "_mm512_sad_epu8"; + case INTRINSIC_XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_mask_shuffle_epi8"; + case INTRINSIC_XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_mask_shuffle_epi8"; + case INTRINSIC_XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_mask_shuffle_epi8"; + case INTRINSIC_XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + return "_mm256_mask_shufflehi_epi16"; + case INTRINSIC_XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + return "_mm512_mask_shufflehi_epi16"; + case INTRINSIC_XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + return "_mm_mask_shufflehi_epi16"; + case INTRINSIC_XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + return "_mm256_mask_shufflelo_epi16"; + case INTRINSIC_XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + return "_mm512_mask_shufflelo_epi16"; + case INTRINSIC_XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + return "_mm_mask_shufflelo_epi16"; + case INTRINSIC_XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512: + return "_mm512_bslli_epi128"; + case INTRINSIC_XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_sllv_epi16"; + case INTRINSIC_XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_sllv_epi16"; + case INTRINSIC_XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_sllv_epi16"; + case INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512: + return "_mm256_mask_sll_epi16"; + case INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + return "_mm256_mask_slli_epi16"; + case INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512: + return "_mm512_mask_sll_epi16"; + case INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + return "_mm512_mask_slli_epi16"; + case INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_sll_epi16"; + case INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + return "_mm_mask_slli_epi16"; + case INTRINSIC_XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_srav_epi16"; + case INTRINSIC_XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_srav_epi16"; + case INTRINSIC_XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_srav_epi16"; + case INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512: + return "_mm256_mask_sra_epi16"; + case INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + return "_mm256_mask_srai_epi16"; + case INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512: + return "_mm512_mask_sra_epi16"; + case INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + return "_mm512_mask_srai_epi16"; + case INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_sra_epi16"; + case INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + return "_mm_mask_srai_epi16"; + case INTRINSIC_XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512: + return "_mm512_bsrli_epi128"; + case INTRINSIC_XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_srlv_epi16"; + case INTRINSIC_XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_srlv_epi16"; + case INTRINSIC_XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_srlv_epi16"; + case INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512: + return "_mm256_mask_srl_epi16"; + case INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + return "_mm256_mask_srli_epi16"; + case INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512: + return "_mm512_mask_srl_epi16"; + case INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + return "_mm512_mask_srli_epi16"; + case INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_srl_epi16"; + case INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + return "_mm_mask_srli_epi16"; + case INTRINSIC_XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_mask_sub_epi8"; + case INTRINSIC_XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_mask_sub_epi8"; + case INTRINSIC_XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_mask_sub_epi8"; + case INTRINSIC_XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + return "_mm256_mask_subs_epi8"; + case INTRINSIC_XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + return "_mm512_mask_subs_epi8"; + case INTRINSIC_XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + return "_mm_mask_subs_epi8"; + case INTRINSIC_XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return "_mm256_mask_subs_epi16"; + case INTRINSIC_XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return "_mm512_mask_subs_epi16"; + case INTRINSIC_XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return "_mm_mask_subs_epi16"; + case INTRINSIC_XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_mask_subs_epu8"; + case INTRINSIC_XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_mask_subs_epu8"; + case INTRINSIC_XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_mask_subs_epu8"; + case INTRINSIC_XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_subs_epu16"; + case INTRINSIC_XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_subs_epu16"; + case INTRINSIC_XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_subs_epu16"; + case INTRINSIC_XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_sub_epi16"; + case INTRINSIC_XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_sub_epi16"; + case INTRINSIC_XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_sub_epi16"; + case INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_mask_test_epi8_mask"; + case INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_mask_test_epi8_mask"; + case INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_mask_test_epi8_mask"; + case INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_test_epi16_mask"; + case INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_test_epi16_mask"; + case INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_test_epi16_mask"; + case INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_mask_testn_epi8_mask"; + case INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_mask_testn_epi8_mask"; + case INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_mask_testn_epi8_mask"; + case INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_testn_epi16_mask"; + case INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_testn_epi16_mask"; + case INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_testn_epi16_mask"; + case INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_mask_unpackhi_epi8"; + case INTRINSIC_XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_mask_unpackhi_epi8"; + case INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_mask_unpackhi_epi8"; + case INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_unpackhi_epi16"; + case INTRINSIC_XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_unpackhi_epi16"; + case INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_unpackhi_epi16"; + case INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_mask_unpacklo_epi8"; + case INTRINSIC_XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_mask_unpacklo_epi8"; + case INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_mask_unpacklo_epi8"; + case INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_mask_unpacklo_epi16"; + case INTRINSIC_XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_mask_unpacklo_epi16"; + case INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_mask_unpacklo_epi16"; + case INTRINSIC_XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kadd_mask32"; + case INTRINSIC_XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kadd_mask64"; + case INTRINSIC_XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kand_mask32"; + case INTRINSIC_XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kand_mask64"; + case INTRINSIC_XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kandn_mask32"; + case INTRINSIC_XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kandn_mask64"; + case INTRINSIC_XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512: + return "_knot_mask32"; + case INTRINSIC_XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512: + return "_knot_mask64"; + case INTRINSIC_XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kor_mask32"; + case INTRINSIC_XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kor_mask64"; + case INTRINSIC_XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kxnor_mask32"; + case INTRINSIC_XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kxnor_mask64"; + case INTRINSIC_XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kxor_mask32"; + case INTRINSIC_XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kxor_mask64"; + case INTRINSIC_XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512: + return "_kshiftli_mask32"; + case INTRINSIC_XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512: + return "_kshiftli_mask64"; + case INTRINSIC_XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512: + return "_kshiftri_mask32"; + case INTRINSIC_XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512: + return "_kshiftri_mask64"; + case INTRINSIC_XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512: + return "_load_mask32"; + case INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512: + return "_load_mask64"; + case INTRINSIC_XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512: + return "_store_mask32"; + case INTRINSIC_XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512: + return "_store_mask64"; + case INTRINSIC_XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512: + return "_kortest_mask32_u8"; + case INTRINSIC_XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512: + return "_kortest_mask64_u8"; + case INTRINSIC_XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512: + return "_ktest_mask32_u8"; + case INTRINSIC_XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512: + return "_ktest_mask64_u8"; + case INTRINSIC_XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512: + return "_cvtmask32_u32"; + case INTRINSIC_XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512: + return "_cvtmask64_u64"; + case INTRINSIC_XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512: + return "_cvtu32_mask32"; + case INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512: + return "_cvtu64_mask64"; + case INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512: + return "_mm256_broadcastmb_epi64"; + case INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512: + return "_mm_broadcastmb_epi64"; + case INTRINSIC_XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512: + return "_mm256_broadcastmw_epi32"; + case INTRINSIC_XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512: + return "_mm_broadcastmw_epi32"; + case INTRINSIC_XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512: + return "_mm256_conflict_epi32"; + case INTRINSIC_XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512: + return "_mm_conflict_epi32"; + case INTRINSIC_XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512: + return "_mm256_conflict_epi64"; + case INTRINSIC_XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512: + return "_mm_conflict_epi64"; + case INTRINSIC_XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512: + return "_mm256_lzcnt_epi32"; + case INTRINSIC_XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512: + return "_mm_lzcnt_epi32"; + case INTRINSIC_XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512: + return "_mm256_lzcnt_epi64"; + case INTRINSIC_XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512: + return "_mm_lzcnt_epi64"; + case INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD: + return "_mm512_broadcastmb_epi64"; + case INTRINSIC_XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD: + return "_mm512_broadcastmw_epi32"; + case INTRINSIC_XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD: + return "_mm512_conflict_epi32"; + case INTRINSIC_XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD: + return "_mm512_conflict_epi64"; + case INTRINSIC_XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD: + return "_mm512_lzcnt_epi32"; + case INTRINSIC_XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD: + return "_mm512_lzcnt_epi64"; + case INTRINSIC_XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_andnot_pd"; + case INTRINSIC_XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_andnot_pd"; + case INTRINSIC_XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_andnot_pd"; + case INTRINSIC_XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_andnot_ps"; + case INTRINSIC_XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_andnot_ps"; + case INTRINSIC_XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_andnot_ps"; + case INTRINSIC_XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_and_pd"; + case INTRINSIC_XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_and_pd"; + case INTRINSIC_XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_and_pd"; + case INTRINSIC_XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_and_ps"; + case INTRINSIC_XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_and_ps"; + case INTRINSIC_XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_and_ps"; + case INTRINSIC_XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512: + return "_mm256_broadcast_f32x2"; + case INTRINSIC_XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512: + return "_mm512_broadcast_f32x2"; + case INTRINSIC_XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512: + return "_mm512_broadcast_f32x8"; + case INTRINSIC_XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512: + return "_mm256_broadcast_f64x2"; + case INTRINSIC_XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512: + return "_mm512_broadcast_f64x2"; + case INTRINSIC_XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512: + return "_mm256_broadcast_i32x2"; + case INTRINSIC_XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512: + return "_mm512_broadcast_i32x2"; + case INTRINSIC_XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512: + return "_mm_broadcast_i32x2"; + case INTRINSIC_XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512: + return "_mm512_broadcast_i32x8"; + case INTRINSIC_XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512: + return "_mm256_broadcast_i64x2"; + case INTRINSIC_XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512: + return "_mm512_broadcast_i64x2"; + case INTRINSIC_XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512: + return "_mm256_cvtpd_epi64"; + case INTRINSIC_XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512: + return "_mm512_cvt_roundpd_epi64"; + case INTRINSIC_XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512: + return "_mm_cvtpd_epi64"; + case INTRINSIC_XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512: + return "_mm256_cvtpd_epu64"; + case INTRINSIC_XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512: + return "_mm512_cvt_roundpd_epu64"; + case INTRINSIC_XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512: + return "_mm_cvtpd_epu64"; + case INTRINSIC_XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512: + return "_mm256_cvtps_epi64"; + case INTRINSIC_XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512: + return "_mm512_cvt_roundps_epi64"; + case INTRINSIC_XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512: + return "_mm_cvtps_epi64"; + case INTRINSIC_XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512: + return "_mm256_cvtps_epu64"; + case INTRINSIC_XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512: + return "_mm512_cvt_roundps_epu64"; + case INTRINSIC_XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512: + return "_mm_cvtps_epu64"; + case INTRINSIC_XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512: + return "_mm256_cvtepi64_pd"; + case INTRINSIC_XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512: + return "_mm512_cvt_roundepi64_pd"; + case INTRINSIC_XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512: + return "_mm_cvtepi64_pd"; + case INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256: + return "_mm256_cvtepi64_ps"; + case INTRINSIC_XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512: + return "_mm512_cvt_roundepi64_ps"; + case INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128: + return "_mm_cvtepi64_ps"; + case INTRINSIC_XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512: + return "_mm256_cvttpd_epi64"; + case INTRINSIC_XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512: + return "_mm512_cvtt_roundpd_epi64"; + case INTRINSIC_XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512: + return "_mm_cvttpd_epi64"; + case INTRINSIC_XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512: + return "_mm256_cvttpd_epu64"; + case INTRINSIC_XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512: + return "_mm512_cvtt_roundpd_epu64"; + case INTRINSIC_XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512: + return "_mm_cvttpd_epu64"; + case INTRINSIC_XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512: + return "_mm256_cvttps_epi64"; + case INTRINSIC_XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512: + return "_mm512_cvtt_roundps_epi64"; + case INTRINSIC_XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512: + return "_mm_cvttps_epi64"; + case INTRINSIC_XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512: + return "_mm256_cvttps_epu64"; + case INTRINSIC_XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512: + return "_mm512_cvtt_roundps_epu64"; + case INTRINSIC_XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512: + return "_mm_cvttps_epu64"; + case INTRINSIC_XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512: + return "_mm256_cvtepu64_pd"; + case INTRINSIC_XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512: + return "_mm512_cvt_roundepu64_pd"; + case INTRINSIC_XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512: + return "_mm_cvtepu64_pd"; + case INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256: + return "_mm256_cvtepu64_ps"; + case INTRINSIC_XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512: + return "_mm512_cvt_roundepu64_ps"; + case INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128: + return "_mm_cvtepu64_ps"; + case INTRINSIC_XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return "_mm512_extractf32x8_ps"; + case INTRINSIC_XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return "_mm256_extractf64x2_pd"; + case INTRINSIC_XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return "_mm512_extractf64x2_pd"; + case INTRINSIC_XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return "_mm512_extracti32x8_epi32"; + case INTRINSIC_XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return "_mm256_extracti64x2_epi64"; + case INTRINSIC_XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return "_mm512_extracti64x2_epi64"; + case INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512: + return "_mm256_fpclass_pd_mask"; + case INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512: + return "_mm512_fpclass_pd_mask"; + case INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512: + return "_mm_fpclass_pd_mask"; + case INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512: + return "_mm256_fpclass_ps_mask"; + case INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512: + return "_mm512_fpclass_ps_mask"; + case INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512: + return "_mm_fpclass_ps_mask"; + case INTRINSIC_XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512: + return "_mm_fpclass_sd_mask"; + case INTRINSIC_XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512: + return "_mm_fpclass_ss_mask"; + case INTRINSIC_XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512: + return "_mm512_insertf32x8"; + case INTRINSIC_XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512: + return "_mm256_insertf64x2"; + case INTRINSIC_XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512: + return "_mm512_insertf64x2"; + case INTRINSIC_XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512: + return "_mm512_inserti32x8"; + case INTRINSIC_XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512: + return "_mm256_inserti64x2"; + case INTRINSIC_XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512: + return "_mm512_inserti64x2"; + case INTRINSIC_XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_or_pd"; + case INTRINSIC_XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_or_pd"; + case INTRINSIC_XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_or_pd"; + case INTRINSIC_XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_or_ps"; + case INTRINSIC_XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_mask_or_ps"; + case INTRINSIC_XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_or_ps"; + case INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512: + return "_mm256_movepi32_mask"; + case INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512: + return "_mm512_movepi32_mask"; + case INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512: + return "_mm_movepi32_mask"; + case INTRINSIC_XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512: + return "_mm256_movm_epi32"; + case INTRINSIC_XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512: + return "_mm512_movm_epi32"; + case INTRINSIC_XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512: + return "_mm_movm_epi32"; + case INTRINSIC_XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512: + return "_mm256_movm_epi64"; + case INTRINSIC_XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512: + return "_mm512_movm_epi64"; + case INTRINSIC_XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512: + return "_mm_movm_epi64"; + case INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512: + return "_mm256_movepi64_mask"; + case INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512: + return "_mm512_movepi64_mask"; + case INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512: + return "_mm_movepi64_mask"; + case INTRINSIC_XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_mullo_epi64"; + case INTRINSIC_XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_mullo_epi64"; + case INTRINSIC_XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_mullo_epi64"; + case INTRINSIC_XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + return "_mm256_mask_range_pd"; + case INTRINSIC_XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + return "_mm512_mask_range_pd"; + case INTRINSIC_XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return "_mm_mask_range_pd"; + case INTRINSIC_XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + return "_mm256_mask_range_ps"; + case INTRINSIC_XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + return "_mm512_mask_range_ps"; + case INTRINSIC_XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return "_mm_mask_range_ps"; + case INTRINSIC_XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return "_mm_mask_range_round_sd"; + case INTRINSIC_XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return "_mm_mask_range_round_ss"; + case INTRINSIC_XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return "_mm256_mask_reduce_pd"; + case INTRINSIC_XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return "_mm512_mask_reduce_pd"; + case INTRINSIC_XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + return "_mm_mask_reduce_pd"; + case INTRINSIC_XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + return "_mm256_mask_reduce_ps"; + case INTRINSIC_XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return "_mm512_mask_reduce_ps"; + case INTRINSIC_XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + return "_mm_mask_reduce_ps"; + case INTRINSIC_XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return "_mm_mask_reduce_sd"; + case INTRINSIC_XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return "_mm_mask_reduce_ss"; + case INTRINSIC_XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_xor_pd"; + case INTRINSIC_XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_xor_pd"; + case INTRINSIC_XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_xor_pd"; + case INTRINSIC_XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_xor_ps"; + case INTRINSIC_XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_mask_xor_ps"; + case INTRINSIC_XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_xor_ps"; + case INTRINSIC_XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kadd_mask8"; + case INTRINSIC_XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kadd_mask16"; + case INTRINSIC_XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kand_mask8"; + case INTRINSIC_XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kandn_mask8"; + case INTRINSIC_XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512: + return "_knot_mask8"; + case INTRINSIC_XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kor_mask8"; + case INTRINSIC_XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kxnor_mask8"; + case INTRINSIC_XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kxor_mask8"; + case INTRINSIC_XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512: + return "_kshiftli_mask8"; + case INTRINSIC_XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512: + return "_kshiftri_mask8"; + case INTRINSIC_XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512: + return "_load_mask8"; + case INTRINSIC_XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512: + return "_store_mask8"; + case INTRINSIC_XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512: + return "_kortest_mask8_u8"; + case INTRINSIC_XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512: + return "_ktest_mask8_u8"; + case INTRINSIC_XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512: + return "_ktest_mask16_u8"; + case INTRINSIC_XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512: + return "_cvtmask8_u32"; + case INTRINSIC_XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512: + return "_cvtu32_mask8"; + case INTRINSIC_XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER: + return "_mm512_exp2a23_round_ps"; + case INTRINSIC_XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER: + return "_mm512_exp2a23_round_pd"; + case INTRINSIC_XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER: + return "_mm_rcp28_round_sd"; + case INTRINSIC_XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER: + return "_mm_rcp28_round_ss"; + case INTRINSIC_XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER: + return "_mm512_rcp28_round_ps"; + case INTRINSIC_XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER: + return "_mm512_rcp28_round_pd"; + case INTRINSIC_XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER: + return "_mm_rsqrt28_round_sd"; + case INTRINSIC_XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER: + return "_mm_rsqrt28_round_ss"; + case INTRINSIC_XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER: + return "_mm512_rsqrt28_round_ps"; + case INTRINSIC_XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER: + return "_mm512_rsqrt28_round_pd"; + case INTRINSIC_XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask_add_pd"; + case INTRINSIC_XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_add_pd"; + case INTRINSIC_XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask_add_ps"; + case INTRINSIC_XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_add_ps"; + case INTRINSIC_XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return "_mm256_alignr_epi32"; + case INTRINSIC_XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + return "_mm_alignr_epi32"; + case INTRINSIC_XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return "_mm256_alignr_epi64"; + case INTRINSIC_XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + return "_mm_alignr_epi64"; + case INTRINSIC_XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask_blend_pd"; + case INTRINSIC_XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_blend_pd"; + case INTRINSIC_XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask_blend_ps"; + case INTRINSIC_XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_blend_ps"; + case INTRINSIC_XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512: + return "_mm256_broadcast_f32x4"; + case INTRINSIC_XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512: + return "_mm256_broadcast_i32x4"; + case INTRINSIC_XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512: + return "_mm256_mask_broadcastsd_pd"; + case INTRINSIC_XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512: + return "_mm256_mask_broadcastss_ps"; + case INTRINSIC_XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512: + return "_mm_mask_broadcastss_ps"; + case INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + return "_mm256_cmp_pd_mask"; + case INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return "_mm_cmp_pd_mask"; + case INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + return "_mm256_cmp_ps_mask"; + case INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return "_mm_cmp_ps_mask"; + case INTRINSIC_XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512: + return "_mm256_mask_compress_pd"; + case INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512: + return "_mm256_mask_compressstoreu_pd"; + case INTRINSIC_XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512: + return "_mm_mask_compress_pd"; + case INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512: + return "_mm_mask_compressstoreu_pd"; + case INTRINSIC_XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512: + return "_mm256_mask_compress_ps"; + case INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512: + return "_mm256_mask_compressstoreu_ps"; + case INTRINSIC_XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512: + return "_mm_mask_compress_ps"; + case INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512: + return "_mm_mask_compressstoreu_ps"; + case INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512: + return "_mm256_mask_cvtepi32_pd"; + case INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512: + return "_mm_mask_cvtepi32_pd"; + case INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512: + return "_mm256_mask_cvtepi32_ps"; + case INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512: + return "_mm_mask_cvtepi32_ps"; + case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256: + return "_mm256_mask_cvtpd_epi32"; + case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128: + return "_mm_mask_cvtpd_epi32"; + case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256: + return "_mm256_mask_cvtpd_ps"; + case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128: + return "_mm_mask_cvtpd_ps"; + case INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256: + return "_mm256_cvtpd_epu32"; + case INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128: + return "_mm_cvtpd_epu32"; + case INTRINSIC_XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512: + return "_mm256_mask_cvtph_ps"; + case INTRINSIC_XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512: + return "_mm_mask_cvtph_ps"; + case INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512: + return "_mm256_mask_cvtps_epi32"; + case INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512: + return "_mm_mask_cvtps_epi32"; + case INTRINSIC_XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512: + return "_mm256_mask_cvt_roundps_ph"; + case INTRINSIC_XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512: + return "_mm_mask_cvt_roundps_ph"; + case INTRINSIC_XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512: + return "_mm256_cvtps_epu32"; + case INTRINSIC_XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512: + return "_mm_cvtps_epu32"; + case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256: + return "_mm256_mask_cvttpd_epi32"; + case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128: + return "_mm_mask_cvttpd_epi32"; + case INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256: + return "_mm256_cvttpd_epu32"; + case INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128: + return "_mm_cvttpd_epu32"; + case INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512: + return "_mm256_mask_cvttps_epi32"; + case INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512: + return "_mm_mask_cvttps_epi32"; + case INTRINSIC_XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512: + return "_mm256_cvttps_epu32"; + case INTRINSIC_XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512: + return "_mm_cvttps_epu32"; + case INTRINSIC_XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512: + return "_mm256_cvtepu32_pd"; + case INTRINSIC_XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512: + return "_mm_cvtepu32_pd"; + case INTRINSIC_XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask_div_pd"; + case INTRINSIC_XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_div_pd"; + case INTRINSIC_XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask_div_ps"; + case INTRINSIC_XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_div_ps"; + case INTRINSIC_XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512: + return "_mm256_mask_expand_pd"; + case INTRINSIC_XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512: + return "_mm256_mask_expandloadu_pd"; + case INTRINSIC_XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512: + return "_mm_mask_expand_pd"; + case INTRINSIC_XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512: + return "_mm_mask_expandloadu_pd"; + case INTRINSIC_XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512: + return "_mm256_mask_expand_ps"; + case INTRINSIC_XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512: + return "_mm256_mask_expandloadu_ps"; + case INTRINSIC_XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512: + return "_mm_mask_expand_ps"; + case INTRINSIC_XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512: + return "_mm_mask_expandloadu_ps"; + case INTRINSIC_XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512: + return "_mm256_extractf32x4_ps"; + case INTRINSIC_XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return "_mm256_extracti32x4_epi32"; + case INTRINSIC_XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + return "_mm256_fixupimm_pd"; + case INTRINSIC_XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return "_mm_fixupimm_pd"; + case INTRINSIC_XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + return "_mm256_fixupimm_ps"; + case INTRINSIC_XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return "_mm_fixupimm_ps"; + case INTRINSIC_XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fmadd_pd"; + case INTRINSIC_XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fmadd_pd"; + case INTRINSIC_XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fmadd_pd"; + case INTRINSIC_XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fmadd_pd"; + case INTRINSIC_XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fmadd_pd"; + case INTRINSIC_XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fmadd_pd"; + case INTRINSIC_XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fmadd_ps"; + case INTRINSIC_XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fmadd_ps"; + case INTRINSIC_XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fmadd_ps"; + case INTRINSIC_XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fmadd_ps"; + case INTRINSIC_XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fmadd_ps"; + case INTRINSIC_XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fmadd_ps"; + case INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fmaddsub_pd"; + case INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fmaddsub_pd"; + case INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fmaddsub_pd"; + case INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fmaddsub_pd"; + case INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fmaddsub_pd"; + case INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fmaddsub_pd"; + case INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fmaddsub_ps"; + case INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fmaddsub_ps"; + case INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fmaddsub_ps"; + case INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fmaddsub_ps"; + case INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fmaddsub_ps"; + case INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fmaddsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fmsub_pd"; + case INTRINSIC_XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fmsub_pd"; + case INTRINSIC_XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fmsub_pd"; + case INTRINSIC_XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fmsub_pd"; + case INTRINSIC_XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fmsub_pd"; + case INTRINSIC_XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fmsub_pd"; + case INTRINSIC_XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fmsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fmsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fmsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fmsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fmsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fmsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fmsubadd_pd"; + case INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fmsubadd_pd"; + case INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fmsubadd_pd"; + case INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fmsubadd_pd"; + case INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fmsubadd_pd"; + case INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fmsubadd_pd"; + case INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fmsubadd_ps"; + case INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fmsubadd_ps"; + case INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fmsubadd_ps"; + case INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fmsubadd_ps"; + case INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fmsubadd_ps"; + case INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fmsubadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fnmadd_pd"; + case INTRINSIC_XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fnmadd_pd"; + case INTRINSIC_XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fnmadd_pd"; + case INTRINSIC_XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fnmadd_pd"; + case INTRINSIC_XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fnmadd_pd"; + case INTRINSIC_XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fnmadd_pd"; + case INTRINSIC_XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fnmadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fnmadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fnmadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fnmadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fnmadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fnmadd_ps"; + case INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fnmsub_pd"; + case INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fnmsub_pd"; + case INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask3_fnmsub_pd"; + case INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fnmsub_pd"; + case INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fnmsub_pd"; + case INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask3_fnmsub_pd"; + case INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fnmsub_ps"; + case INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fnmsub_ps"; + case INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask3_fnmsub_ps"; + case INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fnmsub_ps"; + case INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fnmsub_ps"; + case INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fnmsub_ps"; + case INTRINSIC_XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256: + return "_mm256_mmask_i32gather_pd"; + case INTRINSIC_XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128: + return "_mm_mmask_i32gather_pd"; + case INTRINSIC_XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256: + return "_mm256_mmask_i32gather_ps"; + case INTRINSIC_XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128: + return "_mm_mmask_i32gather_ps"; + case INTRINSIC_XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256: + return "_mm256_mmask_i64gather_pd"; + case INTRINSIC_XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128: + return "_mm_mmask_i64gather_pd"; + case INTRINSIC_XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512: + return "_mm256_mmask_i64gather_ps"; + case INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128: + return "_mm_mmask_i64gather_ps"; + case INTRINSIC_XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512: + return "_mm256_getexp_pd"; + case INTRINSIC_XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512: + return "_mm_getexp_pd"; + case INTRINSIC_XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512: + return "_mm256_getexp_ps"; + case INTRINSIC_XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512: + return "_mm_getexp_ps"; + case INTRINSIC_XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return "_mm256_getmant_pd"; + case INTRINSIC_XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + return "_mm_getmant_pd"; + case INTRINSIC_XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + return "_mm256_getmant_ps"; + case INTRINSIC_XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + return "_mm_getmant_ps"; + case INTRINSIC_XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512: + return "_mm256_insertf32x4"; + case INTRINSIC_XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512: + return "_mm256_inserti32x4"; + case INTRINSIC_XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask_max_pd"; + case INTRINSIC_XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_max_pd"; + case INTRINSIC_XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask_max_ps"; + case INTRINSIC_XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_max_ps"; + case INTRINSIC_XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask_min_pd"; + case INTRINSIC_XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_min_pd"; + case INTRINSIC_XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask_min_ps"; + case INTRINSIC_XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_min_ps"; + case INTRINSIC_XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512: + return "_mm256_mask_load_pd"; + case INTRINSIC_XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512: + return "_mm256_mask_mov_pd"; + case INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512: + return "_mm256_mask_store_pd"; + case INTRINSIC_XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512: + return "_mm_mask_load_pd"; + case INTRINSIC_XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512: + return "_mm_mask_mov_pd"; + case INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512: + return "_mm_mask_store_pd"; + case INTRINSIC_XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512: + return "_mm256_mask_load_ps"; + case INTRINSIC_XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512: + return "_mm256_mask_mov_ps"; + case INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512: + return "_mm256_mask_store_ps"; + case INTRINSIC_XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512: + return "_mm_mask_load_ps"; + case INTRINSIC_XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512: + return "_mm_mask_mov_ps"; + case INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512: + return "_mm_mask_store_ps"; + case INTRINSIC_XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512: + return "_mm256_mask_movedup_pd"; + case INTRINSIC_XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512: + return "_mm_mask_movedup_pd"; + case INTRINSIC_XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512: + return "_mm256_mask_load_epi32"; + case INTRINSIC_XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512: + return "_mm256_mask_mov_epi32"; + case INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512: + return "_mm256_mask_store_epi32"; + case INTRINSIC_XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512: + return "_mm_mask_load_epi32"; + case INTRINSIC_XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512: + return "_mm_mask_mov_epi32"; + case INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512: + return "_mm_mask_store_epi32"; + case INTRINSIC_XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512: + return "_mm256_mask_load_epi64"; + case INTRINSIC_XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512: + return "_mm256_mask_mov_epi64"; + case INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512: + return "_mm256_mask_store_epi64"; + case INTRINSIC_XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512: + return "_mm_mask_load_epi64"; + case INTRINSIC_XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512: + return "_mm_mask_mov_epi64"; + case INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512: + return "_mm_mask_store_epi64"; + case INTRINSIC_XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512: + return "_mm256_mask_loadu_epi32"; + case INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512: + return "_mm256_mask_storeu_epi32"; + case INTRINSIC_XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512: + return "_mm_mask_loadu_epi32"; + case INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512: + return "_mm_mask_storeu_epi32"; + case INTRINSIC_XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512: + return "_mm256_mask_loadu_epi64"; + case INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512: + return "_mm256_mask_storeu_epi64"; + case INTRINSIC_XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512: + return "_mm_mask_loadu_epi64"; + case INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512: + return "_mm_mask_storeu_epi64"; + case INTRINSIC_XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512: + return "_mm256_mask_movehdup_ps"; + case INTRINSIC_XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512: + return "_mm_mask_movehdup_ps"; + case INTRINSIC_XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512: + return "_mm256_mask_moveldup_ps"; + case INTRINSIC_XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512: + return "_mm_mask_moveldup_ps"; + case INTRINSIC_XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512: + return "_mm256_mask_loadu_pd"; + case INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512: + return "_mm256_mask_storeu_pd"; + case INTRINSIC_XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512: + return "_mm_mask_loadu_pd"; + case INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512: + return "_mm_mask_storeu_pd"; + case INTRINSIC_XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512: + return "_mm256_mask_loadu_ps"; + case INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512: + return "_mm256_mask_storeu_ps"; + case INTRINSIC_XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512: + return "_mm_mask_loadu_ps"; + case INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512: + return "_mm_mask_storeu_ps"; + case INTRINSIC_XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask_mul_pd"; + case INTRINSIC_XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_mul_pd"; + case INTRINSIC_XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask_mul_ps"; + case INTRINSIC_XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_mul_ps"; + case INTRINSIC_XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512: + return "_mm256_mask_abs_epi32"; + case INTRINSIC_XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512: + return "_mm_mask_abs_epi32"; + case INTRINSIC_XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512: + return "_mm256_abs_epi64"; + case INTRINSIC_XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512: + return "_mm_abs_epi64"; + case INTRINSIC_XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_add_epi32"; + case INTRINSIC_XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_add_epi32"; + case INTRINSIC_XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_add_epi64"; + case INTRINSIC_XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_add_epi64"; + case INTRINSIC_XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_and_epi32"; + case INTRINSIC_XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_and_epi32"; + case INTRINSIC_XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_andnot_epi32"; + case INTRINSIC_XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_andnot_epi32"; + case INTRINSIC_XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_andnot_epi64"; + case INTRINSIC_XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_andnot_epi64"; + case INTRINSIC_XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_and_epi64"; + case INTRINSIC_XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_and_epi64"; + case INTRINSIC_XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_blend_epi32"; + case INTRINSIC_XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_blend_epi32"; + case INTRINSIC_XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_blend_epi64"; + case INTRINSIC_XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_blend_epi64"; + case INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512: + return "_mm256_mask_broadcastd_epi32"; + case INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512: + return "_mm256_mask_set1_epi32"; + case INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512: + return "_mm_mask_broadcastd_epi32"; + case INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512: + return "_mm_mask_set1_epi32"; + case INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512: + return "_mm256_mask_broadcastq_epi64"; + case INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512: + return "_mm256_mask_set1_epi64"; + case INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512: + return "_mm_mask_broadcastq_epi64"; + case INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512: + return "_mm_mask_set1_epi64"; + case INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512: + return "_mm256_cmp_epi32_mask"; + case INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512: + return "_mm_cmp_epi32_mask"; + case INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512: + return "_mm256_cmp_epi64_mask"; + case INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512: + return "_mm_cmp_epi64_mask"; + case INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return "_mm256_cmp_epu32_mask"; + case INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + return "_mm_cmp_epu32_mask"; + case INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return "_mm256_cmp_epu64_mask"; + case INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + return "_mm_cmp_epu64_mask"; + case INTRINSIC_XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512: + return "_mm256_mask_compress_epi32"; + case INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512: + return "_mm256_mask_compressstoreu_epi32"; + case INTRINSIC_XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512: + return "_mm_mask_compress_epi32"; + case INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512: + return "_mm_mask_compressstoreu_epi32"; + case INTRINSIC_XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512: + return "_mm256_mask_compress_epi64"; + case INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512: + return "_mm256_mask_compressstoreu_epi64"; + case INTRINSIC_XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512: + return "_mm_mask_compress_epi64"; + case INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512: + return "_mm_mask_compressstoreu_epi64"; + case INTRINSIC_XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_permutexvar_epi32"; + case INTRINSIC_XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask2_permutex2var_epi32"; + case INTRINSIC_XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_permutex2var_epi32"; + case INTRINSIC_XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask2_permutex2var_epi32"; + case INTRINSIC_XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_permutex2var_epi32"; + case INTRINSIC_XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask2_permutex2var_pd"; + case INTRINSIC_XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask_permutex2var_pd"; + case INTRINSIC_XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask2_permutex2var_pd"; + case INTRINSIC_XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_permutex2var_pd"; + case INTRINSIC_XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask2_permutex2var_ps"; + case INTRINSIC_XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask_permutex2var_ps"; + case INTRINSIC_XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask2_permutex2var_ps"; + case INTRINSIC_XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_permutex2var_ps"; + case INTRINSIC_XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask2_permutex2var_epi64"; + case INTRINSIC_XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_permutex2var_epi64"; + case INTRINSIC_XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask2_permutex2var_epi64"; + case INTRINSIC_XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_permutex2var_epi64"; + case INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return "_mm256_mask_permute_pd"; + case INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask_permutevar_pd"; + case INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + return "_mm_mask_permute_pd"; + case INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_permutevar_pd"; + case INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + return "_mm256_mask_permute_ps"; + case INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask_permutevar_ps"; + case INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + return "_mm_mask_permute_ps"; + case INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_permutevar_ps"; + case INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return "_mm256_mask_permutex_pd"; + case INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask_permutexvar_pd"; + case INTRINSIC_XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask_permutexvar_ps"; + case INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return "_mm256_mask_permutex_epi64"; + case INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_permutexvar_epi64"; + case INTRINSIC_XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512: + return "_mm256_mask_expand_epi32"; + case INTRINSIC_XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512: + return "_mm256_mask_expandloadu_epi32"; + case INTRINSIC_XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512: + return "_mm_mask_expand_epi32"; + case INTRINSIC_XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512: + return "_mm_mask_expandloadu_epi32"; + case INTRINSIC_XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512: + return "_mm256_mask_expand_epi64"; + case INTRINSIC_XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512: + return "_mm256_mask_expandloadu_epi64"; + case INTRINSIC_XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512: + return "_mm_mask_expand_epi64"; + case INTRINSIC_XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512: + return "_mm_mask_expandloadu_epi64"; + case INTRINSIC_XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256: + return "_mm256_mmask_i32gather_epi32"; + case INTRINSIC_XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128: + return "_mm_mmask_i32gather_epi32"; + case INTRINSIC_XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256: + return "_mm256_mmask_i32gather_epi64"; + case INTRINSIC_XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128: + return "_mm_mmask_i32gather_epi64"; + case INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128: + return "_mm256_mmask_i64gather_epi32"; + case INTRINSIC_XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256: + return "_mm256_mmask_i64gather_epi64"; + case INTRINSIC_XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128: + return "_mm_mmask_i64gather_epi64"; + case INTRINSIC_XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512: + return "_mm256_mask_max_epi32"; + case INTRINSIC_XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512: + return "_mm_mask_max_epi32"; + case INTRINSIC_XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512: + return "_mm256_mask_max_epi64"; + case INTRINSIC_XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512: + return "_mm_mask_max_epi64"; + case INTRINSIC_XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_max_epu32"; + case INTRINSIC_XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_max_epu32"; + case INTRINSIC_XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_max_epu64"; + case INTRINSIC_XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_max_epu64"; + case INTRINSIC_XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512: + return "_mm256_mask_min_epi32"; + case INTRINSIC_XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512: + return "_mm_mask_min_epi32"; + case INTRINSIC_XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512: + return "_mm256_mask_min_epi64"; + case INTRINSIC_XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512: + return "_mm_mask_min_epi64"; + case INTRINSIC_XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_min_epu32"; + case INTRINSIC_XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_min_epu32"; + case INTRINSIC_XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_min_epu64"; + case INTRINSIC_XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_min_epu64"; + case INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512: + return "_mm256_cvtepi32_epi8"; + case INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512: + return "_mm256_mask_cvtepi32_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512: + return "_mm_cvtepi32_epi8"; + case INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512: + return "_mm_mask_cvtepi32_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512: + return "_mm256_cvtepi32_epi16"; + case INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512: + return "_mm256_mask_cvtepi32_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512: + return "_mm_cvtepi32_epi16"; + case INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512: + return "_mm_mask_cvtepi32_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512: + return "_mm256_cvtepi64_epi8"; + case INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512: + return "_mm256_mask_cvtepi64_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512: + return "_mm_cvtepi64_epi8"; + case INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512: + return "_mm_mask_cvtepi64_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512: + return "_mm256_cvtepi64_epi32"; + case INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512: + return "_mm256_mask_cvtepi64_storeu_epi32"; + case INTRINSIC_XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512: + return "_mm_cvtepi64_epi32"; + case INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512: + return "_mm_mask_cvtepi64_storeu_epi32"; + case INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512: + return "_mm256_cvtepi64_epi16"; + case INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512: + return "_mm256_mask_cvtepi64_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512: + return "_mm_cvtepi64_epi16"; + case INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512: + return "_mm_mask_cvtepi64_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512: + return "_mm256_cvtsepi32_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512: + return "_mm256_mask_cvtsepi32_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512: + return "_mm_cvtsepi32_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512: + return "_mm_mask_cvtsepi32_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512: + return "_mm256_cvtsepi32_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512: + return "_mm256_mask_cvtsepi32_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512: + return "_mm_cvtsepi32_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512: + return "_mm_mask_cvtsepi32_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512: + return "_mm256_cvtsepi64_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512: + return "_mm256_mask_cvtsepi64_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512: + return "_mm_cvtsepi64_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512: + return "_mm_mask_cvtsepi64_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512: + return "_mm256_cvtsepi64_epi32"; + case INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512: + return "_mm256_mask_cvtsepi64_storeu_epi32"; + case INTRINSIC_XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512: + return "_mm_cvtsepi64_epi32"; + case INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512: + return "_mm_mask_cvtsepi64_storeu_epi32"; + case INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512: + return "_mm256_cvtsepi64_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512: + return "_mm256_mask_cvtsepi64_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512: + return "_mm_cvtsepi64_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512: + return "_mm_mask_cvtsepi64_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512: + return "_mm256_mask_cvtepi8_epi32"; + case INTRINSIC_XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512: + return "_mm_mask_cvtepi8_epi32"; + case INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512: + return "_mm256_mask_cvtepi8_epi64"; + case INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512: + return "_mm_mask_cvtepi8_epi64"; + case INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512: + return "_mm256_mask_cvtepi32_epi64"; + case INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512: + return "_mm_mask_cvtepi32_epi64"; + case INTRINSIC_XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512: + return "_mm256_mask_cvtepi16_epi32"; + case INTRINSIC_XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512: + return "_mm_mask_cvtepi16_epi32"; + case INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512: + return "_mm256_mask_cvtepi16_epi64"; + case INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512: + return "_mm_mask_cvtepi16_epi64"; + case INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512: + return "_mm256_cvtusepi32_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512: + return "_mm256_mask_cvtusepi32_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512: + return "_mm_cvtusepi32_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512: + return "_mm_mask_cvtusepi32_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512: + return "_mm256_cvtusepi32_epi16"; + case INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512: + return "_mm256_mask_cvtusepi32_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512: + return "_mm_cvtusepi32_epi16"; + case INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512: + return "_mm_mask_cvtusepi32_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512: + return "_mm256_cvtusepi64_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512: + return "_mm256_mask_cvtusepi64_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512: + return "_mm_cvtusepi64_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512: + return "_mm_mask_cvtusepi64_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512: + return "_mm256_cvtusepi64_epi32"; + case INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512: + return "_mm256_mask_cvtusepi64_storeu_epi32"; + case INTRINSIC_XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512: + return "_mm_cvtusepi64_epi32"; + case INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512: + return "_mm_mask_cvtusepi64_storeu_epi32"; + case INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512: + return "_mm256_cvtusepi64_epi16"; + case INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512: + return "_mm256_mask_cvtusepi64_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512: + return "_mm_cvtusepi64_epi16"; + case INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512: + return "_mm_mask_cvtusepi64_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512: + return "_mm256_mask_cvtepu8_epi32"; + case INTRINSIC_XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512: + return "_mm_mask_cvtepu8_epi32"; + case INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512: + return "_mm256_mask_cvtepu8_epi64"; + case INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512: + return "_mm_mask_cvtepu8_epi64"; + case INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512: + return "_mm256_mask_cvtepu32_epi64"; + case INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512: + return "_mm_mask_cvtepu32_epi64"; + case INTRINSIC_XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512: + return "_mm256_mask_cvtepu16_epi32"; + case INTRINSIC_XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512: + return "_mm_mask_cvtepu16_epi32"; + case INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512: + return "_mm256_mask_cvtepu16_epi64"; + case INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512: + return "_mm_mask_cvtepu16_epi64"; + case INTRINSIC_XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512: + return "_mm256_mask_mul_epi32"; + case INTRINSIC_XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512: + return "_mm_mask_mul_epi32"; + case INTRINSIC_XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_mullo_epi32"; + case INTRINSIC_XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_maskz_mullo_epi32"; + case INTRINSIC_XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_mullo_epi32"; + case INTRINSIC_XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_mul_epu32"; + case INTRINSIC_XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_mul_epu32"; + case INTRINSIC_XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_or_epi32"; + case INTRINSIC_XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_or_epi32"; + case INTRINSIC_XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_or_epi64"; + case INTRINSIC_XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_or_epi64"; + case INTRINSIC_XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return "_mm256_mask_rol_epi32"; + case INTRINSIC_XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return "_mm_mask_rol_epi32"; + case INTRINSIC_XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return "_mm256_mask_rol_epi64"; + case INTRINSIC_XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + return "_mm_mask_rol_epi64"; + case INTRINSIC_XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_rolv_epi32"; + case INTRINSIC_XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_rolv_epi32"; + case INTRINSIC_XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_rolv_epi64"; + case INTRINSIC_XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_rolv_epi64"; + case INTRINSIC_XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return "_mm256_mask_ror_epi32"; + case INTRINSIC_XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return "_mm_mask_ror_epi32"; + case INTRINSIC_XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return "_mm256_mask_ror_epi64"; + case INTRINSIC_XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + return "_mm_mask_ror_epi64"; + case INTRINSIC_XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_rorv_epi32"; + case INTRINSIC_XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_rorv_epi32"; + case INTRINSIC_XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_rorv_epi64"; + case INTRINSIC_XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_rorv_epi64"; + case INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256: + return "_mm256_i32scatter_epi32"; + case INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128: + return "_mm_i32scatter_epi32"; + case INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256: + return "_mm256_i32scatter_epi64"; + case INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128: + return "_mm_i32scatter_epi64"; + case INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128: + return "_mm256_i64scatter_epi32"; + case INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256: + return "_mm256_i64scatter_epi64"; + case INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128: + return "_mm_i64scatter_epi64"; + case INTRINSIC_XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return "_mm256_mask_shuffle_epi32"; + case INTRINSIC_XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return "_mm_mask_shuffle_epi32"; + case INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512: + return "_mm256_mask_sll_epi32"; + case INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return "_mm256_mask_slli_epi32"; + case INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_sll_epi32"; + case INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return "_mm_mask_slli_epi32"; + case INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512: + return "_mm256_mask_sll_epi64"; + case INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return "_mm256_mask_slli_epi64"; + case INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_sll_epi64"; + case INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + return "_mm_mask_slli_epi64"; + case INTRINSIC_XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_sllv_epi32"; + case INTRINSIC_XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_sllv_epi32"; + case INTRINSIC_XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_sllv_epi64"; + case INTRINSIC_XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_sllv_epi64"; + case INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512: + return "_mm256_mask_sra_epi32"; + case INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return "_mm256_mask_srai_epi32"; + case INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_sra_epi32"; + case INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return "_mm_mask_srai_epi32"; + case INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512: + return "_mm256_mask_sra_epi64"; + case INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return "_mm256_mask_srai_epi64"; + case INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_sra_epi64"; + case INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + return "_mm_mask_srai_epi64"; + case INTRINSIC_XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_srav_epi32"; + case INTRINSIC_XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_srav_epi32"; + case INTRINSIC_XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_srav_epi64"; + case INTRINSIC_XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_srav_epi64"; + case INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512: + return "_mm256_mask_srl_epi32"; + case INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return "_mm256_mask_srli_epi32"; + case INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_srl_epi32"; + case INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return "_mm_mask_srli_epi32"; + case INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512: + return "_mm256_mask_srl_epi64"; + case INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return "_mm256_mask_srli_epi64"; + case INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_srl_epi64"; + case INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + return "_mm_mask_srli_epi64"; + case INTRINSIC_XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_srlv_epi32"; + case INTRINSIC_XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_srlv_epi32"; + case INTRINSIC_XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_srlv_epi64"; + case INTRINSIC_XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_srlv_epi64"; + case INTRINSIC_XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_sub_epi32"; + case INTRINSIC_XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_sub_epi32"; + case INTRINSIC_XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_sub_epi64"; + case INTRINSIC_XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_sub_epi64"; + case INTRINSIC_XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return "_mm256_mask_ternarylogic_epi32"; + case INTRINSIC_XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + return "_mm_mask_ternarylogic_epi32"; + case INTRINSIC_XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return "_mm256_mask_ternarylogic_epi64"; + case INTRINSIC_XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + return "_mm_mask_ternarylogic_epi64"; + case INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_test_epi32_mask"; + case INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_test_epi32_mask"; + case INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_test_epi64_mask"; + case INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_test_epi64_mask"; + case INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_testn_epi32_mask"; + case INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_testn_epi32_mask"; + case INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_testn_epi64_mask"; + case INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_testn_epi64_mask"; + case INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_unpackhi_epi32"; + case INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_unpackhi_epi32"; + case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_unpackhi_epi64"; + case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_unpackhi_epi64"; + case INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_unpacklo_epi32"; + case INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_unpacklo_epi32"; + case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_unpacklo_epi64"; + case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_unpacklo_epi64"; + case INTRINSIC_XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_mask_xor_epi32"; + case INTRINSIC_XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_mask_xor_epi32"; + case INTRINSIC_XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_mask_xor_epi64"; + case INTRINSIC_XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_mask_xor_epi64"; + case INTRINSIC_XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512: + return "_mm256_mask_rcp14_pd"; + case INTRINSIC_XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512: + return "_mm_mask_rcp14_pd"; + case INTRINSIC_XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512: + return "_mm256_mask_rcp14_ps"; + case INTRINSIC_XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512: + return "_mm_mask_rcp14_ps"; + case INTRINSIC_XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return "_mm256_mask_roundscale_pd"; + case INTRINSIC_XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + return "_mm_mask_roundscale_pd"; + case INTRINSIC_XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + return "_mm256_mask_roundscale_ps"; + case INTRINSIC_XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + return "_mm_mask_roundscale_ps"; + case INTRINSIC_XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512: + return "_mm256_mask_rsqrt14_pd"; + case INTRINSIC_XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512: + return "_mm_mask_rsqrt14_pd"; + case INTRINSIC_XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512: + return "_mm256_mask_rsqrt14_ps"; + case INTRINSIC_XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512: + return "_mm_mask_rsqrt14_ps"; + case INTRINSIC_XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask_scalef_pd"; + case INTRINSIC_XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_scalef_pd"; + case INTRINSIC_XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask_scalef_ps"; + case INTRINSIC_XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_scalef_ps"; + case INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256: + return "_mm256_i32scatter_pd"; + case INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128: + return "_mm_i32scatter_pd"; + case INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256: + return "_mm256_i32scatter_ps"; + case INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128: + return "_mm_i32scatter_ps"; + case INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256: + return "_mm256_i64scatter_pd"; + case INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128: + return "_mm_i64scatter_pd"; + case INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128: + return "_mm256_i64scatter_ps"; + case INTRINSIC_XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + return "_mm256_mask_shuffle_f32x4"; + case INTRINSIC_XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + return "_mm256_mask_shuffle_f64x2"; + case INTRINSIC_XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return "_mm256_mask_shuffle_i32x4"; + case INTRINSIC_XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return "_mm256_mask_shuffle_i64x2"; + case INTRINSIC_XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + return "_mm256_mask_shuffle_pd"; + case INTRINSIC_XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return "_mm_mask_shuffle_pd"; + case INTRINSIC_XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + return "_mm256_mask_shuffle_ps"; + case INTRINSIC_XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return "_mm_mask_shuffle_ps"; + case INTRINSIC_XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512: + return "_mm256_mask_sqrt_pd"; + case INTRINSIC_XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512: + return "_mm_mask_sqrt_pd"; + case INTRINSIC_XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512: + return "_mm256_mask_sqrt_ps"; + case INTRINSIC_XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512: + return "_mm_mask_sqrt_ps"; + case INTRINSIC_XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask_sub_pd"; + case INTRINSIC_XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_sub_pd"; + case INTRINSIC_XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask_sub_ps"; + case INTRINSIC_XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_sub_ps"; + case INTRINSIC_XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask_unpackhi_pd"; + case INTRINSIC_XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_unpackhi_pd"; + case INTRINSIC_XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask_unpackhi_ps"; + case INTRINSIC_XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_unpackhi_ps"; + case INTRINSIC_XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return "_mm256_mask_unpacklo_pd"; + case INTRINSIC_XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_unpacklo_pd"; + case INTRINSIC_XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_mask_unpacklo_ps"; + case INTRINSIC_XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_unpacklo_ps"; + case INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512: + return "_mm512_storeu_epi64"; + case INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512: + return "_mm512_storeu_epi32"; + case INTRINSIC_XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512: + return "_mm512_loadu_epi64"; + case INTRINSIC_XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512: + return "_mm512_loadu_epi32"; + case INTRINSIC_XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512: + return "_mm512_aesenclast_epi128"; + case INTRINSIC_XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512: + return "_mm512_aesenc_epi128"; + case INTRINSIC_XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512: + return "_mm512_aesdeclast_epi128"; + case INTRINSIC_XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512: + return "_mm512_aesdec_epi128"; + case INTRINSIC_XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kand_mask16"; + case INTRINSIC_XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kandn_mask16"; + case INTRINSIC_XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512: + return "_knot_mask16"; + case INTRINSIC_XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kor_mask16"; + case INTRINSIC_XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kxnor_mask16"; + case INTRINSIC_XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_kxor_mask16"; + case INTRINSIC_XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512: + return "_kshiftli_mask16"; + case INTRINSIC_XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512: + return "_kshiftri_mask16"; + case INTRINSIC_XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512: + return "_load_mask16"; + case INTRINSIC_XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512: + return "_store_mask16"; + case INTRINSIC_XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512: + return "_kortest_mask16_u8"; + case INTRINSIC_XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512: + return "_cvtmask16_u32"; + case INTRINSIC_XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512: + return "_cvtu32_mask16"; + case INTRINSIC_XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512: + return "_mm512_kmov"; + case INTRINSIC_XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return "_mm512_kunpackb"; + case INTRINSIC_XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_maskz_add_pd"; + case INTRINSIC_XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_maskz_add_ps"; + case INTRINSIC_XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_add_round_sd"; + case INTRINSIC_XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_add_round_ss"; + case INTRINSIC_XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return "_mm512_maskz_alignr_epi32"; + case INTRINSIC_XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return "_mm512_alignr_epi64"; + case INTRINSIC_XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512: + return "_mm512_broadcast_f32x4"; + case INTRINSIC_XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512: + return "_mm512_broadcast_f64x4"; + case INTRINSIC_XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512: + return "_mm512_broadcast_i32x4"; + case INTRINSIC_XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512: + return "_mm512_broadcast_i64x4"; + case INTRINSIC_XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512: + return "_mm512_broadcastsd_pd"; + case INTRINSIC_XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512: + return "_mm512_broadcastss_ps"; + case INTRINSIC_XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return "_mm_cmp_round_sd_mask"; + case INTRINSIC_XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return "_mm_cmp_round_ss_mask"; + case INTRINSIC_XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512: + return "_mm_comi_round_sd"; + case INTRINSIC_XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512: + return "_mm_comi_round_ss"; + case INTRINSIC_XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512: + return "_mm_comi_round_ss"; + case INTRINSIC_XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return "_mm512_mask_compress_pd"; + case INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512: + return "_mm512_mask_compressstoreu_pd"; + case INTRINSIC_XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return "_mm512_mask_compress_ps"; + case INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512: + return "_mm512_mask_compressstoreu_ps"; + case INTRINSIC_XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512: + return "_mm512_cvtepi32_pd"; + case INTRINSIC_XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512: + return "_mm512_cvt_roundepi32_ps"; + case INTRINSIC_XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512: + return "_mm512_cvt_roundpd_epi32"; + case INTRINSIC_XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512: + return "_mm512_cvt_roundpd_ps"; + case INTRINSIC_XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512: + return "_mm512_cvt_roundpd_epu32"; + case INTRINSIC_XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512: + return "_mm512_cvt_roundph_ps"; + case INTRINSIC_XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512: + return "_mm512_cvt_roundps_epi32"; + case INTRINSIC_XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512: + return "_mm512_cvt_roundps_pd"; + case INTRINSIC_XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512: + return "_mm512_cvt_roundps_ph"; + case INTRINSIC_XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512: + return "_mm512_cvt_roundps_epu32"; + case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512: + return "_mm_cvt_roundsd_i32"; + case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512: + return "_mm_cvt_roundsd_i64"; + case INTRINSIC_XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_cvt_roundsd_ss"; + case INTRINSIC_XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512: + return "_mm_cvt_roundsd_u32"; + case INTRINSIC_XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512: + return "_mm_cvt_roundsd_u64"; + case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512: + return "_mm_cvt_roundi64_sd"; + case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512: + return "_mm_cvti32_sd"; + case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512: + return "_mm_cvt_roundi32_ss"; + case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512: + return "_mm_cvt_roundi64_ss"; + case INTRINSIC_XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_cvt_roundss_sd"; + case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512: + return "_mm_cvt_roundss_i32"; + case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512: + return "_mm_cvt_roundss_i64"; + case INTRINSIC_XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512: + return "_mm_cvt_roundss_u32"; + case INTRINSIC_XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512: + return "_mm_cvt_roundss_u64"; + case INTRINSIC_XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512: + return "_mm512_cvtt_roundpd_epi32"; + case INTRINSIC_XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512: + return "_mm512_cvtt_roundpd_epu32"; + case INTRINSIC_XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512: + return "_mm512_cvtt_roundps_epi32"; + case INTRINSIC_XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512: + return "_mm512_cvtt_roundps_epu32"; + case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512: + return "_mm_cvtt_roundsd_i32"; + case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512: + return "_mm_cvtt_roundsd_i64"; + case INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512: + return "_mm_cvtt_roundsd_u32"; + case INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512: + return "_mm_cvtt_roundsd_u64"; + case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512: + return "_mm_cvtt_roundss_i32"; + case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512: + return "_mm_cvtt_roundss_i64"; + case INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512: + return "_mm_cvtt_roundss_u32"; + case INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512: + return "_mm_cvtt_roundss_u64"; + case INTRINSIC_XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512: + return "_mm512_cvtepu32_pd"; + case INTRINSIC_XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512: + return "_mm512_cvt_roundepu32_ps"; + case INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512: + return "_mm_cvt_roundu64_sd"; + case INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512: + return "_mm_cvtu32_sd"; + case INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512: + return "_mm_cvt_roundu32_ss"; + case INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512: + return "_mm_cvt_roundu64_ss"; + case INTRINSIC_XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_div_pd"; + case INTRINSIC_XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_div_ps"; + case INTRINSIC_XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_div_round_sd"; + case INTRINSIC_XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_div_round_ss"; + case INTRINSIC_XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return "_mm512_mask_expand_pd"; + case INTRINSIC_XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512: + return "_mm512_mask_expandloadu_pd"; + case INTRINSIC_XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return "_mm512_mask_expand_ps"; + case INTRINSIC_XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512: + return "_mm512_mask_expandloadu_ps"; + case INTRINSIC_XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return "_mm512_extractf32x4_ps"; + case INTRINSIC_XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return "_mm512_extractf64x4_pd"; + case INTRINSIC_XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return "_mm512_extracti32x4_epi32"; + case INTRINSIC_XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return "_mm512_extracti64x4_epi64"; + case INTRINSIC_XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + return "_mm512_fixupimm_pd"; + case INTRINSIC_XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + return "_mm512_fixupimm_ps"; + case INTRINSIC_XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return "_mm_fixupimm_round_sd"; + case INTRINSIC_XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return "_mm_fixupimm_round_ss"; + case INTRINSIC_XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_maskz_fmadd_pd"; + case INTRINSIC_XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_maskz_fmadd_pd"; + case INTRINSIC_XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_maskz_fmadd_pd"; + case INTRINSIC_XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_maskz_fmadd_ps"; + case INTRINSIC_XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_maskz_fmadd_ps"; + case INTRINSIC_XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_maskz_fmadd_ps"; + case INTRINSIC_XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_fmadd_round_sd"; + case INTRINSIC_XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_fmadd_round_sd"; + case INTRINSIC_XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_fmadd_round_sd"; + case INTRINSIC_XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fmadd_round_ss"; + case INTRINSIC_XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fmadd_round_ss"; + case INTRINSIC_XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask3_fmadd_round_ss"; + case INTRINSIC_XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_fmaddsub_pd"; + case INTRINSIC_XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_fmaddsub_pd"; + case INTRINSIC_XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_fmaddsub_pd"; + case INTRINSIC_XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_fmaddsub_ps"; + case INTRINSIC_XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_fmaddsub_ps"; + case INTRINSIC_XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_fmaddsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_maskz_fmsub_pd"; + case INTRINSIC_XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_maskz_fmsub_pd"; + case INTRINSIC_XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_maskz_fmsub_pd"; + case INTRINSIC_XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_maskz_fmsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_maskz_fmsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_maskz_fmsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_fmsub_round_sd"; + case INTRINSIC_XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_fmsub_round_sd"; + case INTRINSIC_XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_fmsub_round_sd"; + case INTRINSIC_XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_fmsub_round_ss"; + case INTRINSIC_XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_fmsub_round_ss"; + case INTRINSIC_XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_fmsub_round_ss"; + case INTRINSIC_XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_fmsubadd_pd"; + case INTRINSIC_XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_fmsubadd_pd"; + case INTRINSIC_XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_fmsubadd_pd"; + case INTRINSIC_XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_fmsubadd_ps"; + case INTRINSIC_XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_fmsubadd_ps"; + case INTRINSIC_XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_fmsubadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_maskz_fnmadd_pd"; + case INTRINSIC_XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_maskz_fnmadd_pd"; + case INTRINSIC_XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_maskz_fnmadd_pd"; + case INTRINSIC_XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_maskz_fnmadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_maskz_fnmadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_maskz_fnmadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_fnmadd_round_sd"; + case INTRINSIC_XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_fnmadd_round_sd"; + case INTRINSIC_XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_fnmadd_round_sd"; + case INTRINSIC_XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_fnmadd_round_ss"; + case INTRINSIC_XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_fnmadd_round_ss"; + case INTRINSIC_XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_fnmadd_round_ss"; + case INTRINSIC_XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_maskz_fnmsub_pd"; + case INTRINSIC_XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_maskz_fnmsub_pd"; + case INTRINSIC_XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_maskz_fnmsub_pd"; + case INTRINSIC_XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_maskz_fnmsub_ps"; + case INTRINSIC_XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_maskz_fnmsub_ps"; + case INTRINSIC_XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_maskz_fnmsub_ps"; + case INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_fnmsub_round_sd"; + case INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_fnmsub_round_sd"; + case INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_fnmsub_round_sd"; + case INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_fnmsub_round_ss"; + case INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_fnmsub_round_ss"; + case INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_fnmsub_round_ss"; + case INTRINSIC_XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512: + return "_mm512_i32gather_pd"; + case INTRINSIC_XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512: + return "_mm512_i64gather_pd"; + case INTRINSIC_XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return "_mm512_maskz_getexp_pd"; + case INTRINSIC_XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return "_mm512_maskz_getexp_ps"; + case INTRINSIC_XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_getexp_round_sd"; + case INTRINSIC_XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_getexp_round_ss"; + case INTRINSIC_XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return "_mm512_maskz_getmant_pd"; + case INTRINSIC_XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return "_mm512_maskz_getmant_ps"; + case INTRINSIC_XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return "_mm_getmant_round_sd"; + case INTRINSIC_XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return "_mm_getmant_round_ss"; + case INTRINSIC_XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512: + return "_mm512_insertf32x4"; + case INTRINSIC_XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512: + return "_mm512_insertf64x4"; + case INTRINSIC_XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512: + return "_mm512_inserti32x4"; + case INTRINSIC_XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512: + return "_mm512_inserti64x4"; + case INTRINSIC_XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_mask_max_pd"; + case INTRINSIC_XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_mask_max_ps"; + case INTRINSIC_XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_max_round_sd"; + case INTRINSIC_XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_max_round_ss"; + case INTRINSIC_XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_mask_min_pd"; + case INTRINSIC_XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_mask_min_ps"; + case INTRINSIC_XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_min_round_sd"; + case INTRINSIC_XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_min_round_ss"; + case INTRINSIC_XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512: + return "_mm512_maskz_load_pd"; + case INTRINSIC_XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return "_mm512_maskz_mov_pd"; + case INTRINSIC_XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512: + return "_mm512_maskz_load_ps"; + case INTRINSIC_XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return "_mm512_maskz_mov_ps"; + case INTRINSIC_XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512: + return "_mm512_mask_movedup_pd"; + case INTRINSIC_XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512: + return "_mm512_maskz_load_epi32"; + case INTRINSIC_XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512: + return "_mm512_maskz_mov_epi32"; + case INTRINSIC_XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512: + return "_mm512_maskz_load_epi64"; + case INTRINSIC_XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512: + return "_mm512_maskz_mov_epi64"; + case INTRINSIC_XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512: + return "_mm512_stream_load_si512"; + case INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512: + return "_mm512_stream_si512"; + case INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512: + return "_mm512_stream_pd"; + case INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512: + return "_mm512_stream_ps"; + case INTRINSIC_XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512: + return "_mm_mask_load_sd"; + case INTRINSIC_XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_move_sd"; + case INTRINSIC_XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512: + return "_mm_mask_store_sd"; + case INTRINSIC_XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512: + return "_mm512_mask_movehdup_ps"; + case INTRINSIC_XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512: + return "_mm512_mask_moveldup_ps"; + case INTRINSIC_XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512: + return "_mm_mask_load_ss"; + case INTRINSIC_XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_move_ss"; + case INTRINSIC_XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512: + return "_mm_mask_store_ss"; + case INTRINSIC_XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512: + return "_mm512_loadu_pd"; + case INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512: + return "_mm512_mask_storeu_pd"; + case INTRINSIC_XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512: + return "_mm512_loadu_ps"; + case INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512: + return "_mm512_mask_storeu_ps"; + case INTRINSIC_XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_maskz_mul_pd"; + case INTRINSIC_XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_maskz_mul_ps"; + case INTRINSIC_XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_mul_round_sd"; + case INTRINSIC_XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_mul_round_ss"; + case INTRINSIC_XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512: + return "_mm512_abs_epi32"; + case INTRINSIC_XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512: + return "_mm512_abs_epi64"; + case INTRINSIC_XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_maskz_add_epi32"; + case INTRINSIC_XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_add_epi64"; + case INTRINSIC_XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_maskz_and_epi32"; + case INTRINSIC_XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_maskz_andnot_epi32"; + case INTRINSIC_XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_maskz_andnot_epi64"; + case INTRINSIC_XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_maskz_and_epi64"; + case INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512: + return "_mm512_broadcastd_epi32"; + case INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512: + return "_mm512_mask_set1_epi32"; + case INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512: + return "_mm512_broadcastq_epi64"; + case INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512: + return "_mm512_mask_set1_epi64"; + case INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512: + return "_mm512_cmplt_epi32_mask"; + case INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512: + return "_mm512_cmp_epi64_mask"; + case INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_cmpeq_epi64_mask"; + case INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512: + return "_mm512_cmpgt_epi64_mask"; + case INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return "_mm512_cmp_epu64_mask"; + case INTRINSIC_XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512: + return "_mm512_mask_compress_epi32"; + case INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512: + return "_mm512_mask_compressstoreu_epi32"; + case INTRINSIC_XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512: + return "_mm512_mask_compress_epi64"; + case INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512: + return "_mm512_mask_compressstoreu_epi64"; + case INTRINSIC_XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_mask_permutexvar_epi32"; + case INTRINSIC_XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_mask2_permutex2var_epi32"; + case INTRINSIC_XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_mask_permutex2var_epi32"; + case INTRINSIC_XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_mask2_permutex2var_pd"; + case INTRINSIC_XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_mask_permutex2var_pd"; + case INTRINSIC_XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_mask2_permutex2var_ps"; + case INTRINSIC_XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_mask_permutex2var_ps"; + case INTRINSIC_XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask2_permutex2var_epi64"; + case INTRINSIC_XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_permutex2var_epi64"; + case INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return "_mm512_mask_permute_pd"; + case INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_mask_permutevar_pd"; + case INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return "_mm512_mask_permute_ps"; + case INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_mask_permutevar_ps"; + case INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return "_mm512_mask_permutex_pd"; + case INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_mask_permutexvar_pd"; + case INTRINSIC_XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_mask_permutexvar_ps"; + case INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return "_mm512_mask_permutex_epi64"; + case INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_permutexvar_epi64"; + case INTRINSIC_XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512: + return "_mm512_mask_expand_epi32"; + case INTRINSIC_XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512: + return "_mm512_mask_expandloadu_epi32"; + case INTRINSIC_XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512: + return "_mm512_mask_expand_epi64"; + case INTRINSIC_XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512: + return "_mm512_mask_expandloadu_epi64"; + case INTRINSIC_XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512: + return "_mm512_i32gather_epi64"; + case INTRINSIC_XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512: + return "_mm512_i64gather_epi32"; + case INTRINSIC_XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512: + return "_mm512_i64gather_epi64"; + case INTRINSIC_XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512: + return "_mm512_maskz_max_epi32"; + case INTRINSIC_XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512: + return "_mm512_mask_max_epi64"; + case INTRINSIC_XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_maskz_max_epu32"; + case INTRINSIC_XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_max_epu64"; + case INTRINSIC_XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512: + return "_mm512_maskz_min_epi32"; + case INTRINSIC_XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512: + return "_mm512_mask_min_epi64"; + case INTRINSIC_XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_maskz_min_epu32"; + case INTRINSIC_XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_min_epu64"; + case INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512: + return "_mm512_cvtepi32_epi8"; + case INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512: + return "_mm512_mask_cvtepi32_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512: + return "_mm512_cvtepi32_epi16"; + case INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512: + return "_mm512_mask_cvtepi32_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512: + return "_mm512_cvtepi64_epi8"; + case INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512: + return "_mm512_mask_cvtepi64_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512: + return "_mm512_cvtepi64_epi32"; + case INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512: + return "_mm512_mask_cvtepi64_storeu_epi32"; + case INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512: + return "_mm512_cvtepi64_epi16"; + case INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512: + return "_mm512_mask_cvtepi64_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512: + return "_mm512_cvtsepi32_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512: + return "_mm512_mask_cvtsepi32_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512: + return "_mm512_cvtsepi32_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512: + return "_mm512_mask_cvtsepi32_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512: + return "_mm512_cvtsepi64_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512: + return "_mm512_mask_cvtsepi64_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512: + return "_mm512_cvtsepi64_epi32"; + case INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512: + return "_mm512_mask_cvtsepi64_storeu_epi32"; + case INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512: + return "_mm512_cvtsepi64_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512: + return "_mm512_mask_cvtsepi64_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512: + return "_mm512_cvtepi8_epi32"; + case INTRINSIC_XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512: + return "_mm512_cvtepi8_epi64"; + case INTRINSIC_XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512: + return "_mm512_cvtepi32_epi64"; + case INTRINSIC_XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512: + return "_mm512_cvtepi16_epi32"; + case INTRINSIC_XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512: + return "_mm512_cvtepi16_epi64"; + case INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512: + return "_mm512_cvtusepi32_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512: + return "_mm512_mask_cvtusepi32_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512: + return "_mm512_cvtusepi32_epi16"; + case INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512: + return "_mm512_mask_cvtusepi32_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512: + return "_mm512_cvtusepi64_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512: + return "_mm512_mask_cvtusepi64_storeu_epi8"; + case INTRINSIC_XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512: + return "_mm512_cvtusepi64_epi32"; + case INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512: + return "_mm512_mask_cvtusepi64_storeu_epi32"; + case INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512: + return "_mm512_cvtusepi64_epi16"; + case INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512: + return "_mm512_mask_cvtusepi64_storeu_epi16"; + case INTRINSIC_XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512: + return "_mm512_cvtepu8_epi32"; + case INTRINSIC_XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512: + return "_mm512_cvtepu8_epi64"; + case INTRINSIC_XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512: + return "_mm512_cvtepu32_epi64"; + case INTRINSIC_XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512: + return "_mm512_cvtepu16_epi32"; + case INTRINSIC_XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512: + return "_mm512_cvtepu16_epi64"; + case INTRINSIC_XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512: + return "_mm512_mask_mul_epi32"; + case INTRINSIC_XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_mask_mul_epu32"; + case INTRINSIC_XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_maskz_or_epi32"; + case INTRINSIC_XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_maskz_or_epi64"; + case INTRINSIC_XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return "_mm512_mask_rol_epi32"; + case INTRINSIC_XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return "_mm512_mask_rol_epi64"; + case INTRINSIC_XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_mask_rolv_epi32"; + case INTRINSIC_XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_rolv_epi64"; + case INTRINSIC_XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return "_mm512_mask_ror_epi32"; + case INTRINSIC_XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return "_mm512_mask_ror_epi64"; + case INTRINSIC_XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_mask_rorv_epi32"; + case INTRINSIC_XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_rorv_epi64"; + case INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512: + return "_mm512_i32scatter_epi64"; + case INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512: + return "_mm512_i64scatter_epi32"; + case INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512: + return "_mm512_i64scatter_epi64"; + case INTRINSIC_XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return "_mm512_maskz_shuffle_epi32"; + case INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512: + return "_mm512_mask_sll_epi32"; + case INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return "_mm512_maskz_slli_epi32"; + case INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512: + return "_mm512_mask_sll_epi64"; + case INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return "_mm512_mask_slli_epi64"; + case INTRINSIC_XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_maskz_sllv_epi32"; + case INTRINSIC_XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_sllv_epi64"; + case INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512: + return "_mm512_mask_sra_epi32"; + case INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return "_mm512_maskz_srai_epi32"; + case INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512: + return "_mm512_mask_sra_epi64"; + case INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return "_mm512_mask_srai_epi64"; + case INTRINSIC_XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_maskz_srav_epi32"; + case INTRINSIC_XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_srav_epi64"; + case INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512: + return "_mm512_mask_srl_epi32"; + case INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return "_mm512_maskz_srli_epi32"; + case INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512: + return "_mm512_mask_srl_epi64"; + case INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return "_mm512_mask_srli_epi64"; + case INTRINSIC_XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_maskz_srlv_epi32"; + case INTRINSIC_XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_srlv_epi64"; + case INTRINSIC_XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_maskz_sub_epi32"; + case INTRINSIC_XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_sub_epi64"; + case INTRINSIC_XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return "_mm512_mask_ternarylogic_epi32"; + case INTRINSIC_XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return "_mm512_mask_ternarylogic_epi64"; + case INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_test_epi64_mask"; + case INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_mask_testn_epi32_mask"; + case INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_testn_epi64_mask"; + case INTRINSIC_XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_mask_unpackhi_epi32"; + case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_unpackhi_epi64"; + case INTRINSIC_XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_mask_unpacklo_epi32"; + case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_unpacklo_epi64"; + case INTRINSIC_XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_maskz_xor_epi32"; + case INTRINSIC_XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_maskz_xor_epi64"; + case INTRINSIC_XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return "_mm512_mask_rcp14_pd"; + case INTRINSIC_XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return "_mm512_mask_rcp14_ps"; + case INTRINSIC_XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_rcp14_sd"; + case INTRINSIC_XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_rcp14_ss"; + case INTRINSIC_XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return "_mm512_mask_roundscale_pd"; + case INTRINSIC_XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return "_mm512_mask_roundscale_ps"; + case INTRINSIC_XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return "_mm_mask_roundscale_round_sd"; + case INTRINSIC_XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return "_mm_mask_roundscale_round_ss"; + case INTRINSIC_XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return "_mm512_mask_rsqrt14_pd"; + case INTRINSIC_XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return "_mm512_mask_rsqrt14_ps"; + case INTRINSIC_XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_rsqrt14_sd"; + case INTRINSIC_XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_rsqrt14_ss"; + case INTRINSIC_XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_mask_scalef_pd"; + case INTRINSIC_XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_mask_scalef_ps"; + case INTRINSIC_XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_scalef_round_sd"; + case INTRINSIC_XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_scalef_round_ss"; + case INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512: + return "_mm512_i32scatter_pd"; + case INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512: + return "_mm512_i64scatter_pd"; + case INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512: + return "_mm512_i64scatter_ps"; + case INTRINSIC_XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + return "_mm512_mask_shuffle_f32x4"; + case INTRINSIC_XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + return "_mm512_mask_shuffle_f64x2"; + case INTRINSIC_XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return "_mm512_mask_shuffle_i32x4"; + case INTRINSIC_XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return "_mm512_mask_shuffle_i64x2"; + case INTRINSIC_XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + return "_mm512_mask_shuffle_pd"; + case INTRINSIC_XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + return "_mm512_mask_shuffle_ps"; + case INTRINSIC_XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return "_mm512_mask_sqrt_pd"; + case INTRINSIC_XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return "_mm512_mask_sqrt_ps"; + case INTRINSIC_XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_sqrt_round_sd"; + case INTRINSIC_XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_sqrt_round_ss"; + case INTRINSIC_XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_maskz_sub_pd"; + case INTRINSIC_XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_maskz_sub_ps"; + case INTRINSIC_XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return "_mm_mask_sub_round_sd"; + case INTRINSIC_XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_mask_sub_round_ss"; + case INTRINSIC_XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_mask_unpackhi_pd"; + case INTRINSIC_XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_mask_unpackhi_ps"; + case INTRINSIC_XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_mask_unpacklo_pd"; + case INTRINSIC_XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_mask_unpacklo_ps"; + case INTRINSIC_XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512: + return "_mm512_cvtsi512_si32"; + case INTRINSIC_XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return "_mm512_mask_blend_pd"; + case INTRINSIC_XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_mask_blend_ps"; + case INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + return "_mm512_cmp_pd_mask"; + case INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + return "_mm512_cmp_ps_mask"; + case INTRINSIC_XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512: + return "_mm512_i32gather_ps"; + case INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512: + return "_mm512_mask_store_pd"; + case INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512: + return "_mm512_mask_store_ps"; + case INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512: + return "_mm512_mask_store_epi32"; + case INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512: + return "_mm512_mask_store_epi64"; + case INTRINSIC_XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_mask_blend_epi32"; + case INTRINSIC_XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_mask_blend_epi64"; + case INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_cmpeq_epi32_mask"; + case INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512: + return "_mm512_cmpgt_epi32_mask"; + case INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return "_mm512_cmp_epu32_mask"; + case INTRINSIC_XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512: + return "_mm512_i32gather_epi32"; + case INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512: + return "_mm512_i32scatter_epi32"; + case INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_mask_test_epi32_mask"; + case INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512: + return "_mm512_i32scatter_ps"; + case INTRINSIC_XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return "_mm512_abs_ps"; + case INTRINSIC_XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return "_mm512_abs_pd"; + case INTRINSIC_XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_madd52lo_epu64"; + case INTRINSIC_XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_madd52lo_epu64"; + case INTRINSIC_XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_madd52lo_epu64"; + case INTRINSIC_XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_madd52hi_epu64"; + case INTRINSIC_XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_madd52hi_epu64"; + case INTRINSIC_XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_madd52hi_epu64"; + case INTRINSIC_XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512: + return "_mm512_prefetch_i64gather_ps"; + case INTRINSIC_XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512: + return "_mm512_prefetch_i64gather_ps"; + case INTRINSIC_XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512: + return "_mm512_prefetch_i64scatter_ps"; + case INTRINSIC_XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512: + return "_mm512_prefetch_i64scatter_ps"; + case INTRINSIC_XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512: + return "_mm512_prefetch_i32gather_pd"; + case INTRINSIC_XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512: + return "_mm512_prefetch_i32gather_pd"; + case INTRINSIC_XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512: + return "_mm512_prefetch_i32scatter_pd"; + case INTRINSIC_XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512: + return "_mm512_prefetch_i32scatter_pd"; + case INTRINSIC_XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512: + return "_mm512_prefetch_i64gather_pd"; + case INTRINSIC_XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512: + return "_mm512_prefetch_i64gather_pd"; + case INTRINSIC_XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512: + return "_mm512_prefetch_i64scatter_pd"; + case INTRINSIC_XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512: + return "_mm512_prefetch_i64scatter_pd"; + case INTRINSIC_XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512: + return "_mm512_mask_prefetch_i32gather_ps"; + case INTRINSIC_XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512: + return "_mm512_mask_prefetch_i32gather_ps"; + case INTRINSIC_XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512: + return "_mm512_prefetch_i32extscatter_ps"; + case INTRINSIC_XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512: + return "_mm512_prefetch_i32extscatter_ps"; + case INTRINSIC_XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512: + return "_mm256_maskz_popcnt_epi64"; + case INTRINSIC_XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512: + return "_mm_maskz_popcnt_epi64"; + case INTRINSIC_XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512: + return "_mm256_popcnt_epi32"; + case INTRINSIC_XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512: + return "_mm_popcnt_epi32"; + case INTRINSIC_XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512: + return "_mm512_popcnt_epi32"; + case INTRINSIC_XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512: + return "_mm512_popcnt_epi64"; + case INTRINSIC_XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return "_mm512_4fmadd_ps"; + case INTRINSIC_XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return "_mm512_4fnmadd_ps"; + case INTRINSIC_XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return "_mm_4fmadd_ss"; + case INTRINSIC_XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return "_mm_4fnmadd_ss"; + case INTRINSIC_XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512: + return "_mm512_4dpwssd_epi32"; + case INTRINSIC_XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512: + return "_mm512_4dpwssds_epi32"; + case INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512: + return "_mm_cvtne2ps_pbh"; + case INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512: + return "_mm256_cvtne2ps_pbh"; + case INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512: + return "_mm512_cvtne2ps_pbh"; + case INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512: + return "_mm_cvtneps_pbh"; + case INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512: + return "_mm256_cvtneps_pbh"; + case INTRINSIC_XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512: + return "_mm512_cvtneps_pbh"; + case INTRINSIC_XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_dpbf16_ps"; + case INTRINSIC_XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_dpbf16_ps"; + case INTRINSIC_XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_dpbf16_ps"; + case INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512: + return "_mm512_mask_bitshuffle_epi64_mask"; + case INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512: + return "_mm256_mask_bitshuffle_epi64_mask"; + case INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512: + return "_mm_mask_bitshuffle_epi64_mask"; + case INTRINSIC_XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512: + return "_mm512_popcnt_epi16"; + case INTRINSIC_XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512: + return "_mm256_popcnt_epi16"; + case INTRINSIC_XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512: + return "_mm_popcnt_epi16"; + case INTRINSIC_XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512: + return "_mm512_popcnt_epi8"; + case INTRINSIC_XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512: + return "_mm256_popcnt_epi8"; + case INTRINSIC_XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512: + return "_mm_popcnt_epi8"; + case INTRINSIC_XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512: + return "_mm512_multishift_epi64_epi8"; + case INTRINSIC_XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512: + return "_mm256_multishift_epi64_epi8"; + case INTRINSIC_XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512: + return "_mm_multishift_epi64_epi8"; + case INTRINSIC_XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_permutexvar_epi8"; + case INTRINSIC_XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_permutexvar_epi8"; + case INTRINSIC_XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_permutexvar_epi8"; + case INTRINSIC_XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_permutex2var_epi8"; + case INTRINSIC_XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_mask_permutex2var_epi8"; + case INTRINSIC_XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_permutex2var_epi8"; + case INTRINSIC_XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_mask_permutex2var_epi8"; + case INTRINSIC_XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_permutex2var_epi8"; + case INTRINSIC_XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_mask_permutex2var_epi8"; + case INTRINSIC_XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_maskz_shrdv_epi64"; + case INTRINSIC_XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_maskz_shrdv_epi64"; + case INTRINSIC_XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_maskz_shrdv_epi64"; + case INTRINSIC_XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_maskz_shrdv_epi32"; + case INTRINSIC_XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_maskz_shrdv_epi32"; + case INTRINSIC_XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_maskz_shrdv_epi32"; + case INTRINSIC_XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_maskz_shrdv_epi16"; + case INTRINSIC_XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_maskz_shrdv_epi16"; + case INTRINSIC_XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_maskz_shrdv_epi16"; + case INTRINSIC_XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return "_mm512_maskz_shrdi_epi64"; + case INTRINSIC_XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return "_mm256_maskz_shrdi_epi64"; + case INTRINSIC_XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + return "_mm_maskz_shrdi_epi64"; + case INTRINSIC_XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return "_mm512_maskz_shrdi_epi32"; + case INTRINSIC_XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return "_mm256_maskz_shrdi_epi32"; + case INTRINSIC_XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + return "_mm_maskz_shrdi_epi32"; + case INTRINSIC_XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512: + return "_mm512_maskz_shrdi_epi16"; + case INTRINSIC_XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512: + return "_mm256_maskz_shrdi_epi16"; + case INTRINSIC_XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512: + return "_mm_maskz_shrdi_epi16"; + case INTRINSIC_XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_maskz_shldv_epi64"; + case INTRINSIC_XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_maskz_shldv_epi64"; + case INTRINSIC_XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_maskz_shldv_epi64"; + case INTRINSIC_XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_maskz_shldv_epi32"; + case INTRINSIC_XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_maskz_shldv_epi32"; + case INTRINSIC_XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_maskz_shldv_epi32"; + case INTRINSIC_XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return "_mm512_maskz_shldv_epi16"; + case INTRINSIC_XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return "_mm256_maskz_shldv_epi16"; + case INTRINSIC_XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return "_mm_maskz_shldv_epi16"; + case INTRINSIC_XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return "_mm512_maskz_shldi_epi64"; + case INTRINSIC_XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return "_mm256_maskz_shldi_epi64"; + case INTRINSIC_XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + return "_mm_maskz_shldi_epi64"; + case INTRINSIC_XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return "_mm512_maskz_shldi_epi32"; + case INTRINSIC_XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return "_mm256_maskz_shldi_epi32"; + case INTRINSIC_XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + return "_mm_maskz_shldi_epi32"; + case INTRINSIC_XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512: + return "_mm512_maskz_shldi_epi16"; + case INTRINSIC_XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512: + return "_mm256_maskz_shldi_epi16"; + case INTRINSIC_XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512: + return "_mm_maskz_shldi_epi16"; + case INTRINSIC_XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512: + return "_mm512_maskz_expandloadu_epi16"; + case INTRINSIC_XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512: + return "_mm512_maskz_expand_epi16"; + case INTRINSIC_XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512: + return "_mm256_maskz_expandloadu_epi16"; + case INTRINSIC_XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512: + return "_mm256_maskz_expand_epi16"; + case INTRINSIC_XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512: + return "_mm_maskz_expandloadu_epi16"; + case INTRINSIC_XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512: + return "_mm_maskz_expand_epi16"; + case INTRINSIC_XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512: + return "_mm512_maskz_expandloadu_epi8"; + case INTRINSIC_XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512: + return "_mm256_maskz_expandloadu_epi8"; + case INTRINSIC_XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512: + return "_mm_maskz_expandloadu_epi8"; + case INTRINSIC_XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512: + return "_mm512_maskz_expand_epi8"; + case INTRINSIC_XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512: + return "_mm256_maskz_expand_epi8"; + case INTRINSIC_XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512: + return "_mm_maskz_expand_epi8"; + case INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512: + return "_mm512_mask_compressstoreu_epi16"; + case INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512: + return "_mm256_mask_compressstoreu_epi16"; + case INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512: + return "_mm_mask_compressstoreu_epi16"; + case INTRINSIC_XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512: + return "_mm512_maskz_compress_epi16"; + case INTRINSIC_XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512: + return "_mm256_maskz_compress_epi16"; + case INTRINSIC_XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512: + return "_mm_maskz_compress_epi16"; + case INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512: + return "_mm512_mask_compressstoreu_epi8"; + case INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512: + return "_mm256_mask_compressstoreu_epi8"; + case INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512: + return "_mm_mask_compressstoreu_epi8"; + case INTRINSIC_XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512: + return "_mm512_maskz_compress_epi8"; + case INTRINSIC_XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512: + return "_mm256_maskz_compress_epi8"; + case INTRINSIC_XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512: + return "_mm_maskz_compress_epi8"; + case INTRINSIC_XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512: + return "_mm512_maskz_dpwssds_epi32"; + case INTRINSIC_XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512: + return "_mm256_maskz_dpwssds_epi32"; + case INTRINSIC_XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512: + return "_mm_maskz_dpwssds_epi32"; + case INTRINSIC_XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512: + return "_mm512_maskz_dpwssd_epi32"; + case INTRINSIC_XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512: + return "_mm256_maskz_dpwssd_epi32"; + case INTRINSIC_XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512: + return "_mm_maskz_dpwssd_epi32"; + case INTRINSIC_XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512: + return "_mm512_maskz_dpbusds_epi32"; + case INTRINSIC_XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512: + return "_mm256_maskz_dpbusds_epi32"; + case INTRINSIC_XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512: + return "_mm_maskz_dpbusds_epi32"; + case INTRINSIC_XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512: + return "_mm512_maskz_dpbusd_epi32"; + case INTRINSIC_XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512: + return "_mm256_maskz_dpbusd_epi32"; + case INTRINSIC_XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512: + return "_mm_maskz_dpbusd_epi32"; + case INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512: + return "_mm_2intersect_epi32"; + case INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512: + return "_mm256_2intersect_epi32"; + case INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512: + return "_mm512_2intersect_epi32"; + case INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512: + return "_mm_2intersect_epi64"; + case INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512: + return "_mm256_2intersect_epi64"; + case INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512: + return "_mm512_2intersect_epi64"; + case INTRINSIC_XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d: + return "_bextr_u32"; + case INTRINSIC_XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q: + return "_bextr_u64"; + case INTRINSIC_XED_IFORM_BLSI_VGPR32d_VGPR32d: + return "_blsi_u32"; + case INTRINSIC_XED_IFORM_BLSI_VGPR64q_VGPR64q: + return "_blsi_u64"; + case INTRINSIC_XED_IFORM_BLSMSK_VGPR32d_VGPR32d: + return "_blsmsk_u32"; + case INTRINSIC_XED_IFORM_BLSMSK_VGPR64q_VGPR64q: + return "_blsmsk_u64"; + case INTRINSIC_XED_IFORM_BLSR_VGPR32d_VGPR32d: + return "_blsr_u32"; + case INTRINSIC_XED_IFORM_BLSR_VGPR64q_VGPR64q: + return "_blsr_u64"; + case INTRINSIC_XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d: + return "_andn_u32"; + case INTRINSIC_XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q: + return "_andn_u64"; + case INTRINSIC_XED_IFORM_TZCNT_GPRv_GPRv: + return "_tzcnt_u32"; + case INTRINSIC_XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d: + return "_bzhi_u32"; + case INTRINSIC_XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q: + return "_bzhi_u64"; + case INTRINSIC_XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d: + return "_pdep_u32"; + case INTRINSIC_XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q: + return "_pdep_u64"; + case INTRINSIC_XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d: + return "_pext_u32"; + case INTRINSIC_XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q: + return "_pext_u64"; + case INTRINSIC_XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd: + return "_mulx_u32"; + case INTRINSIC_XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq: + return "_mulx_u64"; + case INTRINSIC_XED_IFORM_INCSSPD_GPR32u8: + return "_incsspd"; + case INTRINSIC_XED_IFORM_INCSSPQ_GPR64u8: + return "_incsspq"; + case INTRINSIC_XED_IFORM_RDSSPD_GPR32u32: + return "_rdsspd_i32"; + case INTRINSIC_XED_IFORM_RDSSPQ_GPR64u64: + return "_rdsspq_i64"; + case INTRINSIC_XED_IFORM_SAVEPREVSSP: + return "_saveprevssp"; + case INTRINSIC_XED_IFORM_RSTORSSP_MEMu64: + return "_rstorssp"; + case INTRINSIC_XED_IFORM_WRSSD_MEMu32_GPR32u32: + return "_wrssd"; + case INTRINSIC_XED_IFORM_WRSSQ_MEMu64_GPR64u64: + return "_wrssq"; + case INTRINSIC_XED_IFORM_WRUSSD_MEMu32_GPR32u32: + return "_wrussd"; + case INTRINSIC_XED_IFORM_WRUSSQ_MEMu64_GPR64u64: + return "_wrussq"; + case INTRINSIC_XED_IFORM_SETSSBSY: + return "_setssbsy"; + case INTRINSIC_XED_IFORM_CLRSSBSY_MEMu64: + return "_clrssbsy"; + case INTRINSIC_XED_IFORM_CLDEMOTE_MEMu8: + return "_mm_cldemote"; + case INTRINSIC_XED_IFORM_CLFLUSHOPT_MEMmprefetch: + return "_mm_clflushopt"; + case INTRINSIC_XED_IFORM_CLWB_MEMmprefetch: + return "_mm_clwb"; + case INTRINSIC_XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq: + return "_mm_fmadd_pd"; + case INTRINSIC_XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq: + return "_mm_fmadd_pd"; + case INTRINSIC_XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq: + return "_mm_fmadd_pd"; + case INTRINSIC_XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fmadd_pd"; + case INTRINSIC_XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fmadd_pd"; + case INTRINSIC_XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fmadd_pd"; + case INTRINSIC_XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq: + return "_mm_fmadd_ps"; + case INTRINSIC_XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq: + return "_mm_fmadd_ps"; + case INTRINSIC_XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq: + return "_mm_fmadd_ps"; + case INTRINSIC_XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fmadd_ps"; + case INTRINSIC_XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fmadd_ps"; + case INTRINSIC_XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fmadd_ps"; + case INTRINSIC_XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq: + return "_mm_fmadd_sd"; + case INTRINSIC_XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq: + return "_mm_fmadd_sd"; + case INTRINSIC_XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq: + return "_mm_fmadd_sd"; + case INTRINSIC_XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd: + return "_mm_fmadd_ss"; + case INTRINSIC_XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd: + return "_mm_fmadd_ss"; + case INTRINSIC_XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd: + return "_mm_fmadd_ss"; + case INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq: + return "_mm_fmaddsub_pd"; + case INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq: + return "_mm_fmaddsub_pd"; + case INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq: + return "_mm_fmaddsub_pd"; + case INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fmaddsub_pd"; + case INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fmaddsub_pd"; + case INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fmaddsub_pd"; + case INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq: + return "_mm_fmaddsub_ps"; + case INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq: + return "_mm_fmaddsub_ps"; + case INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq: + return "_mm_fmaddsub_ps"; + case INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fmaddsub_ps"; + case INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fmaddsub_ps"; + case INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fmaddsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq: + return "_mm_fmsub_pd"; + case INTRINSIC_XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq: + return "_mm_fmsub_pd"; + case INTRINSIC_XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq: + return "_mm_fmsub_pd"; + case INTRINSIC_XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fmsub_pd"; + case INTRINSIC_XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fmsub_pd"; + case INTRINSIC_XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fmsub_pd"; + case INTRINSIC_XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq: + return "_mm_fmsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq: + return "_mm_fmsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq: + return "_mm_fmsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fmsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fmsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fmsub_ps"; + case INTRINSIC_XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq: + return "_mm_fmsub_sd"; + case INTRINSIC_XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq: + return "_mm_fmsub_sd"; + case INTRINSIC_XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq: + return "_mm_fmsub_sd"; + case INTRINSIC_XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd: + return "_mm_fmsub_ss"; + case INTRINSIC_XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd: + return "_mm_fmsub_ss"; + case INTRINSIC_XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd: + return "_mm_fmsub_ss"; + case INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq: + return "_mm_fmsubadd_pd"; + case INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq: + return "_mm_fmsubadd_pd"; + case INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq: + return "_mm_fmsubadd_pd"; + case INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fmsubadd_pd"; + case INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fmsubadd_pd"; + case INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fmsubadd_pd"; + case INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq: + return "_mm_fmsubadd_ps"; + case INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq: + return "_mm_fmsubadd_ps"; + case INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq: + return "_mm_fmsubadd_ps"; + case INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fmsubadd_ps"; + case INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fmsubadd_ps"; + case INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fmsubadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq: + return "_mm_fnmadd_pd"; + case INTRINSIC_XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq: + return "_mm_fnmadd_pd"; + case INTRINSIC_XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq: + return "_mm_fnmadd_pd"; + case INTRINSIC_XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fnmadd_pd"; + case INTRINSIC_XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fnmadd_pd"; + case INTRINSIC_XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fnmadd_pd"; + case INTRINSIC_XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq: + return "_mm_fnmadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq: + return "_mm_fnmadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq: + return "_mm_fnmadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fnmadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fnmadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fnmadd_ps"; + case INTRINSIC_XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq: + return "_mm_fnmadd_sd"; + case INTRINSIC_XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq: + return "_mm_fnmadd_sd"; + case INTRINSIC_XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq: + return "_mm_fnmadd_sd"; + case INTRINSIC_XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd: + return "_mm_fnmadd_ss"; + case INTRINSIC_XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd: + return "_mm_fnmadd_ss"; + case INTRINSIC_XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd: + return "_mm_fnmadd_ss"; + case INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq: + return "_mm_fnmsub_pd"; + case INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq: + return "_mm_fnmsub_pd"; + case INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq: + return "_mm_fnmsub_pd"; + case INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fnmsub_pd"; + case INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fnmsub_pd"; + case INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq: + return "_mm256_fnmsub_pd"; + case INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq: + return "_mm_fnmsub_ps"; + case INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq: + return "_mm_fnmsub_ps"; + case INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq: + return "_mm_fnmsub_ps"; + case INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fnmsub_ps"; + case INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fnmsub_ps"; + case INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq: + return "_mm256_fnmsub_ps"; + case INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq: + return "_mm_fnmsub_sd"; + case INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq: + return "_mm_fnmsub_sd"; + case INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq: + return "_mm_fnmsub_sd"; + case INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd: + return "_mm_fnmsub_ss"; + case INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd: + return "_mm_fnmsub_ss"; + case INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd: + return "_mm_fnmsub_ss"; + case INTRINSIC_XED_IFORM_VCVTPH2PS_YMMqq_XMMdq: + return "_mm256_cvtph_ps"; + case INTRINSIC_XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb: + return "_mm256_cvtps_ph"; + case INTRINSIC_XED_IFORM_VCVTPH2PS_XMMdq_XMMq: + return "_mm_cvtph_ps"; + case INTRINSIC_XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb: + return "_mm_cvtps_ph"; + case INTRINSIC_XED_IFORM_RDFSBASE_GPRy: + return "_readfsbase_u32"; + case INTRINSIC_XED_IFORM_RDGSBASE_GPRy: + return "_readgsbase_u32"; + case INTRINSIC_XED_IFORM_WRFSBASE_GPRy: + return "_writefsbase_u32"; + case INTRINSIC_XED_IFORM_WRGSBASE_GPRy: + return "_writegsbase_u32"; + case INTRINSIC_XED_IFORM_FXRSTOR_MEMmfpxenv: + return "_fxrstor"; + case INTRINSIC_XED_IFORM_FXRSTOR64_MEMmfpxenv: + return "_fxrstor64"; + case INTRINSIC_XED_IFORM_FXSAVE_MEMmfpxenv: + return "_fxsave"; + case INTRINSIC_XED_IFORM_FXSAVE64_MEMmfpxenv: + return "_fxsave64"; + case INTRINSIC_XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return "_mm512_maskz_gf2p8mul_epi8"; + case INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return "_mm256_maskz_gf2p8mul_epi8"; + case INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return "_mm_maskz_gf2p8mul_epi8"; + case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512: + return "_mm512_maskz_gf2p8affine_epi64_epi8"; + case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512: + return "_mm256_maskz_gf2p8affine_epi64_epi8"; + case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512: + return "_mm_maskz_gf2p8affine_epi64_epi8"; + case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512: + return "_mm512_maskz_gf2p8affineinv_epi64_epi8"; + case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512: + return "_mm256_maskz_gf2p8affineinv_epi64_epi8"; + case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512: + return "_mm_maskz_gf2p8affineinv_epi64_epi8"; + case INTRINSIC_XED_IFORM_INVPCID_GPR32_MEMdq: + return "_invpcid"; + case INTRINSIC_XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512: + return "_mm512_extload_ps"; + case INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512: + return "_mm512_extload_epi32"; + case INTRINSIC_XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512: + return "_mm512_extload_pd"; + case INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512: + return "_mm512_extload_epi64"; + case INTRINSIC_XED_IFORM_POPCNT_GPRv_GPRv: + return "_mm_countbits_32"; + case INTRINSIC_XED_IFORM_LZCNT_GPRv_GPRv: + return "_lzcnt_u32"; + case INTRINSIC_XED_IFORM_MOVQ_MMXq_GPR64: + return "_m_from_int64"; + case INTRINSIC_XED_IFORM_MOVQ_GPR64_MMXq: + return "_m_to_int64"; + case INTRINSIC_XED_IFORM_EMMS: + return "_m_empty"; + case INTRINSIC_XED_IFORM_MOVD_MMXq_GPR32: + return "_m_from_int"; + case INTRINSIC_XED_IFORM_MOVD_GPR32_MMXd: + return "_m_to_int"; + case INTRINSIC_XED_IFORM_PACKSSWB_MMXq_MMXq: + return "_m_packsswb"; + case INTRINSIC_XED_IFORM_PACKSSDW_MMXq_MMXq: + return "_m_packssdw"; + case INTRINSIC_XED_IFORM_PACKUSWB_MMXq_MMXq: + return "_m_packuswb"; + case INTRINSIC_XED_IFORM_PUNPCKHBW_MMXq_MMXd: + return "_m_punpckhbw"; + case INTRINSIC_XED_IFORM_PUNPCKLBW_MMXq_MMXd: + return "_m_punpckhwd"; + case INTRINSIC_XED_IFORM_PUNPCKHDQ_MMXq_MMXd: + return "_m_punpckhdq"; + case INTRINSIC_XED_IFORM_PUNPCKLWD_MMXq_MMXd: + return "_m_punpcklwd"; + case INTRINSIC_XED_IFORM_PUNPCKLDQ_MMXq_MMXd: + return "_m_punpckldq"; + case INTRINSIC_XED_IFORM_PADDB_MMXq_MMXq: + return "_m_paddb"; + case INTRINSIC_XED_IFORM_PADDW_MMXq_MMXq: + return "_m_paddw"; + case INTRINSIC_XED_IFORM_PADDD_MMXq_MMXq: + return "_m_paddd"; + case INTRINSIC_XED_IFORM_PADDSB_MMXq_MMXq: + return "_m_paddsb"; + case INTRINSIC_XED_IFORM_PADDSW_MMXq_MMXq: + return "_m_paddsw"; + case INTRINSIC_XED_IFORM_PADDUSB_MMXq_MMXq: + return "_m_paddusb"; + case INTRINSIC_XED_IFORM_PADDUSW_MMXq_MMXq: + return "_m_paddusw"; + case INTRINSIC_XED_IFORM_PSUBB_MMXq_MMXq: + return "_m_psubb"; + case INTRINSIC_XED_IFORM_PSUBW_MMXq_MMXq: + return "_m_psubw"; + case INTRINSIC_XED_IFORM_PSUBD_MMXq_MMXq: + return "_m_psubd"; + case INTRINSIC_XED_IFORM_PSUBSB_MMXq_MMXq: + return "_m_psubsb"; + case INTRINSIC_XED_IFORM_PSUBSW_MMXq_MMXq: + return "_m_psubsw"; + case INTRINSIC_XED_IFORM_PSUBUSB_MMXq_MMXq: + return "_m_psubusb"; + case INTRINSIC_XED_IFORM_PSUBUSW_MMXq_MMXq: + return "_m_psubusw"; + case INTRINSIC_XED_IFORM_PMADDWD_MMXq_MMXq: + return "_m_pmaddwd"; + case INTRINSIC_XED_IFORM_PMULHW_MMXq_MMXq: + return "_m_pmulhw"; + case INTRINSIC_XED_IFORM_PMULLW_MMXq_MMXq: + return "_m_pmullw"; + case INTRINSIC_XED_IFORM_PSLLW_MMXq_MMXq: + return "_m_psllw"; + case INTRINSIC_XED_IFORM_PSLLW_MMXq_IMMb: + return "_m_psllwi"; + case INTRINSIC_XED_IFORM_PSLLD_MMXq_MMXq: + return "_m_pslld"; + case INTRINSIC_XED_IFORM_PSLLD_MMXq_IMMb: + return "_m_pslldi"; + case INTRINSIC_XED_IFORM_PSLLQ_MMXq_MMXq: + return "_m_psllq"; + case INTRINSIC_XED_IFORM_PSLLQ_MMXq_IMMb: + return "_m_psllqi"; + case INTRINSIC_XED_IFORM_PSRAW_MMXq_MMXq: + return "_m_psraw"; + case INTRINSIC_XED_IFORM_PSRAW_MMXq_IMMb: + return "_m_psrawi"; + case INTRINSIC_XED_IFORM_PSRAD_MMXq_MMXq: + return "_m_psrad"; + case INTRINSIC_XED_IFORM_PSRAD_MMXq_IMMb: + return "_m_psradi"; + case INTRINSIC_XED_IFORM_PSRLW_MMXq_MMXq: + return "_m_psrlw"; + case INTRINSIC_XED_IFORM_PSRLW_MMXq_IMMb: + return "_m_psrlwi"; + case INTRINSIC_XED_IFORM_PSRLD_MMXq_MMXq: + return "_m_psrld"; + case INTRINSIC_XED_IFORM_PSRLD_MMXq_IMMb: + return "_m_psrldi"; + case INTRINSIC_XED_IFORM_PSRLQ_MMXq_MMXq: + return "_m_psrlq"; + case INTRINSIC_XED_IFORM_PSRLQ_MMXq_IMMb: + return "_m_psrlqi"; + case INTRINSIC_XED_IFORM_PAND_MMXq_MMXq: + return "_m_pand"; + case INTRINSIC_XED_IFORM_PANDN_MMXq_MMXq: + return "_m_pandn"; + case INTRINSIC_XED_IFORM_POR_MMXq_MMXq: + return "_m_por"; + case INTRINSIC_XED_IFORM_PXOR_MMXq_MMXq: + return "_m_pxor"; + case INTRINSIC_XED_IFORM_PCMPEQB_MMXq_MMXq: + return "_m_pcmpeqb"; + case INTRINSIC_XED_IFORM_PCMPEQW_MMXq_MMXq: + return "_m_pcmpeqw"; + case INTRINSIC_XED_IFORM_PCMPEQD_MMXq_MMXq: + return "_m_pcmpeqd"; + case INTRINSIC_XED_IFORM_PCMPGTB_MMXq_MMXq: + return "_m_pcmpgtb"; + case INTRINSIC_XED_IFORM_PCMPGTW_MMXq_MMXq: + return "_m_pcmpgtw"; + case INTRINSIC_XED_IFORM_PCMPGTD_MMXq_MMXq: + return "_m_pcmpgtd"; + case INTRINSIC_XED_IFORM_MONITOR: + return "_mm_monitor"; + case INTRINSIC_XED_IFORM_MWAIT: + return "_mm_mwait"; + case INTRINSIC_XED_IFORM_MOVBE_GPRv_MEMv: + return "_loadbe_i16"; + case INTRINSIC_XED_IFORM_MOVBE_MEMv_GPRv: + return "_storebe_i16"; + case INTRINSIC_XED_IFORM_MOVDIR64B_GPRa_MEM: + return "_movdir64b"; + case INTRINSIC_XED_IFORM_MOVDIRI_MEMu64_GPR64u64: + return "_directstoreu_u64"; + case INTRINSIC_XED_IFORM_MOVDIRI_MEMu32_GPR32u32: + return "_directstoreu_u32"; + case INTRINSIC_XED_IFORM_BNDMK_BND_AGEN: + return "_bnd_set_ptr_bounds"; + case INTRINSIC_XED_IFORM_BNDSTX_MEMbnd64_BND: + return "_bnd_store_ptr_bounds"; + case INTRINSIC_XED_IFORM_BNDCL_BND_AGEN: + return "_bnd_chk_ptr_lbounds"; + case INTRINSIC_XED_IFORM_BNDCU_BND_AGEN: + return "_bnd_chk_ptr_ubounds"; + case INTRINSIC_XED_IFORM_BNDCN_BND_AGEN: + return "_bnd_chk_ptr_ubounds"; + case INTRINSIC_XED_IFORM_BSF_GPRv_GPRv: + return "_bit_scan_forward"; + case INTRINSIC_XED_IFORM_BSR_GPRv_GPRv: + return "_bit_scan_reverse"; + case INTRINSIC_XED_IFORM_BT_MEMv_GPRv: + return "_bittest"; + case INTRINSIC_XED_IFORM_BTC_MEMv_GPRv: + return "_bittestandcomplement"; + case INTRINSIC_XED_IFORM_BTR_MEMv_GPRv: + return "_bittestandreset"; + case INTRINSIC_XED_IFORM_BTS_MEMv_GPRv: + return "_bittestandset"; + case INTRINSIC_XED_IFORM_BT_GPRv_GPRv: + return "_bittest64"; + case INTRINSIC_XED_IFORM_BTC_GPRv_GPRv: + return "_bittestandcomplement64"; + case INTRINSIC_XED_IFORM_BTR_GPRv_GPRv: + return "_bittestandreset64"; + case INTRINSIC_XED_IFORM_BTS_GPRv_GPRv: + return "_bittestandset64"; + case INTRINSIC_XED_IFORM_BSWAP_GPRv: + return "_bswap"; + case INTRINSIC_XED_IFORM_ROL_GPRv_IMMb: + return "_lrotl"; + case INTRINSIC_XED_IFORM_ROR_GPRv_IMMb: + return "_lrotr"; + case INTRINSIC_XED_IFORM_RDPMC: + return "_rdpmc"; + case INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_11: + return "_addcarry_u32"; + case INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_19: + return "_subborrow_u32"; + case INTRINSIC_XED_IFORM_PTWRITE_GPRy: + return "_ptwrite32"; + case INTRINSIC_XED_IFORM_ENCLU: + return "_enclu_u32"; + case INTRINSIC_XED_IFORM_ENCLS: + return "_encls_u32"; + case INTRINSIC_XED_IFORM_ENCLV: + return "_enclv_u32"; + case INTRINSIC_XED_IFORM_WBINVD: + return "_wbinvd"; + case INTRINSIC_XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb: + return "_mm_clmulepi64_si128"; + case INTRINSIC_XED_IFORM_PCONFIG: + return "_pconfig_u32"; + case INTRINSIC_XED_IFORM_PREFETCHWT1_MEMu8: + return "_mm_prefetch"; + case INTRINSIC_XED_IFORM_RDPID_GPR32u32: + return "_rdpid_u32"; + case INTRINSIC_XED_IFORM_RDRAND_GPRv: + return "_rdrand16_step"; + case INTRINSIC_XED_IFORM_RDSEED_GPRv: + return "_rdseed16_step"; + case INTRINSIC_XED_IFORM_RDTSCP: + return "__rdtscp"; + case INTRINSIC_XED_IFORM_XABORT_IMMb: + return "_xabort"; + case INTRINSIC_XED_IFORM_XBEGIN_RELBRz: + return "_xbegin"; + case INTRINSIC_XED_IFORM_XEND: + return "_xend"; + case INTRINSIC_XED_IFORM_XTEST: + return "_xtest"; + case INTRINSIC_XED_IFORM_SERIALIZE: + return "_serialize"; + case INTRINSIC_XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA: + return "_mm_sha1msg1_epu32"; + case INTRINSIC_XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA: + return "_mm_sha1msg2_epu32"; + case INTRINSIC_XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA: + return "_mm_sha1nexte_epu32"; + case INTRINSIC_XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA: + return "_mm_sha1rnds4_epu32"; + case INTRINSIC_XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA: + return "_mm_sha256msg1_epu32"; + case INTRINSIC_XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA: + return "_mm_sha256msg2_epu32"; + case INTRINSIC_XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA: + return "_mm_sha256rnds2_epu32"; + case INTRINSIC_XED_IFORM_STMXCSR_MEMd: + return "_mm_getcsr"; + case INTRINSIC_XED_IFORM_LDMXCSR_MEMd: + return "_mm_setcsr"; + case INTRINSIC_XED_IFORM_PREFETCHNTA_MEMmprefetch: + return "_mm_prefetch"; + case INTRINSIC_XED_IFORM_PREFETCHT0_MEMmprefetch: + return "_mm_prefetch"; + case INTRINSIC_XED_IFORM_PREFETCHT1_MEMmprefetch: + return "_mm_prefetch"; + case INTRINSIC_XED_IFORM_PREFETCHT2_MEMmprefetch: + return "_mm_prefetch"; + case INTRINSIC_XED_IFORM_SFENCE: + return "_mm_sfence"; + case INTRINSIC_XED_IFORM_PMAXSW_MMXq_MMXq: + return "_mm_max_pi16"; + case INTRINSIC_XED_IFORM_PMAXUB_MMXq_MMXq: + return "_mm_max_pu8"; + case INTRINSIC_XED_IFORM_PMINSW_MMXq_MMXq: + return "_mm_min_pi16"; + case INTRINSIC_XED_IFORM_PMINUB_MMXq_MMXq: + return "_mm_min_pu8"; + case INTRINSIC_XED_IFORM_PMULHUW_MMXq_MMXq: + return "_mm_mulhi_pu16"; + case INTRINSIC_XED_IFORM_PAVGB_MMXq_MMXq: + return "_mm_avg_pu8"; + case INTRINSIC_XED_IFORM_PAVGW_MMXq_MMXq: + return "_mm_avg_pu16"; + case INTRINSIC_XED_IFORM_PSADBW_MMXq_MMXq: + return "_mm_sad_pu8"; + case INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_GPR32d: + return "_mm_cvtsi32_ss"; + case INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_GPR64q: + return "_mm_cvtsi64_ss"; + case INTRINSIC_XED_IFORM_CVTPI2PS_XMMq_MMXq: + return "_mm_cvtpi32_ps"; + case INTRINSIC_XED_IFORM_MOVNTQ_MEMq_MMXq: + return "_mm_stream_pi"; + case INTRINSIC_XED_IFORM_MASKMOVQ_MMXq_MMXq: + return "_mm_maskmove_si64"; + case INTRINSIC_XED_IFORM_PEXTRW_GPR32_MMXq_IMMb: + return "_mm_extract_pi16"; + case INTRINSIC_XED_IFORM_PINSRW_MMXq_GPR32_IMMb: + return "_mm_insert_pi16"; + case INTRINSIC_XED_IFORM_PMOVMSKB_GPR32_MMXq: + return "_mm_movemask_pi8"; + case INTRINSIC_XED_IFORM_PSHUFW_MMXq_MMXq_IMMb: + return "_mm_shuffle_pi16"; + case INTRINSIC_XED_IFORM_ADDSS_XMMss_XMMss: + return "_mm_add_ss"; + case INTRINSIC_XED_IFORM_ADDPS_XMMps_XMMps: + return "_mm_add_ps"; + case INTRINSIC_XED_IFORM_SUBSS_XMMss_XMMss: + return "_mm_sub_ss"; + case INTRINSIC_XED_IFORM_SUBPS_XMMps_XMMps: + return "_mm_sub_ps"; + case INTRINSIC_XED_IFORM_MULSS_XMMss_XMMss: + return "_mm_mul_ss"; + case INTRINSIC_XED_IFORM_MULPS_XMMps_XMMps: + return "_mm_mul_ps"; + case INTRINSIC_XED_IFORM_DIVSS_XMMss_XMMss: + return "_mm_div_ss"; + case INTRINSIC_XED_IFORM_DIVPS_XMMps_XMMps: + return "_mm_div_ps"; + case INTRINSIC_XED_IFORM_SQRTSS_XMMss_XMMss: + return "_mm_sqrt_ss"; + case INTRINSIC_XED_IFORM_SQRTPS_XMMps_XMMps: + return "_mm_sqrt_ps"; + case INTRINSIC_XED_IFORM_RCPSS_XMMss_XMMss: + return "_mm_rcp_ss"; + case INTRINSIC_XED_IFORM_RCPPS_XMMps_XMMps: + return "_mm_rcp_ps"; + case INTRINSIC_XED_IFORM_RSQRTSS_XMMss_XMMss: + return "_mm_rsqrt_ss"; + case INTRINSIC_XED_IFORM_RSQRTPS_XMMps_XMMps: + return "_mm_rsqrt_ps"; + case INTRINSIC_XED_IFORM_MINSS_XMMss_XMMss: + return "_mm_min_ss"; + case INTRINSIC_XED_IFORM_MINPS_XMMps_XMMps: + return "_mm_min_ps"; + case INTRINSIC_XED_IFORM_MAXSS_XMMss_XMMss: + return "_mm_max_ss"; + case INTRINSIC_XED_IFORM_MAXPS_XMMps_XMMps: + return "_mm_max_ps"; + case INTRINSIC_XED_IFORM_ANDPS_XMMxud_XMMxud: + return "_mm_and_ps"; + case INTRINSIC_XED_IFORM_ANDNPS_XMMxud_XMMxud: + return "_mm_andnot_ps"; + case INTRINSIC_XED_IFORM_ORPS_XMMxud_XMMxud: + return "_mm_or_ps"; + case INTRINSIC_XED_IFORM_XORPS_XMMxud_XMMxud: + return "_mm_xor_ps"; + case INTRINSIC_XED_IFORM_CMPSS_XMMss_XMMss_IMMb: + return "_mm_cmpeq_ss"; + case INTRINSIC_XED_IFORM_CMPPS_XMMps_XMMps_IMMb: + return "_mm_cmpeq_ps"; + case INTRINSIC_XED_IFORM_COMISS_XMMss_XMMss: + return "_mm_comieq_ss"; + case INTRINSIC_XED_IFORM_UCOMISS_XMMss_XMMss: + return "_mm_ucomieq_ss"; + case INTRINSIC_XED_IFORM_CVTSS2SI_GPR32d_XMMss: + return "_mm_cvtss_si32"; + case INTRINSIC_XED_IFORM_CVTSS2SI_GPR64q_XMMss: + return "_mm_cvtss_si64"; + case INTRINSIC_XED_IFORM_MOVSS_MEMss_XMMss: + return "_mm_cvtss_f32"; + case INTRINSIC_XED_IFORM_CVTPS2PI_MMXq_XMMq: + return "_mm_cvtps_pi32"; + case INTRINSIC_XED_IFORM_CVTTSS2SI_GPR32d_XMMss: + return "_mm_cvttss_si32"; + case INTRINSIC_XED_IFORM_CVTTSS2SI_GPR64q_XMMss: + return "_mm_cvttss_si64"; + case INTRINSIC_XED_IFORM_CVTTPS2PI_MMXq_XMMq: + return "_mm_cvttps_pi32"; + case INTRINSIC_XED_IFORM_MOVHPS_XMMq_MEMq: + return "_mm_loadh_pi"; + case INTRINSIC_XED_IFORM_MOVLPS_XMMq_MEMq: + return "_mm_loadl_pi"; + case INTRINSIC_XED_IFORM_MOVSS_XMMdq_MEMss: + return "_mm_load_ss"; + case INTRINSIC_XED_IFORM_MOVAPS_XMMps_MEMps: + return "_mm_load_ps"; + case INTRINSIC_XED_IFORM_MOVUPS_XMMps_MEMps: + return "_mm_loadu_ps"; + case INTRINSIC_XED_IFORM_MOVNTPS_MEMdq_XMMps: + return "_mm_stream_ps"; + case INTRINSIC_XED_IFORM_MOVHPS_MEMq_XMMps: + return "_mm_storeh_pi"; + case INTRINSIC_XED_IFORM_MOVLPS_MEMq_XMMps: + return "_mm_storel_pi"; + case INTRINSIC_XED_IFORM_MOVAPS_MEMps_XMMps: + return "_mm_store_ps"; + case INTRINSIC_XED_IFORM_MOVUPS_MEMps_XMMps: + return "_mm_storeu_ps"; + case INTRINSIC_XED_IFORM_MOVSS_XMMss_XMMss_0F10: + return "_mm_move_ss"; + case INTRINSIC_XED_IFORM_SHUFPS_XMMps_XMMps_IMMb: + return "_mm_shuffle_ps"; + case INTRINSIC_XED_IFORM_UNPCKHPS_XMMps_XMMdq: + return "_mm_unpackhi_ps"; + case INTRINSIC_XED_IFORM_UNPCKLPS_XMMps_XMMq: + return "_mm_unpacklo_ps"; + case INTRINSIC_XED_IFORM_MOVHLPS_XMMq_XMMq: + return "_mm_movehl_ps"; + case INTRINSIC_XED_IFORM_MOVLHPS_XMMq_XMMq: + return "_mm_movelh_ps"; + case INTRINSIC_XED_IFORM_MOVMSKPS_GPR32_XMMps: + return "_mm_movemask_ps"; + case INTRINSIC_XED_IFORM_MOVQ_XMMdq_MEMq_0F6E: + return "_mm_loadu_si64"; + case INTRINSIC_XED_IFORM_MOVQ_MEMq_XMMq_0F7E: + return "_mm_storeu_si64"; + case INTRINSIC_XED_IFORM_MOVD_XMMdq_MEMd: + return "_mm_loadu_si32"; + case INTRINSIC_XED_IFORM_MOVD_MEMd_XMMd: + return "_mm_storeu_si32"; + case INTRINSIC_XED_IFORM_PAUSE: + return "_mm_pause"; + case INTRINSIC_XED_IFORM_CLFLUSH_MEMmprefetch: + return "_mm_clflush"; + case INTRINSIC_XED_IFORM_LFENCE: + return "_mm_lfence"; + case INTRINSIC_XED_IFORM_MFENCE: + return "_mm_mfence"; + case INTRINSIC_XED_IFORM_PADDB_XMMdq_XMMdq: + return "_mm_add_epi8"; + case INTRINSIC_XED_IFORM_PADDW_XMMdq_XMMdq: + return "_mm_add_epi16"; + case INTRINSIC_XED_IFORM_PADDD_XMMdq_XMMdq: + return "_mm_add_epi32"; + case INTRINSIC_XED_IFORM_PADDQ_MMXq_MMXq: + return "_mm_add_si64"; + case INTRINSIC_XED_IFORM_PADDQ_XMMdq_XMMdq: + return "_mm_add_epi64"; + case INTRINSIC_XED_IFORM_PADDSB_XMMdq_XMMdq: + return "_mm_adds_epi8"; + case INTRINSIC_XED_IFORM_PADDSW_XMMdq_XMMdq: + return "_mm_adds_epi16"; + case INTRINSIC_XED_IFORM_PADDUSB_XMMdq_XMMdq: + return "_mm_adds_epu8"; + case INTRINSIC_XED_IFORM_PADDUSW_XMMdq_XMMdq: + return "_mm_adds_epu16"; + case INTRINSIC_XED_IFORM_PAVGB_XMMdq_XMMdq: + return "_mm_avg_epu8"; + case INTRINSIC_XED_IFORM_PAVGW_XMMdq_XMMdq: + return "_mm_avg_epu16"; + case INTRINSIC_XED_IFORM_PMADDWD_XMMdq_XMMdq: + return "_mm_madd_epi16"; + case INTRINSIC_XED_IFORM_PMAXSW_XMMdq_XMMdq: + return "_mm_max_epi16"; + case INTRINSIC_XED_IFORM_PMAXUB_XMMdq_XMMdq: + return "_mm_max_epu8"; + case INTRINSIC_XED_IFORM_PMINSW_XMMdq_XMMdq: + return "_mm_min_epi16"; + case INTRINSIC_XED_IFORM_PMINUB_XMMdq_XMMdq: + return "_mm_min_epu8"; + case INTRINSIC_XED_IFORM_PMULHW_XMMdq_XMMdq: + return "_mm_mulhi_epi16"; + case INTRINSIC_XED_IFORM_PMULHUW_XMMdq_XMMdq: + return "_mm_mulhi_epu16"; + case INTRINSIC_XED_IFORM_PMULLW_XMMdq_XMMdq: + return "_mm_mullo_epi16"; + case INTRINSIC_XED_IFORM_PMULUDQ_MMXq_MMXq: + return "_mm_mul_su32"; + case INTRINSIC_XED_IFORM_PMULUDQ_XMMdq_XMMdq: + return "_mm_mul_epu32"; + case INTRINSIC_XED_IFORM_PSADBW_XMMdq_XMMdq: + return "_mm_sad_epu8"; + case INTRINSIC_XED_IFORM_PSUBB_XMMdq_XMMdq: + return "_mm_sub_epi8"; + case INTRINSIC_XED_IFORM_PSUBW_XMMdq_XMMdq: + return "_mm_sub_epi16"; + case INTRINSIC_XED_IFORM_PSUBD_XMMdq_XMMdq: + return "_mm_sub_epi32"; + case INTRINSIC_XED_IFORM_PSUBQ_MMXq_MMXq: + return "_mm_sub_si64"; + case INTRINSIC_XED_IFORM_PSUBQ_XMMdq_XMMdq: + return "_mm_sub_epi64"; + case INTRINSIC_XED_IFORM_PSUBSB_XMMdq_XMMdq: + return "_mm_subs_epi8"; + case INTRINSIC_XED_IFORM_PSUBSW_XMMdq_XMMdq: + return "_mm_subs_epi16"; + case INTRINSIC_XED_IFORM_PSUBUSB_XMMdq_XMMdq: + return "_mm_subs_epu8"; + case INTRINSIC_XED_IFORM_PSUBUSW_XMMdq_XMMdq: + return "_mm_subs_epu16"; + case INTRINSIC_XED_IFORM_PSLLDQ_XMMdq_IMMb: + return "_mm_slli_si128"; + case INTRINSIC_XED_IFORM_PSRLDQ_XMMdq_IMMb: + return "_mm_bsrli_si128"; + case INTRINSIC_XED_IFORM_PSLLW_XMMdq_IMMb: + return "_mm_slli_epi16"; + case INTRINSIC_XED_IFORM_PSLLW_XMMdq_XMMdq: + return "_mm_sll_epi16"; + case INTRINSIC_XED_IFORM_PSLLD_XMMdq_IMMb: + return "_mm_slli_epi32"; + case INTRINSIC_XED_IFORM_PSLLD_XMMdq_XMMdq: + return "_mm_sll_epi32"; + case INTRINSIC_XED_IFORM_PSLLQ_XMMdq_IMMb: + return "_mm_slli_epi64"; + case INTRINSIC_XED_IFORM_PSLLQ_XMMdq_XMMdq: + return "_mm_sll_epi64"; + case INTRINSIC_XED_IFORM_PSRAW_XMMdq_IMMb: + return "_mm_srai_epi16"; + case INTRINSIC_XED_IFORM_PSRAW_XMMdq_XMMdq: + return "_mm_sra_epi16"; + case INTRINSIC_XED_IFORM_PSRAD_XMMdq_IMMb: + return "_mm_srai_epi32"; + case INTRINSIC_XED_IFORM_PSRAD_XMMdq_XMMdq: + return "_mm_sra_epi32"; + case INTRINSIC_XED_IFORM_PSRLW_XMMdq_IMMb: + return "_mm_srli_epi16"; + case INTRINSIC_XED_IFORM_PSRLW_XMMdq_XMMdq: + return "_mm_srl_epi16"; + case INTRINSIC_XED_IFORM_PSRLD_XMMdq_IMMb: + return "_mm_srli_epi32"; + case INTRINSIC_XED_IFORM_PSRLD_XMMdq_XMMdq: + return "_mm_srl_epi32"; + case INTRINSIC_XED_IFORM_PSRLQ_XMMdq_IMMb: + return "_mm_srli_epi64"; + case INTRINSIC_XED_IFORM_PSRLQ_XMMdq_XMMdq: + return "_mm_srl_epi64"; + case INTRINSIC_XED_IFORM_PAND_XMMdq_XMMdq: + return "_mm_and_si128"; + case INTRINSIC_XED_IFORM_PANDN_XMMdq_XMMdq: + return "_mm_andnot_si128"; + case INTRINSIC_XED_IFORM_POR_XMMdq_XMMdq: + return "_mm_or_si128"; + case INTRINSIC_XED_IFORM_PXOR_XMMdq_XMMdq: + return "_mm_xor_si128"; + case INTRINSIC_XED_IFORM_PCMPEQB_XMMdq_XMMdq: + return "_mm_cmpeq_epi8"; + case INTRINSIC_XED_IFORM_PCMPEQW_XMMdq_XMMdq: + return "_mm_cmpeq_epi16"; + case INTRINSIC_XED_IFORM_PCMPEQD_XMMdq_XMMdq: + return "_mm_cmpeq_epi32"; + case INTRINSIC_XED_IFORM_PCMPGTB_XMMdq_XMMdq: + return "_mm_cmpgt_epi8"; + case INTRINSIC_XED_IFORM_PCMPGTW_XMMdq_XMMdq: + return "_mm_cmpgt_epi16"; + case INTRINSIC_XED_IFORM_PCMPGTD_XMMdq_XMMdq: + return "_mm_cmpgt_epi32"; + case INTRINSIC_XED_IFORM_CVTDQ2PD_XMMpd_XMMq: + return "_mm_cvtepi32_pd"; + case INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_GPR32d: + return "_mm_cvtsi32_sd"; + case INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_GPR64q: + return "_mm_cvtsi64_sd"; + case INTRINSIC_XED_IFORM_CVTDQ2PS_XMMps_XMMdq: + return "_mm_cvtepi32_ps"; + case INTRINSIC_XED_IFORM_CVTPI2PD_XMMpd_MMXq: + return "_mm_cvtpi32_pd"; + case INTRINSIC_XED_IFORM_MOVD_XMMdq_GPR32: + return "_mm_cvtsi32_si128"; + case INTRINSIC_XED_IFORM_MOVQ_XMMdq_GPR64: + return "_mm_cvtsi64_si128"; + case INTRINSIC_XED_IFORM_MOVD_GPR32_XMMd: + return "_mm_cvtsi128_si32"; + case INTRINSIC_XED_IFORM_MOVQ_GPR64_XMMq: + return "_mm_cvtsi128_si64"; + case INTRINSIC_XED_IFORM_MOVQ_XMMdq_MEMq_0F7E: + return "_mm_loadl_epi64"; + case INTRINSIC_XED_IFORM_MOVDQA_XMMdq_MEMdq: + return "_mm_load_si128"; + case INTRINSIC_XED_IFORM_MOVDQU_XMMdq_MEMdq: + return "_mm_loadu_si128"; + case INTRINSIC_XED_IFORM_MASKMOVDQU_XMMdq_XMMdq: + return "_mm_maskmoveu_si128"; + case INTRINSIC_XED_IFORM_MOVDQA_MEMdq_XMMdq: + return "_mm_store_si128"; + case INTRINSIC_XED_IFORM_MOVDQU_MEMdq_XMMdq: + return "_mm_storeu_si128"; + case INTRINSIC_XED_IFORM_MOVNTDQ_MEMdq_XMMdq: + return "_mm_stream_si128"; + case INTRINSIC_XED_IFORM_MOVNTI_MEMd_GPR32: + return "_mm_stream_si32"; + case INTRINSIC_XED_IFORM_MOVNTI_MEMq_GPR64: + return "_mm_stream_si64"; + case INTRINSIC_XED_IFORM_MOVDQ2Q_MMXq_XMMq: + return "_mm_movepi64_pi64"; + case INTRINSIC_XED_IFORM_MOVQ2DQ_XMMdq_MMXq: + return "_mm_movpi64_epi64"; + case INTRINSIC_XED_IFORM_MOVQ_XMMdq_XMMq_0F7E: + return "_mm_move_epi64"; + case INTRINSIC_XED_IFORM_PACKSSWB_XMMdq_XMMdq: + return "_mm_packs_epi16"; + case INTRINSIC_XED_IFORM_PACKSSDW_XMMdq_XMMdq: + return "_mm_packs_epi32"; + case INTRINSIC_XED_IFORM_PACKUSWB_XMMdq_XMMdq: + return "_mm_packus_epi16"; + case INTRINSIC_XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb: + return "_mm_extract_epi16"; + case INTRINSIC_XED_IFORM_PINSRW_XMMdq_GPR32_IMMb: + return "_mm_insert_epi16"; + case INTRINSIC_XED_IFORM_PMOVMSKB_GPR32_XMMdq: + return "_mm_movemask_epi8"; + case INTRINSIC_XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb: + return "_mm_shuffle_epi32"; + case INTRINSIC_XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb: + return "_mm_shufflehi_epi16"; + case INTRINSIC_XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb: + return "_mm_shufflelo_epi16"; + case INTRINSIC_XED_IFORM_PUNPCKHBW_XMMdq_XMMq: + return "_mm_unpackhi_epi8"; + case INTRINSIC_XED_IFORM_PUNPCKHWD_XMMdq_XMMq: + return "_mm_unpackhi_epi16"; + case INTRINSIC_XED_IFORM_PUNPCKHDQ_XMMdq_XMMq: + return "_mm_unpackhi_epi32"; + case INTRINSIC_XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq: + return "_mm_unpackhi_epi64"; + case INTRINSIC_XED_IFORM_PUNPCKLBW_XMMdq_XMMq: + return "_mm_unpacklo_epi8"; + case INTRINSIC_XED_IFORM_PUNPCKLWD_XMMdq_XMMq: + return "_mm_unpacklo_epi16"; + case INTRINSIC_XED_IFORM_PUNPCKLDQ_XMMdq_XMMq: + return "_mm_unpacklo_epi32"; + case INTRINSIC_XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq: + return "_mm_unpacklo_epi64"; + case INTRINSIC_XED_IFORM_ADDSD_XMMsd_XMMsd: + return "_mm_add_sd"; + case INTRINSIC_XED_IFORM_ADDPD_XMMpd_XMMpd: + return "_mm_add_pd"; + case INTRINSIC_XED_IFORM_DIVSD_XMMsd_XMMsd: + return "_mm_div_sd"; + case INTRINSIC_XED_IFORM_DIVPD_XMMpd_XMMpd: + return "_mm_div_pd"; + case INTRINSIC_XED_IFORM_MAXSD_XMMsd_XMMsd: + return "_mm_max_sd"; + case INTRINSIC_XED_IFORM_MAXPD_XMMpd_XMMpd: + return "_mm_max_pd"; + case INTRINSIC_XED_IFORM_MINSD_XMMsd_XMMsd: + return "_mm_min_sd"; + case INTRINSIC_XED_IFORM_MINPD_XMMpd_XMMpd: + return "_mm_min_pd"; + case INTRINSIC_XED_IFORM_MULSD_XMMsd_XMMsd: + return "_mm_mul_sd"; + case INTRINSIC_XED_IFORM_MULPD_XMMpd_XMMpd: + return "_mm_mul_pd"; + case INTRINSIC_XED_IFORM_SQRTSD_XMMsd_XMMsd: + return "_mm_sqrt_sd"; + case INTRINSIC_XED_IFORM_SQRTPD_XMMpd_XMMpd: + return "_mm_sqrt_pd"; + case INTRINSIC_XED_IFORM_SUBSD_XMMsd_XMMsd: + return "_mm_sub_sd"; + case INTRINSIC_XED_IFORM_SUBPD_XMMpd_XMMpd: + return "_mm_sub_pd"; + case INTRINSIC_XED_IFORM_ANDPD_XMMxuq_XMMxuq: + return "_mm_and_pd"; + case INTRINSIC_XED_IFORM_ANDNPD_XMMxuq_XMMxuq: + return "_mm_andnot_pd"; + case INTRINSIC_XED_IFORM_ORPD_XMMxuq_XMMxuq: + return "_mm_or_pd"; + case INTRINSIC_XED_IFORM_XORPD_XMMxuq_XMMxuq: + return "_mm_xor_pd"; + case INTRINSIC_XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb: + return "_mm_cmpeq_sd"; + case INTRINSIC_XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb: + return "_mm_cmpeq_pd"; + case INTRINSIC_XED_IFORM_COMISD_XMMsd_XMMsd: + return "_mm_comieq_sd"; + case INTRINSIC_XED_IFORM_UCOMISD_XMMsd_XMMsd: + return "_mm_ucomieq_sd"; + case INTRINSIC_XED_IFORM_CVTPD2PS_XMMps_XMMpd: + return "_mm_cvtpd_ps"; + case INTRINSIC_XED_IFORM_CVTPS2PD_XMMpd_XMMq: + return "_mm_cvtps_pd"; + case INTRINSIC_XED_IFORM_CVTPD2DQ_XMMdq_XMMpd: + return "_mm_cvtpd_epi32"; + case INTRINSIC_XED_IFORM_CVTSD2SI_GPR32d_XMMsd: + return "_mm_cvtsd_si32"; + case INTRINSIC_XED_IFORM_CVTSD2SI_GPR64q_XMMsd: + return "_mm_cvtsd_si64"; + case INTRINSIC_XED_IFORM_CVTSD2SS_XMMss_XMMsd: + return "_mm_cvtsd_ss"; + case INTRINSIC_XED_IFORM_MOVSD_XMM_MEMsd_XMMsd: + return "_mm_cvtsd_f64"; + case INTRINSIC_XED_IFORM_CVTSS2SD_XMMsd_XMMss: + return "_mm_cvtss_sd"; + case INTRINSIC_XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd: + return "_mm_cvttpd_epi32"; + case INTRINSIC_XED_IFORM_CVTTSD2SI_GPR32d_XMMsd: + return "_mm_cvttsd_si32"; + case INTRINSIC_XED_IFORM_CVTTSD2SI_GPR64q_XMMsd: + return "_mm_cvttsd_si64"; + case INTRINSIC_XED_IFORM_CVTPS2DQ_XMMdq_XMMps: + return "_mm_cvtps_epi32"; + case INTRINSIC_XED_IFORM_CVTTPS2DQ_XMMdq_XMMps: + return "_mm_cvttps_epi32"; + case INTRINSIC_XED_IFORM_CVTPD2PI_MMXq_XMMpd: + return "_mm_cvtpd_pi32"; + case INTRINSIC_XED_IFORM_CVTTPD2PI_MMXq_XMMpd: + return "_mm_cvttpd_pi32"; + case INTRINSIC_XED_IFORM_MOVAPD_XMMpd_MEMpd: + return "_mm_load_pd"; + case INTRINSIC_XED_IFORM_MOVUPD_XMMpd_MEMpd: + return "_mm_loadu_pd"; + case INTRINSIC_XED_IFORM_MOVSD_XMM_XMMdq_MEMsd: + return "_mm_load_sd"; + case INTRINSIC_XED_IFORM_MOVHPD_XMMsd_MEMq: + return "_mm_loadh_pd"; + case INTRINSIC_XED_IFORM_MOVLPD_XMMsd_MEMq: + return "_mm_loadl_pd"; + case INTRINSIC_XED_IFORM_MOVNTPD_MEMdq_XMMpd: + return "_mm_stream_pd"; + case INTRINSIC_XED_IFORM_MOVAPD_MEMpd_XMMpd: + return "_mm_store_pd"; + case INTRINSIC_XED_IFORM_MOVUPD_MEMpd_XMMpd: + return "_mm_storeu_pd"; + case INTRINSIC_XED_IFORM_MOVHPD_MEMq_XMMsd: + return "_mm_storeh_pd"; + case INTRINSIC_XED_IFORM_MOVLPD_MEMq_XMMsd: + return "_mm_storel_pd"; + case INTRINSIC_XED_IFORM_UNPCKHPD_XMMpd_XMMq: + return "_mm_unpackhi_pd"; + case INTRINSIC_XED_IFORM_UNPCKLPD_XMMpd_XMMq: + return "_mm_unpacklo_pd"; + case INTRINSIC_XED_IFORM_MOVMSKPD_GPR32_XMMpd: + return "_mm_movemask_pd"; + case INTRINSIC_XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb: + return "_mm_shuffle_pd"; + case INTRINSIC_XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10: + return "_mm_move_sd"; + case INTRINSIC_XED_IFORM_ADDSUBPS_XMMps_XMMps: + return "_mm_addsub_ps"; + case INTRINSIC_XED_IFORM_ADDSUBPD_XMMpd_XMMpd: + return "_mm_addsub_pd"; + case INTRINSIC_XED_IFORM_HADDPD_XMMpd_XMMpd: + return "_mm_hadd_pd"; + case INTRINSIC_XED_IFORM_HADDPS_XMMps_XMMps: + return "_mm_hadd_ps"; + case INTRINSIC_XED_IFORM_HSUBPD_XMMpd_XMMpd: + return "_mm_hsub_pd"; + case INTRINSIC_XED_IFORM_HSUBPS_XMMps_XMMps: + return "_mm_hsub_ps"; + case INTRINSIC_XED_IFORM_LDDQU_XMMpd_MEMdq: + return "_mm_lddqu_si128"; + case INTRINSIC_XED_IFORM_MOVDDUP_XMMdq_MEMq: + return "_mm_loaddup_pd"; + case INTRINSIC_XED_IFORM_MOVSHDUP_XMMps_XMMps: + return "_mm_movehdup_ps"; + case INTRINSIC_XED_IFORM_MOVSLDUP_XMMps_XMMps: + return "_mm_moveldup_ps"; + case INTRINSIC_XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb: + return "_mm_blend_pd"; + case INTRINSIC_XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb: + return "_mm_blend_ps"; + case INTRINSIC_XED_IFORM_BLENDVPD_XMMdq_XMMdq: + return "_mm_blendv_pd"; + case INTRINSIC_XED_IFORM_BLENDVPS_XMMdq_XMMdq: + return "_mm_blendv_ps"; + case INTRINSIC_XED_IFORM_PBLENDVB_XMMdq_XMMdq: + return "_mm_blendv_epi8"; + case INTRINSIC_XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb: + return "_mm_blend_epi16"; + case INTRINSIC_XED_IFORM_DPPD_XMMdq_XMMdq_IMMb: + return "_mm_dp_pd"; + case INTRINSIC_XED_IFORM_DPPS_XMMdq_XMMdq_IMMb: + return "_mm_dp_ps"; + case INTRINSIC_XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb: + return "_mm_extract_ps"; + case INTRINSIC_XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb: + return "_mm_extract_epi8"; + case INTRINSIC_XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb: + return "_mm_extract_epi32"; + case INTRINSIC_XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb: + return "_mm_extract_epi64"; + case INTRINSIC_XED_IFORM_INSERTPS_XMMps_XMMps_IMMb: + return "_mm_insert_ps"; + case INTRINSIC_XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb: + return "_mm_insert_epi8"; + case INTRINSIC_XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb: + return "_mm_insert_epi32"; + case INTRINSIC_XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb: + return "_mm_insert_epi64"; + case INTRINSIC_XED_IFORM_PMAXSB_XMMdq_XMMdq: + return "_mm_max_epi8"; + case INTRINSIC_XED_IFORM_PMAXSD_XMMdq_XMMdq: + return "_mm_max_epi32"; + case INTRINSIC_XED_IFORM_PMAXUD_XMMdq_XMMdq: + return "_mm_max_epu32"; + case INTRINSIC_XED_IFORM_PMAXUW_XMMdq_XMMdq: + return "_mm_max_epu16"; + case INTRINSIC_XED_IFORM_PMINSB_XMMdq_XMMdq: + return "_mm_min_epi8"; + case INTRINSIC_XED_IFORM_PMINSD_XMMdq_XMMdq: + return "_mm_min_epi32"; + case INTRINSIC_XED_IFORM_PMINUD_XMMdq_XMMdq: + return "_mm_min_epu32"; + case INTRINSIC_XED_IFORM_PMINUW_XMMdq_XMMdq: + return "_mm_min_epu16"; + case INTRINSIC_XED_IFORM_PACKUSDW_XMMdq_XMMdq: + return "_mm_packus_epi32"; + case INTRINSIC_XED_IFORM_PCMPEQQ_XMMdq_XMMdq: + return "_mm_cmpeq_epi64"; + case INTRINSIC_XED_IFORM_PMOVSXBW_XMMdq_XMMq: + return "_mm_cvtepi8_epi16"; + case INTRINSIC_XED_IFORM_PMOVSXBD_XMMdq_XMMd: + return "_mm_cvtepi8_epi32"; + case INTRINSIC_XED_IFORM_PMOVSXBQ_XMMdq_XMMw: + return "_mm_cvtepi8_epi64"; + case INTRINSIC_XED_IFORM_PMOVSXWD_XMMdq_XMMq: + return "_mm_cvtepi16_epi32"; + case INTRINSIC_XED_IFORM_PMOVSXWQ_XMMdq_XMMd: + return "_mm_cvtepi16_epi64"; + case INTRINSIC_XED_IFORM_PMOVSXDQ_XMMdq_XMMq: + return "_mm_cvtepi32_epi64"; + case INTRINSIC_XED_IFORM_PMOVZXBW_XMMdq_XMMq: + return "_mm_cvtepu8_epi16"; + case INTRINSIC_XED_IFORM_PMOVZXBD_XMMdq_XMMd: + return "_mm_cvtepu8_epi32"; + case INTRINSIC_XED_IFORM_PMOVZXBQ_XMMdq_XMMw: + return "_mm_cvtepu8_epi64"; + case INTRINSIC_XED_IFORM_PMOVZXWD_XMMdq_XMMq: + return "_mm_cvtepu16_epi32"; + case INTRINSIC_XED_IFORM_PMOVZXWQ_XMMdq_XMMd: + return "_mm_cvtepu16_epi64"; + case INTRINSIC_XED_IFORM_PMOVZXDQ_XMMdq_XMMq: + return "_mm_cvtepu32_epi64"; + case INTRINSIC_XED_IFORM_PMULDQ_XMMdq_XMMdq: + return "_mm_mul_epi32"; + case INTRINSIC_XED_IFORM_PMULLD_XMMdq_XMMdq: + return "_mm_mullo_epi32"; + case INTRINSIC_XED_IFORM_PTEST_XMMdq_XMMdq: + return "_mm_testz_si128"; + case INTRINSIC_XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb: + return "_mm_round_pd"; + case INTRINSIC_XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb: + return "_mm_round_ps"; + case INTRINSIC_XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb: + return "_mm_round_sd"; + case INTRINSIC_XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb: + return "_mm_round_ss"; + case INTRINSIC_XED_IFORM_PHMINPOSUW_XMMdq_XMMdq: + return "_mm_minpos_epu16"; + case INTRINSIC_XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb: + return "_mm_mpsadbw_epu8"; + case INTRINSIC_XED_IFORM_MOVNTDQA_XMMdq_MEMdq: + return "_mm_stream_load_si128"; + case INTRINSIC_XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb: + return "_mm_cmpistrm"; + case INTRINSIC_XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb: + return "_mm_cmpistri"; + case INTRINSIC_XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb: + return "_mm_cmpestrm"; + case INTRINSIC_XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb: + return "_mm_cmpestri"; + case INTRINSIC_XED_IFORM_PCMPGTQ_XMMdq_XMMdq: + return "_mm_cmpgt_epi64"; + case INTRINSIC_XED_IFORM_CRC32_GPRyy_GPR8b: + return "_mm_crc32_u8"; + case INTRINSIC_XED_IFORM_CRC32_GPRyy_GPRv: + return "_mm_crc32_u16"; + case INTRINSIC_XED_IFORM_PABSB_MMXq_MMXq: + return "_mm_abs_pi8"; + case INTRINSIC_XED_IFORM_PABSB_XMMdq_XMMdq: + return "_mm_abs_epi8"; + case INTRINSIC_XED_IFORM_PABSW_MMXq_MMXq: + return "_mm_abs_pi16"; + case INTRINSIC_XED_IFORM_PABSW_XMMdq_XMMdq: + return "_mm_abs_epi16"; + case INTRINSIC_XED_IFORM_PABSD_MMXq_MMXq: + return "_mm_abs_pi32"; + case INTRINSIC_XED_IFORM_PABSD_XMMdq_XMMdq: + return "_mm_abs_epi32"; + case INTRINSIC_XED_IFORM_PSHUFB_XMMdq_XMMdq: + return "_mm_shuffle_epi8"; + case INTRINSIC_XED_IFORM_PSHUFB_MMXq_MMXq: + return "_mm_shuffle_pi8"; + case INTRINSIC_XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb: + return "_mm_alignr_epi8"; + case INTRINSIC_XED_IFORM_PALIGNR_MMXq_MMXq_IMMb: + return "_mm_alignr_pi8"; + case INTRINSIC_XED_IFORM_PHADDW_XMMdq_XMMdq: + return "_mm_hadd_epi16"; + case INTRINSIC_XED_IFORM_PHADDSW_XMMdq_XMMdq: + return "_mm_hadds_epi16"; + case INTRINSIC_XED_IFORM_PHADDD_XMMdq_XMMdq: + return "_mm_hadd_epi32"; + case INTRINSIC_XED_IFORM_PHADDW_MMXq_MMXq: + return "_mm_hadd_pi16"; + case INTRINSIC_XED_IFORM_PHADDSW_MMXq_MMXq: + return "_mm_hadds_pi16"; + case INTRINSIC_XED_IFORM_PHSUBW_XMMdq_XMMdq: + return "_mm_hsub_epi16"; + case INTRINSIC_XED_IFORM_PHSUBSW_XMMdq_XMMdq: + return "_mm_hsubs_epi16"; + case INTRINSIC_XED_IFORM_PHSUBD_XMMdq_XMMdq: + return "_mm_hsub_epi32"; + case INTRINSIC_XED_IFORM_PHSUBW_MMXq_MMXq: + return "_mm_hsub_pi16"; + case INTRINSIC_XED_IFORM_PHSUBD_MMXq_MMXq: + return "_mm_hsub_pi32"; + case INTRINSIC_XED_IFORM_PHSUBSW_MMXq_MMXq: + return "_mm_hsubs_pi16"; + case INTRINSIC_XED_IFORM_PMADDUBSW_XMMdq_XMMdq: + return "_mm_maddubs_epi16"; + case INTRINSIC_XED_IFORM_PMADDUBSW_MMXq_MMXq: + return "_mm_maddubs_pi16"; + case INTRINSIC_XED_IFORM_PMULHRSW_XMMdq_XMMdq: + return "_mm_mulhrs_epi16"; + case INTRINSIC_XED_IFORM_PMULHRSW_MMXq_MMXq: + return "_mm_mulhrs_pi16"; + case INTRINSIC_XED_IFORM_PSIGNB_XMMdq_XMMdq: + return "_mm_sign_epi8"; + case INTRINSIC_XED_IFORM_PSIGNW_XMMdq_XMMdq: + return "_mm_sign_epi16"; + case INTRINSIC_XED_IFORM_PSIGND_XMMdq_XMMdq: + return "_mm_sign_epi32"; + case INTRINSIC_XED_IFORM_PSIGNB_MMXq_MMXq: + return "_mm_sign_pi8"; + case INTRINSIC_XED_IFORM_PSIGNW_MMXq_MMXq: + return "_mm_sign_pi16"; + case INTRINSIC_XED_IFORM_PSIGND_MMXq_MMXq: + return "_mm_sign_pi32"; + case INTRINSIC_XED_IFORM_RDTSC: + return "_rdtsc"; + case INTRINSIC_XED_IFORM_XSUSLDTRK: + return "_xsusldtrk"; + case INTRINSIC_XED_IFORM_XRESLDTRK: + return "_xresldtrk"; + case INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128: + return "_mm256_aesenclast_epi128"; + case INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128: + return "_mm256_aesenc_epi128"; + case INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128: + return "_mm256_aesdeclast_epi128"; + case INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128: + return "_mm256_aesdec_epi128"; + case INTRINSIC_XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512: + return "_mm512_clmulepi64_epi128"; + case INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512: + return "_mm256_clmulepi64_epi128"; + case INTRINSIC_XED_IFORM_TPAUSE_GPR32u32: + return "_tpause"; + case INTRINSIC_XED_IFORM_UMWAIT_GPR32: + return "_umwait"; + case INTRINSIC_XED_IFORM_UMONITOR_GPRa: + return "_umonitor"; + case INTRINSIC_XED_IFORM_WBNOINVD: + return "_wbnoinvd"; + case INTRINSIC_XED_IFORM_XGETBV: + return "_xgetbv"; + case INTRINSIC_XED_IFORM_XRSTOR_MEMmxsave: + return "_xrstor"; + case INTRINSIC_XED_IFORM_XRSTOR64_MEMmxsave: + return "_xrstor64"; + case INTRINSIC_XED_IFORM_XSAVE_MEMmxsave: + return "_xsave"; + case INTRINSIC_XED_IFORM_XSAVE64_MEMmxsave: + return "_xsave64"; + case INTRINSIC_XED_IFORM_XSAVEOPT_MEMmxsave: + return "_xsaveopt"; + case INTRINSIC_XED_IFORM_XSAVEOPT64_MEMmxsave: + return "_xsaveopt64"; + case INTRINSIC_XED_IFORM_XSETBV: + return "_xsetbv"; + case INTRINSIC_XED_IFORM_XSAVEC_MEMmxsave: + return "_xsavec"; + case INTRINSIC_XED_IFORM_XSAVES_MEMmxsave: + return "_xsaves"; + case INTRINSIC_XED_IFORM_XSAVEC64_MEMmxsave: + return "_xsavec64"; + case INTRINSIC_XED_IFORM_XRSTORS_MEMmxsave: + return "_xrstors"; + case INTRINSIC_XED_IFORM_XRSTORS64_MEMmxsave: + return "_xrstors64"; + + // below are modified iforms + case INTRINSIC_XED_IFORM_TZCNT_GPR16_GPRMEM16: + return "_tzcnt_u16"; + case INTRINSIC_XED_IFORM_TZCNT_GPR32_GPRMEM32: + return "_tzcnt_u32"; + case INTRINSIC_XED_IFORM_TZCNT_GPR64_GPRMEM64: + return "_tzcnt_u64"; + + case INTRINSIC_XED_IFORM_LZCNT_GPR16_GPRMEM16: + return "_lzcnt_u16"; + case INTRINSIC_XED_IFORM_LZCNT_GPR32_GPRMEM32: + return "_lzcnt_u32"; + case INTRINSIC_XED_IFORM_LZCNT_GPR64_GPRMEM64: + return "_lzcnt_u64"; + + case INTRINSIC_XED_IFORM_POPCNT_GPR16_GPRMEM16: + return "_popcnt_u16"; + case INTRINSIC_XED_IFORM_POPCNT_GPR32_GPRMEM32: + return "_popcnt_u32"; + case INTRINSIC_XED_IFORM_POPCNT_GPR64_GPRMEM64: + return "_popcnt_u64"; + + case INTRINSIC_XED_IFORM_REP_MOVSB: + return "__memcpy_u8"; + case INTRINSIC_XED_IFORM_REP_MOVSW: + return "__memcpy_u16"; + case INTRINSIC_XED_IFORM_REP_MOVSD: + return "__memcpy_u32"; + case INTRINSIC_XED_IFORM_REP_MOVSQ: + return "__memcpy_u64"; + + case INTRINSIC_XED_IFORM_REP_STOSB: + return "__memfill_u8"; + case INTRINSIC_XED_IFORM_REP_STOSW: + return "__memfill_u16"; + case INTRINSIC_XED_IFORM_REP_STOSD: + return "__memfill_u32"; + case INTRINSIC_XED_IFORM_REP_STOSQ: + return "__memfill_u64"; + + default: + // for iform without a corresponding intrisic, use the iform string + string iformString = xed_iform_enum_t2str((xed_iform_enum_t(intrinsic - 1000))); + for(char& c : iformString) + c = tolower(c); + return string("__") + iformString; + } +} + +vector<uint32_t> X86CommonArchitecture::GetAllIntrinsics() +{ + vector<uint32_t> allIntrinsics = { INTRINSIC_F2XM1, INTRINSIC_FBLD, INTRINSIC_FBST , INTRINSIC_FSIN, + INTRINSIC_FCOS, INTRINSIC_FSINCOS, INTRINSIC_FPATAN, INTRINSIC_FPREM, INTRINSIC_FPREM1, + INTRINSIC_FPTAN, INTRINSIC_FSCALE, INTRINSIC_FXAM, INTRINSIC_FXTRACT, INTRINSIC_FYL2X, + INTRINSIC_FYL2XP1}; + + allIntrinsics.reserve(allIntrinsics.size() + INTRINSIC_LAST - INTRINSIC_XED_IFORM_INVALID + 1); + for (uint32_t value = INTRINSIC_XED_IFORM_INVALID; + value <= INTRINSIC_LAST; value++) + allIntrinsics.emplace_back(value); + + return allIntrinsics; +} + +vector<NameAndType> X86CommonArchitecture::GetIntrinsicInputs(uint32_t intrinsic) +{ + switch (intrinsic) + { + case INTRINSIC_F2XM1: + case INTRINSIC_FBST: + case INTRINSIC_FSIN: + case INTRINSIC_FCOS: + case INTRINSIC_FSINCOS: + case INTRINSIC_FPTAN: + case INTRINSIC_FXAM: + case INTRINSIC_FXTRACT: + return vector<NameAndType> { NameAndType(Type::FloatType(10)) }; + case INTRINSIC_FBLD: + return vector<NameAndType> { NameAndType(Type::IntegerType(10, false)) }; + case INTRINSIC_FPATAN: + case INTRINSIC_FYL2X: + case INTRINSIC_FYL2XP1: + return vector<NameAndType> { NameAndType("x", Type::FloatType(10)), NameAndType("y", Type::FloatType(10)) }; + case INTRINSIC_FPREM: + case INTRINSIC_FPREM1: + case INTRINSIC_FSCALE: + return vector<NameAndType> { NameAndType(Type::FloatType(10)), NameAndType(Type::FloatType(10)) }; + case INTRINSIC_XED_IFORM_TZCNT_GPR64_GPRMEM64: + return vector<NameAndType> { NameAndType(Type::IntegerType(8, false)) }; + case INTRINSIC_XED_IFORM_TZCNT_GPR32_GPRMEM32: + return vector<NameAndType> { NameAndType(Type::IntegerType(4, false)) }; + case INTRINSIC_XED_IFORM_TZCNT_GPR16_GPRMEM16: + return vector<NameAndType> { NameAndType(Type::IntegerType(2, false)) }; + + case INTRINSIC_XED_IFORM_LZCNT_GPR64_GPRMEM64: + return vector<NameAndType> { NameAndType(Type::IntegerType(8, false)) }; + case INTRINSIC_XED_IFORM_LZCNT_GPR32_GPRMEM32: + return vector<NameAndType> { NameAndType(Type::IntegerType(4, false)) }; + case INTRINSIC_XED_IFORM_LZCNT_GPR16_GPRMEM16: + return vector<NameAndType> { NameAndType(Type::IntegerType(2, false)) }; + + case INTRINSIC_XED_IFORM_POPCNT_GPR64_GPRMEM64: + return vector<NameAndType> { NameAndType(Type::IntegerType(8, false)) }; + case INTRINSIC_XED_IFORM_POPCNT_GPR32_GPRMEM32: + return vector<NameAndType> { NameAndType(Type::IntegerType(4, false)) }; + case INTRINSIC_XED_IFORM_POPCNT_GPR16_GPRMEM16: + return vector<NameAndType> { NameAndType(Type::IntegerType(2, false)) }; + + #include "x86_intrinsic_input_type.include" + + default: + return vector<NameAndType>(); + } +} + +vector<Confidence<Ref<Type>>> X86CommonArchitecture::GetIntrinsicOutputs(uint32_t intrinsic) +{ + switch (intrinsic) + { + case INTRINSIC_F2XM1: + case INTRINSIC_FBLD: + case INTRINSIC_FPATAN: + case INTRINSIC_FSCALE: + case INTRINSIC_FYL2X: + case INTRINSIC_FYL2XP1: + return vector<Confidence<Ref<Type>>> { Type::FloatType(10) }; + case INTRINSIC_FBST: + return vector<Confidence<Ref<Type>>> { Type::IntegerType(10, false) }; + case INTRINSIC_FSIN: + case INTRINSIC_FCOS: + case INTRINSIC_FPTAN: + return vector<Confidence<Ref<Type>>> { Type::FloatType(10), Type::BoolType() }; + case INTRINSIC_FSINCOS: + return vector<Confidence<Ref<Type>>> { Type::FloatType(10), Type::FloatType(10), Type::BoolType() }; + case INTRINSIC_FPREM: + case INTRINSIC_FPREM1: + return vector<Confidence<Ref<Type>>> { Type::FloatType(10), Type::BoolType(), Type::IntegerType(1, false) }; + case INTRINSIC_FXAM: + return vector<Confidence<Ref<Type>>> { Type::BoolType(), Type::BoolType(), Type::BoolType(), Type::BoolType() }; + case INTRINSIC_FXTRACT: + return vector<Confidence<Ref<Type>>> { Type::FloatType(10), Type::FloatType(10) }; + + case INTRINSIC_XED_IFORM_TZCNT_GPR64_GPRMEM64: + return vector<Confidence<Ref<Type>>> { Type::IntegerType(8, false)}; + case INTRINSIC_XED_IFORM_TZCNT_GPR32_GPRMEM32: + return vector<Confidence<Ref<Type>>> { Type::IntegerType(4, false)}; + case INTRINSIC_XED_IFORM_TZCNT_GPR16_GPRMEM16: + return vector<Confidence<Ref<Type>>> { Type::IntegerType(2, false)}; + + case INTRINSIC_XED_IFORM_LZCNT_GPR64_GPRMEM64: + return vector<Confidence<Ref<Type>>> { Type::IntegerType(8, false)}; + case INTRINSIC_XED_IFORM_LZCNT_GPR32_GPRMEM32: + return vector<Confidence<Ref<Type>>> { Type::IntegerType(4, false)}; + case INTRINSIC_XED_IFORM_LZCNT_GPR16_GPRMEM16: + return vector<Confidence<Ref<Type>>> { Type::IntegerType(2, false)}; + + case INTRINSIC_XED_IFORM_POPCNT_GPR64_GPRMEM64: + return vector<Confidence<Ref<Type>>> { Type::IntegerType(8, false)}; + case INTRINSIC_XED_IFORM_POPCNT_GPR32_GPRMEM32: + return vector<Confidence<Ref<Type>>> { Type::IntegerType(4, false)}; + case INTRINSIC_XED_IFORM_POPCNT_GPR16_GPRMEM16: + return vector<Confidence<Ref<Type>>> { Type::IntegerType(2, false)}; + + #include "x86_intrinsic_output_type.include" + + default: + return vector<Confidence<Ref<Type>>>(); + } +} + + +#ifdef __APPLE__ +// clang is very slow at optimizing this function. Optimizations have nearly zero +// impact on initialization time, so just turn them off. +void X86CommonArchitecture::InitializeCachedInputTypes() __attribute__((optnone)) +#else +void X86CommonArchitecture::InitializeCachedInputTypes() +#endif +{ +#include "x86_intrinsic_cached_input_types.include" +} + + +#ifdef __APPLE__ +// clang is very slow at optimizing this function. Optimizations have nearly zero +// impact on initialization time, so just turn them off. +void X86CommonArchitecture::InitializeCachedOutputTypes() __attribute__((optnone)) +#else +void X86CommonArchitecture::InitializeCachedOutputTypes() +#endif +{ +#include "x86_intrinsic_cached_output_types.include" +} + + +void X86CommonArchitecture::InitializeCachedTypes() +{ + X86CommonArchitecture::InitializeCachedInputTypes(); + X86CommonArchitecture::InitializeCachedOutputTypes(); +} diff --git a/arch/x86/code_generator/README.md b/arch/x86/code_generator/README.md new file mode 100644 index 00000000..5c53ad1f --- /dev/null +++ b/arch/x86/code_generator/README.md @@ -0,0 +1,11 @@ +This README explains the process of generating the input and output type information for x86 intrinsics. + +It takes two major steps: + +1. Tweak the xed build process and generate the information for each iform. + - Apply the `patch.diff` to `$XED_SOURCE/pysrc/generator.py` + - Build xed and harvest the `iform-type-dump.txt` + - Copy the `iform-type-dump.txt` to the current folder + +2. run the `parse-iform-types.py` + - It will generate `../x86_intrinsic_input_type.cpp` and `../x86_intrinsic_output_type.cpp`.
\ No newline at end of file diff --git a/arch/x86/code_generator/iform-type-dump.txt b/arch/x86/code_generator/iform-type-dump.txt new file mode 100644 index 00000000..b34b2211 --- /dev/null +++ b/arch/x86/code_generator/iform-type-dump.txt @@ -0,0 +1,35791 @@ +INTRINSIC_XED_IFORM_FADD_ST0_MEMmem32real + f80 rw f80 + f32 r mem32real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FADD_ST0_X87 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FADD_ST0_MEMm64real + f80 rw f80 + f64 r m64real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FADD_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FMUL_ST0_MEMmem32real + f80 rw f80 + f32 r mem32real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FMUL_ST0_X87 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FMUL_ST0_MEMm64real + f80 rw f80 + f64 r m64real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FMUL_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOMP_ST0_MEMmem32real + f80 r f80 + f32 r mem32real + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOMP_ST0_X87 + f80 r f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOMP_ST0_X87_DCD1 + f80 r f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOMP_ST0_X87_DED0 + f80 r f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOMP_ST0_MEMm64real + f80 r f80 + f64 r m64real + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUB_ST0_MEMmem32real + f80 rw f80 + f32 r mem32real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUB_ST0_X87 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUB_ST0_MEMm64real + f80 rw f80 + f64 r m64real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUB_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUBR_ST0_MEMmem32real + f80 rw f80 + f32 r mem32real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUBR_ST0_X87 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUBR_ST0_MEMm64real + f80 rw f80 + f64 r m64real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUBR_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIV_ST0_MEMmem32real + f80 rw f80 + f32 r mem32real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIV_ST0_X87 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIV_ST0_MEMm64real + f80 rw f80 + f64 r m64real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIV_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIVR_ST0_MEMmem32real + f80 rw f80 + f32 r mem32real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIVR_ST0_X87 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIVR_ST0_MEMm64real + f80 rw f80 + f64 r m64real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIVR_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOM_ST0_MEMmem32real + f80 r f80 + f32 r mem32real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOM_ST0_MEMm64real + f80 r f80 + f64 r m64real + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOM_ST0_X87 + f80 r f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOM_ST0_X87_DCD0 + f80 r f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLD_ST0_MEMmem32real + f80 w f80 + f32 r mem32real + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLD_ST0_X87 + f80 w f80 + f80 r f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLD_ST0_MEMmem80real + f80 w f80 + f80 r mem80real + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLD_ST0_MEMm64real + f80 w f80 + f64 r m64real + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FST_MEMmem32real_ST0 + f32 w mem32real + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FST_MEMm64real_ST0 + f64 w m64real + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FST_X87_ST0 + f80 w f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSTP_MEMmem32real_ST0 + f32 w mem32real + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSTP_MEMmem80real_ST0 + f80 w mem80real + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSTP_MEMm64real_ST0 + f64 w m64real + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSTP_X87_ST0 + f80 w f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSTP_X87_ST0_DFD0 + f80 w f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSTP_X87_ST0_DFD1 + f80 w f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSTPNCE_X87_ST0 + f80 w f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDENV_MEMmem14 + struct r mem14 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDENV_MEMmem28 + struct r mem28 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDCW_MEMmem16 + struct r mem16 + INVALID w XED_REG_X87CONTROL + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNSTENV_MEMmem14 + struct w mem14 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNSTENV_MEMmem28 + struct w mem28 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNSTCW_MEMmem16 + struct w mem16 + INVALID r XED_REG_X87CONTROL + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FXCH_ST0_X87 + f80 rw f80 + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FXCH_ST0_X87_DFC1 + f80 rw f80 + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FXCH_ST0_X87_DDC1 + f80 rw f80 + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNOP + +INTRINSIC_XED_IFORM_FCHS + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FABS + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FTST + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FXAM + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLD1 + f80 w f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDL2T + f80 w f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDL2E + f80 w f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDPI + f80 w f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDLG2 + f80 w f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDLN2 + f80 w f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FLDZ + f80 w f80 + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_F2XM1 + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FYL2X + f80 r f80 + f80 rw f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FPTAN + f80 rw f80 + f80 w f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FPATAN + f80 r f80 + f80 rw f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FXTRACT + f80 rw f80 + f80 w f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FPREM1 + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDECSTP + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FINCSTP + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FPREM + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FYL2XP1 + f80 r f80 + f80 rw f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSQRT + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSINCOS + f80 rw f80 + f80 w f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FRNDINT + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSCALE + f80 rw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSIN + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOS + f80 rw f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIADD_ST0_MEMmem32int + f80 rw f80 + i32 r mem32int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIADD_ST0_MEMmem16int + f80 rw f80 + i16 r mem16int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIMUL_ST0_MEMmem32int + f80 rw f80 + i32 r mem32int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIMUL_ST0_MEMmem16int + f80 rw f80 + i16 r mem16int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FICOM_ST0_MEMmem32int + f80 r f80 + i32 r mem32int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FICOM_ST0_MEMmem16int + f80 r f80 + i16 r mem16int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FICOMP_ST0_MEMmem32int + f80 r f80 + i32 r mem32int + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FICOMP_ST0_MEMmem16int + f80 r f80 + i16 r mem16int + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISUB_ST0_MEMmem32int + f80 rw f80 + i32 r mem32int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISUB_ST0_MEMmem16int + f80 rw f80 + i16 r mem16int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISUBR_ST0_MEMmem32int + f80 rw f80 + i32 r mem32int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISUBR_ST0_MEMmem16int + f80 rw f80 + i16 r mem16int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIDIV_ST0_MEMmem32int + f80 rw f80 + i32 r mem32int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIDIV_ST0_MEMmem16int + f80 rw f80 + i16 r mem16int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIDIVR_ST0_MEMmem32int + f80 rw f80 + i32 r mem32int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIDIVR_ST0_MEMmem16int + f80 rw f80 + i16 r mem16int + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCMOVB_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FCMOVE_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FCMOVBE_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FCMOVU_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FUCOMPP + f80 r f80 + f80 r f80 + INVALID rw XED_REG_X87POP2 + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FILD_ST0_MEMmem32int + f80 w f80 + i32 r mem32int + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FILD_ST0_MEMmem16int + f80 w f80 + i16 r mem16int + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FILD_ST0_MEMm64int + f80 w f80 + i64 r m64int + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISTTP_MEMmem32int_ST0 + i32 w mem32int + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISTTP_MEMm64int_ST0 + i64 w m64int + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISTTP_MEMmem16int_ST0 + i16 w mem16int + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIST_MEMmem32int_ST0 + i32 w mem32int + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FIST_MEMmem16int_ST0 + i16 w mem16int + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISTP_MEMmem32int_ST0 + i32 w mem32int + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISTP_MEMmem16int_ST0 + i16 w mem16int + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FISTP_MEMm64int_ST0 + i64 w m64int + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCMOVNB_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FCMOVNE_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FCMOVNBE_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FCMOVNU_ST0_X87 + f80 cw f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_FNCLEX + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNINIT + INVALID w XED_REG_X87CONTROL + INVALID w XED_REG_X87TAG + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSETPM287_NOP + +INTRINSIC_XED_IFORM_FENI8087_NOP + +INTRINSIC_XED_IFORM_FDISI8087_NOP + +INTRINSIC_XED_IFORM_FUCOMI_ST0_X87 + f80 r f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_FCOMI_ST0_X87 + f80 r f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_FRSTOR_MEMmem94 + struct r mem94 + INVALID w XED_REG_X87CONTROL + +INTRINSIC_XED_IFORM_FRSTOR_MEMmem108 + struct r mem108 + INVALID w XED_REG_X87CONTROL + +INTRINSIC_XED_IFORM_FNSAVE_MEMmem94 + struct w mem94 + INVALID rw XED_REG_X87CONTROL + INVALID rw XED_REG_X87TAG + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNSAVE_MEMmem108 + struct w mem108 + INVALID rw XED_REG_X87CONTROL + INVALID rw XED_REG_X87TAG + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNSTSW_MEMmem16 + struct w mem16 + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FNSTSW_AX + INVALID w XED_REG_AX + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FFREE_X87 + f80 r f80 + INVALID w XED_REG_X87TAG + +INTRINSIC_XED_IFORM_FUCOM_ST0_X87 + f80 r f80 + f80 r f80 + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FUCOMP_ST0_X87 + f80 r f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FADDP_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FMULP_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FCOMPP + f80 r f80 + f80 r f80 + INVALID r XED_REG_X87POP2 + INVALID rw XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUBRP_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FSUBP_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIVRP_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FDIVP_X87_ST0 + f80 rw f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FBLD_ST0_MEMmem80dec + f80 w f80 + b80 r mem80dec + INVALID r XED_REG_X87PUSH + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FBSTP_MEMmem80dec_ST0 + b80 w mem80dec + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + +INTRINSIC_XED_IFORM_FFREEP_X87 + f80 r f80 + INVALID w XED_REG_X87TAG + INVALID r XED_REG_X87POP + +INTRINSIC_XED_IFORM_FUCOMIP_ST0_X87 + f80 r f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_FCOMIP_ST0_X87 + f80 r f80 + f80 r f80 + INVALID r XED_REG_X87POP + INVALID w XED_REG_X87STATUS + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMb_IMMb_80r0 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8_IMMb_80r0 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_IMMz + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMb_IMMb_82r0 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8_IMMb_82r0 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8_GPR8_00 + INVALID rw GPR8_B + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_01 + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8_MEMb + INVALID rw GPR8_R + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPR8_GPR8_02 + INVALID rw GPR8_R + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_03 + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_AL_IMMb + INVALID rw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADD_OrAX_IMMz + INVALID rw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_LOCK_MEMb_IMMb_80r1 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_LOCK_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_LOCK_MEMb_IMMb_82r1 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_LOCK_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMb_IMMb_80r1 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8_IMMb_80r1 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_IMMz + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMb_IMMb_82r1 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8_IMMb_82r1 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8_GPR8_08 + INVALID rw GPR8_B + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_GPRv_09 + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8_MEMb + INVALID rw GPR8_R + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPR8_GPR8_0A + INVALID rw GPR8_R + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_GPRv_GPRv_0B + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_AL_IMMb + INVALID rw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_OR_OrAX_IMMz + INVALID rw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_IMMz + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_IMMb + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMb_IMMb_80r2 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8_IMMb_80r2 + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMv_IMMz + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_IMMz + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMb_IMMb_82r2 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8_IMMb_82r2 + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMv_IMMb + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_IMMb + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8_GPR8_10 + INVALID rw GPR8_B + INVALID r GPR8_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_11 + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8_MEMb + INVALID rw GPR8_R + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPR8_GPR8_12 + INVALID rw GPR8_R + INVALID r GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_13 + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_AL_IMMb + INVALID rw XED_REG_AL + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADC_OrAX_IMMz + INVALID rw OrAX + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_IMMz + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_IMMb + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMb_IMMb_80r3 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8_IMMb_80r3 + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMv_IMMz + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_IMMz + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMb_IMMb_82r3 + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8_IMMb_82r3 + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMv_IMMb + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_IMMb + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8_GPR8_18 + INVALID rw GPR8_B + INVALID r GPR8_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_19 + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8_GPR8_1A + INVALID rw GPR8_R + INVALID r GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPR8_MEMb + INVALID rw GPR8_R + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_1B + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_AL_IMMb + INVALID rw XED_REG_AL + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SBB_OrAX_IMMz + INVALID rw OrAX + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_AND_LOCK_MEMb_IMMb_80r4 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_LOCK_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_LOCK_MEMb_IMMb_82r4 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_LOCK_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMb_IMMb_80r4 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8_IMMb_80r4 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_IMMz + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMb_IMMb_82r4 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8_IMMb_82r4 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8_GPR8_20 + INVALID rw GPR8_B + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_GPRv_21 + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8_GPR8_22 + INVALID rw GPR8_R + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPR8_MEMb + INVALID rw GPR8_R + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_GPRv_23 + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_AL_IMMb + INVALID rw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AND_OrAX_IMMz + INVALID rw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMb_IMMb_80r5 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8_IMMb_80r5 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_IMMz + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMb_IMMb_82r5 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8_IMMb_82r5 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8_GPR8_28 + INVALID rw GPR8_B + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_GPRv_29 + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8_GPR8_2A + INVALID rw GPR8_R + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPR8_MEMb + INVALID rw GPR8_R + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_GPRv_2B + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_AL_IMMb + INVALID rw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SUB_OrAX_IMMz + INVALID rw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMb_IMMb_80r6 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8_IMMb_80r6 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMv_IMMz + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_IMMz + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMb_IMMb_82r6 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8_IMMb_82r6 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMb_GPR8 + u8 rw b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8_GPR8_30 + INVALID rw GPR8_B + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_GPRv_31 + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8_GPR8_32 + INVALID rw GPR8_R + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPR8_MEMb + INVALID rw GPR8_R + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_GPRv_33 + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_AL_IMMb + INVALID rw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XOR_OrAX_IMMz + INVALID rw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_MEMb_IMMb_80r7 + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPR8_IMMb_80r7 + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_MEMv_IMMz + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPRv_IMMz + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_MEMb_IMMb_82r7 + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPR8_IMMb_82r7 + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_MEMv_IMMb + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPRv_IMMb + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_MEMb_GPR8 + u8 r b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPR8_GPR8_38 + INVALID r GPR8_B + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_MEMv_GPRv + int r v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPRv_GPRv_39 + INVALID r GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPR8_MEMb + INVALID r GPR8_R + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPR8_GPR8_3A + INVALID r GPR8_R + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPRv_MEMv + INVALID r GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_GPRv_GPRv_3B + INVALID r GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_AL_IMMb + INVALID r XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMP_OrAX_IMMz + INVALID r OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_POP_MEMv + int w v + int r spw + int r spw + +INTRINSIC_XED_IFORM_POP_GPRv_8F + INVALID w GPRv_B + int r spw + int r spw + +INTRINSIC_XED_IFORM_POP_ES + INVALID w XED_REG_ES + int r spw + int r spw + +INTRINSIC_XED_IFORM_POP_SS + INVALID w XED_REG_SS + int r spw + int r spw + +INTRINSIC_XED_IFORM_POP_DS + INVALID w XED_REG_DS + int r spw + int r spw + +INTRINSIC_XED_IFORM_POP_GPRv_58 + INVALID w GPRv_SB + int r spw + int r spw + +INTRINSIC_XED_IFORM_POP_FS + INVALID w XED_REG_FS + int r spw + int r spw + +INTRINSIC_XED_IFORM_POP_GS + INVALID w XED_REG_GS + int r spw + int r spw + +INTRINSIC_XED_IFORM_ROL_MEMb_IMMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPR8_IMMb + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMb_ONE + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPR8_ONE + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMv_ONE + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPRv_ONE + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMb_CL + u8 rw b + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPR8_CL + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROL_MEMv_CL + int rw v + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROL_GPRv_CL + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMb_IMMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPR8_IMMb + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMb_ONE + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPR8_ONE + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMv_ONE + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPRv_ONE + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMb_CL + u8 rw b + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPR8_CL + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_MEMv_CL + int rw v + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_ROR_GPRv_CL + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMb_IMMb + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPR8_IMMb + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMv_IMMb + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPRv_IMMb + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMb_ONE + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPR8_ONE + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMv_ONE + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPRv_ONE + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMb_CL + u8 rw b + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPR8_CL + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCL_MEMv_CL + int rw v + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCL_GPRv_CL + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMb_IMMb + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPR8_IMMb + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMv_IMMb + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPRv_IMMb + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMb_ONE + u8 rw b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPR8_ONE + INVALID rw GPR8_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMv_ONE + int rw v + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPRv_ONE + INVALID rw GPRv_B + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMb_CL + u8 rw b + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPR8_CL + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_MEMv_CL + int rw v + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_RCR_GPRv_CL + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMb_IMMb_C0r4 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8_IMMb_C0r4 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMb_IMMb_C0r6 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8_IMMb_C0r6 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMv_IMMb_C1r4 + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_IMMb_C1r4 + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMv_IMMb_C1r6 + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_IMMb_C1r6 + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMb_ONE_D0r4 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8_ONE_D0r4 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMb_ONE_D0r6 + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8_ONE_D0r6 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMv_ONE_D1r6 + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_ONE_D1r6 + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMv_ONE_D1r4 + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_ONE_D1r4 + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMb_CL_D2r4 + u8 rw b + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8_CL_D2r4 + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMb_CL_D2r6 + u8 rw b + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPR8_CL_D2r6 + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMv_CL_D3r4 + int rw v + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_CL_D3r4 + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_MEMv_CL_D3r6 + int rw v + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHL_GPRv_CL_D3r6 + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMb_IMMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPR8_IMMb + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMb_ONE + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPR8_ONE + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMv_ONE + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPRv_ONE + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMb_CL + u8 rw b + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPR8_CL + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_MEMv_CL + int rw v + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHR_GPRv_CL + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMb_IMMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPR8_IMMb + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMb_ONE + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPR8_ONE + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMv_ONE + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPRv_ONE + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMb_CL + u8 rw b + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPR8_CL + INVALID rw GPR8_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_MEMv_CL + int rw v + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SAR_GPRv_CL + INVALID rw GPRv_B + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_TEST_MEMb_IMMb_F6r0 + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_MEMb_IMMb_F6r1 + u8 r b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_GPR8_IMMb_F6r0 + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_GPR8_IMMb_F6r1 + INVALID r GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_MEMv_IMMz_F7r0 + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_MEMv_IMMz_F7r1 + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_GPRv_IMMz_F7r0 + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_GPRv_IMMz_F7r1 + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_MEMb_GPR8 + u8 r b + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_GPR8_GPR8 + INVALID r GPR8_B + INVALID r GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_MEMv_GPRv + int r v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_GPRv_GPRv + INVALID r GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_AL_IMMb + INVALID r XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TEST_OrAX_IMMz + INVALID r OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NOT_LOCK_MEMb + u8 rw b + +INTRINSIC_XED_IFORM_NOT_LOCK_MEMv + int rw v + +INTRINSIC_XED_IFORM_NOT_MEMb + u8 rw b + +INTRINSIC_XED_IFORM_NOT_GPR8 + INVALID rw GPR8_B + +INTRINSIC_XED_IFORM_NOT_MEMv + int rw v + +INTRINSIC_XED_IFORM_NOT_GPRv + INVALID rw GPRv_B + +INTRINSIC_XED_IFORM_NEG_LOCK_MEMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_LOCK_MEMv + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_MEMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_GPR8 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_MEMv + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_NEG_GPRv + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MUL_MEMb + u8 r b + INVALID r XED_REG_AL + INVALID w XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MUL_GPR8 + INVALID r GPR8_B + INVALID r XED_REG_AL + INVALID w XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MUL_MEMv + int r v + INVALID rw OrAX + INVALID w OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MUL_GPRv + INVALID r GPRv_B + INVALID rw OrAX + INVALID w OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_MEMb + u8 r b + INVALID r XED_REG_AL + INVALID w XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPR8 + INVALID r GPR8_B + INVALID r XED_REG_AL + INVALID w XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_MEMv + int r v + INVALID rw OrAX + INVALID w OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv + INVALID r GPRv_B + INVALID rw OrAX + INVALID w OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv_IMMz + INVALID w GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_IMMz + INVALID w GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv_IMMb + INVALID w GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_IMMb + INVALID w GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv + INVALID rw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv + INVALID rw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DIV_MEMb + u8 r b + INVALID rw XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DIV_GPR8 + INVALID r GPR8_B + INVALID rw XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DIV_MEMv + int r v + INVALID rw OrAX + INVALID rw OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DIV_GPRv + INVALID r GPRv_B + INVALID rw OrAX + INVALID rw OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IDIV_MEMb + u8 r b + INVALID rw XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IDIV_GPR8 + INVALID r GPR8_B + INVALID rw XED_REG_AX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IDIV_MEMv + int r v + INVALID rw OrAX + INVALID rw OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_IDIV_GPRv + INVALID r GPRv_B + INVALID rw OrAX + INVALID rw OrDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_LOCK_MEMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_LOCK_MEMv + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_MEMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_GPR8 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_MEMv + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_GPRv_FFr0 + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INC_GPRv_40 + INVALID rw GPRv_SB + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_LOCK_MEMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_LOCK_MEMv + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_MEMb + u8 rw b + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_GPR8 + INVALID rw GPR8_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_MEMv + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_GPRv_FFr1 + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_DEC_GPRv_48 + INVALID rw GPRv_SB + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CALL_NEAR_MEMv + int r v + int w spw + INVALID rw rIP + int w spw + +INTRINSIC_XED_IFORM_CALL_NEAR_GPRv + INVALID r GPRv_B + int w spw + INVALID rw rIP + int w spw + +INTRINSIC_XED_IFORM_CALL_NEAR_RELBRz + int w spw + INVALID rw XED_REG_EIP + int w spw + +INTRINSIC_XED_IFORM_CALL_NEAR_RELBRd + int w spw + INVALID rw XED_REG_RIP + int w spw + +INTRINSIC_XED_IFORM_JMP_MEMv + int r v + INVALID w rIP + +INTRINSIC_XED_IFORM_JMP_GPRv + INVALID r GPRv_B + INVALID w rIP + +INTRINSIC_XED_IFORM_JMP_RELBRz + INVALID rw XED_REG_EIP + +INTRINSIC_XED_IFORM_JMP_RELBRd + INVALID rw XED_REG_RIP + +INTRINSIC_XED_IFORM_JMP_RELBRb + INVALID rw XED_REG_EIP + +INTRINSIC_XED_IFORM_JMP_FAR_MEMp2 + struct r p2 + INVALID w rIP + +INTRINSIC_XED_IFORM_JMP_FAR_PTRp_IMMw + INVALID w XED_REG_EIP + +INTRINSIC_XED_IFORM_PUSH_MEMv + int r v + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_GPRv_FFr6 + INVALID r GPRv_B + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_ES + INVALID r XED_REG_ES + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_CS + INVALID r XED_REG_CS + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_SS + INVALID r XED_REG_SS + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_DS + INVALID r XED_REG_DS + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_GPRv_50 + INVALID r GPRv_SB + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_IMMz + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_IMMb + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_FS + INVALID r XED_REG_FS + int w spw + int w spw + +INTRINSIC_XED_IFORM_PUSH_GS + INVALID r XED_REG_GS + int w spw + int w spw + +INTRINSIC_XED_IFORM_SLDT_MEMw + i16 w w + INVALID r XED_REG_LDTR + +INTRINSIC_XED_IFORM_SLDT_GPRv + INVALID w GPRv_B + INVALID r XED_REG_LDTR + +INTRINSIC_XED_IFORM_STR_MEMw + i16 w w + INVALID r XED_REG_TR + +INTRINSIC_XED_IFORM_STR_GPRv + INVALID w GPRv_B + INVALID r XED_REG_TR + +INTRINSIC_XED_IFORM_LLDT_MEMw + i16 r w + INVALID w XED_REG_LDTR + +INTRINSIC_XED_IFORM_LLDT_GPR16 + INVALID r GPR16_B + INVALID w XED_REG_LDTR + +INTRINSIC_XED_IFORM_LTR_MEMw + i16 r w + INVALID w XED_REG_TR + +INTRINSIC_XED_IFORM_LTR_GPR16 + INVALID r GPR16_B + INVALID w XED_REG_TR + +INTRINSIC_XED_IFORM_VERR_MEMw + i16 r w + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VERR_GPR16 + INVALID r GPR16_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VERW_MEMw + i16 r w + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VERW_GPR16 + INVALID r GPR16_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LGDT_MEMs64 + struct r s64 + INVALID w XED_REG_GDTR + +INTRINSIC_XED_IFORM_LGDT_MEMs + struct r s + INVALID w XED_REG_GDTR + +INTRINSIC_XED_IFORM_SMSW_MEMw + i16 w w + INVALID r XED_REG_CR0 + +INTRINSIC_XED_IFORM_SMSW_GPRv + INVALID w GPRv_B + INVALID r XED_REG_CR0 + +INTRINSIC_XED_IFORM_LMSW_MEMw + i16 r w + INVALID w XED_REG_CR0 + +INTRINSIC_XED_IFORM_LMSW_GPR16 + INVALID r GPR16_B + INVALID w XED_REG_CR0 + +INTRINSIC_XED_IFORM_BT_MEMv_IMMb + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BT_GPRv_IMMb + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BT_MEMv_GPRv + int r v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BT_GPRv_GPRv + INVALID r GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTS_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTS_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTS_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTS_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTS_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTS_GPRv_GPRv + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTR_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTR_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTR_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTR_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTR_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTR_GPRv_GPRv + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTC_LOCK_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTC_LOCK_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTC_MEMv_IMMb + int rw v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTC_GPRv_IMMb + INVALID rw GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTC_MEMv_GPRv + int rw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BTC_GPRv_GPRv + INVALID rw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMCLEAR_MEMq + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMPTRLD_MEMq + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMPTRST_MEMq + i64 w q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMXON_MEMq + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG8B_LOCK_MEMq + i64 rcw q + INVALID rcw XED_REG_EDX + INVALID rcw XED_REG_EAX + INVALID r XED_REG_ECX + INVALID r XED_REG_EBX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG8B_MEMq + i64 rcw q + INVALID rcw XED_REG_EDX + INVALID rcw XED_REG_EAX + INVALID r XED_REG_ECX + INVALID r XED_REG_EBX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG16B_LOCK_MEMdq + i32 rcw dq + INVALID rcw XED_REG_RDX + INVALID rcw XED_REG_RAX + INVALID r XED_REG_RCX + INVALID r XED_REG_RBX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG16B_MEMdq + i32 rcw dq + INVALID rcw XED_REG_RDX + INVALID rcw XED_REG_RAX + INVALID r XED_REG_RCX + INVALID r XED_REG_RBX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MOV_GPR8_IMMb_C6r0 + INVALID w GPR8_B + +INTRINSIC_XED_IFORM_MOV_MEMb_IMMb + u8 w b + +INTRINSIC_XED_IFORM_MOV_GPRv_IMMz + INVALID w GPRv_B + +INTRINSIC_XED_IFORM_MOV_MEMv_IMMz + int w v + +INTRINSIC_XED_IFORM_MOV_GPR8_GPR8_88 + INVALID w GPR8_B + INVALID r GPR8_R + +INTRINSIC_XED_IFORM_MOV_MEMb_GPR8 + u8 w b + INVALID r GPR8_R + +INTRINSIC_XED_IFORM_MOV_MEMv_GPRv + int w v + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_MOV_GPRv_GPRv_89 + INVALID w GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_MOV_GPR8_MEMb + INVALID w GPR8_R + u8 r b + +INTRINSIC_XED_IFORM_MOV_GPR8_GPR8_8A + INVALID w GPR8_R + INVALID r GPR8_B + +INTRINSIC_XED_IFORM_MOV_GPRv_MEMv + INVALID w GPRv_R + int r v + +INTRINSIC_XED_IFORM_MOV_GPRv_GPRv_8B + INVALID w GPRv_R + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_MOV_MEMw_SEG + i16 w w + INVALID r SEG + +INTRINSIC_XED_IFORM_MOV_GPRv_SEG + INVALID w GPRv_B + INVALID r SEG + +INTRINSIC_XED_IFORM_MOV_SEG_MEMw + INVALID w SEG_MOV + i16 r w + +INTRINSIC_XED_IFORM_MOV_SEG_GPR16 + INVALID w SEG_MOV + INVALID r GPR16_B + +INTRINSIC_XED_IFORM_MOV_AL_MEMb + INVALID w XED_REG_AL + u8 r b + +INTRINSIC_XED_IFORM_MOV_OrAX_MEMv + INVALID w OrAX + int r v + +INTRINSIC_XED_IFORM_MOV_MEMb_AL + u8 w b + INVALID r XED_REG_AL + +INTRINSIC_XED_IFORM_MOV_MEMv_OrAX + int w v + INVALID r OrAX + +INTRINSIC_XED_IFORM_MOV_GPR8_IMMb_B0 + INVALID w GPR8_SB + +INTRINSIC_XED_IFORM_MOV_GPRv_IMMv + INVALID w GPRv_SB + +INTRINSIC_XED_IFORM_PSRLW_MMXq_IMMb + u16 rw q + +INTRINSIC_XED_IFORM_PSRLW_XMMdq_IMMb + u16 rw dq + +INTRINSIC_XED_IFORM_PSRLW_MMXq_MEMq + u16 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRLW_MMXq_MMXq + u16 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRLW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSRLW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSRAW_MMXq_IMMb + i16 rw q + +INTRINSIC_XED_IFORM_PSRAW_XMMdq_IMMb + i16 rw dq + +INTRINSIC_XED_IFORM_PSRAW_MMXq_MEMq + i16 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRAW_MMXq_MMXq + i16 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRAW_XMMdq_MEMdq + i16 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_PSRAW_XMMdq_XMMdq + i16 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_PSLLW_MMXq_IMMb + u16 rw q + +INTRINSIC_XED_IFORM_PSLLW_XMMdq_IMMb + u16 rw dq + +INTRINSIC_XED_IFORM_PSLLW_MMXq_MEMq + u16 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSLLW_MMXq_MMXq + u16 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSLLW_XMMdq_MEMdq + u16 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSLLW_XMMdq_XMMdq + u16 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSRLD_MMXq_IMMb + u32 rw q + +INTRINSIC_XED_IFORM_PSRLD_XMMdq_IMMb + u32 rw dq + +INTRINSIC_XED_IFORM_PSRLD_MMXq_MEMq + u32 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRLD_MMXq_MMXq + u32 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRLD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSRLD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSRAD_MMXq_IMMb + i32 rw q + +INTRINSIC_XED_IFORM_PSRAD_XMMdq_IMMb + i32 rw dq + +INTRINSIC_XED_IFORM_PSRAD_MMXq_MEMq + i32 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRAD_MMXq_MMXq + i32 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRAD_XMMdq_MEMdq + i32 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_PSRAD_XMMdq_XMMdq + i32 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_PSLLD_MMXq_IMMb + u32 rw q + +INTRINSIC_XED_IFORM_PSLLD_XMMdq_IMMb + u32 rw dq + +INTRINSIC_XED_IFORM_PSLLD_MMXq_MEMq + u32 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSLLD_MMXq_MMXq + u32 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSLLD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSLLD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSRLQ_MMXq_IMMb + u64 rw q + +INTRINSIC_XED_IFORM_PSRLQ_XMMdq_IMMb + u64 rw dq + +INTRINSIC_XED_IFORM_PSRLQ_MMXq_MEMq + u64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRLQ_MMXq_MMXq + u64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSRLQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSRLQ_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSLLQ_MMXq_IMMb + u64 rw q + +INTRINSIC_XED_IFORM_PSLLQ_XMMdq_IMMb + u64 rw dq + +INTRINSIC_XED_IFORM_PSLLQ_MMXq_MEMq + u64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSLLQ_MMXq_MMXq + u64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSLLQ_XMMdq_MEMdq + u64 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_PSLLQ_XMMdq_XMMdq + u64 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_PSRLDQ_XMMdq_IMMb + u128 rw dq + +INTRINSIC_XED_IFORM_PSLLDQ_XMMdq_IMMb + u128 rw dq + +INTRINSIC_XED_IFORM_FXSAVE_MEMmfpxenv + struct w mfpxenv + INVALID r XED_REG_X87CONTROL + +INTRINSIC_XED_IFORM_FXRSTOR_MEMmfpxenv + struct r mfpxenv + INVALID w XED_REG_X87CONTROL + +INTRINSIC_XED_IFORM_FXSAVE64_MEMmfpxenv + struct w mfpxenv + INVALID r XED_REG_X87CONTROL + +INTRINSIC_XED_IFORM_FXRSTOR64_MEMmfpxenv + struct r mfpxenv + INVALID w XED_REG_X87CONTROL + +INTRINSIC_XED_IFORM_LDMXCSR_MEMd + i32 r d + INVALID w XED_REG_MXCSR + +INTRINSIC_XED_IFORM_STMXCSR_MEMd + i32 w d + INVALID r XED_REG_MXCSR + +INTRINSIC_XED_IFORM_PREFETCHNTA_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCHT0_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCHT1_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCHT2_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r0 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r1 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r2 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r3 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_MEMv_0F18r4 + int r v + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r4 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_MEMv_0F18r5 + int r v + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r5 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_MEMv_0F18r6 + int r v + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r6 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_MEMv_0F18r7 + int r v + +INTRINSIC_XED_IFORM_NOP_GPRv_0F18r7 + INVALID r GPRv_B + +INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F19 + int r v + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F19 + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1D + int r v + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1D + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1F + int r v + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1F + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_90 + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F0D + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1A + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1B + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_MEMv_0F1A + INVALID r GPRv_B + int r v + +INTRINSIC_XED_IFORM_NOP_GPRv_MEM_0F1B + INVALID r GPRv_B + int r v + +INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1E + int r v + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1E + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1C + int r v + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1C + INVALID r GPRv_B + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_VMCALL + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_VMLAUNCH + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_VMRESUME + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_VMXOFF + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SGDT_MEMs64 + struct w s64 + INVALID r XED_REG_GDTR + +INTRINSIC_XED_IFORM_SGDT_MEMs + struct w s + INVALID r XED_REG_GDTR + +INTRINSIC_XED_IFORM_LIDT_MEMs64 + struct r s64 + INVALID w XED_REG_IDTR + +INTRINSIC_XED_IFORM_LIDT_MEMs + struct r s + INVALID w XED_REG_IDTR + +INTRINSIC_XED_IFORM_MONITOR + INVALID r XED_REG_EAX + INVALID r XED_REG_ECX + INVALID r XED_REG_EDX + +INTRINSIC_XED_IFORM_MWAIT + INVALID r XED_REG_EAX + INVALID r XED_REG_ECX + +INTRINSIC_XED_IFORM_SIDT_MEMs + struct w s + INVALID r XED_REG_IDTR + +INTRINSIC_XED_IFORM_SIDT_MEMs64 + struct w s64 + INVALID r XED_REG_IDTR + +INTRINSIC_XED_IFORM_INVLPG_MEMb + u8 r b + +INTRINSIC_XED_IFORM_SWAPGS + +INTRINSIC_XED_IFORM_RDTSCP + INVALID w XED_REG_EAX + INVALID w XED_REG_EDX + INVALID w XED_REG_ECX + INVALID r XED_REG_TSC + INVALID r XED_REG_TSCAUX + +INTRINSIC_XED_IFORM_SFENCE + +INTRINSIC_XED_IFORM_CLFLUSH_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_LFENCE + +INTRINSIC_XED_IFORM_MFENCE + +INTRINSIC_XED_IFORM_MOVHLPS_XMMq_XMMq + f32 w q + f32 r q + +INTRINSIC_XED_IFORM_MOVLPS_XMMq_MEMq + f32 w q + f32 r q + +INTRINSIC_XED_IFORM_MOVLPS_MEMq_XMMps + f32 w q + f32 r ps + +INTRINSIC_XED_IFORM_MOVLHPS_XMMq_XMMq + f32 w q + f32 r q + +INTRINSIC_XED_IFORM_MOVHPS_XMMq_MEMq + f32 w q + f32 r q + +INTRINSIC_XED_IFORM_MOVHPS_MEMq_XMMps + f32 w q + f32 r ps + +INTRINSIC_XED_IFORM_DAA + INVALID rw XED_REG_AL + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_DAS + INVALID rw XED_REG_AL + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_AAA + INVALID rw XED_REG_AL + INVALID rw XED_REG_AH + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_AAS + INVALID rw XED_REG_AL + INVALID rw XED_REG_AH + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_PUSHA + int w spw8 + INVALID r XED_REG_AX + INVALID r XED_REG_CX + INVALID r XED_REG_DX + INVALID r XED_REG_BX + INVALID r XED_REG_SP + INVALID r XED_REG_BP + INVALID r XED_REG_SI + INVALID r XED_REG_DI + int w spw8 + +INTRINSIC_XED_IFORM_PUSHAD + int w spw8 + INVALID r XED_REG_EAX + INVALID r XED_REG_ECX + INVALID r XED_REG_EDX + INVALID r XED_REG_EBX + INVALID r XED_REG_ESP + INVALID r XED_REG_EBP + INVALID r XED_REG_ESI + INVALID r XED_REG_EDI + int w spw8 + +INTRINSIC_XED_IFORM_POPA + int r spw8 + INVALID w XED_REG_AX + INVALID w XED_REG_CX + INVALID w XED_REG_DX + INVALID w XED_REG_BX + INVALID w XED_REG_BP + INVALID w XED_REG_SI + INVALID w XED_REG_DI + int r spw8 + +INTRINSIC_XED_IFORM_POPAD + int r spw8 + INVALID w XED_REG_EAX + INVALID w XED_REG_ECX + INVALID w XED_REG_EDX + INVALID w XED_REG_EBX + INVALID w XED_REG_EBP + INVALID w XED_REG_ESI + INVALID w XED_REG_EDI + int r spw8 + +INTRINSIC_XED_IFORM_BOUND_GPRv_MEMa16 + INVALID r GPRv_R + i16 r a16 + +INTRINSIC_XED_IFORM_BOUND_GPRv_MEMa32 + INVALID r GPRv_R + i32 r a32 + +INTRINSIC_XED_IFORM_ARPL_MEMw_GPR16 + i16 rw w + INVALID r GPR16_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ARPL_GPR16_GPR16 + INVALID rw GPR16_B + INVALID r GPR16_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MOVSXD_GPRv_MEMz + INVALID w GPRv_R + int r z + +INTRINSIC_XED_IFORM_MOVSXD_GPRv_GPRz + INVALID w GPRv_R + INVALID r GPRz_B + +INTRINSIC_XED_IFORM_REP_INSB + u8 cw b + INVALID r XED_REG_DX + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_INSB + u8 w b + INVALID r XED_REG_DX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_INSW + i16 cw w + INVALID r XED_REG_DX + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_INSW + i16 w w + INVALID r XED_REG_DX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_INSD + i32 cw d + INVALID r XED_REG_DX + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_INSD + i32 w d + INVALID r XED_REG_DX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_OUTSB + INVALID r XED_REG_DX + u8 cr b + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_OUTSB + INVALID r XED_REG_DX + u8 r b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_OUTSW + INVALID r XED_REG_DX + i16 cr w + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_OUTSW + INVALID r XED_REG_DX + i16 r w + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_OUTSD + INVALID r XED_REG_DX + i32 cr d + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_OUTSD + INVALID r XED_REG_DX + i32 r d + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JO_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JO_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JO_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNO_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNO_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNO_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JB_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JB_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JB_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNB_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNB_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNB_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JZ_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JZ_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JZ_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNZ_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNZ_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNZ_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JBE_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JBE_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JBE_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNBE_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNBE_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNBE_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JS_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JS_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JS_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNS_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNS_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNS_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JP_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JP_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JP_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNP_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNP_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNP_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JL_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JL_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JL_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNL_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNL_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNL_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JLE_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JLE_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JLE_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNLE_RELBRb + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNLE_RELBRz + INVALID rw XED_REG_EIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_JNLE_RELBRd + INVALID rw XED_REG_RIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_XCHG_MEMb_GPR8 + u8 rw b + INVALID rw GPR8_R + +INTRINSIC_XED_IFORM_XCHG_GPR8_GPR8 + INVALID rw GPR8_B + INVALID rw GPR8_R + +INTRINSIC_XED_IFORM_XCHG_MEMv_GPRv + int rw v + INVALID rw GPRv_R + +INTRINSIC_XED_IFORM_XCHG_GPRv_GPRv + INVALID rw GPRv_B + INVALID rw GPRv_R + +INTRINSIC_XED_IFORM_XCHG_GPRv_OrAX + INVALID rw GPRv_SB + INVALID rw OrAX + +INTRINSIC_XED_IFORM_LEA_GPRv_AGEN + INVALID w GPRv_R + +INTRINSIC_XED_IFORM_PAUSE + +INTRINSIC_XED_IFORM_CBW + INVALID w XED_REG_AX + INVALID r XED_REG_AL + +INTRINSIC_XED_IFORM_CDQE + INVALID w XED_REG_RAX + INVALID r XED_REG_EAX + +INTRINSIC_XED_IFORM_CWDE + INVALID w XED_REG_EAX + INVALID r XED_REG_AX + +INTRINSIC_XED_IFORM_CWD + INVALID w XED_REG_DX + INVALID r XED_REG_AX + +INTRINSIC_XED_IFORM_CQO + INVALID w XED_REG_RDX + INVALID r XED_REG_RAX + +INTRINSIC_XED_IFORM_CDQ + INVALID w XED_REG_EDX + INVALID r XED_REG_EAX + +INTRINSIC_XED_IFORM_CALL_FAR_MEMp2 + struct r p2 + int w spw2 + INVALID w rIP + int w spw2 + +INTRINSIC_XED_IFORM_CALL_FAR_PTRp_IMMw + int w spw2 + INVALID w XED_REG_EIP + int w spw2 + +INTRINSIC_XED_IFORM_FWAIT + +INTRINSIC_XED_IFORM_PUSHF + i16 w w + i16 w w + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_PUSHFD + i32 w d + i32 w d + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_PUSHFQ + i64 w q + i64 w q + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_POPF + i16 r w + i16 r w + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_POPFD + i32 r d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_POPFQ + i64 r q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_SAHF + INVALID r XED_REG_AH + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LAHF + INVALID w XED_REG_AH + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_MOVSB + u8 cw b + u8 cr b + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_MOVSB + u8 w b + u8 r b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_MOVSW + i16 cw w + i16 cr w + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_MOVSW + i16 w w + i16 r w + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_MOVSD + i32 cw d + i32 cr d + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_MOVSD + i32 w d + i32 r d + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_MOVSQ + i64 cw q + i64 cr q + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_MOVSQ + i64 w q + i64 r q + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REPE_CMPSB + u8 cr b + u8 cr b + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_CMPSB + u8 cr b + u8 cr b + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_CMPSB + u8 r b + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_REPE_CMPSW + i16 cr w + i16 cr w + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_CMPSW + i16 cr w + i16 cr w + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_CMPSW + i16 r w + i16 r w + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_REPE_CMPSD + i32 cr d + i32 cr d + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_CMPSD + i32 cr d + i32 cr d + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_CMPSD + i32 r d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_REPE_CMPSQ + i64 cr q + i64 cr q + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_CMPSQ + i64 cr q + i64 cr q + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_CMPSQ + i64 r q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_REP_STOSB + u8 cw b + INVALID r XED_REG_AL + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_STOSB + u8 w b + INVALID r XED_REG_AL + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_STOSW + i16 cw w + INVALID r XED_REG_AX + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_STOSW + i16 w w + INVALID r XED_REG_AX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_STOSD + i32 cw d + INVALID r XED_REG_EAX + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_STOSD + i32 w d + INVALID r XED_REG_EAX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_STOSQ + i64 cw q + INVALID r XED_REG_RAX + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_STOSQ + i64 w q + INVALID r XED_REG_RAX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_LODSB + INVALID cw XED_REG_AL + u8 cr b + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_LODSB + INVALID w XED_REG_AL + u8 r b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_LODSW + INVALID cw XED_REG_AX + i16 cr w + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_LODSW + INVALID w XED_REG_AX + i16 r w + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_LODSD + INVALID cw XED_REG_EAX + i32 cr d + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_LODSD + INVALID w XED_REG_EAX + i32 r d + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REP_LODSQ + INVALID cw XED_REG_RAX + i64 cr q + INVALID rcw ArCX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_LODSQ + INVALID w XED_REG_RAX + i64 r q + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_REPE_SCASB + INVALID r XED_REG_AL + u8 cr b + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_SCASB + INVALID r XED_REG_AL + u8 cr b + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_SCASB + INVALID r XED_REG_AL + u8 r b + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_REPE_SCASW + INVALID r XED_REG_AX + i16 cr w + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_SCASW + INVALID r XED_REG_AX + i16 cr w + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_SCASW + INVALID r XED_REG_AX + i16 r w + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_REPE_SCASD + INVALID r XED_REG_EAX + i32 cr d + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_SCASD + INVALID r XED_REG_EAX + i32 cr d + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_SCASD + INVALID r XED_REG_EAX + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_REPE_SCASQ + INVALID r XED_REG_RAX + i64 cr q + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_REPNE_SCASQ + INVALID r XED_REG_RAX + i64 cr q + INVALID rcw ArCX + INVALID rcw rFLAGS + +INTRINSIC_XED_IFORM_SCASQ + INVALID r XED_REG_RAX + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RET_NEAR_IMMw + int r spw + INVALID w rIP + int r spw + +INTRINSIC_XED_IFORM_RET_NEAR + int r spw + INVALID w rIP + int r spw + +INTRINSIC_XED_IFORM_LES_GPRz_MEMp + INVALID w GPRz_R + struct r p + INVALID w XED_REG_ES + +INTRINSIC_XED_IFORM_LDS_GPRz_MEMp + INVALID w GPRz_R + struct r p + INVALID w XED_REG_DS + +INTRINSIC_XED_IFORM_ENTER_IMMw_IMMb + int w spw + INVALID rw OrBP + int w spw + +INTRINSIC_XED_IFORM_LEAVE + int r v + INVALID rw OrBP + INVALID rw OrSP + +INTRINSIC_XED_IFORM_RET_FAR_IMMw + int r spw2 + INVALID w rIP + int r spw2 + +INTRINSIC_XED_IFORM_RET_FAR + int r spw2 + INVALID w rIP + int r spw2 + +INTRINSIC_XED_IFORM_INT3 + INVALID w rIP + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_INT_IMMb + INVALID w rIP + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_INTO + INVALID w XED_REG_EIP + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_IRET + int r spw5 + INVALID w rIP + int r spw5 + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_IRETD + int r spw5 + INVALID w rIP + int r spw5 + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_IRETQ + int r spw5 + INVALID w XED_REG_RIP + int r spw5 + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_AAM_IMMb + INVALID rw XED_REG_AL + INVALID w XED_REG_AH + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_AAD_IMMb + INVALID rw XED_REG_AL + INVALID rw XED_REG_AH + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SALC + INVALID w XED_REG_AL + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_XLAT + u8 r b + INVALID w XED_REG_AL + +INTRINSIC_XED_IFORM_LOOPNE_RELBRb + INVALID rw ArCX + INVALID rw rIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_LOOPE_RELBRb + INVALID rw ArCX + INVALID rw rIP + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_LOOP_RELBRb + INVALID rw ArCX + INVALID rw rIP + +INTRINSIC_XED_IFORM_JCXZ_RELBRb + INVALID r XED_REG_CX + INVALID rw XED_REG_IP + +INTRINSIC_XED_IFORM_JECXZ_RELBRb + INVALID r XED_REG_ECX + INVALID rw XED_REG_EIP + +INTRINSIC_XED_IFORM_JRCXZ_RELBRb + INVALID r XED_REG_RCX + INVALID rw XED_REG_RIP + +INTRINSIC_XED_IFORM_IN_AL_IMMb + INVALID w XED_REG_AL + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_IN_OeAX_IMMb + INVALID w OeAX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_IN_AL_DX + INVALID w XED_REG_AL + INVALID r XED_REG_DX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_IN_OeAX_DX + INVALID w OeAX + INVALID r XED_REG_DX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_OUT_IMMb_AL + INVALID r XED_REG_AL + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_OUT_IMMb_OeAX + INVALID r OeAX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_OUT_DX_AL + INVALID r XED_REG_DX + INVALID r XED_REG_AL + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_OUT_DX_OeAX + INVALID r XED_REG_DX + INVALID r OeAX + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_INT1 + INVALID w rIP + +INTRINSIC_XED_IFORM_HLT + +INTRINSIC_XED_IFORM_CMC + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_CLC + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_STC + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CLI + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_STI + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_CLD + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_STD + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LAR_GPRv_MEMw + INVALID cw GPRv_R + i16 r w + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LAR_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LSL_GPRv_MEMw + INVALID rw GPRv_R + i16 r w + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LSL_GPRv_GPRz + INVALID rw GPRv_R + INVALID r GPRz_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SYSCALL + INVALID w XED_REG_RIP + INVALID w XED_REG_RCX + INVALID w XED_REG_R11 + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CLTS + +INTRINSIC_XED_IFORM_SYSRET + INVALID w XED_REG_EIP + INVALID r XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SYSRET64 + INVALID w XED_REG_RIP + INVALID r XED_REG_RCX + INVALID r XED_REG_R11 + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_MOVUPS_XMMps_MEMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVUPS_XMMps_XMMps_0F10 + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVUPS_MEMps_XMMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVUPS_XMMps_XMMps_0F11 + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_UNPCKLPS_XMMps_MEMdq + f32 rw ps + i32 r dq + +INTRINSIC_XED_IFORM_UNPCKLPS_XMMps_XMMq + f32 rw ps + i64 r q + +INTRINSIC_XED_IFORM_UNPCKHPS_XMMps_MEMdq + f32 rw ps + i32 r dq + +INTRINSIC_XED_IFORM_UNPCKHPS_XMMps_XMMdq + f32 rw ps + i32 r dq + +INTRINSIC_XED_IFORM_MOVSS_XMMdq_MEMss + f32 w dq + f32 r ss + +INTRINSIC_XED_IFORM_MOVSS_XMMss_XMMss_0F10 + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_MOVSS_MEMss_XMMss + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_MOVSS_XMMss_XMMss_0F11 + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_MOVSLDUP_XMMps_MEMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVSLDUP_XMMps_XMMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVSHDUP_XMMps_MEMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVSHDUP_XMMps_XMMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVUPD_XMMpd_MEMpd + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10 + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVUPD_MEMpd_XMMpd + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11 + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVLPD_XMMsd_MEMq + f64 w sd + i64 r q + +INTRINSIC_XED_IFORM_MOVLPD_MEMq_XMMsd + i64 w q + f64 r sd + +INTRINSIC_XED_IFORM_UNPCKLPD_XMMpd_MEMdq + f64 rw pd + i32 r dq + +INTRINSIC_XED_IFORM_UNPCKLPD_XMMpd_XMMq + f64 rw pd + i64 r q + +INTRINSIC_XED_IFORM_UNPCKHPD_XMMpd_MEMdq + f64 rw pd + i32 r dq + +INTRINSIC_XED_IFORM_UNPCKHPD_XMMpd_XMMq + f64 rw pd + i64 r q + +INTRINSIC_XED_IFORM_MOVHPD_XMMsd_MEMq + f64 w sd + i64 r q + +INTRINSIC_XED_IFORM_MOVHPD_MEMq_XMMsd + i64 w q + f64 r sd + +INTRINSIC_XED_IFORM_MOVSD_XMM_XMMdq_MEMsd + f64 w dq + f64 r sd + +INTRINSIC_XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10 + f64 w sd + f64 r sd + +INTRINSIC_XED_IFORM_MOVSD_XMM_MEMsd_XMMsd + f64 w sd + f64 r sd + +INTRINSIC_XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11 + f64 w sd + f64 r sd + +INTRINSIC_XED_IFORM_MOVDDUP_XMMdq_MEMq + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_MOVDDUP_XMMdq_XMMq + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_MOV_CR_CR_GPR32 + INVALID w CR_R + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_MOV_CR_CR_GPR64 + INVALID w CR_R + INVALID r GPR64_B + +INTRINSIC_XED_IFORM_MOV_CR_GPR32_CR + INVALID w GPR32_B + INVALID r CR_R + +INTRINSIC_XED_IFORM_MOV_CR_GPR64_CR + INVALID w GPR64_B + INVALID r CR_R + +INTRINSIC_XED_IFORM_MOV_DR_DR_GPR32 + INVALID w DR_R + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_MOV_DR_DR_GPR64 + INVALID w DR_R + INVALID r GPR64_B + +INTRINSIC_XED_IFORM_MOV_DR_GPR32_DR + INVALID w GPR32_B + INVALID r DR_R + +INTRINSIC_XED_IFORM_MOV_DR_GPR64_DR + INVALID w GPR64_B + INVALID r DR_R + +INTRINSIC_XED_IFORM_WRMSR + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + INVALID r XED_REG_ECX + INVALID w XED_REG_MSRS + +INTRINSIC_XED_IFORM_RDTSC + INVALID w XED_REG_EAX + INVALID w XED_REG_EDX + INVALID r XED_REG_TSC + +INTRINSIC_XED_IFORM_RDMSR + INVALID w XED_REG_EAX + INVALID w XED_REG_EDX + INVALID r XED_REG_ECX + INVALID r XED_REG_MSRS + +INTRINSIC_XED_IFORM_RDPMC + INVALID w XED_REG_EAX + INVALID w XED_REG_EDX + INVALID r XED_REG_ECX + INVALID r XED_REG_MSRS + +INTRINSIC_XED_IFORM_SYSENTER + INVALID w XED_REG_EIP + INVALID w XED_REG_ESP + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SYSEXIT + INVALID w XED_REG_EIP + INVALID w XED_REG_ESP + INVALID r XED_REG_ECX + INVALID r XED_REG_EDX + +INTRINSIC_XED_IFORM_CMOVO_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVO_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNO_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNO_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVB_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVB_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNB_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNB_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVZ_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVZ_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNZ_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNZ_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVBE_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVBE_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNBE_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNBE_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_MOVMSKPS_GPR32_XMMps + INVALID w GPR32_R + f32 r ps + +INTRINSIC_XED_IFORM_SQRTPS_XMMps_MEMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_SQRTPS_XMMps_XMMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_RSQRTPS_XMMps_MEMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_RSQRTPS_XMMps_XMMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_RCPPS_XMMps_MEMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_RCPPS_XMMps_XMMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_ANDPS_XMMxud_MEMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_ANDPS_XMMxud_XMMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_ANDNPS_XMMxud_MEMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_ANDNPS_XMMxud_XMMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_ORPS_XMMxud_MEMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_ORPS_XMMxud_XMMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_XORPS_XMMxud_MEMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_XORPS_XMMxud_XMMxud + u32 rw xud + u32 r xud + +INTRINSIC_XED_IFORM_SQRTSS_XMMss_MEMss + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_SQRTSS_XMMss_XMMss + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_RSQRTSS_XMMss_MEMss + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_RSQRTSS_XMMss_XMMss + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_RCPSS_XMMss_MEMss + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_RCPSS_XMMss_XMMss + f32 w ss + f32 r ss + +INTRINSIC_XED_IFORM_MOVMSKPD_GPR32_XMMpd + INVALID w GPR32_R + f64 r pd + +INTRINSIC_XED_IFORM_SQRTPD_XMMpd_MEMpd + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_SQRTPD_XMMpd_XMMpd + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_ANDPD_XMMxuq_MEMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_ANDPD_XMMxuq_XMMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_ANDNPD_XMMxuq_MEMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_ANDNPD_XMMxuq_XMMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_ORPD_XMMxuq_MEMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_ORPD_XMMxuq_XMMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_XORPD_XMMxuq_MEMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_XORPD_XMMxuq_XMMxuq + u64 rw xuq + u64 r xuq + +INTRINSIC_XED_IFORM_SQRTSD_XMMsd_MEMsd + f64 w sd + f64 r sd + +INTRINSIC_XED_IFORM_SQRTSD_XMMsd_XMMsd + f64 w sd + f64 r sd + +INTRINSIC_XED_IFORM_PUNPCKLBW_MMXq_MEMd + u8 rw q + u8 r d + +INTRINSIC_XED_IFORM_PUNPCKLBW_MMXq_MMXd + u8 rw q + u8 r d + +INTRINSIC_XED_IFORM_PUNPCKLBW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKLBW_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKLWD_MMXq_MEMd + u16 rw q + u16 r d + +INTRINSIC_XED_IFORM_PUNPCKLWD_MMXq_MMXd + u16 rw q + u16 r d + +INTRINSIC_XED_IFORM_PUNPCKLWD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKLWD_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKLDQ_MMXq_MEMd + u32 rw q + u32 r d + +INTRINSIC_XED_IFORM_PUNPCKLDQ_MMXq_MMXd + u32 rw q + u32 r d + +INTRINSIC_XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKLDQ_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PACKSSWB_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PACKSSWB_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PACKSSWB_XMMdq_MEMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PACKSSWB_XMMdq_XMMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PCMPGTB_MMXq_MEMq + i8 rw q + i8 r q + +INTRINSIC_XED_IFORM_PCMPGTB_MMXq_MMXq + i8 rw q + i8 r q + +INTRINSIC_XED_IFORM_PCMPGTB_XMMdq_MEMdq + i8 rw dq + i8 r dq + +INTRINSIC_XED_IFORM_PCMPGTB_XMMdq_XMMdq + i8 rw dq + i8 r dq + +INTRINSIC_XED_IFORM_PCMPGTW_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PCMPGTW_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PCMPGTW_XMMdq_MEMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PCMPGTW_XMMdq_XMMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PCMPGTD_MMXq_MEMq + i32 rw q + i32 r q + +INTRINSIC_XED_IFORM_PCMPGTD_MMXq_MMXq + i32 rw q + i32 r q + +INTRINSIC_XED_IFORM_PCMPGTD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PCMPGTD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PACKUSWB_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PACKUSWB_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PACKUSWB_XMMdq_MEMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PACKUSWB_XMMdq_XMMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PSHUFW_MMXq_MEMq_IMMb + u16 w q + u16 r q + +INTRINSIC_XED_IFORM_PSHUFW_MMXq_MMXq_IMMb + u16 w q + u16 r q + +INTRINSIC_XED_IFORM_PCMPEQB_MMXq_MEMq + i8 rw q + i8 r q + +INTRINSIC_XED_IFORM_PCMPEQB_MMXq_MMXq + i8 rw q + i8 r q + +INTRINSIC_XED_IFORM_PCMPEQB_XMMdq_MEMdq + i8 rw dq + i8 r dq + +INTRINSIC_XED_IFORM_PCMPEQB_XMMdq_XMMdq + i8 rw dq + i8 r dq + +INTRINSIC_XED_IFORM_PCMPEQW_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PCMPEQW_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PCMPEQW_XMMdq_MEMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PCMPEQW_XMMdq_XMMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PCMPEQD_MMXq_MEMq + i32 rw q + i32 r q + +INTRINSIC_XED_IFORM_PCMPEQD_MMXq_MMXq + i32 rw q + i32 r q + +INTRINSIC_XED_IFORM_PCMPEQD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PCMPEQD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_EMMS + +INTRINSIC_XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_SETO_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETO_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNO_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNO_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETB_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETB_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNB_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNB_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETZ_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETZ_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNZ_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNZ_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETBE_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETBE_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNBE_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNBE_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CPUID + INVALID rw XED_REG_EAX + INVALID w XED_REG_EBX + INVALID crw XED_REG_ECX + INVALID w XED_REG_EDX + +INTRINSIC_XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8 + u8 rcw b + INVALID r GPR8_R + INVALID rcw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv + int rcw v + INVALID r GPRv_R + INVALID rcw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG_MEMb_GPR8 + u8 rcw b + INVALID r GPR8_R + INVALID rcw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG_GPR8_GPR8 + INVALID rcw GPR8_B + INVALID r GPR8_R + INVALID rcw XED_REG_AL + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG_MEMv_GPRv + int rcw v + INVALID r GPRv_R + INVALID rcw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPXCHG_GPRv_GPRv + INVALID rcw GPRv_B + INVALID r GPRv_R + INVALID rcw OrAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LSS_GPRv_MEMp2 + INVALID w GPRv_R + struct r p2 + INVALID w XED_REG_SS + +INTRINSIC_XED_IFORM_LFS_GPRv_MEMp2 + INVALID w GPRv_R + struct r p2 + INVALID w XED_REG_FS + +INTRINSIC_XED_IFORM_LGS_GPRv_MEMp2 + INVALID w GPRv_R + struct r p2 + INVALID w XED_REG_GS + +INTRINSIC_XED_IFORM_MOVZX_GPRv_MEMb + INVALID w GPRv_R + u8 r b + +INTRINSIC_XED_IFORM_MOVZX_GPRv_GPR8 + INVALID w GPRv_R + INVALID r GPR8_B + +INTRINSIC_XED_IFORM_MOVZX_GPRv_MEMw + INVALID w GPRv_R + i16 r w + +INTRINSIC_XED_IFORM_MOVZX_GPRv_GPR16 + INVALID w GPRv_R + INVALID r GPR16_B + +INTRINSIC_XED_IFORM_XADD_LOCK_MEMb_GPR8 + u8 rw b + INVALID rw GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XADD_LOCK_MEMv_GPRv + int rw v + INVALID rw GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XADD_MEMb_GPR8 + u8 rw b + INVALID rw GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XADD_GPR8_GPR8 + INVALID rw GPR8_B + INVALID rw GPR8_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XADD_MEMv_GPRv + int rw v + INVALID rw GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XADD_GPRv_GPRv + INVALID rw GPRv_B + INVALID rw GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CMPPS_XMMps_MEMps_IMMb + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_CMPPS_XMMps_XMMps_IMMb + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVNTI_MEMd_GPR32 + i32 w d + INVALID r GPR32_R + +INTRINSIC_XED_IFORM_MOVNTI_MEMq_GPR64 + i64 w q + INVALID r GPR64_R + +INTRINSIC_XED_IFORM_PINSRW_MMXq_MEMw_IMMb + u16 rw q + u16 r w + +INTRINSIC_XED_IFORM_PINSRW_MMXq_GPR32_IMMb + u16 rw q + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_PINSRW_XMMdq_MEMw_IMMb + i32 rw dq + i16 r w + +INTRINSIC_XED_IFORM_PINSRW_XMMdq_GPR32_IMMb + i32 rw dq + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_PEXTRW_GPR32_MMXq_IMMb + INVALID w GPR32_R + u16 r q + +INTRINSIC_XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb + INVALID w GPR32_R + i32 r dq + +INTRINSIC_XED_IFORM_SHUFPS_XMMps_MEMps_IMMb + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_SHUFPS_XMMps_XMMps_IMMb + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_CMPSS_XMMss_MEMss_IMMb + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_CMPSS_XMMss_XMMss_IMMb + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_PADDQ_MMXq_MEMq + u64 rw q + u64 r q + +INTRINSIC_XED_IFORM_PADDQ_MMXq_MMXq + u64 rw q + u64 r q + +INTRINSIC_XED_IFORM_PADDQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDQ_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULLW_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PMULLW_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PMULLW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULLW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMOVMSKB_GPR32_MMXq + INVALID w GPR32_R + i8 r q + +INTRINSIC_XED_IFORM_PMOVMSKB_GPR32_XMMdq + INVALID w GPR32_R + i8 r dq + +INTRINSIC_XED_IFORM_ADDSUBPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_ADDSUBPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVQ2DQ_XMMdq_MMXq + u64 w dq + u64 r q + +INTRINSIC_XED_IFORM_ADDSUBPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_ADDSUBPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVDQ2Q_MMXq_XMMq + u64 w q + u64 r q + +INTRINSIC_XED_IFORM_PAVGB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PAVGB_MMXq_MMXq + i8 rw q + i8 r q + +INTRINSIC_XED_IFORM_PAVGB_XMMdq_MEMdq + u8 rw dq + u8 r dq + +INTRINSIC_XED_IFORM_PAVGB_XMMdq_XMMdq + u8 rw dq + u8 r dq + +INTRINSIC_XED_IFORM_PAVGW_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PAVGW_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PAVGW_XMMdq_MEMdq + u16 rw dq + u16 r dq + +INTRINSIC_XED_IFORM_PAVGW_XMMdq_XMMdq + u16 rw dq + u16 r dq + +INTRINSIC_XED_IFORM_PMULHUW_MMXq_MEMq + u16 rw q + u16 r q + +INTRINSIC_XED_IFORM_PMULHUW_MMXq_MMXq + u16 rw q + u16 r q + +INTRINSIC_XED_IFORM_PMULHUW_XMMdq_MEMdq + u16 rw dq + u16 r dq + +INTRINSIC_XED_IFORM_PMULHUW_XMMdq_XMMdq + u16 rw dq + u16 r dq + +INTRINSIC_XED_IFORM_PMULHW_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PMULHW_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PMULHW_XMMdq_MEMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PMULHW_XMMdq_XMMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_MOVNTQ_MEMq_MMXq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd + i32 w dq + f64 r pd + +INTRINSIC_XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd + i32 w dq + f64 r pd + +INTRINSIC_XED_IFORM_MOVNTDQ_MEMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_CVTDQ2PD_XMMpd_MEMq + f64 w pd + i32 r q + +INTRINSIC_XED_IFORM_CVTDQ2PD_XMMpd_XMMq + f64 w pd + i32 r q + +INTRINSIC_XED_IFORM_CVTPD2DQ_XMMdq_MEMpd + i32 w dq + f64 r pd + +INTRINSIC_XED_IFORM_CVTPD2DQ_XMMdq_XMMpd + i32 w dq + f64 r pd + +INTRINSIC_XED_IFORM_PMULUDQ_MMXq_MEMq + u32 rw q + u32 r q + +INTRINSIC_XED_IFORM_PMULUDQ_MMXq_MMXq + u32 rw q + u32 r q + +INTRINSIC_XED_IFORM_PMULUDQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULUDQ_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMADDWD_MMXq_MEMq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PMADDWD_MMXq_MMXq + i16 rw q + i16 r q + +INTRINSIC_XED_IFORM_PMADDWD_XMMdq_MEMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PMADDWD_XMMdq_XMMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PSADBW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSADBW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSADBW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSADBW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_MASKMOVQ_MMXq_MMXq + u8 r q + i8 r q + i64 w q + +INTRINSIC_XED_IFORM_MASKMOVDQU_XMMdq_XMMdq + i32 r dq + i32 r dq + i32 w dq + +INTRINSIC_XED_IFORM_LDDQU_XMMpd_MEMdq + f64 w pd + i32 r dq + +INTRINSIC_XED_IFORM_INVD + +INTRINSIC_XED_IFORM_UD0_GPR32_MEMd + INVALID r GPR32_R + i32 r d + +INTRINSIC_XED_IFORM_UD0_GPR32_GPR32 + INVALID r GPR32_R + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_UD1_GPR32_MEMd + INVALID r GPR32_R + i32 r d + +INTRINSIC_XED_IFORM_UD1_GPR32_GPR32 + INVALID r GPR32_R + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_UD2 + +INTRINSIC_XED_IFORM_MOVAPS_XMMps_MEMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVAPS_XMMps_XMMps_0F28 + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVAPS_MEMps_XMMps + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_MOVAPS_XMMps_XMMps_0F29 + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_CVTPI2PS_XMMq_MEMq + f32 w q + i32 r q + +INTRINSIC_XED_IFORM_CVTPI2PS_XMMq_MMXq + f32 w q + i32 r q + +INTRINSIC_XED_IFORM_MOVNTPS_MEMdq_XMMps + i32 w dq + f32 r ps + +INTRINSIC_XED_IFORM_CVTTPS2PI_MMXq_MEMq + i32 w q + f32 r q + +INTRINSIC_XED_IFORM_CVTTPS2PI_MMXq_XMMq + i32 w q + f32 r q + +INTRINSIC_XED_IFORM_CVTPS2PI_MMXq_MEMq + i32 w q + f32 r q + +INTRINSIC_XED_IFORM_CVTPS2PI_MMXq_XMMq + i32 w q + f32 r q + +INTRINSIC_XED_IFORM_UCOMISS_XMMss_MEMss + f32 r ss + f32 r ss + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_UCOMISS_XMMss_XMMss + f32 r ss + f32 r ss + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_COMISS_XMMss_MEMss + f32 r ss + f32 r ss + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_COMISS_XMMss_XMMss + f32 r ss + f32 r ss + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_MEMd + f32 w ss + i32 r d + +INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_GPR32d + f32 w ss + i32 r d + +INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_MEMq + f32 w ss + i32 r q + +INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_GPR64q + f32 w ss + i32 r q + +INTRINSIC_XED_IFORM_CVTTSS2SI_GPR32d_MEMss + i32 w d + f32 r ss + +INTRINSIC_XED_IFORM_CVTTSS2SI_GPR32d_XMMss + i32 w d + f32 r ss + +INTRINSIC_XED_IFORM_CVTTSS2SI_GPR64q_MEMss + i64 w q + f32 r ss + +INTRINSIC_XED_IFORM_CVTTSS2SI_GPR64q_XMMss + i64 w q + f32 r ss + +INTRINSIC_XED_IFORM_CVTSS2SI_GPR32d_MEMss + i32 w d + f32 r ss + +INTRINSIC_XED_IFORM_CVTSS2SI_GPR32d_XMMss + i32 w d + f32 r ss + +INTRINSIC_XED_IFORM_CVTSS2SI_GPR64q_MEMss + i64 w q + f32 r ss + +INTRINSIC_XED_IFORM_CVTSS2SI_GPR64q_XMMss + i64 w q + f32 r ss + +INTRINSIC_XED_IFORM_MOVAPD_XMMpd_MEMpd + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28 + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVAPD_MEMpd_XMMpd + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29 + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_CVTPI2PD_XMMpd_MEMq + f64 w pd + i32 r q + +INTRINSIC_XED_IFORM_CVTPI2PD_XMMpd_MMXq + f64 w pd + i32 r q + +INTRINSIC_XED_IFORM_MOVNTPD_MEMdq_XMMpd + i32 w dq + f64 r pd + +INTRINSIC_XED_IFORM_CVTTPD2PI_MMXq_MEMpd + i32 w q + f64 r pd + +INTRINSIC_XED_IFORM_CVTTPD2PI_MMXq_XMMpd + i32 w q + f64 r pd + +INTRINSIC_XED_IFORM_CVTPD2PI_MMXq_MEMpd + i32 w q + f64 r pd + +INTRINSIC_XED_IFORM_CVTPD2PI_MMXq_XMMpd + i32 w q + f64 r pd + +INTRINSIC_XED_IFORM_UCOMISD_XMMsd_MEMsd + f64 r sd + f64 r sd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_UCOMISD_XMMsd_XMMsd + f64 r sd + f64 r sd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_COMISD_XMMsd_MEMsd + f64 r sd + f64 r sd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_COMISD_XMMsd_XMMsd + f64 r sd + f64 r sd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_MEMd + f64 w sd + i32 r d + +INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_GPR32d + f64 w sd + i32 r d + +INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_MEMq + f64 w sd + i64 r q + +INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_GPR64q + f64 w sd + i64 r q + +INTRINSIC_XED_IFORM_CVTTSD2SI_GPR32d_MEMsd + i32 w d + f64 r sd + +INTRINSIC_XED_IFORM_CVTTSD2SI_GPR32d_XMMsd + i32 w d + f64 r sd + +INTRINSIC_XED_IFORM_CVTTSD2SI_GPR64q_MEMsd + i64 w q + f64 r sd + +INTRINSIC_XED_IFORM_CVTTSD2SI_GPR64q_XMMsd + i64 w q + f64 r sd + +INTRINSIC_XED_IFORM_CVTSD2SI_GPR32d_MEMsd + i32 w d + f64 r sd + +INTRINSIC_XED_IFORM_CVTSD2SI_GPR32d_XMMsd + i32 w d + f64 r sd + +INTRINSIC_XED_IFORM_CVTSD2SI_GPR64q_MEMsd + i64 w q + f64 r sd + +INTRINSIC_XED_IFORM_CVTSD2SI_GPR64q_XMMsd + i64 w q + f64 r sd + +INTRINSIC_XED_IFORM_CMOVS_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVS_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNS_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNS_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVP_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVP_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNP_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNP_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVL_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVL_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNL_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNL_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVLE_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVLE_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNLE_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_CMOVNLE_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_ADDPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_ADDPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MULPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MULPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_CVTPS2PD_XMMpd_MEMq + f64 w pd + f32 r q + +INTRINSIC_XED_IFORM_CVTPS2PD_XMMpd_XMMq + f64 w pd + f32 r q + +INTRINSIC_XED_IFORM_CVTDQ2PS_XMMps_MEMdq + f32 w ps + i32 r dq + +INTRINSIC_XED_IFORM_CVTDQ2PS_XMMps_XMMdq + f32 w ps + i32 r dq + +INTRINSIC_XED_IFORM_SUBPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_SUBPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MINPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MINPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_DIVPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_DIVPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MAXPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MAXPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_ADDSS_XMMss_MEMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_ADDSS_XMMss_XMMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_MULSS_XMMss_MEMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_MULSS_XMMss_XMMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_CVTSS2SD_XMMsd_MEMss + f64 w sd + f32 r ss + +INTRINSIC_XED_IFORM_CVTSS2SD_XMMsd_XMMss + f64 w sd + f32 r ss + +INTRINSIC_XED_IFORM_CVTTPS2DQ_XMMdq_MEMps + i32 w dq + f32 r ps + +INTRINSIC_XED_IFORM_CVTTPS2DQ_XMMdq_XMMps + i32 w dq + f32 r ps + +INTRINSIC_XED_IFORM_SUBSS_XMMss_MEMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_SUBSS_XMMss_XMMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_MINSS_XMMss_MEMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_MINSS_XMMss_XMMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_DIVSS_XMMss_MEMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_DIVSS_XMMss_XMMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_MAXSS_XMMss_MEMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_MAXSS_XMMss_XMMss + f32 rw ss + f32 r ss + +INTRINSIC_XED_IFORM_ADDPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_ADDPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MULPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MULPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_CVTPD2PS_XMMps_MEMpd + f32 w ps + f64 r pd + +INTRINSIC_XED_IFORM_CVTPD2PS_XMMps_XMMpd + f32 w ps + f64 r pd + +INTRINSIC_XED_IFORM_CVTPS2DQ_XMMdq_MEMps + i32 w dq + f32 r ps + +INTRINSIC_XED_IFORM_CVTPS2DQ_XMMdq_XMMps + i32 w dq + f32 r ps + +INTRINSIC_XED_IFORM_SUBPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_SUBPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MINPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MINPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_DIVPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_DIVPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MAXPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MAXPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_ADDSD_XMMsd_MEMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_ADDSD_XMMsd_XMMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_MULSD_XMMsd_MEMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_MULSD_XMMsd_XMMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_CVTSD2SS_XMMss_MEMsd + f32 w ss + f64 r sd + +INTRINSIC_XED_IFORM_CVTSD2SS_XMMss_XMMsd + f32 w ss + f64 r sd + +INTRINSIC_XED_IFORM_SUBSD_XMMsd_MEMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_SUBSD_XMMsd_XMMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_MINSD_XMMsd_MEMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_MINSD_XMMsd_XMMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_DIVSD_XMMsd_MEMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_DIVSD_XMMsd_XMMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_MAXSD_XMMsd_MEMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_MAXSD_XMMsd_XMMsd + f64 rw sd + f64 r sd + +INTRINSIC_XED_IFORM_PUNPCKHBW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKHBW_MMXq_MMXd + i64 rw q + i32 r d + +INTRINSIC_XED_IFORM_PUNPCKHBW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKHBW_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKHWD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKHWD_MMXq_MMXd + i64 rw q + i32 r d + +INTRINSIC_XED_IFORM_PUNPCKHWD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKHWD_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKHDQ_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKHDQ_MMXq_MMXd + i64 rw q + i32 r d + +INTRINSIC_XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKHDQ_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PACKSSDW_MMXq_MEMq + i32 rw q + i32 r q + +INTRINSIC_XED_IFORM_PACKSSDW_MMXq_MMXq + i32 rw q + i32 r q + +INTRINSIC_XED_IFORM_PACKSSDW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PACKSSDW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_MOVD_XMMdq_MEMd + i32 w dq + i32 r d + +INTRINSIC_XED_IFORM_MOVD_XMMdq_GPR32 + i32 w dq + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_MOVD_MEMd_XMMd + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_MOVD_GPR32_XMMd + INVALID w GPR32_B + i32 r d + +INTRINSIC_XED_IFORM_MOVD_MMXq_MEMd + i64 w q + i32 r d + +INTRINSIC_XED_IFORM_MOVD_MMXq_GPR32 + i64 w q + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_MOVD_MEMd_MMXd + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_MOVD_GPR32_MMXd + INVALID w GPR32_B + i32 r d + +INTRINSIC_XED_IFORM_MOVQ_XMMdq_MEMq_0F6E + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_XMMdq_GPR64 + i32 w dq + INVALID r GPR64_B + +INTRINSIC_XED_IFORM_MOVQ_MEMq_XMMq_0F7E + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_GPR64_XMMq + INVALID w GPR64_B + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_MEMq_XMMq_0FD6 + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_XMMdq_XMMq_0FD6 + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_XMMdq_MEMq_0F7E + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_XMMdq_XMMq_0F7E + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_MMXq_MEMq_0F6E + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_MMXq_GPR64 + i64 w q + INVALID r GPR64_B + +INTRINSIC_XED_IFORM_MOVQ_MEMq_MMXq_0F7E + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_GPR64_MMXq + INVALID w GPR64_B + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_MMXq_MEMq_0F6F + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_MMXq_MMXq_0F6F + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_MEMq_MMXq_0F7F + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVQ_MMXq_MMXq_0F7F + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_MOVDQU_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_MOVDQU_MEMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMREAD_MEMq_GPR64 + i64 w q + INVALID r GPR64_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMREAD_GPR64_GPR64 + INVALID w GPR64_B + INVALID r GPR64_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMREAD_MEMd_GPR32 + i32 w d + INVALID r GPR32_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMREAD_GPR32_GPR32 + INVALID w GPR32_B + INVALID r GPR32_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMWRITE_GPR64_MEMq + INVALID r GPR64_R + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMWRITE_GPR64_GPR64 + INVALID r GPR64_R + INVALID r GPR64_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMWRITE_GPR32_MEMd + INVALID r GPR32_R + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMWRITE_GPR32_GPR32 + INVALID r GPR32_R + INVALID r GPR32_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_HADDPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_HADDPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_HSUBPD_XMMpd_MEMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_HSUBPD_XMMpd_XMMpd + f64 rw pd + f64 r pd + +INTRINSIC_XED_IFORM_MOVDQA_MEMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_MOVDQA_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_HADDPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_HADDPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_HSUBPS_XMMps_MEMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_HSUBPS_XMMps_XMMps + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_SETS_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETS_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNS_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNS_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETP_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETP_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNP_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNP_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETL_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETL_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNL_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNL_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETLE_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETLE_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNLE_MEMb + u8 w b + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_SETNLE_GPR8 + INVALID w GPR8_B + INVALID r rFLAGS + +INTRINSIC_XED_IFORM_RSM + INVALID w rIP + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHRD_MEMv_GPRv_IMMb + int rcw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_IMMb + INVALID rcw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHRD_MEMv_GPRv_CL + int rcw v + INVALID r GPRv_R + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_CL + INVALID rcw GPRv_B + INVALID r GPRv_R + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHLD_MEMv_GPRv_IMMb + int rcw v + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_IMMb + INVALID rcw GPRv_B + INVALID r GPRv_R + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHLD_MEMv_GPRv_CL + int rcw v + INVALID r GPRv_R + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_CL + INVALID rcw GPRv_B + INVALID r GPRv_R + INVALID r XED_REG_CL + INVALID cw rFLAGS + +INTRINSIC_XED_IFORM_MOVSX_GPRv_MEMb + INVALID w GPRv_R + u8 r b + +INTRINSIC_XED_IFORM_MOVSX_GPRv_GPR8 + INVALID w GPRv_R + INVALID r GPR8_B + +INTRINSIC_XED_IFORM_MOVSX_GPRv_MEMw + INVALID w GPRv_R + i16 r w + +INTRINSIC_XED_IFORM_MOVSX_GPRv_GPR16 + INVALID w GPRv_R + INVALID r GPR16_B + +INTRINSIC_XED_IFORM_BSWAP_GPRv + INVALID rw GPRv_SB + +INTRINSIC_XED_IFORM_PSUBUSB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBUSB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBUSB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBUSB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBUSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBUSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBUSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBUSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINUB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMINUB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMINUB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINUB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PAND_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PAND_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PAND_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PAND_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDUSB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDUSB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDUSB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDUSB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDUSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDUSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDUSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDUSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXUB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMAXUB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMAXUB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXUB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PANDN_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PANDN_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PANDN_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PANDN_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBSB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBSB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBSB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBSB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMINSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMINSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_POR_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_POR_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_POR_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_POR_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDSB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDSB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDSB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDSB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMAXSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMAXSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PXOR_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PXOR_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PXOR_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PXOR_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBD_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBQ_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBQ_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSUBQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSUBQ_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDW_XMMdq_MEMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PADDW_XMMdq_XMMdq + i16 rw dq + i16 r dq + +INTRINSIC_XED_IFORM_PADDD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDD_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PADDD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PADDD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHADDW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHADDW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHADDW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHADDW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHADDD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHADDD_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHADDD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHADDD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHADDSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHADDSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHADDSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHADDSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHSUBW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHSUBW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHSUBW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHSUBW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHSUBD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHSUBD_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHSUBD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHSUBD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHSUBSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHSUBSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PHSUBSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PHSUBSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMADDUBSW_MMXq_MEMq + i8 rw q + i8 r q + +INTRINSIC_XED_IFORM_PMADDUBSW_MMXq_MMXq + i8 rw q + i8 r q + +INTRINSIC_XED_IFORM_PMADDUBSW_XMMdq_MEMdq + i8 rw dq + i8 r dq + +INTRINSIC_XED_IFORM_PMADDUBSW_XMMdq_XMMdq + i8 rw dq + i8 r dq + +INTRINSIC_XED_IFORM_PMULHRSW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMULHRSW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMULHRSW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULHRSW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSHUFB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSHUFB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSHUFB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSHUFB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSIGNB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSIGNB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSIGNB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSIGNB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSIGNW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSIGNW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSIGNW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSIGNW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSIGND_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSIGND_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSIGND_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PSIGND_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PALIGNR_MMXq_MEMq_IMMb + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PALIGNR_MMXq_MMXq_IMMb + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PABSB_MMXq_MEMq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_PABSB_MMXq_MMXq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_PABSB_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PABSB_XMMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PABSW_MMXq_MEMq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_PABSW_MMXq_MMXq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_PABSW_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PABSW_XMMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PABSD_MMXq_MEMq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_PABSD_MMXq_MMXq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_PABSD_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PABSD_XMMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_POPCNT_GPRv_MEMv + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_POPCNT_GPRv_GPRv + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPGTQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PCMPGTQ_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_CRC32_GPRyy_MEMb + int rw y + u8 r b + +INTRINSIC_XED_IFORM_CRC32_GPRyy_GPR8b + int rw y + u8 r b + +INTRINSIC_XED_IFORM_CRC32_GPRyy_MEMv + int rw y + int r v + +INTRINSIC_XED_IFORM_CRC32_GPRyy_GPRv + int rw y + int r v + +INTRINSIC_XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb + f64 rw dq + f64 r dq + +INTRINSIC_XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb + f64 rw dq + f64 r dq + +INTRINSIC_XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb + f32 rw dq + f32 r dq + +INTRINSIC_XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb + f32 rw dq + f32 r dq + +INTRINSIC_XED_IFORM_BLENDVPD_XMMdq_MEMdq + f64 rw dq + f64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_BLENDVPD_XMMdq_XMMdq + f64 rw dq + f64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_BLENDVPS_XMMdq_MEMdq + f32 rw dq + f32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_BLENDVPS_XMMdq_XMMdq + f32 rw dq + f32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_PCMPEQQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PCMPEQQ_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_DPPD_XMMdq_MEMdq_IMMb + f64 rw dq + f64 r dq + +INTRINSIC_XED_IFORM_DPPD_XMMdq_XMMdq_IMMb + f64 rw dq + f64 r dq + +INTRINSIC_XED_IFORM_DPPS_XMMdq_MEMdq_IMMb + f32 rw dq + f32 r dq + +INTRINSIC_XED_IFORM_DPPS_XMMdq_XMMdq_IMMb + f32 rw dq + f32 r dq + +INTRINSIC_XED_IFORM_MOVNTDQA_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb + i32 w d + f32 r ps + +INTRINSIC_XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb + i32 w d + i32 r dq + +INTRINSIC_XED_IFORM_INSERTPS_XMMps_MEMd_IMMb + f32 rw ps + i32 r d + +INTRINSIC_XED_IFORM_INSERTPS_XMMps_XMMps_IMMb + f32 rw ps + f32 r ps + +INTRINSIC_XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb + u8 rw dq + u8 r dq + +INTRINSIC_XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb + u8 rw dq + u8 r dq + +INTRINSIC_XED_IFORM_PACKUSDW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PACKUSDW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PBLENDVB_XMMdq_MEMdq + i32 rw dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_PBLENDVB_XMMdq_XMMdq + i32 rw dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb + u8 w b + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb + i32 w d + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb + i16 w w + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb + INVALID w GPR32_B + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb + i64 w q + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb + i64 w q + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb + i32 w d + i32 r dq + +INTRINSIC_XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb + i32 w d + i32 r dq + +INTRINSIC_XED_IFORM_PINSRB_XMMdq_MEMb_IMMb + i32 rw dq + u8 r b + +INTRINSIC_XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb + i32 rw dq + i32 r d + +INTRINSIC_XED_IFORM_PINSRD_XMMdq_MEMd_IMMb + i32 rw dq + i32 r d + +INTRINSIC_XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb + i32 rw dq + i32 r d + +INTRINSIC_XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb + i32 rw dq + i64 r q + +INTRINSIC_XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb + f64 w pd + f64 r pd + +INTRINSIC_XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb + f32 w ps + f32 r ps + +INTRINSIC_XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_PTEST_XMMdq_MEMdq + i32 r dq + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PTEST_XMMdq_XMMdq + i32 r dq + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PHMINPOSUW_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PHMINPOSUW_XMMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXSB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXSB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXSD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXSD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXUD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXUD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXUW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMAXUW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINSB_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINSB_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINSD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINSD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINUD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINUD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINUW_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMINUW_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULLD_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULLD_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULDQ_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMULDQ_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PMOVSXBW_XMMdq_MEMq + i16 w dq + i8 r q + +INTRINSIC_XED_IFORM_PMOVSXBW_XMMdq_XMMq + i16 w dq + i8 r q + +INTRINSIC_XED_IFORM_PMOVSXBD_XMMdq_MEMd + i32 w dq + i8 r d + +INTRINSIC_XED_IFORM_PMOVSXBD_XMMdq_XMMd + i32 w dq + i8 r d + +INTRINSIC_XED_IFORM_PMOVSXBQ_XMMdq_MEMw + i64 w dq + i8 r w + +INTRINSIC_XED_IFORM_PMOVSXBQ_XMMdq_XMMw + i64 w dq + i8 r w + +INTRINSIC_XED_IFORM_PMOVSXWD_XMMdq_MEMq + i32 w dq + i16 r q + +INTRINSIC_XED_IFORM_PMOVSXWD_XMMdq_XMMq + i32 w dq + i16 r q + +INTRINSIC_XED_IFORM_PMOVSXWQ_XMMdq_MEMd + i64 w dq + i16 r d + +INTRINSIC_XED_IFORM_PMOVSXWQ_XMMdq_XMMd + i64 w dq + i16 r d + +INTRINSIC_XED_IFORM_PMOVSXDQ_XMMdq_MEMq + i64 w dq + i32 r q + +INTRINSIC_XED_IFORM_PMOVSXDQ_XMMdq_XMMq + i64 w dq + i32 r q + +INTRINSIC_XED_IFORM_PMOVZXBW_XMMdq_MEMq + u16 w dq + u8 r q + +INTRINSIC_XED_IFORM_PMOVZXBW_XMMdq_XMMq + u16 w dq + u8 r q + +INTRINSIC_XED_IFORM_PMOVZXBD_XMMdq_MEMd + u32 w dq + u8 r d + +INTRINSIC_XED_IFORM_PMOVZXBD_XMMdq_XMMd + u32 w dq + u8 r d + +INTRINSIC_XED_IFORM_PMOVZXBQ_XMMdq_MEMw + u64 w dq + u8 r w + +INTRINSIC_XED_IFORM_PMOVZXBQ_XMMdq_XMMw + u64 w dq + u8 r w + +INTRINSIC_XED_IFORM_PMOVZXWD_XMMdq_MEMq + u32 w dq + u16 r q + +INTRINSIC_XED_IFORM_PMOVZXWD_XMMdq_XMMq + u32 w dq + u16 r q + +INTRINSIC_XED_IFORM_PMOVZXWQ_XMMdq_MEMd + u64 w dq + u16 r d + +INTRINSIC_XED_IFORM_PMOVZXWQ_XMMdq_XMMd + u64 w dq + u16 r d + +INTRINSIC_XED_IFORM_PMOVZXDQ_XMMdq_MEMq + u64 w dq + u32 r q + +INTRINSIC_XED_IFORM_PMOVZXDQ_XMMdq_XMMq + u64 w dq + u32 r q + +INTRINSIC_XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb + i32 r dq + i32 r dq + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb + i32 r dq + i32 r dq + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb + i32 r dq + i32 r dq + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb + i32 r dq + i32 r dq + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb + i32 r dq + i32 r dq + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb + i32 r dq + i32 r dq + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XGETBV + INVALID r XED_REG_ECX + INVALID w XED_REG_EDX + INVALID w XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSETBV + INVALID r XED_REG_ECX + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID w XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSAVE_MEMmxsave + struct rw mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XRSTOR_MEMmxsave + struct r mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSAVE64_MEMmxsave + struct rw mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XRSTOR64_MEMmxsave + struct r mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_MOVBE_GPRv_MEMv + INVALID w GPRv_R + int r v + +INTRINSIC_XED_IFORM_MOVBE_MEMv_GPRv + int w v + INVALID r GPRv_R + +INTRINSIC_XED_IFORM_GETSEC + INVALID rcw XED_REG_EAX + INVALID r XED_REG_EBX + +INTRINSIC_XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_AESENC_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESENC_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESENCLAST_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESENCLAST_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESDEC_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESDEC_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESDECLAST_XMMdq_XMMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESDECLAST_XMMdq_MEMdq + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_AESIMC_XMMdq_XMMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_AESIMC_XMMdq_MEMdq + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_INVEPT_GPR64_MEMdq + INVALID r GPR64_R + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INVEPT_GPR32_MEMdq + INVALID r GPR32_R + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INVVPID_GPR64_MEMdq + INVALID r GPR64_R + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_INVVPID_GPR32_MEMdq + INVALID r GPR32_R + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCHW_0F0Dr1 + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCHW_0F0Dr3 + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr4 + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr5 + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr6 + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr7 + i64 r mprefetch + +INTRINSIC_XED_IFORM_XSTORE + u8 w b + INVALID r OrCX + INVALID rw OrDX + INVALID w OrAX + +INTRINSIC_XED_IFORM_REP_XSTORE + u8 w b + INVALID rw OrCX + INVALID rw OrDX + INVALID w OrAX + +INTRINSIC_XED_IFORM_REP_XCRYPTECB + u8 w b + INVALID rw OrCX + INVALID r OrDX + INVALID r OrBX + u8 cr b + +INTRINSIC_XED_IFORM_REP_XCRYPTCBC + u8 w b + INVALID rw OrCX + INVALID r OrDX + INVALID r OrBX + INVALID r ArAX + u8 cr b + +INTRINSIC_XED_IFORM_REP_XCRYPTCTR + u8 w b + INVALID rw OrCX + INVALID r OrDX + INVALID r OrBX + INVALID r ArAX + u8 cr b + +INTRINSIC_XED_IFORM_REP_XCRYPTCFB + u8 w b + INVALID rw OrCX + INVALID r OrDX + INVALID r OrBX + INVALID r ArAX + u8 cr b + +INTRINSIC_XED_IFORM_REP_XCRYPTOFB + u8 w b + INVALID rw OrCX + INVALID r OrDX + INVALID r OrBX + INVALID r ArAX + u8 cr b + +INTRINSIC_XED_IFORM_REP_XSHA1 + INVALID rcw ArAX + INVALID rcw OrCX + u8 w b + u8 r b + +INTRINSIC_XED_IFORM_REP_XSHA256 + INVALID rcw ArAX + INVALID rcw OrCX + u8 w b + u8 r b + +INTRINSIC_XED_IFORM_REP_MONTMUL + INVALID rw XED_REG_EAX + INVALID rw XED_REG_ECX + INVALID w XED_REG_EDX + struct rw pmmsz16 + +INTRINSIC_XED_IFORM_FEMMS + +INTRINSIC_XED_IFORM_PI2FW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PI2FW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PI2FD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PI2FD_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PF2IW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PF2IW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PF2ID_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PF2ID_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFNACC_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFNACC_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFPNACC_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFPNACC_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFCMPGE_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFCMPGE_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFMIN_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFMIN_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRCP_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRCP_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRSQRT_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRSQRT_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFSUB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFSUB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFADD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFADD_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFCMPGT_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFCMPGT_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFMAX_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFMAX_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRCPIT1_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRCPIT1_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRSQIT1_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRSQIT1_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFSUBR_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFSUBR_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFACC_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFACC_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFCMPEQ_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFCMPEQ_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFMUL_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFMUL_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRCPIT2_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PFRCPIT2_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMULHRW_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PMULHRW_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSWAPD_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PSWAPD_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PAVGUSB_MMXq_MEMq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_PAVGUSB_MMXq_MMXq + i64 rw q + i64 r q + +INTRINSIC_XED_IFORM_SYSCALL_AMD + INVALID w rIP + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SYSRET_AMD + INVALID w XED_REG_EIP + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMRUN_ArAX + INVALID r ArAX + +INTRINSIC_XED_IFORM_VMMCALL + +INTRINSIC_XED_IFORM_VMLOAD_ArAX + INVALID r ArAX + +INTRINSIC_XED_IFORM_VMSAVE + +INTRINSIC_XED_IFORM_STGI + +INTRINSIC_XED_IFORM_CLGI + +INTRINSIC_XED_IFORM_SKINIT_EAX + INVALID r XED_REG_EAX + +INTRINSIC_XED_IFORM_INVLPGA_ArAX_ECX + INVALID r ArAX + INVALID r XED_REG_ECX + +INTRINSIC_XED_IFORM_EXTRQ_XMMq_IMMb_IMMb + i64 w q + +INTRINSIC_XED_IFORM_EXTRQ_XMMq_XMMdq + i64 w q + i32 r dq + +INTRINSIC_XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_INSERTQ_XMMq_XMMdq + i64 w q + i32 r dq + +INTRINSIC_XED_IFORM_MOVNTSD_MEMq_XMMq + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_MOVNTSS_MEMd_XMMd + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_CLZERO + INVALID r ArAX + +INTRINSIC_XED_IFORM_MONITORX + INVALID r XED_REG_EAX + INVALID r XED_REG_ECX + INVALID r XED_REG_EDX + +INTRINSIC_XED_IFORM_MWAITX + INVALID rw XED_REG_EAX + INVALID r XED_REG_ECX + +INTRINSIC_XED_IFORM_MCOMMIT + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_RDPRU + i32 w d + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_PSMASH_RAX + INVALID rw XED_REG_RAX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_PVALIDATE_RAX_ECX_EDX + INVALID rw XED_REG_RAX + INVALID r XED_REG_ECX + INVALID r XED_REG_EDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_RMPADJUST_RAX_RCX_RDX + INVALID rw XED_REG_RAX + INVALID r XED_REG_RCX + INVALID r XED_REG_RDX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_RMPUPDATE_RAX_RCX + INVALID rw XED_REG_RAX + INVALID r XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BNDMK_BND_AGEN + INVALID w BND_R + +INTRINSIC_XED_IFORM_BNDCL_BND_AGEN + INVALID r BND_R + +INTRINSIC_XED_IFORM_BNDCL_BND_GPR64 + INVALID r BND_R + INVALID r GPR64_B + +INTRINSIC_XED_IFORM_BNDCL_BND_GPR32 + INVALID r BND_R + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_BNDCU_BND_AGEN + INVALID r BND_R + +INTRINSIC_XED_IFORM_BNDCU_BND_GPR64 + INVALID r BND_R + INVALID r GPR64_B + +INTRINSIC_XED_IFORM_BNDCU_BND_GPR32 + INVALID r BND_R + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_BNDCN_BND_AGEN + INVALID r BND_R + +INTRINSIC_XED_IFORM_BNDCN_BND_GPR64 + INVALID r BND_R + INVALID r GPR64_B + +INTRINSIC_XED_IFORM_BNDCN_BND_GPR32 + INVALID r BND_R + INVALID r GPR32_B + +INTRINSIC_XED_IFORM_BNDMOV_BND_BND + INVALID w BND_R + INVALID r BND_B + +INTRINSIC_XED_IFORM_BNDMOV_BND_MEMq + INVALID w BND_R + u32 r q + +INTRINSIC_XED_IFORM_BNDMOV_BND_MEMdq + INVALID w BND_R + u64 r dq + +INTRINSIC_XED_IFORM_BNDMOV_MEMq_BND + u32 w q + INVALID r BND_R + +INTRINSIC_XED_IFORM_BNDMOV_MEMdq_BND + u64 w dq + INVALID r BND_R + +INTRINSIC_XED_IFORM_BNDLDX_BND_MEMbnd32 + INVALID w BND_R + u32 r bnd32 + +INTRINSIC_XED_IFORM_BNDLDX_BND_MEMbnd64 + INVALID w BND_R + u64 r bnd64 + +INTRINSIC_XED_IFORM_BNDSTX_MEMbnd32_BND + u32 w bnd32 + INVALID r BND_R + +INTRINSIC_XED_IFORM_BNDSTX_MEMbnd64_BND + u64 w bnd64 + INVALID r BND_R + +INTRINSIC_XED_IFORM_CLRSSBSY_MEMu64 + u64 rw q + +INTRINSIC_XED_IFORM_ENDBR32 + +INTRINSIC_XED_IFORM_ENDBR64 + +INTRINSIC_XED_IFORM_INCSSPD_GPR32u8 + u8 r d + u64 rw u64 + +INTRINSIC_XED_IFORM_INCSSPQ_GPR64u8 + u8 r q + u64 rw u64 + +INTRINSIC_XED_IFORM_RDSSPD_GPR32u32 + u32 w d + u64 r u64 + +INTRINSIC_XED_IFORM_RDSSPQ_GPR64u64 + u64 w q + u64 r u64 + +INTRINSIC_XED_IFORM_RSTORSSP_MEMu64 + u64 rw q + u64 w u64 + +INTRINSIC_XED_IFORM_SAVEPREVSSP + u64 r u64 + +INTRINSIC_XED_IFORM_SETSSBSY + +INTRINSIC_XED_IFORM_WRSSD_MEMu32_GPR32u32 + u32 w d + u32 r d + +INTRINSIC_XED_IFORM_WRSSQ_MEMu64_GPR64u64 + u64 w q + u64 r q + +INTRINSIC_XED_IFORM_WRUSSD_MEMu32_GPR32u32 + u32 w d + u32 r d + +INTRINSIC_XED_IFORM_WRUSSQ_MEMu64_GPR64u64 + u64 w q + u64 r q + +INTRINSIC_XED_IFORM_RDRAND_GPRv + INVALID w GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA + i32 rw dq + i32 r dq + +INTRINSIC_XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA + i32 rw dq + i32 r dq + u8 r dq + +INTRINSIC_XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA + i32 rw dq + i32 r dq + u8 r dq + +INTRINSIC_XED_IFORM_XSAVEOPT_MEMmxsave + struct rw mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSAVEOPT64_MEMmxsave + struct rw mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSAVES_MEMmxsave + struct w mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSAVES64_MEMmxsave + struct w mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XRSTORS_MEMmxsave + struct r mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XRSTORS64_MEMmxsave + struct r mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSAVEC_MEMmxsave + struct w mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_XSAVEC64_MEMmxsave + struct w mxsave + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_XCR0 + +INTRINSIC_XED_IFORM_CLFLUSHOPT_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_RDSEED_GPRv + INVALID w GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_RDFSBASE_GPRy + INVALID w GPRy_B + int r y + +INTRINSIC_XED_IFORM_RDGSBASE_GPRy + INVALID w GPRy_B + int r y + +INTRINSIC_XED_IFORM_WRFSBASE_GPRy + INVALID r GPRy_B + int w y + +INTRINSIC_XED_IFORM_WRGSBASE_GPRy + INVALID r GPRy_B + int w y + +INTRINSIC_XED_IFORM_CLAC + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_STAC + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ENCLU + INVALID r XED_REG_EAX + INVALID crw XED_REG_RBX + INVALID crw XED_REG_RCX + INVALID crw XED_REG_RDX + +INTRINSIC_XED_IFORM_ENCLS + INVALID r XED_REG_EAX + INVALID crw XED_REG_RBX + INVALID crw XED_REG_RCX + INVALID crw XED_REG_RDX + +INTRINSIC_XED_IFORM_RDPID_GPR32u32 + u32 w d + u32 r d + +INTRINSIC_XED_IFORM_RDPID_GPR64u64 + u64 w q + u32 r d + +INTRINSIC_XED_IFORM_PTWRITE_GPRy + INVALID r GPRy_B + +INTRINSIC_XED_IFORM_PTWRITE_MEMy + int r y + +INTRINSIC_XED_IFORM_MOVDIR64B_GPRa_MEM + INVALID r A_GPR_R + u32 r zd + i32 w zd + +INTRINSIC_XED_IFORM_MOVDIRI_MEMu32_GPR32u32 + u32 w d + u32 r d + +INTRINSIC_XED_IFORM_MOVDIRI_MEMu64_GPR64u64 + u64 w q + u64 r q + +INTRINSIC_XED_IFORM_TPAUSE_GPR32u32 + u32 r d + u32 r d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TPAUSE_GPR64u64 + u64 r q + u32 r d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_UMONITOR_GPRa + INVALID r A_GPR_B + +INTRINSIC_XED_IFORM_UMWAIT_GPR32 + u32 r d + u32 r d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_UMWAIT_GPR64 + u64 r q + u32 r d + u32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_CLDEMOTE_MEMu8 + u8 r b + +INTRINSIC_XED_IFORM_ENCLV + u32 r d + u64 crw q + u64 crw q + u64 crw q + +INTRINSIC_XED_IFORM_TZCNT_GPRv_MEMv + INVALID w GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TZCNT_GPRv_GPRv + INVALID w GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BSF_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BSF_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMFUNC + INVALID r XED_REG_EAX + +INTRINSIC_XED_IFORM_INVPCID_GPR64_MEMdq + INVALID r GPR64_R + i32 r dq + +INTRINSIC_XED_IFORM_INVPCID_GPR32_MEMdq + INVALID r GPR32_R + i32 r dq + +INTRINSIC_XED_IFORM_LZCNT_GPRv_MEMv + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LZCNT_GPRv_GPRv + int w v + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BSR_GPRv_MEMv + INVALID cw GPRv_R + int r v + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BSR_GPRv_GPRv + INVALID cw GPRv_R + INVALID r GPRv_B + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XBEGIN_RELBRz + INVALID rw rIP + INVALID cw XED_REG_EAX + +INTRINSIC_XED_IFORM_XEND + +INTRINSIC_XED_IFORM_XABORT_IMMb + INVALID rcw XED_REG_EAX + +INTRINSIC_XED_IFORM_XTEST + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR32d_GPR32d + i32 rw d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR32d_MEMd + i32 rw d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR64q_GPR64q + i64 rw q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADCX_GPR64q_MEMq + i64 rw q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR32d_GPR32d + i32 rw d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR32d_MEMd + i32 rw d + i32 r d + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR64q_GPR64q + i64 rw q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_ADOX_GPR64q_MEMq + i64 rw q + i64 r q + INVALID rw rFLAGS + +INTRINSIC_XED_IFORM_RDPKRU + INVALID w XED_REG_EDX + INVALID w XED_REG_EAX + INVALID r XED_REG_ECX + +INTRINSIC_XED_IFORM_WRPKRU + INVALID r XED_REG_EDX + INVALID r XED_REG_EAX + INVALID r XED_REG_ECX + +INTRINSIC_XED_IFORM_CLWB_MEMmprefetch + i64 r mprefetch + +INTRINSIC_XED_IFORM_PREFETCHWT1_MEMu8 + u8 r b + +INTRINSIC_XED_IFORM_WBINVD + +INTRINSIC_XED_IFORM_WBNOINVD + +INTRINSIC_XED_IFORM_PCONFIG + u32 rw d + u32 crw d + u32 crw d + u32 crw d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8 + u8 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8 + u8 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8 + u8 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8 + u8 rw dq + u64 r dq + +INTRINSIC_XED_IFORM_GF2P8MULB_XMMu8_XMMu8 + u8 rw dq + u8 r dq + +INTRINSIC_XED_IFORM_GF2P8MULB_XMMu8_MEMu8 + u8 rw dq + u8 r dq + +INTRINSIC_XED_IFORM_ENQCMD_GPRa_MEMu32 + INVALID r A_GPR_R + u32 r zd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ENQCMDS_GPRa_MEMu32 + INVALID r A_GPR_R + u32 r zd + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_XRESLDTRK + +INTRINSIC_XED_IFORM_XSUSLDTRK + +INTRINSIC_XED_IFORM_SERIALIZE + +INTRINSIC_XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i1 w dq + i1 r dq + i1 r dq + i1 r dq + +INTRINSIC_XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i1 w dq + i1 r dq + i1 r dq + i1 r dq + +INTRINSIC_XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + i1 w dq + i1 r dq + i1 r dq + i1 r dq + +INTRINSIC_XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + i1 w qq + i1 r qq + i1 r qq + i1 r qq + +INTRINSIC_XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + i1 w qq + i1 r qq + i1 r qq + i1 r qq + +INTRINSIC_XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + i1 w qq + i1 r qq + i1 r qq + i1 r qq + +INTRINSIC_XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb +VL128 + u8 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb +VL128 + u8 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb +VL128 + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb +VL128 + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb +VL128 + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb +VL128 + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb +VL128 + u64 w dq + u64 r dq + +INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb +VL128 + u64 w dq + u64 r dq + +INTRINSIC_XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VFRCZPS_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VFRCZPS_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VFRCZPS_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VFRCZPS_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VFRCZPD_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VFRCZPD_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VFRCZPD_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VFRCZPD_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VFRCZSS_XMMdq_MEMd +VL128 + f32 w dq + f32 r d + +INTRINSIC_XED_IFORM_VFRCZSS_XMMdq_XMMd +VL128 + f32 w dq + f32 r d + +INTRINSIC_XED_IFORM_VFRCZSD_XMMdq_MEMq +VL128 + f64 w dq + f64 r q + +INTRINSIC_XED_IFORM_VFRCZSD_XMMdq_XMMq +VL128 + f64 w dq + f64 r q + +INTRINSIC_XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPHADDBW_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHADDBW_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHADDBD_XMMdq_MEMdq +VL128 + i32 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHADDBD_XMMdq_XMMdq +VL128 + i32 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHADDBQ_XMMdq_MEMdq +VL128 + i64 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHADDBQ_XMMdq_XMMdq +VL128 + i64 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHADDWD_XMMdq_MEMdq +VL128 + i32 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDWD_XMMdq_XMMdq +VL128 + i32 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDWQ_XMMdq_MEMdq +VL128 + i64 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDWQ_XMMdq_XMMdq +VL128 + i64 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDUBW_XMMdq_MEMdq +VL128 + u16 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPHADDUBW_XMMdq_XMMdq +VL128 + u16 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPHADDUBD_XMMdq_MEMdq +VL128 + u32 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPHADDUBD_XMMdq_XMMdq +VL128 + u32 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPHADDUBQ_XMMdq_MEMdq +VL128 + u64 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPHADDUBQ_XMMdq_XMMdq +VL128 + u64 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPHADDUWD_XMMdq_MEMdq +VL128 + u32 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPHADDUWD_XMMdq_XMMdq +VL128 + u32 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPHADDUWQ_XMMdq_MEMdq +VL128 + u64 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPHADDUWQ_XMMdq_XMMdq +VL128 + u64 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPHSUBBW_XMMdq_MEMdq +VL128 + i16 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHSUBBW_XMMdq_XMMdq +VL128 + i16 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPHSUBWD_XMMdq_MEMdq +VL128 + i32 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHSUBWD_XMMdq_XMMdq +VL128 + i32 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHSUBDQ_XMMdq_MEMdq +VL128 + i64 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPHSUBDQ_XMMdq_XMMdq +VL128 + i64 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPHADDDQ_XMMdq_MEMdq +VL128 + i64 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPHADDDQ_XMMdq_XMMdq +VL128 + i64 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPHADDUDQ_XMMdq_MEMdq +VL128 + u64 w dq + u32 r dq + +INTRINSIC_XED_IFORM_VPHADDUDQ_XMMdq_XMMdq +VL128 + u64 w dq + u32 r dq + +INTRINSIC_XED_IFORM_BEXTR_XOP_GPR32d_MEMd_IMMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_XOP_GPRyy_MEMy_IMMd +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_XOP_GPR32d_GPR32d_IMMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_XOP_GPRyy_GPRyy_IMMd +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCFILL_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCFILL_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCFILL_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCFILL_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSFILL_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSFILL_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSFILL_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSFILL_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCS_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCS_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCS_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCS_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TZMSK_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TZMSK_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TZMSK_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_TZMSK_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCIC_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCIC_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCIC_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCIC_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSIC_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSIC_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSIC_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSIC_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_T1MSKC_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_T1MSKC_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_T1MSKC_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_T1MSKC_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCMSK_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCMSK_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCMSK_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCMSK_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCI_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCI_VGPRyy_MEMy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCI_VGPR32d_GPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLCI_VGPRyy_GPRyy +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LLWPCB_GPRyy +VL128 + int w y + +INTRINSIC_XED_IFORM_SLWPCB_GPRyy +VL128 + int w y + +INTRINSIC_XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd +VL128 + int w y + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LWPINS_VGPRyy_GPR32y_IMMd +VL128 + int w y + int r y + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd +VL128 + int w y + i32 r d + +INTRINSIC_XED_IFORM_LWPVAL_VGPRyy_GPR32y_IMMd +VL128 + int w y + int r y + +INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd + f32 w dq + f32 r d + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq + f64 w dq + f64 r q + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VCOMISD_XMMq_MEMq + f64 r q + f64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCOMISD_XMMq_XMMq + f64 r q + f64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCOMISS_XMMd_MEMd + f32 r d + f32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCOMISS_XMMd_XMMd + f32 r d + f32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMdq_MEMq +VL128 + f64 w dq + i32 r q + +INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMdq_XMMq +VL128 + f64 w dq + i32 r q + +INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq +VL256 + f64 w qq + i32 r dq + +INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq +VL256 + f64 w qq + i32 r dq + +INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq +VL128 + f32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq +VL128 + f32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq +VL256 + f32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq +VL256 + f32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq +VL128 + i32 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq +VL128 + i32 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq +VL256 + i32 w dq + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq +VL256 + i32 w dq + f64 r qq + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq +VL128 + i32 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq +VL128 + i32 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq +VL256 + i32 w dq + f64 r qq + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq +VL256 + i32 w dq + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_MEMdq +VL128 + f32 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_XMMdq +VL128 + f32 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_MEMqq +VL256 + f32 w dq + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_YMMqq +VL256 + f32 w dq + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq +VL128 + i32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq +VL128 + i32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq +VL256 + i32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq +VL256 + i32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq +VL128 + i32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq +VL128 + i32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq +VL256 + i32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq +VL256 + i32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2PD_XMMdq_MEMq +VL128 + f64 w dq + f32 r q + +INTRINSIC_XED_IFORM_VCVTPS2PD_XMMdq_XMMq +VL128 + f64 w dq + f32 r q + +INTRINSIC_XED_IFORM_VCVTPS2PD_YMMqq_MEMdq +VL256 + f64 w qq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PD_YMMqq_XMMdq +VL256 + f64 w qq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32d_MEMq + i32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32d_XMMq + i32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64q_MEMq + i64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64q_XMMq + i64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32d_MEMq + i32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32d_XMMq + i32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64q_MEMq + i64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64q_XMMq + i64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32d_MEMd + i32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32d_XMMd + i32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64q_MEMd + i64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64q_XMMd + i64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32d_MEMd + i32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32d_XMMd + i32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64q_MEMd + i64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64q_XMMd + i64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq + f32 w dq + f32 r dq + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq + f32 w dq + f32 r dq + f64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd + f64 w dq + f64 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d + f64 w dq + f64 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q + f64 w dq + f64 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d + f32 w dq + f32 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq + f32 w dq + f32 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q + f32 w dq + f32 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd + f64 w dq + f64 r dq + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd + f64 w dq + f64 r dq + f32 r d + +INTRINSIC_XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb +VL256 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb +VL256 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb +VL128 + f32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb +VL128 + INVALID w GPR32_B + f32 r dq + +INTRINSIC_XED_IFORM_VZEROALL +VL256 + +INTRINSIC_XED_IFORM_VZEROUPPER +VL128 + +INTRINSIC_XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VBROADCASTSS_XMMdq_MEMd +VL128 + f32 w dq + f32 r d + +INTRINSIC_XED_IFORM_VBROADCASTSS_YMMqq_MEMd +VL256 + f32 w qq + f32 r d + +INTRINSIC_XED_IFORM_VBROADCASTSS_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTSS_YMMqq_XMMdq +VL256 + f32 w qq + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTSD_YMMqq_MEMq +VL256 + f64 w qq + f64 r q + +INTRINSIC_XED_IFORM_VBROADCASTSD_YMMqq_XMMdq +VL256 + f64 w qq + f64 r dq + +INTRINSIC_XED_IFORM_VBROADCASTF128_YMMqq_MEMdq +VL256 + f64 w qq + f64 r dq + +INTRINSIC_XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r dq + +INTRINSIC_XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r dq + +INTRINSIC_XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb +VL128 + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VLDDQU_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VLDDQU_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + i32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + i32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq +VL128 + f32 w dq + i32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq +VL256 + f32 w qq + i32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + u64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + u64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq +VL128 + f64 w dq + u64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq +VL256 + f64 w qq + u64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPTEST_XMMdq_MEMdq +VL128 + i32 r dq + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPTEST_XMMdq_XMMdq +VL128 + i32 r dq + i32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPTEST_YMMqq_MEMqq +VL256 + i32 r qq + i32 r qq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPTEST_YMMqq_YMMqq +VL256 + i32 r qq + i32 r qq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPS_XMMdq_MEMdq +VL128 + f32 r dq + f32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPS_XMMdq_XMMdq +VL128 + f32 r dq + f32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPS_YMMqq_MEMqq +VL256 + f32 r qq + f32 r qq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPS_YMMqq_YMMqq +VL256 + f32 r qq + f32 r qq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPD_XMMdq_MEMdq +VL128 + f64 r dq + f64 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPD_XMMdq_XMMdq +VL128 + f64 r dq + f64 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPD_YMMqq_MEMqq +VL256 + f64 r qq + f64 r qq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VTESTPD_YMMqq_YMMqq +VL256 + f64 r qq + f64 r qq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMOVAPD_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVAPD_XMMdq_XMMdq_28 +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVAPD_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVAPD_XMMdq_XMMdq_29 +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_YMMqq_28 +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVAPD_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_YMMqq_29 +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVAPS_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVAPS_XMMdq_XMMdq_28 +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVAPS_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVAPS_XMMdq_XMMdq_29 +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_YMMqq_28 +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVAPS_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_YMMqq_29 +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVD_XMMdq_MEMd +VL128 + i32 w dq + i32 r d + +INTRINSIC_XED_IFORM_VMOVD_XMMdq_GPR32d +VL128 + i32 w dq + i32 r d + +INTRINSIC_XED_IFORM_VMOVD_MEMd_XMMd +VL128 + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_VMOVD_GPR32d_XMMd +VL128 + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_VMOVQ_XMMdq_MEMq_6E +VL128 + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_VMOVQ_XMMdq_GPR64q +VL128 + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_VMOVQ_MEMq_XMMq_7E +VL128 + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_VMOVQ_GPR64q_XMMq +VL128 + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_VMOVQ_XMMdq_MEMq_7E +VL128 + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_VMOVQ_XMMdq_XMMq_7E +VL128 + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_VMOVQ_MEMq_XMMq_D6 +VL128 + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_VMOVQ_XMMdq_XMMq_D6 +VL128 + i32 w dq + i64 r q + +INTRINSIC_XED_IFORM_VMOVDDUP_XMMdq_MEMq +VL128 + f64 w dq + f64 r q + +INTRINSIC_XED_IFORM_VMOVDDUP_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVDDUP_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVDDUP_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVDQA_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQA_MEMdq_XMMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVDQA_MEMqq_YMMqq +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVDQU_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVDQU_MEMdq_XMMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVDQU_MEMqq_YMMqq +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVSHDUP_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSHDUP_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSHDUP_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVSHDUP_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVSLDUP_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSLDUP_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSLDUP_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVSLDUP_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq +VL256 + u256 w qq + u256 r qq + u256 r qq + +INTRINSIC_XED_IFORM_VPABSB_XMMdq_MEMdq +VL128 + u8 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPABSB_XMMdq_XMMdq +VL128 + u8 w dq + i8 r dq + +INTRINSIC_XED_IFORM_VPABSB_YMMqq_MEMqq +VL256 + u8 w qq + i8 r qq + +INTRINSIC_XED_IFORM_VPABSB_YMMqq_YMMqq +VL256 + u8 w qq + i8 r qq + +INTRINSIC_XED_IFORM_VPABSW_XMMdq_MEMdq +VL128 + u16 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPABSW_XMMdq_XMMdq +VL128 + u16 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPABSW_YMMqq_MEMqq +VL256 + u16 w qq + i16 r qq + +INTRINSIC_XED_IFORM_VPABSW_YMMqq_YMMqq +VL256 + u16 w qq + i16 r qq + +INTRINSIC_XED_IFORM_VPABSD_XMMdq_MEMdq +VL128 + u32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPABSD_XMMdq_XMMdq +VL128 + u32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPABSD_YMMqq_MEMqq +VL256 + u32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VPABSD_YMMqq_YMMqq +VL256 + u32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb +VL256 + u32 w qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb +VL256 + u32 w qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb +VL256 + u16 w qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb +VL256 + u16 w qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb +VL256 + u16 w qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb +VL256 + u16 w qq + u16 r qq + +INTRINSIC_XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb +VL128 + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq +VL256 + u16 w qq + u16 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq +VL256 + u16 w qq + u16 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb +VL256 + u16 w qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb +VL128 + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq +VL256 + u32 w qq + u32 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq +VL256 + u32 w qq + u32 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb +VL256 + u32 w qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb +VL128 + u64 w dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq +VL256 + u64 w qq + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq +VL256 + u64 w qq + u64 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb +VL256 + u64 w qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb +VL128 + u16 w dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq +VL256 + u16 w qq + u16 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq +VL256 + u16 w qq + u16 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb +VL256 + u16 w qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb +VL128 + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq +VL256 + u32 w qq + u32 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq +VL256 + u32 w qq + u32 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb +VL256 + u32 w qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb +VL128 + u64 w dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq +VL256 + u64 w qq + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq +VL256 + u64 w qq + u64 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb +VL256 + u64 w qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb +VL128 + i16 w dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq +VL256 + i16 w qq + i16 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq +VL256 + i16 w qq + i16 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb +VL256 + i16 w qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq +VL256 + i32 w qq + i32 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq +VL256 + i32 w qq + i32 r qq + u64 r q + +INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq +VL256 + i64 w qq + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq +VL256 + i64 w qq + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq +VL256 + i64 w qq + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq +VL256 + i64 w qq + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq +VL256 + i64 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq +VL256 + i64 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq +VL128 + i64 w dq + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq +VL256 + i64 w qq + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq +VL256 + i64 w qq + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb +VL128 + u128 w dq + u128 r dq + +INTRINSIC_XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb +VL256 + u128 w qq + u128 r qq + +INTRINSIC_XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb +VL128 + u128 w dq + u128 r dq + +INTRINSIC_XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb +VL256 + u128 w qq + u128 r qq + +INTRINSIC_XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq +VL128 + f32 w dq + f32 r q + f32 r q + +INTRINSIC_XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VRCPPS_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VRCPPS_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VRCPPS_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VRCPPS_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VRSQRTPS_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VRSQRTPS_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VRSQRTPS_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VRSQRTPS_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSQRTPD_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VSQRTPD_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VSQRTPD_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VSQRTPD_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VSQRTPS_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VSQRTPS_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VSQRTPS_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VSQRTPS_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq +VL256 + i8 w qq + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq +VL128 + u16 w dq + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq +VL256 + u16 w qq + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq +VL128 + i16 w dq + u8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq +VL128 + i16 w dq + u8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq +VL256 + i16 w qq + u8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq +VL256 + i16 w qq + u8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u16 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u16 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb +VL256 + u16 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb +VL256 + u16 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VUCOMISD_XMMdq_MEMq + f64 r dq + f64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUCOMISD_XMMdq_XMMq + f64 r dq + f64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUCOMISS_XMMdq_MEMd + f32 r dq + f32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUCOMISS_XMMdq_XMMd + f32 r dq + f32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVSS_XMMdq_MEMd + f32 w dq + f32 r d + +INTRINSIC_XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10 + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMOVSS_MEMd_XMMd + f32 w d + f32 r d + +INTRINSIC_XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11 + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMOVSD_XMMdq_MEMq + f64 w dq + f64 r q + +INTRINSIC_XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10 + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMOVSD_MEMq_XMMq + f64 w q + f64 r q + +INTRINSIC_XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11 + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMOVUPD_XMMdq_MEMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_XMMdq_XMMdq_10 +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_XMMdq_XMMdq_11 +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_MEMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_YMMqq_10 +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVUPD_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_YMMqq_11 +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVUPS_XMMdq_MEMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPS_XMMdq_XMMdq_10 +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPS_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPS_XMMdq_XMMdq_11 +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_YMMqq_10 +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVUPS_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_YMMqq_11 +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq +VL128 + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMOVLPD_MEMq_XMMq +VL128 + f64 w q + f64 r q + +INTRINSIC_XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq +VL128 + f32 w dq + f32 r dq + f32 r q + +INTRINSIC_XED_IFORM_VMOVLPS_MEMq_XMMq +VL128 + f32 w q + f32 r q + +INTRINSIC_XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq +VL128 + f64 w dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VMOVHPD_MEMq_XMMdq +VL128 + f64 w q + f64 r dq + +INTRINSIC_XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq +VL128 + f32 w dq + f32 r q + f32 r q + +INTRINSIC_XED_IFORM_VMOVHPS_MEMq_XMMdq +VL128 + f32 w q + f32 r dq + +INTRINSIC_XED_IFORM_VMOVMSKPD_GPR32d_XMMdq +VL128 + i32 w d + f64 r dq + +INTRINSIC_XED_IFORM_VMOVMSKPD_GPR32d_YMMqq +VL256 + i32 w d + f64 r qq + +INTRINSIC_XED_IFORM_VMOVMSKPS_GPR32d_XMMdq +VL128 + i32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VMOVMSKPS_GPR32d_YMMqq +VL256 + i32 w d + f32 r qq + +INTRINSIC_XED_IFORM_VPMOVMSKB_GPR32d_XMMdq +VL128 + u32 w d + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVMSKB_GPR32d_YMMqq +VL256 + u32 w d + i8 r qq + +INTRINSIC_XED_IFORM_VPMOVSXBW_XMMdq_XMMq +VL128 + i16 w dq + i8 r q + +INTRINSIC_XED_IFORM_VPMOVSXBW_XMMdq_MEMq +VL128 + i16 w dq + i8 r q + +INTRINSIC_XED_IFORM_VPMOVSXBW_YMMqq_XMMdq +VL256 + i16 w qq + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBW_YMMqq_MEMdq +VL256 + i16 w qq + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBD_XMMdq_XMMd +VL128 + i32 w dq + i8 r d + +INTRINSIC_XED_IFORM_VPMOVSXBD_XMMdq_MEMd +VL128 + i32 w dq + i8 r d + +INTRINSIC_XED_IFORM_VPMOVSXBD_YMMqq_XMMq +VL256 + i32 w qq + i8 r q + +INTRINSIC_XED_IFORM_VPMOVSXBD_YMMqq_MEMq +VL256 + i32 w qq + i8 r q + +INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMdq_XMMw +VL128 + i64 w dq + i8 r w + +INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMdq_MEMw +VL128 + i64 w dq + i8 r w + +INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMqq_XMMd +VL256 + i64 w qq + i8 r d + +INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMqq_MEMd +VL256 + i64 w qq + i8 r d + +INTRINSIC_XED_IFORM_VPMOVSXWD_XMMdq_XMMq +VL128 + i32 w dq + i16 r q + +INTRINSIC_XED_IFORM_VPMOVSXWD_XMMdq_MEMq +VL128 + i32 w dq + i16 r q + +INTRINSIC_XED_IFORM_VPMOVSXWD_YMMqq_XMMdq +VL256 + i32 w qq + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWD_YMMqq_MEMdq +VL256 + i32 w qq + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMdq_XMMd +VL128 + i64 w dq + i16 r d + +INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMdq_MEMd +VL128 + i64 w dq + i16 r d + +INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMqq_XMMq +VL256 + i64 w qq + i16 r q + +INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMqq_MEMq +VL256 + i64 w qq + i16 r q + +INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMdq_XMMq +VL128 + i64 w dq + i32 r q + +INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMdq_MEMq +VL128 + i64 w dq + i32 r q + +INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq +VL256 + i64 w qq + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq +VL256 + i64 w qq + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBW_XMMdq_XMMq +VL128 + u16 w dq + u8 r q + +INTRINSIC_XED_IFORM_VPMOVZXBW_XMMdq_MEMq +VL128 + u16 w dq + u8 r q + +INTRINSIC_XED_IFORM_VPMOVZXBW_YMMqq_XMMdq +VL256 + u16 w qq + u8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBW_YMMqq_MEMdq +VL256 + u16 w qq + u8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBD_XMMdq_XMMd +VL128 + u32 w dq + u8 r d + +INTRINSIC_XED_IFORM_VPMOVZXBD_XMMdq_MEMd +VL128 + u32 w dq + u8 r d + +INTRINSIC_XED_IFORM_VPMOVZXBD_YMMqq_XMMq +VL256 + u32 w qq + u8 r q + +INTRINSIC_XED_IFORM_VPMOVZXBD_YMMqq_MEMq +VL256 + u32 w qq + u8 r q + +INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMdq_XMMw +VL128 + u64 w dq + u8 r w + +INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMdq_MEMw +VL128 + u64 w dq + u8 r w + +INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMqq_XMMd +VL256 + u64 w qq + u8 r d + +INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMqq_MEMd +VL256 + u64 w qq + u8 r d + +INTRINSIC_XED_IFORM_VPMOVZXWD_XMMdq_XMMq +VL128 + u32 w dq + u16 r q + +INTRINSIC_XED_IFORM_VPMOVZXWD_XMMdq_MEMq +VL128 + u32 w dq + u16 r q + +INTRINSIC_XED_IFORM_VPMOVZXWD_YMMqq_XMMdq +VL256 + u32 w qq + u16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWD_YMMqq_MEMdq +VL256 + u32 w qq + u16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMdq_XMMd +VL128 + u64 w dq + u16 r d + +INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMdq_MEMd +VL128 + u64 w dq + u16 r d + +INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMqq_XMMq +VL256 + u64 w qq + u16 r q + +INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMqq_MEMq +VL256 + u64 w qq + u16 r q + +INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMdq_XMMq +VL128 + u64 w dq + u32 r q + +INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMdq_MEMq +VL128 + u64 w dq + u32 r q + +INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq +VL256 + u64 w qq + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq +VL256 + u64 w qq + u32 r dq + +INTRINSIC_XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb +VL128 + u8 w b + u8 r dq + +INTRINSIC_XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb +VL128 + i32 w d + u8 r dq + +INTRINSIC_XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb +VL128 + i16 w w + u16 r dq + +INTRINSIC_XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15 +VL128 + i32 w d + u16 r dq + +INTRINSIC_XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5 +VL128 + i32 w d + u16 r dq + +INTRINSIC_XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb +VL128 + i64 w q + u64 r dq + +INTRINSIC_XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb +VL128 + i64 w q + u64 r dq + +INTRINSIC_XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb +VL128 + i32 w d + u32 r dq + +INTRINSIC_XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb +VL128 + i32 w d + u32 r dq + +INTRINSIC_XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb +VL128 + u8 w dq + u8 r dq + u8 r b + +INTRINSIC_XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb +VL128 + u8 w dq + u8 r dq + u8 r d + +INTRINSIC_XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb +VL128 + u16 w dq + u16 r dq + u16 r w + +INTRINSIC_XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb +VL128 + u16 w dq + u16 r dq + u16 r d + +INTRINSIC_XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb +VL128 + u32 w dq + u32 r dq + u32 r d + +INTRINSIC_XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb +VL128 + u32 w dq + u32 r dq + u32 r d + +INTRINSIC_XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb +VL128 + u64 w dq + u64 r dq + u64 r q + +INTRINSIC_XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb +VL128 + u64 w dq + u64 r dq + u64 r q + +INTRINSIC_XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID w XED_REG_ECX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID w XED_REG_RCX + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_EAX + INVALID r XED_REG_EDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb +VL128 + i32 r dq + i32 r dq + INVALID r XED_REG_RAX + INVALID r XED_REG_RDX + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb +VL128 + i32 r dq + i32 r dq + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb +VL128 + i32 r dq + i32 r dq + i32 w dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq +VL128 + u8 r dq + u8 r dq + u8 w dq + +INTRINSIC_XED_IFORM_VLDMXCSR_MEMd +VL128 + i32 r d + INVALID w XED_REG_MXCSR + +INTRINSIC_XED_IFORM_VSTMXCSR_MEMd +VL128 + i32 w d + INVALID r XED_REG_MXCSR + +INTRINSIC_XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + i8 w dq + i8 r dq + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + u8 w qq + u8 r qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f64 w dq + f64 r dq + f64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f64 w qq + f64 r qq + f64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq +VL128 + f32 w dq + f32 r dq + f32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VMOVNTDQA_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVNTDQA_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVNTDQ_MEMdq_XMMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VMOVNTDQ_MEMqq_YMMqq +VL256 + i32 w qq + i32 r qq + +INTRINSIC_XED_IFORM_VMOVNTPD_MEMdq_XMMdq +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVNTPD_MEMqq_YMMqq +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVNTPS_MEMdq_XMMdq +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVNTPS_MEMqq_YMMqq +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESIMC_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VAESIMC_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u128 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u128 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 +VL256 + u128 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 +VL256 + u128 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VCVTPH2PS_XMMdq_MEMq +VL128 + f32 w dq + f16 r q + +INTRINSIC_XED_IFORM_VCVTPH2PS_XMMdq_XMMq +VL128 + f32 w dq + f16 r q + +INTRINSIC_XED_IFORM_VCVTPH2PS_YMMqq_MEMdq +VL256 + f32 w qq + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2PS_YMMqq_XMMdq +VL256 + f32 w qq + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb +VL128 + f16 w q + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb +VL128 + f16 w q + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb +VL256 + f16 w dq + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb +VL256 + f16 w dq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq +VL128 + f64 rw dq + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq +VL256 + f64 rw qq + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq +VL128 + f32 rw dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq +VL256 + f32 rw qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq + f64 rw dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd + f32 rw dq + f32 r d + f32 r d + +INTRINSIC_XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 +VL256 + f64 crw qq + f64 r q + i64 rw qq + +INTRINSIC_XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 +VL128 + f64 crw dq + f64 r q + i64 rw dq + +INTRINSIC_XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 +VL256 + f32 crw qq + f32 r d + i32 rw qq + +INTRINSIC_XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 +VL128 + f32 crw dq + f32 r d + i32 rw dq + +INTRINSIC_XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 +VL256 + f64 crw qq + f64 r q + i64 rw qq + +INTRINSIC_XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 +VL128 + f64 crw dq + f64 r q + i64 rw dq + +INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 +VL256 + f32 crw dq + f32 r d + i32 rw dq + +INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 +VL128 + f32 crw q + f32 r d + i32 rw q + +INTRINSIC_XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 +VL256 + u64 crw qq + u64 r q + i64 rw qq + +INTRINSIC_XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 +VL128 + u64 crw dq + u64 r q + i64 rw dq + +INTRINSIC_XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 +VL256 + u32 crw qq + u32 r d + i32 rw qq + +INTRINSIC_XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 +VL128 + u32 crw dq + u32 r d + i32 rw dq + +INTRINSIC_XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 +VL256 + u64 crw qq + u64 r q + i64 rw qq + +INTRINSIC_XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 +VL128 + u64 crw dq + u64 r q + i64 rw dq + +INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 +VL256 + u32 crw dq + u32 r d + i32 rw dq + +INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 +VL128 + u32 crw q + u32 r d + i32 rw q + +INTRINSIC_XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb +VL256 + u128 w qq + u128 r qq + u128 r dq + +INTRINSIC_XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb +VL256 + u128 w qq + u128 r qq + u128 r dq + +INTRINSIC_XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb +VL256 + u128 w dq + u128 r qq + +INTRINSIC_XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb +VL256 + u128 w dq + u128 r qq + +INTRINSIC_XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq +VL128 + u64 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq +VL256 + u64 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb +VL256 + u64 w qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb +VL256 + u64 w qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq +VL256 + f32 w qq + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb +VL128 + u32 w dq + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb +VL256 + u32 w qq + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPBROADCASTB_XMMdq_MEMb +VL128 + u8 w dq + u8 r b + +INTRINSIC_XED_IFORM_VPBROADCASTB_XMMdq_XMMb +VL128 + u8 w dq + u8 r b + +INTRINSIC_XED_IFORM_VPBROADCASTB_YMMqq_MEMb +VL256 + u8 w qq + u8 r b + +INTRINSIC_XED_IFORM_VPBROADCASTB_YMMqq_XMMb +VL256 + u8 w qq + u8 r b + +INTRINSIC_XED_IFORM_VPBROADCASTW_XMMdq_MEMw +VL128 + u16 w dq + u16 r w + +INTRINSIC_XED_IFORM_VPBROADCASTW_XMMdq_XMMw +VL128 + u16 w dq + u16 r w + +INTRINSIC_XED_IFORM_VPBROADCASTW_YMMqq_MEMw +VL256 + u16 w qq + u16 r w + +INTRINSIC_XED_IFORM_VPBROADCASTW_YMMqq_XMMw +VL256 + u16 w qq + u16 r w + +INTRINSIC_XED_IFORM_VPBROADCASTD_XMMdq_MEMd +VL128 + u32 w dq + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_XMMdq_XMMd +VL128 + u32 w dq + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_YMMqq_MEMd +VL256 + u32 w qq + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_YMMqq_XMMd +VL256 + u32 w qq + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMdq_MEMq +VL128 + u64 w dq + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMdq_XMMq +VL128 + u64 w dq + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMqq_MEMq +VL256 + u64 w qq + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMqq_XMMq +VL256 + u64 w qq + u64 r q + +INTRINSIC_XED_IFORM_VBROADCASTI128_YMMqq_MEMdq +VL256 + u128 w qq + u128 r dq + +INTRINSIC_XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq +VL128 + i32 w dq + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq +VL256 + i32 w qq + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSR_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSR_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSR_VGPR64q_MEMq +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSR_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSMSK_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSMSK_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSMSK_VGPR64q_MEMq +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSMSK_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSI_VGPR32d_MEMd +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSI_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSI_VGPR64q_MEMq +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BLSI_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 r d + i32 r d + +INTRINSIC_XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 r q + i64 r q + +INTRINSIC_XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d +VL128 + i32 w d + i32 w d + i32 r d + INVALID r XED_REG_EDX + +INTRINSIC_XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd +VL128 + i32 w d + i32 w d + i32 r d + INVALID r XED_REG_EDX + +INTRINSIC_XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q +VL128 + i64 w q + i64 w q + i64 r q + INVALID r XED_REG_RDX + +INTRINSIC_XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq +VL128 + i64 w q + i64 w q + i64 r q + INVALID r XED_REG_RDX + +INTRINSIC_XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb +VL128 + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_RORX_VGPR32d_MEMd_IMMb +VL128 + i32 w d + i32 r d + +INTRINSIC_XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb +VL128 + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_RORX_VGPR64q_MEMq_IMMb +VL128 + i64 w q + i64 r q + +INTRINSIC_XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512 +VL128 + i1 w mskw + u16 r mskw + +INTRINSIC_XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512 +VL128 + i1 w mskw + u16 r wrd + +INTRINSIC_XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512 +VL128 + u16 w wrd + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512 +VL128 + i1 w mskw + u32 r d + +INTRINSIC_XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512 +VL128 + u32 w d + i1 r mskw + +INTRINSIC_XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512 +VL128 + i1 w mskw + u8 r mskw + +INTRINSIC_XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512 +VL128 + i1 w mskw + u8 r b + +INTRINSIC_XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512 +VL128 + u8 w b + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512 +VL128 + i1 w mskw + u32 r d + +INTRINSIC_XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512 +VL128 + u32 w d + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512 +VL128 + i1 w mskw + u32 r mskw + +INTRINSIC_XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512 +VL128 + i1 w mskw + u32 r d + +INTRINSIC_XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512 +VL128 + u32 w d + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512 +VL128 + i1 w mskw + u32 r d + +INTRINSIC_XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512 +VL128 + u32 w d + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512 +VL128 + i1 w mskw + u64 r mskw + +INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512 +VL128 + i1 w mskw + u64 r q + +INTRINSIC_XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512 +VL128 + u64 w q + i1 r mskw + +INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512 +VL128 + i1 w mskw + u64 r q + +INTRINSIC_XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512 +VL128 + u64 w q + i1 r mskw + +INTRINSIC_XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512 +VL128 + i1 r mskw + i1 r mskw + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +VL256 + i1 w mskw + i1 r mskw + i1 r mskw + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8 +VL128 + u8 w dq + u8 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 +VL128 + u8 w dq + u8 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 +VL256 + u8 w qq + u8 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 +VL256 + u8 w qq + u8 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 +VL128 + u8 w dq + u8 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 +VL128 + u8 w dq + u8 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 +VL256 + u8 w qq + u8 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 +VL256 + u8 w qq + u8 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8 +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8 +VL128 + u8 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8 +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8 +VL256 + u8 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + u8 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + u8 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + u8 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + u8 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + u8 r zu8 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + u8 r zu8 + u32 r vv + +INTRINSIC_XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + u8 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + u8 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + u8 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + u8 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + u8 r zu8 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + u8 r zu8 + u32 r vv + +INTRINSIC_XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + i16 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + i16 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + i16 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + i16 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + i16 r zi16 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + i16 r zi16 + u32 r vv + +INTRINSIC_XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + i16 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 +VL128 + i32 rw dq + i1 r mskw + i16 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + i16 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 +VL256 + i32 rw qq + i1 r mskw + i16 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + i16 r zi16 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + i16 r zi16 + u32 r vv + +INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + bf16 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128 +VL128 + bf16 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + bf16 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256 +VL256 + bf16 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + bf16 w zbf16 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512 +VL512 + bf16 w zbf16 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512 +VL128 + bf16 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128 +VL128 + bf16 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512 +VL256 + bf16 w dq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256 +VL256 + bf16 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512 +VL512 + bf16 w qq + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512 +VL512 + bf16 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + f32 rw dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + f32 rw dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + f32 rw qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + f32 rw qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 +VL512 + f64 r q + i1 rw mskw + +INTRINSIC_XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 +VL512 + f32 r d + i1 rw mskw + +INTRINSIC_XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r dq + +INTRINSIC_XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r dq + +INTRINSIC_XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + i16 r zi16 + u32 r dq + +INTRINSIC_XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +VL512 + i32 rw zi32 + i1 r mskw + i16 r zi16 + u32 r dq + +INTRINSIC_XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r q + +INTRINSIC_XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r q + +INTRINSIC_XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r d + +INTRINSIC_XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r d + +INTRINSIC_XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r d + +INTRINSIC_XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 + i1 w mskw + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 + i1 w mskw + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 + i1 w mskw + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 + i1 w mskw + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512 + f64 r dq + f64 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512 + f64 r dq + f64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512 + f32 r dq + f32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512 + f32 r dq + f32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zd + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zd + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 +VL512 + f64 w zf64 + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 +VL512 + f64 w zf64 + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 +VL128 + f64 w dq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 +VL128 + f64 w dq + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 +VL256 + f64 w qq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 +VL256 + f64 w qq + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + i32 r zi32 + +INTRINSIC_XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 +VL128 + f32 w dq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 +VL128 + f32 w dq + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 +VL256 + f32 w qq + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 +VL256 + f32 w qq + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +VL512 + i32 w qq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 +VL512 + i32 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 +VL128 + i32 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 +VL128 + i32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 +VL256 + i32 w dq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 +VL256 + i32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 +VL512 + f32 w qq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 +VL512 + f32 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 +VL128 + f32 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 +VL128 + f32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 +VL256 + f32 w dq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 +VL256 + f32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +VL512 + u32 w qq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 +VL512 + u32 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 +VL128 + u32 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 +VL128 + u32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 +VL256 + u32 w dq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 +VL256 + u32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f16 r qq + +INTRINSIC_XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 +VL128 + f32 w dq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 +VL128 + f32 w dq + i1 r mskw + f16 r q + +INTRINSIC_XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 +VL256 + f32 w qq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 +VL256 + f32 w qq + i1 r mskw + f16 r dq + +INTRINSIC_XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 +VL128 + i32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 +VL128 + i32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 +VL256 + i32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 +VL256 + i32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 +VL128 + f64 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 +VL128 + f64 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 +VL256 + f64 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 +VL256 + f64 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f16 w qq + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f16 w qq + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 +VL128 + f16 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 +VL128 + f16 w q + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f16 w dq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f16 w dq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 +VL128 + u32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 +VL128 + u32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 +VL256 + u32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 +VL256 + u32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512 + i32 w d + f64 r dq + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512 + i32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512 + i64 w q + f64 r dq + +INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512 + i64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 + f32 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 + f32 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512 + u32 w d + f64 r dq + +INTRINSIC_XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512 + u32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512 + u64 w q + f64 r dq + +INTRINSIC_XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512 + u64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 + f64 w dq + f64 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 + f64 w dq + f64 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 + f64 w dq + f64 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 + f64 w dq + f64 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 + f32 w dq + f32 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 + f32 w dq + f32 r dq + i32 r d + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 + f32 w dq + f32 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 + f32 w dq + f32 r dq + i64 r q + +INTRINSIC_XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 + f64 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 + f64 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512 + i32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512 + i32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512 + i64 w q + f32 r dq + +INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512 + i64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512 + u32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512 + u32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512 + u64 w q + f32 r dq + +INTRINSIC_XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512 + u64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +VL512 + i32 w qq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 +VL512 + i32 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 +VL128 + i32 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 +VL128 + i32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 +VL256 + i32 w dq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 +VL256 + i32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +VL512 + u32 w qq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 +VL512 + u32 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 +VL128 + u32 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 +VL128 + u32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 +VL256 + u32 w dq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 +VL256 + u32 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 +VL128 + i32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 +VL128 + i32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 +VL256 + i32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 +VL256 + i32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 +VL128 + u32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 +VL128 + u32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 +VL256 + u32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 +VL256 + u32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512 + i32 w d + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512 + i32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512 + i64 w q + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512 + i64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512 + u32 w d + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512 + u32 w d + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512 + u64 w q + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512 + u64 w q + f64 r q + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512 + i32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512 + i32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512 + i64 w q + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512 + i64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512 + u32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512 + u32 w d + f32 r d + +INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512 + u64 w q + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512 + u64 w q + f32 r d + +INTRINSIC_XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 +VL512 + f64 w zf64 + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 +VL512 + f64 w zf64 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 +VL128 + f64 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 +VL128 + f64 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 +VL256 + f64 w qq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 +VL256 + f64 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 +VL128 + f32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 +VL128 + f32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 +VL256 + f32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 +VL256 + f32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 + f64 w dq + f64 r dq + u32 r d + +INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 + f64 w dq + f64 r dq + u32 r d + +INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 + f64 w dq + f64 r dq + u64 r q + +INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 + f64 w dq + f64 r dq + u64 r q + +INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 + f32 w dq + f32 r dq + u32 r d + +INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 + f32 w dq + f32 r dq + u32 r d + +INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 + f32 w dq + f32 r dq + u64 r q + +INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 + f32 w dq + f32 r dq + u64 r q + +INTRINSIC_XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zd + +INTRINSIC_XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zd + +INTRINSIC_XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w dq + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w dq + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f32 w dq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f32 w dq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w qq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w qq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w dq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w dq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 +VL128 + f32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 +VL128 + f32 w d + f32 r dq + +INTRINSIC_XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 rw dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 rw dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 +VL512 + f64 w zf64 + i1 rw mskw + f64 r q + +INTRINSIC_XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 +VL128 + f64 w dq + i1 rw mskw + f64 r q + +INTRINSIC_XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 +VL256 + f64 w qq + i1 rw mskw + f64 r q + +INTRINSIC_XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 +VL512 + f32 w zf32 + i1 rw mskw + f32 r d + +INTRINSIC_XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 +VL128 + f32 w dq + i1 rw mskw + f32 r d + +INTRINSIC_XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 +VL256 + f32 w qq + i1 rw mskw + f32 r d + +INTRINSIC_XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 +VL512 + f64 w zf64 + i1 rw mskw + f64 r q + +INTRINSIC_XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 +VL128 + f64 w dq + i1 rw mskw + f64 r q + +INTRINSIC_XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 +VL256 + f64 w qq + i1 rw mskw + f64 r q + +INTRINSIC_XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 +VL512 + f32 w qq + i1 rw mskw + f32 r d + +INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 +VL128 + f32 w dq + i1 rw mskw + f32 r d + +INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 +VL256 + f32 w dq + i1 rw mskw + f32 r d + +INTRINSIC_XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r dq + +INTRINSIC_XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r dq + +INTRINSIC_XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r dq + +INTRINSIC_XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r dq + +INTRINSIC_XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r qq + +INTRINSIC_XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r qq + +INTRINSIC_XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r qq + +INTRINSIC_XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r qq + +INTRINSIC_XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 +VL128 + f32 w dq + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zd + +INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zd + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zd + +INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zd + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512 +VL128 + u32 w dq + u32 r d + +INTRINSIC_XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + u32 r d + +INTRINSIC_XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512 +VL128 + u32 w d + u32 r dq + +INTRINSIC_XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512 +VL128 + u32 w d + u32 r dq + +INTRINSIC_XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zd + +INTRINSIC_XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r q + +INTRINSIC_XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zd + +INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zd + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zd + +INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zd + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zd + +INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zd + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zd + +INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zd + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + f64 r q + f64 r q + +INTRINSIC_XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512 +VL128 + f64 w q + f64 r dq + +INTRINSIC_XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + f32 r q + f32 r q + +INTRINSIC_XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512 +VL128 + f32 w q + f32 r dq + +INTRINSIC_XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + f32 r q + f32 r q + +INTRINSIC_XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512 +VL128 + f64 w q + f64 r q + +INTRINSIC_XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + f32 r dq + f32 r q + +INTRINSIC_XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512 +VL128 + f32 w q + f32 r q + +INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512 +VL512 + u32 w zd + u32 r zu32 + +INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512 +VL128 + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512 +VL256 + u32 w qq + u32 r qq + +INTRINSIC_XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + u32 r zd + +INTRINSIC_XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + u32 r dq + +INTRINSIC_XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + u32 r qq + +INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512 +VL512 + f64 w zd + f64 r zf64 + +INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512 +VL128 + f64 w dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512 +VL256 + f64 w qq + f64 r qq + +INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512 +VL512 + f32 w zd + f32 r zf32 + +INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512 +VL128 + f32 w dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512 +VL256 + f32 w qq + f32 r qq + +INTRINSIC_XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512 +VL128 + u64 w dq + u64 r q + +INTRINSIC_XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + u64 r q + +INTRINSIC_XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512 +VL128 + u64 w q + u64 r dq + +INTRINSIC_XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512 +VL128 + u64 w q + u64 r dq + +INTRINSIC_XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + u64 r dq + +INTRINSIC_XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r q + +INTRINSIC_XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 + f64 w q + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zd + +INTRINSIC_XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zd + +INTRINSIC_XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r d + +INTRINSIC_XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 + f32 w d + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zd + +INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zd + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zd + +INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zd + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i32 r zi32 + +INTRINSIC_XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 +VL128 + i32 w dq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 +VL128 + i32 w dq + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 +VL256 + i32 w qq + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 +VL256 + i32 w qq + i1 r mskw + i32 r vv + +INTRINSIC_XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r zi64 + +INTRINSIC_XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r vv + +INTRINSIC_XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r dq + +INTRINSIC_XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r vv + +INTRINSIC_XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r qq + +INTRINSIC_XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r vv + +INTRINSIC_XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r d + +INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r q + +INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r q + +INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i32 r zi32 + i32 r zi32 + +INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i32 r zi32 + i32 r vv + +INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i32 r dq + i32 r vv + +INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i32 r qq + i32 r vv + +INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 +VL512 + i1 w mskw + i1 r mskw + i32 r zi32 + i32 r zi32 + +INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 +VL512 + i1 w mskw + i1 r mskw + i32 r zi32 + i32 r vv + +INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 +VL128 + i1 w mskw + i1 r mskw + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 +VL128 + i1 w mskw + i1 r mskw + i32 r dq + i32 r vv + +INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 +VL256 + i1 w mskw + i1 r mskw + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 +VL256 + i1 w mskw + i1 r mskw + i32 r qq + i32 r vv + +INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 +VL512 + i1 w mskw + i1 r mskw + i64 r zi64 + i64 r zi64 + +INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 +VL512 + i1 w mskw + i1 r mskw + i64 r zi64 + i64 r vv + +INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 +VL128 + i1 w mskw + i1 r mskw + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 +VL128 + i1 w mskw + i1 r mskw + i64 r dq + i64 r vv + +INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 +VL256 + i1 w mskw + i1 r mskw + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 +VL256 + i1 w mskw + i1 r mskw + i64 r qq + i64 r vv + +INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i64 r zi64 + i64 r zi64 + +INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i64 r zi64 + i64 r vv + +INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i64 r dq + i64 r vv + +INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i64 r qq + i64 r vv + +INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zd + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zd + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 rw zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 rw dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 rw qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 rw zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 rw dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 rw qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zd + +INTRINSIC_XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zd + +INTRINSIC_XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 +VL512 + u32 w zu32 + i1 rw mskw + u32 r d + +INTRINSIC_XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 +VL128 + u32 w dq + i1 rw mskw + u32 r d + +INTRINSIC_XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 +VL256 + u32 w qq + i1 rw mskw + u32 r d + +INTRINSIC_XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 +VL512 + u64 w zu64 + i1 rw mskw + u64 r q + +INTRINSIC_XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 +VL128 + u64 w dq + i1 rw mskw + u64 r q + +INTRINSIC_XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 +VL256 + u64 w qq + i1 rw mskw + u64 r q + +INTRINSIC_XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 +VL512 + u32 w qq + i1 rw mskw + u32 r d + +INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 +VL128 + u32 w dq + i1 rw mskw + u32 r d + +INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 +VL256 + u32 w dq + i1 rw mskw + u32 r d + +INTRINSIC_XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 +VL512 + u64 w zu64 + i1 rw mskw + u64 r q + +INTRINSIC_XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 +VL128 + u64 w dq + i1 rw mskw + u64 r q + +INTRINSIC_XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 +VL256 + u64 w qq + i1 rw mskw + u64 r q + +INTRINSIC_XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i32 r zi32 + i32 r zi32 + +INTRINSIC_XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i32 r zi32 + i32 r vv + +INTRINSIC_XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 +VL128 + i32 w dq + i1 r mskw + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 +VL128 + i32 w dq + i1 r mskw + i32 r dq + i32 r vv + +INTRINSIC_XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 +VL256 + i32 w qq + i1 r mskw + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 +VL256 + i32 w qq + i1 r mskw + i32 r qq + i32 r vv + +INTRINSIC_XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r zi64 + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r zi64 + i64 r vv + +INTRINSIC_XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r dq + i64 r vv + +INTRINSIC_XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r qq + i64 r vv + +INTRINSIC_XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i32 r zi32 + i32 r zi32 + +INTRINSIC_XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i32 r zi32 + i32 r vv + +INTRINSIC_XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 +VL128 + i32 w dq + i1 r mskw + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 +VL128 + i32 w dq + i1 r mskw + i32 r dq + i32 r vv + +INTRINSIC_XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 +VL256 + i32 w qq + i1 r mskw + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 +VL256 + i32 w qq + i1 r mskw + i32 r qq + i32 r vv + +INTRINSIC_XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r zi64 + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r zi64 + i64 r vv + +INTRINSIC_XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r dq + i64 r vv + +INTRINSIC_XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r qq + i64 r vv + +INTRINSIC_XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 +VL512 + u8 w dq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 +VL512 + u8 w dq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 +VL128 + u8 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 +VL128 + u8 w d + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 +VL256 + u8 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 +VL256 + u8 w q + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 +VL512 + u16 w qq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 +VL512 + u16 w qq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 +VL128 + u16 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 +VL128 + u16 w q + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 +VL256 + u16 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 +VL256 + u16 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 +VL512 + u8 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 +VL512 + u8 w q + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 +VL128 + u8 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 +VL128 + u8 w wrd + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 +VL256 + u8 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 +VL256 + u8 w d + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 +VL512 + u32 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 +VL512 + u32 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 +VL128 + u32 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 +VL128 + u32 w q + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 +VL256 + u32 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 +VL256 + u32 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 +VL512 + u16 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 +VL512 + u16 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 +VL128 + u16 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 +VL128 + u16 w d + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 +VL256 + u16 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 +VL256 + u16 w q + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 +VL512 + i8 w dq + i1 r mskw + i32 r zi32 + +INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 +VL512 + i8 w dq + i1 r mskw + i32 r zi32 + +INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 +VL128 + i8 w dq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 +VL128 + i8 w d + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 +VL256 + i8 w dq + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 +VL256 + i8 w q + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 +VL512 + i16 w qq + i1 r mskw + i32 r zi32 + +INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 +VL512 + i16 w qq + i1 r mskw + i32 r zi32 + +INTRINSIC_XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 +VL128 + i16 w dq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 +VL128 + i16 w q + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 +VL256 + i16 w dq + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 +VL256 + i16 w dq + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 +VL512 + i8 w dq + i1 r mskw + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 +VL512 + i8 w q + i1 r mskw + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 +VL128 + i8 w dq + i1 r mskw + i64 r dq + +INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 +VL128 + i8 w wrd + i1 r mskw + i64 r dq + +INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 +VL256 + i8 w dq + i1 r mskw + i64 r qq + +INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 +VL256 + i8 w d + i1 r mskw + i64 r qq + +INTRINSIC_XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 +VL512 + i32 w qq + i1 r mskw + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 +VL512 + i32 w qq + i1 r mskw + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 +VL128 + i32 w dq + i1 r mskw + i64 r dq + +INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 +VL128 + i32 w q + i1 r mskw + i64 r dq + +INTRINSIC_XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 +VL256 + i32 w dq + i1 r mskw + i64 r qq + +INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 +VL256 + i32 w dq + i1 r mskw + i64 r qq + +INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 +VL512 + i16 w dq + i1 r mskw + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 +VL512 + i16 w dq + i1 r mskw + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 +VL128 + i16 w dq + i1 r mskw + i64 r dq + +INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 +VL128 + i16 w d + i1 r mskw + i64 r dq + +INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 +VL256 + i16 w dq + i1 r mskw + i64 r qq + +INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 +VL256 + i16 w q + i1 r mskw + i64 r qq + +INTRINSIC_XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 +VL128 + i32 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 +VL128 + i32 w dq + i1 r mskw + i8 r d + +INTRINSIC_XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 +VL256 + i32 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 +VL256 + i32 w qq + i1 r mskw + i8 r q + +INTRINSIC_XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i8 r q + +INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 +VL128 + i64 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 +VL128 + i64 w dq + i1 r mskw + i8 r wrd + +INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 +VL256 + i64 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 +VL256 + i64 w qq + i1 r mskw + i8 r d + +INTRINSIC_XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 +VL128 + i64 w dq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 +VL128 + i64 w dq + i1 r mskw + i32 r q + +INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 +VL256 + i64 w qq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 +VL256 + i64 w qq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 +VL128 + i32 w dq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 +VL128 + i32 w dq + i1 r mskw + i16 r q + +INTRINSIC_XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 +VL256 + i32 w qq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 +VL256 + i32 w qq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 +VL128 + i64 w dq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 +VL128 + i64 w dq + i1 r mskw + i16 r d + +INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 +VL256 + i64 w qq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 +VL256 + i64 w qq + i1 r mskw + i16 r q + +INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 +VL512 + u8 w dq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 +VL512 + u8 w dq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 +VL128 + u8 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 +VL128 + u8 w d + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 +VL256 + u8 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 +VL256 + u8 w q + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 +VL512 + u16 w qq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 +VL512 + u16 w qq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 +VL128 + u16 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 +VL128 + u16 w q + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 +VL256 + u16 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 +VL256 + u16 w dq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 +VL512 + u8 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 +VL512 + u8 w q + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 +VL128 + u8 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 +VL128 + u8 w wrd + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 +VL256 + u8 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 +VL256 + u8 w d + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 +VL512 + u32 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 +VL512 + u32 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 +VL128 + u32 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 +VL128 + u32 w q + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 +VL256 + u32 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 +VL256 + u32 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 +VL512 + u16 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 +VL512 + u16 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 +VL128 + u16 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 +VL128 + u16 w d + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 +VL256 + u16 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 +VL256 + u16 w q + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 +VL128 + i32 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 +VL128 + i32 w dq + i1 r mskw + i8 r d + +INTRINSIC_XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 +VL256 + i32 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 +VL256 + i32 w qq + i1 r mskw + i8 r q + +INTRINSIC_XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i8 r q + +INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 +VL128 + i64 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 +VL128 + i64 w dq + i1 r mskw + i8 r wrd + +INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 +VL256 + i64 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 +VL256 + i64 w qq + i1 r mskw + i8 r d + +INTRINSIC_XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i32 r qq + +INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 +VL128 + i64 w dq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 +VL128 + i64 w dq + i1 r mskw + i32 r q + +INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 +VL256 + i64 w qq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 +VL256 + i64 w qq + i1 r mskw + i32 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 +VL128 + i32 w dq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 +VL128 + i32 w dq + i1 r mskw + i16 r q + +INTRINSIC_XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 +VL256 + i32 w qq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 +VL256 + i32 w qq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 +VL128 + i64 w dq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 +VL128 + i64 w dq + i1 r mskw + i16 r d + +INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 +VL256 + i64 w qq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 +VL256 + i64 w qq + i1 r mskw + i16 r q + +INTRINSIC_XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r zi64 + i64 r zi64 + +INTRINSIC_XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + i64 r zi64 + i64 r vv + +INTRINSIC_XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r dq + i64 r dq + +INTRINSIC_XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 +VL128 + i64 w dq + i1 r mskw + i64 r dq + i64 r vv + +INTRINSIC_XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r qq + i64 r qq + +INTRINSIC_XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 +VL256 + i64 w qq + i1 r mskw + i64 r qq + i64 r vv + +INTRINSIC_XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 +VL512 + u32 w d + i1 rw mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 +VL128 + u32 w d + i1 rw mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 +VL256 + u32 w d + i1 rw mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 +VL512 + u64 w q + i1 rw mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 +VL128 + u64 w q + i1 rw mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 +VL256 + u64 w q + i1 rw mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 +VL512 + u32 w d + i1 rw mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 +VL128 + u32 w d + i1 rw mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 +VL256 + u32 w d + i1 rw mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 +VL512 + u64 w q + i1 rw mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 +VL128 + u64 w q + i1 rw mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 +VL256 + u64 w q + i1 rw mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + i1 w mskw + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + i1 w mskw + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + i1 w mskw + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 +VL512 + f64 w q + i1 rw mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 +VL128 + f64 w q + i1 rw mskw + f64 r dq + +INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 +VL256 + f64 w q + i1 rw mskw + f64 r qq + +INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 +VL512 + f32 w d + i1 rw mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 +VL128 + f32 w d + i1 rw mskw + f32 r dq + +INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 +VL256 + f32 w d + i1 rw mskw + f32 r qq + +INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 +VL512 + f64 w q + i1 rw mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 +VL128 + f64 w q + i1 rw mskw + f64 r dq + +INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 +VL256 + f64 w q + i1 rw mskw + f64 r qq + +INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 +VL512 + f32 w d + i1 rw mskw + f32 r qq + +INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 +VL128 + f32 w d + i1 rw mskw + f32 r dq + +INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 +VL256 + f32 w d + i1 rw mskw + f32 r dq + +INTRINSIC_XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512 + f64 r dq + f64 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512 + f64 r dq + f64 r q + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512 + f32 r dq + f32 r dq + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512 + f32 r dq + f32 r d + INVALID w rFLAGS + +INTRINSIC_XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD +VL512 + u64 w zu64 + u64 r mskw + +INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 +VL128 + u64 w dq + u64 r mskw + +INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 +VL256 + u64 w qq + u64 r mskw + +INTRINSIC_XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD +VL512 + u32 w zu32 + u32 r mskw + +INTRINSIC_XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 +VL128 + u32 w dq + u32 r mskw + +INTRINSIC_XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 +VL256 + u32 w qq + u32 r mskw + +INTRINSIC_XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD +VL512 + u32 w zu32 + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r vv + +INTRINSIC_XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD +VL512 + u64 w zu64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r q + +INTRINSIC_XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r q + +INTRINSIC_XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r q + +INTRINSIC_XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r q + +INTRINSIC_XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r dq + +INTRINSIC_XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r q + +INTRINSIC_XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r qq + +INTRINSIC_XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 +VL128 + i64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 +VL128 + i64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 +VL256 + i64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 +VL256 + i64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 +VL128 + u64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 +VL128 + u64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 +VL256 + u64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 +VL256 + u64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 +VL128 + i64 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 +VL128 + i64 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 +VL256 + i64 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 +VL256 + i64 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 +VL128 + u64 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 +VL128 + u64 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 +VL256 + u64 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 +VL256 + u64 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 +VL128 + i64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 +VL128 + i64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 +VL256 + i64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 +VL256 + i64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 +VL128 + f32 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 +VL128 + f32 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 +VL256 + f32 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 +VL256 + f32 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +VL512 + f32 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 +VL512 + f32 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 +VL128 + i64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 +VL128 + i64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 +VL256 + i64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 +VL256 + i64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 +VL128 + u64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 +VL128 + u64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 +VL256 + u64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 +VL256 + u64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 +VL128 + i64 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 +VL128 + i64 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 +VL256 + i64 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 +VL256 + i64 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 +VL512 + i64 w zi64 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 +VL128 + u64 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 +VL128 + u64 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 +VL256 + u64 w qq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 +VL256 + u64 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 +VL512 + u64 w zu64 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 +VL128 + f64 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 +VL128 + f64 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 +VL256 + f64 w qq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 +VL256 + f64 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 +VL512 + f64 w zf64 + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 +VL128 + f32 w dq + i1 r mskw + u64 r dq + +INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 +VL128 + f32 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 +VL256 + f32 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 +VL256 + f32 w dq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +VL512 + f32 w qq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 +VL512 + f32 w qq + i1 r mskw + u64 r vv + +INTRINSIC_XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w qq + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w qq + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + f64 w dq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + f64 w dq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w dq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w dq + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w qq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 +VL512 + u32 w qq + i1 r mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 +VL256 + u64 w dq + i1 r mskw + u64 r qq + +INTRINSIC_XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 +VL512 + u64 w dq + i1 r mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 +VL128 + i1 w mskw + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 +VL256 + i1 w mskw + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 +VL512 + i1 w mskw + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 +VL128 + i1 w mskw + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 +VL256 + i1 w mskw + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 +VL512 + i1 w mskw + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 + i1 w mskw + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 + i1 w mskw + i1 r mskw + f64 r q + +INTRINSIC_XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 + i1 w mskw + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 + i1 w mskw + i1 r mskw + f32 r d + +INTRINSIC_XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r qq + +INTRINSIC_XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r qq + +INTRINSIC_XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r dq + +INTRINSIC_XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r dq + +INTRINSIC_XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r dq + +INTRINSIC_XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r dq + +INTRINSIC_XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r qq + +INTRINSIC_XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r qq + +INTRINSIC_XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r dq + +INTRINSIC_XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r dq + +INTRINSIC_XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 +VL512 + u16 w zd + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + +INTRINSIC_XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zd + +INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 +VL512 + u8 w zd + i1 r mskw + u8 r zu8 + +INTRINSIC_XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + +INTRINSIC_XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + +INTRINSIC_XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + +INTRINSIC_XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zd + +INTRINSIC_XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + +INTRINSIC_XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zd + +INTRINSIC_XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 +VL128 + i16 w dq + i1 r mskw + i32 r dq + i32 r dq + +INTRINSIC_XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 +VL128 + i16 w dq + i1 r mskw + i32 r dq + i32 r vv + +INTRINSIC_XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 +VL256 + i16 w qq + i1 r mskw + i32 r qq + i32 r qq + +INTRINSIC_XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 +VL256 + i16 w qq + i1 r mskw + i32 r qq + i32 r vv + +INTRINSIC_XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i32 r zi32 + i32 r zi32 + +INTRINSIC_XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i32 r zi32 + i32 r vv + +INTRINSIC_XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i8 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i8 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i8 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i8 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u16 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u16 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u16 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u16 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u8 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u8 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u8 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u8 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zi8 + +INTRINSIC_XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zd + +INTRINSIC_XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r b + +INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r d + +INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r b + +INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r d + +INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r b + +INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r d + +INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r wrd + +INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r d + +INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r wrd + +INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r d + +INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r wrd + +INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r d + +INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i8 r zi8 + i8 r zi8 + +INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i8 r zi8 + i8 r zd + +INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 +VL128 + i1 w mskw + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 +VL256 + i1 w mskw + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 +VL512 + i1 w mskw + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 +VL128 + u8 w d + u8 r dq + +INTRINSIC_XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 +VL128 + u8 w b + u8 r dq + +INTRINSIC_XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 +VL128 + u32 w d + u32 r dq + +INTRINSIC_XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 +VL128 + u32 w d + u32 r dq + +INTRINSIC_XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 +VL128 + u64 w q + u64 r dq + +INTRINSIC_XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 +VL128 + u64 w q + u64 r dq + +INTRINSIC_XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 +VL128 + u16 w d + u16 r dq + +INTRINSIC_XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 +VL128 + u16 w wrd + u16 r dq + +INTRINSIC_XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 +VL128 + u16 w d + u16 r dq + +INTRINSIC_XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 +VL128 + u8 w dq + u8 r dq + u8 r d + +INTRINSIC_XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 +VL128 + u8 w dq + u8 r dq + u8 r b + +INTRINSIC_XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 +VL128 + u32 w dq + u32 r dq + u32 r d + +INTRINSIC_XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + u32 r dq + u32 r d + +INTRINSIC_XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 +VL128 + u64 w dq + u64 r dq + u64 r q + +INTRINSIC_XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + u64 r dq + u64 r q + +INTRINSIC_XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 +VL128 + u16 w dq + u16 r dq + u16 r d + +INTRINSIC_XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + u16 r dq + u16 r wrd + +INTRINSIC_XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i32 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i32 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i32 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i32 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i32 w zi32 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zi8 + +INTRINSIC_XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zd + +INTRINSIC_XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zi8 + +INTRINSIC_XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zd + +INTRINSIC_XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512 +VL128 + i1 w mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512 +VL256 + i1 w mskw + u8 r qq + +INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512 +VL512 + i1 w mskw + u8 r zu8 + +INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512 +VL128 + i1 w mskw + u32 r dq + +INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512 +VL256 + i1 w mskw + u32 r qq + +INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512 +VL512 + i1 w mskw + u32 r zu32 + +INTRINSIC_XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512 +VL128 + u8 w dq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512 +VL256 + u8 w qq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512 +VL512 + u8 w zu8 + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512 +VL128 + u32 w dq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512 +VL256 + u32 w qq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512 +VL512 + u32 w zu32 + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512 +VL128 + u64 w dq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512 +VL256 + u64 w qq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512 +VL512 + u64 w zu64 + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512 +VL128 + u16 w dq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512 +VL256 + u16 w qq + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512 +VL512 + u16 w zu16 + i1 r mskw + +INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512 +VL128 + i1 w mskw + u64 r dq + +INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512 +VL256 + i1 w mskw + u64 r qq + +INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512 +VL512 + i1 w mskw + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 +VL128 + i8 w dq + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 +VL128 + i8 w q + i1 r mskw + i16 r dq + +INTRINSIC_XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 +VL256 + i8 w dq + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 +VL256 + i8 w dq + i1 r mskw + i16 r qq + +INTRINSIC_XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 +VL512 + i8 w qq + i1 r mskw + i16 r zi16 + +INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 +VL512 + i8 w qq + i1 r mskw + i16 r zi16 + +INTRINSIC_XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 +VL128 + i16 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 +VL128 + i16 w dq + i1 r mskw + i8 r q + +INTRINSIC_XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 +VL256 + i16 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 +VL256 + i16 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i8 r qq + +INTRINSIC_XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i8 r qq + +INTRINSIC_XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 +VL128 + u8 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 +VL128 + u8 w q + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 +VL256 + u8 w dq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 +VL256 + u8 w dq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 +VL512 + u8 w qq + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 +VL512 + u8 w qq + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512 +VL128 + i1 w mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512 +VL256 + i1 w mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512 +VL512 + i1 w mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 +VL128 + u8 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 +VL128 + u8 w q + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 +VL256 + u8 w dq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 +VL256 + u8 w dq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 +VL512 + u8 w qq + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 +VL512 + u8 w qq + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 +VL128 + i16 w dq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 +VL128 + i16 w dq + i1 r mskw + i8 r q + +INTRINSIC_XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 +VL256 + i16 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 +VL256 + i16 w qq + i1 r mskw + i8 r dq + +INTRINSIC_XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i8 r qq + +INTRINSIC_XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i8 r qq + +INTRINSIC_XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 +VL128 + u16 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 +VL128 + u16 w dq + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 +VL256 + u16 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 +VL256 + u16 w qq + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 +VL512 + u16 w zu16 + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 +VL512 + u16 w zu16 + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 +VL128 + u8 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 +VL128 + u8 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 +VL256 + u8 w qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 +VL256 + u8 w qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 +VL512 + u8 w zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 +VL512 + u8 w zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r dq + +INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r dq + +INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 +VL128 + u8 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 +VL128 + u8 w dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 +VL256 + u8 w qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 +VL256 + u8 w qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 +VL512 + u8 w zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 +VL512 + u8 w zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r dq + +INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +VL128 + i8 w dq + i1 r mskw + i8 r dq + i8 r dq + +INTRINSIC_XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +VL256 + i8 w qq + i1 r mskw + i8 r qq + i8 r qq + +INTRINSIC_XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zi8 + +INTRINSIC_XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +VL512 + i8 w zi8 + i1 r mskw + i8 r zi8 + i8 r zd + +INTRINSIC_XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +VL128 + i16 w dq + i1 r mskw + i16 r dq + i16 r dq + +INTRINSIC_XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +VL256 + i16 w qq + i1 r mskw + i16 r qq + i16 r qq + +INTRINSIC_XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zi16 + +INTRINSIC_XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +VL512 + i16 w zi16 + i1 r mskw + i16 r zi16 + i16 r zd + +INTRINSIC_XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + i1 w mskw + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + i1 w mskw + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + i1 w mskw + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + f64 r vv + +INTRINSIC_XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r qq + +INTRINSIC_XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + f64 r vv + +INTRINSIC_XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r zf64 + +INTRINSIC_XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + f64 r vv + +INTRINSIC_XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + f32 r vv + +INTRINSIC_XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r qq + +INTRINSIC_XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + f32 r vv + +INTRINSIC_XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r zf32 + +INTRINSIC_XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + f32 r vv + +INTRINSIC_XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r dq + +INTRINSIC_XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL128 + f64 w dq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r qq + +INTRINSIC_XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL256 + f64 w qq + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r zf64 + +INTRINSIC_XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +VL512 + f64 w zf64 + i1 r mskw + f64 r vv + +INTRINSIC_XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r dq + +INTRINSIC_XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL128 + f32 w dq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r qq + +INTRINSIC_XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL256 + f32 w qq + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r zf32 + +INTRINSIC_XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +VL512 + f32 w zf32 + i1 r mskw + f32 r vv + +INTRINSIC_XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r dq + +INTRINSIC_XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 + f64 w dq + i1 r mskw + f64 r dq + f64 r q + +INTRINSIC_XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r dq + +INTRINSIC_XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 + f32 w dq + i1 r mskw + f32 r dq + f32 r d + +INTRINSIC_XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 rw dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 rw dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 rw qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 rw qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 rw zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 rw zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 rw dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 rw dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 rw qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 rw qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 rw zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 rw zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u64 r vv + +INTRINSIC_XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + +INTRINSIC_XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zd + +INTRINSIC_XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512 +VL128 + i1 w mskw + i1 r mskw + u64 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512 +VL256 + i1 w mskw + i1 r mskw + u64 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u8 r zu8 + +INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512 +VL512 + i1 w mskw + i1 r mskw + u64 r zu64 + u8 r zd + +INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512 +VL512 + u8 w zd + i1 r mskw + u8 r zu8 + +INTRINSIC_XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + +INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512 +VL512 + u16 w zd + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + +INTRINSIC_XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + +INTRINSIC_XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zd + +INTRINSIC_XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + +INTRINSIC_XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + +INTRINSIC_XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + +INTRINSIC_XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zd + +INTRINSIC_XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +VL128 + u32 w dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +VL256 + u32 w qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +VL512 + u32 w zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +VL128 + u64 w dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +VL256 + u64 w qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u64 w zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + u32 rw dq + i1 r mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + u32 rw qq + i1 r mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + u32 rw zu32 + i1 r mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + u64 rw dq + i1 r mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + u64 rw qq + i1 r mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + u64 rw zu64 + i1 r mskw + u64 r zu64 + u64 r vv + +INTRINSIC_XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +VL128 + u16 rw dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +VL256 + u16 rw qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +VL512 + u16 rw zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 +VL128 + u16 w dq + i1 r mskw + u16 r dq + u16 r dq + +INTRINSIC_XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 +VL256 + u16 w qq + i1 r mskw + u16 r qq + u16 r qq + +INTRINSIC_XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zu16 + +INTRINSIC_XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 +VL512 + u16 w zu16 + i1 r mskw + u16 r zu16 + u16 r zd + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u64 r zu64 + +INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u64 r vv + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u64 r zu64 + +INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u64 r vv + +INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +VL128 + u8 w dq + i1 r mskw + u8 r dq + u8 r dq + +INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +VL256 + u8 w qq + i1 r mskw + u8 r qq + u8 r qq + +INTRINSIC_XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zu8 + +INTRINSIC_XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +VL512 + u8 w zu8 + i1 r mskw + u8 r zu8 + u8 r zd + +INTRINSIC_XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zu128 + +INTRINSIC_XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zd + +INTRINSIC_XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zu128 + +INTRINSIC_XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zd + +INTRINSIC_XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zu128 + +INTRINSIC_XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zd + +INTRINSIC_XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512 +VL128 + u128 w dq + u128 r dq + u128 r dq + +INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512 +VL256 + u128 w qq + u128 r qq + u128 r qq + +INTRINSIC_XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zu128 + +INTRINSIC_XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512 +VL512 + u128 w zu128 + u128 r zu128 + u128 r zd + +INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512 +VL128 + u128 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 +VL128 + u128 w dq + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 +VL256 + u128 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 +VL256 + u128 w qq + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 +VL512 + u128 w zu128 + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 +VL512 + u128 w zu128 + u64 r zu64 + u64 r zd + +INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512 +VL128 + i1 w mskw + u32 r dq + u32 r dq + +INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512 +VL128 + i1 w mskw + u32 r dq + u32 r vv + +INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512 +VL256 + i1 w mskw + u32 r qq + u32 r qq + +INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512 +VL256 + i1 w mskw + u32 r qq + u32 r vv + +INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512 +VL512 + i1 w mskw + u32 r zu32 + u32 r zu32 + +INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512 +VL512 + i1 w mskw + u32 r zu32 + u32 r vv + +INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512 +VL128 + i1 w mskw + u64 r dq + u64 r dq + +INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512 +VL128 + i1 w mskw + u64 r dq + u64 r vv + +INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512 +VL256 + i1 w mskw + u64 r qq + u64 r qq + +INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512 +VL256 + i1 w mskw + u64 r qq + u64 r vv + +INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512 +VL512 + i1 w mskw + u64 r zu64 + u64 r zu64 + +INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512 +VL512 + i1 w mskw + u64 r zu64 + u64 r vv + diff --git a/arch/x86/code_generator/parse-iform-types.py b/arch/x86/code_generator/parse-iform-types.py new file mode 100755 index 00000000..27631d2a --- /dev/null +++ b/arch/x86/code_generator/parse-iform-types.py @@ -0,0 +1,452 @@ +#!/usr/bin/env python3 + +# These are not real registers and should be excluded from the intrinsic types +XED_INVALID_OPERAND_REGISTERS = { + 'XED_REG_INVALID', + 'XED_REG_MSRS', + 'XED_REG_STACKPUSH', + 'XED_REG_STACKPOP', + 'XED_REG_ERROR', + 'XED_REG_LAST', +} + +class TypeCacher(): + + def __init__(self, name): + self.cached_types = [] + self.name = name + + def get_cached_type_str(self, type_str): + try: + cached_type_str = 'X86CommonArchitecture::cached_%s_types[%d]' % (self.name, self.cached_types.index(type_str)) + except: + self.cached_types.append(type_str) + cached_type_str = 'X86CommonArchitecture::cached_%s_types[%d]' % (self.name, len(self.cached_types) - 1) + + return cached_type_str + + def dump_to_file(self, decl_path): + with open(decl_path, 'w') as output: + output.write('// Generated file, please do not edit directly\n\n') + type_id_str = self.cached_types[0].split(' ')[0] + n = len(self.cached_types) + output.write(f'X86CommonArchitecture::cached_{self.name}_types = new {type_id_str}[{n}];\n') + for idx, cached_type in enumerate(self.cached_types): + output.write(f'X86CommonArchitecture::cached_{self.name}_types[{idx}] = {cached_type};\n') + +class CodeGenerator(): + + def __init__(self, path, vector_element_name, enclose_element_with, name, rw): + self.file = open(path, 'w') + self.write_header() + self.vector_element_name = vector_element_name + self.enclose_element_with = enclose_element_with + self.rw = rw + self.name = name + self.type_cacher = TypeCacher(name) + # if you do not exclude these, when you run code like `Architecture['x86_64']`, + # if will create integer of size 576 + self.excluded_intrinsics = [ + 'INTRINSIC_XED_IFORM_XSAVE_MEMmxsave', + 'INTRINSIC_XED_IFORM_XSAVE64_MEMmxsave', + 'INTRINSIC_XED_IFORM_XSAVEOPT_MEMmxsave', + 'INTRINSIC_XED_IFORM_XSAVEOPT64_MEMmxsave', + 'INTRINSIC_XED_IFORM_XSAVES_MEMmxsave', + 'INTRINSIC_XED_IFORM_XSAVES64_MEMmxsave', + 'INTRINSIC_XED_IFORM_XSAVEC_MEMmxsave', + 'INTRINSIC_XED_IFORM_XSAVEC64_MEMmxsave', + 'INTRINSIC_XED_IFORM_XRSTOR_MEMmxsave', + 'INTRINSIC_XED_IFORM_XRSTOR64_MEMmxsave', + 'INTRINSIC_XED_IFORM_XRSTORS_MEMmxsave', + 'INTRINSIC_XED_IFORM_XRSTORS64_MEMmxsave', + ] + + def clean_up(self): + self.file.close() + + def write_header(self): + self.file.write('// Generated file, please do not edit directly\n\n') + + def generate_intrinsic(self, ins): + + if ins.iform in self.excluded_intrinsics: + return + + s = 'case %s:' % ins.iform + s += '\n\treturn ' + return_str = 'vector<%s> ' % self.vector_element_name + return_str += '{ ' + for operand in ins.operands: + if not self.rw in operand.rw: + continue + + op_str = operand.generate_str() + + if self.enclose_element_with == '': + return_str += '%s, ' % op_str + else: + return_str += '%s(%s), ' % (self.enclose_element_with, op_str) + + if return_str.endswith(', '): + return_str = return_str[:-2] + + return_str += ' }' + return_str = self.type_cacher.get_cached_type_str(return_str) + s += return_str + s += ';\n' + self.file.write(s) + + def dump_cached_types(self): + self.type_cacher.dump_to_file(f'../x86_intrinsic_cached_{self.name}_types.include') + +class Intrinsic(): + def __init__(self): + self.iform = '' + self.operands = [] + self.vl = None + + def reset(self): + self.iform = '' + self.operands = [] + self.vl = None + + def set_iform(self, iform): + self.iform = iform + + def set_VL(self, vl): + self.vl = vl + + def add_operand(self, operand): + if operand.oc2 == 'vv': + if self.vl is None: + print('cannot determine number of elements') + # more info goes here + else: + operand.oc2 = self.vl + elif operand.oc2 in XED_INVALID_OPERAND_REGISTERS: + # These are not real registers + return + + operand.parse() + self.operands.append(operand) + +class Operand(): + + def __init__(self, xtype, rw, oc2): + self.xtype = xtype + self.rw = rw + self.oc2 = oc2 + + def parse(self): + # from build/obj/dgen/all-element-types.txt + # #XTYPE TYPE BITS-PER-ELEM + # # + # var VARIABLE 0 # instruction must set NELEM and ELEMENT_SIZE + # struct STRUCT 0 # many elements of different widths + # int INT 0 # one element, all the bits, width varies + # uint UINT 0 # one element, all the bits, width varies + # # + # i1 INT 1 + # i8 INT 8 + # i16 INT 16 + # i32 INT 32 + # i64 INT 64 + # u8 UINT 8 + # u16 UINT 16 + # u32 UINT 32 + # u64 UINT 64 + # u128 UINT 128 + # u256 UINT 256 + # f32 SINGLE 32 + # f64 DOUBLE 64 + # f80 LONGDOUBLE 80 + # b80 LONGBCD 80 + + self.signed = (self.xtype[0] == 'i') + + if self.xtype[0] == 'f': + self.type = 'float' + elif self.xtype == 'i1': + self.type = 'boolean' + else: + self.type = 'int' + + # thse lengths are obtained from A.2.2 Codes for Operand Type + # of the Intel Dev Manual Volume 2 + # See comment inside for varying sizes + size_mapping = { + 'f80': 80, + 'mem32real': 32, + 'mem64real': 64, + 'mem80real': 80, + 'm32real': 32, + 'm32int': 32, + 'm64real': 64, + 'm64int': 32, + 'm80real': 80, + 'mskw': 1, + 'mem14': 14 * 8, + 'mem28': 28 * 8, + 'mem16': 16 * 8, + 'mem94': 94 * 8, + 'mem108': 108 * 8, + 'mem32int': 32, + 'mem16int': 16, + "mem80dec": 80, + 'b': 8, + 'w': 16, + 'd': 32, + 'q': 64, + 'u64': 64, + 'dq': 128, + 'qq': 256, + 'zd': 512, + 'zu8': 512, + 'zi8': 512, + 'zi16': 512, + 'zu16': 512, + 'zuf64': 512, + 'zuf32': 512, + 'zf32': 512, + 'zf64': 512, + 'zi64': 512, + 'zu64': 512, + 'zu128': 512, + 'zi32': 512, + 'zu32': 512, + 'VL512': 512, + 'VL256': 256, + 'VL128': 128, + 'ss': 128, + 'sd': 128, + 'ps': 128, + 'pd': 128, + 'zbf16': 16, + 's': 80, + 's64': 64, + 'a16': 16, + 'a32': 32, + 'xud': 128, + 'xuq': 128, + + # The specifiers below actually map to variable sizes, e.g., v can be + # "Word, doubleword or quadword (in 64-bit mode), depending on operand-size attribute". + # However, instructions that contain such operands are mostly covered by explicit liftings, + # for example, add, sub, and mov, etc. So they do not mess up the types + # Excpetions are lzcnt, tzcnt, popcnt, and crc32, + # which have to be further splitted into various finer-grained intrinsics + 'v': 32, + 'z': 32, + 'y': 64, + + # below specifiers are not found in the list, their size are determined manually + 'spw': 32, + 'spw8': 32, + 'spw2': 32, + 'spw3': 32, + 'spw5': 32, + 'wrd': 16, + 'bnd32': 32, + 'bnd64': 64, + 'p': 64, + 'p2': 64, + 'mfpxenv': 512 * 8, + 'mxsave': 576 * 8, + 'mprefetch': 64, + 'pmmsz16': 14 * 8, + 'pmmsz32': 24 * 8, + + 'rFLAGS': 64, + 'eFLAGS': 32, + 'GPR64_R': 64, + 'GPR64_B': 64, + 'GPRv_R': 64, + 'GPRv_B': 64, + 'GPR32_R': 32, + 'GPR32_B': 32, + 'GPR16_R': 16, + 'GPR16_B': 16, + 'GPR8_R': 8, + 'GPR8_B': 8, + 'GPRy_B': 64, + 'GPRz_B': 64, + 'GPRz_R': 64, + 'GPR8_SB': 64, + 'A_GPR_R': 64, + 'A_GPR_B': 64, + 'GPRv_SB': 64, + 'BND_R': 64, + 'BND_B': 64, + 'OeAX': 16, + 'OrAX': 16, + 'OrBX': 16, + 'OrCX': 16, + 'OrDX': 16, + 'OrBP': 16, + 'OrSP': 16, + 'ArAX': 16, + 'ArBX': 16, + 'ArCX': 16, + 'ArDI': 16, + 'ArSI': 16, + 'ArBP': 16, + 'FINAL_SSEG0': 16, + 'FINAL_SSEG1': 16, + 'FINAL_DSEG': 16, + 'FINAL_DSEG0': 16, + 'FINAL_DSEG1': 16, + 'FINAL_ESEG': 16, + 'FINAL_ESEG1': 16, + 'SEG': 16, + 'SEG_MOV': 16, + 'SrSP': 64, + 'rIP': 64, + 'CR_R': 32, + 'DR_R': 32, + 'XED_REG_AL': 8, + 'XED_REG_AH': 8, + 'XED_REG_BL': 8, + 'XED_REG_BH': 8, + 'XED_REG_CL': 8, + 'XED_REG_DL': 8, + + 'XED_REG_AX': 16, + 'XED_REG_BX': 16, + 'XED_REG_CX': 16, + 'XED_REG_DX': 16, + 'XED_REG_BP': 16, + 'XED_REG_SP': 16, + 'XED_REG_SI': 16, + 'XED_REG_DI': 16, + 'XED_REG_SS': 16, + 'XED_REG_DS': 16, + 'XED_REG_ES': 16, + 'XED_REG_IP': 16, + 'XED_REG_FS': 16, + 'XED_REG_GS': 16, + 'XED_REG_CS': 16, + + 'XED_REG_EAX': 32, + 'XED_REG_EBX': 32, + 'XED_REG_ECX': 32, + 'XED_REG_EDX': 32, + 'XED_REG_EIP': 32, + 'XED_REG_ESP': 32, + 'XED_REG_EBP': 32, + 'XED_REG_ESI': 32, + 'XED_REG_EDI': 32, + + 'XED_REG_RAX': 64, + 'XED_REG_RBX': 64, + 'XED_REG_RCX': 64, + 'XED_REG_RDX': 64, + 'XED_REG_RIP': 64, + 'XED_REG_RSP': 64, + 'XED_REG_RBP': 64, + 'XED_REG_RSI': 64, + 'XED_REG_RDI': 64, + 'XED_REG_R11': 64, + + 'XED_REG_X87STATUS': 16, + 'XED_REG_X87CONTROL': 16, + 'XED_REG_X87TAG': 16, + 'XED_REG_X87PUSH': 64, + 'XED_REG_X87POP': 64, + 'XED_REG_X87POP2': 64, + + 'XED_REG_CR0': 64, + 'XED_REG_XCR0': 64, + 'XED_REG_MXCSR': 32, + + 'XED_REG_GDTR': 48, + 'XED_REG_LDTR': 48, + 'XED_REG_IDTR': 48, + + 'XED_REG_TR': 64, + 'XED_REG_TSC': 64, + 'XED_REG_TSCAUX': 64, + 'XED_REG_MSRS': 64, + } + + # if '_' in self.oc2: + # self.oc2 = self.oc2.split('_')[0] + + try: + self.width = size_mapping[self.oc2] + except: + print('I do not know the width of oc2: %s' % self.oc2) + self.width = 8 + + if self.xtype == 'struct' or self.xtype == 'INVALID': + self.element_size = self.width + elif self.xtype == 'int': + self.element_size = 32 + elif self.xtype == 'bf16': + self.element_size = 16 + else: + size_str = self.xtype[1:] + self.element_size = int(size_str) + + self.element_size_byte = int((self.element_size + 7) / 8) + + n = int((self.width + 7) / 8) / self.element_size_byte + n = int(n) + + if n < 1: + n = 1 + + self.n_element = n + + def generate_str(self): + array = False + if self.element_size > 1: + array = True + + inner_str = '' + if self.type == 'float': + inner_str = 'Type::FloatType(%d)' % self.element_size_byte + elif self.type == 'int': + signed_str = 'true' if self.signed else 'false' + inner_str = 'Type::IntegerType(%d, %s)' % (self.element_size_byte, signed_str) + else: + inner_str = 'Type::BoolType()' + + if self.n_element > 1: + s = 'Type::ArrayType(%s, %d)' % (inner_str, self.n_element) + else: + s = inner_str + + return s + +def main(): + intrinsic_input = CodeGenerator('../x86_intrinsic_input_type.include', 'NameAndType', 'NameAndType', 'input', 'r') + intrinsic_output = CodeGenerator('../x86_intrinsic_output_type.include', 'Confidence<Ref<Type>>', '', 'output', 'w') + with open('iform-type-dump.txt', 'r') as f: + ins = Intrinsic() + for line in f: + if line.strip() == '': + intrinsic_input.generate_intrinsic(ins) + intrinsic_output.generate_intrinsic(ins) + ins.reset() + continue + + if line.startswith('INTRINSIC_XED_IFORM_'): + ins.set_iform(line.strip()) + elif line.startswith('VL'): + ins.set_VL(line.strip()) + elif line.startswith('\t'): + fields = line.strip().split('\t') + op = Operand(fields[0], fields[1], fields[2]) + ins.add_operand(op) + else: + print('unexpected line! I do not know what to do with it') + print(line) + + intrinsic_input.dump_cached_types() + intrinsic_output.dump_cached_types() + + intrinsic_input.clean_up() + intrinsic_output.clean_up() + +if __name__ == '__main__': + main() diff --git a/arch/x86/code_generator/patch.diff b/arch/x86/code_generator/patch.diff new file mode 100644 index 00000000..1b22e5b6 --- /dev/null +++ b/arch/x86/code_generator/patch.diff @@ -0,0 +1,43 @@ +diff --git a/pysrc/generator.py b/pysrc/generator.py +index f2fcd93..fff7e6b 100755 +--- a/pysrc/generator.py ++++ b/pysrc/generator.py +@@ -6342,6 +6342,38 @@ def main(): + agi.close_output_files() + agi.dump_generated_files() + ++ generated_iforms = set() ++ with open('iform-type-dump.txt', 'w') as f: ++ for generator in agi.generator_list: ++ ii = generator.parser_output.instructions[0] ++ if not field_check(ii,'iclass'): ++ continue ++ for ii in generator.parser_output.instructions: ++ ++ if ii.iform_enum in generated_iforms: ++ continue ++ else: ++ generated_iforms.add(ii.iform_enum) ++ ++ f.write('INTRINSIC_XED_IFORM_' + ii.iform_enum) ++ f.write('\n') ++ s = str(ii.ipattern_input) ++ for field in s.split(' '): ++ if field.startswith('VL'): ++ f.write(field + '\n') ++ ++ for operand in ii.operands: ++ # if operand.xtype != None and operand.xtype != 'INVALID': ++ if operand.xtype != None: ++ width_hint = '' ++ if operand.oc2 != None: ++ width_hint = str(operand.oc2) ++ elif operand.lookupfn_name != None: ++ width_hint = str(operand.lookupfn_name) ++ if width_hint != '': ++ f.write('\t' + str(operand.xtype) + '\t' + operand.rw + '\t' + width_hint + '\n') ++ f.write('\n') ++ + ################################################ + + if __name__ == '__main__': diff --git a/arch/x86/il.cpp b/arch/x86/il.cpp new file mode 100644 index 00000000..136674e1 --- /dev/null +++ b/arch/x86/il.cpp @@ -0,0 +1,4195 @@ +#include <inttypes.h> +#include "il.h" +#include "lowlevelilinstruction.h" +#include "arch_x86_common_architecture.h" + +using namespace BinaryNinja; +using namespace std; + + +static xed_reg_enum_t GetStackPointer(const size_t addrSize) +{ + switch (addrSize) + { + case 2: + return XED_REG_SP; + case 4: + return XED_REG_ESP; + default: + return XED_REG_RSP; + } +} + + +static xed_reg_enum_t GetFramePointer(const size_t addrSize) +{ + switch (addrSize) + { + case 2: + return XED_REG_BP; + case 4: + return XED_REG_EBP; + default: + return XED_REG_RBP; + } +} + + +static xed_reg_enum_t GetCountRegister(const size_t addrSize) +{ + switch (addrSize) + { + case 2: + return XED_REG_CX; + case 4: + return XED_REG_ECX; + default: + return XED_REG_RCX; + } +} + +//TODO handle imms for MPX args +// For most instructions, instruction_index == operand_index, but some instructions (floating point, some others) have an implicit first operand (st0), so we have to remap things a bit +// Instruction index represents the 'nth' argument/opcode in the instruction, whereas the operand index is index that XED holds that operand in the instruction +static size_t GetILOperandMemoryAddress(LowLevelILFunction& il, const xed_decoded_inst_t* xedd, const uint64_t addr, const size_t instruction_index, const size_t operand_index) +{ + const xed_inst_t* xi = xed_decoded_inst_inst(xedd); + const xed_operand_t* op = xed_inst_operand(xi, (unsigned)operand_index); + const xed_operand_values_t* ov = xed_decoded_inst_operands_const(xedd); + const xed_operand_enum_t op_name = xed_operand_name(op); + size_t offset = BN_INVALID_EXPR; + const size_t addrSize = xed_decoded_inst_get_machine_mode_bits(xedd) / 8; + + switch(op_name) + { + case XED_OPERAND_AGEN: + case XED_OPERAND_MEM0: + { + const int64_t disp = xed_decoded_inst_get_memory_displacement(xedd, 0); + + // [reg] if reg != instruction_pointer + const xed_reg_enum_t base = xed_decoded_inst_get_base_reg(xedd, 0); + if ((base != XED_REG_INVALID) && !((base == XED_REG_RIP) || (base == XED_REG_EIP) || (base == XED_REG_IP))) + { + offset = il.Register(addrSize, base); + } + else if ((base == XED_REG_RIP) || (base == XED_REG_EIP) || (base == XED_REG_IP)) // Resolve RIP to a constant + { + if (xed_operand_values_has_memory_displacement(ov) && (disp != 0)) + return il.Operand(instruction_index, il.ConstPointer(addrSize, disp + addr + xed_decoded_inst_get_length(xedd))); + else + return il.Operand(instruction_index, il.ConstPointer(addrSize, addr + xed_decoded_inst_get_length(xedd))); + } + + // [...+reg] or [...+reg*const] or [reg*const] + const xed_reg_enum_t index = xed_decoded_inst_get_index_reg(xedd, 0); + bool constIsPointer = false; + if (index != XED_REG_INVALID) + if (!xed_decoded_inst_get_attribute(xedd, XED_ATTRIBUTE_INDEX_REG_IS_POINTER)) // MPX...TODO (extra registers) + { + const unsigned int scale = xed_decoded_inst_get_scale(xedd, 0); + if (scale != 1) + { + unsigned short shift = 0; + if (scale == 2) + shift = 1; + else if (scale == 4) + shift = 2; + else if (scale == 8) + shift = 3; + if (offset != BN_INVALID_EXPR) + offset = il.Add(addrSize, + offset, + il.ShiftLeft(addrSize, + il.Register(addrSize, index), + il.Const(1, shift))); + else + { + // case for [...+reg*const] so we know that the const must be a pointer + constIsPointer = true; + offset = il.ShiftLeft(addrSize, + il.Register(addrSize, index), + il.Const(1, shift)); + } + } + else + if (offset != BN_INVALID_EXPR) + offset = il.Add(addrSize, + offset, + il.Register(addrSize, index)); + else + offset = il.Register(addrSize, index); + } + + // The [...+const] bit or just [const] + bool isJmpClass = (XED_ICLASS_JMP == xed_decoded_inst_get_iclass(xedd)) || constIsPointer; + if (xed_operand_values_has_memory_displacement(xed_decoded_inst_operands_const(xedd)) && (disp != 0)) + { + if (offset != BN_INVALID_EXPR) + offset = il.Add(addrSize, offset, isJmpClass ? il.ConstPointer(addrSize, disp) : il.Const(addrSize, disp)); + else + offset = isJmpClass ? il.ConstPointer(addrSize, disp) : il.Const(addrSize, disp); + } + else if (xed_operand_values_has_memory_displacement(xed_decoded_inst_operands_const(xedd)) && (disp == 0) && (offset == BN_INVALID_EXPR)) + { + offset = isJmpClass ? il.ConstPointer(addrSize, disp) : il.Const(addrSize, disp); + } + + // If there's a non-default segment in use + xed_reg_enum_t seg = xed_decoded_inst_get_seg_reg(xedd, 0); + if (seg != XED_REG_INVALID && !xed_operand_values_using_default_segment(ov, 0)) + { + // Remap FS/GS to FSbase/GSbase respectively + if (seg == XED_REG_FS) + seg = XED_REG_FSBASE; + else if (seg == XED_REG_GS) + seg = XED_REG_GSBASE; + + if (offset == BN_INVALID_EXPR) // The only logical path that brings us here with an invalid offset is a disp of 0 + offset = il.Register(addrSize, seg); + else + offset = il.Add(addrSize, il.Register(addrSize, seg), offset); + } + + break; + } + + case XED_OPERAND_MEM1: + { + const xed_reg_enum_t base = xed_decoded_inst_get_base_reg(xedd, 1); + if (base != XED_REG_INVALID) + { + if ((base == XED_REG_RIP) || (base == XED_REG_EIP) || (base == XED_REG_IP)) + offset = il.ConstPointer(addrSize, addr); + else + offset = il.Register(addrSize, base); + } + + xed_reg_enum_t seg = xed_decoded_inst_get_seg_reg(xedd, 1); + if (seg != XED_REG_INVALID && !xed_operand_values_using_default_segment(ov, 1)) + { + if (seg == XED_REG_FS) + seg = XED_REG_FSBASE; + else if (seg == XED_REG_GS) + seg = XED_REG_GSBASE; + + offset = il.Add(addrSize, + il.Register(addrSize, seg), + offset); + } + break; + } + + default: + LogError("%s not implemented in GetILOperandMemoryAddress at address 0x%" PRIx64 ".", xed_operand_enum_t2str(op_name), addr); + } + + return il.Operand(instruction_index, offset); +} + + +// For most instructions, instruction_index == operand_index, but some instructions (floating point, some others) have an implicit first operand (st0), so we have to remap things a bit +// Instruction index represents the 'nth' argument/opcode in the instruction, whereas the operand index is index that XED holds that operand in the instruction +static size_t ReadILOperand(LowLevelILFunction& il, const xed_decoded_inst_t* const xedd, + const size_t addr, const size_t instruction_index, + const size_t operand_index, size_t sizeToRead = 0) +{ + if (sizeToRead == 0) + sizeToRead = xed_decoded_inst_operand_length_bits(xedd, (unsigned)operand_index) / 8; + const unsigned int immediateSize = xed_decoded_inst_get_operand_width(xedd) / 8; + const int64_t relbr = xed_decoded_inst_get_branch_displacement(xedd) + addr + xed_decoded_inst_get_length(xedd); + const xed_operand_enum_t op_name = xed_operand_name(xed_inst_operand(xed_decoded_inst_inst(xedd), (unsigned)operand_index)); + const auto reg1 = xed_decoded_inst_get_reg(xedd, op_name); + const size_t addrSize = xed_decoded_inst_get_machine_mode_bits(xedd) / 8; + + switch (op_name) + { + // Register cases + case XED_OPERAND_REG0: + case XED_OPERAND_REG1: + case XED_OPERAND_REG2: + case XED_OPERAND_REG3: + case XED_OPERAND_REG4: + case XED_OPERAND_REG5: + case XED_OPERAND_REG6: + case XED_OPERAND_REG7: + case XED_OPERAND_REG8: + case XED_OPERAND_BASE0: + case XED_OPERAND_BASE1: + if ((reg1 == XED_REG_RIP) || (reg1 == XED_REG_EIP) || (reg1 == XED_REG_IP)) + return il.Operand(instruction_index, il.ConstPointer(sizeToRead, addr)); + return il.Operand(instruction_index, il.Register(sizeToRead, (uint32_t)reg1)); + + // Immediates: + case XED_OPERAND_IMM0: + if (xed_decoded_inst_get_immediate_is_signed(xedd)) + return il.Operand(instruction_index, il.Const(immediateSize, xed_decoded_inst_get_signed_immediate(xedd))); + else + return il.Operand(instruction_index, il.Const(immediateSize, xed_decoded_inst_get_unsigned_immediate(xedd))); + + // Second Immdiate Value + case XED_OPERAND_IMM1: + return il.Operand(instruction_index, il.Const(1, xed_decoded_inst_get_second_immediate(xedd))); + + // Immediate Address Value + case XED_OPERAND_PTR: + case XED_OPERAND_RELBR: + return il.Operand(instruction_index, il.ConstPointer(addrSize, relbr)); + + // Memory Acesses + case XED_OPERAND_AGEN: + case XED_OPERAND_MEM0: + case XED_OPERAND_MEM1: + return il.Operand(instruction_index, il.Load(sizeToRead, GetILOperandMemoryAddress(il, xedd, addr, instruction_index, operand_index))); + + // Not implimented or error + default: + return il.Undefined(); + } +} + + +// For most instructions, instruction_index == operand_index, but some instructions (floating point, some others) have an implicit first operand (st0), so we have to remap things a bit +// Instruction index represents the 'nth' argument/opcode in the instruction, whereas the operand index is index that XED holds that operand in the instruction +static size_t ReadFloatILOperand(LowLevelILFunction& il, const xed_decoded_inst_t* xedd, const size_t addr, const size_t instruction_index, const size_t operand_index, size_t opLen = 10) +{ + const unsigned int operandSize = xed_decoded_inst_operand_length_bits(xedd, (unsigned)operand_index) / 8; + const xed_operand_enum_t op_name = xed_operand_name(xed_inst_operand(xed_decoded_inst_inst(xedd), (unsigned)operand_index)); + + switch (op_name) + { + // Register cases + case XED_OPERAND_REG0: + case XED_OPERAND_REG1: + case XED_OPERAND_REG2: + case XED_OPERAND_REG3: + case XED_OPERAND_REG4: + case XED_OPERAND_REG5: + case XED_OPERAND_REG6: + case XED_OPERAND_REG7: + case XED_OPERAND_REG8: + case XED_OPERAND_BASE0: + case XED_OPERAND_BASE1: + return il.Operand(instruction_index, il.Register(operandSize, (uint32_t)xed_decoded_inst_get_reg(xedd, op_name))); + + // Immediates + case XED_OPERAND_IMM0: + case XED_OPERAND_PTR: + case XED_OPERAND_RELBR: + if (xed_decoded_inst_get_immediate_is_signed(xedd)) + return il.Operand(instruction_index, il.FloatConvert(opLen, il.FloatConstRaw(operandSize, xed_decoded_inst_get_signed_immediate(xedd)))); + else + return il.Operand(instruction_index, il.FloatConvert(opLen, il.FloatConstRaw(operandSize, xed_decoded_inst_get_unsigned_immediate(xedd)))); + case XED_OPERAND_IMM1: + return il.Operand(instruction_index, il.FloatConvert(opLen, il.FloatConstRaw(operandSize, xed_decoded_inst_get_second_immediate(xedd)))); + + // Memory Acesses + case XED_OPERAND_AGEN: + case XED_OPERAND_MEM0: + case XED_OPERAND_MEM1: // In what case would the memory address size be 10?? (floating point ops?) + if (operandSize != opLen) + return il.Operand(instruction_index, il.FloatConvert(opLen, il.Load(operandSize, GetILOperandMemoryAddress(il, xedd, addr, instruction_index, operand_index)))); + return il.Operand(instruction_index, il.Load(opLen, GetILOperandMemoryAddress(il, xedd, addr, instruction_index, operand_index))); + + default: + return il.Undefined(); + } +} + + +// For most instructions, instruction_index == operand_index, but some instructions (floating point, some others) have an implicit first operand (st0), so we have to remap things a bit +// Instruction index represents the 'nth' argument/opcode in the instruction, whereas the operand index is index that XED holds that operand in the instruction +static size_t WriteILOperand(LowLevelILFunction& il, const xed_decoded_inst_t* const xedd, const size_t addr, + const size_t instruction_index, const size_t operand_index, + const size_t value, size_t sizeToWrite = 0) +{ + // sizeToWrite allows one to specify a part of the operand to write + // other than the whole + // this solves some of the problems we have; but not all + // we still need the ability to read and write a slice of the operand + if (sizeToWrite == 0) + sizeToWrite = xed_decoded_inst_operand_length(xedd, operand_index); + + const xed_operand_enum_t op_name = xed_operand_name(xed_inst_operand(xed_decoded_inst_inst(xedd), operand_index)); + + switch (op_name) + { + // Register cases + case XED_OPERAND_REG0: + case XED_OPERAND_REG1: + case XED_OPERAND_REG2: + case XED_OPERAND_REG3: + case XED_OPERAND_REG4: + case XED_OPERAND_REG5: + case XED_OPERAND_REG6: + case XED_OPERAND_REG7: + case XED_OPERAND_REG8: + case XED_OPERAND_BASE0: + case XED_OPERAND_BASE1: + return il.Operand(instruction_index, il.SetRegister(sizeToWrite, xed_decoded_inst_get_reg(xedd, op_name), value)); + + // Memory Accesses + case XED_OPERAND_AGEN: + case XED_OPERAND_MEM0: + case XED_OPERAND_MEM1: + return il.Operand(instruction_index, il.Store(sizeToWrite, GetILOperandMemoryAddress(il, xedd, addr, instruction_index, operand_index), value)); + + default: + return il.Undefined(); + } +} + + +static void ConditionalJump(Architecture* arch, LowLevelILFunction& il, size_t cond, size_t addrSize, uint64_t t, uint64_t f) +{ + BNLowLevelILLabel* trueLabel = il.GetLabelForAddress(arch, t); + BNLowLevelILLabel* falseLabel = il.GetLabelForAddress(arch, f); + + if (trueLabel && falseLabel) + { + il.AddInstruction(il.If(cond, *trueLabel, *falseLabel)); + return; + } + + LowLevelILLabel trueCode, falseCode; + + if (trueLabel) + { + il.AddInstruction(il.If(cond, *trueLabel, falseCode)); + il.MarkLabel(falseCode); + il.AddInstruction(il.Jump(il.ConstPointer(addrSize, f))); + return; + } + + if (falseLabel) + { + il.AddInstruction(il.If(cond, trueCode, *falseLabel)); + il.MarkLabel(trueCode); + il.AddInstruction(il.Jump(il.ConstPointer(addrSize, t))); + return; + } + + il.AddInstruction(il.If(cond, trueCode, falseCode)); + il.MarkLabel(trueCode); + il.AddInstruction(il.Jump(il.ConstPointer(addrSize, t))); + il.MarkLabel(falseCode); + il.AddInstruction(il.Jump(il.ConstPointer(addrSize, f))); +} + + +static void DirFlagIf(LowLevelILFunction& il, + std::function<void()> addPreTestIl, + std::function<void()> addDirFlagSetIl, + std::function<void()> addDirFlagClearIl) +{ + LowLevelILLabel dirFlagSet, dirFlagClear, dirFlagDone; + + addPreTestIl(); + + il.AddInstruction(il.If(il.Flag(IL_FLAG_D), dirFlagSet, dirFlagClear)); + il.MarkLabel(dirFlagSet); + + addDirFlagSetIl(); + + il.AddInstruction(il.Goto(dirFlagDone)); + il.MarkLabel(dirFlagClear); + + addDirFlagClearIl(); + + il.AddInstruction(il.Goto(dirFlagDone)); + il.MarkLabel(dirFlagDone); +} + + +static void Repeat( + const xed_decoded_inst_t* const xedd, + LowLevelILFunction& il, + std::function<void ()> addil) +{ + const size_t addrSize = xed_decoded_inst_get_machine_mode_bits(xedd) / 8; + LowLevelILLabel trueLabel, falseLabel, doneLabel; + const xed_operand_values_t* const ov = xed_decoded_inst_operands_const(xedd); + + if (xed_operand_values_has_real_rep(ov)) + { + il.AddInstruction(il.Goto(trueLabel)); + il.MarkLabel(trueLabel); + il.AddInstruction(il.If( + il.CompareNotEqual(addrSize, + il.Register(addrSize, GetCountRegister(addrSize)), + il.Const(addrSize, 0)), falseLabel, doneLabel)); + il.MarkLabel(falseLabel); + } + + addil(); + + if (xed_operand_values_has_real_rep(ov)) + { + il.AddInstruction( + il.SetRegister(addrSize, + GetCountRegister(addrSize), + il.Sub(addrSize, + il.Register(addrSize, GetCountRegister(addrSize)), + il.Const(addrSize, 1)))); + + const xed_iclass_enum_t xeddiClass = xed_decoded_inst_get_iclass(xedd); + if (xed_operand_values_has_repne_prefix(ov)) + il.AddInstruction(il.If(il.FlagCondition(LLFC_NE), trueLabel, doneLabel)); + else if (xed_repe_map(xed_norep_map(xeddiClass)) == xeddiClass) + il.AddInstruction(il.If(il.FlagCondition(LLFC_E), trueLabel, doneLabel)); + else + il.AddInstruction(il.Goto(trueLabel)); + il.MarkLabel(doneLabel); + } +} + + +static void CMovFlagCond(const int64_t addr, const xed_decoded_inst_t* xedd, LowLevelILFunction& il, BNLowLevelILFlagCondition flag) +{ + // keep the true branch but let the false branch goto doneLabel directly + LowLevelILLabel trueLabel, doneLabel; + + il.AddInstruction( + il.If( + il.FlagCondition(flag), + trueLabel, doneLabel)); + + il.MarkLabel(trueLabel); + + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + ReadILOperand(il, xedd, addr, 1, 1))); + + il.AddInstruction(il.Goto(doneLabel)); + il.MarkLabel(doneLabel); +} + + +static void CMovFlagGroup(const int64_t addr, const xed_decoded_inst_t* xedd, LowLevelILFunction& il, uint32_t flag) +{ + // keep the true branch but let the false branch goto doneLabel directly + LowLevelILLabel trueLabel, doneLabel; + + il.AddInstruction( + il.If( + il.FlagGroup(flag), + trueLabel, doneLabel + ) + ); + + il.MarkLabel(trueLabel); + + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + ReadILOperand(il, xedd, addr, 1, 1))); + + il.AddInstruction(il.Goto(doneLabel)); + il.MarkLabel(doneLabel); +} + + +bool GetLowLevelILForInstruction(Architecture* arch, const uint64_t addr, LowLevelILFunction& il, const xed_decoded_inst_t* const xedd) +{ + LowLevelILLabel trueLabel, falseLabel, doneLabel, dirFlagSet, dirFlagClear, dirFlagDone, startLabel; + LowLevelILLabel trueLabel2, falseLabel2; + + const xed_iclass_enum_t xedd_iClass = xed_decoded_inst_get_iclass(xedd); + const xed_iform_enum_t xedd_iForm = xed_decoded_inst_get_iform_enum(xedd); + const xed_inst_t* const xi = xed_decoded_inst_inst(xedd); + // const xed_operand_values_t* const ov = xed_decoded_inst_operands_const(xedd); + const unsigned short instLen = xed_decoded_inst_get_length(xedd); + // mode_bits can be used to determine whether the current instruciton is in 16/32/64 bit mode + const size_t mode_bits = xed_decoded_inst_get_machine_mode_bits(xedd); + const size_t addrSize = mode_bits / 8; + + const unsigned short opOneLen = xed_decoded_inst_operand_length_bits(xedd, 0) / 8; + const unsigned short opTwoLen = xed_decoded_inst_operand_length_bits(xedd, 1) / 8; + [[maybe_unused]] const unsigned short + opTreLen = xed_decoded_inst_operand_length_bits(xedd, 2) / 8; + const xed_operand_t* const opOne = xed_inst_operand(xi, 0); + const xed_operand_t* const opTwo = xed_inst_operand(xi, 1); + // this is problematic as operand three may or may not exist at all + // latest version of xed will complain about this + const xed_operand_t* const opTre = xed_inst_operand(xi, 2); + const xed_operand_enum_t opOne_name = xed_operand_name(opOne); + const xed_operand_enum_t opTwo_name = xed_operand_name(opTwo); + const xed_operand_enum_t opTre_name = xed_operand_name(opTre); + const xed_reg_enum_t regOne = xed_decoded_inst_get_reg(xedd, opOne_name); + const xed_reg_enum_t regTwo = xed_decoded_inst_get_reg(xedd, opTwo_name); + // const xed_reg_enum_t regTre = xed_decoded_inst_get_reg(xedd, opTre_name); + // const xed_reg_enum_t baseReg1 = xed_decoded_inst_get_base_reg(xedd, 0); + // const xed_reg_enum_t baseReg2 = xed_decoded_inst_get_base_reg(xedd, 1); + const xed_reg_enum_t segReg1 = xed_decoded_inst_get_seg_reg (xedd, 0); + // const xed_reg_enum_t segReg2 = xed_decoded_inst_get_seg_reg (xedd, 1); + + const uint64_t immediateOne = xed_decoded_inst_get_unsigned_immediate(xedd); + const int64_t branchDestination = xed_decoded_inst_get_branch_displacement(xedd) + addr + instLen; + + auto LiftAsIntrinsic = [& il, xi, xedd, addr, xedd_iForm] () mutable { + + typedef struct + { + uint32_t index; + size_t width; + } MemoryOperandWriteInfo; + + vector<RegisterOrFlag> outputs = {}; + vector<ExprId> parameters = {}; + size_t noperands = xed_inst_noperands(xi); + vector<MemoryOperandWriteInfo> memoryOperandWrites = {}; + size_t numTempRegUsed = 0; + for (uint32_t i = 0; i < noperands; i++) + { + const xed_operand_t* op = xed_inst_operand(xi, i); + xed_operand_enum_t op_name = xed_operand_name(op); + if (xed_operand_written(op)) + { + switch(op_name) + { + case XED_OPERAND_REG0: + case XED_OPERAND_REG1: + case XED_OPERAND_REG2: + case XED_OPERAND_REG3: + case XED_OPERAND_REG4: + case XED_OPERAND_REG5: + case XED_OPERAND_REG6: + case XED_OPERAND_REG7: + case XED_OPERAND_REG8: + case XED_OPERAND_BASE0: + case XED_OPERAND_BASE1: + { + xed_reg_enum_t r = xed_decoded_inst_get_reg(xedd, op_name); + outputs.push_back(RegisterOrFlag::Register(r)); + break; + } + default: + // The intrinsic system can only accept registers or flags as outputs, + // since it might be strange to write to an arbitrary ExprId. + // In order to handle intrinsics that write to memory, we create a temp IL register and + // later generate another il intrustion to write the register value to the memory + // An example of this is: + // vmovss dword [eax], k1, xmm0 (bytes: 6762f17e091100) + // which lifts to: + // temp0 = _mm_mask_store_ss(k1, xmm0) + // [eax.q].d = temp0.d + // Note, however, it is quite rare for an intrinsic to write to memory + size_t operandWidth = (xed_decoded_inst_operand_length_bits(xedd, i) + 7) >> 3; + memoryOperandWrites.push_back({i, operandWidth}); + outputs.push_back(RegisterOrFlag::Register(LLIL_TEMP(numTempRegUsed))); + numTempRegUsed++; + break; + } + } + if (xed_operand_read(op)) + { + switch(op_name) + { + case XED_OPERAND_REG0: + case XED_OPERAND_REG1: + case XED_OPERAND_REG2: + case XED_OPERAND_REG3: + case XED_OPERAND_REG4: + case XED_OPERAND_REG5: + case XED_OPERAND_REG6: + case XED_OPERAND_REG7: + case XED_OPERAND_REG8: + case XED_OPERAND_BASE0: + case XED_OPERAND_BASE1: + { + // XED includes some things that are not actual registers in + // xed_reg_enum_t. We'll just omit those special cases here. + xed_reg_enum_t r = xed_decoded_inst_get_reg(xedd, op_name); + switch(r) + { + case XED_REG_INVALID: + case XED_REG_MSRS: + case XED_REG_STACKPUSH: + case XED_REG_STACKPOP: + case XED_REG_ERROR: + case XED_REG_LAST: + continue; + default: + break; + } + } + default: + break; + } + + parameters.push_back(ReadILOperand(il, xedd, addr, i, i)); + } + } + X86_INTRINSIC intrinsic = (X86_INTRINSIC)(xedd_iForm + 1000); + il.AddInstruction(il.Intrinsic(outputs, intrinsic, parameters)); + // Generate IL instruction for memory writes + for (size_t i = 0; i < memoryOperandWrites.size(); i++) + { + uint32_t operand = memoryOperandWrites[i].index; + size_t openradWidth = memoryOperandWrites[i].width; + il.AddInstruction(WriteILOperand(il, xedd, addr, operand, operand, + il.Register(openradWidth, LLIL_TEMP(i)))); + } + }; + + switch (xedd_iClass) + { + case XED_ICLASS_ADC_LOCK: // TODO: Add Lock construct + case XED_ICLASS_ADC: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.AddCarry(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + il.Flag(IL_FLAG_C), IL_FLAGWRITE_ALL))); + break; + + case XED_ICLASS_ADCX: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.AddCarry(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + il.Flag(IL_FLAG_C), IL_FLAG_C))); + break; + + case XED_ICLASS_ADOX: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.AddCarry(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + il.Flag(IL_FLAG_O), IL_FLAG_O))); + break; + + case XED_ICLASS_ADD_LOCK: // TODO: Add Lock construct + case XED_ICLASS_ADD: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Add(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_ALL))); + break; + + case XED_ICLASS_AND_LOCK: // TODO: Add Lock construct + case XED_ICLASS_AND: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.And(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_ALL))); + break; + case XED_ICLASS_PAND: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.And(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + 0))); // PAND doesn't modify any flag. + break; + + case XED_ICLASS_VPAND: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.And(opOneLen, + ReadILOperand(il, xedd, addr, 1, 1), + ReadILOperand(il, xedd, addr, 2, 2), + 0))); // VPAND doesn't modify any flag + break; + + case XED_ICLASS_ANDN: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.And(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + il.Not( + opTwoLen, + ReadILOperand(il, xedd, addr, 1, 1) + ), + IL_FLAGWRITE_ALL))); + break; + case XED_ICLASS_PANDN: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.And(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + il.Not( + opTwoLen, + ReadILOperand(il, xedd, addr, 1, 1) + ), + 0))); // Does not affect flags + break; + case XED_ICLASS_VPANDN: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.And(opOneLen, + ReadILOperand(il, xedd, addr, 1, 1), + il.Not( + opTwoLen, + ReadILOperand(il, xedd, addr, 2, 2) + ), + IL_FLAGWRITE_ALL))); + break; + + case XED_ICLASS_BT: + il.AddInstruction(il.SetFlag(IL_FLAG_C, + il.TestBit(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1)))); + break; + + case XED_ICLASS_BTC_LOCK: + case XED_ICLASS_BTC: + // TODO: Handle lock prefix + il.AddInstruction(il.SetFlag(IL_FLAG_C, + il.TestBit(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1)))); + + // Complement the bit specified by operand[1] in operand[0] + // operand[0] = operand[0] ^ (1 << operand[1]) + // or in the case operand[1] is a register + // operand[0] = operand[0] ^ (1 << (operand[1] % operand[0].size)) + + if (opTwo_name == XED_OPERAND_IMM0) + { + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.Xor(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + il.ShiftLeft(opOneLen, + il.Const(opOneLen, 1), + ReadILOperand(il, xedd, addr, 1, 1))))); + } + else + { + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.Xor(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + il.ShiftLeft(opOneLen, + il.Const(opOneLen, 1), + il.ModUnsigned(opTwoLen, + ReadILOperand(il, xedd, addr, 1, 1), + il.Const(1, opOneLen * 8)))))); + } + + break; + + case XED_ICLASS_BTR_LOCK: + case XED_ICLASS_BTR: + // TODO: Handle lock prefix + il.AddInstruction(il.SetFlag(IL_FLAG_C, + il.TestBit(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1)))); + + // Reset the bit specified by operand[1] in operand[0] + // operand[0] = operand[0] & ~(1 << operand[1]) + // or in the case operand[1] is a register + // operand[0] = operand[0] & ~(1 << (operand[1] % operand[0].size)) + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.And(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + il.Not(opOneLen, + il.ShiftLeft(opOneLen, + il.Const(opOneLen, 1), + (opTwo_name == XED_OPERAND_IMM0) ? + ReadILOperand(il, xedd, addr, 1, 1) : + il.ModUnsigned(opTwoLen, + ReadILOperand(il, xedd, addr, 1, 1), + il.Const(1, opOneLen * 8))))))); + break; + + case XED_ICLASS_BTS_LOCK: + case XED_ICLASS_BTS: + // TODO: Handle lock prefix + il.AddInstruction(il.SetFlag(IL_FLAG_C, + il.TestBit(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1)))); + + // Complement the bit specified by operand[1] in operand[0] + // operand[0] = operand[0] | (1 << operand[1]) + // or in the case operand[1] is a register + // operand[0] = operand[0] | (1 << (operand[1] % operand[0].size)) + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.Or(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + il.ShiftLeft(opOneLen, + il.Const(opOneLen, 1), + (opTwo_name == XED_OPERAND_IMM0) ? + ReadILOperand(il, xedd, addr, 1, 1) : + il.ModUnsigned(opTwoLen, + ReadILOperand(il, xedd, addr, 1, 1), + il.Const(1, opOneLen * 8)))))); + break; + + case XED_ICLASS_ADDSS: + { + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatAdd(4, + ReadFloatILOperand(il, xedd, addr, 0, 0, 4), + ReadFloatILOperand(il, xedd, addr, 1, 1, 4) + ))); + break; + } + + case XED_ICLASS_VADDSS: + { + if (xed_classify_avx512(xedd)) + { + LiftAsIntrinsic(); + break; + } + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatAdd(4, + ReadFloatILOperand(il, xedd, addr, 1, 1, 4), + ReadFloatILOperand(il, xedd, addr, 2, 2, 4) + ))); + break; + } + + case XED_ICLASS_ADDSD: + { + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatAdd(8, + ReadFloatILOperand(il, xedd, addr, 0, 0, 8), + ReadFloatILOperand(il, xedd, addr, 1, 1, 8) + ))); + break; + } + + case XED_ICLASS_VADDSD: + { + if (xed_classify_avx512(xedd)) + { + LiftAsIntrinsic(); + break; + } + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatAdd(8, + ReadFloatILOperand(il, xedd, addr, 1, 1, 8), + ReadFloatILOperand(il, xedd, addr, 2, 2, 8) + ))); + break; + } + + case XED_ICLASS_SUBSS: + { + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatSub(4, + ReadFloatILOperand(il, xedd, addr, 0, 0, 4), + ReadFloatILOperand(il, xedd, addr, 1, 1, 4) + ))); + break; + } + + case XED_ICLASS_VSUBSS: + { + if (xed_classify_avx512(xedd)) + { + LiftAsIntrinsic(); + break; + } + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatSub(4, + ReadFloatILOperand(il, xedd, addr, 1, 1, 4), + ReadFloatILOperand(il, xedd, addr, 2, 2, 4) + ))); + break; + } + + case XED_ICLASS_SUBSD: + { + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatSub(8, + ReadFloatILOperand(il, xedd, addr, 0, 0, 8), + ReadFloatILOperand(il, xedd, addr, 1, 1, 8) + ))); + break; + } + + case XED_ICLASS_VSUBSD: + { + if (xed_classify_avx512(xedd)) + { + LiftAsIntrinsic(); + break; + } + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatSub(8, + ReadFloatILOperand(il, xedd, addr, 1, 1, 8), + ReadFloatILOperand(il, xedd, addr, 2, 2, 8 + ))) + ); + break; + } + + case XED_ICLASS_MULSS: + { + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatMult(4, + ReadFloatILOperand(il, xedd, addr, 0, 0, 4), + ReadFloatILOperand(il, xedd, addr, 1, 1, 4) + ))); + break; + } + + case XED_ICLASS_VMULSS: + { + if (xed_classify_avx512(xedd)) + { + LiftAsIntrinsic(); + break; + } + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatMult(4, + ReadFloatILOperand(il, xedd, addr, 1, 1, 4), + ReadFloatILOperand(il, xedd, addr, 2, 2, 4) + ))); + break; + } + + case XED_ICLASS_MULSD: + { + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatMult(8, + ReadFloatILOperand(il, xedd, addr, 0, 0, 8), + ReadFloatILOperand(il, xedd, addr, 1, 1, 8) + ))); + break; + } + + case XED_ICLASS_VMULSD: + { + if (xed_classify_avx512(xedd)) + { + LiftAsIntrinsic(); + break; + } + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatMult(8, + ReadFloatILOperand(il, xedd, addr, 1, 1, 8), + ReadFloatILOperand(il, xedd, addr, 2, 2, 8) + ))); + break; + } + + case XED_ICLASS_DIVSS: + { + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatDiv(4, + ReadFloatILOperand(il, xedd, addr, 0, 0, 4), + ReadFloatILOperand(il, xedd, addr, 1, 1, 4) + ))); + break; + } + + case XED_ICLASS_VDIVSS: + { + if (xed_classify_avx512(xedd)) + { + LiftAsIntrinsic(); + break; + } + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatDiv(4, + ReadFloatILOperand(il, xedd, addr, 1, 1, 4), + ReadFloatILOperand(il, xedd, addr, 2, 2, 4) + ))); + break; + } + + case XED_ICLASS_DIVSD: + { + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatDiv(8, + ReadFloatILOperand(il, xedd, addr, 0, 0, 8), + ReadFloatILOperand(il, xedd, addr, 1, 1, 8) + ))); + break; + } + + case XED_ICLASS_VDIVSD: + { + if (xed_classify_avx512(xedd)) + { + LiftAsIntrinsic(); + break; + } + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatDiv(8, + ReadFloatILOperand(il, xedd, addr, 1, 1, 8), + ReadFloatILOperand(il, xedd, addr, 2, 2, 8) + ))); + break; + } + + case XED_ICLASS_LDMXCSR: + case XED_ICLASS_VLDMXCSR: + { + il.AddInstruction( + il.SetRegister(4, XED_REG_MXCSR, + ReadILOperand(il, xedd, addr, 0, 0) + ) + ); + break; + } + + case XED_ICLASS_STMXCSR: + case XED_ICLASS_VSTMXCSR: + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Register(4, XED_REG_MXCSR) + ) + ); + break; + } + + case XED_ICLASS_CVTSI2SS: + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.IntToFloat(4, + ReadILOperand(il, xedd, addr, 1, 1) + ) + ) + ); + break; + } + + case XED_ICLASS_VCVTSI2SS: + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + ReadILOperand(il, xedd, addr, 1, 1) + ) + ); + il.AddInstruction( + il.SetRegister(4, regOne, + il.IntToFloat(4, + ReadILOperand(il, xedd, addr, 2, 2) + ) + ) + ); + break; + } + + case XED_ICLASS_CVTSI2SD: + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.IntToFloat(8, + ReadILOperand(il, xedd, addr, 1, 1) + ) + ) + ); + break; + } + + case XED_ICLASS_VCVTSI2SD: + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + ReadILOperand(il, xedd, addr, 1, 1) + ) + ); + il.AddInstruction( + il.SetRegister(8, regOne, + il.IntToFloat(8, + ReadILOperand(il, xedd, addr, 2, 2) + ) + ) + ); + break; + } + + case XED_ICLASS_CVTSS2SI: + case XED_ICLASS_VCVTSS2SI: + case XED_ICLASS_CVTSD2SI: + case XED_ICLASS_VCVTSD2SI: + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatToInt(opOneLen, + ReadFloatILOperand(il, xedd, addr, 1, 1) + ) + ) + ); + break; + } + + case XED_ICLASS_CVTTSD2SI: + case XED_ICLASS_CVTTSS2SI: + case XED_ICLASS_VCVTTSD2SI: + case XED_ICLASS_VCVTTSS2SI: + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatToInt(opOneLen, + il.FloatTrunc(0, + ReadFloatILOperand(il, xedd, addr, 1, 1) + ) + ) + ) + ); + break; + } + + case XED_ICLASS_CVTSS2SD: + case XED_ICLASS_CVTSD2SS: + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatConvert(opOneLen, + ReadFloatILOperand(il, xedd, addr, 1, 1) + ) + ) + ); + break; + } + + case XED_ICLASS_VCVTSS2SD: + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + ReadILOperand(il, xedd, addr, 1, 1) + ) + ); + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatConvert(8, + ReadFloatILOperand(il, xedd, addr, 2, 2) + ), + 8 + ) + ); + break; + } + + case XED_ICLASS_VCVTSD2SS: + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + ReadILOperand(il, xedd, addr, 1, 1) + ) + ); + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatConvert(4, + ReadFloatILOperand(il, xedd, addr, 2, 2) + ), + 4 + ) + ); + break; + } + + case XED_ICLASS_XLAT: + { + il.AddInstruction( + il.SetRegister( + 1, XED_REG_AL, + // the operand 0 is the MEM being read + ReadILOperand(il, xedd, addr, 0, 0) + ) + ); + break; + } + + // This is a workaround to stop the type propagator from + // making integers of size 576, which is mostly wrong + // However, if we do implement these, it will in turn + // cause problems with parameter resolution + // So as for now, unimplemented is the best solution + case XED_ICLASS_XRSTOR: + case XED_ICLASS_XRSTOR64: + case XED_ICLASS_XRSTORS: + case XED_ICLASS_XRSTORS64: + case XED_ICLASS_XSAVE: + case XED_ICLASS_XSAVE64: + case XED_ICLASS_XSAVEC: + case XED_ICLASS_XSAVEC64: + case XED_ICLASS_XSAVEOPT: + case XED_ICLASS_XSAVEOPT64: + case XED_ICLASS_XSAVES: + case XED_ICLASS_XSAVES64: + il.AddInstruction(il.Unimplemented()); + break; + + case XED_ICLASS_CALL_NEAR: + case XED_ICLASS_CALL_FAR: + if ( + ((xedd_iForm == XED_IFORM_CALL_FAR_MEMp2) || (xedd_iForm == XED_IFORM_CALL_NEAR_MEMv)) && + (immediateOne == 0x10) && + (opOneLen == 4) && + (segReg1 == XED_REG_GS)) + { + // Linux indirect system call (call dword [gs:0x10]) + // TODO: Implement this as a platform-specific lifting extension when such a thing + // is possible + il.AddInstruction(il.SystemCall()); + break; + } + + // Turn 'call next' into a push + if (((uint64_t)branchDestination == addr+instLen) && ((xedd_iForm == XED_IFORM_CALL_NEAR_RELBRz) || (xedd_iForm == XED_IFORM_CALL_NEAR_RELBRd))) + { + il.AddInstruction( + il.Push(addrSize, + il.ConstPointer(addrSize, addr + instLen))); + } + else + { + il.AddInstruction( + il.Call( + ReadILOperand(il, xedd, addr, 0, 0))); + } + break; + + case XED_ICLASS_CBW: + il.AddInstruction(il.SetRegister(2, XED_REG_AX, il.SignExtend(2, il.Register(1, XED_REG_AL)))); + break; + + case XED_ICLASS_CDQ: + il.AddInstruction(il.SetRegisterSplit(4, XED_REG_EDX, XED_REG_EAX, il.SignExtend(8, il.Register(4, XED_REG_EAX)))); + break; + + case XED_ICLASS_CLC: + il.AddInstruction(il.SetFlag(IL_FLAG_C, il.Const(1, 0))); + break; + + case XED_ICLASS_CLD: + il.AddInstruction(il.SetFlag(IL_FLAG_D, il.Const(1, 0))); + break; + + case XED_ICLASS_CMC: + il.AddInstruction(il.SetFlag(IL_FLAG_C, il.Xor(1, il.Flag(IL_FLAG_C), il.Const(1, 1)))); + break; + + case XED_ICLASS_CMOVO: + CMovFlagCond(addr, xedd, il, LLFC_O); + break; + + case XED_ICLASS_CMOVNO: + CMovFlagCond(addr, xedd, il, LLFC_NO); + break; + + case XED_ICLASS_CMOVB: + case XED_ICLASS_FCMOVB: + CMovFlagGroup(addr, xedd, il, IL_FLAG_GROUP_LT); + break; + + case XED_ICLASS_CMOVNB: + case XED_ICLASS_FCMOVNB: + CMovFlagGroup(addr, xedd, il, IL_FLAG_GROUP_GE); + break; + + case XED_ICLASS_CMOVZ: + case XED_ICLASS_FCMOVE: + CMovFlagGroup(addr, xedd, il, IL_FLAG_GROUP_E); + break; + + case XED_ICLASS_CMOVNZ: + case XED_ICLASS_FCMOVNE: + CMovFlagGroup(addr, xedd, il, IL_FLAG_GROUP_NE); + break; + + case XED_ICLASS_CMOVBE: + case XED_ICLASS_FCMOVBE: + CMovFlagGroup(addr, xedd, il, IL_FLAG_GROUP_LE); + break; + + case XED_ICLASS_CMOVNBE: + case XED_ICLASS_FCMOVNBE: + CMovFlagGroup(addr, xedd, il, IL_FLAG_GROUP_GT); + break; + + case XED_ICLASS_CMOVS: + CMovFlagCond(addr, xedd, il, LLFC_NEG); + break; + + case XED_ICLASS_CMOVNS: + CMovFlagCond(addr, xedd, il, LLFC_POS); + break; + + case XED_ICLASS_CMOVP: + case XED_ICLASS_FCMOVU: + CMovFlagGroup(addr, xedd, il, IL_FLAG_GROUP_PE); + break; + + case XED_ICLASS_CMOVNP: + case XED_ICLASS_FCMOVNU: + CMovFlagGroup(addr, xedd, il, IL_FLAG_GROUP_PO); + break; + + case XED_ICLASS_CMOVL: + CMovFlagCond(addr, xedd, il, LLFC_SLT); + break; + + case XED_ICLASS_CMOVNL: + CMovFlagCond(addr, xedd, il, LLFC_SGE); + break; + + case XED_ICLASS_CMOVLE: + CMovFlagCond(addr, xedd, il, LLFC_SLE); + break; + + case XED_ICLASS_CMOVNLE: + CMovFlagCond(addr, xedd, il, LLFC_SGT); + break; + + case XED_ICLASS_CMP: + il.AddInstruction( + il.Sub(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_ALL)); + break; + + case XED_ICLASS_REPE_CMPSQ: + case XED_ICLASS_REPNE_CMPSQ: + case XED_ICLASS_CMPSQ: + case XED_ICLASS_REPE_CMPSD: + case XED_ICLASS_REPNE_CMPSD: + case XED_ICLASS_CMPSD: + case XED_ICLASS_REPE_CMPSW: + case XED_ICLASS_REPNE_CMPSW: + case XED_ICLASS_CMPSW: + case XED_ICLASS_REPE_CMPSB: + case XED_ICLASS_REPNE_CMPSB: + case XED_ICLASS_CMPSB: + { + size_t argSize = 1; + uint32_t srcReg = addrSize == 4 ? XED_REG_ESI : XED_REG_RSI; + uint32_t dstReg = addrSize == 4 ? XED_REG_EDI : XED_REG_RDI; + switch (xedd_iClass) + { + case XED_ICLASS_REPE_CMPSB: + case XED_ICLASS_REPNE_CMPSB: + case XED_ICLASS_CMPSB: + argSize = 1; + break; + case XED_ICLASS_REPE_CMPSW: + case XED_ICLASS_REPNE_CMPSW: + case XED_ICLASS_CMPSW: + argSize = 2; + break; + case XED_ICLASS_REPE_CMPSD: + case XED_ICLASS_REPNE_CMPSD: + case XED_ICLASS_CMPSD: + argSize = 4; + break; + case XED_ICLASS_REPE_CMPSQ: + case XED_ICLASS_REPNE_CMPSQ: + case XED_ICLASS_CMPSQ: + argSize = 8; + break; + default: + break; + } + + Repeat(xedd, il, [&] (){ + DirFlagIf(il, + [&] () + { + il.AddInstruction(il.Sub(argSize, il.Load(argSize, il.Register(addrSize, srcReg)), il.Load(argSize, il.Register(addrSize, dstReg)), IL_FLAGWRITE_ALL)); + }, + [&] () // Dirflag is 1 + { + il.AddInstruction(il.SetRegister(addrSize, srcReg, il.Sub(addrSize, il.Register(addrSize, srcReg), il.Const(1, argSize)))); + il.AddInstruction(il.SetRegister(addrSize, dstReg, il.Sub(addrSize, il.Register(addrSize, dstReg), il.Const(1, argSize)))); + }, + [&] () // Dirflag is 0 + { + il.AddInstruction(il.SetRegister(addrSize, srcReg, il.Add(addrSize, il.Register(addrSize, srcReg), il.Const(1, argSize)))); + il.AddInstruction(il.SetRegister(addrSize, dstReg, il.Add(addrSize, il.Register(addrSize, dstReg), il.Const(1, argSize)))); + }); + }); + break; + } + + case XED_ICLASS_PALIGNR: + { + // the immediate for palignr is smaller than 32 + u_char nshiftBytes = (u_char)xed_decoded_inst_get_unsigned_immediate(xedd); + size_t nShiftBits = 8 * nshiftBytes; + size_t regSize = opOneLen; + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Or(regSize, + il.LogicalShiftRight(regSize, ReadILOperand(il, xedd, addr, 1, 1), il.Const(1, nShiftBits)), + il.ShiftLeft(regSize, + ReadILOperand(il, xedd, addr, 0, 0), + il.Const(1, 8 * (regSize - nshiftBytes)) + ) + ) + ) + ); + break; + } + case XED_ICLASS_VPALIGNR: + { + if (xed_classify_avx512(xedd)) + { + LiftAsIntrinsic(); + break; + } + // the immediate for palignr is smaller than 32 + u_char nshiftBytes = (u_char)xed_decoded_inst_get_unsigned_immediate(xedd); + size_t nShiftBits = 8 * nshiftBytes; + size_t regSize = opOneLen; + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Or(regSize, + il.LogicalShiftRight(regSize, ReadILOperand(il, xedd, addr, 2, 2), il.Const(1, nShiftBits)), + il.ShiftLeft(regSize, + ReadILOperand(il, xedd, addr, 1, 1), + il.Const(1, 8 * (regSize - nshiftBytes)) + ) + ) + ) + ); + break; + } + + case XED_ICLASS_CQO: + il.AddInstruction(il.SetRegisterSplit(8, XED_REG_RDX, XED_REG_RAX, il.SignExtend(16, il.Register(8, XED_REG_RAX)))); + break; + + case XED_ICLASS_CWD: + il.AddInstruction(il.SetRegisterSplit(2, XED_REG_DX, XED_REG_AX, il.SignExtend(4, il.Register(2, XED_REG_AX)))); + break; + + case XED_ICLASS_CWDE: + il.AddInstruction(il.SetRegister(4, XED_REG_EAX, il.SignExtend(4, il.Register(2, XED_REG_AX)))); + break; + + case XED_ICLASS_CDQE: + il.AddInstruction(il.SetRegister(8, XED_REG_RAX, il.SignExtend(8, il.Register(4, XED_REG_EAX)))); + break; + + case XED_ICLASS_DEC_LOCK: // TODO: Handle lock prefix + case XED_ICLASS_DEC: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Sub(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + il.Const(opOneLen, 1), + IL_FLAGWRITE_NOCARRY) + ) + ); + break; + + case XED_ICLASS_DIV: + il.AddInstruction( + il.SetRegister(opOneLen, + LLIL_TEMP(2), + ReadILOperand(il, xedd, addr, 0, 0))); + + switch (opOneLen) + { + case 1: + il.AddInstruction( + il.SetRegister(1, + LLIL_TEMP(0), + il.DivDoublePrecUnsigned(1, + il.Register(2, XED_REG_AX), + il.Register(opOneLen, LLIL_TEMP(2))))); + + il.AddInstruction(il.SetRegister(1, + LLIL_TEMP(1), + il.ModDoublePrecUnsigned(1, + il.Register(2, XED_REG_AX), + il.Register(opOneLen, LLIL_TEMP(2))))); + + il.AddInstruction( + il.SetRegister(1, + XED_REG_AL, + il.Register(1, LLIL_TEMP(0)))); + + il.AddInstruction( + il.SetRegister(1, + XED_REG_AH, + il.Register(1, LLIL_TEMP(1)))); + break; + + case 2: + il.AddInstruction( + il.SetRegister(2, + LLIL_TEMP(0), + il.DivDoublePrecUnsigned(2, + il.RegisterSplit(2, + XED_REG_DX, + XED_REG_AX), + il.Register(opOneLen, LLIL_TEMP(2))))); + + il.AddInstruction( + il.SetRegister(2, + LLIL_TEMP(1), + il.ModDoublePrecUnsigned(2, + il.RegisterSplit(2, + XED_REG_DX, + XED_REG_AX), + il.Register(opOneLen, LLIL_TEMP(2))))); + + il.AddInstruction( + il.SetRegister(2, + XED_REG_AX, + il.Register(2, LLIL_TEMP(0)))); + + il.AddInstruction( + il.SetRegister(2, + XED_REG_DX, + il.Register(2, LLIL_TEMP(1)))); + break; + + case 4: + il.AddInstruction( + il.SetRegister(4, + LLIL_TEMP(0), + il.DivDoublePrecUnsigned(4, + il.RegisterSplit(4, + XED_REG_EDX, + XED_REG_EAX), + il.Register(opOneLen, LLIL_TEMP(2))))); + + il.AddInstruction( + il.SetRegister(4, + LLIL_TEMP(1), + il.ModDoublePrecUnsigned(4, + il.RegisterSplit(4, + XED_REG_EDX, + XED_REG_EAX), + il.Register(opOneLen, LLIL_TEMP(2))))); + + il.AddInstruction( + il.SetRegister(4, + XED_REG_EAX, + il.Register(4, LLIL_TEMP(0)))); + + il.AddInstruction( + il.SetRegister(4, + XED_REG_EDX, + il.Register(4, LLIL_TEMP(1)))); + break; + + case 8: + il.AddInstruction(il.SetRegister(8, + LLIL_TEMP(0), + il.DivDoublePrecUnsigned(8, + il.RegisterSplit(8, + XED_REG_RDX, + XED_REG_RAX), + il.Register(opOneLen, LLIL_TEMP(2))))); + + il.AddInstruction( + il.SetRegister(8, + LLIL_TEMP(1), + il.ModDoublePrecUnsigned(8, + il.RegisterSplit(8, + XED_REG_RDX, + XED_REG_RAX), + il.Register(opOneLen, LLIL_TEMP(2))))); + + il.AddInstruction( + il.SetRegister(8, + XED_REG_RAX, + il.Register(8, LLIL_TEMP(0)))); + + il.AddInstruction( + il.SetRegister(8, + XED_REG_RDX, + il.Register(8, LLIL_TEMP(1)))); + break; + + default: + il.AddInstruction(il.Undefined()); + break; + } + break; + + case XED_ICLASS_ENTER: + { + uint32_t baseReg = addrSize == 4 ? XED_REG_EBP : XED_REG_RBP; + uint32_t stackReg = addrSize == 4 ? XED_REG_ESP : XED_REG_RSP; + if (xed_decoded_inst_get_second_immediate(xedd) != 0) + { + il.AddInstruction(il.Unimplemented()); + break; + } + il.AddInstruction(il.Push(addrSize, il.Register(addrSize, baseReg))); + il.AddInstruction(il.SetRegister(addrSize, baseReg, il.Register(addrSize, stackReg))); + if (immediateOne) + il.AddInstruction(il.SetRegister(addrSize, stackReg, + il.Sub(addrSize, + il.Register(addrSize, stackReg), + il.Const(2, immediateOne)))); + break; + } + + case XED_ICLASS_IDIV: + switch (opOneLen) + { + case 1: + il.AddInstruction(il.SetRegister(1, + LLIL_TEMP(0), + il.DivDoublePrecSigned(1, + il.Register(2, XED_REG_AX), + ReadILOperand(il, xedd, addr, 0, 0)))); + + il.AddInstruction(il.SetRegister(1, + LLIL_TEMP(1), + il.ModDoublePrecSigned(1, + il.Register(2, XED_REG_AX), + ReadILOperand(il, xedd, addr, 0, 0)))); + + il.AddInstruction( + il.SetRegister(1, + XED_REG_AL, + il.Register(1, LLIL_TEMP(0)))); + + il.AddInstruction( + il.SetRegister(1, + XED_REG_AH, + il.Register(1, LLIL_TEMP(1)))); + break; + + case 2: + il.AddInstruction( + il.SetRegister(2, + LLIL_TEMP(0), + il.DivDoublePrecSigned(2, + il.RegisterSplit(2, + XED_REG_DX, + XED_REG_AX), + ReadILOperand(il, xedd, addr, 0, 0)))); + + il.AddInstruction( + il.SetRegister(2, + LLIL_TEMP(1), + il.ModDoublePrecSigned(2, + il.RegisterSplit(2, + XED_REG_DX, + XED_REG_AX), + ReadILOperand(il, xedd, addr, 0, 0)))); + + il.AddInstruction( + il.SetRegister(2, + XED_REG_AX, + il.Register(2, LLIL_TEMP(0)))); + + il.AddInstruction( + il.SetRegister(2, + XED_REG_DX, + il.Register(2, LLIL_TEMP(1)))); + break; + + case 4: + il.AddInstruction(il.SetRegister(4, + LLIL_TEMP(0), + il.DivDoublePrecSigned(4, + il.RegisterSplit(4, + XED_REG_EDX, + XED_REG_EAX), + ReadILOperand(il, xedd, addr, 0, 0)))); + + il.AddInstruction( + il.SetRegister(4, + LLIL_TEMP(1), + il.ModDoublePrecSigned(4, + il.RegisterSplit(4, + XED_REG_EDX, + XED_REG_EAX), + ReadILOperand(il, xedd, addr, 0, 0)))); + + il.AddInstruction( + il.SetRegister(4, + XED_REG_EAX, + il.Register(4, LLIL_TEMP(0)))); + + il.AddInstruction( + il.SetRegister(4, + XED_REG_EDX, + il.Register(4, LLIL_TEMP(1)))); + break; + + case 8: + il.AddInstruction( + il.SetRegister(8, + LLIL_TEMP(0), + il.DivDoublePrecSigned(8, + il.RegisterSplit(8, + XED_REG_RDX, + XED_REG_RAX), + ReadILOperand(il, xedd, addr, 0, 0)))); + + il.AddInstruction( + il.SetRegister(8, + LLIL_TEMP(1), + il.ModDoublePrecSigned(8, + il.RegisterSplit(8, + XED_REG_RDX, + XED_REG_RAX), + ReadILOperand(il, xedd, addr, 0, 0)))); + + il.AddInstruction( + il.SetRegister(8, + XED_REG_RAX, + il.Register(8, LLIL_TEMP(0)))); + + il.AddInstruction( + il.SetRegister(8, + XED_REG_RDX, + il.Register(8, LLIL_TEMP(1)))); + break; + + default: + il.AddInstruction(il.Undefined()); + break; + } + break; + + case XED_ICLASS_IMUL: + switch (xedd_iForm) + { + case XED_IFORM_IMUL_GPR8: + case XED_IFORM_IMUL_GPRv: + case XED_IFORM_IMUL_MEMb: + case XED_IFORM_IMUL_MEMv: + switch (opOneLen) + { + case 1: + il.AddInstruction( + il.SetRegister(2, + XED_REG_AX, + il.MultDoublePrecSigned(1, + il.Register(1, XED_REG_AL), + ReadILOperand(il, xedd, addr, 0, 0), + IL_FLAGWRITE_CO))); + break; + case 2: + il.AddInstruction( + il.SetRegisterSplit(2, + XED_REG_DX, + XED_REG_AX, + il.MultDoublePrecSigned(2, + il.Register(2, XED_REG_AX), + ReadILOperand(il, xedd, addr, 0, 0), + IL_FLAGWRITE_CO))); + break; + case 4: + il.AddInstruction( + il.SetRegisterSplit(4, + XED_REG_EDX, + XED_REG_EAX, + il.MultDoublePrecSigned(4, + il.Register(4, XED_REG_EAX), + ReadILOperand(il, xedd, addr, 0, 0), + IL_FLAGWRITE_CO))); + break; + case 8: + il.AddInstruction( + il.SetRegisterSplit(8, + XED_REG_RDX, + XED_REG_RAX, + il.MultDoublePrecSigned(8, + il.Register(8, XED_REG_RAX), + ReadILOperand(il, xedd, addr, 0, 0), + IL_FLAGWRITE_CO))); + break; + default: + il.AddInstruction(il.Undefined()); + break; + } + break; + + case XED_IFORM_IMUL_GPRv_GPRv: + case XED_IFORM_IMUL_GPRv_MEMv: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Mult(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_CO))); + break; + + case XED_IFORM_IMUL_GPRv_GPRv_IMMb: + case XED_IFORM_IMUL_GPRv_GPRv_IMMz: + case XED_IFORM_IMUL_GPRv_MEMv_IMMb: + case XED_IFORM_IMUL_GPRv_MEMv_IMMz: + default: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Mult(opOneLen, + ReadILOperand(il, xedd, addr, 1, 1), + ReadILOperand(il, xedd, addr, 2, 2), + IL_FLAGWRITE_CO))); + } + break; + + + case XED_ICLASS_INC_LOCK: // TODO: Handle lock prefix + case XED_ICLASS_INC: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Add(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + il.Const(opOneLen, 1), + IL_FLAGWRITE_NOCARRY))); + break; + + case XED_ICLASS_INT: + switch (immediateOne) + { + case 0x29: + il.AddInstruction(il.Trap(TRAP_GPF)); + break; + case 0x80: + il.AddInstruction(il.SystemCall()); + break; + default: + il.AddInstruction(il.Trap(immediateOne)); + break; + } + break; + + case XED_ICLASS_INT3: + il.AddInstruction(il.Breakpoint()); + break; + + case XED_ICLASS_JMP: + if (opOne_name == XED_OPERAND_RELBR) + { + BNLowLevelILLabel* label = il.GetLabelForAddress(arch, branchDestination); + if (label) + il.AddInstruction(il.Goto(*label)); + else + il.AddInstruction(il.Jump(il.ConstPointer(addrSize, branchDestination))); + } + else + il.AddInstruction(il.Jump(ReadILOperand(il, xedd, addr, 0, 0))); + return false; + + case XED_ICLASS_JO: + ConditionalJump(arch, il, il.FlagCondition(LLFC_O), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JNO: + ConditionalJump(arch, il, il.FlagCondition(LLFC_NO), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JB: + ConditionalJump(arch, il, il.FlagGroup(IL_FLAG_GROUP_LT), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JNB: + ConditionalJump(arch, il, il.FlagGroup(IL_FLAG_GROUP_GE), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JZ: + ConditionalJump(arch, il, il.FlagGroup(IL_FLAG_GROUP_E), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JNZ: + ConditionalJump(arch, il, il.FlagGroup(IL_FLAG_GROUP_NE), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JBE: + ConditionalJump(arch, il, il.FlagGroup(IL_FLAG_GROUP_LE), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JNBE: + ConditionalJump(arch, il, il.FlagGroup(IL_FLAG_GROUP_GT), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JS: + ConditionalJump(arch, il, il.FlagCondition(LLFC_NEG), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JNS: + ConditionalJump(arch, il, il.FlagCondition(LLFC_POS), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JP: + ConditionalJump(arch, il, il.FlagGroup(IL_FLAG_GROUP_PE), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JNP: + ConditionalJump(arch, il, il.FlagGroup(IL_FLAG_GROUP_PO), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JL: + ConditionalJump(arch, il, il.FlagCondition(LLFC_SLT), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JNL: + ConditionalJump(arch, il, il.FlagCondition(LLFC_SGE), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JLE: + ConditionalJump(arch, il, il.FlagCondition(LLFC_SLE), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JNLE: + ConditionalJump(arch, il, il.FlagCondition(LLFC_SGT), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JCXZ: + ConditionalJump(arch, il, il.CompareEqual(2, il.Register(2, XED_REG_CX), il.Const(2, 0)), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JECXZ: + ConditionalJump(arch, il, il.CompareEqual(4, il.Register(4, XED_REG_ECX), il.Const(4, 0)), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_JRCXZ: + ConditionalJump(arch, il, il.CompareEqual(8, il.Register(8, XED_REG_RCX), il.Const(8, 0)), addrSize, branchDestination, addr + instLen); + return false; + + case XED_ICLASS_LAHF: + il.AddInstruction(il.SetRegister(1, XED_REG_AH, + il.Or(1, il.FlagBit(1, IL_FLAG_S, 7), + il.Or(1, il.FlagBit(1, IL_FLAG_Z, 6), + il.Or(1, il.FlagBit(1, IL_FLAG_A, 4), + il.Or(1, il.FlagBit(1, IL_FLAG_P, 2), il.FlagBit(1, IL_FLAG_C, 0))))))); + break; + + case XED_ICLASS_LEAVE: + il.AddInstruction( + il.SetRegister(addrSize, + GetStackPointer(addrSize), + il.Register(addrSize, GetFramePointer(addrSize)))); + + il.AddInstruction( + il.SetRegister(addrSize, + GetFramePointer(addrSize), + il.Pop(addrSize))); + break; + + case XED_ICLASS_LOOP: + if (addrSize == 4) + { + il.AddInstruction(il.SetRegister(4, XED_REG_ECX, il.Sub(4, il.Register(4, XED_REG_ECX), il.Const(4, 1)))); + ConditionalJump(arch, il, + il.CompareNotEqual(4, + il.Register(4, XED_REG_ECX), + il.Const(4, 0)), + addrSize, branchDestination, addr + instLen); + } + else + { + il.AddInstruction(il.SetRegister(8, XED_REG_RCX, il.Sub(8, il.Register(8, XED_REG_RCX), il.Const(8, 1)))); + ConditionalJump(arch, il, + il.CompareNotEqual(8, + il.Register(8, XED_REG_RCX), + il.Const(8, 0)), + addrSize, branchDestination, addr + instLen); + } + return false; + + case XED_ICLASS_LOOPE: + if (addrSize == 4) + { + il.AddInstruction(il.SetRegister(4, XED_REG_ECX, il.Sub(4, il.Register(4, XED_REG_ECX), il.Const(4, 1)))); + ConditionalJump(arch, il, + il.Or(0, + il.FlagGroup(IL_FLAG_GROUP_E), + il.CompareNotEqual(4, + il.Register(4, XED_REG_ECX), + il.Const(4, 0))), + addrSize, branchDestination, addr + instLen); + } + else + { + il.AddInstruction(il.SetRegister(8, XED_REG_RCX, il.Sub(8, il.Register(8, XED_REG_RCX), il.Const(8, 1)))); + ConditionalJump(arch, il, + il.Or(0, + il.FlagGroup(IL_FLAG_GROUP_E), + il.CompareNotEqual(8, + il.Register(8, XED_REG_RCX), + il.Const(8, 0))), + addrSize, branchDestination, addr + instLen); + } + return false; + + case XED_ICLASS_LOOPNE: + if (addrSize == 4) + { + il.AddInstruction(il.SetRegister(4, XED_REG_ECX, il.Sub(4, il.Register(4, XED_REG_ECX), il.Const(4, 1)))); + ConditionalJump(arch, il, + il.And(0, + il.FlagGroup(IL_FLAG_GROUP_NE), + il.CompareNotEqual(4, + il.Register(4, XED_REG_ECX), + il.Const(4, 0))), + addrSize, branchDestination, addr + instLen); + } + else + { + il.AddInstruction(il.SetRegister(8, XED_REG_RCX, il.Sub(8, il.Register(8, XED_REG_RCX), il.Const(8, 1)))); + ConditionalJump(arch, il, + il.And(0, + il.FlagGroup(IL_FLAG_GROUP_NE), + il.CompareNotEqual(8, + il.Register(8, XED_REG_RCX), + il.Const(8, 0))), + addrSize, branchDestination, addr + instLen); + } + return false; + + case XED_ICLASS_LEA: + if (opOneLen != opTwoLen) + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.LowPart(opOneLen, + GetILOperandMemoryAddress(il, xedd, addr, 1, 1)))); + } + else + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + GetILOperandMemoryAddress(il, xedd, addr, 1, 1))); + } + break; + + case XED_ICLASS_REP_LODSB: + case XED_ICLASS_REP_LODSD: + case XED_ICLASS_REP_LODSQ: + case XED_ICLASS_REP_LODSW: + case XED_ICLASS_LODSB: + case XED_ICLASS_LODSW: + case XED_ICLASS_LODSD: + case XED_ICLASS_LODSQ: + { + size_t loadSize; + uint32_t dstReg; + uint32_t srcReg = addrSize == 4 ? XED_REG_ESI : XED_REG_RSI; + switch (xedd_iClass) + { + case XED_ICLASS_LODSW: + case XED_ICLASS_REP_LODSW: + loadSize = 2; dstReg = XED_REG_AX; break; + case XED_ICLASS_LODSD: + case XED_ICLASS_REP_LODSD: + loadSize = 4; dstReg = XED_REG_EAX; break; + case XED_ICLASS_LODSQ: + case XED_ICLASS_REP_LODSQ: + loadSize = 8; dstReg = XED_REG_RAX; break; + case XED_ICLASS_REP_LODSB: + default: + loadSize = 1; dstReg = XED_REG_AL; + } + + Repeat(xedd, il, [&] (){ + DirFlagIf(il, + [&] () + { + il.AddInstruction(il.SetRegister(loadSize, dstReg, il.Load(loadSize, il.Register(addrSize, srcReg)))); + }, + [&] () // Dirflag is 1 + { + il.AddInstruction(il.SetRegister(addrSize, srcReg, il.Sub(addrSize, il.Register(addrSize, srcReg), il.Const(1, loadSize)))); + }, + [&] () // Dirflag is 0 + { + il.AddInstruction(il.SetRegister(addrSize, srcReg, il.Add(addrSize, il.Register(addrSize, srcReg), il.Const(1, loadSize)))); + }); + }); + break; + } + + case XED_ICLASS_MOV: + case XED_ICLASS_MOVD: + case XED_ICLASS_MOVQ: + case XED_ICLASS_VMOVD: + case XED_ICLASS_VMOVQ: + case XED_ICLASS_MOVDIRI: + case XED_ICLASS_MOVDIR64B: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + ReadILOperand(il, xedd, addr, 1, 1))); + break; + + case XED_ICLASS_MOVSX: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.SignExtend(opOneLen, + ReadILOperand(il, xedd, addr, 1, 1)))); + break; + + case XED_ICLASS_MOVSXD: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.SignExtend(opOneLen, + ReadILOperand(il, xedd, addr, 1, 1)))); + break; + + case XED_ICLASS_MOVZX: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.ZeroExtend(opOneLen, + ReadILOperand(il, xedd, addr, 1, 1)))); + break; + + case XED_ICLASS_MOVUPS: + case XED_ICLASS_MOVAPS: + case XED_ICLASS_MOVDQA: + case XED_ICLASS_MOVDQU: + case XED_ICLASS_VMOVUPS: + case XED_ICLASS_VMOVAPS: + case XED_ICLASS_VMOVDQA: + case XED_ICLASS_VMOVDQU: + case XED_ICLASS_LDDQU: + case XED_ICLASS_MOVAPD: + case XED_ICLASS_VMOVAPD: + case XED_ICLASS_MOVUPD: + case XED_ICLASS_VMOVUPD: + { + if (xed_classify_avx512(xedd)) + { + LiftAsIntrinsic(); + break; + } + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, ReadILOperand(il, xedd, addr, 1, 1))); + break; + } + + // despite MOVSS and VMOVSS both move floating point values, + // the move is the same as an ordinary move + case XED_ICLASS_MOVSS: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, ReadILOperand(il, xedd, addr, 1, 1))); + break; + + case XED_ICLASS_VMOVSS: + { + uint32_t noperands = xed_inst_noperands(xi); + if (noperands == 2) + // nothing special here + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, ReadILOperand(il, xedd, addr, 1, 1))); + else + { + if (xed_classify_avx512(xedd)) + { + LiftAsIntrinsic(); + break; + } + // the three operands form + // DEST[31:0] <- SRC2[31:0] + // DEST[127:32] <- SRC1[127:32] + // DEST[MAXVL-1:128] <- 0 + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.And(4, ReadILOperand(il, xedd, addr, 2, 2), il.Const(4, 0xffffffff)) + ) + ); + // il.Const() only supports constant up to uint64_t so far so I cannot use this mask + // here I first shift right and then shift left + // __uint128_t mask = (__uint128_t)0xffffffffffffffffffffffff00000000; + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Or(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + il.ShiftLeft( + opOneLen, + il.LogicalShiftRight(opOneLen, + ReadFloatILOperand(il, xedd, addr, 1, 1, opOneLen), + // vmovss ONLY suppors xmm, so we do not need to branch on operand size + il.Const(1, 32) + ), + il.Const(1, 32) + ) + ) + ) + ); + } + break; + } + + case XED_ICLASS_MOVNTDQ: + case XED_ICLASS_MOVNTDQA: + case XED_ICLASS_MOVNTI: + case XED_ICLASS_MOVNTPD: + case XED_ICLASS_MOVNTPS: + case XED_ICLASS_MOVNTQ: + case XED_ICLASS_MOVNTSD: + case XED_ICLASS_MOVNTSS: + + case XED_ICLASS_VMOVNTDQ: + case XED_ICLASS_VMOVNTDQA: + case XED_ICLASS_VMOVNTPD: + case XED_ICLASS_VMOVNTPS: + + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, ReadILOperand(il, xedd, addr, 1, 1))); + break; + + case XED_ICLASS_MOVLPD: + case XED_ICLASS_MOVLPS: + case XED_ICLASS_VMOVLPD: + case XED_ICLASS_VMOVLPS: + { + if (xed_inst_noperands(xi) == 2) + { + // MOVLPD xmm1, m64 + // VMOVLPD m64, xmm1 + // DEST[63:0] ← SRC[63:0] + // DEST[MAXVL-1:64] (Unmodified) + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + ReadILOperand(il, xedd, addr, 1, 1, 8), + 8 + ) + ); + } + else + { + // VMOVLPD xmm2, xmm1, m64 + // DEST[63:0] ← SRC2[63:0] + // DEST[127:64] ← SRC1[127:64] + // DEST[MAXVL-1:128] ← 0 + + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Or( + 16, + ReadILOperand(il, xedd, addr, 2, 2, 8), + il.And( + 16, + ReadILOperand(il, xedd, addr, 1, 1, 16), + il.ShiftLeft(16, + il.Const(8, 0xffffffffffffffff), + il.Const(1, 64)) + ) + ), + 16 + ) + ); + } + break; + } + + case XED_ICLASS_MOVHPD: + case XED_ICLASS_MOVHPS: + case XED_ICLASS_VMOVHPD: + case XED_ICLASS_VMOVHPS: + { + if (xed_inst_noperands(xi) == 2) + { + // MOVHPD xmm1, m64 + // DEST[63:0] (Unmodified) + // DEST[127:64] ← SRC[63:0] + // DEST[MAXVL-1:128] (Unmodified) + + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Or( + 16, + ReadILOperand(il, xedd, addr, 0, 0, 8), + il.ShiftLeft( + 16, + ReadILOperand(il, xedd, addr, 1, 1, 8), + il.Const(1, 64) + ) + ), + 16 + ) + ); + } + else + { + // VMOVHPD xmm2, xmm1, m64 + // DEST[63:0] ← SRC1[63:0] + // DEST[127:64] ← SRC2[63:0] + // DEST[MAXVL-1:128] ← 0 + + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Or( + 16, + ReadILOperand(il, xedd, addr, 1, 1, 8), + il.ShiftLeft( + 16, + ReadILOperand(il, xedd, addr, 2, 2, 8), + il.Const(1, 64) + ) + ), + 16 + ) + ); + } + break; + } + + case XED_ICLASS_MOVHLPS: + { + // MOVHLPS xmm1, xmm2 + // DEST[63:0] ← SRC[127:64] + // DEST[MAXVL-1:64] (Unmodified) + + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.LogicalShiftRight( + 16, + ReadILOperand(il, xedd, addr, 1, 1, 16), + il.Const(1, 64) + ), + 8 + ) + ); + break; + } + + case XED_ICLASS_VMOVHLPS: + { + // VMOVHLPS xmm1, xmm2, xmm3 + // DEST[63:0] ← SRC2[127:64] + // DEST[127:64] ← SRC1[127:64] + // DEST[MAXVL-1:128] ← 0 + + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Or( + 16, + il.And( + 16, + ReadILOperand(il, xedd, addr, 1, 1, 16), + il.ShiftLeft(16, + il.Const(8, 0xffffffffffffffff), + il.Const(1, 64)) + ), + il.LogicalShiftRight( + 16, + ReadILOperand(il, xedd, addr, 2, 2, 16), + il.Const(1, 64) + ) + ), + 16 + ) + ); + + break; + } + + case XED_ICLASS_MOVLHPS: + { + // MOVLHPS xmm1, xmm2 + // DEST[63:0] (Unmodified) + // DEST[127:64] ← SRC[63:0] + // DEST[MAXVL-1:128] (Unmodified) + + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Or( + 16, + ReadILOperand(il, xedd, addr, 0, 0, 8), + il.ShiftLeft( + 16, + ReadILOperand(il, xedd, addr, 1, 1, 8), + il.Const(1, 64) + ) + ), + 16 + ) + ); + + break; + } + + case XED_ICLASS_VMOVLHPS: + { + // VMOVLHPS xmm1, xmm2, xmm3 + // DEST[63:0] ← SRC1[63:0] + // DEST[127:64] ← SRC2[63:0] + // DEST[MAXVL-1:128] ← 0 + + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Or( + 16, + ReadILOperand(il, xedd, addr, 1, 1, 8), + il.ShiftLeft( + 16, + ReadILOperand(il, xedd, addr, 2, 2, 8), + il.Const(1, 64) + ) + ), + 16 + ) + ); + + break; + } + + case XED_ICLASS_MOVSD_XMM: + // SSE instruction MOVSD + if (xed_operand_is_register(opTwo_name)) + { + // movsd xmm, xmm + // movsd mem, xmm + // 64 bits at dst equals low part src xmm reg + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.LowPart(8, il.Register(16, regTwo)))); + } + else // movsd xmm, mem + { + // low part of dst xmm reg equals 64 bits from src + // high part is zerod + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.ZeroExtend(16, + il.Load(8, + GetILOperandMemoryAddress(il, xedd, addr, 1, 1))))); + } + break; + + case XED_ICLASS_REP_MOVSB: + case XED_ICLASS_REP_MOVSW: + case XED_ICLASS_REP_MOVSD: + case XED_ICLASS_REP_MOVSQ: + case XED_ICLASS_MOVSB: + case XED_ICLASS_MOVSW: + case XED_ICLASS_MOVSD: + case XED_ICLASS_MOVSQ: + { + uint32_t intrinsic = INTRINSIC_XED_IFORM_REP_MOVSB; + uint32_t srcReg = addrSize == 4 ? XED_REG_ESI : XED_REG_RSI; + uint32_t dstReg = addrSize == 4 ? XED_REG_EDI : XED_REG_RDI; + size_t moveSize; + switch (xedd_iClass) + { + case XED_ICLASS_REP_MOVSW: + case XED_ICLASS_MOVSW: + intrinsic = INTRINSIC_XED_IFORM_REP_MOVSW; + moveSize = 2; + break; + case XED_ICLASS_REP_MOVSD: + case XED_ICLASS_MOVSD: + intrinsic = INTRINSIC_XED_IFORM_REP_MOVSD; + moveSize = 4; + break; + case XED_ICLASS_REP_MOVSQ: + case XED_ICLASS_MOVSQ: + intrinsic = INTRINSIC_XED_IFORM_REP_MOVSQ; + moveSize = 8; + break; + default: + moveSize = 1; + break; + } + + if (xed_operand_values_has_real_rep(xed_decoded_inst_operands_const(xedd))) + { + ExprId countExpr = il.Register(addrSize, GetCountRegister(addrSize)); + + DirFlagIf(il, + [&](){}, + [&]() // Direction flag 1 + { + auto dstExpr = il.Sub(addrSize, il.Register(addrSize, dstReg), countExpr); + auto srcExpr = il.Sub(addrSize, il.Register(addrSize, srcReg), countExpr); + il.AddInstruction(il.Intrinsic( + vector<RegisterOrFlag> { RegisterOrFlag::Register(dstReg), RegisterOrFlag::Register(srcReg), RegisterOrFlag::Register(GetCountRegister(addrSize)) }, + intrinsic, + vector<ExprId> { dstExpr, srcExpr, countExpr } + )); + }, + [&]() // Direction flag 0 + { + auto dstExpr = il.Sub(addrSize, il.Register(addrSize, dstReg), countExpr); + auto srcExpr = il.Sub(addrSize, il.Register(addrSize, srcReg), countExpr); + il.AddInstruction(il.Intrinsic( + vector<RegisterOrFlag> { RegisterOrFlag::Register(dstReg), RegisterOrFlag::Register(srcReg), RegisterOrFlag::Register(GetCountRegister(addrSize)) }, + intrinsic, + vector<ExprId> { dstExpr, srcExpr, countExpr } + )); + } + ); + break; + } + + Repeat(xedd, il, [&] (){ + DirFlagIf(il, + [&](){}, // Pre check direction flag check + [&]() // Direction flag true + { + il.AddInstruction(il.Store(moveSize, il.Register(addrSize, dstReg), + il.Load(moveSize, il.Register(addrSize, srcReg)))); + + il.AddInstruction( + il.SetRegister(addrSize, + dstReg, + il.Sub(addrSize, + il.Register(addrSize, dstReg), + il.Const(addrSize, moveSize)))); + + il.AddInstruction( + il.SetRegister(addrSize, + srcReg, + il.Sub(addrSize, + il.Register(addrSize, srcReg), + il.Const(addrSize, moveSize)))); + }, + [&]() // Direction flag false + { + il.AddInstruction( + il.Store(moveSize, + il.Register(addrSize, dstReg), + il.Load(moveSize, + il.Register(addrSize, srcReg)))); + + il.AddInstruction( + il.SetRegister(addrSize, + dstReg, + il.Add(addrSize, + il.Register(addrSize, dstReg), + il.Const(addrSize, moveSize)))); + + il.AddInstruction( + il.SetRegister(addrSize, + srcReg, + il.Add(addrSize, + il.Register(addrSize, srcReg), + il.Const(addrSize, moveSize)))); + }); + }); + break; + } + case XED_ICLASS_MUL: + switch (opOneLen) + { + case 1: + il.AddInstruction( + il.SetRegister(2, + XED_REG_AX, + il.MultDoublePrecUnsigned(1, + il.Register(1, XED_REG_AL), + ReadILOperand(il, xedd, addr, 0, 0), + IL_FLAGWRITE_CO))); + break; + case 2: + il.AddInstruction( + il.SetRegisterSplit(2, + XED_REG_DX, + XED_REG_AX, + il.MultDoublePrecUnsigned(2, + il.Register(2, XED_REG_AX), + ReadILOperand(il, xedd, addr, 0, 0), + IL_FLAGWRITE_CO))); + break; + case 4: + il.AddInstruction( + il.SetRegisterSplit(4, + XED_REG_EDX, + XED_REG_EAX, + il.MultDoublePrecUnsigned(4, + il.Register(4, XED_REG_EAX), + ReadILOperand(il, xedd, addr, 0, 0), + IL_FLAGWRITE_CO))); + break; + case 8: + il.AddInstruction( + il.SetRegisterSplit(8, + XED_REG_RDX, + XED_REG_RAX, + il.MultDoublePrecUnsigned(8, + il.Register(8, XED_REG_RAX), + ReadILOperand(il, xedd, addr, 0, 0), + IL_FLAGWRITE_CO))); + break; + default: + il.AddInstruction(il.Undefined()); + break; + } + break; + + case XED_ICLASS_NEG_LOCK: // TODO: Handle lock prefix + case XED_ICLASS_NEG: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Neg(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + IL_FLAGWRITE_ALL))); + break; + + case XED_ICLASS_NOP: + case XED_ICLASS_NOP2: + case XED_ICLASS_NOP3: + case XED_ICLASS_NOP4: + case XED_ICLASS_NOP5: + case XED_ICLASS_NOP6: + case XED_ICLASS_NOP7: + case XED_ICLASS_NOP8: + case XED_ICLASS_NOP9: + case XED_ICLASS_FNOP: + case XED_ICLASS_FDISI8087_NOP: + case XED_ICLASS_FENI8087_NOP: + case XED_ICLASS_FSETPM287_NOP: + + case XED_ICLASS_PAUSE: + + case XED_ICLASS_PREFETCHNTA: + case XED_ICLASS_PREFETCHT0: + case XED_ICLASS_PREFETCHT1: + case XED_ICLASS_PREFETCHT2: + case XED_ICLASS_PREFETCHW: + case XED_ICLASS_PREFETCHWT1: + case XED_ICLASS_PREFETCH_EXCLUSIVE: + case XED_ICLASS_PREFETCH_RESERVED: + + case XED_ICLASS_FWAIT: + + case XED_ICLASS_LFENCE: + case XED_ICLASS_MFENCE: + case XED_ICLASS_SFENCE: + + case XED_ICLASS_ENDBR32: + case XED_ICLASS_ENDBR64: + il.AddInstruction(il.Nop()); + break; + + case XED_ICLASS_NOT_LOCK: // TODO: Handle lock prefix + case XED_ICLASS_NOT: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Not(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0)))); + break; + + case XED_ICLASS_OR_LOCK: // TODO: Handle lock prefix + case XED_ICLASS_OR: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Or(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_ALL))); + break; + case XED_ICLASS_POR: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Or(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + 0))); // POR doesn't modify any flag + break; + case XED_ICLASS_VPOR: + if (xed_classify_avx512(xedd)) + { + LiftAsIntrinsic(); + break; + } + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Or(opOneLen, + ReadILOperand(il, xedd, addr, 1, 1), + ReadILOperand(il, xedd, addr, 2, 2), + 0))); // VPOR doesn't modify flags + break; + + case XED_ICLASS_POP: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Pop(opOneLen))); + break; + + case XED_ICLASS_POPA: + il.AddInstruction(il.SetRegister(2, XED_REG_DI, il.Pop(2))); + il.AddInstruction(il.SetRegister(2, XED_REG_SI, il.Pop(2))); + il.AddInstruction(il.SetRegister(2, XED_REG_BP, il.Pop(2))); + il.AddInstruction(il.SetRegister(2, XED_REG_SP, il.Add(2, il.Register(2, XED_REG_SP), il.Const(2, 2)))); + il.AddInstruction(il.SetRegister(2, XED_REG_BX, il.Pop(2))); + il.AddInstruction(il.SetRegister(2, XED_REG_DX, il.Pop(2))); + il.AddInstruction(il.SetRegister(2, XED_REG_CX, il.Pop(2))); + il.AddInstruction(il.SetRegister(2, XED_REG_AX, il.Pop(2))); + break; + + case XED_ICLASS_POPAD: + il.AddInstruction(il.SetRegister(4, XED_REG_EDI, il.Pop(4))); + il.AddInstruction(il.SetRegister(4, XED_REG_ESI, il.Pop(4))); + il.AddInstruction(il.SetRegister(4, XED_REG_EBP, il.Pop(4))); + il.AddInstruction(il.SetRegister(4, XED_REG_ESP, il.Add(4, il.Register(4, XED_REG_ESP), il.Const(4, 4)))); + il.AddInstruction(il.SetRegister(4, XED_REG_EBX, il.Pop(4))); + il.AddInstruction(il.SetRegister(4, XED_REG_EDX, il.Pop(4))); + il.AddInstruction(il.SetRegister(4, XED_REG_ECX, il.Pop(4))); + il.AddInstruction(il.SetRegister(4, XED_REG_EAX, il.Pop(4))); + break; + + case XED_ICLASS_POPF: + il.AddInstruction(il.SetRegister(2, LLIL_TEMP(0), il.Pop(2))); + il.AddInstruction(il.SetFlag(IL_FLAG_C, il.TestBit(2, il.Register(2, LLIL_TEMP(0)), il.Const(1, 0)))); + il.AddInstruction(il.SetFlag(IL_FLAG_P, il.TestBit(2, il.Register(2, LLIL_TEMP(0)), il.Const(1, 2)))); + il.AddInstruction(il.SetFlag(IL_FLAG_A, il.TestBit(2, il.Register(2, LLIL_TEMP(0)), il.Const(1, 4)))); + il.AddInstruction(il.SetFlag(IL_FLAG_Z, il.TestBit(2, il.Register(2, LLIL_TEMP(0)), il.Const(1, 6)))); + il.AddInstruction(il.SetFlag(IL_FLAG_S, il.TestBit(2, il.Register(2, LLIL_TEMP(0)), il.Const(1, 7)))); + il.AddInstruction(il.SetFlag(IL_FLAG_D, il.TestBit(2, il.Register(2, LLIL_TEMP(0)), il.Const(1, 10)))); + il.AddInstruction(il.SetFlag(IL_FLAG_O, il.TestBit(2, il.Register(2, LLIL_TEMP(0)), il.Const(1, 11)))); + break; + + case XED_ICLASS_POPFD: + il.AddInstruction(il.SetRegister(4, LLIL_TEMP(0), il.Pop(4))); + il.AddInstruction(il.SetFlag(IL_FLAG_C, il.TestBit(4, il.Register(4, LLIL_TEMP(0)), il.Const(1, 0)))); + il.AddInstruction(il.SetFlag(IL_FLAG_P, il.TestBit(4, il.Register(4, LLIL_TEMP(0)), il.Const(1, 2)))); + il.AddInstruction(il.SetFlag(IL_FLAG_A, il.TestBit(4, il.Register(4, LLIL_TEMP(0)), il.Const(1, 4)))); + il.AddInstruction(il.SetFlag(IL_FLAG_Z, il.TestBit(4, il.Register(4, LLIL_TEMP(0)), il.Const(1, 6)))); + il.AddInstruction(il.SetFlag(IL_FLAG_S, il.TestBit(4, il.Register(4, LLIL_TEMP(0)), il.Const(1, 7)))); + il.AddInstruction(il.SetFlag(IL_FLAG_D, il.TestBit(4, il.Register(4, LLIL_TEMP(0)), il.Const(1, 10)))); + il.AddInstruction(il.SetFlag(IL_FLAG_O, il.TestBit(4, il.Register(4, LLIL_TEMP(0)), il.Const(1, 11)))); + break; + + case XED_ICLASS_POPFQ: + il.AddInstruction(il.SetRegister(8, LLIL_TEMP(0), il.Pop(8))); + il.AddInstruction(il.SetFlag(IL_FLAG_C, il.TestBit(8, il.Register(8, LLIL_TEMP(0)), il.Const(1, 0)))); + il.AddInstruction(il.SetFlag(IL_FLAG_P, il.TestBit(8, il.Register(8, LLIL_TEMP(0)), il.Const(1, 2)))); + il.AddInstruction(il.SetFlag(IL_FLAG_A, il.TestBit(8, il.Register(8, LLIL_TEMP(0)), il.Const(1, 4)))); + il.AddInstruction(il.SetFlag(IL_FLAG_Z, il.TestBit(8, il.Register(8, LLIL_TEMP(0)), il.Const(1, 6)))); + il.AddInstruction(il.SetFlag(IL_FLAG_S, il.TestBit(8, il.Register(8, LLIL_TEMP(0)), il.Const(1, 7)))); + il.AddInstruction(il.SetFlag(IL_FLAG_D, il.TestBit(8, il.Register(8, LLIL_TEMP(0)), il.Const(1, 10)))); + il.AddInstruction(il.SetFlag(IL_FLAG_O, il.TestBit(8, il.Register(8, LLIL_TEMP(0)), il.Const(1, 11)))); + break; + + case XED_ICLASS_PUSHA: + il.AddInstruction(il.Push(2, il.Register(2, XED_REG_AX))); + il.AddInstruction(il.Push(2, il.Register(2, XED_REG_CX))); + il.AddInstruction(il.Push(2, il.Register(2, XED_REG_DX))); + il.AddInstruction(il.Push(2, il.Register(2, XED_REG_BX))); + il.AddInstruction(il.Push(2, il.Register(2, XED_REG_SP))); + il.AddInstruction(il.Push(2, il.Register(2, XED_REG_BP))); + il.AddInstruction(il.Push(2, il.Register(2, XED_REG_SI))); + il.AddInstruction(il.Push(2, il.Register(2, XED_REG_DI))); + break; + + case XED_ICLASS_PUSHAD: + il.AddInstruction(il.Push(4, il.Register(4, XED_REG_EAX))); + il.AddInstruction(il.Push(4, il.Register(4, XED_REG_ECX))); + il.AddInstruction(il.Push(4, il.Register(4, XED_REG_EDX))); + il.AddInstruction(il.Push(4, il.Register(4, XED_REG_EBX))); + il.AddInstruction(il.Push(4, il.Register(4, XED_REG_ESP))); + il.AddInstruction(il.Push(4, il.Register(4, XED_REG_EBP))); + il.AddInstruction(il.Push(4, il.Register(4, XED_REG_ESI))); + il.AddInstruction(il.Push(4, il.Register(4, XED_REG_EDI))); + break; + + case XED_ICLASS_PUSHF: + il.AddInstruction(il.Push(2, + il.Or(2, il.FlagBit(2, IL_FLAG_O, 11), + il.Or(2, il.FlagBit(2, IL_FLAG_D, 10), + il.Or(2, il.FlagBit(2, IL_FLAG_S, 7), + il.Or(2, il.FlagBit(2, IL_FLAG_Z, 6), + il.Or(2, il.FlagBit(2, IL_FLAG_A, 4), + il.Or(2, il.FlagBit(2, IL_FLAG_P, 2), + il.FlagBit(2, IL_FLAG_C, 0))))))))); + break; + + case XED_ICLASS_PUSHFD: + il.AddInstruction(il.Push(4, + il.Or(4, il.FlagBit(4, IL_FLAG_O, 11), + il.Or(4, il.FlagBit(4, IL_FLAG_D, 10), + il.Or(4, il.FlagBit(4, IL_FLAG_S, 7), + il.Or(4, il.FlagBit(4, IL_FLAG_Z, 6), + il.Or(4, il.FlagBit(4, IL_FLAG_A, 4), + il.Or(4, il.FlagBit(4, IL_FLAG_P, 2), + il.FlagBit(4, IL_FLAG_C, 0))))))))); + break; + + case XED_ICLASS_PUSHFQ: + il.AddInstruction( + il.Push(8, + il.Or(8, + il.FlagBit(8, IL_FLAG_O, 11), + il.Or(8, + il.FlagBit(8, IL_FLAG_D, 10), + il.Or(8, + il.FlagBit(8, IL_FLAG_S, 7), + il.Or(8, + il.FlagBit(8, IL_FLAG_Z, 6), + il.Or(8, + il.FlagBit(8, IL_FLAG_A, 4), + il.Or(8, + il.FlagBit(8, IL_FLAG_P, 2), + il.FlagBit(8, IL_FLAG_C, 0) + ) + ) + ) + ) + ) + ) + ) + ); + break; + + case XED_ICLASS_PUSH: + { + const unsigned int stackAdjustment = xed_decoded_inst_get_memop_address_width(xedd, 0) / 8; + if (opOneLen != stackAdjustment) // 32-bit push on 64-bit pushes a 64-bit value + { + il.AddInstruction( + il.Push(stackAdjustment, + il.ZeroExtend(stackAdjustment, + ReadILOperand(il, xedd, addr, 0, 0)))); + } + else + il.AddInstruction( + il.Push(stackAdjustment, + ReadILOperand(il, xedd, addr, 0, 0))); + break; + } + + case XED_ICLASS_RCL: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.RotateLeftCarry(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + il.Flag(IL_FLAG_C), IL_FLAGWRITE_ALL))); + break; + + case XED_ICLASS_RCR: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.RotateRightCarry(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + il.Flag(IL_FLAG_C), IL_FLAGWRITE_ALL))); + break; + + case XED_ICLASS_RET_NEAR: + if ((opOne_name != XED_OPERAND_IMM0) || (immediateOne == 0)) + il.AddInstruction(il.Return(il.Pop(addrSize))); + else + { + il.AddInstruction(il.SetRegister(addrSize, LLIL_TEMP(0), il.Pop(addrSize))); + il.AddInstruction( + il.SetRegister(addrSize, + GetStackPointer(addrSize), + il.Add(addrSize, + il.Register(addrSize, GetStackPointer(addrSize)), + il.Const(addrSize, immediateOne)))); + + il.AddInstruction(il.Return(il.Register(addrSize, LLIL_TEMP(0)))); + } + break; + + case XED_ICLASS_ROL: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.RotateLeft(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_ALL))); + break; + + case XED_ICLASS_ROR: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.RotateRight(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_ALL))); + break; + + // there is no ROLX instruciton + case XED_ICLASS_RORX: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.RotateRight(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1) + ))); + break; + + case XED_ICLASS_SAR: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.ArithShiftRight(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_ALL))); + break; + + case XED_ICLASS_SARX: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.ArithShiftRight(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1) + ))); + break; + + case XED_ICLASS_SAHF: + il.AddInstruction(il.SetFlag(IL_FLAG_C, il.TestBit(1, il.Register(1, XED_REG_AH), il.Const(1, 0)))); + il.AddInstruction(il.SetFlag(IL_FLAG_P, il.TestBit(1, il.Register(1, XED_REG_AH), il.Const(1, 2)))); + il.AddInstruction(il.SetFlag(IL_FLAG_A, il.TestBit(1, il.Register(1, XED_REG_AH), il.Const(1, 4)))); + il.AddInstruction(il.SetFlag(IL_FLAG_Z, il.TestBit(1, il.Register(1, XED_REG_AH), il.Const(1, 6)))); + il.AddInstruction(il.SetFlag(IL_FLAG_S, il.TestBit(1, il.Register(1, XED_REG_AH), il.Const(1, 7)))); + break; + + case XED_ICLASS_SBB_LOCK: // TODO: Handle lock prefix + case XED_ICLASS_SBB: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.SubBorrow(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + il.Flag(IL_FLAG_C), IL_FLAGWRITE_ALL))); + break; + + case XED_ICLASS_REPE_SCASB: + case XED_ICLASS_REPE_SCASD: + case XED_ICLASS_REPE_SCASQ: + case XED_ICLASS_REPE_SCASW: + case XED_ICLASS_REPNE_SCASB: + case XED_ICLASS_REPNE_SCASD: + case XED_ICLASS_REPNE_SCASQ: + case XED_ICLASS_REPNE_SCASW: + case XED_ICLASS_SCASB: + case XED_ICLASS_SCASW: + case XED_ICLASS_SCASD: + case XED_ICLASS_SCASQ: + { + size_t searchSize; + uint32_t cmpReg; + uint32_t srcReg = addrSize == 4 ? XED_REG_EDI : XED_REG_RDI; + switch (xedd_iClass) + { + case XED_ICLASS_REPE_SCASW: + case XED_ICLASS_REPNE_SCASW: + case XED_ICLASS_SCASW: + searchSize = 2; + cmpReg = XED_REG_AX; + break; + case XED_ICLASS_REPE_SCASD: + case XED_ICLASS_REPNE_SCASD: + case XED_ICLASS_SCASD: + searchSize = 4; + cmpReg = XED_REG_EAX; + break; + case XED_ICLASS_REPE_SCASQ: + case XED_ICLASS_REPNE_SCASQ: + case XED_ICLASS_SCASQ: + searchSize = 8; + cmpReg = XED_REG_RAX; + break; + default: + searchSize = 1; + cmpReg = XED_REG_AL; + break; + } + + Repeat(xedd, il, [&]() { + DirFlagIf(il, [&]() + { + (void)addrSize; + il.AddInstruction(il.Sub(searchSize, il.Register(searchSize, cmpReg), il.Load(searchSize, il.Register(addrSize, srcReg)), IL_FLAGWRITE_ALL)); + }, + [&] () // Direction flag is 1 + { + il.AddInstruction(il.SetRegister(addrSize, srcReg, il.Sub(addrSize, il.Register(addrSize, srcReg), il.Const(addrSize, searchSize)))); + }, + [&] () // Direction flag is 0 + { + il.AddInstruction(il.SetRegister(addrSize, srcReg, il.Add(addrSize, il.Register(addrSize, srcReg), il.Const(addrSize, searchSize)))); + }); + }); + break; + } + + case XED_ICLASS_SETO: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.Flag(IL_FLAG_O))); + break; + + case XED_ICLASS_SETNO: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.Not(0, il.Flag(IL_FLAG_O)))); + break; + + case XED_ICLASS_SETB: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.Flag(IL_FLAG_C))); + break; + + case XED_ICLASS_SETNB: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.FlagGroup(IL_FLAG_GROUP_GE))); + break; + + case XED_ICLASS_SETZ: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.FlagGroup(IL_FLAG_GROUP_E))); + break; + + case XED_ICLASS_SETNZ: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.FlagGroup(IL_FLAG_GROUP_NE))); + break; + + case XED_ICLASS_SETBE: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.FlagGroup(IL_FLAG_GROUP_LE))); + break; + + case XED_ICLASS_SETNBE: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.FlagGroup(IL_FLAG_GROUP_GT))); + break; + + case XED_ICLASS_SETS: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.FlagCondition(LLFC_NEG))); + break; + + case XED_ICLASS_SETNS: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.FlagCondition(LLFC_POS))); + break; + + case XED_ICLASS_SETP: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.FlagGroup(IL_FLAG_GROUP_PE))); + break; + + case XED_ICLASS_SETNP: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.FlagGroup(IL_FLAG_GROUP_PO))); + break; + + case XED_ICLASS_SETL: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.FlagCondition(LLFC_SLT))); + break; + + case XED_ICLASS_SETNL: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.FlagCondition(LLFC_SGE))); + break; + + case XED_ICLASS_SETLE: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.FlagCondition(LLFC_SLE))); + break; + + case XED_ICLASS_SETNLE: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, il.FlagCondition(LLFC_SGT))); + break; + + case XED_ICLASS_SHL: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.ShiftLeft(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_ALL))); + break; + + // This is imprecise since it does NOT move the last shifted bit into CF + // the same problem also happens on SHL, SAR + case XED_ICLASS_SHR: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.LogicalShiftRight(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_ALL))); + break; + + case XED_ICLASS_SHLX: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.ShiftLeft(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1) + ))); + break; + + case XED_ICLASS_SHRX: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.LogicalShiftRight(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1) + ))); + break; + + case XED_ICLASS_SHLD: + { + size_t opSize = opOneLen; + size_t mask = opSize == 4 ? 31 : 63; + + // Shift left double: operand[0] = operand[0]:operand[1] << operand[3] + // this since we can't easily operation on a combined register we do it like this + // operand[0] = (operand[0] << operand[3]) | (operand[1] >> (63|32 - operand[3])) + // One final cevate operand[3] must be masked with 63|32 + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.Or(opSize, + il.ShiftLeft(opSize, + ReadILOperand(il, xedd, addr, 0, 0), + il.And(opSize, + il.Const(1, mask), + ReadILOperand(il, xedd, addr, 2, 2)), + IL_FLAGWRITE_ALL), + il.LogicalShiftRight(opSize, + ReadILOperand(il, xedd, addr, 1, 1), + il.Sub(opSize, + il.And(opSize, + il.Const(1, mask), + ReadILOperand(il, xedd, addr, 2, 2)), + il.Const(1, opSize * 8)))))); + break; + } + case XED_ICLASS_SHRD: + { + size_t opSize = opOneLen; + size_t mask = opSize == 4 ? 31 : 63; + + // Shift right double: operand[0] = operand[0]:operand[1] >> operand[3] + // this since we can't easily operation on a combined register we do it like this + // operand[0] = (operand[0] >> operand[3]) | (operand[1] << (63|31 - operand[3])) + // One final cevate operand[3] must be masked with 63|31 + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.Or(opSize, + il.LogicalShiftRight(opSize, + ReadILOperand(il, xedd, addr, 0, 0), + il.And(opSize, + il.Const(1, mask), + ReadILOperand(il, xedd, addr, 2, 2)), + IL_FLAGWRITE_ALL), + il.ShiftLeft(opSize, + ReadILOperand(il, xedd, addr, 1, 1), + il.Sub(opSize, + il.Const(1, opSize * 8), + il.And(opSize, + il.Const(1, mask), + ReadILOperand(il, xedd, addr, 2, 2))))))); + break; + } + case XED_ICLASS_STOSB: + case XED_ICLASS_STOSW: + case XED_ICLASS_STOSD: + case XED_ICLASS_STOSQ: + case XED_ICLASS_REP_STOSB: + case XED_ICLASS_REP_STOSW: + case XED_ICLASS_REP_STOSD: + case XED_ICLASS_REP_STOSQ: + { + uint32_t intrinsic = INTRINSIC_XED_IFORM_REP_STOSB; + size_t moveSize = 1; + ExprId moveReg = 0; + uint32_t ilDestReg = addrSize == 4 ? XED_REG_EDI : XED_REG_RDI; + switch (xedd_iClass) + { + case XED_ICLASS_STOSB: + case XED_ICLASS_REP_STOSB: + intrinsic = INTRINSIC_XED_IFORM_REP_STOSB; + moveSize = 1; moveReg = il.Register(moveSize, XED_REG_AL); + break; + case XED_ICLASS_STOSW: + case XED_ICLASS_REP_STOSW: + intrinsic = INTRINSIC_XED_IFORM_REP_STOSW; + moveSize = 2; moveReg = il.Register(moveSize, XED_REG_AX); + break; + case XED_ICLASS_STOSD: + case XED_ICLASS_REP_STOSD: + intrinsic = INTRINSIC_XED_IFORM_REP_STOSD; + moveSize = 4; moveReg = il.Register(moveSize, XED_REG_EAX); + break; + case XED_ICLASS_STOSQ: + case XED_ICLASS_REP_STOSQ: + intrinsic = INTRINSIC_XED_IFORM_REP_STOSQ; + moveSize = 8; moveReg = il.Register(moveSize, XED_REG_RAX); + break; + default: break; + } + + if (xed_operand_values_has_real_rep(xed_decoded_inst_operands_const(xedd))) + { + ExprId countExpr = il.Register(addrSize, GetCountRegister(addrSize)); + DirFlagIf(il, + [&](){}, + [&]() // Direction flag 1 + { + il.AddInstruction(il.Intrinsic( + vector<RegisterOrFlag> { RegisterOrFlag::Register(ilDestReg), RegisterOrFlag::Register(GetCountRegister(addrSize)) }, + intrinsic, + vector<ExprId> { il.Sub(addrSize, il.Register(addrSize, ilDestReg), countExpr), moveReg, countExpr } + )); + }, + [&]() // Direction flag 0 + { + il.AddInstruction(il.Intrinsic( + vector<RegisterOrFlag> { RegisterOrFlag::Register(ilDestReg), RegisterOrFlag::Register(GetCountRegister(addrSize)) }, + intrinsic, + vector<ExprId> { il.Register(addrSize, ilDestReg), moveReg, countExpr } + )); + } + ); + break; + } + + Repeat(xedd, il, [&](){ + DirFlagIf(il, + [&](){}, + [&]() // Direction flag 1 + { + il.AddInstruction( + il.Store(moveSize, + il.Register(addrSize, ilDestReg), + moveReg)); + + il.AddInstruction( + il.SetRegister(addrSize, + ilDestReg, + il.Sub(addrSize, + il.Register(addrSize, ilDestReg), + il.Const(addrSize, moveSize)))); + }, + [&]() // Direction flag 0 + { + il.AddInstruction( + il.Store(moveSize, + il.Register(addrSize, ilDestReg), + moveReg)); + + il.AddInstruction( + il.SetRegister(addrSize, + ilDestReg, + il.Add(addrSize, + il.Register(addrSize, ilDestReg), + il.Const(addrSize, moveSize)))); + } + ); + }); + break; + } + + case XED_ICLASS_STC: + il.AddInstruction(il.SetFlag(IL_FLAG_C, il.Const(1, 1))); + break; + + case XED_ICLASS_STD: + il.AddInstruction(il.SetFlag(IL_FLAG_D, il.Const(1, 1))); + break; + + case XED_ICLASS_SUB_LOCK: // TODO: Handle lock prefix + case XED_ICLASS_SUB: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Sub(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_ALL))); + break; + + case XED_ICLASS_TEST: + il.AddInstruction( + il.And(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_ALL)); + break; + + case XED_ICLASS_PTEST: + case XED_ICLASS_VPTEST: + il.AddInstruction( + il.SetFlag(IL_FLAG_Z, + il.BoolToInt( + 1, + il.CompareEqual( + opOneLen, + il.And( + opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1) + ), + il.Const(opOneLen, 0) + ) + ) + ) + ); + il.AddInstruction( + il.SetFlag(IL_FLAG_C, + il.BoolToInt( + 1, + il.CompareEqual( + opOneLen, + il.And( + opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + il.Not(opTwoLen, + ReadILOperand(il, xedd, addr, 1, 1) + ) + ), + il.Const(opOneLen, 0) + ) + ) + ) + ); + break; + + case XED_ICLASS_XCHG: + il.AddInstruction(il.SetRegister(opOneLen, LLIL_TEMP(0), ReadILOperand(il, xedd, addr, 0, 0))); + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, ReadILOperand(il, xedd, addr, 1, 1))); + il.AddInstruction(WriteILOperand(il, xedd, addr, 1, 1, il.Register(opOneLen, LLIL_TEMP(0)))); + break; + + case XED_ICLASS_CMPXCHG: + case XED_ICLASS_CMPXCHG_LOCK: + { + LowLevelILLabel trueLabel, falseLabel, doneLabel; + size_t cmpGranularity = xed_decoded_inst_operand_element_size_bits(xedd, 0) / 8; + xed_reg_enum_t cmpReg = xed_decoded_inst_get_reg(xedd, opTre_name); + + il.AddInstruction( + il.If( + il.CompareEqual( + cmpGranularity, + il.Register(cmpGranularity, cmpReg), + ReadILOperand(il, xedd, addr, 0, 0) + ), trueLabel, falseLabel + ) + ); + + il.MarkLabel(trueLabel); + + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + ReadILOperand(il, xedd, addr, 1, 1) + ) + ); + il.AddInstruction(il.SetFlag(IL_FLAG_Z, il.Const(1, 1))); + + il.AddInstruction(il.Goto(doneLabel)); + + il.MarkLabel(falseLabel); + + il.AddInstruction( + il.SetRegister( + cmpGranularity, cmpReg, + ReadILOperand(il, xedd, addr, 0, 0) + ) + ); + il.AddInstruction(il.SetFlag(IL_FLAG_Z, il.Const(1, 0))); + + il.MarkLabel(doneLabel); + + break; + } + + case XED_ICLASS_CMPXCHG8B: + case XED_ICLASS_CMPXCHG8B_LOCK: + case XED_ICLASS_CMPXCHG16B: + case XED_ICLASS_CMPXCHG16B_LOCK: + { + // assembly: cmpxchg8b qword [rdi] + // $ ./xed-ex1 0fc70f + // Attempting to decode: 0f c7 0f + // iclass CMPXCHG8B category SEMAPHORE ISA-extension BASE ISA-set PENTIUMREAL + // instruction-length 3 + // operand-width 32 + // Operands + // # TYPE DETAILS VIS RW OC2 BITS BYTES NELEM ELEMSZ ELEMTYPE REGCLASS + // # ==== ======= === == === ==== ===== ===== ====== ======== ======== + // 0 MEM0 (see below) EXPLICIT RCW Q 64 8 1 64 INT INVALID + // 1 REG0 REG0=EDX SUPPRESSED RCW D 32 4 1 32 INT GPR + // 2 REG1 REG1=EAX SUPPRESSED RCW D 32 4 1 32 INT GPR + // 3 REG2 REG2=ECX SUPPRESSED R D 32 4 1 32 INT GPR + // 4 REG3 REG3=EBX SUPPRESSED R D 32 4 1 32 INT GPR + // 5 REG4 REG4=EFLAGS SUPPRESSED W Y 32 4 1 32 INT FLAGS + // Memory Operands + // 0 read written SEG= DS BASE= EDI/GPR ASZ0=32 + // MemopBytes = 8 + + LowLevelILLabel trueLabel, falseLabel, doneLabel; + size_t cmpGranularity = xed_decoded_inst_operand_element_size_bits(xedd, 1) / 8 * 2; + + xed_reg_enum_t cmpRegHigh = xed_decoded_inst_get_reg(xedd, opTwo_name); + xed_reg_enum_t cmpRegLow = xed_decoded_inst_get_reg(xedd, opTre_name); + + const xed_operand_t* const opFour = xed_inst_operand(xi, 3); + const xed_operand_enum_t opFour_name = xed_operand_name(opFour); + xed_reg_enum_t resultRegHigh = xed_decoded_inst_get_reg(xedd, opFour_name); + + const xed_operand_t* const opFive = xed_inst_operand(xi, 4); + const xed_operand_enum_t opFive_name = xed_operand_name(opFive); + xed_reg_enum_t resultRegLow = xed_decoded_inst_get_reg(xedd, opFive_name); + + il.AddInstruction( + il.If( + il.CompareEqual( + cmpGranularity, + il.RegisterSplit(cmpGranularity / 2, cmpRegHigh, cmpRegLow), + ReadILOperand(il, xedd, addr, 0, 0) + ), + trueLabel, falseLabel + ) + ); + + il.MarkLabel(trueLabel); + + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.RegisterSplit(cmpGranularity / 2, resultRegHigh, resultRegLow) + ) + ); + il.AddInstruction(il.SetFlag(IL_FLAG_Z, il.Const(1, 1))); + + il.AddInstruction(il.Goto(doneLabel)); + + il.MarkLabel(falseLabel); + + il.AddInstruction( + il.SetRegisterSplit(cmpGranularity / 2, cmpRegHigh, cmpRegLow, + ReadILOperand(il, xedd, addr, 0, 0) + ) + ); + il.AddInstruction(il.SetFlag(IL_FLAG_Z, il.Const(1, 0))); + + il.MarkLabel(doneLabel); + + break; + } + case XED_ICLASS_XORPS: + case XED_ICLASS_PXOR: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Xor(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + 0))); + break; + case XED_ICLASS_XOR_LOCK: // TODO: Handle lock prefix + case XED_ICLASS_XOR: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Xor(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_ALL))); + break; + case XED_ICLASS_VPXOR: + if (xed_classify_avx512(xedd)) + { + LiftAsIntrinsic(); + break; + } + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Xor(opOneLen, + ReadILOperand(il, xedd, addr, 1, 1), + ReadILOperand(il, xedd, addr, 2, 2), + 0))); + break; + + case XED_ICLASS_XADD: + case XED_ICLASS_XADD_LOCK: + il.AddInstruction( + il.SetRegister(opOneLen, LLIL_TEMP(0), + il.Add(opOneLen, + ReadILOperand(il, xedd, addr, 0, 0), + ReadILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_ALL))); + il.AddInstruction( + WriteILOperand(il, xedd, addr, 1, 1, ReadILOperand(il, xedd, addr, 0, 0))); + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, il.Register(opOneLen, LLIL_TEMP(0)))); + break; + case XED_ICLASS_JMP_FAR: + case XED_ICLASS_RET_FAR: + case XED_ICLASS_IRET: + case XED_ICLASS_IRETD: + case XED_ICLASS_IRETQ: + il.AddInstruction(il.Undefined()); + return false; + + case XED_ICLASS_UD2: + il.AddInstruction(il.Trap(TRAP_ILL)); + return false; + + case XED_ICLASS_SYSCALL: + case XED_ICLASS_SYSENTER: + il.AddInstruction(il.SystemCall()); + break; + + case XED_ICLASS_SYSEXIT: + case XED_ICLASS_SYSRET: + case XED_ICLASS_HLT: + il.AddInstruction(il.Trap(TRAP_GPF)); + return false; + + case XED_ICLASS_FLD: + il.AddInstruction( + il.RegisterStackPush(10, + REG_STACK_X87, + ReadFloatILOperand(il, xedd, addr, 1, 1))); + break; + + case XED_ICLASS_FILD: + il.AddInstruction( + il.RegisterStackPush(10, + REG_STACK_X87, + il.IntToFloat(10, + ReadILOperand(il, xedd, addr, 1, 1)), + IL_FLAGWRITE_X87C1Z)); + break; + + case XED_ICLASS_FLDZ: + il.AddInstruction( + il.RegisterStackPush(10, + REG_STACK_X87, + il.IntToFloat(10, il.Const(4, 0)), + IL_FLAGWRITE_X87C1Z)); + break; + + case XED_ICLASS_FLD1: + il.AddInstruction( + il.RegisterStackPush(10, + REG_STACK_X87, + il.IntToFloat(10, il.Const(4, 1)), + IL_FLAGWRITE_X87C1Z)); + break; + + case XED_ICLASS_FLDPI: + // Load 66-bit precision constant with two 33-bit components + il.AddInstruction( + il.RegisterStackPush(10, + REG_STACK_X87, + il.FloatAdd(10, + il.FloatConvert(10, il.FloatConstRaw(8, 0x400921fb54400000LL)), + il.FloatConvert(10, il.FloatConstRaw(8, 0x3de0b4611a600000LL))), + IL_FLAGWRITE_X87C1Z)); + break; + + case XED_ICLASS_FLDL2T: + // Load 66-bit precision constant with two 33-bit components + il.AddInstruction( + il.RegisterStackPush(10, + REG_STACK_X87, + il.FloatAdd(10, + il.FloatConvert(10, il.FloatConstRaw(8, 0x400a934f09700000LL)), + il.FloatConvert(10, il.FloatConstRaw(8, 0x3df346e2bf900000LL))), + IL_FLAGWRITE_X87C1Z)); + break; + + case XED_ICLASS_FLDL2E: + // Load 66-bit precision constant with two 33-bit components + il.AddInstruction( + il.RegisterStackPush(10, + REG_STACK_X87, + il.FloatAdd(10, + il.FloatConvert(10, il.FloatConstRaw(8, 0x3ff7154765200000LL)), + il.FloatConvert(10, il.FloatConstRaw(8, 0x3de705fc2ee00000LL))), + IL_FLAGWRITE_X87C1Z)); + break; + + case XED_ICLASS_FLDLG2: + // Load 66-bit precision constant with two 33-bit components + il.AddInstruction( + il.RegisterStackPush(10, + REG_STACK_X87, + il.FloatAdd(10, + il.FloatConvert(10, il.FloatConstRaw(8, 0x3fd3441350900000LL)), + il.FloatConvert(10, il.FloatConstRaw(8, 0x3dcef3fde6200000LL))), + IL_FLAGWRITE_X87C1Z)); + break; + + case XED_ICLASS_FLDLN2: + // Load 66-bit precision constant with two 33-bit components + il.AddInstruction( + il.RegisterStackPush(10, + REG_STACK_X87, + il.FloatAdd(10, + il.FloatConvert(10, il.FloatConstRaw(8, 0x3fe62e42fef00000LL)), + il.FloatConvert(10, il.FloatConstRaw(8, 0x3dd473de6af00000LL))), + IL_FLAGWRITE_X87C1Z)); + break; + + case XED_ICLASS_FST: + if (opOneLen != 10) + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatConvert(opOneLen, + il.Register(10, XED_REG_ST0), + IL_FLAGWRITE_X87RND))); + } + else + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Register(10, XED_REG_ST0))); + } + break; + + case XED_ICLASS_FSTP: + if (opOneLen != 10) + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatConvert(opOneLen, + il.RegisterStackPop(10, REG_STACK_X87), + IL_FLAGWRITE_X87RND))); + } + else + { + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.RegisterStackPop(10, REG_STACK_X87, IL_FLAGWRITE_X87C1Z))); + } + break; + + case XED_ICLASS_FIST: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatToInt(opOneLen, + il.Register(10, XED_REG_ST0), + IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FISTP: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatToInt(opOneLen, + il.RegisterStackPop(10, REG_STACK_X87), + IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FISTTP: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatToInt(opOneLen, + il.FloatTrunc(10, + il.RegisterStackPop(10, REG_STACK_X87), + IL_FLAGWRITE_X87RND)))); + break; + + case XED_ICLASS_FADD: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatAdd(10, + ReadFloatILOperand(il, xedd, addr, 0, 0), + ReadFloatILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FADDP: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatAdd(10, + ReadFloatILOperand(il, xedd, addr, 0, 0), + ReadFloatILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_X87RND))); + il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0)); + il.AddInstruction( + il.SetRegister(2, + REG_X87_TOP, + il.Add(2, + il.Register(2, REG_X87_TOP), + il.Const(2, 1)))); + break; + + case XED_ICLASS_FIADD: + il.AddInstruction( + il.SetRegister(10, XED_REG_ST0, + il.FloatAdd(10, + il.Register(10, XED_REG_ST0), + il.IntToFloat(10, + ReadILOperand(il, xedd, addr, 1, 1)), + IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FSUB: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatSub(10, + ReadFloatILOperand(il, xedd, addr, 0, 0), + ReadFloatILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FSUBP: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatSub(10, + ReadFloatILOperand(il, xedd, addr, 0, 0), + ReadFloatILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_X87RND))); + il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0)); + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1)))); + break; + + case XED_ICLASS_FISUB: + il.AddInstruction(il.SetRegister(10, XED_REG_ST0, + il.FloatSub(10, + il.Register(10, XED_REG_ST0), + il.IntToFloat(10, ReadILOperand(il, xedd, addr, 1, 1)), + IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FSUBR: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatSub(10, + ReadFloatILOperand(il, xedd, addr, 1, 1), + ReadFloatILOperand(il, xedd, addr, 0, 0), + IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FSUBRP: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatSub(10, + ReadFloatILOperand(il, xedd, addr, 1, 1), + ReadFloatILOperand(il, xedd, addr, 0, 0), + IL_FLAGWRITE_X87RND))); + il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0)); + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1)))); + break; + + case XED_ICLASS_FISUBR: + il.AddInstruction( + il.SetRegister(10, + XED_REG_ST0, + il.FloatSub(10, + il.IntToFloat(10, + ReadILOperand(il, xedd, addr, 1, 1)), + il.Register(10, XED_REG_ST0), + IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FMUL: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatMult(10, + ReadFloatILOperand(il, xedd, addr, 0, 0), + ReadFloatILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FMULP: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatMult(10, + ReadFloatILOperand(il, xedd, addr, 0, 0), + ReadFloatILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_X87RND))); + il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0)); + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1)))); + break; + + case XED_ICLASS_FIMUL: + il.AddInstruction( + il.SetRegister(10, XED_REG_ST0, + il.FloatMult(10, + il.Register(10, XED_REG_ST0), + il.IntToFloat(10, + ReadILOperand(il, xedd, addr, 1, 1)), + IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FDIV: + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, + il.FloatDiv(10, + ReadFloatILOperand(il, xedd, addr, 0, 0), + ReadFloatILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FDIVP: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatDiv(10, + ReadFloatILOperand(il, xedd, addr, 0, 0), + ReadFloatILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_X87RND))); + il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0)); + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1)))); + break; + + case XED_ICLASS_FIDIV: + il.AddInstruction( + il.SetRegister(10, XED_REG_ST0, + il.FloatDiv(10, + il.Register(10, XED_REG_ST0), + il.IntToFloat(10, + ReadILOperand(il, xedd, addr, 1, 1)), + IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FDIVR: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatDiv(10, + ReadFloatILOperand(il, xedd, addr, 1, 1), + ReadFloatILOperand(il, xedd, addr, 0, 0), + IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FDIVRP: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.FloatDiv(10, + ReadFloatILOperand(il, xedd, addr, 1, 1), + il.Register(10, XED_REG_ST0)))); + il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0)); + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1)))); + break; + + case XED_ICLASS_FIDIVR: + il.AddInstruction( + il.SetRegister(10, XED_REG_ST0, + il.FloatDiv(10, + il.IntToFloat(10, + ReadILOperand(il, xedd, addr, 1, 1)), + il.Register(10, XED_REG_ST0), + IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FABS: + il.AddInstruction(il.SetRegister(10, XED_REG_ST0, il.FloatAbs(10, il.Register(10, XED_REG_ST0), IL_FLAGWRITE_X87C1Z))); + break; + + case XED_ICLASS_FCHS: + il.AddInstruction(il.SetRegister(10, XED_REG_ST0, il.FloatNeg(10, il.Register(10, XED_REG_ST0), IL_FLAGWRITE_X87C1Z))); + break; + + case XED_ICLASS_FDECSTP: + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Sub(2, il.Register(2, REG_X87_TOP), il.Const(2, 1), + IL_FLAGWRITE_X87C1Z))); + break; + + case XED_ICLASS_FINCSTP: + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1), + IL_FLAGWRITE_X87C1Z))); + break; + + case XED_ICLASS_FFREE: + il.AddInstruction(il.RegisterStackFreeReg(regOne)); + break; + + case XED_ICLASS_EMMS: + for (uint32_t i = 0; i < 8; i++) + il.AddInstruction(il.RegisterStackFreeReg(REG_X87_r(i))); + break; + + case XED_ICLASS_FNINIT: + for (uint32_t i = 0; i < 8; i++) + il.AddInstruction(il.RegisterStackFreeReg(REG_X87_r(i))); + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Const(2, 0))); + break; + + case XED_ICLASS_FSQRT: + il.AddInstruction(il.SetRegister(10, XED_REG_ST0, il.FloatSqrt(10, il.Register(10, XED_REG_ST0), IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FXCH: + il.AddInstruction(il.SetRegister(10, LLIL_TEMP(0), ReadFloatILOperand(il, xedd, addr, 0, 0), IL_FLAGWRITE_X87C1Z)); + il.AddInstruction(WriteILOperand(il, xedd, addr, 0, 0, ReadFloatILOperand(il, xedd, addr, 1, 1))); + il.AddInstruction(WriteILOperand(il, xedd, addr, 1, 1, il.Register(10, LLIL_TEMP(0)))); + break; + + case XED_ICLASS_VUCOMISS: + case XED_ICLASS_UCOMISS: + case XED_ICLASS_COMISS: + il.AddInstruction( + il.FloatSub(4, + ReadFloatILOperand(il, xedd, addr, 0, 0, 4), + ReadFloatILOperand(il, xedd, addr, 1, 1, 4), + IL_FLAGWRITE_VCOMI)); + break; + + case XED_ICLASS_VUCOMISD: + case XED_ICLASS_UCOMISD: + case XED_ICLASS_COMISD: + il.AddInstruction( + il.FloatSub(8, + ReadFloatILOperand(il, xedd, addr, 0, 0, 8), + ReadFloatILOperand(il, xedd, addr, 1, 1, 8), + IL_FLAGWRITE_VCOMI)); + break; + + case XED_ICLASS_FCOMI: + case XED_ICLASS_FUCOMI: + il.AddInstruction( + il.FloatSub(10, + ReadFloatILOperand(il, xedd, addr, 0, 0), + ReadFloatILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_X87COMI)); + break; + + case XED_ICLASS_FCOMIP: + case XED_ICLASS_FUCOMIP: + il.AddInstruction( + il.FloatSub(10, + ReadFloatILOperand(il, xedd, addr, 0, 0), + ReadFloatILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_X87COMI)); + il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0)); + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1)))); + break; + + case XED_ICLASS_FCOM: + case XED_ICLASS_FUCOM: + il.AddInstruction( + il.FloatSub(10, + il.Register(10, XED_REG_ST0), + ReadFloatILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_X87COM)); + break; + + case XED_ICLASS_FICOM: + il.AddInstruction( + il.FloatSub(10, + il.Register(10, XED_REG_ST0), + il.IntToFloat(10, + ReadILOperand(il, xedd, addr, 1, 1)), + IL_FLAGWRITE_X87COM)); + break; + + case XED_ICLASS_FCOMP: + case XED_ICLASS_FUCOMP: + il.AddInstruction( + il.FloatSub(10, + il.Register(10, XED_REG_ST0), + ReadFloatILOperand(il, xedd, addr, 1, 1), + IL_FLAGWRITE_X87COM)); + il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0)); + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1)))); + break; + + case XED_ICLASS_FICOMP: + il.AddInstruction( + il.FloatSub(10, + il.Register(10, XED_REG_ST0), + il.IntToFloat(10, + ReadILOperand(il, xedd, addr, 1, 1)), + IL_FLAGWRITE_X87COM)); + il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0)); + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1)))); + break; + + case XED_ICLASS_FCOMPP: + case XED_ICLASS_FUCOMPP: + il.AddInstruction(il.FloatSub(10, il.Register(10, XED_REG_ST0), il.Register(10, XED_REG_ST1), + IL_FLAGWRITE_X87COM)); + il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0)); + il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST1)); + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 2)))); + break; + + case XED_ICLASS_FTST: + il.AddInstruction(il.FloatSub(10, il.Register(10, XED_REG_ST0), + il.IntToFloat(10, il.Const(4, 0)), IL_FLAGWRITE_X87COM)); + break; + + case XED_ICLASS_FNSTSW: + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Or(2, + il.FlagBit(2, IL_FLAG_C0, 8), + il.Or(2, + il.FlagBit(2, IL_FLAG_C1, 9), + il.Or(2, + il.FlagBit(2, IL_FLAG_C2, 10), + il.Or(2, + il.FlagBit(2, IL_FLAG_C3, 14), + il.ShiftLeft(2, + il.And(2, + il.Register(2, REG_X87_TOP), + il.Const(2, 7)), + il.Const(2, 11)))))))); + break; + + case XED_ICLASS_F2XM1: + il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0) }, + INTRINSIC_F2XM1, vector<ExprId> { il.Register(10, XED_REG_ST0) }, IL_FLAGWRITE_X87RND)); + break; + + case XED_ICLASS_FBLD: + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Sub(2, il.Register(2, REG_X87_TOP), il.Const(2, 1)))); + il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0) }, + INTRINSIC_FBLD, vector<ExprId> { ReadILOperand(il, xedd, addr, 1, 1) }, IL_FLAGWRITE_X87C1Z)); + break; + + case XED_ICLASS_FBSTP: + il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(LLIL_TEMP(0)) }, + INTRINSIC_FBST, vector<ExprId> { il.Register(10, XED_REG_ST0) }, IL_FLAGWRITE_X87RND)); + il.AddInstruction( + WriteILOperand(il, xedd, addr, 0, 0, + il.Register(10, LLIL_TEMP(0)))); + il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0)); + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1)))); + break; + + case XED_ICLASS_FSIN: + il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0), + RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FSIN, vector<ExprId> { il.Register(10, XED_REG_ST0) }, + IL_FLAGWRITE_X87RND)); + break; + + case XED_ICLASS_FCOS: + il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0), + RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FCOS, vector<ExprId> { il.Register(10, XED_REG_ST0) }, + IL_FLAGWRITE_X87RND)); + break; + + case XED_ICLASS_FSINCOS: + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Sub(2, il.Register(2, REG_X87_TOP), il.Const(2, 1)))); + il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1), + RegisterOrFlag::Register(XED_REG_ST0), RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FSINCOS, + vector<ExprId> { il.Register(10, XED_REG_ST1) }, IL_FLAGWRITE_X87RND)); + break; + + case XED_ICLASS_FPATAN: + il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1) }, + INTRINSIC_FPATAN, vector<ExprId> { il.Register(10, XED_REG_ST0), il.Register(10, XED_REG_ST1) }, IL_FLAGWRITE_X87RND)); + il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0)); + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1)))); + break; + + case XED_ICLASS_FPREM: + il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0), + RegisterOrFlag::Flag(IL_FLAG_C2), RegisterOrFlag::Register(LLIL_TEMP(0)) }, INTRINSIC_FPREM, + vector<ExprId> { il.Register(10, XED_REG_ST0), il.Register(10, XED_REG_ST1) })); + il.AddInstruction(il.If(il.Flag(IL_FLAG_C2), doneLabel, falseLabel)); + il.MarkLabel(falseLabel); + il.AddInstruction(il.SetFlag(IL_FLAG_C0, il.CompareNotEqual(1, + il.And(1, il.Register(1, LLIL_TEMP(0)), il.Const(1, 4)), il.Const(1, 0)))); + il.AddInstruction(il.SetFlag(IL_FLAG_C1, il.CompareNotEqual(1, + il.And(1, il.Register(1, LLIL_TEMP(0)), il.Const(1, 1)), il.Const(1, 0)))); + il.AddInstruction(il.SetFlag(IL_FLAG_C3, il.CompareNotEqual(1, + il.And(1, il.Register(1, LLIL_TEMP(0)), il.Const(1, 2)), il.Const(1, 0)))); + il.AddInstruction(il.Goto(doneLabel)); + il.MarkLabel(doneLabel); + break; + + case XED_ICLASS_FPREM1: + il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0), + RegisterOrFlag::Flag(IL_FLAG_C2), RegisterOrFlag::Register(LLIL_TEMP(0)) }, INTRINSIC_FPREM1, + vector<ExprId> { il.Register(10, XED_REG_ST0), il.Register(10, XED_REG_ST1) })); + il.AddInstruction(il.If(il.Flag(IL_FLAG_C2), doneLabel, falseLabel)); + il.MarkLabel(falseLabel); + il.AddInstruction(il.SetFlag(IL_FLAG_C0, il.CompareNotEqual(1, + il.And(1, il.Register(1, LLIL_TEMP(0)), il.Const(1, 4)), il.Const(1, 0)))); + il.AddInstruction(il.SetFlag(IL_FLAG_C1, il.CompareNotEqual(1, + il.And(1, il.Register(1, LLIL_TEMP(0)), il.Const(1, 1)), il.Const(1, 0)))); + il.AddInstruction(il.SetFlag(IL_FLAG_C3, il.CompareNotEqual(1, + il.And(1, il.Register(1, LLIL_TEMP(0)), il.Const(1, 2)), il.Const(1, 0)))); + il.AddInstruction(il.Goto(doneLabel)); + il.MarkLabel(doneLabel); + break; + + case XED_ICLASS_FPTAN: + il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0), + RegisterOrFlag::Flag(IL_FLAG_C2) }, INTRINSIC_FPTAN, vector<ExprId> { il.Register(10, XED_REG_ST0) }, + IL_FLAGWRITE_X87RND)); + il.AddInstruction(il.If(il.Flag(IL_FLAG_C2), doneLabel, falseLabel)); + il.MarkLabel(falseLabel); + il.AddInstruction(il.RegisterStackPush(10, REG_STACK_X87, il.IntToFloat(10, il.Const(4, 1)))); + il.AddInstruction(il.Goto(doneLabel)); + il.MarkLabel(doneLabel); + break; + + case XED_ICLASS_FRNDINT: + il.AddInstruction(il.SetRegister(10, XED_REG_ST0, il.RoundToInt(10, il.Register(10, XED_REG_ST0), IL_FLAGWRITE_X87RND))); + break; + + case XED_ICLASS_FSCALE: + il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0) }, + INTRINSIC_FSCALE, vector<ExprId> { il.Register(10, XED_REG_ST0), il.Register(10, XED_REG_ST1) }, + IL_FLAGWRITE_X87RND)); + break; + + case XED_ICLASS_FXAM: + il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Flag(IL_FLAG_C0), + RegisterOrFlag::Flag(IL_FLAG_C1), RegisterOrFlag::Flag(IL_FLAG_C2), RegisterOrFlag::Flag(IL_FLAG_C3) }, + INTRINSIC_FXAM, vector<ExprId> { il.Register(10, XED_REG_ST0) })); + break; + + case XED_ICLASS_FXTRACT: + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Sub(2, il.Register(2, REG_X87_TOP), il.Const(2, 1)))); + il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST0), + RegisterOrFlag::Register(XED_REG_ST1) }, INTRINSIC_FXTRACT, vector<ExprId> { il.Register(10, XED_REG_ST1) }, + IL_FLAGWRITE_X87C1Z)); + break; + + case XED_ICLASS_FYL2X: + il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1) }, + INTRINSIC_FYL2X, vector<ExprId> { il.Register(10, XED_REG_ST0), il.Register(10, XED_REG_ST1) }, + IL_FLAGWRITE_X87RND)); + il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0)); + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1)))); + break; + + case XED_ICLASS_FYL2XP1: + il.AddInstruction(il.Intrinsic(vector<RegisterOrFlag> { RegisterOrFlag::Register(XED_REG_ST1) }, + INTRINSIC_FYL2XP1, vector<ExprId> { il.Register(10, XED_REG_ST0), il.Register(10, XED_REG_ST1) }, + IL_FLAGWRITE_X87RND)); + il.AddInstruction(il.RegisterStackFreeReg(XED_REG_ST0)); + il.AddInstruction(il.SetRegister(2, REG_X87_TOP, il.Add(2, il.Register(2, REG_X87_TOP), il.Const(2, 1)))); + break; + + case XED_ICLASS_TZCNT: + { + if (opOneLen == 8) + il.AddInstruction( + il.Intrinsic( + vector<RegisterOrFlag> { RegisterOrFlag::Register(regOne) }, + INTRINSIC_XED_IFORM_TZCNT_GPR64_GPRMEM64, + vector<ExprId> { ReadILOperand(il, xedd, addr, 1, 1) } )); + else if (opOneLen == 4) + il.AddInstruction( + il.Intrinsic( + vector<RegisterOrFlag> { RegisterOrFlag::Register(regOne) }, + INTRINSIC_XED_IFORM_TZCNT_GPR32_GPRMEM32, + vector<ExprId> { ReadILOperand(il, xedd, addr, 1, 1) } )); + else + il.AddInstruction( + il.Intrinsic( + vector<RegisterOrFlag> { RegisterOrFlag::Register(regOne) }, + INTRINSIC_XED_IFORM_TZCNT_GPR16_GPRMEM16, + vector<ExprId> { ReadILOperand(il, xedd, addr, 1, 1) } )); + + break; + } + + case XED_ICLASS_LZCNT: + { + if (opOneLen == 8) + il.AddInstruction( + il.Intrinsic( + vector<RegisterOrFlag> { RegisterOrFlag::Register(regOne) }, + INTRINSIC_XED_IFORM_LZCNT_GPR64_GPRMEM64, + vector<ExprId> { ReadILOperand(il, xedd, addr, 1, 1) } + ) + ); + else if (opOneLen == 4) + il.AddInstruction( + il.Intrinsic( + vector<RegisterOrFlag> { RegisterOrFlag::Register(regOne) }, + INTRINSIC_XED_IFORM_LZCNT_GPR32_GPRMEM32, + vector<ExprId> { ReadILOperand(il, xedd, addr, 1, 1) } )); + else + il.AddInstruction( + il.Intrinsic( + vector<RegisterOrFlag> { RegisterOrFlag::Register(regOne) }, + INTRINSIC_XED_IFORM_LZCNT_GPR16_GPRMEM16, + vector<ExprId> { ReadILOperand(il, xedd, addr, 1, 1) } )); + + break; + } + + case XED_ICLASS_POPCNT: + { + if (opOneLen == 8) + il.AddInstruction( + il.Intrinsic( + vector<RegisterOrFlag> { RegisterOrFlag::Register(regOne) }, + INTRINSIC_XED_IFORM_POPCNT_GPR64_GPRMEM64, + vector<ExprId> { ReadILOperand(il, xedd, addr, 1, 1) } + ) + ); + else if (opOneLen == 4) + il.AddInstruction( + il.Intrinsic( + vector<RegisterOrFlag> { RegisterOrFlag::Register(regOne) }, + INTRINSIC_XED_IFORM_POPCNT_GPR32_GPRMEM32, + vector<ExprId> { ReadILOperand(il, xedd, addr, 1, 1) } )); + else + il.AddInstruction( + il.Intrinsic( + vector<RegisterOrFlag> { RegisterOrFlag::Register(regOne) }, + INTRINSIC_XED_IFORM_POPCNT_GPR16_GPRMEM16, + vector<ExprId> { ReadILOperand(il, xedd, addr, 1, 1) } )); + + break; + } + + default: + LiftAsIntrinsic(); + break; + } + + return true; +} diff --git a/arch/x86/il.h b/arch/x86/il.h new file mode 100644 index 00000000..2082b660 --- /dev/null +++ b/arch/x86/il.h @@ -0,0 +1,6481 @@ +#pragma once + +#include <string> +#include "binaryninjaapi.h" +extern "C" { + #include "xed-interface.h" +} + + +// The difference between DF_INTEL and DF_BN_INTEL is +// DF_INTEL is more verbose (states size more often, and some more subtle things) +// DF_INTEL uses some different opcodes (jz and jnz vs je and jne) +enum DISASSEMBLY_FLAVOR_ENUM +{ + DF_INTEL, + DF_BN_INTEL, + DF_ATT, + DF_XED +}; + +struct DISASSEMBLY_OPTIONS +{ + DISASSEMBLY_FLAVOR_ENUM df; + + bool lowerCase; + std::string separator; + + DISASSEMBLY_OPTIONS(DISASSEMBLY_FLAVOR_ENUM df = DF_BN_INTEL, bool lowerCase = true, std::string separator = ", ") + : df(df), lowerCase(lowerCase), separator(separator) { }; +}; + +#define IL_FLAG_C 0 +#define IL_FLAG_P 2 +#define IL_FLAG_A 4 +#define IL_FLAG_Z 6 +#define IL_FLAG_S 7 +#define IL_FLAG_D 10 +#define IL_FLAG_O 11 +#define IL_FLAG_C0 32 +#define IL_FLAG_C1 33 +#define IL_FLAG_C2 34 +#define IL_FLAG_C3 35 + +#define IL_FLAGWRITE_ALL 1 +#define IL_FLAGWRITE_NOCARRY 2 +#define IL_FLAGWRITE_CO 3 +#define IL_FLAGWRITE_X87COM 4 +#define IL_FLAGWRITE_X87COMI 5 +#define IL_FLAGWRITE_X87C1Z 6 +#define IL_FLAGWRITE_X87RND 7 +#define IL_FLAGWRITE_VCOMI 8 + +#define IL_FLAG_CLASS_INT 0 // Default +#define IL_FLAG_CLASS_X87COM 1 +#define IL_FLAG_CLASS_X87COMI 2 +#define IL_FLAG_CLASS_VCOMI 3 + +#define IL_FLAG_GROUP_E 0 +#define IL_FLAG_GROUP_NE 1 +#define IL_FLAG_GROUP_LT 2 +#define IL_FLAG_GROUP_LE 3 +#define IL_FLAG_GROUP_GE 4 +#define IL_FLAG_GROUP_GT 5 +#define IL_FLAG_GROUP_PE 6 +#define IL_FLAG_GROUP_PO 7 + +#define TRAP_DIV 0 +#define TRAP_ICEBP 1 +#define TRAP_NMI 2 +#define TRAP_BP 3 +#define TRAP_OVERFLOW 4 +#define TRAP_BOUND 5 +#define TRAP_ILL 6 +#define TRAP_NOT_AVAIL 7 +#define TRAP_DOUBLE 8 +#define TRAP_TSS 10 +#define TRAP_NO_SEG 11 +#define TRAP_STACK 12 +#define TRAP_GPF 13 +#define TRAP_PAGE 14 +#define TRAP_FPU 16 +#define TRAP_ALIGN 17 +#define TRAP_MCE 18 +#define TRAP_SIMD 19 +// interrupts [20, 31] aren't mentioned in Intel SDM +// interrupts [32, 255] are user defined + +#define REG_STACK_X87 0x999 +#define REG_X87_r(n) (0x1000 + (n)) // The fake "real" (physical) register +#define REG_X87_TOP 0x1008 + +enum X86_INTRINSIC +{ + INTRINSIC_F2XM1, + INTRINSIC_FBLD, + INTRINSIC_FBST, + INTRINSIC_FSIN, + INTRINSIC_FCOS, + INTRINSIC_FSINCOS, + INTRINSIC_FPATAN, + INTRINSIC_FPREM, + INTRINSIC_FPREM1, + INTRINSIC_FPTAN, + INTRINSIC_FSCALE, + INTRINSIC_FXAM, + INTRINSIC_FXTRACT, + INTRINSIC_FYL2X, + INTRINSIC_FYL2XP1, + // below are for vector instrinsics + // copied from public/arch/x86/xedInc/xed-iform-enum.h + INTRINSIC_XED_IFORM_INVALID = 1000, + INTRINSIC_XED_IFORM_AAA, + INTRINSIC_XED_IFORM_AAD_IMMb, + INTRINSIC_XED_IFORM_AAM_IMMb, + INTRINSIC_XED_IFORM_AAS, + INTRINSIC_XED_IFORM_ADC_AL_IMMb, + INTRINSIC_XED_IFORM_ADC_GPR8_GPR8_10, + INTRINSIC_XED_IFORM_ADC_GPR8_GPR8_12, + INTRINSIC_XED_IFORM_ADC_GPR8_IMMb_80r2, + INTRINSIC_XED_IFORM_ADC_GPR8_IMMb_82r2, + INTRINSIC_XED_IFORM_ADC_GPR8_MEMb, + INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_11, + INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_13, + INTRINSIC_XED_IFORM_ADC_GPRv_IMMb, + INTRINSIC_XED_IFORM_ADC_GPRv_IMMz, + INTRINSIC_XED_IFORM_ADC_GPRv_MEMv, + INTRINSIC_XED_IFORM_ADC_MEMb_GPR8, + INTRINSIC_XED_IFORM_ADC_MEMb_IMMb_80r2, + INTRINSIC_XED_IFORM_ADC_MEMb_IMMb_82r2, + INTRINSIC_XED_IFORM_ADC_MEMv_GPRv, + INTRINSIC_XED_IFORM_ADC_MEMv_IMMb, + INTRINSIC_XED_IFORM_ADC_MEMv_IMMz, + INTRINSIC_XED_IFORM_ADC_OrAX_IMMz, + INTRINSIC_XED_IFORM_ADCX_GPR32d_GPR32d, + INTRINSIC_XED_IFORM_ADCX_GPR32d_MEMd, + INTRINSIC_XED_IFORM_ADCX_GPR64q_GPR64q, + INTRINSIC_XED_IFORM_ADCX_GPR64q_MEMq, + INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_GPR8, + INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2, + INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2, + INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_GPRv, + INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_IMMb, + INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_IMMz, + INTRINSIC_XED_IFORM_ADD_AL_IMMb, + INTRINSIC_XED_IFORM_ADD_GPR8_GPR8_00, + INTRINSIC_XED_IFORM_ADD_GPR8_GPR8_02, + INTRINSIC_XED_IFORM_ADD_GPR8_IMMb_80r0, + INTRINSIC_XED_IFORM_ADD_GPR8_IMMb_82r0, + INTRINSIC_XED_IFORM_ADD_GPR8_MEMb, + INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_01, + INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_03, + INTRINSIC_XED_IFORM_ADD_GPRv_IMMb, + INTRINSIC_XED_IFORM_ADD_GPRv_IMMz, + INTRINSIC_XED_IFORM_ADD_GPRv_MEMv, + INTRINSIC_XED_IFORM_ADD_MEMb_GPR8, + INTRINSIC_XED_IFORM_ADD_MEMb_IMMb_80r0, + INTRINSIC_XED_IFORM_ADD_MEMb_IMMb_82r0, + INTRINSIC_XED_IFORM_ADD_MEMv_GPRv, + INTRINSIC_XED_IFORM_ADD_MEMv_IMMb, + INTRINSIC_XED_IFORM_ADD_MEMv_IMMz, + INTRINSIC_XED_IFORM_ADD_OrAX_IMMz, + INTRINSIC_XED_IFORM_ADDPD_XMMpd_MEMpd, + INTRINSIC_XED_IFORM_ADDPD_XMMpd_XMMpd, + INTRINSIC_XED_IFORM_ADDPS_XMMps_MEMps, + INTRINSIC_XED_IFORM_ADDPS_XMMps_XMMps, + INTRINSIC_XED_IFORM_ADDSD_XMMsd_MEMsd, + INTRINSIC_XED_IFORM_ADDSD_XMMsd_XMMsd, + INTRINSIC_XED_IFORM_ADDSS_XMMss_MEMss, + INTRINSIC_XED_IFORM_ADDSS_XMMss_XMMss, + INTRINSIC_XED_IFORM_ADDSUBPD_XMMpd_MEMpd, + INTRINSIC_XED_IFORM_ADDSUBPD_XMMpd_XMMpd, + INTRINSIC_XED_IFORM_ADDSUBPS_XMMps_MEMps, + INTRINSIC_XED_IFORM_ADDSUBPS_XMMps_XMMps, + INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_GPR8, + INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0, + INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0, + INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_GPRv, + INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_IMMb, + INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_IMMz, + INTRINSIC_XED_IFORM_ADOX_GPR32d_GPR32d, + INTRINSIC_XED_IFORM_ADOX_GPR32d_MEMd, + INTRINSIC_XED_IFORM_ADOX_GPR64q_GPR64q, + INTRINSIC_XED_IFORM_ADOX_GPR64q_MEMq, + INTRINSIC_XED_IFORM_AESDEC_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_AESDEC_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_AESDECLAST_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_AESDECLAST_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_AESENC_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_AESENC_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_AESENCLAST_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_AESENCLAST_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_AESIMC_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_AESIMC_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_AND_AL_IMMb, + INTRINSIC_XED_IFORM_AND_GPR8_GPR8_20, + INTRINSIC_XED_IFORM_AND_GPR8_GPR8_22, + INTRINSIC_XED_IFORM_AND_GPR8_IMMb_80r4, + INTRINSIC_XED_IFORM_AND_GPR8_IMMb_82r4, + INTRINSIC_XED_IFORM_AND_GPR8_MEMb, + INTRINSIC_XED_IFORM_AND_GPRv_GPRv_21, + INTRINSIC_XED_IFORM_AND_GPRv_GPRv_23, + INTRINSIC_XED_IFORM_AND_GPRv_IMMb, + INTRINSIC_XED_IFORM_AND_GPRv_IMMz, + INTRINSIC_XED_IFORM_AND_GPRv_MEMv, + INTRINSIC_XED_IFORM_AND_MEMb_GPR8, + INTRINSIC_XED_IFORM_AND_MEMb_IMMb_80r4, + INTRINSIC_XED_IFORM_AND_MEMb_IMMb_82r4, + INTRINSIC_XED_IFORM_AND_MEMv_GPRv, + INTRINSIC_XED_IFORM_AND_MEMv_IMMb, + INTRINSIC_XED_IFORM_AND_MEMv_IMMz, + INTRINSIC_XED_IFORM_AND_OrAX_IMMz, + INTRINSIC_XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d, + INTRINSIC_XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq, + INTRINSIC_XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q, + INTRINSIC_XED_IFORM_ANDNPD_XMMxuq_MEMxuq, + INTRINSIC_XED_IFORM_ANDNPD_XMMxuq_XMMxuq, + INTRINSIC_XED_IFORM_ANDNPS_XMMxud_MEMxud, + INTRINSIC_XED_IFORM_ANDNPS_XMMxud_XMMxud, + INTRINSIC_XED_IFORM_ANDPD_XMMxuq_MEMxuq, + INTRINSIC_XED_IFORM_ANDPD_XMMxuq_XMMxuq, + INTRINSIC_XED_IFORM_ANDPS_XMMxud_MEMxud, + INTRINSIC_XED_IFORM_ANDPS_XMMxud_XMMxud, + INTRINSIC_XED_IFORM_AND_LOCK_MEMb_GPR8, + INTRINSIC_XED_IFORM_AND_LOCK_MEMb_IMMb_80r4, + INTRINSIC_XED_IFORM_AND_LOCK_MEMb_IMMb_82r4, + INTRINSIC_XED_IFORM_AND_LOCK_MEMv_GPRv, + INTRINSIC_XED_IFORM_AND_LOCK_MEMv_IMMb, + INTRINSIC_XED_IFORM_AND_LOCK_MEMv_IMMz, + INTRINSIC_XED_IFORM_ARPL_GPR16_GPR16, + INTRINSIC_XED_IFORM_ARPL_MEMw_GPR16, + INTRINSIC_XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d, + INTRINSIC_XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d, + INTRINSIC_XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q, + INTRINSIC_XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q, + INTRINSIC_XED_IFORM_BEXTR_XOP_GPR32d_GPR32d_IMMd, + INTRINSIC_XED_IFORM_BEXTR_XOP_GPR32d_MEMd_IMMd, + INTRINSIC_XED_IFORM_BEXTR_XOP_GPRyy_GPRyy_IMMd, + INTRINSIC_XED_IFORM_BEXTR_XOP_GPRyy_MEMy_IMMd, + INTRINSIC_XED_IFORM_BLCFILL_VGPR32d_GPR32d, + INTRINSIC_XED_IFORM_BLCFILL_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_BLCFILL_VGPRyy_GPRyy, + INTRINSIC_XED_IFORM_BLCFILL_VGPRyy_MEMy, + INTRINSIC_XED_IFORM_BLCI_VGPR32d_GPR32d, + INTRINSIC_XED_IFORM_BLCI_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_BLCI_VGPRyy_GPRyy, + INTRINSIC_XED_IFORM_BLCI_VGPRyy_MEMy, + INTRINSIC_XED_IFORM_BLCIC_VGPR32d_GPR32d, + INTRINSIC_XED_IFORM_BLCIC_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_BLCIC_VGPRyy_GPRyy, + INTRINSIC_XED_IFORM_BLCIC_VGPRyy_MEMy, + INTRINSIC_XED_IFORM_BLCMSK_VGPR32d_GPR32d, + INTRINSIC_XED_IFORM_BLCMSK_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_BLCMSK_VGPRyy_GPRyy, + INTRINSIC_XED_IFORM_BLCMSK_VGPRyy_MEMy, + INTRINSIC_XED_IFORM_BLCS_VGPR32d_GPR32d, + INTRINSIC_XED_IFORM_BLCS_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_BLCS_VGPRyy_GPRyy, + INTRINSIC_XED_IFORM_BLCS_VGPRyy_MEMy, + INTRINSIC_XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_BLENDVPD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_BLENDVPD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_BLENDVPS_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_BLENDVPS_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_BLSFILL_VGPR32d_GPR32d, + INTRINSIC_XED_IFORM_BLSFILL_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_BLSFILL_VGPRyy_GPRyy, + INTRINSIC_XED_IFORM_BLSFILL_VGPRyy_MEMy, + INTRINSIC_XED_IFORM_BLSI_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_BLSI_VGPR32d_VGPR32d, + INTRINSIC_XED_IFORM_BLSI_VGPR64q_MEMq, + INTRINSIC_XED_IFORM_BLSI_VGPR64q_VGPR64q, + INTRINSIC_XED_IFORM_BLSIC_VGPR32d_GPR32d, + INTRINSIC_XED_IFORM_BLSIC_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_BLSIC_VGPRyy_GPRyy, + INTRINSIC_XED_IFORM_BLSIC_VGPRyy_MEMy, + INTRINSIC_XED_IFORM_BLSMSK_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_BLSMSK_VGPR32d_VGPR32d, + INTRINSIC_XED_IFORM_BLSMSK_VGPR64q_MEMq, + INTRINSIC_XED_IFORM_BLSMSK_VGPR64q_VGPR64q, + INTRINSIC_XED_IFORM_BLSR_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_BLSR_VGPR32d_VGPR32d, + INTRINSIC_XED_IFORM_BLSR_VGPR64q_MEMq, + INTRINSIC_XED_IFORM_BLSR_VGPR64q_VGPR64q, + INTRINSIC_XED_IFORM_BNDCL_BND_AGEN, + INTRINSIC_XED_IFORM_BNDCL_BND_GPR32, + INTRINSIC_XED_IFORM_BNDCL_BND_GPR64, + INTRINSIC_XED_IFORM_BNDCN_BND_AGEN, + INTRINSIC_XED_IFORM_BNDCN_BND_GPR32, + INTRINSIC_XED_IFORM_BNDCN_BND_GPR64, + INTRINSIC_XED_IFORM_BNDCU_BND_AGEN, + INTRINSIC_XED_IFORM_BNDCU_BND_GPR32, + INTRINSIC_XED_IFORM_BNDCU_BND_GPR64, + INTRINSIC_XED_IFORM_BNDLDX_BND_MEMbnd32, + INTRINSIC_XED_IFORM_BNDLDX_BND_MEMbnd64, + INTRINSIC_XED_IFORM_BNDMK_BND_AGEN, + INTRINSIC_XED_IFORM_BNDMOV_BND_BND, + INTRINSIC_XED_IFORM_BNDMOV_BND_MEMdq, + INTRINSIC_XED_IFORM_BNDMOV_BND_MEMq, + INTRINSIC_XED_IFORM_BNDMOV_MEMdq_BND, + INTRINSIC_XED_IFORM_BNDMOV_MEMq_BND, + INTRINSIC_XED_IFORM_BNDSTX_MEMbnd32_BND, + INTRINSIC_XED_IFORM_BNDSTX_MEMbnd64_BND, + INTRINSIC_XED_IFORM_BOUND_GPRv_MEMa16, + INTRINSIC_XED_IFORM_BOUND_GPRv_MEMa32, + INTRINSIC_XED_IFORM_BSF_GPRv_GPRv, + INTRINSIC_XED_IFORM_BSF_GPRv_MEMv, + INTRINSIC_XED_IFORM_BSR_GPRv_GPRv, + INTRINSIC_XED_IFORM_BSR_GPRv_MEMv, + INTRINSIC_XED_IFORM_BSWAP_GPRv, + INTRINSIC_XED_IFORM_BT_GPRv_GPRv, + INTRINSIC_XED_IFORM_BT_GPRv_IMMb, + INTRINSIC_XED_IFORM_BT_MEMv_GPRv, + INTRINSIC_XED_IFORM_BT_MEMv_IMMb, + INTRINSIC_XED_IFORM_BTC_GPRv_GPRv, + INTRINSIC_XED_IFORM_BTC_GPRv_IMMb, + INTRINSIC_XED_IFORM_BTC_MEMv_GPRv, + INTRINSIC_XED_IFORM_BTC_MEMv_IMMb, + INTRINSIC_XED_IFORM_BTC_LOCK_MEMv_GPRv, + INTRINSIC_XED_IFORM_BTC_LOCK_MEMv_IMMb, + INTRINSIC_XED_IFORM_BTR_GPRv_GPRv, + INTRINSIC_XED_IFORM_BTR_GPRv_IMMb, + INTRINSIC_XED_IFORM_BTR_MEMv_GPRv, + INTRINSIC_XED_IFORM_BTR_MEMv_IMMb, + INTRINSIC_XED_IFORM_BTR_LOCK_MEMv_GPRv, + INTRINSIC_XED_IFORM_BTR_LOCK_MEMv_IMMb, + INTRINSIC_XED_IFORM_BTS_GPRv_GPRv, + INTRINSIC_XED_IFORM_BTS_GPRv_IMMb, + INTRINSIC_XED_IFORM_BTS_MEMv_GPRv, + INTRINSIC_XED_IFORM_BTS_MEMv_IMMb, + INTRINSIC_XED_IFORM_BTS_LOCK_MEMv_GPRv, + INTRINSIC_XED_IFORM_BTS_LOCK_MEMv_IMMb, + INTRINSIC_XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d, + INTRINSIC_XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d, + INTRINSIC_XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q, + INTRINSIC_XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q, + INTRINSIC_XED_IFORM_CALL_FAR_MEMp2, + INTRINSIC_XED_IFORM_CALL_FAR_PTRp_IMMw, + INTRINSIC_XED_IFORM_CALL_NEAR_GPRv, + INTRINSIC_XED_IFORM_CALL_NEAR_MEMv, + INTRINSIC_XED_IFORM_CALL_NEAR_RELBRd, + INTRINSIC_XED_IFORM_CALL_NEAR_RELBRz, + INTRINSIC_XED_IFORM_CBW, + INTRINSIC_XED_IFORM_CDQ, + INTRINSIC_XED_IFORM_CDQE, + INTRINSIC_XED_IFORM_CLAC, + INTRINSIC_XED_IFORM_CLC, + INTRINSIC_XED_IFORM_CLD, + INTRINSIC_XED_IFORM_CLDEMOTE_MEMu8, + INTRINSIC_XED_IFORM_CLFLUSH_MEMmprefetch, + INTRINSIC_XED_IFORM_CLFLUSHOPT_MEMmprefetch, + INTRINSIC_XED_IFORM_CLGI, + INTRINSIC_XED_IFORM_CLI, + INTRINSIC_XED_IFORM_CLRSSBSY_MEMu64, + INTRINSIC_XED_IFORM_CLTS, + INTRINSIC_XED_IFORM_CLWB_MEMmprefetch, + INTRINSIC_XED_IFORM_CLZERO, + INTRINSIC_XED_IFORM_CMC, + INTRINSIC_XED_IFORM_CMOVB_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVB_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMOVBE_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVBE_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMOVL_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVL_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMOVLE_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVLE_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMOVNB_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVNB_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMOVNBE_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVNBE_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMOVNL_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVNL_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMOVNLE_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVNLE_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMOVNO_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVNO_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMOVNP_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVNP_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMOVNS_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVNS_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMOVNZ_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVNZ_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMOVO_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVO_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMOVP_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVP_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMOVS_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVS_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMOVZ_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMOVZ_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMP_AL_IMMb, + INTRINSIC_XED_IFORM_CMP_GPR8_GPR8_38, + INTRINSIC_XED_IFORM_CMP_GPR8_GPR8_3A, + INTRINSIC_XED_IFORM_CMP_GPR8_IMMb_80r7, + INTRINSIC_XED_IFORM_CMP_GPR8_IMMb_82r7, + INTRINSIC_XED_IFORM_CMP_GPR8_MEMb, + INTRINSIC_XED_IFORM_CMP_GPRv_GPRv_39, + INTRINSIC_XED_IFORM_CMP_GPRv_GPRv_3B, + INTRINSIC_XED_IFORM_CMP_GPRv_IMMb, + INTRINSIC_XED_IFORM_CMP_GPRv_IMMz, + INTRINSIC_XED_IFORM_CMP_GPRv_MEMv, + INTRINSIC_XED_IFORM_CMP_MEMb_GPR8, + INTRINSIC_XED_IFORM_CMP_MEMb_IMMb_80r7, + INTRINSIC_XED_IFORM_CMP_MEMb_IMMb_82r7, + INTRINSIC_XED_IFORM_CMP_MEMv_GPRv, + INTRINSIC_XED_IFORM_CMP_MEMv_IMMb, + INTRINSIC_XED_IFORM_CMP_MEMv_IMMz, + INTRINSIC_XED_IFORM_CMP_OrAX_IMMz, + INTRINSIC_XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb, + INTRINSIC_XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb, + INTRINSIC_XED_IFORM_CMPPS_XMMps_MEMps_IMMb, + INTRINSIC_XED_IFORM_CMPPS_XMMps_XMMps_IMMb, + INTRINSIC_XED_IFORM_CMPSB, + INTRINSIC_XED_IFORM_CMPSD, + INTRINSIC_XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb, + INTRINSIC_XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb, + INTRINSIC_XED_IFORM_CMPSQ, + INTRINSIC_XED_IFORM_CMPSS_XMMss_MEMss_IMMb, + INTRINSIC_XED_IFORM_CMPSS_XMMss_XMMss_IMMb, + INTRINSIC_XED_IFORM_CMPSW, + INTRINSIC_XED_IFORM_CMPXCHG_GPR8_GPR8, + INTRINSIC_XED_IFORM_CMPXCHG_GPRv_GPRv, + INTRINSIC_XED_IFORM_CMPXCHG_MEMb_GPR8, + INTRINSIC_XED_IFORM_CMPXCHG_MEMv_GPRv, + INTRINSIC_XED_IFORM_CMPXCHG16B_MEMdq, + INTRINSIC_XED_IFORM_CMPXCHG16B_LOCK_MEMdq, + INTRINSIC_XED_IFORM_CMPXCHG8B_MEMq, + INTRINSIC_XED_IFORM_CMPXCHG8B_LOCK_MEMq, + INTRINSIC_XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8, + INTRINSIC_XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv, + INTRINSIC_XED_IFORM_COMISD_XMMsd_MEMsd, + INTRINSIC_XED_IFORM_COMISD_XMMsd_XMMsd, + INTRINSIC_XED_IFORM_COMISS_XMMss_MEMss, + INTRINSIC_XED_IFORM_COMISS_XMMss_XMMss, + INTRINSIC_XED_IFORM_CPUID, + INTRINSIC_XED_IFORM_CQO, + INTRINSIC_XED_IFORM_CRC32_GPRyy_GPR8b, + INTRINSIC_XED_IFORM_CRC32_GPRyy_GPRv, + INTRINSIC_XED_IFORM_CRC32_GPRyy_MEMb, + INTRINSIC_XED_IFORM_CRC32_GPRyy_MEMv, + INTRINSIC_XED_IFORM_CVTDQ2PD_XMMpd_MEMq, + INTRINSIC_XED_IFORM_CVTDQ2PD_XMMpd_XMMq, + INTRINSIC_XED_IFORM_CVTDQ2PS_XMMps_MEMdq, + INTRINSIC_XED_IFORM_CVTDQ2PS_XMMps_XMMdq, + INTRINSIC_XED_IFORM_CVTPD2DQ_XMMdq_MEMpd, + INTRINSIC_XED_IFORM_CVTPD2DQ_XMMdq_XMMpd, + INTRINSIC_XED_IFORM_CVTPD2PI_MMXq_MEMpd, + INTRINSIC_XED_IFORM_CVTPD2PI_MMXq_XMMpd, + INTRINSIC_XED_IFORM_CVTPD2PS_XMMps_MEMpd, + INTRINSIC_XED_IFORM_CVTPD2PS_XMMps_XMMpd, + INTRINSIC_XED_IFORM_CVTPI2PD_XMMpd_MEMq, + INTRINSIC_XED_IFORM_CVTPI2PD_XMMpd_MMXq, + INTRINSIC_XED_IFORM_CVTPI2PS_XMMq_MEMq, + INTRINSIC_XED_IFORM_CVTPI2PS_XMMq_MMXq, + INTRINSIC_XED_IFORM_CVTPS2DQ_XMMdq_MEMps, + INTRINSIC_XED_IFORM_CVTPS2DQ_XMMdq_XMMps, + INTRINSIC_XED_IFORM_CVTPS2PD_XMMpd_MEMq, + INTRINSIC_XED_IFORM_CVTPS2PD_XMMpd_XMMq, + INTRINSIC_XED_IFORM_CVTPS2PI_MMXq_MEMq, + INTRINSIC_XED_IFORM_CVTPS2PI_MMXq_XMMq, + INTRINSIC_XED_IFORM_CVTSD2SI_GPR32d_MEMsd, + INTRINSIC_XED_IFORM_CVTSD2SI_GPR32d_XMMsd, + INTRINSIC_XED_IFORM_CVTSD2SI_GPR64q_MEMsd, + INTRINSIC_XED_IFORM_CVTSD2SI_GPR64q_XMMsd, + INTRINSIC_XED_IFORM_CVTSD2SS_XMMss_MEMsd, + INTRINSIC_XED_IFORM_CVTSD2SS_XMMss_XMMsd, + INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_GPR32d, + INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_GPR64q, + INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_MEMd, + INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_MEMq, + INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_GPR32d, + INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_GPR64q, + INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_MEMd, + INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_MEMq, + INTRINSIC_XED_IFORM_CVTSS2SD_XMMsd_MEMss, + INTRINSIC_XED_IFORM_CVTSS2SD_XMMsd_XMMss, + INTRINSIC_XED_IFORM_CVTSS2SI_GPR32d_MEMss, + INTRINSIC_XED_IFORM_CVTSS2SI_GPR32d_XMMss, + INTRINSIC_XED_IFORM_CVTSS2SI_GPR64q_MEMss, + INTRINSIC_XED_IFORM_CVTSS2SI_GPR64q_XMMss, + INTRINSIC_XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd, + INTRINSIC_XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd, + INTRINSIC_XED_IFORM_CVTTPD2PI_MMXq_MEMpd, + INTRINSIC_XED_IFORM_CVTTPD2PI_MMXq_XMMpd, + INTRINSIC_XED_IFORM_CVTTPS2DQ_XMMdq_MEMps, + INTRINSIC_XED_IFORM_CVTTPS2DQ_XMMdq_XMMps, + INTRINSIC_XED_IFORM_CVTTPS2PI_MMXq_MEMq, + INTRINSIC_XED_IFORM_CVTTPS2PI_MMXq_XMMq, + INTRINSIC_XED_IFORM_CVTTSD2SI_GPR32d_MEMsd, + INTRINSIC_XED_IFORM_CVTTSD2SI_GPR32d_XMMsd, + INTRINSIC_XED_IFORM_CVTTSD2SI_GPR64q_MEMsd, + INTRINSIC_XED_IFORM_CVTTSD2SI_GPR64q_XMMsd, + INTRINSIC_XED_IFORM_CVTTSS2SI_GPR32d_MEMss, + INTRINSIC_XED_IFORM_CVTTSS2SI_GPR32d_XMMss, + INTRINSIC_XED_IFORM_CVTTSS2SI_GPR64q_MEMss, + INTRINSIC_XED_IFORM_CVTTSS2SI_GPR64q_XMMss, + INTRINSIC_XED_IFORM_CWD, + INTRINSIC_XED_IFORM_CWDE, + INTRINSIC_XED_IFORM_DAA, + INTRINSIC_XED_IFORM_DAS, + INTRINSIC_XED_IFORM_DEC_GPR8, + INTRINSIC_XED_IFORM_DEC_GPRv_48, + INTRINSIC_XED_IFORM_DEC_GPRv_FFr1, + INTRINSIC_XED_IFORM_DEC_MEMb, + INTRINSIC_XED_IFORM_DEC_MEMv, + INTRINSIC_XED_IFORM_DEC_LOCK_MEMb, + INTRINSIC_XED_IFORM_DEC_LOCK_MEMv, + INTRINSIC_XED_IFORM_DIV_GPR8, + INTRINSIC_XED_IFORM_DIV_GPRv, + INTRINSIC_XED_IFORM_DIV_MEMb, + INTRINSIC_XED_IFORM_DIV_MEMv, + INTRINSIC_XED_IFORM_DIVPD_XMMpd_MEMpd, + INTRINSIC_XED_IFORM_DIVPD_XMMpd_XMMpd, + INTRINSIC_XED_IFORM_DIVPS_XMMps_MEMps, + INTRINSIC_XED_IFORM_DIVPS_XMMps_XMMps, + INTRINSIC_XED_IFORM_DIVSD_XMMsd_MEMsd, + INTRINSIC_XED_IFORM_DIVSD_XMMsd_XMMsd, + INTRINSIC_XED_IFORM_DIVSS_XMMss_MEMss, + INTRINSIC_XED_IFORM_DIVSS_XMMss_XMMss, + INTRINSIC_XED_IFORM_DPPD_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_DPPD_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_DPPS_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_DPPS_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_EMMS, + INTRINSIC_XED_IFORM_ENCLS, + INTRINSIC_XED_IFORM_ENCLU, + INTRINSIC_XED_IFORM_ENCLV, + INTRINSIC_XED_IFORM_ENDBR32, + INTRINSIC_XED_IFORM_ENDBR64, + INTRINSIC_XED_IFORM_ENQCMD_GPRa_MEMu32, + INTRINSIC_XED_IFORM_ENQCMDS_GPRa_MEMu32, + INTRINSIC_XED_IFORM_ENTER_IMMw_IMMb, + INTRINSIC_XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb, + INTRINSIC_XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb, + INTRINSIC_XED_IFORM_EXTRQ_XMMq_IMMb_IMMb, + INTRINSIC_XED_IFORM_EXTRQ_XMMq_XMMdq, + INTRINSIC_XED_IFORM_F2XM1, + INTRINSIC_XED_IFORM_FABS, + INTRINSIC_XED_IFORM_FADD_ST0_MEMm64real, + INTRINSIC_XED_IFORM_FADD_ST0_MEMmem32real, + INTRINSIC_XED_IFORM_FADD_ST0_X87, + INTRINSIC_XED_IFORM_FADD_X87_ST0, + INTRINSIC_XED_IFORM_FADDP_X87_ST0, + INTRINSIC_XED_IFORM_FBLD_ST0_MEMmem80dec, + INTRINSIC_XED_IFORM_FBSTP_MEMmem80dec_ST0, + INTRINSIC_XED_IFORM_FCHS, + INTRINSIC_XED_IFORM_FCMOVB_ST0_X87, + INTRINSIC_XED_IFORM_FCMOVBE_ST0_X87, + INTRINSIC_XED_IFORM_FCMOVE_ST0_X87, + INTRINSIC_XED_IFORM_FCMOVNB_ST0_X87, + INTRINSIC_XED_IFORM_FCMOVNBE_ST0_X87, + INTRINSIC_XED_IFORM_FCMOVNE_ST0_X87, + INTRINSIC_XED_IFORM_FCMOVNU_ST0_X87, + INTRINSIC_XED_IFORM_FCMOVU_ST0_X87, + INTRINSIC_XED_IFORM_FCOM_ST0_MEMm64real, + INTRINSIC_XED_IFORM_FCOM_ST0_MEMmem32real, + INTRINSIC_XED_IFORM_FCOM_ST0_X87, + INTRINSIC_XED_IFORM_FCOM_ST0_X87_DCD0, + INTRINSIC_XED_IFORM_FCOMI_ST0_X87, + INTRINSIC_XED_IFORM_FCOMIP_ST0_X87, + INTRINSIC_XED_IFORM_FCOMP_ST0_MEMm64real, + INTRINSIC_XED_IFORM_FCOMP_ST0_MEMmem32real, + INTRINSIC_XED_IFORM_FCOMP_ST0_X87, + INTRINSIC_XED_IFORM_FCOMP_ST0_X87_DCD1, + INTRINSIC_XED_IFORM_FCOMP_ST0_X87_DED0, + INTRINSIC_XED_IFORM_FCOMPP, + INTRINSIC_XED_IFORM_FCOS, + INTRINSIC_XED_IFORM_FDECSTP, + INTRINSIC_XED_IFORM_FDISI8087_NOP, + INTRINSIC_XED_IFORM_FDIV_ST0_MEMm64real, + INTRINSIC_XED_IFORM_FDIV_ST0_MEMmem32real, + INTRINSIC_XED_IFORM_FDIV_ST0_X87, + INTRINSIC_XED_IFORM_FDIV_X87_ST0, + INTRINSIC_XED_IFORM_FDIVP_X87_ST0, + INTRINSIC_XED_IFORM_FDIVR_ST0_MEMm64real, + INTRINSIC_XED_IFORM_FDIVR_ST0_MEMmem32real, + INTRINSIC_XED_IFORM_FDIVR_ST0_X87, + INTRINSIC_XED_IFORM_FDIVR_X87_ST0, + INTRINSIC_XED_IFORM_FDIVRP_X87_ST0, + INTRINSIC_XED_IFORM_FEMMS, + INTRINSIC_XED_IFORM_FENI8087_NOP, + INTRINSIC_XED_IFORM_FFREE_X87, + INTRINSIC_XED_IFORM_FFREEP_X87, + INTRINSIC_XED_IFORM_FIADD_ST0_MEMmem16int, + INTRINSIC_XED_IFORM_FIADD_ST0_MEMmem32int, + INTRINSIC_XED_IFORM_FICOM_ST0_MEMmem16int, + INTRINSIC_XED_IFORM_FICOM_ST0_MEMmem32int, + INTRINSIC_XED_IFORM_FICOMP_ST0_MEMmem16int, + INTRINSIC_XED_IFORM_FICOMP_ST0_MEMmem32int, + INTRINSIC_XED_IFORM_FIDIV_ST0_MEMmem16int, + INTRINSIC_XED_IFORM_FIDIV_ST0_MEMmem32int, + INTRINSIC_XED_IFORM_FIDIVR_ST0_MEMmem16int, + INTRINSIC_XED_IFORM_FIDIVR_ST0_MEMmem32int, + INTRINSIC_XED_IFORM_FILD_ST0_MEMm64int, + INTRINSIC_XED_IFORM_FILD_ST0_MEMmem16int, + INTRINSIC_XED_IFORM_FILD_ST0_MEMmem32int, + INTRINSIC_XED_IFORM_FIMUL_ST0_MEMmem16int, + INTRINSIC_XED_IFORM_FIMUL_ST0_MEMmem32int, + INTRINSIC_XED_IFORM_FINCSTP, + INTRINSIC_XED_IFORM_FIST_MEMmem16int_ST0, + INTRINSIC_XED_IFORM_FIST_MEMmem32int_ST0, + INTRINSIC_XED_IFORM_FISTP_MEMm64int_ST0, + INTRINSIC_XED_IFORM_FISTP_MEMmem16int_ST0, + INTRINSIC_XED_IFORM_FISTP_MEMmem32int_ST0, + INTRINSIC_XED_IFORM_FISTTP_MEMm64int_ST0, + INTRINSIC_XED_IFORM_FISTTP_MEMmem16int_ST0, + INTRINSIC_XED_IFORM_FISTTP_MEMmem32int_ST0, + INTRINSIC_XED_IFORM_FISUB_ST0_MEMmem16int, + INTRINSIC_XED_IFORM_FISUB_ST0_MEMmem32int, + INTRINSIC_XED_IFORM_FISUBR_ST0_MEMmem16int, + INTRINSIC_XED_IFORM_FISUBR_ST0_MEMmem32int, + INTRINSIC_XED_IFORM_FLD_ST0_MEMm64real, + INTRINSIC_XED_IFORM_FLD_ST0_MEMmem32real, + INTRINSIC_XED_IFORM_FLD_ST0_MEMmem80real, + INTRINSIC_XED_IFORM_FLD_ST0_X87, + INTRINSIC_XED_IFORM_FLD1, + INTRINSIC_XED_IFORM_FLDCW_MEMmem16, + INTRINSIC_XED_IFORM_FLDENV_MEMmem14, + INTRINSIC_XED_IFORM_FLDENV_MEMmem28, + INTRINSIC_XED_IFORM_FLDL2E, + INTRINSIC_XED_IFORM_FLDL2T, + INTRINSIC_XED_IFORM_FLDLG2, + INTRINSIC_XED_IFORM_FLDLN2, + INTRINSIC_XED_IFORM_FLDPI, + INTRINSIC_XED_IFORM_FLDZ, + INTRINSIC_XED_IFORM_FMUL_ST0_MEMm64real, + INTRINSIC_XED_IFORM_FMUL_ST0_MEMmem32real, + INTRINSIC_XED_IFORM_FMUL_ST0_X87, + INTRINSIC_XED_IFORM_FMUL_X87_ST0, + INTRINSIC_XED_IFORM_FMULP_X87_ST0, + INTRINSIC_XED_IFORM_FNCLEX, + INTRINSIC_XED_IFORM_FNINIT, + INTRINSIC_XED_IFORM_FNOP, + INTRINSIC_XED_IFORM_FNSAVE_MEMmem108, + INTRINSIC_XED_IFORM_FNSAVE_MEMmem94, + INTRINSIC_XED_IFORM_FNSTCW_MEMmem16, + INTRINSIC_XED_IFORM_FNSTENV_MEMmem14, + INTRINSIC_XED_IFORM_FNSTENV_MEMmem28, + INTRINSIC_XED_IFORM_FNSTSW_AX, + INTRINSIC_XED_IFORM_FNSTSW_MEMmem16, + INTRINSIC_XED_IFORM_FPATAN, + INTRINSIC_XED_IFORM_FPREM, + INTRINSIC_XED_IFORM_FPREM1, + INTRINSIC_XED_IFORM_FPTAN, + INTRINSIC_XED_IFORM_FRNDINT, + INTRINSIC_XED_IFORM_FRSTOR_MEMmem108, + INTRINSIC_XED_IFORM_FRSTOR_MEMmem94, + INTRINSIC_XED_IFORM_FSCALE, + INTRINSIC_XED_IFORM_FSETPM287_NOP, + INTRINSIC_XED_IFORM_FSIN, + INTRINSIC_XED_IFORM_FSINCOS, + INTRINSIC_XED_IFORM_FSQRT, + INTRINSIC_XED_IFORM_FST_MEMm64real_ST0, + INTRINSIC_XED_IFORM_FST_MEMmem32real_ST0, + INTRINSIC_XED_IFORM_FST_X87_ST0, + INTRINSIC_XED_IFORM_FSTP_MEMm64real_ST0, + INTRINSIC_XED_IFORM_FSTP_MEMmem32real_ST0, + INTRINSIC_XED_IFORM_FSTP_MEMmem80real_ST0, + INTRINSIC_XED_IFORM_FSTP_X87_ST0, + INTRINSIC_XED_IFORM_FSTP_X87_ST0_DFD0, + INTRINSIC_XED_IFORM_FSTP_X87_ST0_DFD1, + INTRINSIC_XED_IFORM_FSTPNCE_X87_ST0, + INTRINSIC_XED_IFORM_FSUB_ST0_MEMm64real, + INTRINSIC_XED_IFORM_FSUB_ST0_MEMmem32real, + INTRINSIC_XED_IFORM_FSUB_ST0_X87, + INTRINSIC_XED_IFORM_FSUB_X87_ST0, + INTRINSIC_XED_IFORM_FSUBP_X87_ST0, + INTRINSIC_XED_IFORM_FSUBR_ST0_MEMm64real, + INTRINSIC_XED_IFORM_FSUBR_ST0_MEMmem32real, + INTRINSIC_XED_IFORM_FSUBR_ST0_X87, + INTRINSIC_XED_IFORM_FSUBR_X87_ST0, + INTRINSIC_XED_IFORM_FSUBRP_X87_ST0, + INTRINSIC_XED_IFORM_FTST, + INTRINSIC_XED_IFORM_FUCOM_ST0_X87, + INTRINSIC_XED_IFORM_FUCOMI_ST0_X87, + INTRINSIC_XED_IFORM_FUCOMIP_ST0_X87, + INTRINSIC_XED_IFORM_FUCOMP_ST0_X87, + INTRINSIC_XED_IFORM_FUCOMPP, + INTRINSIC_XED_IFORM_FWAIT, + INTRINSIC_XED_IFORM_FXAM, + INTRINSIC_XED_IFORM_FXCH_ST0_X87, + INTRINSIC_XED_IFORM_FXCH_ST0_X87_DDC1, + INTRINSIC_XED_IFORM_FXCH_ST0_X87_DFC1, + INTRINSIC_XED_IFORM_FXRSTOR_MEMmfpxenv, + INTRINSIC_XED_IFORM_FXRSTOR64_MEMmfpxenv, + INTRINSIC_XED_IFORM_FXSAVE_MEMmfpxenv, + INTRINSIC_XED_IFORM_FXSAVE64_MEMmfpxenv, + INTRINSIC_XED_IFORM_FXTRACT, + INTRINSIC_XED_IFORM_FYL2X, + INTRINSIC_XED_IFORM_FYL2XP1, + INTRINSIC_XED_IFORM_GETSEC, + INTRINSIC_XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8, + INTRINSIC_XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8, + INTRINSIC_XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8, + INTRINSIC_XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8, + INTRINSIC_XED_IFORM_GF2P8MULB_XMMu8_MEMu8, + INTRINSIC_XED_IFORM_GF2P8MULB_XMMu8_XMMu8, + INTRINSIC_XED_IFORM_HADDPD_XMMpd_MEMpd, + INTRINSIC_XED_IFORM_HADDPD_XMMpd_XMMpd, + INTRINSIC_XED_IFORM_HADDPS_XMMps_MEMps, + INTRINSIC_XED_IFORM_HADDPS_XMMps_XMMps, + INTRINSIC_XED_IFORM_HLT, + INTRINSIC_XED_IFORM_HSUBPD_XMMpd_MEMpd, + INTRINSIC_XED_IFORM_HSUBPD_XMMpd_XMMpd, + INTRINSIC_XED_IFORM_HSUBPS_XMMps_MEMps, + INTRINSIC_XED_IFORM_HSUBPS_XMMps_XMMps, + INTRINSIC_XED_IFORM_IDIV_GPR8, + INTRINSIC_XED_IFORM_IDIV_GPRv, + INTRINSIC_XED_IFORM_IDIV_MEMb, + INTRINSIC_XED_IFORM_IDIV_MEMv, + INTRINSIC_XED_IFORM_IMUL_GPR8, + INTRINSIC_XED_IFORM_IMUL_GPRv, + INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv, + INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_IMMb, + INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_IMMz, + INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv, + INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv_IMMb, + INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv_IMMz, + INTRINSIC_XED_IFORM_IMUL_MEMb, + INTRINSIC_XED_IFORM_IMUL_MEMv, + INTRINSIC_XED_IFORM_IN_AL_DX, + INTRINSIC_XED_IFORM_IN_AL_IMMb, + INTRINSIC_XED_IFORM_IN_OeAX_DX, + INTRINSIC_XED_IFORM_IN_OeAX_IMMb, + INTRINSIC_XED_IFORM_INC_GPR8, + INTRINSIC_XED_IFORM_INC_GPRv_40, + INTRINSIC_XED_IFORM_INC_GPRv_FFr0, + INTRINSIC_XED_IFORM_INC_MEMb, + INTRINSIC_XED_IFORM_INC_MEMv, + INTRINSIC_XED_IFORM_INCSSPD_GPR32u8, + INTRINSIC_XED_IFORM_INCSSPQ_GPR64u8, + INTRINSIC_XED_IFORM_INC_LOCK_MEMb, + INTRINSIC_XED_IFORM_INC_LOCK_MEMv, + INTRINSIC_XED_IFORM_INSB, + INTRINSIC_XED_IFORM_INSD, + INTRINSIC_XED_IFORM_INSERTPS_XMMps_MEMd_IMMb, + INTRINSIC_XED_IFORM_INSERTPS_XMMps_XMMps_IMMb, + INTRINSIC_XED_IFORM_INSERTQ_XMMq_XMMdq, + INTRINSIC_XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb, + INTRINSIC_XED_IFORM_INSW, + INTRINSIC_XED_IFORM_INT_IMMb, + INTRINSIC_XED_IFORM_INT1, + INTRINSIC_XED_IFORM_INT3, + INTRINSIC_XED_IFORM_INTO, + INTRINSIC_XED_IFORM_INVD, + INTRINSIC_XED_IFORM_INVEPT_GPR32_MEMdq, + INTRINSIC_XED_IFORM_INVEPT_GPR64_MEMdq, + INTRINSIC_XED_IFORM_INVLPG_MEMb, + INTRINSIC_XED_IFORM_INVLPGA_ArAX_ECX, + INTRINSIC_XED_IFORM_INVPCID_GPR32_MEMdq, + INTRINSIC_XED_IFORM_INVPCID_GPR64_MEMdq, + INTRINSIC_XED_IFORM_INVVPID_GPR32_MEMdq, + INTRINSIC_XED_IFORM_INVVPID_GPR64_MEMdq, + INTRINSIC_XED_IFORM_IRET, + INTRINSIC_XED_IFORM_IRETD, + INTRINSIC_XED_IFORM_IRETQ, + INTRINSIC_XED_IFORM_JB_RELBRb, + INTRINSIC_XED_IFORM_JB_RELBRd, + INTRINSIC_XED_IFORM_JB_RELBRz, + INTRINSIC_XED_IFORM_JBE_RELBRb, + INTRINSIC_XED_IFORM_JBE_RELBRd, + INTRINSIC_XED_IFORM_JBE_RELBRz, + INTRINSIC_XED_IFORM_JCXZ_RELBRb, + INTRINSIC_XED_IFORM_JECXZ_RELBRb, + INTRINSIC_XED_IFORM_JL_RELBRb, + INTRINSIC_XED_IFORM_JL_RELBRd, + INTRINSIC_XED_IFORM_JL_RELBRz, + INTRINSIC_XED_IFORM_JLE_RELBRb, + INTRINSIC_XED_IFORM_JLE_RELBRd, + INTRINSIC_XED_IFORM_JLE_RELBRz, + INTRINSIC_XED_IFORM_JMP_GPRv, + INTRINSIC_XED_IFORM_JMP_MEMv, + INTRINSIC_XED_IFORM_JMP_RELBRb, + INTRINSIC_XED_IFORM_JMP_RELBRd, + INTRINSIC_XED_IFORM_JMP_RELBRz, + INTRINSIC_XED_IFORM_JMP_FAR_MEMp2, + INTRINSIC_XED_IFORM_JMP_FAR_PTRp_IMMw, + INTRINSIC_XED_IFORM_JNB_RELBRb, + INTRINSIC_XED_IFORM_JNB_RELBRd, + INTRINSIC_XED_IFORM_JNB_RELBRz, + INTRINSIC_XED_IFORM_JNBE_RELBRb, + INTRINSIC_XED_IFORM_JNBE_RELBRd, + INTRINSIC_XED_IFORM_JNBE_RELBRz, + INTRINSIC_XED_IFORM_JNL_RELBRb, + INTRINSIC_XED_IFORM_JNL_RELBRd, + INTRINSIC_XED_IFORM_JNL_RELBRz, + INTRINSIC_XED_IFORM_JNLE_RELBRb, + INTRINSIC_XED_IFORM_JNLE_RELBRd, + INTRINSIC_XED_IFORM_JNLE_RELBRz, + INTRINSIC_XED_IFORM_JNO_RELBRb, + INTRINSIC_XED_IFORM_JNO_RELBRd, + INTRINSIC_XED_IFORM_JNO_RELBRz, + INTRINSIC_XED_IFORM_JNP_RELBRb, + INTRINSIC_XED_IFORM_JNP_RELBRd, + INTRINSIC_XED_IFORM_JNP_RELBRz, + INTRINSIC_XED_IFORM_JNS_RELBRb, + INTRINSIC_XED_IFORM_JNS_RELBRd, + INTRINSIC_XED_IFORM_JNS_RELBRz, + INTRINSIC_XED_IFORM_JNZ_RELBRb, + INTRINSIC_XED_IFORM_JNZ_RELBRd, + INTRINSIC_XED_IFORM_JNZ_RELBRz, + INTRINSIC_XED_IFORM_JO_RELBRb, + INTRINSIC_XED_IFORM_JO_RELBRd, + INTRINSIC_XED_IFORM_JO_RELBRz, + INTRINSIC_XED_IFORM_JP_RELBRb, + INTRINSIC_XED_IFORM_JP_RELBRd, + INTRINSIC_XED_IFORM_JP_RELBRz, + INTRINSIC_XED_IFORM_JRCXZ_RELBRb, + INTRINSIC_XED_IFORM_JS_RELBRb, + INTRINSIC_XED_IFORM_JS_RELBRd, + INTRINSIC_XED_IFORM_JS_RELBRz, + INTRINSIC_XED_IFORM_JZ_RELBRb, + INTRINSIC_XED_IFORM_JZ_RELBRd, + INTRINSIC_XED_IFORM_JZ_RELBRz, + INTRINSIC_XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512, + INTRINSIC_XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512, + INTRINSIC_XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512, + INTRINSIC_XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512, + INTRINSIC_XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512, + INTRINSIC_XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512, + INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512, + INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512, + INTRINSIC_XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512, + INTRINSIC_XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512, + INTRINSIC_XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512, + INTRINSIC_XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512, + INTRINSIC_XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512, + INTRINSIC_XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512, + INTRINSIC_XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512, + INTRINSIC_XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512, + INTRINSIC_XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512, + INTRINSIC_XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512, + INTRINSIC_XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_LAHF, + INTRINSIC_XED_IFORM_LAR_GPRv_GPRv, + INTRINSIC_XED_IFORM_LAR_GPRv_MEMw, + INTRINSIC_XED_IFORM_LDDQU_XMMpd_MEMdq, + INTRINSIC_XED_IFORM_LDMXCSR_MEMd, + INTRINSIC_XED_IFORM_LDS_GPRz_MEMp, + INTRINSIC_XED_IFORM_LEA_GPRv_AGEN, + INTRINSIC_XED_IFORM_LEAVE, + INTRINSIC_XED_IFORM_LES_GPRz_MEMp, + INTRINSIC_XED_IFORM_LFENCE, + INTRINSIC_XED_IFORM_LFS_GPRv_MEMp2, + INTRINSIC_XED_IFORM_LGDT_MEMs, + INTRINSIC_XED_IFORM_LGDT_MEMs64, + INTRINSIC_XED_IFORM_LGS_GPRv_MEMp2, + INTRINSIC_XED_IFORM_LIDT_MEMs, + INTRINSIC_XED_IFORM_LIDT_MEMs64, + INTRINSIC_XED_IFORM_LLDT_GPR16, + INTRINSIC_XED_IFORM_LLDT_MEMw, + INTRINSIC_XED_IFORM_LLWPCB_GPRyy, + INTRINSIC_XED_IFORM_LMSW_GPR16, + INTRINSIC_XED_IFORM_LMSW_MEMw, + INTRINSIC_XED_IFORM_LODSB, + INTRINSIC_XED_IFORM_LODSD, + INTRINSIC_XED_IFORM_LODSQ, + INTRINSIC_XED_IFORM_LODSW, + INTRINSIC_XED_IFORM_LOOP_RELBRb, + INTRINSIC_XED_IFORM_LOOPE_RELBRb, + INTRINSIC_XED_IFORM_LOOPNE_RELBRb, + INTRINSIC_XED_IFORM_LSL_GPRv_GPRz, + INTRINSIC_XED_IFORM_LSL_GPRv_MEMw, + INTRINSIC_XED_IFORM_LSS_GPRv_MEMp2, + INTRINSIC_XED_IFORM_LTR_GPR16, + INTRINSIC_XED_IFORM_LTR_MEMw, + INTRINSIC_XED_IFORM_LWPINS_VGPRyy_GPR32y_IMMd, + INTRINSIC_XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd, + INTRINSIC_XED_IFORM_LWPVAL_VGPRyy_GPR32y_IMMd, + INTRINSIC_XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd, + INTRINSIC_XED_IFORM_LZCNT_GPRv_GPRv, + INTRINSIC_XED_IFORM_LZCNT_GPRv_MEMv, + INTRINSIC_XED_IFORM_MASKMOVDQU_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_MASKMOVQ_MMXq_MMXq, + INTRINSIC_XED_IFORM_MAXPD_XMMpd_MEMpd, + INTRINSIC_XED_IFORM_MAXPD_XMMpd_XMMpd, + INTRINSIC_XED_IFORM_MAXPS_XMMps_MEMps, + INTRINSIC_XED_IFORM_MAXPS_XMMps_XMMps, + INTRINSIC_XED_IFORM_MAXSD_XMMsd_MEMsd, + INTRINSIC_XED_IFORM_MAXSD_XMMsd_XMMsd, + INTRINSIC_XED_IFORM_MAXSS_XMMss_MEMss, + INTRINSIC_XED_IFORM_MAXSS_XMMss_XMMss, + INTRINSIC_XED_IFORM_MCOMMIT, + INTRINSIC_XED_IFORM_MFENCE, + INTRINSIC_XED_IFORM_MINPD_XMMpd_MEMpd, + INTRINSIC_XED_IFORM_MINPD_XMMpd_XMMpd, + INTRINSIC_XED_IFORM_MINPS_XMMps_MEMps, + INTRINSIC_XED_IFORM_MINPS_XMMps_XMMps, + INTRINSIC_XED_IFORM_MINSD_XMMsd_MEMsd, + INTRINSIC_XED_IFORM_MINSD_XMMsd_XMMsd, + INTRINSIC_XED_IFORM_MINSS_XMMss_MEMss, + INTRINSIC_XED_IFORM_MINSS_XMMss_XMMss, + INTRINSIC_XED_IFORM_MONITOR, + INTRINSIC_XED_IFORM_MONITORX, + INTRINSIC_XED_IFORM_MOV_AL_MEMb, + INTRINSIC_XED_IFORM_MOV_GPR8_GPR8_88, + INTRINSIC_XED_IFORM_MOV_GPR8_GPR8_8A, + INTRINSIC_XED_IFORM_MOV_GPR8_IMMb_B0, + INTRINSIC_XED_IFORM_MOV_GPR8_IMMb_C6r0, + INTRINSIC_XED_IFORM_MOV_GPR8_MEMb, + INTRINSIC_XED_IFORM_MOV_GPRv_GPRv_89, + INTRINSIC_XED_IFORM_MOV_GPRv_GPRv_8B, + INTRINSIC_XED_IFORM_MOV_GPRv_IMMv, + INTRINSIC_XED_IFORM_MOV_GPRv_IMMz, + INTRINSIC_XED_IFORM_MOV_GPRv_MEMv, + INTRINSIC_XED_IFORM_MOV_GPRv_SEG, + INTRINSIC_XED_IFORM_MOV_MEMb_AL, + INTRINSIC_XED_IFORM_MOV_MEMb_GPR8, + INTRINSIC_XED_IFORM_MOV_MEMb_IMMb, + INTRINSIC_XED_IFORM_MOV_MEMv_GPRv, + INTRINSIC_XED_IFORM_MOV_MEMv_IMMz, + INTRINSIC_XED_IFORM_MOV_MEMv_OrAX, + INTRINSIC_XED_IFORM_MOV_MEMw_SEG, + INTRINSIC_XED_IFORM_MOV_OrAX_MEMv, + INTRINSIC_XED_IFORM_MOV_SEG_GPR16, + INTRINSIC_XED_IFORM_MOV_SEG_MEMw, + INTRINSIC_XED_IFORM_MOVAPD_MEMpd_XMMpd, + INTRINSIC_XED_IFORM_MOVAPD_XMMpd_MEMpd, + INTRINSIC_XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28, + INTRINSIC_XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29, + INTRINSIC_XED_IFORM_MOVAPS_MEMps_XMMps, + INTRINSIC_XED_IFORM_MOVAPS_XMMps_MEMps, + INTRINSIC_XED_IFORM_MOVAPS_XMMps_XMMps_0F28, + INTRINSIC_XED_IFORM_MOVAPS_XMMps_XMMps_0F29, + INTRINSIC_XED_IFORM_MOVBE_GPRv_MEMv, + INTRINSIC_XED_IFORM_MOVBE_MEMv_GPRv, + INTRINSIC_XED_IFORM_MOVD_GPR32_MMXd, + INTRINSIC_XED_IFORM_MOVD_GPR32_XMMd, + INTRINSIC_XED_IFORM_MOVD_MEMd_MMXd, + INTRINSIC_XED_IFORM_MOVD_MEMd_XMMd, + INTRINSIC_XED_IFORM_MOVD_MMXq_GPR32, + INTRINSIC_XED_IFORM_MOVD_MMXq_MEMd, + INTRINSIC_XED_IFORM_MOVD_XMMdq_GPR32, + INTRINSIC_XED_IFORM_MOVD_XMMdq_MEMd, + INTRINSIC_XED_IFORM_MOVDDUP_XMMdq_MEMq, + INTRINSIC_XED_IFORM_MOVDDUP_XMMdq_XMMq, + INTRINSIC_XED_IFORM_MOVDIR64B_GPRa_MEM, + INTRINSIC_XED_IFORM_MOVDIRI_MEMu32_GPR32u32, + INTRINSIC_XED_IFORM_MOVDIRI_MEMu64_GPR64u64, + INTRINSIC_XED_IFORM_MOVDQ2Q_MMXq_XMMq, + INTRINSIC_XED_IFORM_MOVDQA_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_MOVDQA_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F, + INTRINSIC_XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F, + INTRINSIC_XED_IFORM_MOVDQU_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_MOVDQU_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F, + INTRINSIC_XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F, + INTRINSIC_XED_IFORM_MOVHLPS_XMMq_XMMq, + INTRINSIC_XED_IFORM_MOVHPD_MEMq_XMMsd, + INTRINSIC_XED_IFORM_MOVHPD_XMMsd_MEMq, + INTRINSIC_XED_IFORM_MOVHPS_MEMq_XMMps, + INTRINSIC_XED_IFORM_MOVHPS_XMMq_MEMq, + INTRINSIC_XED_IFORM_MOVLHPS_XMMq_XMMq, + INTRINSIC_XED_IFORM_MOVLPD_MEMq_XMMsd, + INTRINSIC_XED_IFORM_MOVLPD_XMMsd_MEMq, + INTRINSIC_XED_IFORM_MOVLPS_MEMq_XMMps, + INTRINSIC_XED_IFORM_MOVLPS_XMMq_MEMq, + INTRINSIC_XED_IFORM_MOVMSKPD_GPR32_XMMpd, + INTRINSIC_XED_IFORM_MOVMSKPS_GPR32_XMMps, + INTRINSIC_XED_IFORM_MOVNTDQ_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_MOVNTDQA_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_MOVNTI_MEMd_GPR32, + INTRINSIC_XED_IFORM_MOVNTI_MEMq_GPR64, + INTRINSIC_XED_IFORM_MOVNTPD_MEMdq_XMMpd, + INTRINSIC_XED_IFORM_MOVNTPS_MEMdq_XMMps, + INTRINSIC_XED_IFORM_MOVNTQ_MEMq_MMXq, + INTRINSIC_XED_IFORM_MOVNTSD_MEMq_XMMq, + INTRINSIC_XED_IFORM_MOVNTSS_MEMd_XMMd, + INTRINSIC_XED_IFORM_MOVQ_GPR64_MMXq, + INTRINSIC_XED_IFORM_MOVQ_GPR64_XMMq, + INTRINSIC_XED_IFORM_MOVQ_MEMq_MMXq_0F7E, + INTRINSIC_XED_IFORM_MOVQ_MEMq_MMXq_0F7F, + INTRINSIC_XED_IFORM_MOVQ_MEMq_XMMq_0F7E, + INTRINSIC_XED_IFORM_MOVQ_MEMq_XMMq_0FD6, + INTRINSIC_XED_IFORM_MOVQ_MMXq_GPR64, + INTRINSIC_XED_IFORM_MOVQ_MMXq_MEMq_0F6E, + INTRINSIC_XED_IFORM_MOVQ_MMXq_MEMq_0F6F, + INTRINSIC_XED_IFORM_MOVQ_MMXq_MMXq_0F6F, + INTRINSIC_XED_IFORM_MOVQ_MMXq_MMXq_0F7F, + INTRINSIC_XED_IFORM_MOVQ_XMMdq_GPR64, + INTRINSIC_XED_IFORM_MOVQ_XMMdq_MEMq_0F6E, + INTRINSIC_XED_IFORM_MOVQ_XMMdq_MEMq_0F7E, + INTRINSIC_XED_IFORM_MOVQ_XMMdq_XMMq_0F7E, + INTRINSIC_XED_IFORM_MOVQ_XMMdq_XMMq_0FD6, + INTRINSIC_XED_IFORM_MOVQ2DQ_XMMdq_MMXq, + INTRINSIC_XED_IFORM_MOVSB, + INTRINSIC_XED_IFORM_MOVSD, + INTRINSIC_XED_IFORM_MOVSD_XMM_MEMsd_XMMsd, + INTRINSIC_XED_IFORM_MOVSD_XMM_XMMdq_MEMsd, + INTRINSIC_XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10, + INTRINSIC_XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11, + INTRINSIC_XED_IFORM_MOVSHDUP_XMMps_MEMps, + INTRINSIC_XED_IFORM_MOVSHDUP_XMMps_XMMps, + INTRINSIC_XED_IFORM_MOVSLDUP_XMMps_MEMps, + INTRINSIC_XED_IFORM_MOVSLDUP_XMMps_XMMps, + INTRINSIC_XED_IFORM_MOVSQ, + INTRINSIC_XED_IFORM_MOVSS_MEMss_XMMss, + INTRINSIC_XED_IFORM_MOVSS_XMMdq_MEMss, + INTRINSIC_XED_IFORM_MOVSS_XMMss_XMMss_0F10, + INTRINSIC_XED_IFORM_MOVSS_XMMss_XMMss_0F11, + INTRINSIC_XED_IFORM_MOVSW, + INTRINSIC_XED_IFORM_MOVSX_GPRv_GPR16, + INTRINSIC_XED_IFORM_MOVSX_GPRv_GPR8, + INTRINSIC_XED_IFORM_MOVSX_GPRv_MEMb, + INTRINSIC_XED_IFORM_MOVSX_GPRv_MEMw, + INTRINSIC_XED_IFORM_MOVSXD_GPRv_GPRz, + INTRINSIC_XED_IFORM_MOVSXD_GPRv_MEMz, + INTRINSIC_XED_IFORM_MOVUPD_MEMpd_XMMpd, + INTRINSIC_XED_IFORM_MOVUPD_XMMpd_MEMpd, + INTRINSIC_XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10, + INTRINSIC_XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11, + INTRINSIC_XED_IFORM_MOVUPS_MEMps_XMMps, + INTRINSIC_XED_IFORM_MOVUPS_XMMps_MEMps, + INTRINSIC_XED_IFORM_MOVUPS_XMMps_XMMps_0F10, + INTRINSIC_XED_IFORM_MOVUPS_XMMps_XMMps_0F11, + INTRINSIC_XED_IFORM_MOVZX_GPRv_GPR16, + INTRINSIC_XED_IFORM_MOVZX_GPRv_GPR8, + INTRINSIC_XED_IFORM_MOVZX_GPRv_MEMb, + INTRINSIC_XED_IFORM_MOVZX_GPRv_MEMw, + INTRINSIC_XED_IFORM_MOV_CR_CR_GPR32, + INTRINSIC_XED_IFORM_MOV_CR_CR_GPR64, + INTRINSIC_XED_IFORM_MOV_CR_GPR32_CR, + INTRINSIC_XED_IFORM_MOV_CR_GPR64_CR, + INTRINSIC_XED_IFORM_MOV_DR_DR_GPR32, + INTRINSIC_XED_IFORM_MOV_DR_DR_GPR64, + INTRINSIC_XED_IFORM_MOV_DR_GPR32_DR, + INTRINSIC_XED_IFORM_MOV_DR_GPR64_DR, + INTRINSIC_XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_MUL_GPR8, + INTRINSIC_XED_IFORM_MUL_GPRv, + INTRINSIC_XED_IFORM_MUL_MEMb, + INTRINSIC_XED_IFORM_MUL_MEMv, + INTRINSIC_XED_IFORM_MULPD_XMMpd_MEMpd, + INTRINSIC_XED_IFORM_MULPD_XMMpd_XMMpd, + INTRINSIC_XED_IFORM_MULPS_XMMps_MEMps, + INTRINSIC_XED_IFORM_MULPS_XMMps_XMMps, + INTRINSIC_XED_IFORM_MULSD_XMMsd_MEMsd, + INTRINSIC_XED_IFORM_MULSD_XMMsd_XMMsd, + INTRINSIC_XED_IFORM_MULSS_XMMss_MEMss, + INTRINSIC_XED_IFORM_MULSS_XMMss_XMMss, + INTRINSIC_XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d, + INTRINSIC_XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq, + INTRINSIC_XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q, + INTRINSIC_XED_IFORM_MWAIT, + INTRINSIC_XED_IFORM_MWAITX, + INTRINSIC_XED_IFORM_NEG_GPR8, + INTRINSIC_XED_IFORM_NEG_GPRv, + INTRINSIC_XED_IFORM_NEG_MEMb, + INTRINSIC_XED_IFORM_NEG_MEMv, + INTRINSIC_XED_IFORM_NEG_LOCK_MEMb, + INTRINSIC_XED_IFORM_NEG_LOCK_MEMv, + INTRINSIC_XED_IFORM_NOP_90, + INTRINSIC_XED_IFORM_NOP_GPRv_0F18r0, + INTRINSIC_XED_IFORM_NOP_GPRv_0F18r1, + INTRINSIC_XED_IFORM_NOP_GPRv_0F18r2, + INTRINSIC_XED_IFORM_NOP_GPRv_0F18r3, + INTRINSIC_XED_IFORM_NOP_GPRv_0F18r4, + INTRINSIC_XED_IFORM_NOP_GPRv_0F18r5, + INTRINSIC_XED_IFORM_NOP_GPRv_0F18r6, + INTRINSIC_XED_IFORM_NOP_GPRv_0F18r7, + INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F0D, + INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F19, + INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1A, + INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1B, + INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1C, + INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1D, + INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1E, + INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1F, + INTRINSIC_XED_IFORM_NOP_GPRv_MEM_0F1B, + INTRINSIC_XED_IFORM_NOP_GPRv_MEMv_0F1A, + INTRINSIC_XED_IFORM_NOP_MEMv_0F18r4, + INTRINSIC_XED_IFORM_NOP_MEMv_0F18r5, + INTRINSIC_XED_IFORM_NOP_MEMv_0F18r6, + INTRINSIC_XED_IFORM_NOP_MEMv_0F18r7, + INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F19, + INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1C, + INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1D, + INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1E, + INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1F, + INTRINSIC_XED_IFORM_NOT_GPR8, + INTRINSIC_XED_IFORM_NOT_GPRv, + INTRINSIC_XED_IFORM_NOT_MEMb, + INTRINSIC_XED_IFORM_NOT_MEMv, + INTRINSIC_XED_IFORM_NOT_LOCK_MEMb, + INTRINSIC_XED_IFORM_NOT_LOCK_MEMv, + INTRINSIC_XED_IFORM_OR_AL_IMMb, + INTRINSIC_XED_IFORM_OR_GPR8_GPR8_08, + INTRINSIC_XED_IFORM_OR_GPR8_GPR8_0A, + INTRINSIC_XED_IFORM_OR_GPR8_IMMb_80r1, + INTRINSIC_XED_IFORM_OR_GPR8_IMMb_82r1, + INTRINSIC_XED_IFORM_OR_GPR8_MEMb, + INTRINSIC_XED_IFORM_OR_GPRv_GPRv_09, + INTRINSIC_XED_IFORM_OR_GPRv_GPRv_0B, + INTRINSIC_XED_IFORM_OR_GPRv_IMMb, + INTRINSIC_XED_IFORM_OR_GPRv_IMMz, + INTRINSIC_XED_IFORM_OR_GPRv_MEMv, + INTRINSIC_XED_IFORM_OR_MEMb_GPR8, + INTRINSIC_XED_IFORM_OR_MEMb_IMMb_80r1, + INTRINSIC_XED_IFORM_OR_MEMb_IMMb_82r1, + INTRINSIC_XED_IFORM_OR_MEMv_GPRv, + INTRINSIC_XED_IFORM_OR_MEMv_IMMb, + INTRINSIC_XED_IFORM_OR_MEMv_IMMz, + INTRINSIC_XED_IFORM_OR_OrAX_IMMz, + INTRINSIC_XED_IFORM_ORPD_XMMxuq_MEMxuq, + INTRINSIC_XED_IFORM_ORPD_XMMxuq_XMMxuq, + INTRINSIC_XED_IFORM_ORPS_XMMxud_MEMxud, + INTRINSIC_XED_IFORM_ORPS_XMMxud_XMMxud, + INTRINSIC_XED_IFORM_OR_LOCK_MEMb_GPR8, + INTRINSIC_XED_IFORM_OR_LOCK_MEMb_IMMb_80r1, + INTRINSIC_XED_IFORM_OR_LOCK_MEMb_IMMb_82r1, + INTRINSIC_XED_IFORM_OR_LOCK_MEMv_GPRv, + INTRINSIC_XED_IFORM_OR_LOCK_MEMv_IMMb, + INTRINSIC_XED_IFORM_OR_LOCK_MEMv_IMMz, + INTRINSIC_XED_IFORM_OUT_DX_AL, + INTRINSIC_XED_IFORM_OUT_DX_OeAX, + INTRINSIC_XED_IFORM_OUT_IMMb_AL, + INTRINSIC_XED_IFORM_OUT_IMMb_OeAX, + INTRINSIC_XED_IFORM_OUTSB, + INTRINSIC_XED_IFORM_OUTSD, + INTRINSIC_XED_IFORM_OUTSW, + INTRINSIC_XED_IFORM_PABSB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PABSB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PABSB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PABSB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PABSD_MMXq_MEMq, + INTRINSIC_XED_IFORM_PABSD_MMXq_MMXq, + INTRINSIC_XED_IFORM_PABSD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PABSD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PABSW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PABSW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PABSW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PABSW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PACKSSDW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PACKSSDW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PACKSSDW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PACKSSDW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PACKSSWB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PACKSSWB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PACKSSWB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PACKSSWB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PACKUSDW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PACKUSDW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PACKUSWB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PACKUSWB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PACKUSWB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PACKUSWB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PADDB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PADDB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PADDB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PADDB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PADDD_MMXq_MEMq, + INTRINSIC_XED_IFORM_PADDD_MMXq_MMXq, + INTRINSIC_XED_IFORM_PADDD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PADDD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PADDQ_MMXq_MEMq, + INTRINSIC_XED_IFORM_PADDQ_MMXq_MMXq, + INTRINSIC_XED_IFORM_PADDQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PADDQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PADDSB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PADDSB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PADDSB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PADDSB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PADDSW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PADDSW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PADDSW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PADDSW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PADDUSB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PADDUSB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PADDUSB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PADDUSB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PADDUSW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PADDUSW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PADDUSW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PADDUSW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PADDW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PADDW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PADDW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PADDW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PALIGNR_MMXq_MEMq_IMMb, + INTRINSIC_XED_IFORM_PALIGNR_MMXq_MMXq_IMMb, + INTRINSIC_XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PAND_MMXq_MEMq, + INTRINSIC_XED_IFORM_PAND_MMXq_MMXq, + INTRINSIC_XED_IFORM_PAND_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PAND_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PANDN_MMXq_MEMq, + INTRINSIC_XED_IFORM_PANDN_MMXq_MMXq, + INTRINSIC_XED_IFORM_PANDN_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PANDN_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PAUSE, + INTRINSIC_XED_IFORM_PAVGB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PAVGB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PAVGB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PAVGB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PAVGUSB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PAVGUSB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PAVGW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PAVGW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PAVGW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PAVGW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PBLENDVB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PBLENDVB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PCMPEQB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PCMPEQB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PCMPEQB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PCMPEQB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PCMPEQD_MMXq_MEMq, + INTRINSIC_XED_IFORM_PCMPEQD_MMXq_MMXq, + INTRINSIC_XED_IFORM_PCMPEQD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PCMPEQD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PCMPEQQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PCMPEQQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PCMPEQW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PCMPEQW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PCMPEQW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PCMPEQW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PCMPGTB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PCMPGTB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PCMPGTB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PCMPGTB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PCMPGTD_MMXq_MEMq, + INTRINSIC_XED_IFORM_PCMPGTD_MMXq_MMXq, + INTRINSIC_XED_IFORM_PCMPGTD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PCMPGTD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PCMPGTQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PCMPGTQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PCMPGTW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PCMPGTW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PCMPGTW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PCMPGTW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PCONFIG, + INTRINSIC_XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d, + INTRINSIC_XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq, + INTRINSIC_XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q, + INTRINSIC_XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d, + INTRINSIC_XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq, + INTRINSIC_XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q, + INTRINSIC_XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PEXTRW_GPR32_MMXq_IMMb, + INTRINSIC_XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PF2ID_MMXq_MEMq, + INTRINSIC_XED_IFORM_PF2ID_MMXq_MMXq, + INTRINSIC_XED_IFORM_PF2IW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PF2IW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFACC_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFACC_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFADD_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFADD_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFCMPEQ_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFCMPEQ_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFCMPGE_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFCMPGE_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFCMPGT_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFCMPGT_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFMAX_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFMAX_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFMIN_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFMIN_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFMUL_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFMUL_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFNACC_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFNACC_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFPNACC_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFPNACC_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFRCP_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFRCP_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFRCPIT1_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFRCPIT1_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFRCPIT2_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFRCPIT2_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFRSQIT1_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFRSQIT1_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFRSQRT_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFRSQRT_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFSUB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFSUB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PFSUBR_MMXq_MEMq, + INTRINSIC_XED_IFORM_PFSUBR_MMXq_MMXq, + INTRINSIC_XED_IFORM_PHADDD_MMXq_MEMq, + INTRINSIC_XED_IFORM_PHADDD_MMXq_MMXq, + INTRINSIC_XED_IFORM_PHADDD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PHADDD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PHADDSW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PHADDSW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PHADDSW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PHADDSW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PHADDW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PHADDW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PHADDW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PHADDW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PHMINPOSUW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PHMINPOSUW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PHSUBD_MMXq_MEMq, + INTRINSIC_XED_IFORM_PHSUBD_MMXq_MMXq, + INTRINSIC_XED_IFORM_PHSUBD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PHSUBD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PHSUBSW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PHSUBSW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PHSUBSW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PHSUBSW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PHSUBW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PHSUBW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PHSUBW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PHSUBW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PI2FD_MMXq_MEMq, + INTRINSIC_XED_IFORM_PI2FD_MMXq_MMXq, + INTRINSIC_XED_IFORM_PI2FW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PI2FW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb, + INTRINSIC_XED_IFORM_PINSRB_XMMdq_MEMb_IMMb, + INTRINSIC_XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb, + INTRINSIC_XED_IFORM_PINSRD_XMMdq_MEMd_IMMb, + INTRINSIC_XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb, + INTRINSIC_XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb, + INTRINSIC_XED_IFORM_PINSRW_MMXq_GPR32_IMMb, + INTRINSIC_XED_IFORM_PINSRW_MMXq_MEMw_IMMb, + INTRINSIC_XED_IFORM_PINSRW_XMMdq_GPR32_IMMb, + INTRINSIC_XED_IFORM_PINSRW_XMMdq_MEMw_IMMb, + INTRINSIC_XED_IFORM_PMADDUBSW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PMADDUBSW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PMADDUBSW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMADDUBSW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMADDWD_MMXq_MEMq, + INTRINSIC_XED_IFORM_PMADDWD_MMXq_MMXq, + INTRINSIC_XED_IFORM_PMADDWD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMADDWD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMAXSB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMAXSB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMAXSD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMAXSD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMAXSW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PMAXSW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PMAXSW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMAXSW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMAXUB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PMAXUB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PMAXUB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMAXUB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMAXUD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMAXUD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMAXUW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMAXUW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMINSB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMINSB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMINSD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMINSD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMINSW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PMINSW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PMINSW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMINSW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMINUB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PMINUB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PMINUB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMINUB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMINUD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMINUD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMINUW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMINUW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMOVMSKB_GPR32_MMXq, + INTRINSIC_XED_IFORM_PMOVMSKB_GPR32_XMMdq, + INTRINSIC_XED_IFORM_PMOVSXBD_XMMdq_MEMd, + INTRINSIC_XED_IFORM_PMOVSXBD_XMMdq_XMMd, + INTRINSIC_XED_IFORM_PMOVSXBQ_XMMdq_MEMw, + INTRINSIC_XED_IFORM_PMOVSXBQ_XMMdq_XMMw, + INTRINSIC_XED_IFORM_PMOVSXBW_XMMdq_MEMq, + INTRINSIC_XED_IFORM_PMOVSXBW_XMMdq_XMMq, + INTRINSIC_XED_IFORM_PMOVSXDQ_XMMdq_MEMq, + INTRINSIC_XED_IFORM_PMOVSXDQ_XMMdq_XMMq, + INTRINSIC_XED_IFORM_PMOVSXWD_XMMdq_MEMq, + INTRINSIC_XED_IFORM_PMOVSXWD_XMMdq_XMMq, + INTRINSIC_XED_IFORM_PMOVSXWQ_XMMdq_MEMd, + INTRINSIC_XED_IFORM_PMOVSXWQ_XMMdq_XMMd, + INTRINSIC_XED_IFORM_PMOVZXBD_XMMdq_MEMd, + INTRINSIC_XED_IFORM_PMOVZXBD_XMMdq_XMMd, + INTRINSIC_XED_IFORM_PMOVZXBQ_XMMdq_MEMw, + INTRINSIC_XED_IFORM_PMOVZXBQ_XMMdq_XMMw, + INTRINSIC_XED_IFORM_PMOVZXBW_XMMdq_MEMq, + INTRINSIC_XED_IFORM_PMOVZXBW_XMMdq_XMMq, + INTRINSIC_XED_IFORM_PMOVZXDQ_XMMdq_MEMq, + INTRINSIC_XED_IFORM_PMOVZXDQ_XMMdq_XMMq, + INTRINSIC_XED_IFORM_PMOVZXWD_XMMdq_MEMq, + INTRINSIC_XED_IFORM_PMOVZXWD_XMMdq_XMMq, + INTRINSIC_XED_IFORM_PMOVZXWQ_XMMdq_MEMd, + INTRINSIC_XED_IFORM_PMOVZXWQ_XMMdq_XMMd, + INTRINSIC_XED_IFORM_PMULDQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMULDQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMULHRSW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PMULHRSW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PMULHRSW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMULHRSW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMULHRW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PMULHRW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PMULHUW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PMULHUW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PMULHUW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMULHUW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMULHW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PMULHW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PMULHW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMULHW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMULLD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMULLD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMULLW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PMULLW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PMULLW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMULLW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PMULUDQ_MMXq_MEMq, + INTRINSIC_XED_IFORM_PMULUDQ_MMXq_MMXq, + INTRINSIC_XED_IFORM_PMULUDQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PMULUDQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_POP_DS, + INTRINSIC_XED_IFORM_POP_ES, + INTRINSIC_XED_IFORM_POP_FS, + INTRINSIC_XED_IFORM_POP_GPRv_58, + INTRINSIC_XED_IFORM_POP_GPRv_8F, + INTRINSIC_XED_IFORM_POP_GS, + INTRINSIC_XED_IFORM_POP_MEMv, + INTRINSIC_XED_IFORM_POP_SS, + INTRINSIC_XED_IFORM_POPA, + INTRINSIC_XED_IFORM_POPAD, + INTRINSIC_XED_IFORM_POPCNT_GPRv_GPRv, + INTRINSIC_XED_IFORM_POPCNT_GPRv_MEMv, + INTRINSIC_XED_IFORM_POPF, + INTRINSIC_XED_IFORM_POPFD, + INTRINSIC_XED_IFORM_POPFQ, + INTRINSIC_XED_IFORM_POR_MMXq_MEMq, + INTRINSIC_XED_IFORM_POR_MMXq_MMXq, + INTRINSIC_XED_IFORM_POR_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_POR_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PREFETCHNTA_MEMmprefetch, + INTRINSIC_XED_IFORM_PREFETCHT0_MEMmprefetch, + INTRINSIC_XED_IFORM_PREFETCHT1_MEMmprefetch, + INTRINSIC_XED_IFORM_PREFETCHT2_MEMmprefetch, + INTRINSIC_XED_IFORM_PREFETCHW_0F0Dr1, + INTRINSIC_XED_IFORM_PREFETCHW_0F0Dr3, + INTRINSIC_XED_IFORM_PREFETCHWT1_MEMu8, + INTRINSIC_XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch, + INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr4, + INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr5, + INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr6, + INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr7, + INTRINSIC_XED_IFORM_PSADBW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSADBW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSADBW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSADBW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSHUFB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSHUFB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSHUFB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSHUFB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PSHUFW_MMXq_MEMq_IMMb, + INTRINSIC_XED_IFORM_PSHUFW_MMXq_MMXq_IMMb, + INTRINSIC_XED_IFORM_PSIGNB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSIGNB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSIGNB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSIGNB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSIGND_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSIGND_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSIGND_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSIGND_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSIGNW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSIGNW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSIGNW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSIGNW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSLLD_MMXq_IMMb, + INTRINSIC_XED_IFORM_PSLLD_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSLLD_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSLLD_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PSLLD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSLLD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSLLDQ_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PSLLQ_MMXq_IMMb, + INTRINSIC_XED_IFORM_PSLLQ_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSLLQ_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSLLQ_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PSLLQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSLLQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSLLW_MMXq_IMMb, + INTRINSIC_XED_IFORM_PSLLW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSLLW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSLLW_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PSLLW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSLLW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSMASH_RAX, + INTRINSIC_XED_IFORM_PSRAD_MMXq_IMMb, + INTRINSIC_XED_IFORM_PSRAD_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSRAD_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSRAD_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PSRAD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSRAD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSRAW_MMXq_IMMb, + INTRINSIC_XED_IFORM_PSRAW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSRAW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSRAW_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PSRAW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSRAW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSRLD_MMXq_IMMb, + INTRINSIC_XED_IFORM_PSRLD_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSRLD_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSRLD_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PSRLD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSRLD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSRLDQ_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PSRLQ_MMXq_IMMb, + INTRINSIC_XED_IFORM_PSRLQ_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSRLQ_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSRLQ_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PSRLQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSRLQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSRLW_MMXq_IMMb, + INTRINSIC_XED_IFORM_PSRLW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSRLW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSRLW_XMMdq_IMMb, + INTRINSIC_XED_IFORM_PSRLW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSRLW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSUBB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSUBB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSUBB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSUBB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSUBD_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSUBD_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSUBD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSUBD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSUBQ_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSUBQ_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSUBQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSUBQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSUBSB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSUBSB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSUBSB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSUBSB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSUBSW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSUBSW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSUBSW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSUBSW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSUBUSB_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSUBUSB_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSUBUSB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSUBUSB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSUBUSW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSUBUSW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSUBUSW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSUBUSW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSUBW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSUBW_MMXq_MMXq, + INTRINSIC_XED_IFORM_PSUBW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PSUBW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PSWAPD_MMXq_MEMq, + INTRINSIC_XED_IFORM_PSWAPD_MMXq_MMXq, + INTRINSIC_XED_IFORM_PTEST_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PTEST_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_PTWRITE_GPRy, + INTRINSIC_XED_IFORM_PTWRITE_MEMy, + INTRINSIC_XED_IFORM_PUNPCKHBW_MMXq_MEMq, + INTRINSIC_XED_IFORM_PUNPCKHBW_MMXq_MMXd, + INTRINSIC_XED_IFORM_PUNPCKHBW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PUNPCKHBW_XMMdq_XMMq, + INTRINSIC_XED_IFORM_PUNPCKHDQ_MMXq_MEMq, + INTRINSIC_XED_IFORM_PUNPCKHDQ_MMXq_MMXd, + INTRINSIC_XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PUNPCKHDQ_XMMdq_XMMq, + INTRINSIC_XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq, + INTRINSIC_XED_IFORM_PUNPCKHWD_MMXq_MEMq, + INTRINSIC_XED_IFORM_PUNPCKHWD_MMXq_MMXd, + INTRINSIC_XED_IFORM_PUNPCKHWD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PUNPCKHWD_XMMdq_XMMq, + INTRINSIC_XED_IFORM_PUNPCKLBW_MMXq_MEMd, + INTRINSIC_XED_IFORM_PUNPCKLBW_MMXq_MMXd, + INTRINSIC_XED_IFORM_PUNPCKLBW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PUNPCKLBW_XMMdq_XMMq, + INTRINSIC_XED_IFORM_PUNPCKLDQ_MMXq_MEMd, + INTRINSIC_XED_IFORM_PUNPCKLDQ_MMXq_MMXd, + INTRINSIC_XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PUNPCKLDQ_XMMdq_XMMq, + INTRINSIC_XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq, + INTRINSIC_XED_IFORM_PUNPCKLWD_MMXq_MEMd, + INTRINSIC_XED_IFORM_PUNPCKLWD_MMXq_MMXd, + INTRINSIC_XED_IFORM_PUNPCKLWD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PUNPCKLWD_XMMdq_XMMq, + INTRINSIC_XED_IFORM_PUSH_CS, + INTRINSIC_XED_IFORM_PUSH_DS, + INTRINSIC_XED_IFORM_PUSH_ES, + INTRINSIC_XED_IFORM_PUSH_FS, + INTRINSIC_XED_IFORM_PUSH_GPRv_50, + INTRINSIC_XED_IFORM_PUSH_GPRv_FFr6, + INTRINSIC_XED_IFORM_PUSH_GS, + INTRINSIC_XED_IFORM_PUSH_IMMb, + INTRINSIC_XED_IFORM_PUSH_IMMz, + INTRINSIC_XED_IFORM_PUSH_MEMv, + INTRINSIC_XED_IFORM_PUSH_SS, + INTRINSIC_XED_IFORM_PUSHA, + INTRINSIC_XED_IFORM_PUSHAD, + INTRINSIC_XED_IFORM_PUSHF, + INTRINSIC_XED_IFORM_PUSHFD, + INTRINSIC_XED_IFORM_PUSHFQ, + INTRINSIC_XED_IFORM_PVALIDATE_RAX_ECX_EDX, + INTRINSIC_XED_IFORM_PXOR_MMXq_MEMq, + INTRINSIC_XED_IFORM_PXOR_MMXq_MMXq, + INTRINSIC_XED_IFORM_PXOR_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_PXOR_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_RCL_GPR8_CL, + INTRINSIC_XED_IFORM_RCL_GPR8_IMMb, + INTRINSIC_XED_IFORM_RCL_GPR8_ONE, + INTRINSIC_XED_IFORM_RCL_GPRv_CL, + INTRINSIC_XED_IFORM_RCL_GPRv_IMMb, + INTRINSIC_XED_IFORM_RCL_GPRv_ONE, + INTRINSIC_XED_IFORM_RCL_MEMb_CL, + INTRINSIC_XED_IFORM_RCL_MEMb_IMMb, + INTRINSIC_XED_IFORM_RCL_MEMb_ONE, + INTRINSIC_XED_IFORM_RCL_MEMv_CL, + INTRINSIC_XED_IFORM_RCL_MEMv_IMMb, + INTRINSIC_XED_IFORM_RCL_MEMv_ONE, + INTRINSIC_XED_IFORM_RCPPS_XMMps_MEMps, + INTRINSIC_XED_IFORM_RCPPS_XMMps_XMMps, + INTRINSIC_XED_IFORM_RCPSS_XMMss_MEMss, + INTRINSIC_XED_IFORM_RCPSS_XMMss_XMMss, + INTRINSIC_XED_IFORM_RCR_GPR8_CL, + INTRINSIC_XED_IFORM_RCR_GPR8_IMMb, + INTRINSIC_XED_IFORM_RCR_GPR8_ONE, + INTRINSIC_XED_IFORM_RCR_GPRv_CL, + INTRINSIC_XED_IFORM_RCR_GPRv_IMMb, + INTRINSIC_XED_IFORM_RCR_GPRv_ONE, + INTRINSIC_XED_IFORM_RCR_MEMb_CL, + INTRINSIC_XED_IFORM_RCR_MEMb_IMMb, + INTRINSIC_XED_IFORM_RCR_MEMb_ONE, + INTRINSIC_XED_IFORM_RCR_MEMv_CL, + INTRINSIC_XED_IFORM_RCR_MEMv_IMMb, + INTRINSIC_XED_IFORM_RCR_MEMv_ONE, + INTRINSIC_XED_IFORM_RDFSBASE_GPRy, + INTRINSIC_XED_IFORM_RDGSBASE_GPRy, + INTRINSIC_XED_IFORM_RDMSR, + INTRINSIC_XED_IFORM_RDPID_GPR32u32, + INTRINSIC_XED_IFORM_RDPID_GPR64u64, + INTRINSIC_XED_IFORM_RDPKRU, + INTRINSIC_XED_IFORM_RDPMC, + INTRINSIC_XED_IFORM_RDPRU, + INTRINSIC_XED_IFORM_RDRAND_GPRv, + INTRINSIC_XED_IFORM_RDSEED_GPRv, + INTRINSIC_XED_IFORM_RDSSPD_GPR32u32, + INTRINSIC_XED_IFORM_RDSSPQ_GPR64u64, + INTRINSIC_XED_IFORM_RDTSC, + INTRINSIC_XED_IFORM_RDTSCP, + INTRINSIC_XED_IFORM_REPE_CMPSB, + INTRINSIC_XED_IFORM_REPE_CMPSD, + INTRINSIC_XED_IFORM_REPE_CMPSQ, + INTRINSIC_XED_IFORM_REPE_CMPSW, + INTRINSIC_XED_IFORM_REPE_SCASB, + INTRINSIC_XED_IFORM_REPE_SCASD, + INTRINSIC_XED_IFORM_REPE_SCASQ, + INTRINSIC_XED_IFORM_REPE_SCASW, + INTRINSIC_XED_IFORM_REPNE_CMPSB, + INTRINSIC_XED_IFORM_REPNE_CMPSD, + INTRINSIC_XED_IFORM_REPNE_CMPSQ, + INTRINSIC_XED_IFORM_REPNE_CMPSW, + INTRINSIC_XED_IFORM_REPNE_SCASB, + INTRINSIC_XED_IFORM_REPNE_SCASD, + INTRINSIC_XED_IFORM_REPNE_SCASQ, + INTRINSIC_XED_IFORM_REPNE_SCASW, + INTRINSIC_XED_IFORM_REP_INSB, + INTRINSIC_XED_IFORM_REP_INSD, + INTRINSIC_XED_IFORM_REP_INSW, + INTRINSIC_XED_IFORM_REP_LODSB, + INTRINSIC_XED_IFORM_REP_LODSD, + INTRINSIC_XED_IFORM_REP_LODSQ, + INTRINSIC_XED_IFORM_REP_LODSW, + INTRINSIC_XED_IFORM_REP_MONTMUL, + INTRINSIC_XED_IFORM_REP_MOVSB, + INTRINSIC_XED_IFORM_REP_MOVSD, + INTRINSIC_XED_IFORM_REP_MOVSQ, + INTRINSIC_XED_IFORM_REP_MOVSW, + INTRINSIC_XED_IFORM_REP_OUTSB, + INTRINSIC_XED_IFORM_REP_OUTSD, + INTRINSIC_XED_IFORM_REP_OUTSW, + INTRINSIC_XED_IFORM_REP_STOSB, + INTRINSIC_XED_IFORM_REP_STOSD, + INTRINSIC_XED_IFORM_REP_STOSQ, + INTRINSIC_XED_IFORM_REP_STOSW, + INTRINSIC_XED_IFORM_REP_XCRYPTCBC, + INTRINSIC_XED_IFORM_REP_XCRYPTCFB, + INTRINSIC_XED_IFORM_REP_XCRYPTCTR, + INTRINSIC_XED_IFORM_REP_XCRYPTECB, + INTRINSIC_XED_IFORM_REP_XCRYPTOFB, + INTRINSIC_XED_IFORM_REP_XSHA1, + INTRINSIC_XED_IFORM_REP_XSHA256, + INTRINSIC_XED_IFORM_REP_XSTORE, + INTRINSIC_XED_IFORM_RET_FAR, + INTRINSIC_XED_IFORM_RET_FAR_IMMw, + INTRINSIC_XED_IFORM_RET_NEAR, + INTRINSIC_XED_IFORM_RET_NEAR_IMMw, + INTRINSIC_XED_IFORM_RMPADJUST_RAX_RCX_RDX, + INTRINSIC_XED_IFORM_RMPUPDATE_RAX_RCX, + INTRINSIC_XED_IFORM_ROL_GPR8_CL, + INTRINSIC_XED_IFORM_ROL_GPR8_IMMb, + INTRINSIC_XED_IFORM_ROL_GPR8_ONE, + INTRINSIC_XED_IFORM_ROL_GPRv_CL, + INTRINSIC_XED_IFORM_ROL_GPRv_IMMb, + INTRINSIC_XED_IFORM_ROL_GPRv_ONE, + INTRINSIC_XED_IFORM_ROL_MEMb_CL, + INTRINSIC_XED_IFORM_ROL_MEMb_IMMb, + INTRINSIC_XED_IFORM_ROL_MEMb_ONE, + INTRINSIC_XED_IFORM_ROL_MEMv_CL, + INTRINSIC_XED_IFORM_ROL_MEMv_IMMb, + INTRINSIC_XED_IFORM_ROL_MEMv_ONE, + INTRINSIC_XED_IFORM_ROR_GPR8_CL, + INTRINSIC_XED_IFORM_ROR_GPR8_IMMb, + INTRINSIC_XED_IFORM_ROR_GPR8_ONE, + INTRINSIC_XED_IFORM_ROR_GPRv_CL, + INTRINSIC_XED_IFORM_ROR_GPRv_IMMb, + INTRINSIC_XED_IFORM_ROR_GPRv_ONE, + INTRINSIC_XED_IFORM_ROR_MEMb_CL, + INTRINSIC_XED_IFORM_ROR_MEMb_IMMb, + INTRINSIC_XED_IFORM_ROR_MEMb_ONE, + INTRINSIC_XED_IFORM_ROR_MEMv_CL, + INTRINSIC_XED_IFORM_ROR_MEMv_IMMb, + INTRINSIC_XED_IFORM_ROR_MEMv_ONE, + INTRINSIC_XED_IFORM_RORX_VGPR32d_MEMd_IMMb, + INTRINSIC_XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb, + INTRINSIC_XED_IFORM_RORX_VGPR64q_MEMq_IMMb, + INTRINSIC_XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb, + INTRINSIC_XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb, + INTRINSIC_XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb, + INTRINSIC_XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb, + INTRINSIC_XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb, + INTRINSIC_XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb, + INTRINSIC_XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb, + INTRINSIC_XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb, + INTRINSIC_XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb, + INTRINSIC_XED_IFORM_RSM, + INTRINSIC_XED_IFORM_RSQRTPS_XMMps_MEMps, + INTRINSIC_XED_IFORM_RSQRTPS_XMMps_XMMps, + INTRINSIC_XED_IFORM_RSQRTSS_XMMss_MEMss, + INTRINSIC_XED_IFORM_RSQRTSS_XMMss_XMMss, + INTRINSIC_XED_IFORM_RSTORSSP_MEMu64, + INTRINSIC_XED_IFORM_SAHF, + INTRINSIC_XED_IFORM_SALC, + INTRINSIC_XED_IFORM_SAR_GPR8_CL, + INTRINSIC_XED_IFORM_SAR_GPR8_IMMb, + INTRINSIC_XED_IFORM_SAR_GPR8_ONE, + INTRINSIC_XED_IFORM_SAR_GPRv_CL, + INTRINSIC_XED_IFORM_SAR_GPRv_IMMb, + INTRINSIC_XED_IFORM_SAR_GPRv_ONE, + INTRINSIC_XED_IFORM_SAR_MEMb_CL, + INTRINSIC_XED_IFORM_SAR_MEMb_IMMb, + INTRINSIC_XED_IFORM_SAR_MEMb_ONE, + INTRINSIC_XED_IFORM_SAR_MEMv_CL, + INTRINSIC_XED_IFORM_SAR_MEMv_IMMb, + INTRINSIC_XED_IFORM_SAR_MEMv_ONE, + INTRINSIC_XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d, + INTRINSIC_XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d, + INTRINSIC_XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q, + INTRINSIC_XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q, + INTRINSIC_XED_IFORM_SAVEPREVSSP, + INTRINSIC_XED_IFORM_SBB_AL_IMMb, + INTRINSIC_XED_IFORM_SBB_GPR8_GPR8_18, + INTRINSIC_XED_IFORM_SBB_GPR8_GPR8_1A, + INTRINSIC_XED_IFORM_SBB_GPR8_IMMb_80r3, + INTRINSIC_XED_IFORM_SBB_GPR8_IMMb_82r3, + INTRINSIC_XED_IFORM_SBB_GPR8_MEMb, + INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_19, + INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_1B, + INTRINSIC_XED_IFORM_SBB_GPRv_IMMb, + INTRINSIC_XED_IFORM_SBB_GPRv_IMMz, + INTRINSIC_XED_IFORM_SBB_GPRv_MEMv, + INTRINSIC_XED_IFORM_SBB_MEMb_GPR8, + INTRINSIC_XED_IFORM_SBB_MEMb_IMMb_80r3, + INTRINSIC_XED_IFORM_SBB_MEMb_IMMb_82r3, + INTRINSIC_XED_IFORM_SBB_MEMv_GPRv, + INTRINSIC_XED_IFORM_SBB_MEMv_IMMb, + INTRINSIC_XED_IFORM_SBB_MEMv_IMMz, + INTRINSIC_XED_IFORM_SBB_OrAX_IMMz, + INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_GPR8, + INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3, + INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3, + INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_GPRv, + INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_IMMb, + INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_IMMz, + INTRINSIC_XED_IFORM_SCASB, + INTRINSIC_XED_IFORM_SCASD, + INTRINSIC_XED_IFORM_SCASQ, + INTRINSIC_XED_IFORM_SCASW, + INTRINSIC_XED_IFORM_SERIALIZE, + INTRINSIC_XED_IFORM_SETB_GPR8, + INTRINSIC_XED_IFORM_SETB_MEMb, + INTRINSIC_XED_IFORM_SETBE_GPR8, + INTRINSIC_XED_IFORM_SETBE_MEMb, + INTRINSIC_XED_IFORM_SETL_GPR8, + INTRINSIC_XED_IFORM_SETL_MEMb, + INTRINSIC_XED_IFORM_SETLE_GPR8, + INTRINSIC_XED_IFORM_SETLE_MEMb, + INTRINSIC_XED_IFORM_SETNB_GPR8, + INTRINSIC_XED_IFORM_SETNB_MEMb, + INTRINSIC_XED_IFORM_SETNBE_GPR8, + INTRINSIC_XED_IFORM_SETNBE_MEMb, + INTRINSIC_XED_IFORM_SETNL_GPR8, + INTRINSIC_XED_IFORM_SETNL_MEMb, + INTRINSIC_XED_IFORM_SETNLE_GPR8, + INTRINSIC_XED_IFORM_SETNLE_MEMb, + INTRINSIC_XED_IFORM_SETNO_GPR8, + INTRINSIC_XED_IFORM_SETNO_MEMb, + INTRINSIC_XED_IFORM_SETNP_GPR8, + INTRINSIC_XED_IFORM_SETNP_MEMb, + INTRINSIC_XED_IFORM_SETNS_GPR8, + INTRINSIC_XED_IFORM_SETNS_MEMb, + INTRINSIC_XED_IFORM_SETNZ_GPR8, + INTRINSIC_XED_IFORM_SETNZ_MEMb, + INTRINSIC_XED_IFORM_SETO_GPR8, + INTRINSIC_XED_IFORM_SETO_MEMb, + INTRINSIC_XED_IFORM_SETP_GPR8, + INTRINSIC_XED_IFORM_SETP_MEMb, + INTRINSIC_XED_IFORM_SETS_GPR8, + INTRINSIC_XED_IFORM_SETS_MEMb, + INTRINSIC_XED_IFORM_SETSSBSY, + INTRINSIC_XED_IFORM_SETZ_GPR8, + INTRINSIC_XED_IFORM_SETZ_MEMb, + INTRINSIC_XED_IFORM_SFENCE, + INTRINSIC_XED_IFORM_SGDT_MEMs, + INTRINSIC_XED_IFORM_SGDT_MEMs64, + INTRINSIC_XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA, + INTRINSIC_XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA, + INTRINSIC_XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA, + INTRINSIC_XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA, + INTRINSIC_XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA, + INTRINSIC_XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA, + INTRINSIC_XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA, + INTRINSIC_XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA, + INTRINSIC_XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA, + INTRINSIC_XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA, + INTRINSIC_XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA, + INTRINSIC_XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA, + INTRINSIC_XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA, + INTRINSIC_XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA, + INTRINSIC_XED_IFORM_SHL_GPR8_CL_D2r4, + INTRINSIC_XED_IFORM_SHL_GPR8_CL_D2r6, + INTRINSIC_XED_IFORM_SHL_GPR8_IMMb_C0r4, + INTRINSIC_XED_IFORM_SHL_GPR8_IMMb_C0r6, + INTRINSIC_XED_IFORM_SHL_GPR8_ONE_D0r4, + INTRINSIC_XED_IFORM_SHL_GPR8_ONE_D0r6, + INTRINSIC_XED_IFORM_SHL_GPRv_CL_D3r4, + INTRINSIC_XED_IFORM_SHL_GPRv_CL_D3r6, + INTRINSIC_XED_IFORM_SHL_GPRv_IMMb_C1r4, + INTRINSIC_XED_IFORM_SHL_GPRv_IMMb_C1r6, + INTRINSIC_XED_IFORM_SHL_GPRv_ONE_D1r4, + INTRINSIC_XED_IFORM_SHL_GPRv_ONE_D1r6, + INTRINSIC_XED_IFORM_SHL_MEMb_CL_D2r4, + INTRINSIC_XED_IFORM_SHL_MEMb_CL_D2r6, + INTRINSIC_XED_IFORM_SHL_MEMb_IMMb_C0r4, + INTRINSIC_XED_IFORM_SHL_MEMb_IMMb_C0r6, + INTRINSIC_XED_IFORM_SHL_MEMb_ONE_D0r4, + INTRINSIC_XED_IFORM_SHL_MEMb_ONE_D0r6, + INTRINSIC_XED_IFORM_SHL_MEMv_CL_D3r4, + INTRINSIC_XED_IFORM_SHL_MEMv_CL_D3r6, + INTRINSIC_XED_IFORM_SHL_MEMv_IMMb_C1r4, + INTRINSIC_XED_IFORM_SHL_MEMv_IMMb_C1r6, + INTRINSIC_XED_IFORM_SHL_MEMv_ONE_D1r4, + INTRINSIC_XED_IFORM_SHL_MEMv_ONE_D1r6, + INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_CL, + INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_IMMb, + INTRINSIC_XED_IFORM_SHLD_MEMv_GPRv_CL, + INTRINSIC_XED_IFORM_SHLD_MEMv_GPRv_IMMb, + INTRINSIC_XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d, + INTRINSIC_XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d, + INTRINSIC_XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q, + INTRINSIC_XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q, + INTRINSIC_XED_IFORM_SHR_GPR8_CL, + INTRINSIC_XED_IFORM_SHR_GPR8_IMMb, + INTRINSIC_XED_IFORM_SHR_GPR8_ONE, + INTRINSIC_XED_IFORM_SHR_GPRv_CL, + INTRINSIC_XED_IFORM_SHR_GPRv_IMMb, + INTRINSIC_XED_IFORM_SHR_GPRv_ONE, + INTRINSIC_XED_IFORM_SHR_MEMb_CL, + INTRINSIC_XED_IFORM_SHR_MEMb_IMMb, + INTRINSIC_XED_IFORM_SHR_MEMb_ONE, + INTRINSIC_XED_IFORM_SHR_MEMv_CL, + INTRINSIC_XED_IFORM_SHR_MEMv_IMMb, + INTRINSIC_XED_IFORM_SHR_MEMv_ONE, + INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_CL, + INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_IMMb, + INTRINSIC_XED_IFORM_SHRD_MEMv_GPRv_CL, + INTRINSIC_XED_IFORM_SHRD_MEMv_GPRv_IMMb, + INTRINSIC_XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d, + INTRINSIC_XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d, + INTRINSIC_XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q, + INTRINSIC_XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q, + INTRINSIC_XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb, + INTRINSIC_XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb, + INTRINSIC_XED_IFORM_SHUFPS_XMMps_MEMps_IMMb, + INTRINSIC_XED_IFORM_SHUFPS_XMMps_XMMps_IMMb, + INTRINSIC_XED_IFORM_SIDT_MEMs, + INTRINSIC_XED_IFORM_SIDT_MEMs64, + INTRINSIC_XED_IFORM_SKINIT_EAX, + INTRINSIC_XED_IFORM_SLDT_GPRv, + INTRINSIC_XED_IFORM_SLDT_MEMw, + INTRINSIC_XED_IFORM_SLWPCB_GPRyy, + INTRINSIC_XED_IFORM_SMSW_GPRv, + INTRINSIC_XED_IFORM_SMSW_MEMw, + INTRINSIC_XED_IFORM_SQRTPD_XMMpd_MEMpd, + INTRINSIC_XED_IFORM_SQRTPD_XMMpd_XMMpd, + INTRINSIC_XED_IFORM_SQRTPS_XMMps_MEMps, + INTRINSIC_XED_IFORM_SQRTPS_XMMps_XMMps, + INTRINSIC_XED_IFORM_SQRTSD_XMMsd_MEMsd, + INTRINSIC_XED_IFORM_SQRTSD_XMMsd_XMMsd, + INTRINSIC_XED_IFORM_SQRTSS_XMMss_MEMss, + INTRINSIC_XED_IFORM_SQRTSS_XMMss_XMMss, + INTRINSIC_XED_IFORM_STAC, + INTRINSIC_XED_IFORM_STC, + INTRINSIC_XED_IFORM_STD, + INTRINSIC_XED_IFORM_STGI, + INTRINSIC_XED_IFORM_STI, + INTRINSIC_XED_IFORM_STMXCSR_MEMd, + INTRINSIC_XED_IFORM_STOSB, + INTRINSIC_XED_IFORM_STOSD, + INTRINSIC_XED_IFORM_STOSQ, + INTRINSIC_XED_IFORM_STOSW, + INTRINSIC_XED_IFORM_STR_GPRv, + INTRINSIC_XED_IFORM_STR_MEMw, + INTRINSIC_XED_IFORM_SUB_AL_IMMb, + INTRINSIC_XED_IFORM_SUB_GPR8_GPR8_28, + INTRINSIC_XED_IFORM_SUB_GPR8_GPR8_2A, + INTRINSIC_XED_IFORM_SUB_GPR8_IMMb_80r5, + INTRINSIC_XED_IFORM_SUB_GPR8_IMMb_82r5, + INTRINSIC_XED_IFORM_SUB_GPR8_MEMb, + INTRINSIC_XED_IFORM_SUB_GPRv_GPRv_29, + INTRINSIC_XED_IFORM_SUB_GPRv_GPRv_2B, + INTRINSIC_XED_IFORM_SUB_GPRv_IMMb, + INTRINSIC_XED_IFORM_SUB_GPRv_IMMz, + INTRINSIC_XED_IFORM_SUB_GPRv_MEMv, + INTRINSIC_XED_IFORM_SUB_MEMb_GPR8, + INTRINSIC_XED_IFORM_SUB_MEMb_IMMb_80r5, + INTRINSIC_XED_IFORM_SUB_MEMb_IMMb_82r5, + INTRINSIC_XED_IFORM_SUB_MEMv_GPRv, + INTRINSIC_XED_IFORM_SUB_MEMv_IMMb, + INTRINSIC_XED_IFORM_SUB_MEMv_IMMz, + INTRINSIC_XED_IFORM_SUB_OrAX_IMMz, + INTRINSIC_XED_IFORM_SUBPD_XMMpd_MEMpd, + INTRINSIC_XED_IFORM_SUBPD_XMMpd_XMMpd, + INTRINSIC_XED_IFORM_SUBPS_XMMps_MEMps, + INTRINSIC_XED_IFORM_SUBPS_XMMps_XMMps, + INTRINSIC_XED_IFORM_SUBSD_XMMsd_MEMsd, + INTRINSIC_XED_IFORM_SUBSD_XMMsd_XMMsd, + INTRINSIC_XED_IFORM_SUBSS_XMMss_MEMss, + INTRINSIC_XED_IFORM_SUBSS_XMMss_XMMss, + INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_GPR8, + INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5, + INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5, + INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_GPRv, + INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_IMMb, + INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_IMMz, + INTRINSIC_XED_IFORM_SWAPGS, + INTRINSIC_XED_IFORM_SYSCALL, + INTRINSIC_XED_IFORM_SYSCALL_AMD, + INTRINSIC_XED_IFORM_SYSENTER, + INTRINSIC_XED_IFORM_SYSEXIT, + INTRINSIC_XED_IFORM_SYSRET, + INTRINSIC_XED_IFORM_SYSRET64, + INTRINSIC_XED_IFORM_SYSRET_AMD, + INTRINSIC_XED_IFORM_T1MSKC_VGPR32d_GPR32d, + INTRINSIC_XED_IFORM_T1MSKC_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_T1MSKC_VGPRyy_GPRyy, + INTRINSIC_XED_IFORM_T1MSKC_VGPRyy_MEMy, + INTRINSIC_XED_IFORM_TEST_AL_IMMb, + INTRINSIC_XED_IFORM_TEST_GPR8_GPR8, + INTRINSIC_XED_IFORM_TEST_GPR8_IMMb_F6r0, + INTRINSIC_XED_IFORM_TEST_GPR8_IMMb_F6r1, + INTRINSIC_XED_IFORM_TEST_GPRv_GPRv, + INTRINSIC_XED_IFORM_TEST_GPRv_IMMz_F7r0, + INTRINSIC_XED_IFORM_TEST_GPRv_IMMz_F7r1, + INTRINSIC_XED_IFORM_TEST_MEMb_GPR8, + INTRINSIC_XED_IFORM_TEST_MEMb_IMMb_F6r0, + INTRINSIC_XED_IFORM_TEST_MEMb_IMMb_F6r1, + INTRINSIC_XED_IFORM_TEST_MEMv_GPRv, + INTRINSIC_XED_IFORM_TEST_MEMv_IMMz_F7r0, + INTRINSIC_XED_IFORM_TEST_MEMv_IMMz_F7r1, + INTRINSIC_XED_IFORM_TEST_OrAX_IMMz, + INTRINSIC_XED_IFORM_TPAUSE_GPR32u32, + INTRINSIC_XED_IFORM_TPAUSE_GPR64u64, + INTRINSIC_XED_IFORM_TZCNT_GPRv_GPRv, + INTRINSIC_XED_IFORM_TZCNT_GPRv_MEMv, + INTRINSIC_XED_IFORM_TZMSK_VGPR32d_GPR32d, + INTRINSIC_XED_IFORM_TZMSK_VGPR32d_MEMd, + INTRINSIC_XED_IFORM_TZMSK_VGPRyy_GPRyy, + INTRINSIC_XED_IFORM_TZMSK_VGPRyy_MEMy, + INTRINSIC_XED_IFORM_UCOMISD_XMMsd_MEMsd, + INTRINSIC_XED_IFORM_UCOMISD_XMMsd_XMMsd, + INTRINSIC_XED_IFORM_UCOMISS_XMMss_MEMss, + INTRINSIC_XED_IFORM_UCOMISS_XMMss_XMMss, + INTRINSIC_XED_IFORM_UD0_GPR32_GPR32, + INTRINSIC_XED_IFORM_UD0_GPR32_MEMd, + INTRINSIC_XED_IFORM_UD1_GPR32_GPR32, + INTRINSIC_XED_IFORM_UD1_GPR32_MEMd, + INTRINSIC_XED_IFORM_UD2, + INTRINSIC_XED_IFORM_UMONITOR_GPRa, + INTRINSIC_XED_IFORM_UMWAIT_GPR32, + INTRINSIC_XED_IFORM_UMWAIT_GPR64, + INTRINSIC_XED_IFORM_UNPCKHPD_XMMpd_MEMdq, + INTRINSIC_XED_IFORM_UNPCKHPD_XMMpd_XMMq, + INTRINSIC_XED_IFORM_UNPCKHPS_XMMps_MEMdq, + INTRINSIC_XED_IFORM_UNPCKHPS_XMMps_XMMdq, + INTRINSIC_XED_IFORM_UNPCKLPD_XMMpd_MEMdq, + INTRINSIC_XED_IFORM_UNPCKLPD_XMMpd_XMMq, + INTRINSIC_XED_IFORM_UNPCKLPS_XMMps_MEMdq, + INTRINSIC_XED_IFORM_UNPCKLPS_XMMps_XMMq, + INTRINSIC_XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512, + INTRINSIC_XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512, + INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128, + INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512, + INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128, + INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512, + INTRINSIC_XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512, + INTRINSIC_XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512, + INTRINSIC_XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512, + INTRINSIC_XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512, + INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128, + INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512, + INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128, + INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512, + INTRINSIC_XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512, + INTRINSIC_XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512, + INTRINSIC_XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512, + INTRINSIC_XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512, + INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128, + INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512, + INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128, + INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512, + INTRINSIC_XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512, + INTRINSIC_XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512, + INTRINSIC_XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512, + INTRINSIC_XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512, + INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128, + INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512, + INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128, + INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512, + INTRINSIC_XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512, + INTRINSIC_XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512, + INTRINSIC_XED_IFORM_VAESIMC_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VAESIMC_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VBROADCASTF128_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTI128_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTSD_YMMqq_MEMq, + INTRINSIC_XED_IFORM_VBROADCASTSD_YMMqq_XMMdq, + INTRINSIC_XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTSS_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VBROADCASTSS_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTSS_YMMqq_MEMd, + INTRINSIC_XED_IFORM_VBROADCASTSS_YMMqq_XMMdq, + INTRINSIC_XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb, + INTRINSIC_XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb, + INTRINSIC_XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb, + INTRINSIC_XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb, + INTRINSIC_XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCOMISD_XMMq_MEMq, + INTRINSIC_XED_IFORM_VCOMISD_XMMq_XMMq, + INTRINSIC_XED_IFORM_VCOMISS_XMMd_MEMd, + INTRINSIC_XED_IFORM_VCOMISS_XMMd_XMMd, + INTRINSIC_XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq, + INTRINSIC_XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512, + INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512, + INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, + INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq, + INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq, + INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_MEMqq, + INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_YMMqq, + INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTPH2PS_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VCVTPH2PS_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512, + INTRINSIC_XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512, + INTRINSIC_XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512, + INTRINSIC_XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512, + INTRINSIC_XED_IFORM_VCVTPH2PS_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VCVTPH2PS_YMMqq_XMMdq, + INTRINSIC_XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512, + INTRINSIC_XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2PD_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VCVTPS2PD_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2PD_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VCVTPS2PD_YMMqq_XMMdq, + INTRINSIC_XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32d_MEMq, + INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32d_XMMq, + INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64q_MEMq, + INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64q_XMMq, + INTRINSIC_XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d, + INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q, + INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512, + INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512, + INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512, + INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d, + INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q, + INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, + INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512, + INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512, + INTRINSIC_XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32d_MEMd, + INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32d_XMMd, + INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64q_MEMd, + INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64q_XMMd, + INTRINSIC_XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq, + INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq, + INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32d_MEMq, + INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32d_XMMq, + INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64q_MEMq, + INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64q_XMMq, + INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32d_MEMd, + INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32d_XMMd, + INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64q_MEMd, + INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64q_XMMd, + INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128, + INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256, + INTRINSIC_XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, + INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512, + INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512, + INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, + INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512, + INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VERR_GPR16, + INTRINSIC_XED_IFORM_VERR_MEMw, + INTRINSIC_XED_IFORM_VERW_GPR16, + INTRINSIC_XED_IFORM_VERW_MEMw, + INTRINSIC_XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, + INTRINSIC_XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, + INTRINSIC_XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, + INTRINSIC_XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, + INTRINSIC_XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb, + INTRINSIC_XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb, + INTRINSIC_XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq, + INTRINSIC_XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd, + INTRINSIC_XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq, + INTRINSIC_XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd, + INTRINSIC_XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq, + INTRINSIC_XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd, + INTRINSIC_XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq, + INTRINSIC_XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd, + INTRINSIC_XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd, + INTRINSIC_XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd, + INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128, + INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256, + INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512, + INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128, + INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256, + INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512, + INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VFRCZPD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFRCZPD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFRCZPD_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFRCZPD_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFRCZPS_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VFRCZPS_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VFRCZPS_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VFRCZPS_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VFRCZSD_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VFRCZSD_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VFRCZSS_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VFRCZSS_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128, + INTRINSIC_XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128, + INTRINSIC_XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256, + INTRINSIC_XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256, + INTRINSIC_XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512, + INTRINSIC_XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128, + INTRINSIC_XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128, + INTRINSIC_XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256, + INTRINSIC_XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256, + INTRINSIC_XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512, + INTRINSIC_XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128, + INTRINSIC_XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128, + INTRINSIC_XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256, + INTRINSIC_XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256, + INTRINSIC_XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512, + INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128, + INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256, + INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128, + INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256, + INTRINSIC_XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512, + INTRINSIC_XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8, + INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8, + INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8, + INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8, + INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8, + INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8, + INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8, + INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8, + INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8, + INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8, + INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8, + INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8, + INTRINSIC_XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb, + INTRINSIC_XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VLDDQU_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VLDDQU_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VLDMXCSR_MEMd, + INTRINSIC_XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMCALL, + INTRINSIC_XED_IFORM_VMCLEAR_MEMq, + INTRINSIC_XED_IFORM_VMFUNC, + INTRINSIC_XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMLAUNCH, + INTRINSIC_XED_IFORM_VMLOAD_ArAX, + INTRINSIC_XED_IFORM_VMMCALL, + INTRINSIC_XED_IFORM_VMOVAPD_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVAPD_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VMOVAPD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMOVAPD_XMMdq_XMMdq_28, + INTRINSIC_XED_IFORM_VMOVAPD_XMMdq_XMMdq_29, + INTRINSIC_XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_YMMqq_28, + INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_YMMqq_29, + INTRINSIC_XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVAPS_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVAPS_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VMOVAPS_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMOVAPS_XMMdq_XMMdq_28, + INTRINSIC_XED_IFORM_VMOVAPS_XMMdq_XMMdq_29, + INTRINSIC_XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_YMMqq_28, + INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_YMMqq_29, + INTRINSIC_XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVD_GPR32d_XMMd, + INTRINSIC_XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVD_MEMd_XMMd, + INTRINSIC_XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVD_XMMdq_GPR32d, + INTRINSIC_XED_IFORM_VMOVD_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512, + INTRINSIC_XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDDUP_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VMOVDDUP_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVDDUP_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMOVDDUP_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VMOVDQA_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VMOVDQA_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F, + INTRINSIC_XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F, + INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F, + INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F, + INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VMOVDQU_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VMOVDQU_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F, + INTRINSIC_XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F, + INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F, + INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F, + INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVHPD_MEMq_XMMdq, + INTRINSIC_XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVHPS_MEMq_XMMdq, + INTRINSIC_XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq, + INTRINSIC_XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq, + INTRINSIC_XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVLPD_MEMq_XMMq, + INTRINSIC_XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVLPS_MEMq_XMMq, + INTRINSIC_XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVMSKPD_GPR32d_XMMdq, + INTRINSIC_XED_IFORM_VMOVMSKPD_GPR32d_YMMqq, + INTRINSIC_XED_IFORM_VMOVMSKPS_GPR32d_XMMdq, + INTRINSIC_XED_IFORM_VMOVMSKPS_GPR32d_YMMqq, + INTRINSIC_XED_IFORM_VMOVNTDQ_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VMOVNTDQ_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVNTDQA_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVNTDQA_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VMOVNTPD_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVNTPD_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VMOVNTPS_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVNTPS_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VMOVQ_GPR64q_XMMq, + INTRINSIC_XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVQ_MEMq_XMMq_7E, + INTRINSIC_XED_IFORM_VMOVQ_MEMq_XMMq_D6, + INTRINSIC_XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVQ_XMMdq_GPR64q, + INTRINSIC_XED_IFORM_VMOVQ_XMMdq_MEMq_6E, + INTRINSIC_XED_IFORM_VMOVQ_XMMdq_MEMq_7E, + INTRINSIC_XED_IFORM_VMOVQ_XMMdq_XMMq_7E, + INTRINSIC_XED_IFORM_VMOVQ_XMMdq_XMMq_D6, + INTRINSIC_XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512, + INTRINSIC_XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVSD_MEMq_XMMq, + INTRINSIC_XED_IFORM_VMOVSD_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10, + INTRINSIC_XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11, + INTRINSIC_XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVSHDUP_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMOVSHDUP_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVSHDUP_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMOVSHDUP_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVSLDUP_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMOVSLDUP_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVSLDUP_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMOVSLDUP_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVSS_MEMd_XMMd, + INTRINSIC_XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVSS_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10, + INTRINSIC_XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11, + INTRINSIC_XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVUPD_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVUPD_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VMOVUPD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMOVUPD_XMMdq_XMMdq_10, + INTRINSIC_XED_IFORM_VMOVUPD_XMMdq_XMMdq_11, + INTRINSIC_XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_YMMqq_10, + INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_YMMqq_11, + INTRINSIC_XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VMOVUPS_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVUPS_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VMOVUPS_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMOVUPS_XMMdq_XMMdq_10, + INTRINSIC_XED_IFORM_VMOVUPS_XMMdq_XMMdq_11, + INTRINSIC_XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_YMMqq_10, + INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_YMMqq_11, + INTRINSIC_XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VMPTRLD_MEMq, + INTRINSIC_XED_IFORM_VMPTRST_MEMq, + INTRINSIC_XED_IFORM_VMREAD_GPR32_GPR32, + INTRINSIC_XED_IFORM_VMREAD_GPR64_GPR64, + INTRINSIC_XED_IFORM_VMREAD_MEMd_GPR32, + INTRINSIC_XED_IFORM_VMREAD_MEMq_GPR64, + INTRINSIC_XED_IFORM_VMRESUME, + INTRINSIC_XED_IFORM_VMRUN_ArAX, + INTRINSIC_XED_IFORM_VMSAVE, + INTRINSIC_XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VMWRITE_GPR32_GPR32, + INTRINSIC_XED_IFORM_VMWRITE_GPR32_MEMd, + INTRINSIC_XED_IFORM_VMWRITE_GPR64_GPR64, + INTRINSIC_XED_IFORM_VMWRITE_GPR64_MEMq, + INTRINSIC_XED_IFORM_VMXOFF, + INTRINSIC_XED_IFORM_VMXON_MEMq, + INTRINSIC_XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPABSB_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPABSB_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512, + INTRINSIC_XED_IFORM_VPABSB_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPABSB_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512, + INTRINSIC_XED_IFORM_VPABSD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPABSD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512, + INTRINSIC_XED_IFORM_VPABSD_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPABSD_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512, + INTRINSIC_XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512, + INTRINSIC_XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512, + INTRINSIC_XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512, + INTRINSIC_XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512, + INTRINSIC_XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512, + INTRINSIC_XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512, + INTRINSIC_XED_IFORM_VPABSW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPABSW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512, + INTRINSIC_XED_IFORM_VPABSW_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPABSW_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512, + INTRINSIC_XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512, + INTRINSIC_XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512, + INTRINSIC_XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512, + INTRINSIC_XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512, + INTRINSIC_XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, + INTRINSIC_XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, + INTRINSIC_XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, + INTRINSIC_XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, + INTRINSIC_XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPBROADCASTB_XMMdq_MEMb, + INTRINSIC_XED_IFORM_VPBROADCASTB_XMMdq_XMMb, + INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTB_YMMqq_MEMb, + INTRINSIC_XED_IFORM_VPBROADCASTB_YMMqq_XMMb, + INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTD_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VPBROADCASTD_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTD_YMMqq_MEMd, + INTRINSIC_XED_IFORM_VPBROADCASTD_YMMqq_XMMd, + INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD, + INTRINSIC_XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD, + INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMqq_MEMq, + INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMqq_XMMq, + INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTW_XMMdq_MEMw, + INTRINSIC_XED_IFORM_VPBROADCASTW_XMMdq_XMMw, + INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTW_YMMqq_MEMw, + INTRINSIC_XED_IFORM_VPBROADCASTW_YMMqq_XMMw, + INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8, + INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8, + INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq, + INTRINSIC_XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD, + INTRINSIC_XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD, + INTRINSIC_XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD, + INTRINSIC_XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD, + INTRINSIC_XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15, + INTRINSIC_XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5, + INTRINSIC_XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5, + INTRINSIC_XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128, + INTRINSIC_XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128, + INTRINSIC_XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256, + INTRINSIC_XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256, + INTRINSIC_XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512, + INTRINSIC_XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128, + INTRINSIC_XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128, + INTRINSIC_XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256, + INTRINSIC_XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256, + INTRINSIC_XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512, + INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128, + INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256, + INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128, + INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256, + INTRINSIC_XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512, + INTRINSIC_XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128, + INTRINSIC_XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128, + INTRINSIC_XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256, + INTRINSIC_XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256, + INTRINSIC_XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512, + INTRINSIC_XED_IFORM_VPHADDBD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHADDBD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHADDBQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHADDBQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHADDBW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHADDBW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPHADDDQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHADDDQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPHADDUBD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHADDUBD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHADDUBQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHADDUBQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHADDUBW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHADDUBW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHADDUDQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHADDUDQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHADDUWD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHADDUWD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHADDUWQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHADDUWQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPHADDWD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHADDWD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHADDWQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHADDWQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHSUBBW_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHSUBBW_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPHSUBDQ_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHSUBDQ_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPHSUBWD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPHSUBWD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb, + INTRINSIC_XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb, + INTRINSIC_XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb, + INTRINSIC_XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb, + INTRINSIC_XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb, + INTRINSIC_XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb, + INTRINSIC_XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb, + INTRINSIC_XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb, + INTRINSIC_XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD, + INTRINSIC_XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD, + INTRINSIC_XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD, + INTRINSIC_XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD, + INTRINSIC_XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512, + INTRINSIC_XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512, + INTRINSIC_XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512, + INTRINSIC_XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512, + INTRINSIC_XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512, + INTRINSIC_XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512, + INTRINSIC_XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512, + INTRINSIC_XED_IFORM_VPMOVMSKB_GPR32d_XMMdq, + INTRINSIC_XED_IFORM_VPMOVMSKB_GPR32d_YMMqq, + INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512, + INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBD_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VPMOVSXBD_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBD_YMMqq_MEMq, + INTRINSIC_XED_IFORM_VPMOVSXBD_YMMqq_XMMq, + INTRINSIC_XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMdq_MEMw, + INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMdq_XMMw, + INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMqq_MEMd, + INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMqq_XMMd, + INTRINSIC_XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBW_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VPMOVSXBW_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBW_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VPMOVSXBW_YMMqq_XMMdq, + INTRINSIC_XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq, + INTRINSIC_XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXWD_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VPMOVSXWD_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXWD_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VPMOVSXWD_YMMqq_XMMdq, + INTRINSIC_XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMqq_MEMq, + INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMqq_XMMq, + INTRINSIC_XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBD_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VPMOVZXBD_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBD_YMMqq_MEMq, + INTRINSIC_XED_IFORM_VPMOVZXBD_YMMqq_XMMq, + INTRINSIC_XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMdq_MEMw, + INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMdq_XMMw, + INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMqq_MEMd, + INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMqq_XMMd, + INTRINSIC_XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBW_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VPMOVZXBW_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBW_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VPMOVZXBW_YMMqq_XMMdq, + INTRINSIC_XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq, + INTRINSIC_XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXWD_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VPMOVZXWD_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXWD_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VPMOVZXWD_YMMqq_XMMdq, + INTRINSIC_XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMqq_MEMq, + INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMqq_XMMq, + INTRINSIC_XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512, + INTRINSIC_XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512, + INTRINSIC_XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, + INTRINSIC_XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128, + INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256, + INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512, + INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128, + INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256, + INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512, + INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128, + INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256, + INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512, + INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128, + INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256, + INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512, + INTRINSIC_XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq, + INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq, + INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq, + INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq, + INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq, + INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq, + INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq, + INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq, + INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq, + INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, + INTRINSIC_XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, + INTRINSIC_XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, + INTRINSIC_XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, + INTRINSIC_XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, + INTRINSIC_XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, + INTRINSIC_XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, + INTRINSIC_XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, + INTRINSIC_XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VPTEST_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPTEST_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPTEST_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPTEST_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, + INTRINSIC_XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, + INTRINSIC_XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, + INTRINSIC_XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, + INTRINSIC_XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, + INTRINSIC_XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, + INTRINSIC_XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER, + INTRINSIC_XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER, + INTRINSIC_XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER, + INTRINSIC_XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER, + INTRINSIC_XED_IFORM_VRCPPS_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VRCPPS_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VRCPPS_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VRCPPS_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb, + INTRINSIC_XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb, + INTRINSIC_XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb, + INTRINSIC_XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb, + INTRINSIC_XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, + INTRINSIC_XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, + INTRINSIC_XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, + INTRINSIC_XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, + INTRINSIC_XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER, + INTRINSIC_XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER, + INTRINSIC_XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER, + INTRINSIC_XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER, + INTRINSIC_XED_IFORM_VRSQRTPS_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VRSQRTPS_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VRSQRTPS_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VRSQRTPS_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128, + INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256, + INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512, + INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128, + INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256, + INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512, + INTRINSIC_XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512, + INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128, + INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256, + INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512, + INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128, + INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256, + INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512, + INTRINSIC_XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb, + INTRINSIC_XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb, + INTRINSIC_XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb, + INTRINSIC_XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb, + INTRINSIC_XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, + INTRINSIC_XED_IFORM_VSQRTPD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VSQRTPD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VSQRTPD_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VSQRTPD_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VSQRTPS_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VSQRTPS_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VSQRTPS_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VSQRTPS_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VSTMXCSR_MEMd, + INTRINSIC_XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VTESTPD_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VTESTPD_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VTESTPD_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VTESTPD_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VTESTPS_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VTESTPS_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VTESTPS_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VTESTPS_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VUCOMISD_XMMdq_MEMq, + INTRINSIC_XED_IFORM_VUCOMISD_XMMdq_XMMq, + INTRINSIC_XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VUCOMISS_XMMdq_MEMd, + INTRINSIC_XED_IFORM_VUCOMISS_XMMdq_XMMd, + INTRINSIC_XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, + INTRINSIC_XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, + INTRINSIC_XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, + INTRINSIC_XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, + INTRINSIC_XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, + INTRINSIC_XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, + INTRINSIC_XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, + INTRINSIC_XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, + INTRINSIC_XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, + INTRINSIC_XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, + INTRINSIC_XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, + INTRINSIC_XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, + INTRINSIC_XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq, + INTRINSIC_XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq, + INTRINSIC_XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, + INTRINSIC_XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq, + INTRINSIC_XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq, + INTRINSIC_XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, + INTRINSIC_XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, + INTRINSIC_XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, + INTRINSIC_XED_IFORM_VZEROALL, + INTRINSIC_XED_IFORM_VZEROUPPER, + INTRINSIC_XED_IFORM_WBINVD, + INTRINSIC_XED_IFORM_WBNOINVD, + INTRINSIC_XED_IFORM_WRFSBASE_GPRy, + INTRINSIC_XED_IFORM_WRGSBASE_GPRy, + INTRINSIC_XED_IFORM_WRMSR, + INTRINSIC_XED_IFORM_WRPKRU, + INTRINSIC_XED_IFORM_WRSSD_MEMu32_GPR32u32, + INTRINSIC_XED_IFORM_WRSSQ_MEMu64_GPR64u64, + INTRINSIC_XED_IFORM_WRUSSD_MEMu32_GPR32u32, + INTRINSIC_XED_IFORM_WRUSSQ_MEMu64_GPR64u64, + INTRINSIC_XED_IFORM_XABORT_IMMb, + INTRINSIC_XED_IFORM_XADD_GPR8_GPR8, + INTRINSIC_XED_IFORM_XADD_GPRv_GPRv, + INTRINSIC_XED_IFORM_XADD_MEMb_GPR8, + INTRINSIC_XED_IFORM_XADD_MEMv_GPRv, + INTRINSIC_XED_IFORM_XADD_LOCK_MEMb_GPR8, + INTRINSIC_XED_IFORM_XADD_LOCK_MEMv_GPRv, + INTRINSIC_XED_IFORM_XBEGIN_RELBRz, + INTRINSIC_XED_IFORM_XCHG_GPR8_GPR8, + INTRINSIC_XED_IFORM_XCHG_GPRv_GPRv, + INTRINSIC_XED_IFORM_XCHG_GPRv_OrAX, + INTRINSIC_XED_IFORM_XCHG_MEMb_GPR8, + INTRINSIC_XED_IFORM_XCHG_MEMv_GPRv, + INTRINSIC_XED_IFORM_XEND, + INTRINSIC_XED_IFORM_XGETBV, + INTRINSIC_XED_IFORM_XLAT, + INTRINSIC_XED_IFORM_XOR_AL_IMMb, + INTRINSIC_XED_IFORM_XOR_GPR8_GPR8_30, + INTRINSIC_XED_IFORM_XOR_GPR8_GPR8_32, + INTRINSIC_XED_IFORM_XOR_GPR8_IMMb_80r6, + INTRINSIC_XED_IFORM_XOR_GPR8_IMMb_82r6, + INTRINSIC_XED_IFORM_XOR_GPR8_MEMb, + INTRINSIC_XED_IFORM_XOR_GPRv_GPRv_31, + INTRINSIC_XED_IFORM_XOR_GPRv_GPRv_33, + INTRINSIC_XED_IFORM_XOR_GPRv_IMMb, + INTRINSIC_XED_IFORM_XOR_GPRv_IMMz, + INTRINSIC_XED_IFORM_XOR_GPRv_MEMv, + INTRINSIC_XED_IFORM_XOR_MEMb_GPR8, + INTRINSIC_XED_IFORM_XOR_MEMb_IMMb_80r6, + INTRINSIC_XED_IFORM_XOR_MEMb_IMMb_82r6, + INTRINSIC_XED_IFORM_XOR_MEMv_GPRv, + INTRINSIC_XED_IFORM_XOR_MEMv_IMMb, + INTRINSIC_XED_IFORM_XOR_MEMv_IMMz, + INTRINSIC_XED_IFORM_XOR_OrAX_IMMz, + INTRINSIC_XED_IFORM_XORPD_XMMxuq_MEMxuq, + INTRINSIC_XED_IFORM_XORPD_XMMxuq_XMMxuq, + INTRINSIC_XED_IFORM_XORPS_XMMxud_MEMxud, + INTRINSIC_XED_IFORM_XORPS_XMMxud_XMMxud, + INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_GPR8, + INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6, + INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6, + INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_GPRv, + INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_IMMb, + INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_IMMz, + INTRINSIC_XED_IFORM_XRESLDTRK, + INTRINSIC_XED_IFORM_XRSTOR_MEMmxsave, + INTRINSIC_XED_IFORM_XRSTOR64_MEMmxsave, + INTRINSIC_XED_IFORM_XRSTORS_MEMmxsave, + INTRINSIC_XED_IFORM_XRSTORS64_MEMmxsave, + INTRINSIC_XED_IFORM_XSAVE_MEMmxsave, + INTRINSIC_XED_IFORM_XSAVE64_MEMmxsave, + INTRINSIC_XED_IFORM_XSAVEC_MEMmxsave, + INTRINSIC_XED_IFORM_XSAVEC64_MEMmxsave, + INTRINSIC_XED_IFORM_XSAVEOPT_MEMmxsave, + INTRINSIC_XED_IFORM_XSAVEOPT64_MEMmxsave, + INTRINSIC_XED_IFORM_XSAVES_MEMmxsave, + INTRINSIC_XED_IFORM_XSAVES64_MEMmxsave, + INTRINSIC_XED_IFORM_XSETBV, + INTRINSIC_XED_IFORM_XSTORE, + INTRINSIC_XED_IFORM_XSUSLDTRK, + INTRINSIC_XED_IFORM_XTEST, + INTRINSIC_XED_IFORM_LAST, + + // Below are modified iforms + // They are added to allow GetIntrinsicName() return an accurate intrinsic name. + // The old intrinsics (e.g., INTRINSIC_XED_IFORM_TZCNT_GPRv_GPRv), + // which are copied from xed include file is NOT deleted from above. + // It is not used since no code will ever emit them. + // Do NOT remove them since that will break the way we get intrinsic names. + INTRINSIC_XED_IFORM_TZCNT_GPR64_GPRMEM64, + INTRINSIC_XED_IFORM_TZCNT_GPR32_GPRMEM32, + INTRINSIC_XED_IFORM_TZCNT_GPR16_GPRMEM16, + + INTRINSIC_XED_IFORM_LZCNT_GPR64_GPRMEM64, + INTRINSIC_XED_IFORM_LZCNT_GPR32_GPRMEM32, + INTRINSIC_XED_IFORM_LZCNT_GPR16_GPRMEM16, + + INTRINSIC_XED_IFORM_POPCNT_GPR64_GPRMEM64, + INTRINSIC_XED_IFORM_POPCNT_GPR32_GPRMEM32, + INTRINSIC_XED_IFORM_POPCNT_GPR16_GPRMEM16, + + INTRINSIC_LAST +}; + +bool GetLowLevelILForInstruction(BinaryNinja::Architecture* arch, const uint64_t addr, BinaryNinja::LowLevelILFunction& il, const xed_decoded_inst_t* const xedd); diff --git a/arch/x86/mbuild b/arch/x86/mbuild new file mode 160000 +Subproject 75cb46e6536758f1a3cdb3d6bd83a4a9fd0338b diff --git a/arch/x86/test_lifting.py b/arch/x86/test_lifting.py new file mode 100755 index 00000000..49c808c7 --- /dev/null +++ b/arch/x86/test_lifting.py @@ -0,0 +1,127 @@ +#!/usr/bin/env python + +tests_interrupts = [ + (b'\xcd\x00', 'LLIL_TRAP(0)'), # int 0 + (b'\xcd\x01', 'LLIL_TRAP(1)'), # int 1 + (b'\xcd\x02', 'LLIL_TRAP(2)'), # int 2 + (b'\xcd\x03', 'LLIL_TRAP(3)'), # int 3 + (b'\xcd\x04', 'LLIL_TRAP(4)'), # int 4 + (b'\xcd\x05', 'LLIL_TRAP(5)'), # int 5 + (b'\xcd\x06', 'LLIL_TRAP(6)'), # int 6 + (b'\xcd\x07', 'LLIL_TRAP(7)'), # int 7 + (b'\xcd\x08', 'LLIL_TRAP(8)'), # int 8 + (b'\xcd\x09', 'LLIL_TRAP(9)'), # int 9 + (b'\xcd\x0A', 'LLIL_TRAP(10)'), # int 10 + (b'\xcd\x0B', 'LLIL_TRAP(11)'), # int 11 + (b'\xcd\x0C', 'LLIL_TRAP(12)'), # int 12 + (b'\xcd\x0D', 'LLIL_TRAP(13)'), # int 13 + (b'\xcd\x0E', 'LLIL_TRAP(14)'), # int 14 + (b'\xcd\x0F', 'LLIL_TRAP(15)'), # int 15 + (b'\xcd\x29', 'LLIL_TRAP(13)'), # int 0x29 is lifted as TRAP_GPF + (b'\xcd\x80', 'LLIL_SYSCALL()'), # int 0x80 is syscall on Linux +] + +tests_basics = [ + # nop + (b'\x90', 'LLIL_NOP()') +] + +test_cases = \ + tests_interrupts + \ + tests_basics + +import re +import sys +import binaryninja +from binaryninja import binaryview +from binaryninja import lowlevelil +from binaryninja.enums import LowLevelILOperation + +def il2str(il): + sz_lookup = {1:'.b', 2:'.w', 4:'.d', 8:'.q', 16:'.o'} + if isinstance(il, lowlevelil.LowLevelILInstruction): + size_code = sz_lookup.get(il.size, '?') if il.size else '' + flags_code = '' if not hasattr(il, 'flags') or not il.flags else '{%s}'%il.flags + + # print size-specified IL constants in hex + if il.operation in [LowLevelILOperation.LLIL_CONST, LowLevelILOperation.LLIL_CONST_PTR] and il.size: + tmp = il.operands[0] + if tmp < 0: tmp = (1<<(il.size*8))+tmp + tmp = '0x%X' % tmp if il.size else '%d' % il.size + return 'LLIL_CONST%s(%s)' % (size_code, tmp) + else: + return '%s%s%s(%s)' % (il.operation.name, size_code, flags_code, ','.join([il2str(o) for o in il.operands])) + elif isinstance(il, list): + return '[' + ','.join([il2str(x) for x in il]) + ']' + else: + return str(il) + +# TODO: make this less hacky +def instr_to_il(data): + platform = binaryninja.Platform['linux-x86'] + # make a pretend function that returns + bv = binaryview.BinaryView.new(data) + bv.add_function(0, plat=platform) + assert len(bv.functions) == 1 + + result = [] + for block in bv.functions[0].lifted_il: + for il in block: + result.append(il2str(il)) + result = '; '.join(result) + + try: + result = result[0:result.rindex('; LLIL_UNDEF{none}()')] + except: + pass + + try: + result = result[0:result.rindex('; LLIL_UNDEF()')] + except: + pass + + return result + +def il_str_to_tree(ilstr): + result = '' + depth = 0 + for c in ilstr: + if c == '(': + result += '\n' + depth += 1 + result += ' '*depth + elif c == ')': + depth -= 1 + elif c == ',': + result += '\n' + result += ' '*depth + pass + else: + result += c + return result + +def test_all(): + for (test_i, (data, expected)) in enumerate(test_cases): + actual = instr_to_il(data) + if actual != expected: + print('MISMATCH AT TEST %d!' % test_i) + print('\t input: %s' % data.hex()) + print('\texpected: %s' % expected) + print('\t actual: %s' % actual) + print('\t tree:') + print(il_str_to_tree(actual)) + + return False + + return True + +if __name__ == '__main__': + if test_all(): + print('success!') + sys.exit(0) + else: + sys.exit(-1) + +if __name__ == 'test_lifting': + if test_all(): + print('success!') diff --git a/arch/x86/x86_intrinsic_cached_input_types.include b/arch/x86/x86_intrinsic_cached_input_types.include new file mode 100644 index 00000000..fb89bb53 --- /dev/null +++ b/arch/x86/x86_intrinsic_cached_input_types.include @@ -0,0 +1,430 @@ +// Generated file, please do not edit directly + +X86CommonArchitecture::cached_input_types = new vector<NameAndType>[427]; +X86CommonArchitecture::cached_input_types[0] = vector<NameAndType> { NameAndType(Type::FloatType(10)), NameAndType(Type::FloatType(4)) }; +X86CommonArchitecture::cached_input_types[1] = vector<NameAndType> { NameAndType(Type::FloatType(10)), NameAndType(Type::FloatType(10)) }; +X86CommonArchitecture::cached_input_types[2] = vector<NameAndType> { NameAndType(Type::FloatType(10)), NameAndType(Type::FloatType(8)) }; +X86CommonArchitecture::cached_input_types[3] = vector<NameAndType> { NameAndType(Type::FloatType(10)), NameAndType(Type::FloatType(4)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[4] = vector<NameAndType> { NameAndType(Type::FloatType(10)), NameAndType(Type::FloatType(10)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[5] = vector<NameAndType> { NameAndType(Type::FloatType(10)), NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[6] = vector<NameAndType> { NameAndType(Type::FloatType(4)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[7] = vector<NameAndType> { NameAndType(Type::FloatType(10)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[8] = vector<NameAndType> { NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[9] = vector<NameAndType> { NameAndType(Type::FloatType(10)) }; +X86CommonArchitecture::cached_input_types[10] = vector<NameAndType> { NameAndType(Type::IntegerType(14, false)) }; +X86CommonArchitecture::cached_input_types[11] = vector<NameAndType> { NameAndType(Type::IntegerType(28, false)) }; +X86CommonArchitecture::cached_input_types[12] = vector<NameAndType> { NameAndType(Type::IntegerType(16, false)) }; +X86CommonArchitecture::cached_input_types[13] = vector<NameAndType> { }; +X86CommonArchitecture::cached_input_types[14] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[15] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[16] = vector<NameAndType> { NameAndType(Type::FloatType(10)), NameAndType(Type::IntegerType(4, true)) }; +X86CommonArchitecture::cached_input_types[17] = vector<NameAndType> { NameAndType(Type::FloatType(10)), NameAndType(Type::IntegerType(2, true)) }; +X86CommonArchitecture::cached_input_types[18] = vector<NameAndType> { NameAndType(Type::FloatType(10)), NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[19] = vector<NameAndType> { NameAndType(Type::FloatType(10)), NameAndType(Type::IntegerType(2, true)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[20] = vector<NameAndType> { NameAndType(Type::FloatType(10)), NameAndType(Type::FloatType(10)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[21] = vector<NameAndType> { NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[22] = vector<NameAndType> { NameAndType(Type::IntegerType(2, true)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[23] = vector<NameAndType> { NameAndType(Type::IntegerType(8, true)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[24] = vector<NameAndType> { NameAndType(Type::IntegerType(94, false)) }; +X86CommonArchitecture::cached_input_types[25] = vector<NameAndType> { NameAndType(Type::IntegerType(108, false)) }; +X86CommonArchitecture::cached_input_types[26] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[27] = vector<NameAndType> { NameAndType(Type::IntegerType(10, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[28] = vector<NameAndType> { NameAndType(Type::IntegerType(1, false)) }; +X86CommonArchitecture::cached_input_types[29] = vector<NameAndType> { NameAndType(Type::IntegerType(4, true)) }; +X86CommonArchitecture::cached_input_types[30] = vector<NameAndType> { NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(1, false)) }; +X86CommonArchitecture::cached_input_types[31] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[32] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, true)) }; +X86CommonArchitecture::cached_input_types[33] = vector<NameAndType> { NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[34] = vector<NameAndType> { NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[35] = vector<NameAndType> { NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[36] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[37] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[38] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[39] = vector<NameAndType> { NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(4, true)) }; +X86CommonArchitecture::cached_input_types[40] = vector<NameAndType> { NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(1, false)) }; +X86CommonArchitecture::cached_input_types[41] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(1, false)) }; +X86CommonArchitecture::cached_input_types[42] = vector<NameAndType> { NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[43] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[44] = vector<NameAndType> { NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[45] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[46] = vector<NameAndType> { NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[47] = vector<NameAndType> { NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[48] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[49] = vector<NameAndType> { NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[50] = vector<NameAndType> { NameAndType(Type::IntegerType(6, false)) }; +X86CommonArchitecture::cached_input_types[51] = vector<NameAndType> { NameAndType(Type::IntegerType(2, true)) }; +X86CommonArchitecture::cached_input_types[52] = vector<NameAndType> { NameAndType(Type::IntegerType(10, false)) }; +X86CommonArchitecture::cached_input_types[53] = vector<NameAndType> { NameAndType(Type::IntegerType(8, true)) }; +X86CommonArchitecture::cached_input_types[54] = vector<NameAndType> { NameAndType(Type::IntegerType(8, true)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[55] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[56] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 4)) }; +X86CommonArchitecture::cached_input_types[57] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 8)) }; +X86CommonArchitecture::cached_input_types[58] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 4)), NameAndType(Type::IntegerType(8, true)) }; +X86CommonArchitecture::cached_input_types[59] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)) }; +X86CommonArchitecture::cached_input_types[60] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, true), 4)) }; +X86CommonArchitecture::cached_input_types[61] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, true), 8)) }; +X86CommonArchitecture::cached_input_types[62] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, true), 4)), NameAndType(Type::IntegerType(8, true)) }; +X86CommonArchitecture::cached_input_types[63] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, true), 8)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[64] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)) }; +X86CommonArchitecture::cached_input_types[65] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 2)) }; +X86CommonArchitecture::cached_input_types[66] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)) }; +X86CommonArchitecture::cached_input_types[67] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 2)), NameAndType(Type::IntegerType(8, true)) }; +X86CommonArchitecture::cached_input_types[68] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 2)) }; +X86CommonArchitecture::cached_input_types[69] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)) }; +X86CommonArchitecture::cached_input_types[70] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 2)), NameAndType(Type::IntegerType(8, true)) }; +X86CommonArchitecture::cached_input_types[71] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[72] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[73] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, true)) }; +X86CommonArchitecture::cached_input_types[74] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[75] = vector<NameAndType> { NameAndType(Type::IntegerType(512, false)) }; +X86CommonArchitecture::cached_input_types[76] = vector<NameAndType> { NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[77] = vector<NameAndType> { NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[78] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 2)) }; +X86CommonArchitecture::cached_input_types[79] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)) }; +X86CommonArchitecture::cached_input_types[80] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[81] = vector<NameAndType> { NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[82] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(2, true)) }; +X86CommonArchitecture::cached_input_types[83] = vector<NameAndType> { NameAndType(Type::IntegerType(2, true)), NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[84] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[85] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[86] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[87] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[88] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, true)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[89] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, true)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[90] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[91] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[92] = vector<NameAndType> { NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[93] = vector<NameAndType> { NameAndType(Type::IntegerType(2, true)), NameAndType(Type::IntegerType(2, true)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[94] = vector<NameAndType> { NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[95] = vector<NameAndType> { NameAndType(Type::IntegerType(8, true)), NameAndType(Type::IntegerType(8, true)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[96] = vector<NameAndType> { NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[97] = vector<NameAndType> { NameAndType(Type::IntegerType(2, true)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[98] = vector<NameAndType> { NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[99] = vector<NameAndType> { NameAndType(Type::IntegerType(8, true)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[100] = vector<NameAndType> { NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[101] = vector<NameAndType> { NameAndType(Type::IntegerType(2, true)), NameAndType(Type::IntegerType(2, true)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[102] = vector<NameAndType> { NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[103] = vector<NameAndType> { NameAndType(Type::IntegerType(8, true)), NameAndType(Type::IntegerType(8, true)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[104] = vector<NameAndType> { NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[105] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[106] = vector<NameAndType> { NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[107] = vector<NameAndType> { NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[108] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, true)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[109] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, true)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[110] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[111] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)) }; +X86CommonArchitecture::cached_input_types[112] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::IntegerType(8, true)) }; +X86CommonArchitecture::cached_input_types[113] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)) }; +X86CommonArchitecture::cached_input_types[114] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)) }; +X86CommonArchitecture::cached_input_types[115] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::IntegerType(8, true)) }; +X86CommonArchitecture::cached_input_types[116] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)) }; +X86CommonArchitecture::cached_input_types[117] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 4)) }; +X86CommonArchitecture::cached_input_types[118] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::IntegerType(8, true)) }; +X86CommonArchitecture::cached_input_types[119] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 4)), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 2)) }; +X86CommonArchitecture::cached_input_types[120] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 2)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[121] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, true), 4)), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 4)) }; +X86CommonArchitecture::cached_input_types[122] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, true), 8)), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 8)) }; +X86CommonArchitecture::cached_input_types[123] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, true), 8)), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 8)) }; +X86CommonArchitecture::cached_input_types[124] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, true), 16)), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 16)) }; +X86CommonArchitecture::cached_input_types[125] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 2)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 2)) }; +X86CommonArchitecture::cached_input_types[126] = vector<NameAndType> { NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(1, false)) }; +X86CommonArchitecture::cached_input_types[127] = vector<NameAndType> { NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[128] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[129] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::ArrayType(Type::FloatType(4), 4)) }; +X86CommonArchitecture::cached_input_types[130] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 4)), NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[131] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 4)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[132] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::IntegerType(2, true)) }; +X86CommonArchitecture::cached_input_types[133] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[134] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::ArrayType(Type::FloatType(8), 2)) }; +X86CommonArchitecture::cached_input_types[135] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, true), 8)) }; +X86CommonArchitecture::cached_input_types[136] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, true), 16)) }; +X86CommonArchitecture::cached_input_types[137] = vector<NameAndType> { NameAndType(Type::IntegerType(8, true)), NameAndType(Type::IntegerType(8, true)) }; +X86CommonArchitecture::cached_input_types[138] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)) }; +X86CommonArchitecture::cached_input_types[139] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 8)) }; +X86CommonArchitecture::cached_input_types[140] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 4)), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 4)) }; +X86CommonArchitecture::cached_input_types[141] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 2)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 2)) }; +X86CommonArchitecture::cached_input_types[142] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 8)) }; +X86CommonArchitecture::cached_input_types[143] = vector<NameAndType> { NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, true)) }; +X86CommonArchitecture::cached_input_types[144] = vector<NameAndType> { NameAndType(Type::IntegerType(8, true)), NameAndType(Type::IntegerType(4, true)) }; +X86CommonArchitecture::cached_input_types[145] = vector<NameAndType> { NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(1, false)) }; +X86CommonArchitecture::cached_input_types[146] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(1, false)) }; +X86CommonArchitecture::cached_input_types[147] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 2)), NameAndType(Type::IntegerType(1, false)) }; +X86CommonArchitecture::cached_input_types[148] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 2)), NameAndType(Type::IntegerType(4, true)) }; +X86CommonArchitecture::cached_input_types[149] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[150] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)) }; +X86CommonArchitecture::cached_input_types[151] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::IntegerType(4, true)) }; +X86CommonArchitecture::cached_input_types[152] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)) }; +X86CommonArchitecture::cached_input_types[153] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::IntegerType(1, false)) }; +X86CommonArchitecture::cached_input_types[154] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::IntegerType(4, true)) }; +X86CommonArchitecture::cached_input_types[155] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, true), 4)) }; +X86CommonArchitecture::cached_input_types[156] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, true), 2)) }; +X86CommonArchitecture::cached_input_types[157] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, true), 2)) }; +X86CommonArchitecture::cached_input_types[158] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 8)) }; +X86CommonArchitecture::cached_input_types[159] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 4)) }; +X86CommonArchitecture::cached_input_types[160] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 2)) }; +X86CommonArchitecture::cached_input_types[161] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 2)) }; +X86CommonArchitecture::cached_input_types[162] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[163] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[164] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)) }; +X86CommonArchitecture::cached_input_types[165] = vector<NameAndType> { NameAndType(Type::IntegerType(4, false)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)) }; +X86CommonArchitecture::cached_input_types[166] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(1, false)) }; +X86CommonArchitecture::cached_input_types[167] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(1, false)) }; +X86CommonArchitecture::cached_input_types[168] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(1, false)) }; +X86CommonArchitecture::cached_input_types[169] = vector<NameAndType> { NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(14, false)) }; +X86CommonArchitecture::cached_input_types[170] = vector<NameAndType> { NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[171] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[172] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[173] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 4)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[174] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 8)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[175] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)) }; +X86CommonArchitecture::cached_input_types[176] = vector<NameAndType> { NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[177] = vector<NameAndType> { NameAndType(Type::IntegerType(8, false)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)) }; +X86CommonArchitecture::cached_input_types[178] = vector<NameAndType> { NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[179] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[180] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, true), 8)), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 8)), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 8)) }; +X86CommonArchitecture::cached_input_types[181] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, true), 8)), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 8)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)) }; +X86CommonArchitecture::cached_input_types[182] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 2)) }; +X86CommonArchitecture::cached_input_types[183] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::BoolType(), 16)), NameAndType(Type::ArrayType(Type::BoolType(), 16)), NameAndType(Type::ArrayType(Type::BoolType(), 16)) }; +X86CommonArchitecture::cached_input_types[184] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::BoolType(), 32)), NameAndType(Type::ArrayType(Type::BoolType(), 32)), NameAndType(Type::ArrayType(Type::BoolType(), 32)) }; +X86CommonArchitecture::cached_input_types[185] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)) }; +X86CommonArchitecture::cached_input_types[186] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, true), 2)), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 2)) }; +X86CommonArchitecture::cached_input_types[187] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 8)) }; +X86CommonArchitecture::cached_input_types[188] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 4)) }; +X86CommonArchitecture::cached_input_types[189] = vector<NameAndType> { NameAndType(Type::FloatType(4)) }; +X86CommonArchitecture::cached_input_types[190] = vector<NameAndType> { NameAndType(Type::FloatType(8)) }; +X86CommonArchitecture::cached_input_types[191] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::ArrayType(Type::FloatType(4), 4)) }; +X86CommonArchitecture::cached_input_types[192] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 8)), NameAndType(Type::ArrayType(Type::FloatType(4), 8)), NameAndType(Type::ArrayType(Type::FloatType(4), 8)) }; +X86CommonArchitecture::cached_input_types[193] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::ArrayType(Type::FloatType(8), 2)) }; +X86CommonArchitecture::cached_input_types[194] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 4)), NameAndType(Type::ArrayType(Type::FloatType(8), 4)), NameAndType(Type::ArrayType(Type::FloatType(8), 4)) }; +X86CommonArchitecture::cached_input_types[195] = vector<NameAndType> { NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(4)) }; +X86CommonArchitecture::cached_input_types[196] = vector<NameAndType> { NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)) }; +X86CommonArchitecture::cached_input_types[197] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 4)), NameAndType(Type::ArrayType(Type::FloatType(8), 4)) }; +X86CommonArchitecture::cached_input_types[198] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 8)), NameAndType(Type::ArrayType(Type::FloatType(4), 8)) }; +X86CommonArchitecture::cached_input_types[199] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::FloatType(8)) }; +X86CommonArchitecture::cached_input_types[200] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::FloatType(4)) }; +X86CommonArchitecture::cached_input_types[201] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)) }; +X86CommonArchitecture::cached_input_types[202] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 8)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 8)) }; +X86CommonArchitecture::cached_input_types[203] = vector<NameAndType> { NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)) }; +X86CommonArchitecture::cached_input_types[204] = vector<NameAndType> { NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(4)) }; +X86CommonArchitecture::cached_input_types[205] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 8)) }; +X86CommonArchitecture::cached_input_types[206] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::FloatType(8)) }; +X86CommonArchitecture::cached_input_types[207] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::IntegerType(4, true)) }; +X86CommonArchitecture::cached_input_types[208] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::FloatType(4)) }; +X86CommonArchitecture::cached_input_types[209] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[210] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 4)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)) }; +X86CommonArchitecture::cached_input_types[211] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)) }; +X86CommonArchitecture::cached_input_types[212] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 8)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)) }; +X86CommonArchitecture::cached_input_types[213] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 4)), NameAndType(Type::ArrayType(Type::FloatType(8), 2)) }; +X86CommonArchitecture::cached_input_types[214] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::ArrayType(Type::FloatType(4), 4)) }; +X86CommonArchitecture::cached_input_types[215] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 8)), NameAndType(Type::ArrayType(Type::FloatType(4), 8)) }; +X86CommonArchitecture::cached_input_types[216] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)), NameAndType(Type::ArrayType(Type::FloatType(8), 2)) }; +X86CommonArchitecture::cached_input_types[217] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)), NameAndType(Type::ArrayType(Type::FloatType(8), 4)) }; +X86CommonArchitecture::cached_input_types[218] = vector<NameAndType> { NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false)) }; +X86CommonArchitecture::cached_input_types[219] = vector<NameAndType> { NameAndType(Type::IntegerType(32, false)), NameAndType(Type::IntegerType(32, false)) }; +X86CommonArchitecture::cached_input_types[220] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, true), 32)) }; +X86CommonArchitecture::cached_input_types[221] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, true), 16)) }; +X86CommonArchitecture::cached_input_types[222] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)) }; +X86CommonArchitecture::cached_input_types[223] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 16)) }; +X86CommonArchitecture::cached_input_types[224] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, true), 16)), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 16)) }; +X86CommonArchitecture::cached_input_types[225] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[226] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[227] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 16)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[228] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[229] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[230] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[231] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[232] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[233] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)) }; +X86CommonArchitecture::cached_input_types[234] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, true), 16)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[235] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, true), 16)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[236] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 8)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[237] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 8)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[238] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, true), 32)), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 32)) }; +X86CommonArchitecture::cached_input_types[239] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, true), 4)), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 4)) }; +X86CommonArchitecture::cached_input_types[240] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)) }; +X86CommonArchitecture::cached_input_types[241] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 16)) }; +X86CommonArchitecture::cached_input_types[242] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)) }; +X86CommonArchitecture::cached_input_types[243] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(16, false), 2)) }; +X86CommonArchitecture::cached_input_types[244] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 2)), NameAndType(Type::ArrayType(Type::FloatType(4), 2)) }; +X86CommonArchitecture::cached_input_types[245] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 16)) }; +X86CommonArchitecture::cached_input_types[246] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 32)) }; +X86CommonArchitecture::cached_input_types[247] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::ArrayType(Type::FloatType(4), 2)) }; +X86CommonArchitecture::cached_input_types[248] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)), NameAndType(Type::IntegerType(1, false)) }; +X86CommonArchitecture::cached_input_types[249] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 4)) }; +X86CommonArchitecture::cached_input_types[250] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 8)), NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[251] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 2)) }; +X86CommonArchitecture::cached_input_types[252] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[253] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[254] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, true), 16)), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 16)), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 16)) }; +X86CommonArchitecture::cached_input_types[255] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)) }; +X86CommonArchitecture::cached_input_types[256] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 4)), NameAndType(Type::ArrayType(Type::FloatType(8), 4)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)) }; +X86CommonArchitecture::cached_input_types[257] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 8)), NameAndType(Type::ArrayType(Type::FloatType(4), 8)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)) }; +X86CommonArchitecture::cached_input_types[258] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(16, false), 2)), NameAndType(Type::ArrayType(Type::IntegerType(16, false), 2)) }; +X86CommonArchitecture::cached_input_types[259] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(2), 4)) }; +X86CommonArchitecture::cached_input_types[260] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(2), 8)) }; +X86CommonArchitecture::cached_input_types[261] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)) }; +X86CommonArchitecture::cached_input_types[262] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(4)) }; +X86CommonArchitecture::cached_input_types[263] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 4)), NameAndType(Type::FloatType(8)), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 4)) }; +X86CommonArchitecture::cached_input_types[264] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::FloatType(8)), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 2)) }; +X86CommonArchitecture::cached_input_types[265] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 8)), NameAndType(Type::FloatType(4)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 8)) }; +X86CommonArchitecture::cached_input_types[266] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::FloatType(4)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)) }; +X86CommonArchitecture::cached_input_types[267] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 2)), NameAndType(Type::FloatType(4)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 2)) }; +X86CommonArchitecture::cached_input_types[268] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 4)) }; +X86CommonArchitecture::cached_input_types[269] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 2)) }; +X86CommonArchitecture::cached_input_types[270] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 8)) }; +X86CommonArchitecture::cached_input_types[271] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)) }; +X86CommonArchitecture::cached_input_types[272] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 2)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 2)) }; +X86CommonArchitecture::cached_input_types[273] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(16, false), 2)), NameAndType(Type::IntegerType(16, false)) }; +X86CommonArchitecture::cached_input_types[274] = vector<NameAndType> { NameAndType(Type::IntegerType(4, true)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[275] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::BoolType()) }; +X86CommonArchitecture::cached_input_types[276] = vector<NameAndType> { NameAndType(Type::BoolType()) }; +X86CommonArchitecture::cached_input_types[277] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)) }; +X86CommonArchitecture::cached_input_types[278] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)) }; +X86CommonArchitecture::cached_input_types[279] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 8)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)) }; +X86CommonArchitecture::cached_input_types[280] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 16)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 64)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)) }; +X86CommonArchitecture::cached_input_types[281] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 8)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)) }; +X86CommonArchitecture::cached_input_types[282] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 8)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 16)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)) }; +X86CommonArchitecture::cached_input_types[283] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 16)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 32)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)) }; +X86CommonArchitecture::cached_input_types[284] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::ArrayType(Type::FloatType(4), 4)) }; +X86CommonArchitecture::cached_input_types[285] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 8)), NameAndType(Type::ArrayType(Type::FloatType(4), 8)) }; +X86CommonArchitecture::cached_input_types[286] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 16)), NameAndType(Type::ArrayType(Type::FloatType(4), 16)) }; +X86CommonArchitecture::cached_input_types[287] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 4)) }; +X86CommonArchitecture::cached_input_types[288] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 8)) }; +X86CommonArchitecture::cached_input_types[289] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 16)) }; +X86CommonArchitecture::cached_input_types[290] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)) }; +X86CommonArchitecture::cached_input_types[291] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 8)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)) }; +X86CommonArchitecture::cached_input_types[292] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 16)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)) }; +X86CommonArchitecture::cached_input_types[293] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(8), 8)) }; +X86CommonArchitecture::cached_input_types[294] = vector<NameAndType> { NameAndType(Type::FloatType(8)), NameAndType(Type::BoolType()) }; +X86CommonArchitecture::cached_input_types[295] = vector<NameAndType> { NameAndType(Type::FloatType(4)), NameAndType(Type::BoolType()) }; +X86CommonArchitecture::cached_input_types[296] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::ArrayType(Type::FloatType(8), 2)) }; +X86CommonArchitecture::cached_input_types[297] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::FloatType(8)) }; +X86CommonArchitecture::cached_input_types[298] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::FloatType(4)) }; +X86CommonArchitecture::cached_input_types[299] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 16)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 16)), NameAndType(Type::ArrayType(Type::FloatType(4), 4)) }; +X86CommonArchitecture::cached_input_types[300] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::ArrayType(Type::FloatType(4), 4)) }; +X86CommonArchitecture::cached_input_types[301] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, true), 16)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 32)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)) }; +X86CommonArchitecture::cached_input_types[302] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)) }; +X86CommonArchitecture::cached_input_types[303] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)) }; +X86CommonArchitecture::cached_input_types[304] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)) }; +X86CommonArchitecture::cached_input_types[305] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 8)) }; +X86CommonArchitecture::cached_input_types[306] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[307] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)) }; +X86CommonArchitecture::cached_input_types[308] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(8), 8)), NameAndType(Type::ArrayType(Type::FloatType(8), 8)) }; +X86CommonArchitecture::cached_input_types[309] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(8), 4)), NameAndType(Type::ArrayType(Type::FloatType(8), 4)) }; +X86CommonArchitecture::cached_input_types[310] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)) }; +X86CommonArchitecture::cached_input_types[311] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)) }; +X86CommonArchitecture::cached_input_types[312] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)) }; +X86CommonArchitecture::cached_input_types[313] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 8)) }; +X86CommonArchitecture::cached_input_types[314] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[315] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)) }; +X86CommonArchitecture::cached_input_types[316] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(8), 4)) }; +X86CommonArchitecture::cached_input_types[317] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::FloatType(8)) }; +X86CommonArchitecture::cached_input_types[318] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(8), 2)) }; +X86CommonArchitecture::cached_input_types[319] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::FloatType(4)) }; +X86CommonArchitecture::cached_input_types[320] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 8)) }; +X86CommonArchitecture::cached_input_types[321] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 16)) }; +X86CommonArchitecture::cached_input_types[322] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)) }; +X86CommonArchitecture::cached_input_types[323] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(2), 16)) }; +X86CommonArchitecture::cached_input_types[324] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(2), 8)) }; +X86CommonArchitecture::cached_input_types[325] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(2), 4)) }; +X86CommonArchitecture::cached_input_types[326] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[327] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[328] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[329] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[330] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 8)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(8), 8)), NameAndType(Type::ArrayType(Type::FloatType(8), 8)) }; +X86CommonArchitecture::cached_input_types[331] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::ArrayType(Type::FloatType(8), 2)) }; +X86CommonArchitecture::cached_input_types[332] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 4)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(8), 4)), NameAndType(Type::ArrayType(Type::FloatType(8), 4)) }; +X86CommonArchitecture::cached_input_types[333] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 16)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 16)), NameAndType(Type::ArrayType(Type::FloatType(4), 16)) }; +X86CommonArchitecture::cached_input_types[334] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 8)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 8)), NameAndType(Type::ArrayType(Type::FloatType(4), 8)) }; +X86CommonArchitecture::cached_input_types[335] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(8), 2)), NameAndType(Type::FloatType(8)) }; +X86CommonArchitecture::cached_input_types[336] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 4)), NameAndType(Type::FloatType(4)) }; +X86CommonArchitecture::cached_input_types[337] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 16)), NameAndType(Type::ArrayType(Type::FloatType(4), 4)) }; +X86CommonArchitecture::cached_input_types[338] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 8)), NameAndType(Type::ArrayType(Type::FloatType(4), 4)) }; +X86CommonArchitecture::cached_input_types[339] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(8), 8)), NameAndType(Type::ArrayType(Type::FloatType(8), 4)) }; +X86CommonArchitecture::cached_input_types[340] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)) }; +X86CommonArchitecture::cached_input_types[341] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)) }; +X86CommonArchitecture::cached_input_types[342] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)) }; +X86CommonArchitecture::cached_input_types[343] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)) }; +X86CommonArchitecture::cached_input_types[344] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(8), 8)) }; +X86CommonArchitecture::cached_input_types[345] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::FloatType(4), 16)) }; +X86CommonArchitecture::cached_input_types[346] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 8)) }; +X86CommonArchitecture::cached_input_types[347] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 2)) }; +X86CommonArchitecture::cached_input_types[348] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 4)) }; +X86CommonArchitecture::cached_input_types[349] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::IntegerType(4, false)) }; +X86CommonArchitecture::cached_input_types[350] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::IntegerType(8, false)) }; +X86CommonArchitecture::cached_input_types[351] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 16)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 16)) }; +X86CommonArchitecture::cached_input_types[352] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 4)) }; +X86CommonArchitecture::cached_input_types[353] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 8)), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 8)) }; +X86CommonArchitecture::cached_input_types[354] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 8)), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 8)) }; +X86CommonArchitecture::cached_input_types[355] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 2)), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 2)) }; +X86CommonArchitecture::cached_input_types[356] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 4)), NameAndType(Type::ArrayType(Type::IntegerType(8, true), 4)) }; +X86CommonArchitecture::cached_input_types[357] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)) }; +X86CommonArchitecture::cached_input_types[358] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 4)) }; +X86CommonArchitecture::cached_input_types[359] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)) }; +X86CommonArchitecture::cached_input_types[360] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 8)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 8)) }; +X86CommonArchitecture::cached_input_types[361] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[362] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)) }; +X86CommonArchitecture::cached_input_types[363] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 16)) }; +X86CommonArchitecture::cached_input_types[364] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 4)) }; +X86CommonArchitecture::cached_input_types[365] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 8)) }; +X86CommonArchitecture::cached_input_types[366] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 2)) }; +X86CommonArchitecture::cached_input_types[367] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, true), 2)) }; +X86CommonArchitecture::cached_input_types[368] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 16)) }; +X86CommonArchitecture::cached_input_types[369] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 8)) }; +X86CommonArchitecture::cached_input_types[370] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 4)) }; +X86CommonArchitecture::cached_input_types[371] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 2)) }; +X86CommonArchitecture::cached_input_types[372] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[373] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[374] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 2)) }; +X86CommonArchitecture::cached_input_types[375] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 2)) }; +X86CommonArchitecture::cached_input_types[376] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)) }; +X86CommonArchitecture::cached_input_types[377] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)) }; +X86CommonArchitecture::cached_input_types[378] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 64)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 64)) }; +X86CommonArchitecture::cached_input_types[379] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(4), 16)), NameAndType(Type::ArrayType(Type::FloatType(4), 8)) }; +X86CommonArchitecture::cached_input_types[380] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(8), 4)), NameAndType(Type::ArrayType(Type::FloatType(8), 2)) }; +X86CommonArchitecture::cached_input_types[381] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::FloatType(8), 8)), NameAndType(Type::ArrayType(Type::FloatType(8), 2)) }; +X86CommonArchitecture::cached_input_types[382] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 8)) }; +X86CommonArchitecture::cached_input_types[383] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 8)) }; +X86CommonArchitecture::cached_input_types[384] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 16)) }; +X86CommonArchitecture::cached_input_types[385] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 32)) }; +X86CommonArchitecture::cached_input_types[386] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)) }; +X86CommonArchitecture::cached_input_types[387] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)) }; +X86CommonArchitecture::cached_input_types[388] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 64)) }; +X86CommonArchitecture::cached_input_types[389] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 32)) }; +X86CommonArchitecture::cached_input_types[390] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 64)) }; +X86CommonArchitecture::cached_input_types[391] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 32)) }; +X86CommonArchitecture::cached_input_types[392] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 8)), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 8)) }; +X86CommonArchitecture::cached_input_types[393] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 16)), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 16)) }; +X86CommonArchitecture::cached_input_types[394] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 32)), NameAndType(Type::ArrayType(Type::IntegerType(2, true), 32)) }; +X86CommonArchitecture::cached_input_types[395] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 8)) }; +X86CommonArchitecture::cached_input_types[396] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 16)) }; +X86CommonArchitecture::cached_input_types[397] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 32)), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 32)) }; +X86CommonArchitecture::cached_input_types[398] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 16)), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 16)) }; +X86CommonArchitecture::cached_input_types[399] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 32)), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 32)) }; +X86CommonArchitecture::cached_input_types[400] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 64)), NameAndType(Type::ArrayType(Type::IntegerType(1, true), 64)) }; +X86CommonArchitecture::cached_input_types[401] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::IntegerType(1, false)) }; +X86CommonArchitecture::cached_input_types[402] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 4)) }; +X86CommonArchitecture::cached_input_types[403] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::IntegerType(2, false)) }; +X86CommonArchitecture::cached_input_types[404] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 2)) }; +X86CommonArchitecture::cached_input_types[405] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 8)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 8)) }; +X86CommonArchitecture::cached_input_types[406] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 16)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 16)) }; +X86CommonArchitecture::cached_input_types[407] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 32)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 32)), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 32)) }; +X86CommonArchitecture::cached_input_types[408] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)) }; +X86CommonArchitecture::cached_input_types[409] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 64)) }; +X86CommonArchitecture::cached_input_types[410] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 8)) }; +X86CommonArchitecture::cached_input_types[411] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(2, false), 32)) }; +X86CommonArchitecture::cached_input_types[412] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 64)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 64)) }; +X86CommonArchitecture::cached_input_types[413] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 8)) }; +X86CommonArchitecture::cached_input_types[414] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 32)), NameAndType(Type::ArrayType(Type::IntegerType(2, false), 8)) }; +X86CommonArchitecture::cached_input_types[415] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)) }; +X86CommonArchitecture::cached_input_types[416] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)) }; +X86CommonArchitecture::cached_input_types[417] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(1, false), 64)), NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 64)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 64)) }; +X86CommonArchitecture::cached_input_types[418] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)) }; +X86CommonArchitecture::cached_input_types[419] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)) }; +X86CommonArchitecture::cached_input_types[420] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 64)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 8)) }; +X86CommonArchitecture::cached_input_types[421] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 2)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 16)) }; +X86CommonArchitecture::cached_input_types[422] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 4)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 32)) }; +X86CommonArchitecture::cached_input_types[423] = vector<NameAndType> { NameAndType(Type::BoolType()), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(1, false), 64)) }; +X86CommonArchitecture::cached_input_types[424] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(16, false), 4)), NameAndType(Type::ArrayType(Type::IntegerType(16, false), 4)) }; +X86CommonArchitecture::cached_input_types[425] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(8, false), 8)), NameAndType(Type::ArrayType(Type::IntegerType(8, false), 8)) }; +X86CommonArchitecture::cached_input_types[426] = vector<NameAndType> { NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)), NameAndType(Type::ArrayType(Type::IntegerType(4, false), 16)) }; diff --git a/arch/x86/x86_intrinsic_cached_output_types.include b/arch/x86/x86_intrinsic_cached_output_types.include new file mode 100644 index 00000000..0987e40a --- /dev/null +++ b/arch/x86/x86_intrinsic_cached_output_types.include @@ -0,0 +1,151 @@ +// Generated file, please do not edit directly + +X86CommonArchitecture::cached_output_types = new vector<Confidence<Ref<Type>>>[148]; +X86CommonArchitecture::cached_output_types[0] = vector<Confidence<Ref<Type>>> { Type::FloatType(10), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[1] = vector<Confidence<Ref<Type>>> { Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[2] = vector<Confidence<Ref<Type>>> { Type::FloatType(4), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[3] = vector<Confidence<Ref<Type>>> { Type::FloatType(8), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[4] = vector<Confidence<Ref<Type>>> { Type::IntegerType(2, false), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[5] = vector<Confidence<Ref<Type>>> { Type::IntegerType(14, false), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[6] = vector<Confidence<Ref<Type>>> { Type::IntegerType(28, false), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[7] = vector<Confidence<Ref<Type>>> { Type::IntegerType(16, false), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[8] = vector<Confidence<Ref<Type>>> { Type::FloatType(10), Type::FloatType(10), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[9] = vector<Confidence<Ref<Type>>> { }; +X86CommonArchitecture::cached_output_types[10] = vector<Confidence<Ref<Type>>> { Type::FloatType(10), Type::IntegerType(2, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[11] = vector<Confidence<Ref<Type>>> { Type::IntegerType(8, false), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[12] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, true), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[13] = vector<Confidence<Ref<Type>>> { Type::IntegerType(8, true), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[14] = vector<Confidence<Ref<Type>>> { Type::IntegerType(2, true), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[15] = vector<Confidence<Ref<Type>>> { Type::IntegerType(2, false), Type::IntegerType(2, false), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[16] = vector<Confidence<Ref<Type>>> { Type::IntegerType(2, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[17] = vector<Confidence<Ref<Type>>> { Type::IntegerType(94, false), Type::IntegerType(2, false), Type::IntegerType(2, false), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[18] = vector<Confidence<Ref<Type>>> { Type::IntegerType(108, false), Type::IntegerType(2, false), Type::IntegerType(2, false), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[19] = vector<Confidence<Ref<Type>>> { Type::IntegerType(10, false), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[20] = vector<Confidence<Ref<Type>>> { Type::IntegerType(1, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[21] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, true), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[22] = vector<Confidence<Ref<Type>>> { Type::IntegerType(8, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[23] = vector<Confidence<Ref<Type>>> { Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[24] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, true) }; +X86CommonArchitecture::cached_output_types[25] = vector<Confidence<Ref<Type>>> { Type::IntegerType(1, false) }; +X86CommonArchitecture::cached_output_types[26] = vector<Confidence<Ref<Type>>> { Type::IntegerType(2, false), Type::IntegerType(2, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[27] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, true), Type::IntegerType(8, false), Type::IntegerType(4, true) }; +X86CommonArchitecture::cached_output_types[28] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, true), Type::IntegerType(4, false), Type::IntegerType(4, true) }; +X86CommonArchitecture::cached_output_types[29] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, false) }; +X86CommonArchitecture::cached_output_types[30] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, true), Type::IntegerType(4, true) }; +X86CommonArchitecture::cached_output_types[31] = vector<Confidence<Ref<Type>>> { Type::IntegerType(2, true) }; +X86CommonArchitecture::cached_output_types[32] = vector<Confidence<Ref<Type>>> { Type::IntegerType(6, false) }; +X86CommonArchitecture::cached_output_types[33] = vector<Confidence<Ref<Type>>> { Type::IntegerType(8, true), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[34] = vector<Confidence<Ref<Type>>> { Type::IntegerType(8, true), Type::IntegerType(4, false), Type::IntegerType(4, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[35] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, true), 4), Type::IntegerType(8, false), Type::IntegerType(8, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[36] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(2, false), 4) }; +X86CommonArchitecture::cached_output_types[37] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(2, false), 8) }; +X86CommonArchitecture::cached_output_types[38] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, true), 4) }; +X86CommonArchitecture::cached_output_types[39] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(2, true), 4) }; +X86CommonArchitecture::cached_output_types[40] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(2, true), 8) }; +X86CommonArchitecture::cached_output_types[41] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, false), 2) }; +X86CommonArchitecture::cached_output_types[42] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, false), 4) }; +X86CommonArchitecture::cached_output_types[43] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, true), 2) }; +X86CommonArchitecture::cached_output_types[44] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(8, false), 2) }; +X86CommonArchitecture::cached_output_types[45] = vector<Confidence<Ref<Type>>> { Type::IntegerType(16, false) }; +X86CommonArchitecture::cached_output_types[46] = vector<Confidence<Ref<Type>>> { Type::IntegerType(512, false) }; +X86CommonArchitecture::cached_output_types[47] = vector<Confidence<Ref<Type>>> { Type::IntegerType(10, false) }; +X86CommonArchitecture::cached_output_types[48] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, false), Type::IntegerType(4, false), Type::IntegerType(4, false) }; +X86CommonArchitecture::cached_output_types[49] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(4), 2) }; +X86CommonArchitecture::cached_output_types[50] = vector<Confidence<Ref<Type>>> { Type::IntegerType(1, false), Type::IntegerType(1, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[51] = vector<Confidence<Ref<Type>>> { Type::IntegerType(2, false), Type::IntegerType(2, false), Type::IntegerType(2, false), Type::IntegerType(2, false), Type::IntegerType(2, false), Type::IntegerType(2, false), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[52] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, false), Type::IntegerType(4, false), Type::IntegerType(4, false), Type::IntegerType(4, false), Type::IntegerType(4, false), Type::IntegerType(4, false), Type::IntegerType(4, false) }; +X86CommonArchitecture::cached_output_types[53] = vector<Confidence<Ref<Type>>> { Type::IntegerType(2, true), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[54] = vector<Confidence<Ref<Type>>> { Type::IntegerType(1, false), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[55] = vector<Confidence<Ref<Type>>> { Type::IntegerType(1, false), Type::IntegerType(1, false) }; +X86CommonArchitecture::cached_output_types[56] = vector<Confidence<Ref<Type>>> { Type::IntegerType(2, true), Type::IntegerType(2, true) }; +X86CommonArchitecture::cached_output_types[57] = vector<Confidence<Ref<Type>>> { Type::IntegerType(8, true), Type::IntegerType(8, true) }; +X86CommonArchitecture::cached_output_types[58] = vector<Confidence<Ref<Type>>> { Type::IntegerType(8, true) }; +X86CommonArchitecture::cached_output_types[59] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, false), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[60] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, true), Type::IntegerType(2, false), Type::IntegerType(4, true) }; +X86CommonArchitecture::cached_output_types[61] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[62] = vector<Confidence<Ref<Type>>> { Type::IntegerType(8, false), Type::IntegerType(8, false), Type::IntegerType(8, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[63] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(4), 4) }; +X86CommonArchitecture::cached_output_types[64] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(8), 2) }; +X86CommonArchitecture::cached_output_types[65] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, false), Type::IntegerType(4, false) }; +X86CommonArchitecture::cached_output_types[66] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, false), Type::IntegerType(4, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[67] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(1, false), 8) }; +X86CommonArchitecture::cached_output_types[68] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(1, true), 8) }; +X86CommonArchitecture::cached_output_types[69] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(1, true), 16) }; +X86CommonArchitecture::cached_output_types[70] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, false), Type::IntegerType(4, false), Type::IntegerType(4, false), Type::IntegerType(4, false) }; +X86CommonArchitecture::cached_output_types[71] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, true), Type::IntegerType(2, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[72] = vector<Confidence<Ref<Type>>> { Type::IntegerType(8, false), Type::IntegerType(2, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[73] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, true), Type::IntegerType(8, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[74] = vector<Confidence<Ref<Type>>> { Type::IntegerType(8, false), Type::IntegerType(8, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[75] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(1, false), 16) }; +X86CommonArchitecture::cached_output_types[76] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(8, true), 2) }; +X86CommonArchitecture::cached_output_types[77] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, true), 4), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[78] = vector<Confidence<Ref<Type>>> { Type::IntegerType(1, false), Type::IntegerType(2, false), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[79] = vector<Confidence<Ref<Type>>> { Type::IntegerType(1, false), Type::IntegerType(2, false), Type::IntegerType(2, false), Type::IntegerType(2, false) }; +X86CommonArchitecture::cached_output_types[80] = vector<Confidence<Ref<Type>>> { Type::IntegerType(2, false), Type::IntegerType(2, false), Type::IntegerType(1, false) }; +X86CommonArchitecture::cached_output_types[81] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, false), Type::IntegerType(4, false), Type::IntegerType(4, false), Type::IntegerType(14, false) }; +X86CommonArchitecture::cached_output_types[82] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, true), 16) }; +X86CommonArchitecture::cached_output_types[83] = vector<Confidence<Ref<Type>>> { Type::IntegerType(8, false), Type::IntegerType(4, false) }; +X86CommonArchitecture::cached_output_types[84] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, false), Type::IntegerType(4, false), Type::IntegerType(4, false), Type::IntegerType(4, false), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[85] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::BoolType(), 16) }; +X86CommonArchitecture::cached_output_types[86] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::BoolType(), 32) }; +X86CommonArchitecture::cached_output_types[87] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(4), 8) }; +X86CommonArchitecture::cached_output_types[88] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(8), 4) }; +X86CommonArchitecture::cached_output_types[89] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, true), 2), Type::IntegerType(8, false) }; +X86CommonArchitecture::cached_output_types[90] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(8, false), 4) }; +X86CommonArchitecture::cached_output_types[91] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, true), 8) }; +X86CommonArchitecture::cached_output_types[92] = vector<Confidence<Ref<Type>>> { Type::FloatType(4) }; +X86CommonArchitecture::cached_output_types[93] = vector<Confidence<Ref<Type>>> { Type::IntegerType(32, false) }; +X86CommonArchitecture::cached_output_types[94] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(1, false), 32) }; +X86CommonArchitecture::cached_output_types[95] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(2, false), 16) }; +X86CommonArchitecture::cached_output_types[96] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, false), 8) }; +X86CommonArchitecture::cached_output_types[97] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(1, true), 32) }; +X86CommonArchitecture::cached_output_types[98] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(2, true), 16) }; +X86CommonArchitecture::cached_output_types[99] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(8, true), 4) }; +X86CommonArchitecture::cached_output_types[100] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(16, false), 2) }; +X86CommonArchitecture::cached_output_types[101] = vector<Confidence<Ref<Type>>> { Type::FloatType(8) }; +X86CommonArchitecture::cached_output_types[102] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(2), 4) }; +X86CommonArchitecture::cached_output_types[103] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(2), 8) }; +X86CommonArchitecture::cached_output_types[104] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(8), 4), Type::ArrayType(Type::IntegerType(8, true), 4) }; +X86CommonArchitecture::cached_output_types[105] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(8), 2), Type::ArrayType(Type::IntegerType(8, true), 2) }; +X86CommonArchitecture::cached_output_types[106] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(4), 8), Type::ArrayType(Type::IntegerType(4, true), 8) }; +X86CommonArchitecture::cached_output_types[107] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(4), 4), Type::ArrayType(Type::IntegerType(4, true), 4) }; +X86CommonArchitecture::cached_output_types[108] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(4), 2), Type::ArrayType(Type::IntegerType(4, true), 2) }; +X86CommonArchitecture::cached_output_types[109] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(8, false), 4), Type::ArrayType(Type::IntegerType(8, true), 4) }; +X86CommonArchitecture::cached_output_types[110] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(8, false), 2), Type::ArrayType(Type::IntegerType(8, true), 2) }; +X86CommonArchitecture::cached_output_types[111] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, false), 8), Type::ArrayType(Type::IntegerType(4, true), 8) }; +X86CommonArchitecture::cached_output_types[112] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, false), 4), Type::ArrayType(Type::IntegerType(4, true), 4) }; +X86CommonArchitecture::cached_output_types[113] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, false), 2), Type::ArrayType(Type::IntegerType(4, true), 2) }; +X86CommonArchitecture::cached_output_types[114] = vector<Confidence<Ref<Type>>> { Type::BoolType() }; +X86CommonArchitecture::cached_output_types[115] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(4), 16) }; +X86CommonArchitecture::cached_output_types[116] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(8), 8) }; +X86CommonArchitecture::cached_output_types[117] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, false), 16) }; +X86CommonArchitecture::cached_output_types[118] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(8, false), 8) }; +X86CommonArchitecture::cached_output_types[119] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(2), 16) }; +X86CommonArchitecture::cached_output_types[120] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(8), 8), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[121] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(8), 2), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[122] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(8), 4), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[123] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(4), 16), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[124] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(4), 4), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[125] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::FloatType(4), 8), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[126] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(8, true), 8) }; +X86CommonArchitecture::cached_output_types[127] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, false), 16), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[128] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, false), 4), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[129] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(4, false), 8), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[130] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(8, false), 8), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[131] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(8, false), 2), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[132] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(8, false), 4), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[133] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(1, false), 4) }; +X86CommonArchitecture::cached_output_types[134] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(1, false), 2) }; +X86CommonArchitecture::cached_output_types[135] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(2, false), 2) }; +X86CommonArchitecture::cached_output_types[136] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(1, true), 4) }; +X86CommonArchitecture::cached_output_types[137] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(1, true), 2) }; +X86CommonArchitecture::cached_output_types[138] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(2, true), 2) }; +X86CommonArchitecture::cached_output_types[139] = vector<Confidence<Ref<Type>>> { Type::IntegerType(4, false), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[140] = vector<Confidence<Ref<Type>>> { Type::IntegerType(8, false), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[141] = vector<Confidence<Ref<Type>>> { Type::FloatType(8), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[142] = vector<Confidence<Ref<Type>>> { Type::FloatType(4), Type::BoolType() }; +X86CommonArchitecture::cached_output_types[143] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(2, false), 32) }; +X86CommonArchitecture::cached_output_types[144] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(1, false), 64) }; +X86CommonArchitecture::cached_output_types[145] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(1, true), 64) }; +X86CommonArchitecture::cached_output_types[146] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(2, true), 32) }; +X86CommonArchitecture::cached_output_types[147] = vector<Confidence<Ref<Type>>> { Type::ArrayType(Type::IntegerType(16, false), 4) }; diff --git a/arch/x86/x86_intrinsic_input_type.include b/arch/x86/x86_intrinsic_input_type.include new file mode 100644 index 00000000..f7cf9535 --- /dev/null +++ b/arch/x86/x86_intrinsic_input_type.include @@ -0,0 +1,12670 @@ +// Generated file, please do not edit directly + +case INTRINSIC_XED_IFORM_FADD_ST0_MEMmem32real: + return X86CommonArchitecture::cached_input_types[0]; +case INTRINSIC_XED_IFORM_FADD_ST0_X87: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FADD_ST0_MEMm64real: + return X86CommonArchitecture::cached_input_types[2]; +case INTRINSIC_XED_IFORM_FADD_X87_ST0: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FMUL_ST0_MEMmem32real: + return X86CommonArchitecture::cached_input_types[0]; +case INTRINSIC_XED_IFORM_FMUL_ST0_X87: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FMUL_ST0_MEMm64real: + return X86CommonArchitecture::cached_input_types[2]; +case INTRINSIC_XED_IFORM_FMUL_X87_ST0: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FCOMP_ST0_MEMmem32real: + return X86CommonArchitecture::cached_input_types[3]; +case INTRINSIC_XED_IFORM_FCOMP_ST0_X87: + return X86CommonArchitecture::cached_input_types[4]; +case INTRINSIC_XED_IFORM_FCOMP_ST0_X87_DCD1: + return X86CommonArchitecture::cached_input_types[4]; +case INTRINSIC_XED_IFORM_FCOMP_ST0_X87_DED0: + return X86CommonArchitecture::cached_input_types[4]; +case INTRINSIC_XED_IFORM_FCOMP_ST0_MEMm64real: + return X86CommonArchitecture::cached_input_types[5]; +case INTRINSIC_XED_IFORM_FSUB_ST0_MEMmem32real: + return X86CommonArchitecture::cached_input_types[0]; +case INTRINSIC_XED_IFORM_FSUB_ST0_X87: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FSUB_ST0_MEMm64real: + return X86CommonArchitecture::cached_input_types[2]; +case INTRINSIC_XED_IFORM_FSUB_X87_ST0: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FSUBR_ST0_MEMmem32real: + return X86CommonArchitecture::cached_input_types[0]; +case INTRINSIC_XED_IFORM_FSUBR_ST0_X87: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FSUBR_ST0_MEMm64real: + return X86CommonArchitecture::cached_input_types[2]; +case INTRINSIC_XED_IFORM_FSUBR_X87_ST0: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FDIV_ST0_MEMmem32real: + return X86CommonArchitecture::cached_input_types[0]; +case INTRINSIC_XED_IFORM_FDIV_ST0_X87: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FDIV_ST0_MEMm64real: + return X86CommonArchitecture::cached_input_types[2]; +case INTRINSIC_XED_IFORM_FDIV_X87_ST0: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FDIVR_ST0_MEMmem32real: + return X86CommonArchitecture::cached_input_types[0]; +case INTRINSIC_XED_IFORM_FDIVR_ST0_X87: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FDIVR_ST0_MEMm64real: + return X86CommonArchitecture::cached_input_types[2]; +case INTRINSIC_XED_IFORM_FDIVR_X87_ST0: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FCOM_ST0_MEMmem32real: + return X86CommonArchitecture::cached_input_types[0]; +case INTRINSIC_XED_IFORM_FCOM_ST0_MEMm64real: + return X86CommonArchitecture::cached_input_types[2]; +case INTRINSIC_XED_IFORM_FCOM_ST0_X87: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FCOM_ST0_X87_DCD0: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FLD_ST0_MEMmem32real: + return X86CommonArchitecture::cached_input_types[6]; +case INTRINSIC_XED_IFORM_FLD_ST0_X87: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FLD_ST0_MEMmem80real: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FLD_ST0_MEMm64real: + return X86CommonArchitecture::cached_input_types[8]; +case INTRINSIC_XED_IFORM_FST_MEMmem32real_ST0: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FST_MEMm64real_ST0: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FST_X87_ST0: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FSTP_MEMmem32real_ST0: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FSTP_MEMmem80real_ST0: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FSTP_MEMm64real_ST0: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FSTP_X87_ST0: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FSTP_X87_ST0_DFD0: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FSTP_X87_ST0_DFD1: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FSTPNCE_X87_ST0: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FLDENV_MEMmem14: + return X86CommonArchitecture::cached_input_types[10]; +case INTRINSIC_XED_IFORM_FLDENV_MEMmem28: + return X86CommonArchitecture::cached_input_types[11]; +case INTRINSIC_XED_IFORM_FLDCW_MEMmem16: + return X86CommonArchitecture::cached_input_types[12]; +case INTRINSIC_XED_IFORM_FNSTENV_MEMmem14: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_FNSTENV_MEMmem28: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_FNSTCW_MEMmem16: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_FXCH_ST0_X87: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FXCH_ST0_X87_DFC1: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FXCH_ST0_X87_DDC1: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FNOP: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_FCHS: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FABS: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FTST: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FXAM: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FLD1: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_FLDL2T: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_FLDL2E: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_FLDPI: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_FLDLG2: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_FLDLN2: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_FLDZ: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_F2XM1: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FYL2X: + return X86CommonArchitecture::cached_input_types[4]; +case INTRINSIC_XED_IFORM_FPTAN: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FPATAN: + return X86CommonArchitecture::cached_input_types[4]; +case INTRINSIC_XED_IFORM_FXTRACT: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FPREM1: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FDECSTP: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_FINCSTP: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_FPREM: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FYL2XP1: + return X86CommonArchitecture::cached_input_types[4]; +case INTRINSIC_XED_IFORM_FSQRT: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FSINCOS: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FRNDINT: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FSCALE: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FSIN: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FCOS: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FIADD_ST0_MEMmem32int: + return X86CommonArchitecture::cached_input_types[16]; +case INTRINSIC_XED_IFORM_FIADD_ST0_MEMmem16int: + return X86CommonArchitecture::cached_input_types[17]; +case INTRINSIC_XED_IFORM_FIMUL_ST0_MEMmem32int: + return X86CommonArchitecture::cached_input_types[16]; +case INTRINSIC_XED_IFORM_FIMUL_ST0_MEMmem16int: + return X86CommonArchitecture::cached_input_types[17]; +case INTRINSIC_XED_IFORM_FICOM_ST0_MEMmem32int: + return X86CommonArchitecture::cached_input_types[16]; +case INTRINSIC_XED_IFORM_FICOM_ST0_MEMmem16int: + return X86CommonArchitecture::cached_input_types[17]; +case INTRINSIC_XED_IFORM_FICOMP_ST0_MEMmem32int: + return X86CommonArchitecture::cached_input_types[18]; +case INTRINSIC_XED_IFORM_FICOMP_ST0_MEMmem16int: + return X86CommonArchitecture::cached_input_types[19]; +case INTRINSIC_XED_IFORM_FISUB_ST0_MEMmem32int: + return X86CommonArchitecture::cached_input_types[16]; +case INTRINSIC_XED_IFORM_FISUB_ST0_MEMmem16int: + return X86CommonArchitecture::cached_input_types[17]; +case INTRINSIC_XED_IFORM_FISUBR_ST0_MEMmem32int: + return X86CommonArchitecture::cached_input_types[16]; +case INTRINSIC_XED_IFORM_FISUBR_ST0_MEMmem16int: + return X86CommonArchitecture::cached_input_types[17]; +case INTRINSIC_XED_IFORM_FIDIV_ST0_MEMmem32int: + return X86CommonArchitecture::cached_input_types[16]; +case INTRINSIC_XED_IFORM_FIDIV_ST0_MEMmem16int: + return X86CommonArchitecture::cached_input_types[17]; +case INTRINSIC_XED_IFORM_FIDIVR_ST0_MEMmem32int: + return X86CommonArchitecture::cached_input_types[16]; +case INTRINSIC_XED_IFORM_FIDIVR_ST0_MEMmem16int: + return X86CommonArchitecture::cached_input_types[17]; +case INTRINSIC_XED_IFORM_FCMOVB_ST0_X87: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FCMOVE_ST0_X87: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FCMOVBE_ST0_X87: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FCMOVU_ST0_X87: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FUCOMPP: + return X86CommonArchitecture::cached_input_types[20]; +case INTRINSIC_XED_IFORM_FILD_ST0_MEMmem32int: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_FILD_ST0_MEMmem16int: + return X86CommonArchitecture::cached_input_types[22]; +case INTRINSIC_XED_IFORM_FILD_ST0_MEMm64int: + return X86CommonArchitecture::cached_input_types[23]; +case INTRINSIC_XED_IFORM_FISTTP_MEMmem32int_ST0: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FISTTP_MEMm64int_ST0: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FISTTP_MEMmem16int_ST0: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FIST_MEMmem32int_ST0: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FIST_MEMmem16int_ST0: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FISTP_MEMmem32int_ST0: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FISTP_MEMmem16int_ST0: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FISTP_MEMm64int_ST0: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FCMOVNB_ST0_X87: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FCMOVNE_ST0_X87: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FCMOVNBE_ST0_X87: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FCMOVNU_ST0_X87: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FNCLEX: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_FNINIT: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_FSETPM287_NOP: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_FENI8087_NOP: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_FDISI8087_NOP: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_FUCOMI_ST0_X87: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FCOMI_ST0_X87: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FRSTOR_MEMmem94: + return X86CommonArchitecture::cached_input_types[24]; +case INTRINSIC_XED_IFORM_FRSTOR_MEMmem108: + return X86CommonArchitecture::cached_input_types[25]; +case INTRINSIC_XED_IFORM_FNSAVE_MEMmem94: + return X86CommonArchitecture::cached_input_types[26]; +case INTRINSIC_XED_IFORM_FNSAVE_MEMmem108: + return X86CommonArchitecture::cached_input_types[26]; +case INTRINSIC_XED_IFORM_FNSTSW_MEMmem16: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_FNSTSW_AX: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_FFREE_X87: + return X86CommonArchitecture::cached_input_types[9]; +case INTRINSIC_XED_IFORM_FUCOM_ST0_X87: + return X86CommonArchitecture::cached_input_types[1]; +case INTRINSIC_XED_IFORM_FUCOMP_ST0_X87: + return X86CommonArchitecture::cached_input_types[20]; +case INTRINSIC_XED_IFORM_FADDP_X87_ST0: + return X86CommonArchitecture::cached_input_types[4]; +case INTRINSIC_XED_IFORM_FMULP_X87_ST0: + return X86CommonArchitecture::cached_input_types[4]; +case INTRINSIC_XED_IFORM_FCOMPP: + return X86CommonArchitecture::cached_input_types[20]; +case INTRINSIC_XED_IFORM_FSUBRP_X87_ST0: + return X86CommonArchitecture::cached_input_types[4]; +case INTRINSIC_XED_IFORM_FSUBP_X87_ST0: + return X86CommonArchitecture::cached_input_types[4]; +case INTRINSIC_XED_IFORM_FDIVRP_X87_ST0: + return X86CommonArchitecture::cached_input_types[4]; +case INTRINSIC_XED_IFORM_FDIVP_X87_ST0: + return X86CommonArchitecture::cached_input_types[4]; +case INTRINSIC_XED_IFORM_FBLD_ST0_MEMmem80dec: + return X86CommonArchitecture::cached_input_types[27]; +case INTRINSIC_XED_IFORM_FBSTP_MEMmem80dec_ST0: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FFREEP_X87: + return X86CommonArchitecture::cached_input_types[7]; +case INTRINSIC_XED_IFORM_FUCOMIP_ST0_X87: + return X86CommonArchitecture::cached_input_types[4]; +case INTRINSIC_XED_IFORM_FCOMIP_ST0_X87: + return X86CommonArchitecture::cached_input_types[4]; +case INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_ADD_MEMb_IMMb_80r0: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ADD_GPR8_IMMb_80r0: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ADD_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_ADD_GPRv_IMMz: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_ADD_MEMb_IMMb_82r0: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ADD_GPR8_IMMb_82r0: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ADD_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_ADD_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_ADD_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_ADD_GPR8_GPR8_00: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_ADD_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_01: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_ADD_GPR8_MEMb: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_ADD_GPR8_GPR8_02: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_ADD_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[32]; +case INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_03: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_ADD_AL_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ADD_OrAX_IMMz: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_OR_LOCK_MEMb_IMMb_80r1: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_OR_LOCK_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_OR_LOCK_MEMb_IMMb_82r1: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_OR_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_OR_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_OR_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_OR_MEMb_IMMb_80r1: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_OR_GPR8_IMMb_80r1: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_OR_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_OR_GPRv_IMMz: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_OR_MEMb_IMMb_82r1: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_OR_GPR8_IMMb_82r1: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_OR_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_OR_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_OR_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_OR_GPR8_GPR8_08: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_OR_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_OR_GPRv_GPRv_09: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_OR_GPR8_MEMb: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_OR_GPR8_GPR8_0A: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_OR_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[32]; +case INTRINSIC_XED_IFORM_OR_GPRv_GPRv_0B: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_OR_AL_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_OR_OrAX_IMMz: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[35]; +case INTRINSIC_XED_IFORM_ADC_MEMb_IMMb_80r2: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_ADC_GPR8_IMMb_80r2: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_ADC_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_ADC_GPRv_IMMz: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_ADC_MEMb_IMMb_82r2: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_ADC_GPR8_IMMb_82r2: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_ADC_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_ADC_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_ADC_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_ADC_GPR8_GPR8_10: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_ADC_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[35]; +case INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_11: + return X86CommonArchitecture::cached_input_types[36]; +case INTRINSIC_XED_IFORM_ADC_GPR8_MEMb: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_ADC_GPR8_GPR8_12: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_ADC_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[37]; +case INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_13: + return X86CommonArchitecture::cached_input_types[36]; +case INTRINSIC_XED_IFORM_ADC_AL_IMMb: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_ADC_OrAX_IMMz: + return X86CommonArchitecture::cached_input_types[38]; +case INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[35]; +case INTRINSIC_XED_IFORM_SBB_MEMb_IMMb_80r3: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_SBB_GPR8_IMMb_80r3: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_SBB_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_SBB_GPRv_IMMz: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_SBB_MEMb_IMMb_82r3: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_SBB_GPR8_IMMb_82r3: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_SBB_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_SBB_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_SBB_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_SBB_GPR8_GPR8_18: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_SBB_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[35]; +case INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_19: + return X86CommonArchitecture::cached_input_types[36]; +case INTRINSIC_XED_IFORM_SBB_GPR8_GPR8_1A: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_SBB_GPR8_MEMb: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_1B: + return X86CommonArchitecture::cached_input_types[36]; +case INTRINSIC_XED_IFORM_SBB_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[37]; +case INTRINSIC_XED_IFORM_SBB_AL_IMMb: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_SBB_OrAX_IMMz: + return X86CommonArchitecture::cached_input_types[38]; +case INTRINSIC_XED_IFORM_AND_LOCK_MEMb_IMMb_80r4: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_AND_LOCK_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_AND_LOCK_MEMb_IMMb_82r4: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_AND_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_AND_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_AND_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_AND_MEMb_IMMb_80r4: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_AND_GPR8_IMMb_80r4: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_AND_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_AND_GPRv_IMMz: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_AND_MEMb_IMMb_82r4: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_AND_GPR8_IMMb_82r4: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_AND_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_AND_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_AND_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_AND_GPR8_GPR8_20: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_AND_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_AND_GPRv_GPRv_21: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_AND_GPR8_GPR8_22: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_AND_GPR8_MEMb: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_AND_GPRv_GPRv_23: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_AND_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[32]; +case INTRINSIC_XED_IFORM_AND_AL_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_AND_OrAX_IMMz: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_SUB_MEMb_IMMb_80r5: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SUB_GPR8_IMMb_80r5: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SUB_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_SUB_GPRv_IMMz: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SUB_MEMb_IMMb_82r5: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SUB_GPR8_IMMb_82r5: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SUB_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_SUB_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SUB_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_SUB_GPR8_GPR8_28: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_SUB_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_SUB_GPRv_GPRv_29: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_SUB_GPR8_GPR8_2A: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_SUB_GPR8_MEMb: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_SUB_GPRv_GPRv_2B: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_SUB_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[32]; +case INTRINSIC_XED_IFORM_SUB_AL_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SUB_OrAX_IMMz: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_XOR_MEMb_IMMb_80r6: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_XOR_GPR8_IMMb_80r6: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_XOR_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_XOR_GPRv_IMMz: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_XOR_MEMb_IMMb_82r6: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_XOR_GPR8_IMMb_82r6: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_XOR_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_XOR_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_XOR_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_XOR_GPR8_GPR8_30: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_XOR_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_XOR_GPRv_GPRv_31: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_XOR_GPR8_GPR8_32: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_XOR_GPR8_MEMb: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_XOR_GPRv_GPRv_33: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_XOR_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[32]; +case INTRINSIC_XED_IFORM_XOR_AL_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_XOR_OrAX_IMMz: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_CMP_MEMb_IMMb_80r7: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_CMP_GPR8_IMMb_80r7: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_CMP_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_CMP_GPRv_IMMz: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_CMP_MEMb_IMMb_82r7: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_CMP_GPR8_IMMb_82r7: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_CMP_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_CMP_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_CMP_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_CMP_GPR8_GPR8_38: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_CMP_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMP_GPRv_GPRv_39: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMP_GPR8_MEMb: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_CMP_GPR8_GPR8_3A: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_CMP_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[32]; +case INTRINSIC_XED_IFORM_CMP_GPRv_GPRv_3B: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMP_AL_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_CMP_OrAX_IMMz: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_POP_MEMv: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_POP_GPRv_8F: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_POP_ES: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_POP_SS: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_POP_DS: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_POP_GPRv_58: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_POP_FS: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_POP_GS: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_ROL_MEMb_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ROL_GPR8_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ROL_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_ROL_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_ROL_MEMb_ONE: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ROL_GPR8_ONE: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ROL_MEMv_ONE: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_ROL_GPRv_ONE: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_ROL_MEMb_CL: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_ROL_GPR8_CL: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_ROL_MEMv_CL: + return X86CommonArchitecture::cached_input_types[40]; +case INTRINSIC_XED_IFORM_ROL_GPRv_CL: + return X86CommonArchitecture::cached_input_types[41]; +case INTRINSIC_XED_IFORM_ROR_MEMb_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ROR_GPR8_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ROR_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_ROR_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_ROR_MEMb_ONE: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ROR_GPR8_ONE: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ROR_MEMv_ONE: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_ROR_GPRv_ONE: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_ROR_MEMb_CL: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_ROR_GPR8_CL: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_ROR_MEMv_CL: + return X86CommonArchitecture::cached_input_types[40]; +case INTRINSIC_XED_IFORM_ROR_GPRv_CL: + return X86CommonArchitecture::cached_input_types[41]; +case INTRINSIC_XED_IFORM_RCL_MEMb_IMMb: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_RCL_GPR8_IMMb: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_RCL_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_RCL_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_RCL_MEMb_ONE: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_RCL_GPR8_ONE: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_RCL_MEMv_ONE: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_RCL_GPRv_ONE: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_RCL_MEMb_CL: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_RCL_GPR8_CL: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_RCL_MEMv_CL: + return X86CommonArchitecture::cached_input_types[42]; +case INTRINSIC_XED_IFORM_RCL_GPRv_CL: + return X86CommonArchitecture::cached_input_types[43]; +case INTRINSIC_XED_IFORM_RCR_MEMb_IMMb: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_RCR_GPR8_IMMb: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_RCR_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_RCR_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_RCR_MEMb_ONE: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_RCR_GPR8_ONE: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_RCR_MEMv_ONE: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_RCR_GPRv_ONE: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_RCR_MEMb_CL: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_RCR_GPR8_CL: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_RCR_MEMv_CL: + return X86CommonArchitecture::cached_input_types[42]; +case INTRINSIC_XED_IFORM_RCR_GPRv_CL: + return X86CommonArchitecture::cached_input_types[43]; +case INTRINSIC_XED_IFORM_SHL_MEMb_IMMb_C0r4: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SHL_GPR8_IMMb_C0r4: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SHL_MEMb_IMMb_C0r6: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SHL_GPR8_IMMb_C0r6: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SHL_MEMv_IMMb_C1r4: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_SHL_GPRv_IMMb_C1r4: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SHL_MEMv_IMMb_C1r6: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_SHL_GPRv_IMMb_C1r6: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SHL_MEMb_ONE_D0r4: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SHL_GPR8_ONE_D0r4: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SHL_MEMb_ONE_D0r6: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SHL_GPR8_ONE_D0r6: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SHL_MEMv_ONE_D1r6: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_SHL_GPRv_ONE_D1r6: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SHL_MEMv_ONE_D1r4: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_SHL_GPRv_ONE_D1r4: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SHL_MEMb_CL_D2r4: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_SHL_GPR8_CL_D2r4: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_SHL_MEMb_CL_D2r6: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_SHL_GPR8_CL_D2r6: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_SHL_MEMv_CL_D3r4: + return X86CommonArchitecture::cached_input_types[40]; +case INTRINSIC_XED_IFORM_SHL_GPRv_CL_D3r4: + return X86CommonArchitecture::cached_input_types[41]; +case INTRINSIC_XED_IFORM_SHL_MEMv_CL_D3r6: + return X86CommonArchitecture::cached_input_types[40]; +case INTRINSIC_XED_IFORM_SHL_GPRv_CL_D3r6: + return X86CommonArchitecture::cached_input_types[41]; +case INTRINSIC_XED_IFORM_SHR_MEMb_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SHR_GPR8_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SHR_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_SHR_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SHR_MEMb_ONE: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SHR_GPR8_ONE: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SHR_MEMv_ONE: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_SHR_GPRv_ONE: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SHR_MEMb_CL: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_SHR_GPR8_CL: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_SHR_MEMv_CL: + return X86CommonArchitecture::cached_input_types[40]; +case INTRINSIC_XED_IFORM_SHR_GPRv_CL: + return X86CommonArchitecture::cached_input_types[41]; +case INTRINSIC_XED_IFORM_SAR_MEMb_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SAR_GPR8_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SAR_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_SAR_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SAR_MEMb_ONE: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SAR_GPR8_ONE: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SAR_MEMv_ONE: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_SAR_GPRv_ONE: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SAR_MEMb_CL: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_SAR_GPR8_CL: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_SAR_MEMv_CL: + return X86CommonArchitecture::cached_input_types[40]; +case INTRINSIC_XED_IFORM_SAR_GPRv_CL: + return X86CommonArchitecture::cached_input_types[41]; +case INTRINSIC_XED_IFORM_TEST_MEMb_IMMb_F6r0: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_TEST_MEMb_IMMb_F6r1: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_TEST_GPR8_IMMb_F6r0: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_TEST_GPR8_IMMb_F6r1: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_TEST_MEMv_IMMz_F7r0: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_TEST_MEMv_IMMz_F7r1: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_TEST_GPRv_IMMz_F7r0: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_TEST_GPRv_IMMz_F7r1: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_TEST_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_TEST_GPR8_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_TEST_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_TEST_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_TEST_AL_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_TEST_OrAX_IMMz: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_NOT_LOCK_MEMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_NOT_LOCK_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_NOT_MEMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_NOT_GPR8: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_NOT_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_NOT_GPRv: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_NEG_LOCK_MEMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_NEG_LOCK_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_NEG_MEMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_NEG_GPR8: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_NEG_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_NEG_GPRv: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_MUL_MEMb: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_MUL_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_MUL_MEMv: + return X86CommonArchitecture::cached_input_types[44]; +case INTRINSIC_XED_IFORM_MUL_GPRv: + return X86CommonArchitecture::cached_input_types[45]; +case INTRINSIC_XED_IFORM_IMUL_MEMb: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_IMUL_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_IMUL_MEMv: + return X86CommonArchitecture::cached_input_types[44]; +case INTRINSIC_XED_IFORM_IMUL_GPRv: + return X86CommonArchitecture::cached_input_types[45]; +case INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_IMMz: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[32]; +case INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_DIV_MEMb: + return X86CommonArchitecture::cached_input_types[46]; +case INTRINSIC_XED_IFORM_DIV_GPR8: + return X86CommonArchitecture::cached_input_types[46]; +case INTRINSIC_XED_IFORM_DIV_MEMv: + return X86CommonArchitecture::cached_input_types[47]; +case INTRINSIC_XED_IFORM_DIV_GPRv: + return X86CommonArchitecture::cached_input_types[48]; +case INTRINSIC_XED_IFORM_IDIV_MEMb: + return X86CommonArchitecture::cached_input_types[46]; +case INTRINSIC_XED_IFORM_IDIV_GPR8: + return X86CommonArchitecture::cached_input_types[46]; +case INTRINSIC_XED_IFORM_IDIV_MEMv: + return X86CommonArchitecture::cached_input_types[47]; +case INTRINSIC_XED_IFORM_IDIV_GPRv: + return X86CommonArchitecture::cached_input_types[48]; +case INTRINSIC_XED_IFORM_INC_LOCK_MEMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_INC_LOCK_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_INC_MEMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_INC_GPR8: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_INC_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_INC_GPRv_FFr0: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_INC_GPRv_40: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_DEC_LOCK_MEMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_DEC_LOCK_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_DEC_MEMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_DEC_GPR8: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_DEC_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_DEC_GPRv_FFr1: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_DEC_GPRv_48: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_CALL_NEAR_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CALL_NEAR_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CALL_NEAR_RELBRz: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_CALL_NEAR_RELBRd: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_JMP_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_JMP_GPRv: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_JMP_RELBRz: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_JMP_RELBRd: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_JMP_RELBRb: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_JMP_FAR_MEMp2: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_JMP_FAR_PTRp_IMMw: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_PUSH_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_PUSH_GPRv_FFr6: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_PUSH_ES: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_PUSH_CS: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_PUSH_SS: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_PUSH_DS: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_PUSH_GPRv_50: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_PUSH_IMMz: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_PUSH_IMMb: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_PUSH_FS: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_PUSH_GS: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_SLDT_MEMw: + return X86CommonArchitecture::cached_input_types[50]; +case INTRINSIC_XED_IFORM_SLDT_GPRv: + return X86CommonArchitecture::cached_input_types[50]; +case INTRINSIC_XED_IFORM_STR_MEMw: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_STR_GPRv: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_LLDT_MEMw: + return X86CommonArchitecture::cached_input_types[51]; +case INTRINSIC_XED_IFORM_LLDT_GPR16: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_LTR_MEMw: + return X86CommonArchitecture::cached_input_types[51]; +case INTRINSIC_XED_IFORM_LTR_GPR16: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_VERR_MEMw: + return X86CommonArchitecture::cached_input_types[51]; +case INTRINSIC_XED_IFORM_VERR_GPR16: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_VERW_MEMw: + return X86CommonArchitecture::cached_input_types[51]; +case INTRINSIC_XED_IFORM_VERW_GPR16: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_LGDT_MEMs64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_LGDT_MEMs: + return X86CommonArchitecture::cached_input_types[52]; +case INTRINSIC_XED_IFORM_SMSW_MEMw: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SMSW_GPRv: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_LMSW_MEMw: + return X86CommonArchitecture::cached_input_types[51]; +case INTRINSIC_XED_IFORM_LMSW_GPR16: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_BT_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BT_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_BT_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_BT_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_BTS_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BTS_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_BTS_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BTS_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_BTS_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_BTS_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_BTR_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BTR_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_BTR_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BTR_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_BTR_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_BTR_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_BTC_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BTC_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_BTC_MEMv_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BTC_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_BTC_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_BTC_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_VMCLEAR_MEMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_VMPTRLD_MEMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_VMPTRST_MEMq: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_VMXON_MEMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_CMPXCHG8B_LOCK_MEMq: + return X86CommonArchitecture::cached_input_types[54]; +case INTRINSIC_XED_IFORM_CMPXCHG8B_MEMq: + return X86CommonArchitecture::cached_input_types[54]; +case INTRINSIC_XED_IFORM_CMPXCHG16B_LOCK_MEMdq: + return X86CommonArchitecture::cached_input_types[55]; +case INTRINSIC_XED_IFORM_CMPXCHG16B_MEMdq: + return X86CommonArchitecture::cached_input_types[55]; +case INTRINSIC_XED_IFORM_MOV_GPR8_IMMb_C6r0: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_MOV_MEMb_IMMb: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_MOV_GPRv_IMMz: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_MOV_MEMv_IMMz: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_MOV_GPR8_GPR8_88: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_MOV_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_MOV_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_MOV_GPRv_GPRv_89: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_MOV_GPR8_MEMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_MOV_GPR8_GPR8_8A: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_MOV_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_MOV_GPRv_GPRv_8B: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_MOV_MEMw_SEG: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_MOV_GPRv_SEG: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_MOV_SEG_MEMw: + return X86CommonArchitecture::cached_input_types[51]; +case INTRINSIC_XED_IFORM_MOV_SEG_GPR16: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_MOV_AL_MEMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_MOV_OrAX_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_MOV_MEMb_AL: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_MOV_MEMv_OrAX: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_MOV_GPR8_IMMb_B0: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_MOV_GPRv_IMMv: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_PSRLW_MMXq_IMMb: + return X86CommonArchitecture::cached_input_types[56]; +case INTRINSIC_XED_IFORM_PSRLW_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_PSRLW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[58]; +case INTRINSIC_XED_IFORM_PSRLW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[58]; +case INTRINSIC_XED_IFORM_PSRLW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSRLW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSRAW_MMXq_IMMb: + return X86CommonArchitecture::cached_input_types[60]; +case INTRINSIC_XED_IFORM_PSRAW_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[61]; +case INTRINSIC_XED_IFORM_PSRAW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[62]; +case INTRINSIC_XED_IFORM_PSRAW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[62]; +case INTRINSIC_XED_IFORM_PSRAW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[63]; +case INTRINSIC_XED_IFORM_PSRAW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[63]; +case INTRINSIC_XED_IFORM_PSLLW_MMXq_IMMb: + return X86CommonArchitecture::cached_input_types[56]; +case INTRINSIC_XED_IFORM_PSLLW_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_PSLLW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[58]; +case INTRINSIC_XED_IFORM_PSLLW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[58]; +case INTRINSIC_XED_IFORM_PSLLW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[64]; +case INTRINSIC_XED_IFORM_PSLLW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[64]; +case INTRINSIC_XED_IFORM_PSRLD_MMXq_IMMb: + return X86CommonArchitecture::cached_input_types[65]; +case INTRINSIC_XED_IFORM_PSRLD_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_PSRLD_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[67]; +case INTRINSIC_XED_IFORM_PSRLD_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[67]; +case INTRINSIC_XED_IFORM_PSRLD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSRLD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSRAD_MMXq_IMMb: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_PSRAD_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PSRAD_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[70]; +case INTRINSIC_XED_IFORM_PSRAD_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[70]; +case INTRINSIC_XED_IFORM_PSRAD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[71]; +case INTRINSIC_XED_IFORM_PSRAD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[71]; +case INTRINSIC_XED_IFORM_PSLLD_MMXq_IMMb: + return X86CommonArchitecture::cached_input_types[65]; +case INTRINSIC_XED_IFORM_PSLLD_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_PSLLD_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[67]; +case INTRINSIC_XED_IFORM_PSLLD_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[67]; +case INTRINSIC_XED_IFORM_PSLLD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSLLD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSRLQ_MMXq_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_PSRLQ_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[72]; +case INTRINSIC_XED_IFORM_PSRLQ_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[73]; +case INTRINSIC_XED_IFORM_PSRLQ_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[73]; +case INTRINSIC_XED_IFORM_PSRLQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSRLQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSLLQ_MMXq_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_PSLLQ_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[72]; +case INTRINSIC_XED_IFORM_PSLLQ_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[73]; +case INTRINSIC_XED_IFORM_PSLLQ_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[73]; +case INTRINSIC_XED_IFORM_PSLLQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_PSLLQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_PSRLDQ_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[12]; +case INTRINSIC_XED_IFORM_PSLLDQ_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[12]; +case INTRINSIC_XED_IFORM_FXSAVE_MEMmfpxenv: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_FXRSTOR_MEMmfpxenv: + return X86CommonArchitecture::cached_input_types[75]; +case INTRINSIC_XED_IFORM_FXSAVE64_MEMmfpxenv: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_FXRSTOR64_MEMmfpxenv: + return X86CommonArchitecture::cached_input_types[75]; +case INTRINSIC_XED_IFORM_LDMXCSR_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_STMXCSR_MEMd: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_PREFETCHNTA_MEMmprefetch: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PREFETCHT0_MEMmprefetch: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PREFETCHT1_MEMmprefetch: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PREFETCHT2_MEMmprefetch: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r0: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r1: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r2: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r3: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_NOP_MEMv_0F18r4: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r4: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_NOP_MEMv_0F18r5: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r5: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_NOP_MEMv_0F18r6: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r6: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_NOP_MEMv_0F18r7: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r7: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F19: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F19: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1D: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1D: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1F: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1F: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_NOP_90: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F0D: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1A: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1B: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_NOP_GPRv_MEMv_0F1A: + return X86CommonArchitecture::cached_input_types[32]; +case INTRINSIC_XED_IFORM_NOP_GPRv_MEM_0F1B: + return X86CommonArchitecture::cached_input_types[32]; +case INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1E: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1E: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1C: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1C: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_VMCALL: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_VMLAUNCH: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_VMRESUME: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_VMXOFF: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_SGDT_MEMs64: + return X86CommonArchitecture::cached_input_types[50]; +case INTRINSIC_XED_IFORM_SGDT_MEMs: + return X86CommonArchitecture::cached_input_types[50]; +case INTRINSIC_XED_IFORM_LIDT_MEMs64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_LIDT_MEMs: + return X86CommonArchitecture::cached_input_types[52]; +case INTRINSIC_XED_IFORM_MONITOR: + return X86CommonArchitecture::cached_input_types[76]; +case INTRINSIC_XED_IFORM_MWAIT: + return X86CommonArchitecture::cached_input_types[77]; +case INTRINSIC_XED_IFORM_SIDT_MEMs: + return X86CommonArchitecture::cached_input_types[50]; +case INTRINSIC_XED_IFORM_SIDT_MEMs64: + return X86CommonArchitecture::cached_input_types[50]; +case INTRINSIC_XED_IFORM_INVLPG_MEMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_SWAPGS: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_RDTSCP: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_SFENCE: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_CLFLUSH_MEMmprefetch: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_LFENCE: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_MFENCE: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_MOVHLPS_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[78]; +case INTRINSIC_XED_IFORM_MOVLPS_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[78]; +case INTRINSIC_XED_IFORM_MOVLPS_MEMq_XMMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVLHPS_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[78]; +case INTRINSIC_XED_IFORM_MOVHPS_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[78]; +case INTRINSIC_XED_IFORM_MOVHPS_MEMq_XMMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_DAA: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_DAS: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_AAA: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_AAS: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_PUSHA: + return X86CommonArchitecture::cached_input_types[80]; +case INTRINSIC_XED_IFORM_PUSHAD: + return X86CommonArchitecture::cached_input_types[81]; +case INTRINSIC_XED_IFORM_POPA: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_POPAD: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_BOUND_GPRv_MEMa16: + return X86CommonArchitecture::cached_input_types[82]; +case INTRINSIC_XED_IFORM_BOUND_GPRv_MEMa32: + return X86CommonArchitecture::cached_input_types[32]; +case INTRINSIC_XED_IFORM_ARPL_MEMw_GPR16: + return X86CommonArchitecture::cached_input_types[83]; +case INTRINSIC_XED_IFORM_ARPL_GPR16_GPR16: + return X86CommonArchitecture::cached_input_types[84]; +case INTRINSIC_XED_IFORM_MOVSXD_GPRv_MEMz: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_MOVSXD_GPRv_GPRz: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_REP_INSB: + return X86CommonArchitecture::cached_input_types[85]; +case INTRINSIC_XED_IFORM_INSB: + return X86CommonArchitecture::cached_input_types[38]; +case INTRINSIC_XED_IFORM_REP_INSW: + return X86CommonArchitecture::cached_input_types[85]; +case INTRINSIC_XED_IFORM_INSW: + return X86CommonArchitecture::cached_input_types[38]; +case INTRINSIC_XED_IFORM_REP_INSD: + return X86CommonArchitecture::cached_input_types[85]; +case INTRINSIC_XED_IFORM_INSD: + return X86CommonArchitecture::cached_input_types[38]; +case INTRINSIC_XED_IFORM_REP_OUTSB: + return X86CommonArchitecture::cached_input_types[86]; +case INTRINSIC_XED_IFORM_OUTSB: + return X86CommonArchitecture::cached_input_types[87]; +case INTRINSIC_XED_IFORM_REP_OUTSW: + return X86CommonArchitecture::cached_input_types[88]; +case INTRINSIC_XED_IFORM_OUTSW: + return X86CommonArchitecture::cached_input_types[89]; +case INTRINSIC_XED_IFORM_REP_OUTSD: + return X86CommonArchitecture::cached_input_types[90]; +case INTRINSIC_XED_IFORM_OUTSD: + return X86CommonArchitecture::cached_input_types[91]; +case INTRINSIC_XED_IFORM_JO_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JO_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JO_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JNO_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JNO_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JNO_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JB_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JB_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JB_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JNB_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JNB_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JNB_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JZ_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JZ_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JZ_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JNZ_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JNZ_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JNZ_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JBE_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JBE_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JBE_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JNBE_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JNBE_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JNBE_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JS_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JS_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JS_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JNS_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JNS_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JNS_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JP_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JP_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JP_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JNP_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JNP_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JNP_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JL_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JL_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JL_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JNL_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JNL_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JNL_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JLE_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JLE_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JLE_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JNLE_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_JNLE_RELBRz: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_JNLE_RELBRd: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_XCHG_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_XCHG_GPR8_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_XCHG_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_XCHG_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_XCHG_GPRv_OrAX: + return X86CommonArchitecture::cached_input_types[45]; +case INTRINSIC_XED_IFORM_LEA_GPRv_AGEN: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_PAUSE: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_CBW: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_CDQE: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_CWDE: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_CWD: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_CQO: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_CDQ: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_CALL_FAR_MEMp2: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_CALL_FAR_PTRp_IMMw: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_FWAIT: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_PUSHF: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_PUSHFD: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_PUSHFQ: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_POPF: + return X86CommonArchitecture::cached_input_types[93]; +case INTRINSIC_XED_IFORM_POPFD: + return X86CommonArchitecture::cached_input_types[94]; +case INTRINSIC_XED_IFORM_POPFQ: + return X86CommonArchitecture::cached_input_types[95]; +case INTRINSIC_XED_IFORM_SAHF: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_LAHF: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_REP_MOVSB: + return X86CommonArchitecture::cached_input_types[96]; +case INTRINSIC_XED_IFORM_MOVSB: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_REP_MOVSW: + return X86CommonArchitecture::cached_input_types[97]; +case INTRINSIC_XED_IFORM_MOVSW: + return X86CommonArchitecture::cached_input_types[22]; +case INTRINSIC_XED_IFORM_REP_MOVSD: + return X86CommonArchitecture::cached_input_types[98]; +case INTRINSIC_XED_IFORM_MOVSD: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_REP_MOVSQ: + return X86CommonArchitecture::cached_input_types[99]; +case INTRINSIC_XED_IFORM_MOVSQ: + return X86CommonArchitecture::cached_input_types[23]; +case INTRINSIC_XED_IFORM_REPE_CMPSB: + return X86CommonArchitecture::cached_input_types[100]; +case INTRINSIC_XED_IFORM_REPNE_CMPSB: + return X86CommonArchitecture::cached_input_types[100]; +case INTRINSIC_XED_IFORM_CMPSB: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_REPE_CMPSW: + return X86CommonArchitecture::cached_input_types[101]; +case INTRINSIC_XED_IFORM_REPNE_CMPSW: + return X86CommonArchitecture::cached_input_types[101]; +case INTRINSIC_XED_IFORM_CMPSW: + return X86CommonArchitecture::cached_input_types[93]; +case INTRINSIC_XED_IFORM_REPE_CMPSD: + return X86CommonArchitecture::cached_input_types[102]; +case INTRINSIC_XED_IFORM_REPNE_CMPSD: + return X86CommonArchitecture::cached_input_types[102]; +case INTRINSIC_XED_IFORM_CMPSD: + return X86CommonArchitecture::cached_input_types[94]; +case INTRINSIC_XED_IFORM_REPE_CMPSQ: + return X86CommonArchitecture::cached_input_types[103]; +case INTRINSIC_XED_IFORM_REPNE_CMPSQ: + return X86CommonArchitecture::cached_input_types[103]; +case INTRINSIC_XED_IFORM_CMPSQ: + return X86CommonArchitecture::cached_input_types[95]; +case INTRINSIC_XED_IFORM_REP_STOSB: + return X86CommonArchitecture::cached_input_types[96]; +case INTRINSIC_XED_IFORM_STOSB: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_REP_STOSW: + return X86CommonArchitecture::cached_input_types[85]; +case INTRINSIC_XED_IFORM_STOSW: + return X86CommonArchitecture::cached_input_types[38]; +case INTRINSIC_XED_IFORM_REP_STOSD: + return X86CommonArchitecture::cached_input_types[104]; +case INTRINSIC_XED_IFORM_STOSD: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_REP_STOSQ: + return X86CommonArchitecture::cached_input_types[105]; +case INTRINSIC_XED_IFORM_STOSQ: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_REP_LODSB: + return X86CommonArchitecture::cached_input_types[96]; +case INTRINSIC_XED_IFORM_LODSB: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_REP_LODSW: + return X86CommonArchitecture::cached_input_types[97]; +case INTRINSIC_XED_IFORM_LODSW: + return X86CommonArchitecture::cached_input_types[22]; +case INTRINSIC_XED_IFORM_REP_LODSD: + return X86CommonArchitecture::cached_input_types[98]; +case INTRINSIC_XED_IFORM_LODSD: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_REP_LODSQ: + return X86CommonArchitecture::cached_input_types[99]; +case INTRINSIC_XED_IFORM_LODSQ: + return X86CommonArchitecture::cached_input_types[23]; +case INTRINSIC_XED_IFORM_REPE_SCASB: + return X86CommonArchitecture::cached_input_types[100]; +case INTRINSIC_XED_IFORM_REPNE_SCASB: + return X86CommonArchitecture::cached_input_types[100]; +case INTRINSIC_XED_IFORM_SCASB: + return X86CommonArchitecture::cached_input_types[34]; +case INTRINSIC_XED_IFORM_REPE_SCASW: + return X86CommonArchitecture::cached_input_types[88]; +case INTRINSIC_XED_IFORM_REPNE_SCASW: + return X86CommonArchitecture::cached_input_types[88]; +case INTRINSIC_XED_IFORM_SCASW: + return X86CommonArchitecture::cached_input_types[89]; +case INTRINSIC_XED_IFORM_REPE_SCASD: + return X86CommonArchitecture::cached_input_types[106]; +case INTRINSIC_XED_IFORM_REPNE_SCASD: + return X86CommonArchitecture::cached_input_types[106]; +case INTRINSIC_XED_IFORM_SCASD: + return X86CommonArchitecture::cached_input_types[107]; +case INTRINSIC_XED_IFORM_REPE_SCASQ: + return X86CommonArchitecture::cached_input_types[108]; +case INTRINSIC_XED_IFORM_REPNE_SCASQ: + return X86CommonArchitecture::cached_input_types[108]; +case INTRINSIC_XED_IFORM_SCASQ: + return X86CommonArchitecture::cached_input_types[109]; +case INTRINSIC_XED_IFORM_RET_NEAR_IMMw: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_RET_NEAR: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_LES_GPRz_MEMp: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_LDS_GPRz_MEMp: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_ENTER_IMMw_IMMb: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_LEAVE: + return X86CommonArchitecture::cached_input_types[47]; +case INTRINSIC_XED_IFORM_RET_FAR_IMMw: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_RET_FAR: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_INT3: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_INT_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_INTO: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_IRET: + return X86CommonArchitecture::cached_input_types[94]; +case INTRINSIC_XED_IFORM_IRETD: + return X86CommonArchitecture::cached_input_types[94]; +case INTRINSIC_XED_IFORM_IRETQ: + return X86CommonArchitecture::cached_input_types[94]; +case INTRINSIC_XED_IFORM_AAM_IMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_AAD_IMMb: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_SALC: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_XLAT: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_LOOPNE_RELBRb: + return X86CommonArchitecture::cached_input_types[110]; +case INTRINSIC_XED_IFORM_LOOPE_RELBRb: + return X86CommonArchitecture::cached_input_types[110]; +case INTRINSIC_XED_IFORM_LOOP_RELBRb: + return X86CommonArchitecture::cached_input_types[38]; +case INTRINSIC_XED_IFORM_JCXZ_RELBRb: + return X86CommonArchitecture::cached_input_types[84]; +case INTRINSIC_XED_IFORM_JECXZ_RELBRb: + return X86CommonArchitecture::cached_input_types[77]; +case INTRINSIC_XED_IFORM_JRCXZ_RELBRb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_IN_AL_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_IN_OeAX_IMMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_IN_AL_DX: + return X86CommonArchitecture::cached_input_types[38]; +case INTRINSIC_XED_IFORM_IN_OeAX_DX: + return X86CommonArchitecture::cached_input_types[38]; +case INTRINSIC_XED_IFORM_OUT_IMMb_AL: + return X86CommonArchitecture::cached_input_types[33]; +case INTRINSIC_XED_IFORM_OUT_IMMb_OeAX: + return X86CommonArchitecture::cached_input_types[38]; +case INTRINSIC_XED_IFORM_OUT_DX_AL: + return X86CommonArchitecture::cached_input_types[87]; +case INTRINSIC_XED_IFORM_OUT_DX_OeAX: + return X86CommonArchitecture::cached_input_types[85]; +case INTRINSIC_XED_IFORM_INT1: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_HLT: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_CMC: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_CLC: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_STC: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_CLI: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_STI: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_CLD: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_STD: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_LAR_GPRv_MEMw: + return X86CommonArchitecture::cached_input_types[51]; +case INTRINSIC_XED_IFORM_LAR_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_LSL_GPRv_MEMw: + return X86CommonArchitecture::cached_input_types[82]; +case INTRINSIC_XED_IFORM_LSL_GPRv_GPRz: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_SYSCALL: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_CLTS: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_SYSRET: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_SYSRET64: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_MOVUPS_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVUPS_XMMps_XMMps_0F10: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVUPS_MEMps_XMMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVUPS_XMMps_XMMps_0F11: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_UNPCKLPS_XMMps_MEMdq: + return X86CommonArchitecture::cached_input_types[111]; +case INTRINSIC_XED_IFORM_UNPCKLPS_XMMps_XMMq: + return X86CommonArchitecture::cached_input_types[112]; +case INTRINSIC_XED_IFORM_UNPCKHPS_XMMps_MEMdq: + return X86CommonArchitecture::cached_input_types[111]; +case INTRINSIC_XED_IFORM_UNPCKHPS_XMMps_XMMdq: + return X86CommonArchitecture::cached_input_types[111]; +case INTRINSIC_XED_IFORM_MOVSS_XMMdq_MEMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVSS_XMMss_XMMss_0F10: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVSS_MEMss_XMMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVSS_XMMss_XMMss_0F11: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVSLDUP_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVSLDUP_XMMps_XMMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVSHDUP_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVSHDUP_XMMps_XMMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVUPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_MOVUPD_MEMpd_XMMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_MOVLPD_XMMsd_MEMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVLPD_MEMq_XMMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_UNPCKLPD_XMMpd_MEMdq: + return X86CommonArchitecture::cached_input_types[114]; +case INTRINSIC_XED_IFORM_UNPCKLPD_XMMpd_XMMq: + return X86CommonArchitecture::cached_input_types[115]; +case INTRINSIC_XED_IFORM_UNPCKHPD_XMMpd_MEMdq: + return X86CommonArchitecture::cached_input_types[114]; +case INTRINSIC_XED_IFORM_UNPCKHPD_XMMpd_XMMq: + return X86CommonArchitecture::cached_input_types[115]; +case INTRINSIC_XED_IFORM_MOVHPD_XMMsd_MEMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVHPD_MEMq_XMMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_MOVSD_XMM_XMMdq_MEMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_MOVSD_XMM_MEMsd_XMMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_MOVDDUP_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVDDUP_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOV_CR_CR_GPR32: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_MOV_CR_CR_GPR64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_MOV_CR_GPR32_CR: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_MOV_CR_GPR64_CR: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_MOV_DR_DR_GPR32: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_MOV_DR_DR_GPR64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_MOV_DR_GPR32_DR: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_MOV_DR_GPR64_DR: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_WRMSR: + return X86CommonArchitecture::cached_input_types[76]; +case INTRINSIC_XED_IFORM_RDTSC: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_RDMSR: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_RDPMC: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_SYSENTER: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_SYSEXIT: + return X86CommonArchitecture::cached_input_types[77]; +case INTRINSIC_XED_IFORM_CMOVO_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVO_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMOVNO_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVNO_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMOVB_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVB_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMOVNB_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVNB_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMOVZ_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVZ_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMOVNZ_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVNZ_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMOVBE_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVBE_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMOVNBE_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVNBE_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_MOVMSKPS_GPR32_XMMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_SQRTPS_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_SQRTPS_XMMps_XMMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_RSQRTPS_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_RSQRTPS_XMMps_XMMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_RCPPS_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_RCPPS_XMMps_XMMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_ANDPS_XMMxud_MEMxud: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_ANDPS_XMMxud_XMMxud: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_ANDNPS_XMMxud_MEMxud: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_ANDNPS_XMMxud_XMMxud: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_ORPS_XMMxud_MEMxud: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_ORPS_XMMxud_XMMxud: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_XORPS_XMMxud_MEMxud: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_XORPS_XMMxud_XMMxud: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_SQRTSS_XMMss_MEMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_SQRTSS_XMMss_XMMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_RSQRTSS_XMMss_MEMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_RSQRTSS_XMMss_XMMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_RCPSS_XMMss_MEMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_RCPSS_XMMss_XMMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVMSKPD_GPR32_XMMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_SQRTPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_SQRTPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_ANDPD_XMMxuq_MEMxuq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_ANDPD_XMMxuq_XMMxuq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_ANDNPD_XMMxuq_MEMxuq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_ANDNPD_XMMxuq_XMMxuq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_ORPD_XMMxuq_MEMxuq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_ORPD_XMMxuq_XMMxuq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_XORPD_XMMxuq_MEMxuq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_XORPD_XMMxuq_XMMxuq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_SQRTSD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_SQRTSD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_PUNPCKLBW_MMXq_MEMd: + return X86CommonArchitecture::cached_input_types[117]; +case INTRINSIC_XED_IFORM_PUNPCKLBW_MMXq_MMXd: + return X86CommonArchitecture::cached_input_types[117]; +case INTRINSIC_XED_IFORM_PUNPCKLBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PUNPCKLBW_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[118]; +case INTRINSIC_XED_IFORM_PUNPCKLWD_MMXq_MEMd: + return X86CommonArchitecture::cached_input_types[119]; +case INTRINSIC_XED_IFORM_PUNPCKLWD_MMXq_MMXd: + return X86CommonArchitecture::cached_input_types[119]; +case INTRINSIC_XED_IFORM_PUNPCKLWD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PUNPCKLWD_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[118]; +case INTRINSIC_XED_IFORM_PUNPCKLDQ_MMXq_MEMd: + return X86CommonArchitecture::cached_input_types[120]; +case INTRINSIC_XED_IFORM_PUNPCKLDQ_MMXq_MMXd: + return X86CommonArchitecture::cached_input_types[120]; +case INTRINSIC_XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PUNPCKLDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[118]; +case INTRINSIC_XED_IFORM_PACKSSWB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PACKSSWB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PACKSSWB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_PACKSSWB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_PCMPGTB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[123]; +case INTRINSIC_XED_IFORM_PCMPGTB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[123]; +case INTRINSIC_XED_IFORM_PCMPGTB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_PCMPGTB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_PCMPGTW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PCMPGTW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PCMPGTW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_PCMPGTW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_PCMPGTD_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[125]; +case INTRINSIC_XED_IFORM_PCMPGTD_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[125]; +case INTRINSIC_XED_IFORM_PCMPGTD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PCMPGTD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PACKUSWB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PACKUSWB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PACKUSWB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_PACKUSWB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_PSHUFW_MMXq_MEMq_IMMb: + return X86CommonArchitecture::cached_input_types[56]; +case INTRINSIC_XED_IFORM_PSHUFW_MMXq_MMXq_IMMb: + return X86CommonArchitecture::cached_input_types[56]; +case INTRINSIC_XED_IFORM_PCMPEQB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[123]; +case INTRINSIC_XED_IFORM_PCMPEQB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[123]; +case INTRINSIC_XED_IFORM_PCMPEQB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_PCMPEQB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_PCMPEQW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PCMPEQW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PCMPEQW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_PCMPEQW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_PCMPEQD_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[125]; +case INTRINSIC_XED_IFORM_PCMPEQD_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[125]; +case INTRINSIC_XED_IFORM_PCMPEQD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PCMPEQD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_EMMS: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_SETO_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETO_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNO_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNO_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETB_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETB_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNB_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNB_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETZ_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETZ_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNZ_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNZ_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETBE_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETBE_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNBE_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNBE_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_CPUID: + return X86CommonArchitecture::cached_input_types[77]; +case INTRINSIC_XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[126]; +case INTRINSIC_XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[127]; +case INTRINSIC_XED_IFORM_CMPXCHG_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[126]; +case INTRINSIC_XED_IFORM_CMPXCHG_GPR8_GPR8: + return X86CommonArchitecture::cached_input_types[126]; +case INTRINSIC_XED_IFORM_CMPXCHG_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[127]; +case INTRINSIC_XED_IFORM_CMPXCHG_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[128]; +case INTRINSIC_XED_IFORM_LSS_GPRv_MEMp2: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_LFS_GPRv_MEMp2: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_LGS_GPRv_MEMp2: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_MOVZX_GPRv_MEMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_MOVZX_GPRv_GPR8: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_MOVZX_GPRv_MEMw: + return X86CommonArchitecture::cached_input_types[51]; +case INTRINSIC_XED_IFORM_MOVZX_GPRv_GPR16: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_XADD_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_XADD_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_XADD_MEMb_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_XADD_GPR8_GPR8: + return X86CommonArchitecture::cached_input_types[30]; +case INTRINSIC_XED_IFORM_XADD_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_XADD_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMPPS_XMMps_MEMps_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_CMPPS_XMMps_XMMps_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MOVNTI_MEMd_GPR32: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_MOVNTI_MEMq_GPR64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_PINSRW_MMXq_MEMw_IMMb: + return X86CommonArchitecture::cached_input_types[130]; +case INTRINSIC_XED_IFORM_PINSRW_MMXq_GPR32_IMMb: + return X86CommonArchitecture::cached_input_types[131]; +case INTRINSIC_XED_IFORM_PINSRW_XMMdq_MEMw_IMMb: + return X86CommonArchitecture::cached_input_types[132]; +case INTRINSIC_XED_IFORM_PINSRW_XMMdq_GPR32_IMMb: + return X86CommonArchitecture::cached_input_types[133]; +case INTRINSIC_XED_IFORM_PEXTRW_GPR32_MMXq_IMMb: + return X86CommonArchitecture::cached_input_types[56]; +case INTRINSIC_XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_SHUFPS_XMMps_MEMps_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_SHUFPS_XMMps_XMMps_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_CMPSS_XMMss_MEMss_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_CMPSS_XMMss_XMMss_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_PADDQ_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_PADDQ_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_PADDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PADDQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMULLW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PMULLW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PMULLW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMULLW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMOVMSKB_GPR32_MMXq: + return X86CommonArchitecture::cached_input_types[135]; +case INTRINSIC_XED_IFORM_PMOVMSKB_GPR32_XMMdq: + return X86CommonArchitecture::cached_input_types[136]; +case INTRINSIC_XED_IFORM_ADDSUBPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_ADDSUBPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_MOVQ2DQ_XMMdq_MMXq: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_ADDSUBPS_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_ADDSUBPS_XMMps_XMMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MOVDQ2Q_MMXq_XMMq: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_PAVGB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PAVGB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[123]; +case INTRINSIC_XED_IFORM_PAVGB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_PAVGB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_PAVGW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PAVGW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PAVGW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_PAVGW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_PMULHUW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[140]; +case INTRINSIC_XED_IFORM_PMULHUW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[140]; +case INTRINSIC_XED_IFORM_PMULHUW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_PMULHUW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_PMULHW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PMULHW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PMULHW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_PMULHW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_MOVNTQ_MEMq_MMXq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_MOVNTDQ_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_CVTDQ2PD_XMMpd_MEMq: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_CVTDQ2PD_XMMpd_XMMq: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_CVTPD2DQ_XMMdq_MEMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTPD2DQ_XMMdq_XMMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_PMULUDQ_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[141]; +case INTRINSIC_XED_IFORM_PMULUDQ_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[141]; +case INTRINSIC_XED_IFORM_PMULUDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMULUDQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMADDWD_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PMADDWD_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[121]; +case INTRINSIC_XED_IFORM_PMADDWD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_PMADDWD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_PSADBW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSADBW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSADBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSADBW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_MASKMOVQ_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[142]; +case INTRINSIC_XED_IFORM_MASKMOVDQU_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_LDDQU_XMMpd_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_INVD: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_UD0_GPR32_MEMd: + return X86CommonArchitecture::cached_input_types[143]; +case INTRINSIC_XED_IFORM_UD0_GPR32_GPR32: + return X86CommonArchitecture::cached_input_types[77]; +case INTRINSIC_XED_IFORM_UD1_GPR32_MEMd: + return X86CommonArchitecture::cached_input_types[143]; +case INTRINSIC_XED_IFORM_UD1_GPR32_GPR32: + return X86CommonArchitecture::cached_input_types[77]; +case INTRINSIC_XED_IFORM_UD2: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_MOVAPS_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVAPS_XMMps_XMMps_0F28: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVAPS_MEMps_XMMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVAPS_XMMps_XMMps_0F29: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_CVTPI2PS_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_CVTPI2PS_XMMq_MMXq: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_MOVNTPS_MEMdq_XMMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_CVTTPS2PI_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[78]; +case INTRINSIC_XED_IFORM_CVTTPS2PI_MMXq_XMMq: + return X86CommonArchitecture::cached_input_types[78]; +case INTRINSIC_XED_IFORM_CVTPS2PI_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[78]; +case INTRINSIC_XED_IFORM_CVTPS2PI_MMXq_XMMq: + return X86CommonArchitecture::cached_input_types[78]; +case INTRINSIC_XED_IFORM_UCOMISS_XMMss_MEMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_UCOMISS_XMMss_XMMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_COMISS_XMMss_MEMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_COMISS_XMMss_XMMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_GPR32d: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_MEMq: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_GPR64q: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_CVTTSS2SI_GPR32d_MEMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_CVTTSS2SI_GPR32d_XMMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_CVTTSS2SI_GPR64q_MEMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_CVTTSS2SI_GPR64q_XMMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_CVTSS2SI_GPR32d_MEMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_CVTSS2SI_GPR32d_XMMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_CVTSS2SI_GPR64q_MEMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_CVTSS2SI_GPR64q_XMMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_MOVAPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_MOVAPD_MEMpd_XMMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTPI2PD_XMMpd_MEMq: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_CVTPI2PD_XMMpd_MMXq: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_MOVNTPD_MEMdq_XMMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTTPD2PI_MMXq_MEMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTTPD2PI_MMXq_XMMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTPD2PI_MMXq_MEMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTPD2PI_MMXq_XMMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_UCOMISD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_UCOMISD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_COMISD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_COMISD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_GPR32d: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_MEMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_GPR64q: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_CVTTSD2SI_GPR32d_MEMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTTSD2SI_GPR32d_XMMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTTSD2SI_GPR64q_MEMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTTSD2SI_GPR64q_XMMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTSD2SI_GPR32d_MEMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTSD2SI_GPR32d_XMMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTSD2SI_GPR64q_MEMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTSD2SI_GPR64q_XMMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CMOVS_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVS_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMOVNS_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVNS_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMOVP_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVP_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMOVNP_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVNP_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMOVL_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVL_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMOVNL_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVNL_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMOVLE_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVLE_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_CMOVNLE_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_CMOVNLE_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_ADDPS_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_ADDPS_XMMps_XMMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MULPS_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MULPS_XMMps_XMMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_CVTPS2PD_XMMpd_MEMq: + return X86CommonArchitecture::cached_input_types[78]; +case INTRINSIC_XED_IFORM_CVTPS2PD_XMMpd_XMMq: + return X86CommonArchitecture::cached_input_types[78]; +case INTRINSIC_XED_IFORM_CVTDQ2PS_XMMps_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_CVTDQ2PS_XMMps_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_SUBPS_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_SUBPS_XMMps_XMMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MINPS_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MINPS_XMMps_XMMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_DIVPS_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_DIVPS_XMMps_XMMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MAXPS_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MAXPS_XMMps_XMMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_ADDSS_XMMss_MEMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_ADDSS_XMMss_XMMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MULSS_XMMss_MEMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MULSS_XMMss_XMMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_CVTSS2SD_XMMsd_MEMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_CVTSS2SD_XMMsd_XMMss: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_CVTTPS2DQ_XMMdq_MEMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_CVTTPS2DQ_XMMdq_XMMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_SUBSS_XMMss_MEMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_SUBSS_XMMss_XMMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MINSS_XMMss_MEMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MINSS_XMMss_XMMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_DIVSS_XMMss_MEMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_DIVSS_XMMss_XMMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MAXSS_XMMss_MEMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MAXSS_XMMss_XMMss: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_ADDPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_ADDPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_MULPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_MULPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_CVTPD2PS_XMMps_MEMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTPD2PS_XMMps_XMMpd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTPS2DQ_XMMdq_MEMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_CVTPS2DQ_XMMdq_XMMps: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_SUBPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_SUBPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_MINPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_MINPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_DIVPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_DIVPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_MAXPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_MAXPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_ADDSD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_ADDSD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_MULSD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_MULSD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_CVTSD2SS_XMMss_MEMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_CVTSD2SS_XMMss_XMMsd: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_SUBSD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_SUBSD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_MINSD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_MINSD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_DIVSD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_DIVSD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_MAXSD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_MAXSD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_PUNPCKHBW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PUNPCKHBW_MMXq_MMXd: + return X86CommonArchitecture::cached_input_types[144]; +case INTRINSIC_XED_IFORM_PUNPCKHBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PUNPCKHBW_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[118]; +case INTRINSIC_XED_IFORM_PUNPCKHWD_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PUNPCKHWD_MMXq_MMXd: + return X86CommonArchitecture::cached_input_types[144]; +case INTRINSIC_XED_IFORM_PUNPCKHWD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PUNPCKHWD_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[118]; +case INTRINSIC_XED_IFORM_PUNPCKHDQ_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PUNPCKHDQ_MMXq_MMXd: + return X86CommonArchitecture::cached_input_types[144]; +case INTRINSIC_XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PUNPCKHDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[118]; +case INTRINSIC_XED_IFORM_PACKSSDW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[125]; +case INTRINSIC_XED_IFORM_PACKSSDW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[125]; +case INTRINSIC_XED_IFORM_PACKSSDW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PACKSSDW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_MOVD_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_MOVD_XMMdq_GPR32: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_MOVD_MEMd_XMMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_MOVD_GPR32_XMMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_MOVD_MMXq_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_MOVD_MMXq_GPR32: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_MOVD_MEMd_MMXd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_MOVD_GPR32_MMXd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_MOVQ_XMMdq_MEMq_0F6E: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVQ_XMMdq_GPR64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_MOVQ_MEMq_XMMq_0F7E: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVQ_GPR64_XMMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVQ_MEMq_XMMq_0FD6: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVQ_XMMdq_XMMq_0FD6: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVQ_XMMdq_MEMq_0F7E: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVQ_XMMdq_XMMq_0F7E: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVQ_MMXq_MEMq_0F6E: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVQ_MMXq_GPR64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_MOVQ_MEMq_MMXq_0F7E: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVQ_GPR64_MMXq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVQ_MMXq_MEMq_0F6F: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVQ_MMXq_MMXq_0F6F: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVQ_MEMq_MMXq_0F7F: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVQ_MMXq_MMXq_0F7F: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[118]; +case INTRINSIC_XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[118]; +case INTRINSIC_XED_IFORM_MOVDQU_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_MOVDQU_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VMREAD_MEMq_GPR64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_VMREAD_GPR64_GPR64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_VMREAD_MEMd_GPR32: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_VMREAD_GPR32_GPR32: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_VMWRITE_GPR64_MEMq: + return X86CommonArchitecture::cached_input_types[73]; +case INTRINSIC_XED_IFORM_VMWRITE_GPR64_GPR64: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_VMWRITE_GPR32_MEMd: + return X86CommonArchitecture::cached_input_types[143]; +case INTRINSIC_XED_IFORM_VMWRITE_GPR32_GPR32: + return X86CommonArchitecture::cached_input_types[77]; +case INTRINSIC_XED_IFORM_HADDPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_HADDPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_HSUBPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_HSUBPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_MOVDQA_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_MOVDQA_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_HADDPS_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_HADDPS_XMMps_XMMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_HSUBPS_XMMps_MEMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_HSUBPS_XMMps_XMMps: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_SETS_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETS_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNS_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNS_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETP_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETP_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNP_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNP_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETL_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETL_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNL_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNL_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETLE_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETLE_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNLE_MEMb: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETNLE_GPR8: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_RSM: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_SHRD_MEMv_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_SHRD_MEMv_GPRv_CL: + return X86CommonArchitecture::cached_input_types[145]; +case INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_CL: + return X86CommonArchitecture::cached_input_types[146]; +case INTRINSIC_XED_IFORM_SHLD_MEMv_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[21]; +case INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_IMMb: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_SHLD_MEMv_GPRv_CL: + return X86CommonArchitecture::cached_input_types[145]; +case INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_CL: + return X86CommonArchitecture::cached_input_types[146]; +case INTRINSIC_XED_IFORM_MOVSX_GPRv_MEMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_MOVSX_GPRv_GPR8: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_MOVSX_GPRv_MEMw: + return X86CommonArchitecture::cached_input_types[51]; +case INTRINSIC_XED_IFORM_MOVSX_GPRv_GPR16: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_BSWAP_GPRv: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_PSUBUSB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBUSB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBUSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSUBUSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSUBUSW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBUSW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBUSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSUBUSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMINUB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PMINUB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PMINUB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMINUB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PAND_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PAND_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PAND_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PAND_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PADDUSB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PADDUSB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PADDUSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PADDUSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PADDUSW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PADDUSW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PADDUSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PADDUSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMAXUB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PMAXUB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PMAXUB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMAXUB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PANDN_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PANDN_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PANDN_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PANDN_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSUBSB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBSB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSUBSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSUBSW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBSW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSUBSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMINSW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PMINSW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PMINSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMINSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_POR_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_POR_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_POR_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_POR_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PADDSB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PADDSB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PADDSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PADDSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PADDSW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PADDSW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PADDSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PADDSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMAXSW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PMAXSW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PMAXSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMAXSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PXOR_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PXOR_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PXOR_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PXOR_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSUBB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSUBB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSUBW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSUBW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSUBD_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBD_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSUBD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSUBQ_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBQ_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSUBQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSUBQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PADDB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PADDB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PADDB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PADDB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PADDW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PADDW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PADDW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_PADDW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_PADDD_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PADDD_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PADDD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PADDD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PHADDW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PHADDW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PHADDW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PHADDW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PHADDD_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PHADDD_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PHADDD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PHADDD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PHADDSW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PHADDSW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PHADDSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PHADDSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PHSUBW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PHSUBW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PHSUBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PHSUBW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PHSUBD_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PHSUBD_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PHSUBD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PHSUBD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PHSUBSW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PHSUBSW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PHSUBSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PHSUBSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMADDUBSW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[123]; +case INTRINSIC_XED_IFORM_PMADDUBSW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[123]; +case INTRINSIC_XED_IFORM_PMADDUBSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_PMADDUBSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_PMULHRSW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PMULHRSW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PMULHRSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMULHRSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSHUFB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSHUFB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSHUFB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSHUFB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSIGNB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSIGNB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSIGNB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSIGNB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSIGNW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSIGNW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSIGNW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSIGNW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSIGND_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSIGND_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSIGND_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PSIGND_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PALIGNR_MMXq_MEMq_IMMb: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PALIGNR_MMXq_MMXq_IMMb: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PABSB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PABSB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PABSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PABSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PABSW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PABSW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PABSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PABSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PABSD_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PABSD_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PABSD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PABSD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_POPCNT_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_POPCNT_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_PCMPGTQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PCMPGTQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_CRC32_GPRyy_MEMb: + return X86CommonArchitecture::cached_input_types[147]; +case INTRINSIC_XED_IFORM_CRC32_GPRyy_GPR8b: + return X86CommonArchitecture::cached_input_types[147]; +case INTRINSIC_XED_IFORM_CRC32_GPRyy_MEMv: + return X86CommonArchitecture::cached_input_types[148]; +case INTRINSIC_XED_IFORM_CRC32_GPRyy_GPRv: + return X86CommonArchitecture::cached_input_types[148]; +case INTRINSIC_XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_BLENDVPD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[149]; +case INTRINSIC_XED_IFORM_BLENDVPD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[149]; +case INTRINSIC_XED_IFORM_BLENDVPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[150]; +case INTRINSIC_XED_IFORM_BLENDVPS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[150]; +case INTRINSIC_XED_IFORM_PCMPEQQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PCMPEQQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_DPPD_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_DPPD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_DPPS_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_DPPS_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MOVNTDQA_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_INSERTPS_XMMps_MEMd_IMMb: + return X86CommonArchitecture::cached_input_types[151]; +case INTRINSIC_XED_IFORM_INSERTPS_XMMps_XMMps_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_PACKUSDW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PACKUSDW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PBLENDVB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[152]; +case INTRINSIC_XED_IFORM_PBLENDVB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[152]; +case INTRINSIC_XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PINSRB_XMMdq_MEMb_IMMb: + return X86CommonArchitecture::cached_input_types[153]; +case INTRINSIC_XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb: + return X86CommonArchitecture::cached_input_types[154]; +case INTRINSIC_XED_IFORM_PINSRD_XMMdq_MEMd_IMMb: + return X86CommonArchitecture::cached_input_types[154]; +case INTRINSIC_XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb: + return X86CommonArchitecture::cached_input_types[154]; +case INTRINSIC_XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb: + return X86CommonArchitecture::cached_input_types[118]; +case INTRINSIC_XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb: + return X86CommonArchitecture::cached_input_types[118]; +case INTRINSIC_XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_PTEST_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PTEST_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PHMINPOSUW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PHMINPOSUW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PMAXSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMAXSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMAXSD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMAXSD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMAXUD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMAXUD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMAXUW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMAXUW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMINSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMINSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMINSD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMINSD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMINUD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMINUD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMINUW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMINUW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMULLD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMULLD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMULDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMULDQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PMOVSXBW_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[135]; +case INTRINSIC_XED_IFORM_PMOVSXBW_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[135]; +case INTRINSIC_XED_IFORM_PMOVSXBD_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[155]; +case INTRINSIC_XED_IFORM_PMOVSXBD_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[155]; +case INTRINSIC_XED_IFORM_PMOVSXBQ_XMMdq_MEMw: + return X86CommonArchitecture::cached_input_types[156]; +case INTRINSIC_XED_IFORM_PMOVSXBQ_XMMdq_XMMw: + return X86CommonArchitecture::cached_input_types[156]; +case INTRINSIC_XED_IFORM_PMOVSXWD_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[60]; +case INTRINSIC_XED_IFORM_PMOVSXWD_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[60]; +case INTRINSIC_XED_IFORM_PMOVSXWQ_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[157]; +case INTRINSIC_XED_IFORM_PMOVSXWQ_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[157]; +case INTRINSIC_XED_IFORM_PMOVSXDQ_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_PMOVSXDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_PMOVZXBW_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[158]; +case INTRINSIC_XED_IFORM_PMOVZXBW_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[158]; +case INTRINSIC_XED_IFORM_PMOVZXBD_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[159]; +case INTRINSIC_XED_IFORM_PMOVZXBD_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[159]; +case INTRINSIC_XED_IFORM_PMOVZXBQ_XMMdq_MEMw: + return X86CommonArchitecture::cached_input_types[160]; +case INTRINSIC_XED_IFORM_PMOVZXBQ_XMMdq_XMMw: + return X86CommonArchitecture::cached_input_types[160]; +case INTRINSIC_XED_IFORM_PMOVZXWD_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[56]; +case INTRINSIC_XED_IFORM_PMOVZXWD_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[56]; +case INTRINSIC_XED_IFORM_PMOVZXWQ_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[161]; +case INTRINSIC_XED_IFORM_PMOVZXWQ_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[161]; +case INTRINSIC_XED_IFORM_PMOVZXDQ_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[65]; +case INTRINSIC_XED_IFORM_PMOVZXDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[65]; +case INTRINSIC_XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[162]; +case INTRINSIC_XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[162]; +case INTRINSIC_XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[163]; +case INTRINSIC_XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[163]; +case INTRINSIC_XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[162]; +case INTRINSIC_XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[162]; +case INTRINSIC_XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[163]; +case INTRINSIC_XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[163]; +case INTRINSIC_XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_XGETBV: + return X86CommonArchitecture::cached_input_types[92]; +case INTRINSIC_XED_IFORM_XSETBV: + return X86CommonArchitecture::cached_input_types[76]; +case INTRINSIC_XED_IFORM_MOVBE_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_MOVBE_MEMv_GPRv: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_GETSEC: + return X86CommonArchitecture::cached_input_types[77]; +case INTRINSIC_XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_AESENC_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_AESENC_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_AESENCLAST_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_AESENCLAST_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_AESDEC_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_AESDEC_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_AESDECLAST_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_AESDECLAST_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_AESIMC_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_AESIMC_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_INVEPT_GPR64_MEMdq: + return X86CommonArchitecture::cached_input_types[164]; +case INTRINSIC_XED_IFORM_INVEPT_GPR32_MEMdq: + return X86CommonArchitecture::cached_input_types[165]; +case INTRINSIC_XED_IFORM_INVVPID_GPR64_MEMdq: + return X86CommonArchitecture::cached_input_types[164]; +case INTRINSIC_XED_IFORM_INVVPID_GPR32_MEMdq: + return X86CommonArchitecture::cached_input_types[165]; +case INTRINSIC_XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PREFETCHW_0F0Dr1: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PREFETCHW_0F0Dr3: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr4: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr5: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr6: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr7: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_XSTORE: + return X86CommonArchitecture::cached_input_types[84]; +case INTRINSIC_XED_IFORM_REP_XSTORE: + return X86CommonArchitecture::cached_input_types[84]; +case INTRINSIC_XED_IFORM_REP_XCRYPTECB: + return X86CommonArchitecture::cached_input_types[166]; +case INTRINSIC_XED_IFORM_REP_XCRYPTCBC: + return X86CommonArchitecture::cached_input_types[167]; +case INTRINSIC_XED_IFORM_REP_XCRYPTCTR: + return X86CommonArchitecture::cached_input_types[167]; +case INTRINSIC_XED_IFORM_REP_XCRYPTCFB: + return X86CommonArchitecture::cached_input_types[167]; +case INTRINSIC_XED_IFORM_REP_XCRYPTOFB: + return X86CommonArchitecture::cached_input_types[167]; +case INTRINSIC_XED_IFORM_REP_XSHA1: + return X86CommonArchitecture::cached_input_types[168]; +case INTRINSIC_XED_IFORM_REP_XSHA256: + return X86CommonArchitecture::cached_input_types[168]; +case INTRINSIC_XED_IFORM_REP_MONTMUL: + return X86CommonArchitecture::cached_input_types[169]; +case INTRINSIC_XED_IFORM_FEMMS: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_PI2FW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PI2FW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PI2FD_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PI2FD_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PF2IW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PF2IW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PF2ID_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PF2ID_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFNACC_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFNACC_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFPNACC_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFPNACC_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFCMPGE_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFCMPGE_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFMIN_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFMIN_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFRCP_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFRCP_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFRSQRT_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFRSQRT_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFSUB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFSUB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFADD_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFADD_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFCMPGT_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFCMPGT_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFMAX_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFMAX_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFRCPIT1_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFRCPIT1_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFRSQIT1_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFRSQIT1_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFSUBR_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFSUBR_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFACC_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFACC_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFCMPEQ_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFCMPEQ_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFMUL_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFMUL_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFRCPIT2_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PFRCPIT2_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PMULHRW_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PMULHRW_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSWAPD_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PSWAPD_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PAVGUSB_MMXq_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PAVGUSB_MMXq_MMXq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_SYSCALL_AMD: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_SYSRET_AMD: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_VMRUN_ArAX: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_VMMCALL: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_VMLOAD_ArAX: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_VMSAVE: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_STGI: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_CLGI: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_SKINIT_EAX: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_INVLPGA_ArAX_ECX: + return X86CommonArchitecture::cached_input_types[170]; +case INTRINSIC_XED_IFORM_EXTRQ_XMMq_IMMb_IMMb: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_EXTRQ_XMMq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_INSERTQ_XMMq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_MOVNTSD_MEMq_XMMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_MOVNTSS_MEMd_XMMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_CLZERO: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_MONITORX: + return X86CommonArchitecture::cached_input_types[76]; +case INTRINSIC_XED_IFORM_MWAITX: + return X86CommonArchitecture::cached_input_types[77]; +case INTRINSIC_XED_IFORM_MCOMMIT: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_RDPRU: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_PSMASH_RAX: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_PVALIDATE_RAX_ECX_EDX: + return X86CommonArchitecture::cached_input_types[171]; +case INTRINSIC_XED_IFORM_RMPADJUST_RAX_RCX_RDX: + return X86CommonArchitecture::cached_input_types[36]; +case INTRINSIC_XED_IFORM_RMPUPDATE_RAX_RCX: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_BNDMK_BND_AGEN: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_BNDCL_BND_AGEN: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_BNDCL_BND_GPR64: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_BNDCL_BND_GPR32: + return X86CommonArchitecture::cached_input_types[172]; +case INTRINSIC_XED_IFORM_BNDCU_BND_AGEN: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_BNDCU_BND_GPR64: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_BNDCU_BND_GPR32: + return X86CommonArchitecture::cached_input_types[172]; +case INTRINSIC_XED_IFORM_BNDCN_BND_AGEN: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_BNDCN_BND_GPR64: + return X86CommonArchitecture::cached_input_types[31]; +case INTRINSIC_XED_IFORM_BNDCN_BND_GPR32: + return X86CommonArchitecture::cached_input_types[172]; +case INTRINSIC_XED_IFORM_BNDMOV_BND_BND: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_BNDMOV_BND_MEMq: + return X86CommonArchitecture::cached_input_types[65]; +case INTRINSIC_XED_IFORM_BNDMOV_BND_MEMdq: + return X86CommonArchitecture::cached_input_types[72]; +case INTRINSIC_XED_IFORM_BNDMOV_MEMq_BND: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_BNDMOV_MEMdq_BND: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_BNDLDX_BND_MEMbnd32: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_BNDLDX_BND_MEMbnd64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_BNDSTX_MEMbnd32_BND: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_BNDSTX_MEMbnd64_BND: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_CLRSSBSY_MEMu64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_ENDBR32: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_ENDBR64: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_INCSSPD_GPR32u8: + return X86CommonArchitecture::cached_input_types[173]; +case INTRINSIC_XED_IFORM_INCSSPQ_GPR64u8: + return X86CommonArchitecture::cached_input_types[174]; +case INTRINSIC_XED_IFORM_RDSSPD_GPR32u32: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_RDSSPQ_GPR64u64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_RSTORSSP_MEMu64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SAVEPREVSSP: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_SETSSBSY: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_WRSSD_MEMu32_GPR32u32: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_WRSSQ_MEMu64_GPR64u64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_WRUSSD_MEMu32_GPR32u32: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_WRUSSQ_MEMu64_GPR64u64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_RDRAND_GPRv: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA: + return X86CommonArchitecture::cached_input_types[175]; +case INTRINSIC_XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA: + return X86CommonArchitecture::cached_input_types[175]; +case INTRINSIC_XED_IFORM_CLFLUSHOPT_MEMmprefetch: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_RDSEED_GPRv: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_RDFSBASE_GPRy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_RDGSBASE_GPRy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_WRFSBASE_GPRy: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_WRGSBASE_GPRy: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_CLAC: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_STAC: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_ENCLU: + return X86CommonArchitecture::cached_input_types[176]; +case INTRINSIC_XED_IFORM_ENCLS: + return X86CommonArchitecture::cached_input_types[176]; +case INTRINSIC_XED_IFORM_RDPID_GPR32u32: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_RDPID_GPR64u64: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_PTWRITE_GPRy: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_PTWRITE_MEMy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_MOVDIR64B_GPRa_MEM: + return X86CommonArchitecture::cached_input_types[177]; +case INTRINSIC_XED_IFORM_MOVDIRI_MEMu32_GPR32u32: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_MOVDIRI_MEMu64_GPR64u64: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_TPAUSE_GPR32u32: + return X86CommonArchitecture::cached_input_types[76]; +case INTRINSIC_XED_IFORM_TPAUSE_GPR64u64: + return X86CommonArchitecture::cached_input_types[171]; +case INTRINSIC_XED_IFORM_UMONITOR_GPRa: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_UMWAIT_GPR32: + return X86CommonArchitecture::cached_input_types[76]; +case INTRINSIC_XED_IFORM_UMWAIT_GPR64: + return X86CommonArchitecture::cached_input_types[171]; +case INTRINSIC_XED_IFORM_CLDEMOTE_MEMu8: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_ENCLV: + return X86CommonArchitecture::cached_input_types[176]; +case INTRINSIC_XED_IFORM_TZCNT_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_TZCNT_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_BSF_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BSF_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_VMFUNC: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_INVPCID_GPR64_MEMdq: + return X86CommonArchitecture::cached_input_types[164]; +case INTRINSIC_XED_IFORM_INVPCID_GPR32_MEMdq: + return X86CommonArchitecture::cached_input_types[165]; +case INTRINSIC_XED_IFORM_LZCNT_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_LZCNT_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BSR_GPRv_MEMv: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BSR_GPRv_GPRv: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_XBEGIN_RELBRz: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_XEND: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_XABORT_IMMb: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_XTEST: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_ADCX_GPR32d_GPR32d: + return X86CommonArchitecture::cached_input_types[94]; +case INTRINSIC_XED_IFORM_ADCX_GPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[94]; +case INTRINSIC_XED_IFORM_ADCX_GPR64q_GPR64q: + return X86CommonArchitecture::cached_input_types[95]; +case INTRINSIC_XED_IFORM_ADCX_GPR64q_MEMq: + return X86CommonArchitecture::cached_input_types[95]; +case INTRINSIC_XED_IFORM_ADOX_GPR32d_GPR32d: + return X86CommonArchitecture::cached_input_types[94]; +case INTRINSIC_XED_IFORM_ADOX_GPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[94]; +case INTRINSIC_XED_IFORM_ADOX_GPR64q_GPR64q: + return X86CommonArchitecture::cached_input_types[95]; +case INTRINSIC_XED_IFORM_ADOX_GPR64q_MEMq: + return X86CommonArchitecture::cached_input_types[95]; +case INTRINSIC_XED_IFORM_RDPKRU: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_WRPKRU: + return X86CommonArchitecture::cached_input_types[76]; +case INTRINSIC_XED_IFORM_CLWB_MEMmprefetch: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_PREFETCHWT1_MEMu8: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_WBINVD: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_WBNOINVD: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_PCONFIG: + return X86CommonArchitecture::cached_input_types[178]; +case INTRINSIC_XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8: + return X86CommonArchitecture::cached_input_types[179]; +case INTRINSIC_XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8: + return X86CommonArchitecture::cached_input_types[179]; +case INTRINSIC_XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8: + return X86CommonArchitecture::cached_input_types[179]; +case INTRINSIC_XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8: + return X86CommonArchitecture::cached_input_types[179]; +case INTRINSIC_XED_IFORM_GF2P8MULB_XMMu8_XMMu8: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_GF2P8MULB_XMMu8_MEMu8: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_ENQCMD_GPRa_MEMu32: + return X86CommonArchitecture::cached_input_types[177]; +case INTRINSIC_XED_IFORM_ENQCMDS_GPRa_MEMu32: + return X86CommonArchitecture::cached_input_types[177]; +case INTRINSIC_XED_IFORM_XRESLDTRK: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_XSUSLDTRK: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_SERIALIZE: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[180]; +case INTRINSIC_XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[180]; +case INTRINSIC_XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[181]; +case INTRINSIC_XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[181]; +case INTRINSIC_XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[182]; +case INTRINSIC_XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[182]; +case INTRINSIC_XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[180]; +case INTRINSIC_XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[180]; +case INTRINSIC_XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[181]; +case INTRINSIC_XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[181]; +case INTRINSIC_XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[182]; +case INTRINSIC_XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[182]; +case INTRINSIC_XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[183]; +case INTRINSIC_XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[183]; +case INTRINSIC_XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[183]; +case INTRINSIC_XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[184]; +case INTRINSIC_XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[184]; +case INTRINSIC_XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[184]; +case INTRINSIC_XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[180]; +case INTRINSIC_XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[180]; +case INTRINSIC_XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[180]; +case INTRINSIC_XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[181]; +case INTRINSIC_XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[181]; +case INTRINSIC_XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[181]; +case INTRINSIC_XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[181]; +case INTRINSIC_XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[72]; +case INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[72]; +case INTRINSIC_XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[152]; +case INTRINSIC_XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[152]; +case INTRINSIC_XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[182]; +case INTRINSIC_XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[182]; +case INTRINSIC_XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[152]; +case INTRINSIC_XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[152]; +case INTRINSIC_XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[182]; +case INTRINSIC_XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[182]; +case INTRINSIC_XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[186]; +case INTRINSIC_XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[186]; +case INTRINSIC_XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VFRCZPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VFRCZPS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VFRCZPS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VFRCZPS_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VFRCZPD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VFRCZPD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VFRCZPD_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VFRCZPD_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VFRCZSS_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VFRCZSS_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VFRCZSD_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VFRCZSD_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPHADDBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[136]; +case INTRINSIC_XED_IFORM_VPHADDBW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[136]; +case INTRINSIC_XED_IFORM_VPHADDBD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[136]; +case INTRINSIC_XED_IFORM_VPHADDBD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[136]; +case INTRINSIC_XED_IFORM_VPHADDBQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[136]; +case INTRINSIC_XED_IFORM_VPHADDBQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[136]; +case INTRINSIC_XED_IFORM_VPHADDWD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[61]; +case INTRINSIC_XED_IFORM_VPHADDWD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[61]; +case INTRINSIC_XED_IFORM_VPHADDWQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[61]; +case INTRINSIC_XED_IFORM_VPHADDWQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[61]; +case INTRINSIC_XED_IFORM_VPHADDUBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPHADDUBW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPHADDUBD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPHADDUBD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPHADDUBQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPHADDUBQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPHADDUWD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPHADDUWD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPHADDUWQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPHADDUWQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPHSUBBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[136]; +case INTRINSIC_XED_IFORM_VPHSUBBW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[136]; +case INTRINSIC_XED_IFORM_VPHSUBWD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[61]; +case INTRINSIC_XED_IFORM_VPHSUBWD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[61]; +case INTRINSIC_XED_IFORM_VPHSUBDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPHSUBDQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[186]; +case INTRINSIC_XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[186]; +case INTRINSIC_XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[186]; +case INTRINSIC_XED_IFORM_VPHADDDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPHADDDQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPHADDUDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VPHADDUDQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_BEXTR_XOP_GPR32d_MEMd_IMMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BEXTR_XOP_GPRyy_MEMy_IMMd: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_BEXTR_XOP_GPR32d_GPR32d_IMMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BEXTR_XOP_GPRyy_GPRyy_IMMd: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_BLCFILL_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLCFILL_VGPRyy_MEMy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_BLCFILL_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLCFILL_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_BLSFILL_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLSFILL_VGPRyy_MEMy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_BLSFILL_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLSFILL_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_BLCS_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLCS_VGPRyy_MEMy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_BLCS_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLCS_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_TZMSK_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_TZMSK_VGPRyy_MEMy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_TZMSK_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_TZMSK_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_BLCIC_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLCIC_VGPRyy_MEMy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_BLCIC_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLCIC_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_BLSIC_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLSIC_VGPRyy_MEMy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_BLSIC_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLSIC_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_T1MSKC_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_T1MSKC_VGPRyy_MEMy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_T1MSKC_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_T1MSKC_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_BLCMSK_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLCMSK_VGPRyy_MEMy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_BLCMSK_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLCMSK_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_BLCI_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLCI_VGPRyy_MEMy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_BLCI_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLCI_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_LLWPCB_GPRyy: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_SLWPCB_GPRyy: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_LWPINS_VGPRyy_GPR32y_IMMd: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_LWPVAL_VGPRyy_GPR32y_IMMd: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd: + return X86CommonArchitecture::cached_input_types[195]; +case INTRINSIC_XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[195]; +case INTRINSIC_XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[195]; +case INTRINSIC_XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq: + return X86CommonArchitecture::cached_input_types[196]; +case INTRINSIC_XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[196]; +case INTRINSIC_XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[196]; +case INTRINSIC_XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd: + return X86CommonArchitecture::cached_input_types[195]; +case INTRINSIC_XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[195]; +case INTRINSIC_XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[195]; +case INTRINSIC_XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq: + return X86CommonArchitecture::cached_input_types[196]; +case INTRINSIC_XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[196]; +case INTRINSIC_XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[196]; +case INTRINSIC_XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd: + return X86CommonArchitecture::cached_input_types[195]; +case INTRINSIC_XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[195]; +case INTRINSIC_XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[195]; +case INTRINSIC_XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq: + return X86CommonArchitecture::cached_input_types[196]; +case INTRINSIC_XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[196]; +case INTRINSIC_XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[196]; +case INTRINSIC_XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd: + return X86CommonArchitecture::cached_input_types[195]; +case INTRINSIC_XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[195]; +case INTRINSIC_XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[195]; +case INTRINSIC_XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq: + return X86CommonArchitecture::cached_input_types[196]; +case INTRINSIC_XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[196]; +case INTRINSIC_XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[196]; +case INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VCOMISD_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[203]; +case INTRINSIC_XED_IFORM_VCOMISD_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[203]; +case INTRINSIC_XED_IFORM_VCOMISS_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[204]; +case INTRINSIC_XED_IFORM_VCOMISS_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[204]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_MEMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_YMMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[78]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[78]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_YMMqq_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32d_MEMq: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32d_XMMq: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64q_MEMq: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64q_XMMq: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32d_MEMq: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32d_XMMq: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64q_MEMq: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64q_XMMq: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32d_XMMd: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64q_MEMd: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64q_XMMd: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32d_XMMd: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64q_MEMd: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64q_XMMd: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[206]; +case INTRINSIC_XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[206]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[207]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d: + return X86CommonArchitecture::cached_input_types[207]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[115]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q: + return X86CommonArchitecture::cached_input_types[115]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[151]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d: + return X86CommonArchitecture::cached_input_types[151]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[112]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q: + return X86CommonArchitecture::cached_input_types[112]; +case INTRINSIC_XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[208]; +case INTRINSIC_XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[208]; +case INTRINSIC_XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VZEROALL: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_VZEROUPPER: + return X86CommonArchitecture::cached_input_types[13]; +case INTRINSIC_XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[209]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[209]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[210]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[210]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[211]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[211]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[212]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[212]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_YMMqq_MEMd: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_YMMqq_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VBROADCASTSD_YMMqq_MEMq: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VBROADCASTSD_YMMqq_XMMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VBROADCASTF128_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[213]; +case INTRINSIC_XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[213]; +case INTRINSIC_XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VLDDQU_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VLDDQU_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[214]; +case INTRINSIC_XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[215]; +case INTRINSIC_XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[214]; +case INTRINSIC_XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[215]; +case INTRINSIC_XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[216]; +case INTRINSIC_XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[217]; +case INTRINSIC_XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[216]; +case INTRINSIC_XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[217]; +case INTRINSIC_XED_IFORM_VPTEST_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPTEST_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPTEST_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPTEST_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VTESTPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VTESTPS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VTESTPS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VTESTPS_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VTESTPD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VTESTPD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VTESTPD_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VTESTPD_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VMOVAPD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VMOVAPD_XMMdq_XMMdq_28: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VMOVAPD_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VMOVAPD_XMMdq_XMMdq_29: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_YMMqq_28: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VMOVAPD_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_YMMqq_29: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VMOVAPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVAPS_XMMdq_XMMdq_28: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVAPS_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVAPS_XMMdq_XMMdq_29: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_YMMqq_28: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VMOVAPS_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_YMMqq_29: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VMOVD_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_VMOVD_XMMdq_GPR32d: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_VMOVD_MEMd_XMMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_VMOVD_GPR32d_XMMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMdq_MEMq_6E: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMdq_GPR64q: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_VMOVQ_MEMq_XMMq_7E: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_VMOVQ_GPR64q_XMMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMdq_MEMq_7E: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMdq_XMMq_7E: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_VMOVQ_MEMq_XMMq_D6: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMdq_XMMq_D6: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_VMOVDDUP_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VMOVDDUP_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VMOVDDUP_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VMOVDDUP_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VMOVDQA_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VMOVDQA_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VMOVDQA_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VMOVDQU_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VMOVDQU_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VMOVDQU_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[219]; +case INTRINSIC_XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[219]; +case INTRINSIC_XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[219]; +case INTRINSIC_XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[219]; +case INTRINSIC_XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[219]; +case INTRINSIC_XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[219]; +case INTRINSIC_XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[219]; +case INTRINSIC_XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[219]; +case INTRINSIC_XED_IFORM_VPABSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[136]; +case INTRINSIC_XED_IFORM_VPABSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[136]; +case INTRINSIC_XED_IFORM_VPABSB_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[220]; +case INTRINSIC_XED_IFORM_VPABSB_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[220]; +case INTRINSIC_XED_IFORM_VPABSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[61]; +case INTRINSIC_XED_IFORM_VPABSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[61]; +case INTRINSIC_XED_IFORM_VPABSW_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[221]; +case INTRINSIC_XED_IFORM_VPABSW_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[221]; +case INTRINSIC_XED_IFORM_VPABSD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPABSD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPABSD_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VPABSD_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[222]; +case INTRINSIC_XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[222]; +case INTRINSIC_XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[223]; +case INTRINSIC_XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[223]; +case INTRINSIC_XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[223]; +case INTRINSIC_XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[223]; +case INTRINSIC_XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[225]; +case INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[225]; +case INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[226]; +case INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_input_types[227]; +case INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[223]; +case INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[228]; +case INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[228]; +case INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[229]; +case INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_input_types[230]; +case INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[222]; +case INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[72]; +case INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[231]; +case INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_input_types[232]; +case INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[233]; +case INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[225]; +case INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[225]; +case INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[226]; +case INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_input_types[227]; +case INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[223]; +case INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[228]; +case INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[228]; +case INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[229]; +case INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_input_types[230]; +case INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[222]; +case INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[72]; +case INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[231]; +case INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_input_types[232]; +case INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[233]; +case INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[63]; +case INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[63]; +case INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[61]; +case INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[234]; +case INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_input_types[235]; +case INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[221]; +case INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[71]; +case INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[71]; +case INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[236]; +case INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_input_types[237]; +case INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[186]; +case INTRINSIC_XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[186]; +case INTRINSIC_XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[239]; +case INTRINSIC_XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[239]; +case INTRINSIC_XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[186]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[186]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[239]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[239]; +case INTRINSIC_XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[186]; +case INTRINSIC_XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[186]; +case INTRINSIC_XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[239]; +case INTRINSIC_XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[239]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[12]; +case INTRINSIC_XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[243]; +case INTRINSIC_XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[12]; +case INTRINSIC_XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[243]; +case INTRINSIC_XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[244]; +case INTRINSIC_XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VRCPPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VRCPPS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VRCPPS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VRCPPS_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VRSQRTPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VRSQRTPS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VRSQRTPS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VRSQRTPS_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VSQRTPD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VSQRTPD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VSQRTPD_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VSQRTPD_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VSQRTPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VSQRTPS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VSQRTPS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VSQRTPS_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[124]; +case INTRINSIC_XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[238]; +case INTRINSIC_XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[139]; +case INTRINSIC_XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[241]; +case INTRINSIC_XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[122]; +case INTRINSIC_XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[224]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[245]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[245]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[246]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[246]; +case INTRINSIC_XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VUCOMISD_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VUCOMISD_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VUCOMISS_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VUCOMISS_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[197]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VMOVSS_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VMOVSS_MEMd_XMMd: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VMOVSD_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VMOVSD_MEMq_XMMq: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VMOVUPD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VMOVUPD_XMMdq_XMMdq_10: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VMOVUPD_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VMOVUPD_XMMdq_XMMdq_11: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_YMMqq_10: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VMOVUPD_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_YMMqq_11: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VMOVUPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVUPS_XMMdq_XMMdq_10: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVUPS_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVUPS_XMMdq_XMMdq_11: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_YMMqq_10: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VMOVUPS_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_YMMqq_11: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VMOVLPD_MEMq_XMMq: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[247]; +case INTRINSIC_XED_IFORM_VMOVLPS_MEMq_XMMq: + return X86CommonArchitecture::cached_input_types[78]; +case INTRINSIC_XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[203]; +case INTRINSIC_XED_IFORM_VMOVHPD_MEMq_XMMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[244]; +case INTRINSIC_XED_IFORM_VMOVHPS_MEMq_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVMSKPD_GPR32d_XMMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VMOVMSKPD_GPR32d_YMMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VMOVMSKPS_GPR32d_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVMSKPS_GPR32d_YMMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VPMOVMSKB_GPR32d_XMMdq: + return X86CommonArchitecture::cached_input_types[136]; +case INTRINSIC_XED_IFORM_VPMOVMSKB_GPR32d_YMMqq: + return X86CommonArchitecture::cached_input_types[220]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[135]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[135]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_YMMqq_XMMdq: + return X86CommonArchitecture::cached_input_types[136]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[136]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[155]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[155]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_YMMqq_XMMq: + return X86CommonArchitecture::cached_input_types[135]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_YMMqq_MEMq: + return X86CommonArchitecture::cached_input_types[135]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMdq_XMMw: + return X86CommonArchitecture::cached_input_types[156]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMdq_MEMw: + return X86CommonArchitecture::cached_input_types[156]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMqq_XMMd: + return X86CommonArchitecture::cached_input_types[155]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMqq_MEMd: + return X86CommonArchitecture::cached_input_types[155]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[60]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[60]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_YMMqq_XMMdq: + return X86CommonArchitecture::cached_input_types[61]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[61]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[157]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[157]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMqq_XMMq: + return X86CommonArchitecture::cached_input_types[60]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMqq_MEMq: + return X86CommonArchitecture::cached_input_types[60]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[68]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[158]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[158]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_YMMqq_XMMdq: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[159]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[159]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_YMMqq_XMMq: + return X86CommonArchitecture::cached_input_types[158]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_YMMqq_MEMq: + return X86CommonArchitecture::cached_input_types[158]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMdq_XMMw: + return X86CommonArchitecture::cached_input_types[160]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMdq_MEMw: + return X86CommonArchitecture::cached_input_types[160]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMqq_XMMd: + return X86CommonArchitecture::cached_input_types[159]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMqq_MEMd: + return X86CommonArchitecture::cached_input_types[159]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[56]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[56]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_YMMqq_XMMdq: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[161]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[161]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMqq_XMMq: + return X86CommonArchitecture::cached_input_types[56]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMqq_MEMq: + return X86CommonArchitecture::cached_input_types[56]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[65]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[65]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[72]; +case INTRINSIC_XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[72]; +case INTRINSIC_XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb: + return X86CommonArchitecture::cached_input_types[248]; +case INTRINSIC_XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb: + return X86CommonArchitecture::cached_input_types[249]; +case INTRINSIC_XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb: + return X86CommonArchitecture::cached_input_types[250]; +case INTRINSIC_XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb: + return X86CommonArchitecture::cached_input_types[251]; +case INTRINSIC_XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb: + return X86CommonArchitecture::cached_input_types[252]; +case INTRINSIC_XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb: + return X86CommonArchitecture::cached_input_types[252]; +case INTRINSIC_XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb: + return X86CommonArchitecture::cached_input_types[253]; +case INTRINSIC_XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb: + return X86CommonArchitecture::cached_input_types[253]; +case INTRINSIC_XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[162]; +case INTRINSIC_XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[162]; +case INTRINSIC_XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[163]; +case INTRINSIC_XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[163]; +case INTRINSIC_XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[162]; +case INTRINSIC_XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[162]; +case INTRINSIC_XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[163]; +case INTRINSIC_XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[163]; +case INTRINSIC_XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VLDMXCSR_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_VSTMXCSR_MEMd: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[254]; +case INTRINSIC_XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[254]; +case INTRINSIC_XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[255]; +case INTRINSIC_XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[255]; +case INTRINSIC_XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[149]; +case INTRINSIC_XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[149]; +case INTRINSIC_XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[256]; +case INTRINSIC_XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[256]; +case INTRINSIC_XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[150]; +case INTRINSIC_XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[150]; +case INTRINSIC_XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[257]; +case INTRINSIC_XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[257]; +case INTRINSIC_XED_IFORM_VMOVNTDQA_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VMOVNTDQA_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VMOVNTDQ_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VMOVNTDQ_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[205]; +case INTRINSIC_XED_IFORM_VMOVNTPD_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VMOVNTPD_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VMOVNTPS_MEMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVNTPS_MEMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESIMC_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VAESIMC_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[69]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[259]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[259]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[260]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_YMMqq_XMMdq: + return X86CommonArchitecture::cached_input_types[260]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[193]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[194]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[191]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[192]; +case INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_input_types[261]; +case INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_input_types[262]; +case INTRINSIC_XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256: + return X86CommonArchitecture::cached_input_types[263]; +case INTRINSIC_XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128: + return X86CommonArchitecture::cached_input_types[264]; +case INTRINSIC_XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256: + return X86CommonArchitecture::cached_input_types[265]; +case INTRINSIC_XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128: + return X86CommonArchitecture::cached_input_types[266]; +case INTRINSIC_XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256: + return X86CommonArchitecture::cached_input_types[263]; +case INTRINSIC_XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128: + return X86CommonArchitecture::cached_input_types[264]; +case INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256: + return X86CommonArchitecture::cached_input_types[266]; +case INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128: + return X86CommonArchitecture::cached_input_types[267]; +case INTRINSIC_XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256: + return X86CommonArchitecture::cached_input_types[268]; +case INTRINSIC_XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128: + return X86CommonArchitecture::cached_input_types[269]; +case INTRINSIC_XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256: + return X86CommonArchitecture::cached_input_types[270]; +case INTRINSIC_XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128: + return X86CommonArchitecture::cached_input_types[271]; +case INTRINSIC_XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256: + return X86CommonArchitecture::cached_input_types[268]; +case INTRINSIC_XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128: + return X86CommonArchitecture::cached_input_types[269]; +case INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256: + return X86CommonArchitecture::cached_input_types[271]; +case INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128: + return X86CommonArchitecture::cached_input_types[272]; +case INTRINSIC_XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[273]; +case INTRINSIC_XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[273]; +case INTRINSIC_XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[243]; +case INTRINSIC_XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[243]; +case INTRINSIC_XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[233]; +case INTRINSIC_XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[233]; +case INTRINSIC_XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[198]; +case INTRINSIC_XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_XMMdq_MEMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_XMMdq_XMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_YMMqq_MEMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_YMMqq_XMMb: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_XMMdq_MEMw: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_XMMdq_XMMw: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_YMMqq_MEMw: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_YMMqq_XMMw: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_XMMdq_MEMd: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_XMMdq_XMMd: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_YMMqq_MEMd: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_YMMqq_XMMd: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMdq_MEMq: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMqq_MEMq: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMqq_XMMq: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_VBROADCASTI128_YMMqq_MEMdq: + return X86CommonArchitecture::cached_input_types[12]; +case INTRINSIC_XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_input_types[59]; +case INTRINSIC_XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_input_types[202]; +case INTRINSIC_XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_BLSR_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLSR_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLSR_VGPR64q_MEMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_BLSR_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_BLSMSK_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLSMSK_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLSMSK_VGPR64q_MEMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_BLSMSK_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_BLSI_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLSI_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_BLSI_VGPR64q_MEMq: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_BLSI_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_input_types[39]; +case INTRINSIC_XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_input_types[137]; +case INTRINSIC_XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_input_types[274]; +case INTRINSIC_XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd: + return X86CommonArchitecture::cached_input_types[274]; +case INTRINSIC_XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_input_types[23]; +case INTRINSIC_XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq: + return X86CommonArchitecture::cached_input_types[23]; +case INTRINSIC_XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_RORX_VGPR32d_MEMd_IMMb: + return X86CommonArchitecture::cached_input_types[29]; +case INTRINSIC_XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_RORX_VGPR64q_MEMq_IMMb: + return X86CommonArchitecture::cached_input_types[53]; +case INTRINSIC_XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[14]; +case INTRINSIC_XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[28]; +case INTRINSIC_XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[275]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8: + return X86CommonArchitecture::cached_input_types[179]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8: + return X86CommonArchitecture::cached_input_types[179]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8: + return X86CommonArchitecture::cached_input_types[277]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8: + return X86CommonArchitecture::cached_input_types[277]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8: + return X86CommonArchitecture::cached_input_types[179]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8: + return X86CommonArchitecture::cached_input_types[179]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8: + return X86CommonArchitecture::cached_input_types[277]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8: + return X86CommonArchitecture::cached_input_types[277]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[278]; +case INTRINSIC_XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[278]; +case INTRINSIC_XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[279]; +case INTRINSIC_XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[279]; +case INTRINSIC_XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[280]; +case INTRINSIC_XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[280]; +case INTRINSIC_XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[278]; +case INTRINSIC_XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[278]; +case INTRINSIC_XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[279]; +case INTRINSIC_XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[279]; +case INTRINSIC_XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[280]; +case INTRINSIC_XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[280]; +case INTRINSIC_XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[281]; +case INTRINSIC_XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[281]; +case INTRINSIC_XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[282]; +case INTRINSIC_XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[282]; +case INTRINSIC_XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[283]; +case INTRINSIC_XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[283]; +case INTRINSIC_XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[281]; +case INTRINSIC_XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[281]; +case INTRINSIC_XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[282]; +case INTRINSIC_XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[282]; +case INTRINSIC_XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[283]; +case INTRINSIC_XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[283]; +case INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[290]; +case INTRINSIC_XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[290]; +case INTRINSIC_XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[291]; +case INTRINSIC_XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[291]; +case INTRINSIC_XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[292]; +case INTRINSIC_XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[292]; +case INTRINSIC_XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[294]; +case INTRINSIC_XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[295]; +case INTRINSIC_XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[294]; +case INTRINSIC_XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[295]; +case INTRINSIC_XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[294]; +case INTRINSIC_XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[295]; +case INTRINSIC_XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[294]; +case INTRINSIC_XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[295]; +case INTRINSIC_XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[294]; +case INTRINSIC_XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[295]; +case INTRINSIC_XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[294]; +case INTRINSIC_XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[295]; +case INTRINSIC_XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[294]; +case INTRINSIC_XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[295]; +case INTRINSIC_XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[294]; +case INTRINSIC_XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_input_types[295]; +case INTRINSIC_XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[299]; +case INTRINSIC_XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[299]; +case INTRINSIC_XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[301]; +case INTRINSIC_XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[301]; +case INTRINSIC_XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[317]; +case INTRINSIC_XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[317]; +case INTRINSIC_XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[319]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[319]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[319]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[320]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[321]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[320]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[321]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[321]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[320]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[320]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512: + return X86CommonArchitecture::cached_input_types[323]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512: + return X86CommonArchitecture::cached_input_types[323]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512: + return X86CommonArchitecture::cached_input_types[324]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512: + return X86CommonArchitecture::cached_input_types[325]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512: + return X86CommonArchitecture::cached_input_types[324]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512: + return X86CommonArchitecture::cached_input_types[324]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512: + return X86CommonArchitecture::cached_input_types[207]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[207]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512: + return X86CommonArchitecture::cached_input_types[115]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512: + return X86CommonArchitecture::cached_input_types[115]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512: + return X86CommonArchitecture::cached_input_types[151]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[151]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512: + return X86CommonArchitecture::cached_input_types[112]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512: + return X86CommonArchitecture::cached_input_types[112]; +case INTRINSIC_XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[189]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512: + return X86CommonArchitecture::cached_input_types[326]; +case INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[326]; +case INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512: + return X86CommonArchitecture::cached_input_types[327]; +case INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[327]; +case INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512: + return X86CommonArchitecture::cached_input_types[328]; +case INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[328]; +case INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512: + return X86CommonArchitecture::cached_input_types[329]; +case INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[329]; +case INTRINSIC_XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[335]; +case INTRINSIC_XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[336]; +case INTRINSIC_XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[335]; +case INTRINSIC_XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[336]; +case INTRINSIC_XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[335]; +case INTRINSIC_XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[336]; +case INTRINSIC_XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[335]; +case INTRINSIC_XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[336]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[335]; +case INTRINSIC_XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[336]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[335]; +case INTRINSIC_XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[336]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[335]; +case INTRINSIC_XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[336]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[335]; +case INTRINSIC_XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[336]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[335]; +case INTRINSIC_XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[336]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[335]; +case INTRINSIC_XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[336]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[335]; +case INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[336]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[335]; +case INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[336]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[335]; +case INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[336]; +case INTRINSIC_XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[317]; +case INTRINSIC_XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[317]; +case INTRINSIC_XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[317]; +case INTRINSIC_XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[319]; +case INTRINSIC_XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[319]; +case INTRINSIC_XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[319]; +case INTRINSIC_XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[317]; +case INTRINSIC_XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[317]; +case INTRINSIC_XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[317]; +case INTRINSIC_XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[319]; +case INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[319]; +case INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[319]; +case INTRINSIC_XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[337]; +case INTRINSIC_XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[337]; +case INTRINSIC_XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[338]; +case INTRINSIC_XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[338]; +case INTRINSIC_XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[339]; +case INTRINSIC_XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[339]; +case INTRINSIC_XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[340]; +case INTRINSIC_XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[340]; +case INTRINSIC_XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[341]; +case INTRINSIC_XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[341]; +case INTRINSIC_XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[342]; +case INTRINSIC_XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[342]; +case INTRINSIC_XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[317]; +case INTRINSIC_XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[203]; +case INTRINSIC_XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[244]; +case INTRINSIC_XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[244]; +case INTRINSIC_XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[190]; +case INTRINSIC_XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[247]; +case INTRINSIC_XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[78]; +case INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[343]; +case INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[222]; +case INTRINSIC_XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[343]; +case INTRINSIC_XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[222]; +case INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[344]; +case INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[113]; +case INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[188]; +case INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[345]; +case INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[79]; +case INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[187]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[72]; +case INTRINSIC_XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[72]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[72]; +case INTRINSIC_XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[317]; +case INTRINSIC_XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[319]; +case INTRINSIC_XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[321]; +case INTRINSIC_XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[321]; +case INTRINSIC_XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[320]; +case INTRINSIC_XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[320]; +case INTRINSIC_XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[346]; +case INTRINSIC_XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512: + return X86CommonArchitecture::cached_input_types[346]; +case INTRINSIC_XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[347]; +case INTRINSIC_XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512: + return X86CommonArchitecture::cached_input_types[347]; +case INTRINSIC_XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[348]; +case INTRINSIC_XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512: + return X86CommonArchitecture::cached_input_types[348]; +case INTRINSIC_XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[349]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512: + return X86CommonArchitecture::cached_input_types[349]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[349]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512: + return X86CommonArchitecture::cached_input_types[349]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[349]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512: + return X86CommonArchitecture::cached_input_types[349]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[350]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512: + return X86CommonArchitecture::cached_input_types[350]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[350]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512: + return X86CommonArchitecture::cached_input_types[350]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[350]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512: + return X86CommonArchitecture::cached_input_types[350]; +case INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[351]; +case INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[351]; +case INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[352]; +case INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[352]; +case INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[353]; +case INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[353]; +case INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[351]; +case INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[351]; +case INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[352]; +case INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[352]; +case INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[353]; +case INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[353]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[354]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_input_types[354]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[355]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_input_types[355]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[356]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_input_types[356]; +case INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[354]; +case INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[354]; +case INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[355]; +case INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[355]; +case INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[356]; +case INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[356]; +case INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[357]; +case INTRINSIC_XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[357]; +case INTRINSIC_XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[358]; +case INTRINSIC_XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[358]; +case INTRINSIC_XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[359]; +case INTRINSIC_XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[359]; +case INTRINSIC_XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[360]; +case INTRINSIC_XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[360]; +case INTRINSIC_XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[361]; +case INTRINSIC_XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[361]; +case INTRINSIC_XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[362]; +case INTRINSIC_XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[362]; +case INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[357]; +case INTRINSIC_XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[357]; +case INTRINSIC_XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[358]; +case INTRINSIC_XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[358]; +case INTRINSIC_XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[359]; +case INTRINSIC_XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[359]; +case INTRINSIC_XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[330]; +case INTRINSIC_XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[331]; +case INTRINSIC_XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[332]; +case INTRINSIC_XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[333]; +case INTRINSIC_XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[300]; +case INTRINSIC_XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[334]; +case INTRINSIC_XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[360]; +case INTRINSIC_XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[360]; +case INTRINSIC_XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[361]; +case INTRINSIC_XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[361]; +case INTRINSIC_XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[362]; +case INTRINSIC_XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[362]; +case INTRINSIC_XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[349]; +case INTRINSIC_XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[349]; +case INTRINSIC_XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[349]; +case INTRINSIC_XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[350]; +case INTRINSIC_XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[350]; +case INTRINSIC_XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[350]; +case INTRINSIC_XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[349]; +case INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[349]; +case INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[349]; +case INTRINSIC_XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[350]; +case INTRINSIC_XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[350]; +case INTRINSIC_XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[350]; +case INTRINSIC_XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[351]; +case INTRINSIC_XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[351]; +case INTRINSIC_XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[352]; +case INTRINSIC_XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[352]; +case INTRINSIC_XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[353]; +case INTRINSIC_XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[353]; +case INTRINSIC_XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[354]; +case INTRINSIC_XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_input_types[354]; +case INTRINSIC_XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[355]; +case INTRINSIC_XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_input_types[355]; +case INTRINSIC_XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[356]; +case INTRINSIC_XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_input_types[356]; +case INTRINSIC_XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[351]; +case INTRINSIC_XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[351]; +case INTRINSIC_XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[352]; +case INTRINSIC_XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[352]; +case INTRINSIC_XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[353]; +case INTRINSIC_XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[353]; +case INTRINSIC_XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[354]; +case INTRINSIC_XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_input_types[354]; +case INTRINSIC_XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[355]; +case INTRINSIC_XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_input_types[355]; +case INTRINSIC_XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[356]; +case INTRINSIC_XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_input_types[356]; +case INTRINSIC_XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[321]; +case INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[321]; +case INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[320]; +case INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[320]; +case INTRINSIC_XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[321]; +case INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[321]; +case INTRINSIC_XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[320]; +case INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[320]; +case INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[346]; +case INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[346]; +case INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[347]; +case INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[347]; +case INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[348]; +case INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[348]; +case INTRINSIC_XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[346]; +case INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[346]; +case INTRINSIC_XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[347]; +case INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[347]; +case INTRINSIC_XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[348]; +case INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[348]; +case INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[346]; +case INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[346]; +case INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[347]; +case INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[347]; +case INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[348]; +case INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512: + return X86CommonArchitecture::cached_input_types[348]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[364]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[365]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[365]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[366]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[364]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[320]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[320]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[367]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[368]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[368]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[370]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[371]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[370]; +case INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[364]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[365]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[365]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[366]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[364]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[320]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[320]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[367]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[322]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[368]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[368]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[370]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[371]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[370]; +case INTRINSIC_XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[354]; +case INTRINSIC_XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[354]; +case INTRINSIC_XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[355]; +case INTRINSIC_XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[355]; +case INTRINSIC_XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[356]; +case INTRINSIC_XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[356]; +case INTRINSIC_XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[340]; +case INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[340]; +case INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[341]; +case INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[341]; +case INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[372]; +case INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[372]; +case INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[373]; +case INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[373]; +case INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[340]; +case INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[340]; +case INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[341]; +case INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[341]; +case INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[372]; +case INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[372]; +case INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[373]; +case INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[373]; +case INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[340]; +case INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[340]; +case INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[341]; +case INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[341]; +case INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[372]; +case INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[372]; +case INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[373]; +case INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[373]; +case INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[357]; +case INTRINSIC_XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[357]; +case INTRINSIC_XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[358]; +case INTRINSIC_XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[358]; +case INTRINSIC_XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[359]; +case INTRINSIC_XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[359]; +case INTRINSIC_XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[360]; +case INTRINSIC_XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[360]; +case INTRINSIC_XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[361]; +case INTRINSIC_XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[361]; +case INTRINSIC_XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[362]; +case INTRINSIC_XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[362]; +case INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[134]; +case INTRINSIC_XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[199]; +case INTRINSIC_XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[129]; +case INTRINSIC_XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[200]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512: + return X86CommonArchitecture::cached_input_types[15]; +case INTRINSIC_XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512: + return X86CommonArchitecture::cached_input_types[49]; +case INTRINSIC_XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[374]; +case INTRINSIC_XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[374]; +case INTRINSIC_XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[375]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[375]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[303]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[375]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[304]; +case INTRINSIC_XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[306]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[302]; +case INTRINSIC_XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[307]; +case INTRINSIC_XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[305]; +case INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[317]; +case INTRINSIC_XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[319]; +case INTRINSIC_XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[379]; +case INTRINSIC_XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[379]; +case INTRINSIC_XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[380]; +case INTRINSIC_XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[380]; +case INTRINSIC_XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[381]; +case INTRINSIC_XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[381]; +case INTRINSIC_XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[382]; +case INTRINSIC_XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[382]; +case INTRINSIC_XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[373]; +case INTRINSIC_XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[373]; +case INTRINSIC_XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[372]; +case INTRINSIC_XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[372]; +case INTRINSIC_XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[386]; +case INTRINSIC_XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[386]; +case INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[386]; +case INTRINSIC_XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[387]; +case INTRINSIC_XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[387]; +case INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[387]; +case INTRINSIC_XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[388]; +case INTRINSIC_XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[388]; +case INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[388]; +case INTRINSIC_XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[389]; +case INTRINSIC_XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[389]; +case INTRINSIC_XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[390]; +case INTRINSIC_XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[390]; +case INTRINSIC_XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[368]; +case INTRINSIC_XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[368]; +case INTRINSIC_XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[391]; +case INTRINSIC_XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[391]; +case INTRINSIC_XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[352]; +case INTRINSIC_XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[352]; +case INTRINSIC_XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[353]; +case INTRINSIC_XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[353]; +case INTRINSIC_XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512: + return X86CommonArchitecture::cached_input_types[351]; +case INTRINSIC_XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_input_types[351]; +case INTRINSIC_XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[398]; +case INTRINSIC_XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[398]; +case INTRINSIC_XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[399]; +case INTRINSIC_XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[399]; +case INTRINSIC_XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[400]; +case INTRINSIC_XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[400]; +case INTRINSIC_XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[386]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[401]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512: + return X86CommonArchitecture::cached_input_types[402]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[386]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[401]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512: + return X86CommonArchitecture::cached_input_types[402]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[386]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[401]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512: + return X86CommonArchitecture::cached_input_types[402]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[403]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512: + return X86CommonArchitecture::cached_input_types[404]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[403]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512: + return X86CommonArchitecture::cached_input_types[404]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[403]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512: + return X86CommonArchitecture::cached_input_types[404]; +case INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[398]; +case INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[398]; +case INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[399]; +case INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[399]; +case INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[400]; +case INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[400]; +case INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[405]; +case INTRINSIC_XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[405]; +case INTRINSIC_XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[406]; +case INTRINSIC_XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[406]; +case INTRINSIC_XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[407]; +case INTRINSIC_XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[407]; +case INTRINSIC_XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[405]; +case INTRINSIC_XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[405]; +case INTRINSIC_XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[406]; +case INTRINSIC_XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[406]; +case INTRINSIC_XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[407]; +case INTRINSIC_XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[407]; +case INTRINSIC_XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[72]; +case INTRINSIC_XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[72]; +case INTRINSIC_XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[249]; +case INTRINSIC_XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[248]; +case INTRINSIC_XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[252]; +case INTRINSIC_XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[252]; +case INTRINSIC_XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[253]; +case INTRINSIC_XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[253]; +case INTRINSIC_XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[251]; +case INTRINSIC_XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[250]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[398]; +case INTRINSIC_XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[398]; +case INTRINSIC_XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[399]; +case INTRINSIC_XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[399]; +case INTRINSIC_XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[400]; +case INTRINSIC_XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[400]; +case INTRINSIC_XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[398]; +case INTRINSIC_XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[398]; +case INTRINSIC_XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[399]; +case INTRINSIC_XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[399]; +case INTRINSIC_XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[400]; +case INTRINSIC_XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[400]; +case INTRINSIC_XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[408]; +case INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[409]; +case INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[66]; +case INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[222]; +case INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[343]; +case INTRINSIC_XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512: + return X86CommonArchitecture::cached_input_types[276]; +case INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[72]; +case INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[233]; +case INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[410]; +case INTRINSIC_XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[369]; +case INTRINSIC_XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[368]; +case INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[368]; +case INTRINSIC_XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[391]; +case INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[391]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[365]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[389]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[389]; +case INTRINSIC_XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[57]; +case INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[223]; +case INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[411]; +case INTRINSIC_XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[365]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[363]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[389]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[389]; +case INTRINSIC_XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[138]; +case INTRINSIC_XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[240]; +case INTRINSIC_XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[412]; +case INTRINSIC_XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[412]; +case INTRINSIC_XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[408]; +case INTRINSIC_XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[408]; +case INTRINSIC_XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[409]; +case INTRINSIC_XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[409]; +case INTRINSIC_XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[413]; +case INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[413]; +case INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[414]; +case INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[414]; +case INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[413]; +case INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[413]; +case INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[414]; +case INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[414]; +case INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[185]; +case INTRINSIC_XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[408]; +case INTRINSIC_XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[408]; +case INTRINSIC_XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[409]; +case INTRINSIC_XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[409]; +case INTRINSIC_XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[413]; +case INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[413]; +case INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[414]; +case INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[414]; +case INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[398]; +case INTRINSIC_XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[398]; +case INTRINSIC_XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[399]; +case INTRINSIC_XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[399]; +case INTRINSIC_XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + return X86CommonArchitecture::cached_input_types[400]; +case INTRINSIC_XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_input_types[400]; +case INTRINSIC_XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[392]; +case INTRINSIC_XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[393]; +case INTRINSIC_XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_input_types[394]; +case INTRINSIC_XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[309]; +case INTRINSIC_XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[308]; +case INTRINSIC_XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[285]; +case INTRINSIC_XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[286]; +case INTRINSIC_XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[318]; +case INTRINSIC_XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[316]; +case INTRINSIC_XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[293]; +case INTRINSIC_XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[287]; +case INTRINSIC_XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[288]; +case INTRINSIC_XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[289]; +case INTRINSIC_XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[296]; +case INTRINSIC_XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[297]; +case INTRINSIC_XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[284]; +case INTRINSIC_XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[298]; +case INTRINSIC_XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[361]; +case INTRINSIC_XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[361]; +case INTRINSIC_XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[362]; +case INTRINSIC_XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[362]; +case INTRINSIC_XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[360]; +case INTRINSIC_XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[360]; +case INTRINSIC_XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[361]; +case INTRINSIC_XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[361]; +case INTRINSIC_XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[362]; +case INTRINSIC_XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[362]; +case INTRINSIC_XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[360]; +case INTRINSIC_XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[360]; +case INTRINSIC_XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[415]; +case INTRINSIC_XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[415]; +case INTRINSIC_XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[416]; +case INTRINSIC_XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[416]; +case INTRINSIC_XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[417]; +case INTRINSIC_XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[417]; +case INTRINSIC_XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[415]; +case INTRINSIC_XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[415]; +case INTRINSIC_XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[416]; +case INTRINSIC_XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[416]; +case INTRINSIC_XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[417]; +case INTRINSIC_XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[417]; +case INTRINSIC_XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[418]; +case INTRINSIC_XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[418]; +case INTRINSIC_XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[419]; +case INTRINSIC_XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[419]; +case INTRINSIC_XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[420]; +case INTRINSIC_XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[420]; +case INTRINSIC_XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[386]; +case INTRINSIC_XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[386]; +case INTRINSIC_XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[387]; +case INTRINSIC_XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[387]; +case INTRINSIC_XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[388]; +case INTRINSIC_XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[388]; +case INTRINSIC_XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[421]; +case INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[421]; +case INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[422]; +case INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[422]; +case INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[423]; +case INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[423]; +case INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[386]; +case INTRINSIC_XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[386]; +case INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[387]; +case INTRINSIC_XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[387]; +case INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[388]; +case INTRINSIC_XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[388]; +case INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[386]; +case INTRINSIC_XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[386]; +case INTRINSIC_XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[387]; +case INTRINSIC_XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[387]; +case INTRINSIC_XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[388]; +case INTRINSIC_XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[388]; +case INTRINSIC_XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[383]; +case INTRINSIC_XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[384]; +case INTRINSIC_XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[385]; +case INTRINSIC_XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[358]; +case INTRINSIC_XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[358]; +case INTRINSIC_XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[359]; +case INTRINSIC_XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[359]; +case INTRINSIC_XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[357]; +case INTRINSIC_XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[357]; +case INTRINSIC_XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[361]; +case INTRINSIC_XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[361]; +case INTRINSIC_XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[362]; +case INTRINSIC_XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[362]; +case INTRINSIC_XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[360]; +case INTRINSIC_XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[360]; +case INTRINSIC_XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[405]; +case INTRINSIC_XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[405]; +case INTRINSIC_XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[406]; +case INTRINSIC_XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[406]; +case INTRINSIC_XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[407]; +case INTRINSIC_XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[407]; +case INTRINSIC_XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[311]; +case INTRINSIC_XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[312]; +case INTRINSIC_XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[310]; +case INTRINSIC_XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[314]; +case INTRINSIC_XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[315]; +case INTRINSIC_XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[313]; +case INTRINSIC_XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[358]; +case INTRINSIC_XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[358]; +case INTRINSIC_XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[359]; +case INTRINSIC_XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[359]; +case INTRINSIC_XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[357]; +case INTRINSIC_XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[357]; +case INTRINSIC_XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[361]; +case INTRINSIC_XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[361]; +case INTRINSIC_XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[362]; +case INTRINSIC_XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[362]; +case INTRINSIC_XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[360]; +case INTRINSIC_XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[360]; +case INTRINSIC_XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[405]; +case INTRINSIC_XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[405]; +case INTRINSIC_XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[406]; +case INTRINSIC_XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[406]; +case INTRINSIC_XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_input_types[407]; +case INTRINSIC_XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_input_types[407]; +case INTRINSIC_XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[395]; +case INTRINSIC_XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[396]; +case INTRINSIC_XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[397]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[418]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[418]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[419]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[419]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[420]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[420]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[418]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[418]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[419]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[419]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[420]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[420]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[376]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[377]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_input_types[378]; +case INTRINSIC_XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512: + return X86CommonArchitecture::cached_input_types[424]; +case INTRINSIC_XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_input_types[424]; +case INTRINSIC_XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512: + return X86CommonArchitecture::cached_input_types[424]; +case INTRINSIC_XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_input_types[424]; +case INTRINSIC_XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512: + return X86CommonArchitecture::cached_input_types[424]; +case INTRINSIC_XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_input_types[424]; +case INTRINSIC_XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_input_types[218]; +case INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_input_types[258]; +case INTRINSIC_XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512: + return X86CommonArchitecture::cached_input_types[424]; +case INTRINSIC_XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_input_types[424]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[425]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_input_types[425]; +case INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[116]; +case INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[242]; +case INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_input_types[426]; +case INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_input_types[426]; +case INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[74]; +case INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[201]; +case INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_input_types[425]; +case INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_input_types[425]; diff --git a/arch/x86/x86_intrinsic_output_type.include b/arch/x86/x86_intrinsic_output_type.include new file mode 100644 index 00000000..f17677e6 --- /dev/null +++ b/arch/x86/x86_intrinsic_output_type.include @@ -0,0 +1,12670 @@ +// Generated file, please do not edit directly + +case INTRINSIC_XED_IFORM_FADD_ST0_MEMmem32real: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FADD_ST0_X87: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FADD_ST0_MEMm64real: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FADD_X87_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FMUL_ST0_MEMmem32real: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FMUL_ST0_X87: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FMUL_ST0_MEMm64real: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FMUL_X87_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FCOMP_ST0_MEMmem32real: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FCOMP_ST0_X87: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FCOMP_ST0_X87_DCD1: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FCOMP_ST0_X87_DED0: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FCOMP_ST0_MEMm64real: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FSUB_ST0_MEMmem32real: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSUB_ST0_X87: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSUB_ST0_MEMm64real: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSUB_X87_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSUBR_ST0_MEMmem32real: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSUBR_ST0_X87: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSUBR_ST0_MEMm64real: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSUBR_X87_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FDIV_ST0_MEMmem32real: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FDIV_ST0_X87: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FDIV_ST0_MEMm64real: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FDIV_X87_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FDIVR_ST0_MEMmem32real: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FDIVR_ST0_X87: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FDIVR_ST0_MEMm64real: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FDIVR_X87_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FCOM_ST0_MEMmem32real: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FCOM_ST0_MEMm64real: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FCOM_ST0_X87: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FCOM_ST0_X87_DCD0: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FLD_ST0_MEMmem32real: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FLD_ST0_X87: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FLD_ST0_MEMmem80real: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FLD_ST0_MEMm64real: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FST_MEMmem32real_ST0: + return X86CommonArchitecture::cached_output_types[2]; +case INTRINSIC_XED_IFORM_FST_MEMm64real_ST0: + return X86CommonArchitecture::cached_output_types[3]; +case INTRINSIC_XED_IFORM_FST_X87_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSTP_MEMmem32real_ST0: + return X86CommonArchitecture::cached_output_types[2]; +case INTRINSIC_XED_IFORM_FSTP_MEMmem80real_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSTP_MEMm64real_ST0: + return X86CommonArchitecture::cached_output_types[3]; +case INTRINSIC_XED_IFORM_FSTP_X87_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSTP_X87_ST0_DFD0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSTP_X87_ST0_DFD1: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSTPNCE_X87_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FLDENV_MEMmem14: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FLDENV_MEMmem28: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FLDCW_MEMmem16: + return X86CommonArchitecture::cached_output_types[4]; +case INTRINSIC_XED_IFORM_FNSTENV_MEMmem14: + return X86CommonArchitecture::cached_output_types[5]; +case INTRINSIC_XED_IFORM_FNSTENV_MEMmem28: + return X86CommonArchitecture::cached_output_types[6]; +case INTRINSIC_XED_IFORM_FNSTCW_MEMmem16: + return X86CommonArchitecture::cached_output_types[7]; +case INTRINSIC_XED_IFORM_FXCH_ST0_X87: + return X86CommonArchitecture::cached_output_types[8]; +case INTRINSIC_XED_IFORM_FXCH_ST0_X87_DFC1: + return X86CommonArchitecture::cached_output_types[8]; +case INTRINSIC_XED_IFORM_FXCH_ST0_X87_DDC1: + return X86CommonArchitecture::cached_output_types[8]; +case INTRINSIC_XED_IFORM_FNOP: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_FCHS: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FABS: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FTST: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FXAM: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FLD1: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FLDL2T: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FLDL2E: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FLDPI: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FLDLG2: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FLDLN2: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FLDZ: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_F2XM1: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FYL2X: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FPTAN: + return X86CommonArchitecture::cached_output_types[8]; +case INTRINSIC_XED_IFORM_FPATAN: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FXTRACT: + return X86CommonArchitecture::cached_output_types[8]; +case INTRINSIC_XED_IFORM_FPREM1: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FDECSTP: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FINCSTP: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FPREM: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FYL2XP1: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSQRT: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSINCOS: + return X86CommonArchitecture::cached_output_types[8]; +case INTRINSIC_XED_IFORM_FRNDINT: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSCALE: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSIN: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FCOS: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FIADD_ST0_MEMmem32int: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FIADD_ST0_MEMmem16int: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FIMUL_ST0_MEMmem32int: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FIMUL_ST0_MEMmem16int: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FICOM_ST0_MEMmem32int: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FICOM_ST0_MEMmem16int: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FICOMP_ST0_MEMmem32int: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FICOMP_ST0_MEMmem16int: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FISUB_ST0_MEMmem32int: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FISUB_ST0_MEMmem16int: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FISUBR_ST0_MEMmem32int: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FISUBR_ST0_MEMmem16int: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FIDIV_ST0_MEMmem32int: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FIDIV_ST0_MEMmem16int: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FIDIVR_ST0_MEMmem32int: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FIDIVR_ST0_MEMmem16int: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FCMOVB_ST0_X87: + return X86CommonArchitecture::cached_output_types[10]; +case INTRINSIC_XED_IFORM_FCMOVE_ST0_X87: + return X86CommonArchitecture::cached_output_types[10]; +case INTRINSIC_XED_IFORM_FCMOVBE_ST0_X87: + return X86CommonArchitecture::cached_output_types[10]; +case INTRINSIC_XED_IFORM_FCMOVU_ST0_X87: + return X86CommonArchitecture::cached_output_types[10]; +case INTRINSIC_XED_IFORM_FUCOMPP: + return X86CommonArchitecture::cached_output_types[11]; +case INTRINSIC_XED_IFORM_FILD_ST0_MEMmem32int: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FILD_ST0_MEMmem16int: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FILD_ST0_MEMm64int: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FISTTP_MEMmem32int_ST0: + return X86CommonArchitecture::cached_output_types[12]; +case INTRINSIC_XED_IFORM_FISTTP_MEMm64int_ST0: + return X86CommonArchitecture::cached_output_types[13]; +case INTRINSIC_XED_IFORM_FISTTP_MEMmem16int_ST0: + return X86CommonArchitecture::cached_output_types[14]; +case INTRINSIC_XED_IFORM_FIST_MEMmem32int_ST0: + return X86CommonArchitecture::cached_output_types[12]; +case INTRINSIC_XED_IFORM_FIST_MEMmem16int_ST0: + return X86CommonArchitecture::cached_output_types[14]; +case INTRINSIC_XED_IFORM_FISTP_MEMmem32int_ST0: + return X86CommonArchitecture::cached_output_types[12]; +case INTRINSIC_XED_IFORM_FISTP_MEMmem16int_ST0: + return X86CommonArchitecture::cached_output_types[14]; +case INTRINSIC_XED_IFORM_FISTP_MEMm64int_ST0: + return X86CommonArchitecture::cached_output_types[13]; +case INTRINSIC_XED_IFORM_FCMOVNB_ST0_X87: + return X86CommonArchitecture::cached_output_types[10]; +case INTRINSIC_XED_IFORM_FCMOVNE_ST0_X87: + return X86CommonArchitecture::cached_output_types[10]; +case INTRINSIC_XED_IFORM_FCMOVNBE_ST0_X87: + return X86CommonArchitecture::cached_output_types[10]; +case INTRINSIC_XED_IFORM_FCMOVNU_ST0_X87: + return X86CommonArchitecture::cached_output_types[10]; +case INTRINSIC_XED_IFORM_FNCLEX: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FNINIT: + return X86CommonArchitecture::cached_output_types[15]; +case INTRINSIC_XED_IFORM_FSETPM287_NOP: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_FENI8087_NOP: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_FDISI8087_NOP: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_FUCOMI_ST0_X87: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_FCOMI_ST0_X87: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_FRSTOR_MEMmem94: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FRSTOR_MEMmem108: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FNSAVE_MEMmem94: + return X86CommonArchitecture::cached_output_types[17]; +case INTRINSIC_XED_IFORM_FNSAVE_MEMmem108: + return X86CommonArchitecture::cached_output_types[18]; +case INTRINSIC_XED_IFORM_FNSTSW_MEMmem16: + return X86CommonArchitecture::cached_output_types[7]; +case INTRINSIC_XED_IFORM_FNSTSW_AX: + return X86CommonArchitecture::cached_output_types[4]; +case INTRINSIC_XED_IFORM_FFREE_X87: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FUCOM_ST0_X87: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FUCOMP_ST0_X87: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FADDP_X87_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FMULP_X87_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FCOMPP: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FSUBRP_X87_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FSUBP_X87_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FDIVRP_X87_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FDIVP_X87_ST0: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FBLD_ST0_MEMmem80dec: + return X86CommonArchitecture::cached_output_types[0]; +case INTRINSIC_XED_IFORM_FBSTP_MEMmem80dec_ST0: + return X86CommonArchitecture::cached_output_types[19]; +case INTRINSIC_XED_IFORM_FFREEP_X87: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FUCOMIP_ST0_X87: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_FCOMIP_ST0_X87: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADD_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADD_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADD_MEMb_IMMb_80r0: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADD_GPR8_IMMb_80r0: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADD_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADD_GPRv_IMMz: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_ADD_MEMb_IMMb_82r0: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADD_GPR8_IMMb_82r0: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADD_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADD_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_ADD_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADD_GPR8_GPR8_00: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADD_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_01: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_ADD_GPR8_MEMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADD_GPR8_GPR8_02: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADD_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_ADD_GPRv_GPRv_03: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_ADD_AL_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADD_OrAX_IMMz: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_OR_LOCK_MEMb_IMMb_80r1: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_OR_LOCK_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_OR_LOCK_MEMb_IMMb_82r1: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_OR_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_OR_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_OR_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_OR_MEMb_IMMb_80r1: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_OR_GPR8_IMMb_80r1: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_OR_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_OR_GPRv_IMMz: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_OR_MEMb_IMMb_82r1: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_OR_GPR8_IMMb_82r1: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_OR_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_OR_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_OR_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_OR_GPR8_GPR8_08: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_OR_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_OR_GPRv_GPRv_09: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_OR_GPR8_MEMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_OR_GPR8_GPR8_0A: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_OR_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_OR_GPRv_GPRv_0B: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_OR_AL_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_OR_OrAX_IMMz: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADC_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADC_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADC_MEMb_IMMb_80r2: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADC_GPR8_IMMb_80r2: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADC_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADC_GPRv_IMMz: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_ADC_MEMb_IMMb_82r2: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADC_GPR8_IMMb_82r2: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADC_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADC_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_ADC_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADC_GPR8_GPR8_10: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADC_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_11: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_ADC_GPR8_MEMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADC_GPR8_GPR8_12: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADC_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_ADC_GPRv_GPRv_13: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_ADC_AL_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ADC_OrAX_IMMz: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SBB_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SBB_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SBB_MEMb_IMMb_80r3: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SBB_GPR8_IMMb_80r3: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SBB_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SBB_GPRv_IMMz: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SBB_MEMb_IMMb_82r3: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SBB_GPR8_IMMb_82r3: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SBB_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SBB_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SBB_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SBB_GPR8_GPR8_18: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SBB_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_19: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SBB_GPR8_GPR8_1A: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SBB_GPR8_MEMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SBB_GPRv_GPRv_1B: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SBB_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SBB_AL_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SBB_OrAX_IMMz: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_AND_LOCK_MEMb_IMMb_80r4: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_AND_LOCK_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_AND_LOCK_MEMb_IMMb_82r4: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_AND_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_AND_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_AND_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_AND_MEMb_IMMb_80r4: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_AND_GPR8_IMMb_80r4: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_AND_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_AND_GPRv_IMMz: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_AND_MEMb_IMMb_82r4: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_AND_GPR8_IMMb_82r4: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_AND_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_AND_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_AND_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_AND_GPR8_GPR8_20: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_AND_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_AND_GPRv_GPRv_21: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_AND_GPR8_GPR8_22: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_AND_GPR8_MEMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_AND_GPRv_GPRv_23: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_AND_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_AND_AL_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_AND_OrAX_IMMz: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SUB_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SUB_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SUB_MEMb_IMMb_80r5: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SUB_GPR8_IMMb_80r5: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SUB_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SUB_GPRv_IMMz: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SUB_MEMb_IMMb_82r5: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SUB_GPR8_IMMb_82r5: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SUB_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SUB_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SUB_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SUB_GPR8_GPR8_28: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SUB_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SUB_GPRv_GPRv_29: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SUB_GPR8_GPR8_2A: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SUB_GPR8_MEMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SUB_GPRv_GPRv_2B: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SUB_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SUB_AL_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SUB_OrAX_IMMz: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_XOR_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_XOR_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_XOR_MEMb_IMMb_80r6: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_XOR_GPR8_IMMb_80r6: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_XOR_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_XOR_GPRv_IMMz: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_XOR_MEMb_IMMb_82r6: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_XOR_GPR8_IMMb_82r6: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_XOR_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_XOR_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_XOR_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_XOR_GPR8_GPR8_30: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_XOR_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_XOR_GPRv_GPRv_31: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_XOR_GPR8_GPR8_32: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_XOR_GPR8_MEMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_XOR_GPRv_GPRv_33: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_XOR_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_XOR_AL_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_XOR_OrAX_IMMz: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_CMP_MEMb_IMMb_80r7: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_GPR8_IMMb_80r7: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_GPRv_IMMz: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_MEMb_IMMb_82r7: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_GPR8_IMMb_82r7: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_GPR8_GPR8_38: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_GPRv_GPRv_39: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_GPR8_MEMb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_GPR8_GPR8_3A: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_GPRv_GPRv_3B: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_AL_IMMb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMP_OrAX_IMMz: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_POP_MEMv: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_POP_GPRv_8F: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_POP_ES: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_POP_SS: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_POP_DS: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_POP_GPRv_58: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_POP_FS: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_POP_GS: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_ROL_MEMb_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ROL_GPR8_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ROL_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ROL_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_ROL_MEMb_ONE: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ROL_GPR8_ONE: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ROL_MEMv_ONE: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ROL_GPRv_ONE: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_ROL_MEMb_CL: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ROL_GPR8_CL: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ROL_MEMv_CL: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ROL_GPRv_CL: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_ROR_MEMb_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ROR_GPR8_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ROR_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_ROR_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ROR_MEMb_ONE: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ROR_GPR8_ONE: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ROR_MEMv_ONE: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ROR_GPRv_ONE: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_ROR_MEMb_CL: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ROR_GPR8_CL: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_ROR_MEMv_CL: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ROR_GPRv_CL: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_RCL_MEMb_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_RCL_GPR8_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_RCL_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_RCL_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_RCL_MEMb_ONE: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_RCL_GPR8_ONE: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_RCL_MEMv_ONE: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_RCL_GPRv_ONE: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_RCL_MEMb_CL: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_RCL_GPR8_CL: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_RCL_MEMv_CL: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_RCL_GPRv_CL: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_RCR_MEMb_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_RCR_GPR8_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_RCR_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_RCR_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_RCR_MEMb_ONE: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_RCR_GPR8_ONE: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_RCR_MEMv_ONE: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_RCR_GPRv_ONE: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_RCR_MEMb_CL: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_RCR_GPR8_CL: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_RCR_MEMv_CL: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_RCR_GPRv_CL: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SHL_MEMb_IMMb_C0r4: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHL_GPR8_IMMb_C0r4: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHL_MEMb_IMMb_C0r6: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHL_GPR8_IMMb_C0r6: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHL_MEMv_IMMb_C1r4: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SHL_GPRv_IMMb_C1r4: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SHL_MEMv_IMMb_C1r6: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SHL_GPRv_IMMb_C1r6: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SHL_MEMb_ONE_D0r4: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHL_GPR8_ONE_D0r4: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHL_MEMb_ONE_D0r6: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHL_GPR8_ONE_D0r6: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHL_MEMv_ONE_D1r6: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SHL_GPRv_ONE_D1r6: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SHL_MEMv_ONE_D1r4: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SHL_GPRv_ONE_D1r4: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SHL_MEMb_CL_D2r4: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHL_GPR8_CL_D2r4: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHL_MEMb_CL_D2r6: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHL_GPR8_CL_D2r6: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHL_MEMv_CL_D3r4: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SHL_GPRv_CL_D3r4: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SHL_MEMv_CL_D3r6: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SHL_GPRv_CL_D3r6: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SHR_MEMb_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHR_GPR8_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHR_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SHR_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SHR_MEMb_ONE: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHR_GPR8_ONE: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHR_MEMv_ONE: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SHR_GPRv_ONE: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SHR_MEMb_CL: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHR_GPR8_CL: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SHR_MEMv_CL: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SHR_GPRv_CL: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SAR_MEMb_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SAR_GPR8_IMMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SAR_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SAR_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SAR_MEMb_ONE: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SAR_GPR8_ONE: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SAR_MEMv_ONE: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SAR_GPRv_ONE: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SAR_MEMb_CL: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SAR_GPR8_CL: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_SAR_MEMv_CL: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SAR_GPRv_CL: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_TEST_MEMb_IMMb_F6r0: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_TEST_MEMb_IMMb_F6r1: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_TEST_GPR8_IMMb_F6r0: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_TEST_GPR8_IMMb_F6r1: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_TEST_MEMv_IMMz_F7r0: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_TEST_MEMv_IMMz_F7r1: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_TEST_GPRv_IMMz_F7r0: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_TEST_GPRv_IMMz_F7r1: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_TEST_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_TEST_GPR8_GPR8: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_TEST_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_TEST_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_TEST_AL_IMMb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_TEST_OrAX_IMMz: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_NOT_LOCK_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_NOT_LOCK_MEMv: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_NOT_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_NOT_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_NOT_MEMv: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_NOT_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_NEG_LOCK_MEMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_NEG_LOCK_MEMv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_NEG_MEMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_NEG_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_NEG_MEMv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_NEG_GPRv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_MUL_MEMb: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_MUL_GPR8: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_MUL_MEMv: + return X86CommonArchitecture::cached_output_types[26]; +case INTRINSIC_XED_IFORM_MUL_GPRv: + return X86CommonArchitecture::cached_output_types[26]; +case INTRINSIC_XED_IFORM_IMUL_MEMb: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_IMUL_GPR8: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_IMUL_MEMv: + return X86CommonArchitecture::cached_output_types[26]; +case INTRINSIC_XED_IFORM_IMUL_GPRv: + return X86CommonArchitecture::cached_output_types[26]; +case INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_IMMz: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_IMUL_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_IMUL_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_DIV_MEMb: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_DIV_GPR8: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_DIV_MEMv: + return X86CommonArchitecture::cached_output_types[26]; +case INTRINSIC_XED_IFORM_DIV_GPRv: + return X86CommonArchitecture::cached_output_types[26]; +case INTRINSIC_XED_IFORM_IDIV_MEMb: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_IDIV_GPR8: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_IDIV_MEMv: + return X86CommonArchitecture::cached_output_types[26]; +case INTRINSIC_XED_IFORM_IDIV_GPRv: + return X86CommonArchitecture::cached_output_types[26]; +case INTRINSIC_XED_IFORM_INC_LOCK_MEMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_INC_LOCK_MEMv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_INC_MEMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_INC_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_INC_MEMv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_INC_GPRv_FFr0: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_INC_GPRv_40: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_DEC_LOCK_MEMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_DEC_LOCK_MEMv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_DEC_MEMb: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_DEC_GPR8: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_DEC_MEMv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_DEC_GPRv_FFr1: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_DEC_GPRv_48: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_CALL_NEAR_MEMv: + return X86CommonArchitecture::cached_output_types[27]; +case INTRINSIC_XED_IFORM_CALL_NEAR_GPRv: + return X86CommonArchitecture::cached_output_types[27]; +case INTRINSIC_XED_IFORM_CALL_NEAR_RELBRz: + return X86CommonArchitecture::cached_output_types[28]; +case INTRINSIC_XED_IFORM_CALL_NEAR_RELBRd: + return X86CommonArchitecture::cached_output_types[27]; +case INTRINSIC_XED_IFORM_JMP_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JMP_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JMP_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JMP_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JMP_RELBRb: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JMP_FAR_MEMp2: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JMP_FAR_PTRp_IMMw: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_PUSH_MEMv: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_PUSH_GPRv_FFr6: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_PUSH_ES: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_PUSH_CS: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_PUSH_SS: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_PUSH_DS: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_PUSH_GPRv_50: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_PUSH_IMMz: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_PUSH_IMMb: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_PUSH_FS: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_PUSH_GS: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_SLDT_MEMw: + return X86CommonArchitecture::cached_output_types[31]; +case INTRINSIC_XED_IFORM_SLDT_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_STR_MEMw: + return X86CommonArchitecture::cached_output_types[31]; +case INTRINSIC_XED_IFORM_STR_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_LLDT_MEMw: + return X86CommonArchitecture::cached_output_types[32]; +case INTRINSIC_XED_IFORM_LLDT_GPR16: + return X86CommonArchitecture::cached_output_types[32]; +case INTRINSIC_XED_IFORM_LTR_MEMw: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_LTR_GPR16: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VERR_MEMw: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VERR_GPR16: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VERW_MEMw: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VERW_GPR16: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_LGDT_MEMs64: + return X86CommonArchitecture::cached_output_types[32]; +case INTRINSIC_XED_IFORM_LGDT_MEMs: + return X86CommonArchitecture::cached_output_types[32]; +case INTRINSIC_XED_IFORM_SMSW_MEMw: + return X86CommonArchitecture::cached_output_types[31]; +case INTRINSIC_XED_IFORM_SMSW_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_LMSW_MEMw: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_LMSW_GPR16: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_BT_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_BT_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_BT_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_BT_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_BTS_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BTS_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BTS_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BTS_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_BTS_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BTS_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_BTR_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BTR_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BTR_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BTR_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_BTR_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BTR_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_BTC_LOCK_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BTC_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BTC_MEMv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BTC_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_BTC_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BTC_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_VMCLEAR_MEMq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VMPTRLD_MEMq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VMPTRST_MEMq: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_VMXON_MEMq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMPXCHG8B_LOCK_MEMq: + return X86CommonArchitecture::cached_output_types[34]; +case INTRINSIC_XED_IFORM_CMPXCHG8B_MEMq: + return X86CommonArchitecture::cached_output_types[34]; +case INTRINSIC_XED_IFORM_CMPXCHG16B_LOCK_MEMdq: + return X86CommonArchitecture::cached_output_types[35]; +case INTRINSIC_XED_IFORM_CMPXCHG16B_MEMdq: + return X86CommonArchitecture::cached_output_types[35]; +case INTRINSIC_XED_IFORM_MOV_GPR8_IMMb_C6r0: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_MOV_MEMb_IMMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_MOV_GPRv_IMMz: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOV_MEMv_IMMz: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_MOV_GPR8_GPR8_88: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_MOV_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_MOV_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_MOV_GPRv_GPRv_89: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOV_GPR8_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_MOV_GPR8_GPR8_8A: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_MOV_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOV_GPRv_GPRv_8B: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOV_MEMw_SEG: + return X86CommonArchitecture::cached_output_types[31]; +case INTRINSIC_XED_IFORM_MOV_GPRv_SEG: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOV_SEG_MEMw: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_MOV_SEG_GPR16: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_MOV_AL_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_MOV_OrAX_MEMv: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_MOV_MEMb_AL: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_MOV_MEMv_OrAX: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_MOV_GPR8_IMMb_B0: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOV_GPRv_IMMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PSRLW_MMXq_IMMb: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_PSRLW_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_PSRLW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_PSRLW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_PSRLW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSRLW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSRAW_MMXq_IMMb: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PSRAW_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PSRAW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PSRAW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PSRAW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PSRAW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PSLLW_MMXq_IMMb: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_PSLLW_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_PSLLW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_PSLLW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_PSLLW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_PSLLW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_PSRLD_MMXq_IMMb: + return X86CommonArchitecture::cached_output_types[41]; +case INTRINSIC_XED_IFORM_PSRLD_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_PSRLD_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[41]; +case INTRINSIC_XED_IFORM_PSRLD_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[41]; +case INTRINSIC_XED_IFORM_PSRLD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSRLD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSRAD_MMXq_IMMb: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_PSRAD_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSRAD_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_PSRAD_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_PSRAD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSRAD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSLLD_MMXq_IMMb: + return X86CommonArchitecture::cached_output_types[41]; +case INTRINSIC_XED_IFORM_PSLLD_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_PSLLD_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[41]; +case INTRINSIC_XED_IFORM_PSLLD_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[41]; +case INTRINSIC_XED_IFORM_PSLLD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSLLD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSRLQ_MMXq_IMMb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PSRLQ_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_PSRLQ_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PSRLQ_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PSRLQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSRLQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSLLQ_MMXq_IMMb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PSLLQ_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_PSLLQ_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PSLLQ_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PSLLQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_PSLLQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_PSRLDQ_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_PSLLDQ_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_FXSAVE_MEMmfpxenv: + return X86CommonArchitecture::cached_output_types[46]; +case INTRINSIC_XED_IFORM_FXRSTOR_MEMmfpxenv: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_FXSAVE64_MEMmfpxenv: + return X86CommonArchitecture::cached_output_types[46]; +case INTRINSIC_XED_IFORM_FXRSTOR64_MEMmfpxenv: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_LDMXCSR_MEMd: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_STMXCSR_MEMd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_PREFETCHNTA_MEMmprefetch: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_PREFETCHT0_MEMmprefetch: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_PREFETCHT1_MEMmprefetch: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_PREFETCHT2_MEMmprefetch: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r0: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r1: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r2: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r3: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_MEMv_0F18r4: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r4: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_MEMv_0F18r5: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r5: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_MEMv_0F18r6: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r6: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_MEMv_0F18r7: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_0F18r7: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F19: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F19: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1D: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1D: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1F: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1F: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_90: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F0D: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1A: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1B: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_MEMv_0F1A: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_MEM_0F1B: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1E: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1E: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_MEMv_GPRv_0F1C: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_NOP_GPRv_GPRv_0F1C: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_VMCALL: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VMLAUNCH: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VMRESUME: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VMXOFF: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_SGDT_MEMs64: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_SGDT_MEMs: + return X86CommonArchitecture::cached_output_types[47]; +case INTRINSIC_XED_IFORM_LIDT_MEMs64: + return X86CommonArchitecture::cached_output_types[32]; +case INTRINSIC_XED_IFORM_LIDT_MEMs: + return X86CommonArchitecture::cached_output_types[32]; +case INTRINSIC_XED_IFORM_MONITOR: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_MWAIT: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_SIDT_MEMs: + return X86CommonArchitecture::cached_output_types[47]; +case INTRINSIC_XED_IFORM_SIDT_MEMs64: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_INVLPG_MEMb: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_SWAPGS: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_RDTSCP: + return X86CommonArchitecture::cached_output_types[48]; +case INTRINSIC_XED_IFORM_SFENCE: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_CLFLUSH_MEMmprefetch: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_LFENCE: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_MFENCE: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_MOVHLPS_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[49]; +case INTRINSIC_XED_IFORM_MOVLPS_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[49]; +case INTRINSIC_XED_IFORM_MOVLPS_MEMq_XMMps: + return X86CommonArchitecture::cached_output_types[49]; +case INTRINSIC_XED_IFORM_MOVLHPS_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[49]; +case INTRINSIC_XED_IFORM_MOVHPS_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[49]; +case INTRINSIC_XED_IFORM_MOVHPS_MEMq_XMMps: + return X86CommonArchitecture::cached_output_types[49]; +case INTRINSIC_XED_IFORM_DAA: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_DAS: + return X86CommonArchitecture::cached_output_types[20]; +case INTRINSIC_XED_IFORM_AAA: + return X86CommonArchitecture::cached_output_types[50]; +case INTRINSIC_XED_IFORM_AAS: + return X86CommonArchitecture::cached_output_types[50]; +case INTRINSIC_XED_IFORM_PUSHA: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_PUSHAD: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_POPA: + return X86CommonArchitecture::cached_output_types[51]; +case INTRINSIC_XED_IFORM_POPAD: + return X86CommonArchitecture::cached_output_types[52]; +case INTRINSIC_XED_IFORM_BOUND_GPRv_MEMa16: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_BOUND_GPRv_MEMa32: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_ARPL_MEMw_GPR16: + return X86CommonArchitecture::cached_output_types[53]; +case INTRINSIC_XED_IFORM_ARPL_GPR16_GPR16: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_MOVSXD_GPRv_MEMz: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOVSXD_GPRv_GPRz: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_REP_INSB: + return X86CommonArchitecture::cached_output_types[54]; +case INTRINSIC_XED_IFORM_INSB: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_REP_INSW: + return X86CommonArchitecture::cached_output_types[14]; +case INTRINSIC_XED_IFORM_INSW: + return X86CommonArchitecture::cached_output_types[31]; +case INTRINSIC_XED_IFORM_REP_INSD: + return X86CommonArchitecture::cached_output_types[12]; +case INTRINSIC_XED_IFORM_INSD: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_REP_OUTSB: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_OUTSB: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_REP_OUTSW: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_OUTSW: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_REP_OUTSD: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_OUTSD: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_JO_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JO_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JO_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JNO_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JNO_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JNO_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JB_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JB_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JB_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JNB_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JNB_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JNB_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JZ_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JZ_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JZ_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JNZ_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JNZ_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JNZ_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JBE_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JBE_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JBE_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JNBE_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JNBE_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JNBE_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JS_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JS_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JS_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JNS_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JNS_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JNS_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JP_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JP_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JP_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JNP_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JNP_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JNP_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JL_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JL_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JL_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JNL_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JNL_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JNL_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JLE_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JLE_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JLE_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JNLE_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_JNLE_RELBRz: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JNLE_RELBRd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_XCHG_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[55]; +case INTRINSIC_XED_IFORM_XCHG_GPR8_GPR8: + return X86CommonArchitecture::cached_output_types[55]; +case INTRINSIC_XED_IFORM_XCHG_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_XCHG_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_XCHG_GPRv_OrAX: + return X86CommonArchitecture::cached_output_types[11]; +case INTRINSIC_XED_IFORM_LEA_GPRv_AGEN: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PAUSE: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_CBW: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_CDQE: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CWDE: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_CWD: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_CQO: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CDQ: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_CALL_FAR_MEMp2: + return X86CommonArchitecture::cached_output_types[27]; +case INTRINSIC_XED_IFORM_CALL_FAR_PTRp_IMMw: + return X86CommonArchitecture::cached_output_types[28]; +case INTRINSIC_XED_IFORM_FWAIT: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_PUSHF: + return X86CommonArchitecture::cached_output_types[56]; +case INTRINSIC_XED_IFORM_PUSHFD: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_PUSHFQ: + return X86CommonArchitecture::cached_output_types[57]; +case INTRINSIC_XED_IFORM_POPF: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_POPFD: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_POPFQ: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_SAHF: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_LAHF: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_REP_MOVSB: + return X86CommonArchitecture::cached_output_types[54]; +case INTRINSIC_XED_IFORM_MOVSB: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_REP_MOVSW: + return X86CommonArchitecture::cached_output_types[14]; +case INTRINSIC_XED_IFORM_MOVSW: + return X86CommonArchitecture::cached_output_types[31]; +case INTRINSIC_XED_IFORM_REP_MOVSD: + return X86CommonArchitecture::cached_output_types[12]; +case INTRINSIC_XED_IFORM_MOVSD: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_REP_MOVSQ: + return X86CommonArchitecture::cached_output_types[13]; +case INTRINSIC_XED_IFORM_MOVSQ: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_REPE_CMPSB: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_REPNE_CMPSB: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_CMPSB: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_REPE_CMPSW: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_REPNE_CMPSW: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_CMPSW: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_REPE_CMPSD: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_REPNE_CMPSD: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_CMPSD: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_REPE_CMPSQ: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_REPNE_CMPSQ: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_CMPSQ: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_REP_STOSB: + return X86CommonArchitecture::cached_output_types[54]; +case INTRINSIC_XED_IFORM_STOSB: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_REP_STOSW: + return X86CommonArchitecture::cached_output_types[14]; +case INTRINSIC_XED_IFORM_STOSW: + return X86CommonArchitecture::cached_output_types[31]; +case INTRINSIC_XED_IFORM_REP_STOSD: + return X86CommonArchitecture::cached_output_types[12]; +case INTRINSIC_XED_IFORM_STOSD: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_REP_STOSQ: + return X86CommonArchitecture::cached_output_types[13]; +case INTRINSIC_XED_IFORM_STOSQ: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_REP_LODSB: + return X86CommonArchitecture::cached_output_types[54]; +case INTRINSIC_XED_IFORM_LODSB: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_REP_LODSW: + return X86CommonArchitecture::cached_output_types[4]; +case INTRINSIC_XED_IFORM_LODSW: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_REP_LODSD: + return X86CommonArchitecture::cached_output_types[59]; +case INTRINSIC_XED_IFORM_LODSD: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_REP_LODSQ: + return X86CommonArchitecture::cached_output_types[11]; +case INTRINSIC_XED_IFORM_LODSQ: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_REPE_SCASB: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_REPNE_SCASB: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_SCASB: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_REPE_SCASW: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_REPNE_SCASW: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_SCASW: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_REPE_SCASD: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_REPNE_SCASD: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_SCASD: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_REPE_SCASQ: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_REPNE_SCASQ: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_SCASQ: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_RET_NEAR_IMMw: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_RET_NEAR: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_LES_GPRz_MEMp: + return X86CommonArchitecture::cached_output_types[11]; +case INTRINSIC_XED_IFORM_LDS_GPRz_MEMp: + return X86CommonArchitecture::cached_output_types[11]; +case INTRINSIC_XED_IFORM_ENTER_IMMw_IMMb: + return X86CommonArchitecture::cached_output_types[60]; +case INTRINSIC_XED_IFORM_LEAVE: + return X86CommonArchitecture::cached_output_types[4]; +case INTRINSIC_XED_IFORM_RET_FAR_IMMw: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_RET_FAR: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_INT3: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_INT_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_INTO: + return X86CommonArchitecture::cached_output_types[61]; +case INTRINSIC_XED_IFORM_IRET: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_IRETD: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_IRETQ: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_AAM_IMMb: + return X86CommonArchitecture::cached_output_types[50]; +case INTRINSIC_XED_IFORM_AAD_IMMb: + return X86CommonArchitecture::cached_output_types[50]; +case INTRINSIC_XED_IFORM_SALC: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_XLAT: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_LOOPNE_RELBRb: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_LOOPE_RELBRb: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_LOOP_RELBRb: + return X86CommonArchitecture::cached_output_types[16]; +case INTRINSIC_XED_IFORM_JCXZ_RELBRb: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_JECXZ_RELBRb: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_JRCXZ_RELBRb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_IN_AL_IMMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_IN_OeAX_IMMb: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_IN_AL_DX: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_IN_OeAX_DX: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_OUT_IMMb_AL: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_OUT_IMMb_OeAX: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_OUT_DX_AL: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_OUT_DX_OeAX: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_INT1: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_HLT: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_CMC: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CLC: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_STC: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CLI: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_STI: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CLD: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_STD: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_LAR_GPRv_MEMw: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_LAR_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_LSL_GPRv_MEMw: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_LSL_GPRv_GPRz: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SYSCALL: + return X86CommonArchitecture::cached_output_types[62]; +case INTRINSIC_XED_IFORM_CLTS: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_SYSRET: + return X86CommonArchitecture::cached_output_types[61]; +case INTRINSIC_XED_IFORM_SYSRET64: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_MOVUPS_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVUPS_XMMps_XMMps_0F10: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVUPS_MEMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVUPS_XMMps_XMMps_0F11: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_UNPCKLPS_XMMps_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_UNPCKLPS_XMMps_XMMq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_UNPCKHPS_XMMps_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_UNPCKHPS_XMMps_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVSS_XMMdq_MEMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVSS_XMMss_XMMss_0F10: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVSS_MEMss_XMMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVSS_XMMss_XMMss_0F11: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVSLDUP_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVSLDUP_XMMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVSHDUP_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVSHDUP_XMMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVUPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVUPD_MEMpd_XMMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVLPD_XMMsd_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVLPD_MEMq_XMMsd: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_UNPCKLPD_XMMpd_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_UNPCKLPD_XMMpd_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_UNPCKHPD_XMMpd_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_UNPCKHPD_XMMpd_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVHPD_XMMsd_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVHPD_MEMq_XMMsd: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MOVSD_XMM_XMMdq_MEMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVSD_XMM_MEMsd_XMMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVDDUP_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVDDUP_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOV_CR_CR_GPR32: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_MOV_CR_CR_GPR64: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_MOV_CR_GPR32_CR: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_MOV_CR_GPR64_CR: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOV_DR_DR_GPR32: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_MOV_DR_DR_GPR64: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_MOV_DR_GPR32_DR: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_MOV_DR_GPR64_DR: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_WRMSR: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_RDTSC: + return X86CommonArchitecture::cached_output_types[65]; +case INTRINSIC_XED_IFORM_RDMSR: + return X86CommonArchitecture::cached_output_types[65]; +case INTRINSIC_XED_IFORM_RDPMC: + return X86CommonArchitecture::cached_output_types[65]; +case INTRINSIC_XED_IFORM_SYSENTER: + return X86CommonArchitecture::cached_output_types[66]; +case INTRINSIC_XED_IFORM_SYSEXIT: + return X86CommonArchitecture::cached_output_types[65]; +case INTRINSIC_XED_IFORM_CMOVO_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVO_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNO_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNO_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVB_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVB_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNB_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNB_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVZ_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVZ_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNZ_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNZ_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVBE_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVBE_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNBE_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNBE_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOVMSKPS_GPR32_XMMps: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_SQRTPS_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_SQRTPS_XMMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_RSQRTPS_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_RSQRTPS_XMMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_RCPPS_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_RCPPS_XMMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_ANDPS_XMMxud_MEMxud: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_ANDPS_XMMxud_XMMxud: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_ANDNPS_XMMxud_MEMxud: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_ANDNPS_XMMxud_XMMxud: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_ORPS_XMMxud_MEMxud: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_ORPS_XMMxud_XMMxud: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_XORPS_XMMxud_MEMxud: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_XORPS_XMMxud_XMMxud: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_SQRTSS_XMMss_MEMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_SQRTSS_XMMss_XMMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_RSQRTSS_XMMss_MEMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_RSQRTSS_XMMss_XMMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_RCPSS_XMMss_MEMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_RCPSS_XMMss_XMMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVMSKPD_GPR32_XMMpd: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_SQRTPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_SQRTPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_ANDPD_XMMxuq_MEMxuq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_ANDPD_XMMxuq_XMMxuq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_ANDNPD_XMMxuq_MEMxuq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_ANDNPD_XMMxuq_XMMxuq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_ORPD_XMMxuq_MEMxuq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_ORPD_XMMxuq_XMMxuq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_XORPD_XMMxuq_MEMxuq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_XORPD_XMMxuq_XMMxuq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_SQRTSD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_SQRTSD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_PUNPCKLBW_MMXq_MEMd: + return X86CommonArchitecture::cached_output_types[67]; +case INTRINSIC_XED_IFORM_PUNPCKLBW_MMXq_MMXd: + return X86CommonArchitecture::cached_output_types[67]; +case INTRINSIC_XED_IFORM_PUNPCKLBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PUNPCKLBW_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PUNPCKLWD_MMXq_MEMd: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_PUNPCKLWD_MMXq_MMXd: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_PUNPCKLWD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PUNPCKLWD_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PUNPCKLDQ_MMXq_MEMd: + return X86CommonArchitecture::cached_output_types[41]; +case INTRINSIC_XED_IFORM_PUNPCKLDQ_MMXq_MMXd: + return X86CommonArchitecture::cached_output_types[41]; +case INTRINSIC_XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PUNPCKLDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PACKSSWB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PACKSSWB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PACKSSWB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PACKSSWB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PCMPGTB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[68]; +case INTRINSIC_XED_IFORM_PCMPGTB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[68]; +case INTRINSIC_XED_IFORM_PCMPGTB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_PCMPGTB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_PCMPGTW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PCMPGTW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PCMPGTW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PCMPGTW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PCMPGTD_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_PCMPGTD_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_PCMPGTD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PCMPGTD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PACKUSWB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PACKUSWB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PACKUSWB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PACKUSWB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PSHUFW_MMXq_MEMq_IMMb: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_PSHUFW_MMXq_MMXq_IMMb: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_PCMPEQB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[68]; +case INTRINSIC_XED_IFORM_PCMPEQB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[68]; +case INTRINSIC_XED_IFORM_PCMPEQB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_PCMPEQB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_PCMPEQW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PCMPEQW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PCMPEQW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PCMPEQW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PCMPEQD_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_PCMPEQD_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_PCMPEQD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PCMPEQD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_EMMS: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_SETO_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETO_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNO_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNO_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETB_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETB_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNB_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNB_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETZ_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETZ_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNZ_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNZ_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETBE_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETBE_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNBE_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNBE_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_CPUID: + return X86CommonArchitecture::cached_output_types[70]; +case INTRINSIC_XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[50]; +case INTRINSIC_XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[71]; +case INTRINSIC_XED_IFORM_CMPXCHG_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[50]; +case INTRINSIC_XED_IFORM_CMPXCHG_GPR8_GPR8: + return X86CommonArchitecture::cached_output_types[50]; +case INTRINSIC_XED_IFORM_CMPXCHG_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[71]; +case INTRINSIC_XED_IFORM_CMPXCHG_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[72]; +case INTRINSIC_XED_IFORM_LSS_GPRv_MEMp2: + return X86CommonArchitecture::cached_output_types[11]; +case INTRINSIC_XED_IFORM_LFS_GPRv_MEMp2: + return X86CommonArchitecture::cached_output_types[11]; +case INTRINSIC_XED_IFORM_LGS_GPRv_MEMp2: + return X86CommonArchitecture::cached_output_types[11]; +case INTRINSIC_XED_IFORM_MOVZX_GPRv_MEMb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOVZX_GPRv_GPR8: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOVZX_GPRv_MEMw: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOVZX_GPRv_GPR16: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_XADD_LOCK_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[50]; +case INTRINSIC_XED_IFORM_XADD_LOCK_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[73]; +case INTRINSIC_XED_IFORM_XADD_MEMb_GPR8: + return X86CommonArchitecture::cached_output_types[50]; +case INTRINSIC_XED_IFORM_XADD_GPR8_GPR8: + return X86CommonArchitecture::cached_output_types[50]; +case INTRINSIC_XED_IFORM_XADD_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[73]; +case INTRINSIC_XED_IFORM_XADD_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[74]; +case INTRINSIC_XED_IFORM_CMPPS_XMMps_MEMps_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_CMPPS_XMMps_XMMps_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVNTI_MEMd_GPR32: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_MOVNTI_MEMq_GPR64: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PINSRW_MMXq_MEMw_IMMb: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_PINSRW_MMXq_GPR32_IMMb: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_PINSRW_XMMdq_MEMw_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PINSRW_XMMdq_GPR32_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PEXTRW_GPR32_MMXq_IMMb: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_SHUFPS_XMMps_MEMps_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_SHUFPS_XMMps_XMMps_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_CMPSS_XMMss_MEMss_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_CMPSS_XMMss_XMMss_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_PADDQ_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PADDQ_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PADDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PADDQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMULLW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PMULLW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PMULLW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMULLW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMOVMSKB_GPR32_MMXq: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_PMOVMSKB_GPR32_XMMdq: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_ADDSUBPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_ADDSUBPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVQ2DQ_XMMdq_MMXq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_ADDSUBPS_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_ADDSUBPS_XMMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVDQ2Q_MMXq_XMMq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PAVGB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PAVGB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[68]; +case INTRINSIC_XED_IFORM_PAVGB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_PAVGB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_PAVGW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PAVGW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PAVGW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_PAVGW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_PMULHUW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_PMULHUW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_PMULHUW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_PMULHUW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_PMULHW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PMULHW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PMULHW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PMULHW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_MOVNTQ_MEMq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVNTDQ_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_CVTDQ2PD_XMMpd_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CVTDQ2PD_XMMpd_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CVTPD2DQ_XMMdq_MEMpd: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_CVTPD2DQ_XMMdq_XMMpd: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMULUDQ_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[41]; +case INTRINSIC_XED_IFORM_PMULUDQ_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[41]; +case INTRINSIC_XED_IFORM_PMULUDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMULUDQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMADDWD_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PMADDWD_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_PMADDWD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PMADDWD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PSADBW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSADBW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSADBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSADBW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MASKMOVQ_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MASKMOVDQU_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_LDDQU_XMMpd_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_INVD: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_UD0_GPR32_MEMd: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_UD0_GPR32_GPR32: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_UD1_GPR32_MEMd: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_UD1_GPR32_GPR32: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_UD2: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_MOVAPS_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVAPS_XMMps_XMMps_0F28: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVAPS_MEMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVAPS_XMMps_XMMps_0F29: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_CVTPI2PS_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[49]; +case INTRINSIC_XED_IFORM_CVTPI2PS_XMMq_MMXq: + return X86CommonArchitecture::cached_output_types[49]; +case INTRINSIC_XED_IFORM_MOVNTPS_MEMdq_XMMps: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_CVTTPS2PI_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_CVTTPS2PI_MMXq_XMMq: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_CVTPS2PI_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_CVTPS2PI_MMXq_XMMq: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_UCOMISS_XMMss_MEMss: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_UCOMISS_XMMss_XMMss: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_COMISS_XMMss_MEMss: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_COMISS_XMMss_XMMss: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_GPR32d: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_MEMq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_CVTSI2SS_XMMss_GPR64q: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_CVTTSS2SI_GPR32d_MEMss: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_CVTTSS2SI_GPR32d_XMMss: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_CVTTSS2SI_GPR64q_MEMss: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_CVTTSS2SI_GPR64q_XMMss: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_CVTSS2SI_GPR32d_MEMss: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_CVTSS2SI_GPR32d_XMMss: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_CVTSS2SI_GPR64q_MEMss: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_CVTSS2SI_GPR64q_XMMss: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MOVAPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVAPD_MEMpd_XMMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CVTPI2PD_XMMpd_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CVTPI2PD_XMMpd_MMXq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVNTPD_MEMdq_XMMpd: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_CVTTPD2PI_MMXq_MEMpd: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_CVTTPD2PI_MMXq_XMMpd: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_CVTPD2PI_MMXq_MEMpd: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_CVTPD2PI_MMXq_XMMpd: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_UCOMISD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_UCOMISD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_COMISD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_COMISD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_MEMd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_GPR32d: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CVTSI2SD_XMMsd_GPR64q: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CVTTSD2SI_GPR32d_MEMsd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_CVTTSD2SI_GPR32d_XMMsd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_CVTTSD2SI_GPR64q_MEMsd: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_CVTTSD2SI_GPR64q_XMMsd: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_CVTSD2SI_GPR32d_MEMsd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_CVTSD2SI_GPR32d_XMMsd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_CVTSD2SI_GPR64q_MEMsd: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_CVTSD2SI_GPR64q_XMMsd: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_CMOVS_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVS_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNS_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNS_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVP_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVP_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNP_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNP_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVL_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVL_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNL_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNL_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVLE_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVLE_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNLE_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CMOVNLE_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_ADDPS_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_ADDPS_XMMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MULPS_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MULPS_XMMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_CVTPS2PD_XMMpd_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CVTPS2PD_XMMpd_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CVTDQ2PS_XMMps_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_CVTDQ2PS_XMMps_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_SUBPS_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_SUBPS_XMMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MINPS_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MINPS_XMMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_DIVPS_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_DIVPS_XMMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MAXPS_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MAXPS_XMMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_ADDSS_XMMss_MEMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_ADDSS_XMMss_XMMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MULSS_XMMss_MEMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MULSS_XMMss_XMMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_CVTSS2SD_XMMsd_MEMss: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CVTSS2SD_XMMsd_XMMss: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CVTTPS2DQ_XMMdq_MEMps: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_CVTTPS2DQ_XMMdq_XMMps: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_SUBSS_XMMss_MEMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_SUBSS_XMMss_XMMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MINSS_XMMss_MEMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MINSS_XMMss_XMMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_DIVSS_XMMss_MEMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_DIVSS_XMMss_XMMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MAXSS_XMMss_MEMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MAXSS_XMMss_XMMss: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_ADDPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_ADDPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MULPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MULPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CVTPD2PS_XMMps_MEMpd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_CVTPD2PS_XMMps_XMMpd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_CVTPS2DQ_XMMdq_MEMps: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_CVTPS2DQ_XMMdq_XMMps: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_SUBPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_SUBPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MINPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MINPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_DIVPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_DIVPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MAXPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MAXPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_ADDSD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_ADDSD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MULSD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MULSD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_CVTSD2SS_XMMss_MEMsd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_CVTSD2SS_XMMss_XMMsd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_SUBSD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_SUBSD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MINSD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MINSD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_DIVSD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_DIVSD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MAXSD_XMMsd_MEMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MAXSD_XMMsd_XMMsd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_PUNPCKHBW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PUNPCKHBW_MMXq_MMXd: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PUNPCKHBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PUNPCKHBW_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PUNPCKHWD_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PUNPCKHWD_MMXq_MMXd: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PUNPCKHWD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PUNPCKHWD_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PUNPCKHDQ_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PUNPCKHDQ_MMXq_MMXd: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PUNPCKHDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PACKSSDW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_PACKSSDW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_PACKSSDW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PACKSSDW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVD_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVD_XMMdq_GPR32: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVD_MEMd_XMMd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_MOVD_GPR32_XMMd: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_MOVD_MMXq_MEMd: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MOVD_MMXq_GPR32: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MOVD_MEMd_MMXd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_MOVD_GPR32_MMXd: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_MOVQ_XMMdq_MEMq_0F6E: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVQ_XMMdq_GPR64: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVQ_MEMq_XMMq_0F7E: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MOVQ_GPR64_XMMq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOVQ_MEMq_XMMq_0FD6: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MOVQ_XMMdq_XMMq_0FD6: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVQ_XMMdq_MEMq_0F7E: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVQ_XMMdq_XMMq_0F7E: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVQ_MMXq_MEMq_0F6E: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MOVQ_MMXq_GPR64: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MOVQ_MEMq_MMXq_0F7E: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MOVQ_GPR64_MMXq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOVQ_MMXq_MEMq_0F6F: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MOVQ_MMXq_MMXq_0F6F: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MOVQ_MEMq_MMXq_0F7F: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MOVQ_MMXq_MMXq_0F7F: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVDQU_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVDQU_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMREAD_MEMq_GPR64: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_VMREAD_GPR64_GPR64: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_VMREAD_MEMd_GPR32: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_VMREAD_GPR32_GPR32: + return X86CommonArchitecture::cached_output_types[61]; +case INTRINSIC_XED_IFORM_VMWRITE_GPR64_MEMq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VMWRITE_GPR64_GPR64: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VMWRITE_GPR32_MEMd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VMWRITE_GPR32_GPR32: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_HADDPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_HADDPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_HSUBPD_XMMpd_MEMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_HSUBPD_XMMpd_XMMpd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_MOVDQA_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVDQA_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_HADDPS_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_HADDPS_XMMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_HSUBPS_XMMps_MEMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_HSUBPS_XMMps_XMMps: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_SETS_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETS_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNS_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNS_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETP_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETP_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNP_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNP_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETL_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETL_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNL_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNL_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETLE_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETLE_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNLE_MEMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_SETNLE_GPR8: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_RSM: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SHRD_MEMv_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SHRD_MEMv_GPRv_CL: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SHRD_GPRv_GPRv_CL: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SHLD_MEMv_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SHLD_MEMv_GPRv_CL: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_SHLD_GPRv_GPRv_CL: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_MOVSX_GPRv_MEMb: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOVSX_GPRv_GPR8: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOVSX_GPRv_MEMw: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOVSX_GPRv_GPR16: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_BSWAP_GPRv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PSUBUSB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBUSB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBUSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSUBUSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSUBUSW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBUSW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBUSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSUBUSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMINUB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PMINUB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PMINUB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMINUB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PAND_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PAND_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PAND_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PAND_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PADDUSB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PADDUSB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PADDUSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PADDUSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PADDUSW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PADDUSW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PADDUSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PADDUSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMAXUB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PMAXUB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PMAXUB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMAXUB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PANDN_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PANDN_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PANDN_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PANDN_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSUBSB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBSB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSUBSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSUBSW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBSW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSUBSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMINSW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PMINSW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PMINSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMINSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_POR_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_POR_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_POR_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_POR_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PADDSB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PADDSB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PADDSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PADDSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PADDSW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PADDSW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PADDSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PADDSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMAXSW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PMAXSW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PMAXSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMAXSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PXOR_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PXOR_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PXOR_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PXOR_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSUBB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSUBB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSUBW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSUBW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSUBD_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBD_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSUBD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSUBQ_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBQ_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSUBQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSUBQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PADDB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PADDB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PADDB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PADDB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PADDW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PADDW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PADDW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PADDW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PADDD_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PADDD_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PADDD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PADDD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PHADDW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PHADDW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PHADDW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PHADDW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PHADDD_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PHADDD_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PHADDD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PHADDD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PHADDSW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PHADDSW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PHADDSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PHADDSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PHSUBW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PHSUBW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PHSUBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PHSUBW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PHSUBD_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PHSUBD_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PHSUBD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PHSUBD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PHSUBSW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PHSUBSW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PHSUBSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PHSUBSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMADDUBSW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[68]; +case INTRINSIC_XED_IFORM_PMADDUBSW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[68]; +case INTRINSIC_XED_IFORM_PMADDUBSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_PMADDUBSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_PMULHRSW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PMULHRSW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PMULHRSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMULHRSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSHUFB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSHUFB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSHUFB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSHUFB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSIGNB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSIGNB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSIGNB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSIGNB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSIGNW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSIGNW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSIGNW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSIGNW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSIGND_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSIGND_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSIGND_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PSIGND_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PALIGNR_MMXq_MEMq_IMMb: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PALIGNR_MMXq_MMXq_IMMb: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PABSB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PABSB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PABSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PABSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PABSW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PABSW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PABSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PABSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PABSD_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PABSD_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PABSD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PABSD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_POPCNT_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_POPCNT_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_PCMPGTQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PCMPGTQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_CRC32_GPRyy_MEMb: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_CRC32_GPRyy_GPR8b: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_CRC32_GPRyy_MEMv: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_CRC32_GPRyy_GPRv: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_BLENDVPD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_BLENDVPD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_BLENDVPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_BLENDVPS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_PCMPEQQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PCMPEQQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_DPPD_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_DPPD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_DPPS_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_DPPS_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MOVNTDQA_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_INSERTPS_XMMps_MEMd_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_INSERTPS_XMMps_XMMps_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_PACKUSDW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PACKUSDW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PBLENDVB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PBLENDVB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[31]; +case INTRINSIC_XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_PINSRB_XMMdq_MEMb_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PINSRD_XMMdq_MEMd_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_PTEST_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PTEST_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PHMINPOSUW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PHMINPOSUW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMAXSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMAXSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMAXSD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMAXSD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMAXUD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMAXUD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMAXUW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMAXUW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMINSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMINSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMINSD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMINSD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMINUD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMINUD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMINUW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMINUW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMULLD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMULLD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMULDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMULDQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMOVSXBW_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PMOVSXBW_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_PMOVSXBD_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMOVSXBD_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMOVSXBQ_XMMdq_MEMw: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_PMOVSXBQ_XMMdq_XMMw: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_PMOVSXWD_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMOVSXWD_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PMOVSXWQ_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_PMOVSXWQ_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_PMOVSXDQ_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_PMOVSXDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_PMOVZXBW_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_PMOVZXBW_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_PMOVZXBD_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_PMOVZXBD_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_PMOVZXBQ_XMMdq_MEMw: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_PMOVZXBQ_XMMdq_XMMw: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_PMOVZXWD_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_PMOVZXWD_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_PMOVZXWQ_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_PMOVZXWQ_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_PMOVZXDQ_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_PMOVZXDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[61]; +case INTRINSIC_XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[61]; +case INTRINSIC_XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[61]; +case INTRINSIC_XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[61]; +case INTRINSIC_XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[77]; +case INTRINSIC_XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[77]; +case INTRINSIC_XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[77]; +case INTRINSIC_XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[77]; +case INTRINSIC_XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[77]; +case INTRINSIC_XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[77]; +case INTRINSIC_XED_IFORM_XGETBV: + return X86CommonArchitecture::cached_output_types[65]; +case INTRINSIC_XED_IFORM_XSETBV: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOVBE_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_MOVBE_MEMv_GPRv: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_GETSEC: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_AESENC_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_AESENC_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_AESENCLAST_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_AESENCLAST_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_AESDEC_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_AESDEC_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_AESDECLAST_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_AESDECLAST_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_AESIMC_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_AESIMC_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_INVEPT_GPR64_MEMdq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_INVEPT_GPR32_MEMdq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_INVVPID_GPR64_MEMdq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_INVVPID_GPR32_MEMdq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_PREFETCHW_0F0Dr1: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_PREFETCHW_0F0Dr3: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr4: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr5: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr6: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_PREFETCH_RESERVED_0F0Dr7: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_XSTORE: + return X86CommonArchitecture::cached_output_types[78]; +case INTRINSIC_XED_IFORM_REP_XSTORE: + return X86CommonArchitecture::cached_output_types[79]; +case INTRINSIC_XED_IFORM_REP_XCRYPTECB: + return X86CommonArchitecture::cached_output_types[54]; +case INTRINSIC_XED_IFORM_REP_XCRYPTCBC: + return X86CommonArchitecture::cached_output_types[54]; +case INTRINSIC_XED_IFORM_REP_XCRYPTCTR: + return X86CommonArchitecture::cached_output_types[54]; +case INTRINSIC_XED_IFORM_REP_XCRYPTCFB: + return X86CommonArchitecture::cached_output_types[54]; +case INTRINSIC_XED_IFORM_REP_XCRYPTOFB: + return X86CommonArchitecture::cached_output_types[54]; +case INTRINSIC_XED_IFORM_REP_XSHA1: + return X86CommonArchitecture::cached_output_types[80]; +case INTRINSIC_XED_IFORM_REP_XSHA256: + return X86CommonArchitecture::cached_output_types[80]; +case INTRINSIC_XED_IFORM_REP_MONTMUL: + return X86CommonArchitecture::cached_output_types[81]; +case INTRINSIC_XED_IFORM_FEMMS: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_PI2FW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PI2FW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PI2FD_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PI2FD_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PF2IW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PF2IW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PF2ID_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PF2ID_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFNACC_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFNACC_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFPNACC_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFPNACC_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFCMPGE_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFCMPGE_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFMIN_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFMIN_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFRCP_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFRCP_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFRSQRT_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFRSQRT_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFSUB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFSUB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFADD_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFADD_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFCMPGT_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFCMPGT_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFMAX_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFMAX_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFRCPIT1_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFRCPIT1_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFRSQIT1_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFRSQIT1_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFSUBR_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFSUBR_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFACC_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFACC_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFCMPEQ_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFCMPEQ_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFMUL_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFMUL_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFRCPIT2_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PFRCPIT2_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PMULHRW_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PMULHRW_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSWAPD_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PSWAPD_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PAVGUSB_MMXq_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PAVGUSB_MMXq_MMXq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_SYSCALL_AMD: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SYSRET_AMD: + return X86CommonArchitecture::cached_output_types[61]; +case INTRINSIC_XED_IFORM_VMRUN_ArAX: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_VMMCALL: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_VMLOAD_ArAX: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_VMSAVE: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_STGI: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_CLGI: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_SKINIT_EAX: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_INVLPGA_ArAX_ECX: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_EXTRQ_XMMq_IMMb_IMMb: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_EXTRQ_XMMq_XMMdq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_INSERTQ_XMMq_XMMdq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MOVNTSD_MEMq_XMMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MOVNTSS_MEMd_XMMd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_CLZERO: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_MONITORX: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_MWAITX: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_MCOMMIT: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_RDPRU: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_PSMASH_RAX: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_PVALIDATE_RAX_ECX_EDX: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_RMPADJUST_RAX_RCX_RDX: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_RMPUPDATE_RAX_RCX: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_BNDMK_BND_AGEN: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_BNDCL_BND_AGEN: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_BNDCL_BND_GPR64: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_BNDCL_BND_GPR32: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_BNDCU_BND_AGEN: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_BNDCU_BND_GPR64: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_BNDCU_BND_GPR32: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_BNDCN_BND_AGEN: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_BNDCN_BND_GPR64: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_BNDCN_BND_GPR32: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_BNDMOV_BND_BND: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_BNDMOV_BND_MEMq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_BNDMOV_BND_MEMdq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_BNDMOV_MEMq_BND: + return X86CommonArchitecture::cached_output_types[41]; +case INTRINSIC_XED_IFORM_BNDMOV_MEMdq_BND: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_BNDLDX_BND_MEMbnd32: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_BNDLDX_BND_MEMbnd64: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_BNDSTX_MEMbnd32_BND: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_BNDSTX_MEMbnd64_BND: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CLRSSBSY_MEMu64: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_ENDBR32: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_ENDBR64: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_INCSSPD_GPR32u8: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_INCSSPQ_GPR64u8: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_RDSSPD_GPR32u32: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_RDSSPQ_GPR64u64: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_RSTORSSP_MEMu64: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SAVEPREVSSP: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_SETSSBSY: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_WRSSD_MEMu32_GPR32u32: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_WRSSQ_MEMu64_GPR64u64: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_WRUSSD_MEMu32_GPR32u32: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_WRUSSQ_MEMu64_GPR64u64: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_RDRAND_GPRv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_CLFLUSHOPT_MEMmprefetch: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_RDSEED_GPRv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_RDFSBASE_GPRy: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_RDGSBASE_GPRy: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_WRFSBASE_GPRy: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_WRGSBASE_GPRy: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_CLAC: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_STAC: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_ENCLU: + return X86CommonArchitecture::cached_output_types[74]; +case INTRINSIC_XED_IFORM_ENCLS: + return X86CommonArchitecture::cached_output_types[74]; +case INTRINSIC_XED_IFORM_RDPID_GPR32u32: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_RDPID_GPR64u64: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_PTWRITE_GPRy: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_PTWRITE_MEMy: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_MOVDIR64B_GPRa_MEM: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_MOVDIRI_MEMu32_GPR32u32: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_MOVDIRI_MEMu64_GPR64u64: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_TPAUSE_GPR32u32: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_TPAUSE_GPR64u64: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_UMONITOR_GPRa: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_UMWAIT_GPR32: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_UMWAIT_GPR64: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_CLDEMOTE_MEMu8: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_ENCLV: + return X86CommonArchitecture::cached_output_types[74]; +case INTRINSIC_XED_IFORM_TZCNT_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_TZCNT_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_BSF_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_BSF_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_VMFUNC: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_INVPCID_GPR64_MEMdq: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_INVPCID_GPR32_MEMdq: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_LZCNT_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_LZCNT_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BSR_GPRv_MEMv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_BSR_GPRv_GPRv: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_XBEGIN_RELBRz: + return X86CommonArchitecture::cached_output_types[83]; +case INTRINSIC_XED_IFORM_XEND: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_XABORT_IMMb: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_XTEST: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_ADCX_GPR32d_GPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADCX_GPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADCX_GPR64q_GPR64q: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_ADCX_GPR64q_MEMq: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_ADOX_GPR32d_GPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADOX_GPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ADOX_GPR64q_GPR64q: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_ADOX_GPR64q_MEMq: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_RDPKRU: + return X86CommonArchitecture::cached_output_types[65]; +case INTRINSIC_XED_IFORM_WRPKRU: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_CLWB_MEMmprefetch: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_PREFETCHWT1_MEMu8: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_WBINVD: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_WBNOINVD: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_PCONFIG: + return X86CommonArchitecture::cached_output_types[84]; +case INTRINSIC_XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_GF2P8MULB_XMMu8_XMMu8: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_GF2P8MULB_XMMu8_MEMu8: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_ENQCMD_GPRa_MEMu32: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_ENQCMDS_GPRa_MEMu32: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_XRESLDTRK: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_XSUSLDTRK: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_SERIALIZE: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[85]; +case INTRINSIC_XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[85]; +case INTRINSIC_XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[85]; +case INTRINSIC_XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[86]; +case INTRINSIC_XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[86]; +case INTRINSIC_XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[86]; +case INTRINSIC_XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VFRCZPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFRCZPS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFRCZPS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFRCZPS_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFRCZPD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFRCZPD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFRCZPD_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFRCZPD_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFRCZSS_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFRCZSS_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFRCZSD_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFRCZSD_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPHADDBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPHADDBW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPHADDBD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPHADDBD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPHADDBQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPHADDBQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPHADDWD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPHADDWD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPHADDWQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPHADDWQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPHADDUBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPHADDUBW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPHADDUBD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPHADDUBD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPHADDUBQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPHADDUBQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPHADDUWD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPHADDUWD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPHADDUWQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPHADDUWQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPHSUBBW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPHSUBBW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPHSUBWD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPHSUBWD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPHSUBDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPHSUBDQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPHADDDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPHADDDQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPHADDUDQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPHADDUDQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_BEXTR_XOP_GPR32d_MEMd_IMMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BEXTR_XOP_GPRyy_MEMy_IMMd: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_BEXTR_XOP_GPR32d_GPR32d_IMMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BEXTR_XOP_GPRyy_GPRyy_IMMd: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_BLCFILL_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLCFILL_VGPRyy_MEMy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_BLCFILL_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLCFILL_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_BLSFILL_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLSFILL_VGPRyy_MEMy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_BLSFILL_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLSFILL_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_BLCS_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLCS_VGPRyy_MEMy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_BLCS_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLCS_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_TZMSK_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_TZMSK_VGPRyy_MEMy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_TZMSK_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_TZMSK_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_BLCIC_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLCIC_VGPRyy_MEMy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_BLCIC_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLCIC_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_BLSIC_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLSIC_VGPRyy_MEMy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_BLSIC_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLSIC_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_T1MSKC_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_T1MSKC_VGPRyy_MEMy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_T1MSKC_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_T1MSKC_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_BLCMSK_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLCMSK_VGPRyy_MEMy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_BLCMSK_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLCMSK_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_BLCI_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLCI_VGPRyy_MEMy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_BLCI_VGPR32d_GPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLCI_VGPRyy_GPRyy: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_LLWPCB_GPRyy: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_SLWPCB_GPRyy: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_LWPINS_VGPRyy_GPR32y_IMMd: + return X86CommonArchitecture::cached_output_types[89]; +case INTRINSIC_XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_LWPVAL_VGPRyy_GPR32y_IMMd: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCOMISD_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCOMISD_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCOMISS_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCOMISS_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_MEMqq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMdq_YMMqq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_YMMqq_XMMdq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32d_MEMq: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32d_XMMq: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64q_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64q_XMMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32d_MEMq: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32d_XMMq: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64q_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64q_XMMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32d_XMMd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64q_MEMd: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64q_XMMd: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32d_XMMd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64q_MEMd: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64q_XMMd: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[92]; +case INTRINSIC_XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VZEROALL: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_VZEROUPPER: + return X86CommonArchitecture::cached_output_types[9]; +case INTRINSIC_XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_YMMqq_MEMd: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_YMMqq_XMMdq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VBROADCASTSD_YMMqq_MEMq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VBROADCASTSD_YMMqq_XMMdq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VBROADCASTF128_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VLDDQU_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VLDDQU_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPTEST_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VPTEST_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VPTEST_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VPTEST_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VTESTPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VTESTPS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VTESTPS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VTESTPS_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VTESTPD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VTESTPD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VTESTPD_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VTESTPD_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVAPD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVAPD_XMMdq_XMMdq_28: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVAPD_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVAPD_XMMdq_XMMdq_29: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_YMMqq_28: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVAPD_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVAPD_YMMqq_YMMqq_29: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVAPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVAPS_XMMdq_XMMdq_28: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVAPS_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVAPS_XMMdq_XMMdq_29: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_YMMqq_28: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVAPS_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVAPS_YMMqq_YMMqq_29: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVD_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVD_XMMdq_GPR32d: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVD_MEMd_XMMd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VMOVD_GPR32d_XMMd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMdq_MEMq_6E: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMdq_GPR64q: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVQ_MEMq_XMMq_7E: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VMOVQ_GPR64q_XMMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMdq_MEMq_7E: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMdq_XMMq_7E: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVQ_MEMq_XMMq_D6: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMdq_XMMq_D6: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVDDUP_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVDDUP_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVDDUP_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVDDUP_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVDQA_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVDQA_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VMOVDQA_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VMOVDQU_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VMOVDQU_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVDQU_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[93]; +case INTRINSIC_XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[93]; +case INTRINSIC_XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[93]; +case INTRINSIC_XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[93]; +case INTRINSIC_XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[93]; +case INTRINSIC_XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[93]; +case INTRINSIC_XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[93]; +case INTRINSIC_XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[93]; +case INTRINSIC_XED_IFORM_VPABSB_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPABSB_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPABSB_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPABSB_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPABSW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPABSW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPABSW_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPABSW_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPABSD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPABSD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPABSD_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPABSD_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VRCPPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRCPPS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRCPPS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VRCPPS_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRSQRTPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRSQRTPS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRSQRTPS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VRSQRTPS_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSQRTPD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSQRTPD_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSQRTPD_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSQRTPD_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSQRTPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSQRTPS_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSQRTPS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSQRTPS_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VUCOMISD_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VUCOMISD_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VUCOMISS_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VUCOMISS_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VMOVSS_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVSS_MEMd_XMMd: + return X86CommonArchitecture::cached_output_types[92]; +case INTRINSIC_XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVSD_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVSD_MEMq_XMMq: + return X86CommonArchitecture::cached_output_types[101]; +case INTRINSIC_XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVUPD_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVUPD_XMMdq_XMMdq_10: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVUPD_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVUPD_XMMdq_XMMdq_11: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_YMMqq_10: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVUPD_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVUPD_YMMqq_YMMqq_11: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVUPS_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVUPS_XMMdq_XMMdq_10: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVUPS_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVUPS_XMMdq_XMMdq_11: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_YMMqq_10: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVUPS_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVUPS_YMMqq_YMMqq_11: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVLPD_MEMq_XMMq: + return X86CommonArchitecture::cached_output_types[101]; +case INTRINSIC_XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVLPS_MEMq_XMMq: + return X86CommonArchitecture::cached_output_types[49]; +case INTRINSIC_XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVHPD_MEMq_XMMdq: + return X86CommonArchitecture::cached_output_types[101]; +case INTRINSIC_XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVHPS_MEMq_XMMdq: + return X86CommonArchitecture::cached_output_types[49]; +case INTRINSIC_XED_IFORM_VMOVMSKPD_GPR32d_XMMdq: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VMOVMSKPD_GPR32d_YMMqq: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VMOVMSKPS_GPR32d_XMMdq: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VMOVMSKPS_GPR32d_YMMqq: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VPMOVMSKB_GPR32d_XMMdq: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VPMOVMSKB_GPR32d_YMMqq: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_YMMqq_XMMdq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_YMMqq_XMMq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_YMMqq_MEMq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMdq_XMMw: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMdq_MEMw: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMqq_XMMd: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMqq_MEMd: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_YMMqq_XMMdq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMqq_XMMq: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMqq_MEMq: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_YMMqq_XMMdq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_YMMqq_XMMq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_YMMqq_MEMq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMdq_XMMw: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMdq_MEMw: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMqq_XMMd: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMqq_MEMd: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_YMMqq_XMMdq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMqq_XMMq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMqq_MEMq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[31]; +case INTRINSIC_XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[61]; +case INTRINSIC_XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[61]; +case INTRINSIC_XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[61]; +case INTRINSIC_XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[61]; +case INTRINSIC_XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[22]; +case INTRINSIC_XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[77]; +case INTRINSIC_XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[77]; +case INTRINSIC_XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[77]; +case INTRINSIC_XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[77]; +case INTRINSIC_XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[77]; +case INTRINSIC_XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[77]; +case INTRINSIC_XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VLDMXCSR_MEMd: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VSTMXCSR_MEMd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVNTDQA_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVNTDQA_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VMOVNTDQ_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VMOVNTDQ_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VMOVNTPD_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVNTPD_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVNTPS_MEMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVNTPS_MEMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESIMC_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VAESIMC_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_YMMqq_XMMdq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[102]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[102]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[103]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[103]; +case INTRINSIC_XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256: + return X86CommonArchitecture::cached_output_types[104]; +case INTRINSIC_XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128: + return X86CommonArchitecture::cached_output_types[105]; +case INTRINSIC_XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256: + return X86CommonArchitecture::cached_output_types[106]; +case INTRINSIC_XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128: + return X86CommonArchitecture::cached_output_types[107]; +case INTRINSIC_XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256: + return X86CommonArchitecture::cached_output_types[104]; +case INTRINSIC_XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128: + return X86CommonArchitecture::cached_output_types[105]; +case INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256: + return X86CommonArchitecture::cached_output_types[107]; +case INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128: + return X86CommonArchitecture::cached_output_types[108]; +case INTRINSIC_XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256: + return X86CommonArchitecture::cached_output_types[109]; +case INTRINSIC_XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128: + return X86CommonArchitecture::cached_output_types[110]; +case INTRINSIC_XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256: + return X86CommonArchitecture::cached_output_types[111]; +case INTRINSIC_XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128: + return X86CommonArchitecture::cached_output_types[112]; +case INTRINSIC_XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256: + return X86CommonArchitecture::cached_output_types[109]; +case INTRINSIC_XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128: + return X86CommonArchitecture::cached_output_types[110]; +case INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256: + return X86CommonArchitecture::cached_output_types[112]; +case INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128: + return X86CommonArchitecture::cached_output_types[113]; +case INTRINSIC_XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_XMMdq_MEMb: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_XMMdq_XMMb: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_YMMqq_MEMb: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_YMMqq_XMMb: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_XMMdq_MEMw: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_XMMdq_XMMw: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_YMMqq_MEMw: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_YMMqq_XMMw: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_XMMdq_MEMd: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_XMMdq_XMMd: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_YMMqq_MEMd: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_YMMqq_XMMd: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMdq_MEMq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMdq_XMMq: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMqq_MEMq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMqq_XMMq: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VBROADCASTI128_YMMqq_MEMdq: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_BLSR_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLSR_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLSR_VGPR64q_MEMq: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_BLSR_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_BLSMSK_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLSMSK_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLSMSK_VGPR64q_MEMq: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_BLSMSK_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_BLSI_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLSI_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BLSI_VGPR64q_MEMq: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_BLSI_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_output_types[21]; +case INTRINSIC_XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_output_types[33]; +case INTRINSIC_XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd: + return X86CommonArchitecture::cached_output_types[30]; +case INTRINSIC_XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q: + return X86CommonArchitecture::cached_output_types[57]; +case INTRINSIC_XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq: + return X86CommonArchitecture::cached_output_types[57]; +case INTRINSIC_XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_RORX_VGPR32d_MEMd_IMMb: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_RORX_VGPR64q_MEMq_IMMb: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[119]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[119]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[103]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[102]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[103]; +case INTRINSIC_XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[103]; +case INTRINSIC_XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[24]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[58]; +case INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[92]; +case INTRINSIC_XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[92]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[120]; +case INTRINSIC_XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[121]; +case INTRINSIC_XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[122]; +case INTRINSIC_XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[123]; +case INTRINSIC_XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[124]; +case INTRINSIC_XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[125]; +case INTRINSIC_XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[120]; +case INTRINSIC_XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[121]; +case INTRINSIC_XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[122]; +case INTRINSIC_XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[125]; +case INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[124]; +case INTRINSIC_XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[124]; +case INTRINSIC_XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[101]; +case INTRINSIC_XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[49]; +case INTRINSIC_XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[101]; +case INTRINSIC_XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[49]; +case INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[101]; +case INTRINSIC_XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[92]; +case INTRINSIC_XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[127]; +case INTRINSIC_XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[128]; +case INTRINSIC_XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[129]; +case INTRINSIC_XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[130]; +case INTRINSIC_XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[131]; +case INTRINSIC_XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[132]; +case INTRINSIC_XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[129]; +case INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[128]; +case INTRINSIC_XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[128]; +case INTRINSIC_XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[130]; +case INTRINSIC_XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[131]; +case INTRINSIC_XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[132]; +case INTRINSIC_XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[133]; +case INTRINSIC_XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[67]; +case INTRINSIC_XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[67]; +case INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[134]; +case INTRINSIC_XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[133]; +case INTRINSIC_XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[41]; +case INTRINSIC_XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[135]; +case INTRINSIC_XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[136]; +case INTRINSIC_XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[68]; +case INTRINSIC_XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[68]; +case INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[137]; +case INTRINSIC_XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[136]; +case INTRINSIC_XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[43]; +case INTRINSIC_XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[138]; +case INTRINSIC_XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512: + return X86CommonArchitecture::cached_output_types[39]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[133]; +case INTRINSIC_XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[67]; +case INTRINSIC_XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[67]; +case INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[134]; +case INTRINSIC_XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[133]; +case INTRINSIC_XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[41]; +case INTRINSIC_XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[135]; +case INTRINSIC_XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[36]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[139]; +case INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[139]; +case INTRINSIC_XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[139]; +case INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[140]; +case INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[140]; +case INTRINSIC_XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[140]; +case INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[139]; +case INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[139]; +case INTRINSIC_XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[139]; +case INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[140]; +case INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[140]; +case INTRINSIC_XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[140]; +case INTRINSIC_XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[141]; +case INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[141]; +case INTRINSIC_XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[141]; +case INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[142]; +case INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[142]; +case INTRINSIC_XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[142]; +case INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[141]; +case INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[141]; +case INTRINSIC_XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[141]; +case INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[142]; +case INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[142]; +case INTRINSIC_XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[142]; +case INTRINSIC_XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[76]; +case INTRINSIC_XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[99]; +case INTRINSIC_XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[126]; +case INTRINSIC_XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[145]; +case INTRINSIC_XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[145]; +case INTRINSIC_XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[145]; +case INTRINSIC_XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[145]; +case INTRINSIC_XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[145]; +case INTRINSIC_XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[145]; +case INTRINSIC_XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[133]; +case INTRINSIC_XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[25]; +case INTRINSIC_XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[29]; +case INTRINSIC_XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[23]; +case INTRINSIC_XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[135]; +case INTRINSIC_XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[1]; +case INTRINSIC_XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5: + return X86CommonArchitecture::cached_output_types[135]; +case INTRINSIC_XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[38]; +case INTRINSIC_XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[91]; +case INTRINSIC_XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[82]; +case INTRINSIC_XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[145]; +case INTRINSIC_XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[145]; +case INTRINSIC_XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[145]; +case INTRINSIC_XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[145]; +case INTRINSIC_XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[68]; +case INTRINSIC_XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[67]; +case INTRINSIC_XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[67]; +case INTRINSIC_XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[69]; +case INTRINSIC_XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[97]; +case INTRINSIC_XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + return X86CommonArchitecture::cached_output_types[145]; +case INTRINSIC_XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512: + return X86CommonArchitecture::cached_output_types[145]; +case INTRINSIC_XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[40]; +case INTRINSIC_XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[98]; +case INTRINSIC_XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + return X86CommonArchitecture::cached_output_types[146]; +case INTRINSIC_XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[88]; +case INTRINSIC_XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[116]; +case INTRINSIC_XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[87]; +case INTRINSIC_XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[115]; +case INTRINSIC_XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[64]; +case INTRINSIC_XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[63]; +case INTRINSIC_XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[42]; +case INTRINSIC_XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[96]; +case INTRINSIC_XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[117]; +case INTRINSIC_XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[44]; +case INTRINSIC_XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[90]; +case INTRINSIC_XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[118]; +case INTRINSIC_XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[37]; +case INTRINSIC_XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[95]; +case INTRINSIC_XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[143]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[75]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[94]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + return X86CommonArchitecture::cached_output_types[144]; +case INTRINSIC_XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512: + return X86CommonArchitecture::cached_output_types[147]; +case INTRINSIC_XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_output_types[147]; +case INTRINSIC_XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512: + return X86CommonArchitecture::cached_output_types[147]; +case INTRINSIC_XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_output_types[147]; +case INTRINSIC_XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512: + return X86CommonArchitecture::cached_output_types[147]; +case INTRINSIC_XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_output_types[147]; +case INTRINSIC_XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512: + return X86CommonArchitecture::cached_output_types[147]; +case INTRINSIC_XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512: + return X86CommonArchitecture::cached_output_types[147]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[45]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[100]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[147]; +case INTRINSIC_XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512: + return X86CommonArchitecture::cached_output_types[147]; +case INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; +case INTRINSIC_XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512: + return X86CommonArchitecture::cached_output_types[114]; diff --git a/arch/x86/xed b/arch/x86/xed new file mode 160000 +Subproject afbb851b5f2f2ac6cdb6e6d9bebbaf2d4e77286 diff --git a/arch/x86/xed-mbuild.patch b/arch/x86/xed-mbuild.patch new file mode 100644 index 00000000..11d88322 --- /dev/null +++ b/arch/x86/xed-mbuild.patch @@ -0,0 +1,57 @@ +diff --git a/mbuild/build_env.py b/mbuild/build_env.py +index 396cd99..85a1c4f 100755 +--- a/mbuild/build_env.py ++++ b/mbuild/build_env.py +@@ -145,7 +145,7 @@ def set_env_gnu(env): + env['ARCHIVER'] = ( 'compiler', { 'gnu': 'ar', # or GAR?? + 'icc' : 'xiar', + 'iclang' : 'xiar', +- 'clang':'llvm-ar' }) ++ 'clang':'ar' }) + if env['RANLIB_CMD'] == '': + env['RANLIB_CMD'] = 'ranlib' + +@@ -250,20 +250,6 @@ def find_ms_toolchain(env): + # anything else is probably questionable. + + incoming_setup = True # presume system setup by user +- if env['vc_dir'] == '' or env['setup_msvc']: +- incoming_setup = False +- env['vc_dir'] = msvs.set_msvs_env(env) +- +- # toolchain is the bin directory of the compiler with a trailing slash +- if env['toolchain'] == '': +- if incoming_setup: +- # relying on user-setup env (say MSVS cmd.exe or vcvars-equiv bat file) +- if os.environ['VisualStudioVersion'] in ['15.0','16.0','17.0']: +- env['msvs_version'] = str(int(float(os.environ['VisualStudioVersion']))) +- msvs.set_msvc_compilers(env, os.environ['VCToolsInstallDir']) +- if env['compiler']=='ms': +- env['toolchain'] = msvs.pick_compiler(env) +- + + + def _check_set_rc(env, sdk): +@@ -366,22 +352,6 @@ def set_env_ms(env): + + env['link_prefix'] = ('use_compiler_to_link', { True:'/link', + False:'' }) +- if env['host_cpu'] == 'ia32': +- env['LINKFLAGS'] += ' %(link_prefix)s /MACHINE:X86' +- env['ARFLAGS'] += ' /MACHINE:X86' +- elif env['host_cpu'] == 'x86-64': +- env['LINKFLAGS'] += ' %(link_prefix)s /MACHINE:X64' +- env['ARFLAGS'] += ' /MACHINE:X64' +- +- env['favor'] = ( 'compiler', { 'ms' : ' /favor:EM64T', +- 'otherwise' : '' }) +- env['CXXFLAGS'] += ' %(favor)s' +- env['CCFLAGS'] += ' %(favor)s' +- +- elif env['host_cpu'] == 'ipf': +- env['LINKFLAGS'] += ' %(link_prefix)s /MACHINE:IA64' +- env['ARFLAGS'] += ' /MACHINE:IA64' +- + env['COPT'] = '/c' + env['DOPT'] = '/D' + env['ASDOPT'] = '/D' diff --git a/arch/x86/yasm b/arch/x86/yasm new file mode 160000 +Subproject bb619b659ed082744ffbe65b0b31367d34e5bd4 |