diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/arch_mips.cpp | 4 | ||||
| -rw-r--r-- | arch/riscv/src/lib.rs | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/arch_mips.cpp b/arch/mips/arch_mips.cpp index 6a3d80e4..50ad0f75 100644 --- a/arch/mips/arch_mips.cpp +++ b/arch/mips/arch_mips.cpp @@ -301,7 +301,7 @@ protected: if (instr.operands[0].immediate != addr + 8) result.AddBranch(CallDestination, instr.operands[0].immediate, nullptr, hasBranchDelay); else - result.branchDelay = 1; // We have a "get pc" mnemonic; do nothing + result.delaySlots = 1; // We have a "get pc" mnemonic; do nothing break; case MIPS_JAL: @@ -311,7 +311,7 @@ protected: //Jmp to register register value is unknown case MIPS_JALR: case MIPS_JALR_HB: - result.branchDelay = 1; + result.delaySlots = 1; break; case MIPS_BGEZAL: diff --git a/arch/riscv/src/lib.rs b/arch/riscv/src/lib.rs index 91a418f7..bc67e465 100644 --- a/arch/riscv/src/lib.rs +++ b/arch/riscv/src/lib.rs @@ -687,7 +687,7 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo _ => return None, }; - let mut res = InstructionInfo::new(inst_len, false); + let mut res = InstructionInfo::new(inst_len, 0); match op { Op::Jal(ref j) => { |