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-rw-r--r--arch/arm64/arch_arm64.cpp19
-rwxr-xr-xarch/arm64/arm64test.py5153
-rw-r--r--arch/arm64/disassembler/test_cases.txt1
-rw-r--r--arch/arm64/il.cpp704
-rw-r--r--arch/arm64/il.h2
-rw-r--r--arch/arm64/il_macros.h2
-rw-r--r--arch/arm64/misc/neon_intrins.c6
-rw-r--r--arch/arm64/neon_intrinsics.cpp21051
-rw-r--r--arch/arm64/neon_intrinsics.h57
-rwxr-xr-xarch/arm64/test_gen.py108
10 files changed, 17259 insertions, 9844 deletions
diff --git a/arch/arm64/arch_arm64.cpp b/arch/arm64/arch_arm64.cpp
index be856e79..13198af9 100644
--- a/arch/arm64/arch_arm64.cpp
+++ b/arch/arm64/arch_arm64.cpp
@@ -266,6 +266,7 @@ class Arm64Architecture : public Architecture
protected:
size_t m_bits;
bool m_onlyDisassembleOnAlignedAddresses;
+ bool m_preferIntrinsics;
virtual bool Disassemble(const uint8_t* data, uint64_t addr, size_t maxLen, Instruction& result)
{
@@ -717,6 +718,7 @@ class Arm64Architecture : public Architecture
{
Ref<Settings> settings = Settings::Instance();
m_onlyDisassembleOnAlignedAddresses = settings->Get<bool>("arch.aarch64.disassembly.alignRequired") ? 1 : 0;
+ m_preferIntrinsics = settings->Get<bool>("arch.aarch64.disassembly.preferIntrinsics") ? 1 : 0;
}
bool CanAssemble() override { return true; }
@@ -1238,7 +1240,15 @@ class Arm64Architecture : public Architecture
}
len = 4;
- return GetLowLevelILForInstruction(this, addr, il, instr, GetAddressSize(), m_onlyDisassembleOnAlignedAddresses);
+ return GetLowLevelILForInstruction(this, addr, il, instr, GetAddressSize(), m_onlyDisassembleOnAlignedAddresses, [&]() -> bool
+ {
+ Ref<Function> f = il.GetFunction();
+ Ref<BinaryView> v;
+ Ref<Settings> s = Settings::Instance();
+ if (s && f && (v = f->GetView()))
+ return m_preferIntrinsics && s->Get<bool>("arch.aarch64.disassembly.preferIntrinsics", v);
+ return true;
+ });
}
@@ -3513,6 +3523,13 @@ static void InitAarch64Settings()
"default" : true,
"description" : "Require instructions be on 4-byte aligned addresses to be disassembled."
})");
+ settings->RegisterSetting("arch.aarch64.disassembly.preferIntrinsics",
+ R"({
+ "title" : "AARCH64 Prefer Intrinsics for Vector Operations",
+ "type" : "boolean",
+ "default" : true,
+ "description" : "Prefer generating calls to intrinsics (where one is available) to lifting vector operations as unrolled loops (where available). Note that not all vector operations are currently lifted as either intrinsics or unrolled loops."
+ })");
}
diff --git a/arch/arm64/arm64test.py b/arch/arm64/arm64test.py
index 1a375457..159d76af 100755
--- a/arch/arm64/arm64test.py
+++ b/arch/arm64/arm64test.py
@@ -15,6 +15,7 @@ path_il_h = os.path.join(path_here, 'il.h')
ATTR_PTR_AUTH = ILInstructionAttribute(16) # enum BNILInstructionAttribute.SrcInstructionUsesPointerAuth from api/binaryninjacore.h
+
tests_udf = [
# udf #0
(b'\x00\x00\x00\x00', 'LLIL_TRAP(0)'),
@@ -58,11 +59,13 @@ tests_pac = [
# ldraa x7, [x30, #-0x6b0] (example of encoding: LDRAA_64_ldst_pac)
(b'\xC7\xA7\x72\xF8', 'LLIL_SET_REG.q(x7,LLIL_LOAD.q(LLIL_ADD.q(LLIL_REG.q(x30),LLIL_CONST.q(0xFFFFFFFFFFFFF950))))', ATTR_PTR_AUTH),
# ldraa x7, [sp, #-0xf20]! (example of encoding: LDRAA_64W_ldst_pac)
- (b'\xE7\xCF\x61\xF8', 'LLIL_SET_REG.q(sp,LLIL_ADD.q(LLIL_REG.q(sp),LLIL_CONST.q(0xFFFFFFFFFFFFF0E0))); LLIL_SET_REG.q(x7,LLIL_LOAD.q(LLIL_REG.q(sp)))', ATTR_PTR_AUTH),
+ (b'\xE7\xCF\x61\xF8', 'LLIL_SET_REG.q(sp,LLIL_ADD.q(LLIL_REG.q(sp),LLIL_CONST.q(0xFFFFFFFFFFFFF0E0)));' + \
+ ' LLIL_SET_REG.q(x7,LLIL_LOAD.q(LLIL_REG.q(sp)))', ATTR_PTR_AUTH),
# ldrab x27, [x17, #0x8d0] (example of encoding: LDRAB_64_ldst_pac)
(b'\x3B\xA6\xB1\xF8', 'LLIL_SET_REG.q(x27,LLIL_LOAD.q(LLIL_ADD.q(LLIL_REG.q(x17),LLIL_CONST.q(0x8D0))))', ATTR_PTR_AUTH),
# ldrab x20, [x1, #0xac8]! (example of encoding: LDRAB_64W_ldst_pac)
- (b'\x34\x9C\xB5\xF8', 'LLIL_SET_REG.q(x1,LLIL_ADD.q(LLIL_REG.q(x1),LLIL_CONST.q(0xAC8))); LLIL_SET_REG.q(x20,LLIL_LOAD.q(LLIL_REG.q(x1)))', ATTR_PTR_AUTH),
+ (b'\x34\x9C\xB5\xF8', 'LLIL_SET_REG.q(x1,LLIL_ADD.q(LLIL_REG.q(x1),LLIL_CONST.q(0xAC8)));' + \
+ ' LLIL_SET_REG.q(x20,LLIL_LOAD.q(LLIL_REG.q(x1)))', ATTR_PTR_AUTH),
# RETURN
# ret x27 (example of encoding: RET_64R_branch_reg)
@@ -101,21 +104,21 @@ tests_pac = [
(b'\xA3\x0E\x1F\xD7', 'LLIL_JUMP(LLIL_REG.q(x21))', ATTR_PTR_AUTH), # brab x21, x3
# LDRAA_64W_ldst_pac 111110000x1xxxxxxxxxxxxxxxxxxxxx
(b'\xAE\x1D\x25\xF8', 'LLIL_SET_REG.q(x13,LLIL_ADD.q(LLIL_REG.q(x13),LLIL_CONST.q(0x288)));' + \
- ' LLIL_SET_REG.q(x14,LLIL_LOAD.q(LLIL_REG.q(x13)))', ATTR_PTR_AUTH), # ldraa x14, [x13, #648]!
+ ' LLIL_SET_REG.q(x14,LLIL_LOAD.q(LLIL_REG.q(x13)))', ATTR_PTR_AUTH), # ldraa x14, [x13, #648]!
(b'\x63\x6E\x62\xF8', 'LLIL_SET_REG.q(x19,LLIL_ADD.q(LLIL_REG.q(x19),LLIL_CONST.q(0xFFFFFFFFFFFFF130)));' + \
- ' LLIL_SET_REG.q(x3,LLIL_LOAD.q(LLIL_REG.q(x19)))', ATTR_PTR_AUTH), # ldraa x3, [x19, #-3792]!
+ ' LLIL_SET_REG.q(x3,LLIL_LOAD.q(LLIL_REG.q(x19)))', ATTR_PTR_AUTH), # ldraa x3, [x19, #-3792]!
# LDRAA_64_ldst_pac 111110000x1xxxxxxxxxxxxxxxxxxxxx
(b'\x90\x15\x62\xF8', 'LLIL_SET_REG.q(x16,LLIL_LOAD.q(LLIL_ADD.q(LLIL_REG.q(x12),LLIL_CONST.q(0xFFFFFFFFFFFFF108))))', ATTR_PTR_AUTH), # ldraa x16, [x12, #-3832]
(b'\x52\x26\x73\xF8', 'LLIL_SET_REG.q(x18,LLIL_LOAD.q(LLIL_ADD.q(LLIL_REG.q(x18),LLIL_CONST.q(0xFFFFFFFFFFFFF990))))', ATTR_PTR_AUTH), # ldraa x18, [x18, #-1648]
# LDRAB_64W_ldst_pac 111110001x1xxxxxxxxx11xxxxxxxxxx
(b'\x68\xDE\xB8\xF8', 'LLIL_SET_REG.q(x19,LLIL_ADD.q(LLIL_REG.q(x19),LLIL_CONST.q(0xC68)));' + \
- ' LLIL_SET_REG.q(x8,LLIL_LOAD.q(LLIL_REG.q(x19)))', ATTR_PTR_AUTH), # ldrab x8, [x19, #3176]!
+ ' LLIL_SET_REG.q(x8,LLIL_LOAD.q(LLIL_REG.q(x19)))', ATTR_PTR_AUTH), # ldrab x8, [x19, #3176]!
(b'\x8D\x0D\xFF\xF8', 'LLIL_SET_REG.q(x12,LLIL_ADD.q(LLIL_REG.q(x12),LLIL_CONST.q(0xFFFFFFFFFFFFFF80)));' + \
- ' LLIL_SET_REG.q(x13,LLIL_LOAD.q(LLIL_REG.q(x12)))', ATTR_PTR_AUTH), # ldrab x13, [x12, #-o]!
+ ' LLIL_SET_REG.q(x13,LLIL_LOAD.q(LLIL_REG.q(x12)))', ATTR_PTR_AUTH), # ldrab x13, [x12, #-o]!
# LDRAB_64_ldst_pac 111110001x1xxxxxxxxxxxxxxxxxxxxx
(b'\x94\xF5\xA1\xF8', 'LLIL_SET_REG.q(x20,LLIL_LOAD.q(LLIL_ADD.q(LLIL_REG.q(x12),LLIL_CONST.q(0xF8))))', ATTR_PTR_AUTH), # ldrab x20, [x12, #248]
(b'\x2B\x35\xAA\xF8', 'LLIL_SET_REG.q(x11,LLIL_LOAD.q(LLIL_ADD.q(LLIL_REG.q(x9),LLIL_CONST.q(0x518))))', ATTR_PTR_AUTH), # ldrab x11, [x9, #1304]
- (b'\x28\x1b\x02\x90', 'LLIL_SET_REG.q(x8,LLIL_CONST.q(0x4364000))'), # ldrsw x8, 0x100008000
+ (b'\x28\x1B\x02\x90', 'LLIL_SET_REG.q(x8,LLIL_CONST.q(0x4364000))'), # ldrsw x8, 0x100008000
# RETAA_64E_branch_reg 11010110010111110000101111111111
(b'\xFF\x0B\x5F\xD6', 'LLIL_RET(LLIL_REG.q(x30))', ATTR_PTR_AUTH), # retaa
# RETAB_64E_branch_reg 11010110010111110000111111111111
@@ -126,7 +129,7 @@ tests_pac = [
# intrinsics or as their non-authenticated counterparts
# see if the line "#define LIFT_PAC_AS_INTRINSIC 1" exists in il.h
if '#define LIFT_PAC_AS_INTRINSIC 1\n' in open(path_il_h).readlines():
- print('testing that select PAC instructions lift to intrinsics')
+ print('testing that select PAC instructions lift to intrinsics', file=sys.stderr)
tests_pac.extend([
# AUTHENTICATE (VALIDATE CODE)
# regex: autda[d|i]z?[a|b] where:
@@ -235,7 +238,7 @@ if '#define LIFT_PAC_AS_INTRINSIC 1\n' in open(path_il_h).readlines():
])
# DO NOT LIFT PAC AS INTRINSIC
else:
- print('testing that select PAC instructions lift to NOP')
+ print('testing that select PAC instructions lift to NOP', file=sys.stderr)
tests_pac.extend([
# In all these cases, we leave the target untouched.
# Authenticate instructions normally modify the target, removing the code if authentication succeeds.
@@ -377,23 +380,24 @@ tests_load_acquire_store_release = [
(b'\x51\x52\x5B\xD9', 'LLIL_SET_REG.q(x17,LLIL_LOAD.q(LLIL_ADD.q(LLIL_REG.q(x18),LLIL_CONST.q(0xFFFFFFFFFFFFFFB5))))'), # ldapur x17, [x18, #-0x4b]
(b'\x71\x30\x56\xD9', 'LLIL_SET_REG.q(x17,LLIL_LOAD.q(LLIL_ADD.q(LLIL_REG.q(x3),LLIL_CONST.q(0xFFFFFFFFFFFFFF63))))'), # ldapur x17, [x3, #-0x9d]
(b'\x6C\x00\x4C\xD9', 'LLIL_SET_REG.q(x12,LLIL_LOAD.q(LLIL_ADD.q(LLIL_REG.q(x3),LLIL_CONST.q(0xC0))))'), # ldapur x12, [x3, #0xc0]
- (b'\xD4\x82\x43\xD9', 'LLIL_SET_REG.q(x20,LLIL_LOAD.q(LLIL_ADD.q(LLIL_REG.q(x22),LLIL_CONST.q(0x38))))') # ldapur x20, [x22, #0x38]
+ (b'\xD4\x82\x43\xD9', 'LLIL_SET_REG.q(x20,LLIL_LOAD.q(LLIL_ADD.q(LLIL_REG.q(x22),LLIL_CONST.q(0x38))))'), # ldapur x20, [x22, #0x38]
]
tests_movk = [
- (b'\xe9\xae\xb7\xf2', 'LLIL_SET_REG.q(x9,LLIL_AND.q(LLIL_REG.q(x9),LLIL_NOT.q(LLIL_CONST.q(0xFFFF0000)))); LLIL_SET_REG.q(x9,LLIL_OR.q(LLIL_REG.q(x9),LLIL_CONST.q(0xBD770000)))'), # movk x9, #0xbd77, lsl #0x10
+ (b'\xE9\xAE\xB7\xF2', 'LLIL_SET_REG.q(x9,LLIL_AND.q(LLIL_REG.q(x9),LLIL_CONST.q(0xFFFFFFFF0000FFFF)));' + \
+ ' LLIL_SET_REG.q(x9,LLIL_OR.q(LLIL_REG.q(x9),LLIL_CONST.q(0xBD770000)))'), # movk x9, #0xbd77, lsl #0x10
]
tests_mvni = [
- (b'\xe2\x05\x01\x6f', 'LLIL_SET_REG.o(v2,LLIL_NOT.o(LLIL_CONST.o(0x2F)))'), # mvni v2.4s, #0x2f
+ (b'\xE2\x05\x01\x6F', 'LLIL_SET_REG.o(v2,LLIL_NOT.o(LLIL_CONST.o(0x2F)))'), # mvni v2.4s, #0x2f
]
# https://github.com/Vector35/binaryninja-api/issues/2791
tests_2791 = [
- (b'\x00\x20\x21\x1e', 'LLIL_FSUB.d{f*}(LLIL_REG.d(s0),LLIL_REG.d(s1))'), # fcmp s0, s1
+ (b'\x00\x20\x21\x1E', 'LLIL_FSUB.d{f*}(LLIL_REG.d(s0),LLIL_REG.d(s1))'), # fcmp s0, s1
]
-tests_ucvtf = [
+tests_msr = [
# msr, mrs with unnamed (implementation specific) sysregs
(b'\x2B\x19\x1B\xD5', 'LLIL_INTRINSIC([sysreg_unknown],_WriteStatusReg,[LLIL_REG.q(x11)])'), # msr s3_3_c1_c9_1, x11
(b'\xEE\x47\x1E\xD5', 'LLIL_INTRINSIC([sysreg_unknown],_WriteStatusReg,[LLIL_REG.q(x14)])'), # msr s3_6_c4_c7_7, x14
@@ -416,98 +420,101 @@ tests_ucvtf = [
(b'\x23\x00\x3B\xD5', 'LLIL_INTRINSIC([x3],_ReadStatusReg,[LLIL_REG(ctr_el0)])'), # mrs x3, ctr_el0
(b'\xE1\x00\x1B\xD5', 'LLIL_INTRINSIC([dczid_el0],_WriteStatusReg,[LLIL_REG.q(x1)])'), # msr dczid_el0, x1
(b'\xE3\x00\x3B\xD5', 'LLIL_INTRINSIC([x3],_ReadStatusReg,[LLIL_REG(dczid_el0)])'), # mrs x3, dczid_el0
+]
+
+tests_ucvtf = [
# when same input/output register, encoding is UCVTF_asisdmisc_R
# ucvtf s16, s7 UCVTF_asisdmisc_R
- (b'\xF0\xD8\x21\x7E', 'LLIL_INTRINSIC([s16],vcvts_f32_u32,[LLIL_REG.d(s7)])'),
+ (b'\xF0\xD8\x21\x7E', 'LLIL_SET_REG.d(s16,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.d(s7))))'),
# ucvtf d26, d30 UCVTF_asisdmisc_R
- (b'\xDA\xDB\x61\x7E', 'LLIL_INTRINSIC([d26],vcvt_f64_u64,[LLIL_REG.q(d30)])'),
+ (b'\xDA\xDB\x61\x7E', 'LLIL_SET_REG.q(d26,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.q(d30))))'),
# ucvtf s6, s19 UCVTF_asisdmisc_R
- (b'\x66\xDA\x21\x7E', 'LLIL_INTRINSIC([s6],vcvts_f32_u32,[LLIL_REG.d(s19)])'),
+ (b'\x66\xDA\x21\x7E', 'LLIL_SET_REG.d(s6,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.d(s19))))'),
# ucvtf s13, s0 UCVTF_asisdmisc_R
- (b'\x0D\xD8\x21\x7E', 'LLIL_INTRINSIC([s13],vcvts_f32_u32,[LLIL_REG.d(s0)])'),
+ (b'\x0D\xD8\x21\x7E', 'LLIL_SET_REG.d(s13,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.d(s0))))'),
# ucvtf d28, d26 UCVTF_asisdmisc_R
- (b'\x5C\xDB\x61\x7E', 'LLIL_INTRINSIC([d28],vcvt_f64_u64,[LLIL_REG.q(d26)])'),
+ (b'\x5C\xDB\x61\x7E', 'LLIL_SET_REG.q(d28,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.q(d26))))'),
# ucvtf d25, d11 UCVTF_asisdmisc_R
- (b'\x79\xD9\x61\x7E', 'LLIL_INTRINSIC([d25],vcvt_f64_u64,[LLIL_REG.q(d11)])'),
+ (b'\x79\xD9\x61\x7E', 'LLIL_SET_REG.q(d25,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.q(d11))))'),
# ucvtf d24, d21 UCVTF_asisdmisc_R
- (b'\xB8\xDA\x61\x7E', 'LLIL_INTRINSIC([d24],vcvt_f64_u64,[LLIL_REG.q(d21)])'),
+ (b'\xB8\xDA\x61\x7E', 'LLIL_SET_REG.q(d24,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.q(d21))))'),
# ucvtf s7, s18 UCVTF_asisdmisc_R
- (b'\x47\xDA\x21\x7E', 'LLIL_INTRINSIC([s7],vcvts_f32_u32,[LLIL_REG.d(s18)])'),
+ (b'\x47\xDA\x21\x7E', 'LLIL_SET_REG.d(s7,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.d(s18))))'),
# when 16-bit reg, needs FP16 extension and encoding name breaks convention
# ucvtf h30, h0 UCVTF_asisdmiscfp16_R
- (b'\x1E\xD8\x79\x7E', 'LLIL_INTRINSIC([h30],vcvth_f16_u16,[LLIL_REG.w(h0)])'),
+ (b'\x1E\xD8\x79\x7E', 'LLIL_SET_REG.w(h30,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.w(h0))))'),
# ucvtf h22, h6 UCVTF_asisdmiscfp16_R
- (b'\xD6\xD8\x79\x7E', 'LLIL_INTRINSIC([h22],vcvth_f16_u16,[LLIL_REG.w(h6)])'),
+ (b'\xD6\xD8\x79\x7E', 'LLIL_SET_REG.w(h22,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.w(h6))))'),
# ucvtf h7, h2 UCVTF_asisdmiscfp16_R
- (b'\x47\xD8\x79\x7E', 'LLIL_INTRINSIC([h7],vcvth_f16_u16,[LLIL_REG.w(h2)])'),
+ (b'\x47\xD8\x79\x7E', 'LLIL_SET_REG.w(h7,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.w(h2))))'),
# ucvtf h24, h18 UCVTF_asisdmiscfp16_R
- (b'\x58\xDA\x79\x7E', 'LLIL_INTRINSIC([h24],vcvth_f16_u16,[LLIL_REG.w(h18)])'),
+ (b'\x58\xDA\x79\x7E', 'LLIL_SET_REG.w(h24,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.w(h18))))'),
# ucvtf h8, h21 UCVTF_asisdmiscfp16_R
# 64-bit GPR to 64-bit FP
# ucvtf d30, x19 UCVTF_D64_float2int
- (b'\x7E\x02\x63\x9E', 'LLIL_INTRINSIC([d30],vcvt_f64_u64,[LLIL_REG.q(x19)])'),
+ (b'\x7E\x02\x63\x9E', 'LLIL_SET_REG.q(d30,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.q(x19))))'),
# ucvtf d10, x28 UCVTF_D64_float2int
- (b'\x8A\x03\x63\x9E', 'LLIL_INTRINSIC([d10],vcvt_f64_u64,[LLIL_REG.q(x28)])'),
+ (b'\x8A\x03\x63\x9E', 'LLIL_SET_REG.q(d10,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.q(x28))))'),
# ucvtf d16, x21 UCVTF_D64_float2int
- (b'\xB0\x02\x63\x9E', 'LLIL_INTRINSIC([d16],vcvt_f64_u64,[LLIL_REG.q(x21)])'),
+ (b'\xB0\x02\x63\x9E', 'LLIL_SET_REG.q(d16,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.q(x21))))'),
# ucvtf d18, x24 UCVTF_D64_float2int
- (b'\x12\x03\x63\x9E', 'LLIL_INTRINSIC([d18],vcvt_f64_u64,[LLIL_REG.q(x24)])'),
+ (b'\x12\x03\x63\x9E', 'LLIL_SET_REG.q(d18,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.q(x24))))'),
# 64-bit GPR to 32-bit FP
# ucvtf s29, x5 UCVTF_S64_float2int
- (b'\xBD\x00\x23\x9E', 'LLIL_INTRINSIC([s29],vcvth_f16_u16,[LLIL_REG.q(x5)])'),
+ (b'\xBD\x00\x23\x9E', 'LLIL_SET_REG.d(s29,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.q(x5))))'),
# ucvtf s23, x8 UCVTF_S64_float2int
- (b'\x17\x01\x23\x9E', 'LLIL_INTRINSIC([s23],vcvth_f16_u16,[LLIL_REG.q(x8)])'),
+ (b'\x17\x01\x23\x9E', 'LLIL_SET_REG.d(s23,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.q(x8))))'),
# ucvtf s22, x14 UCVTF_S64_float2int
- (b'\xD6\x01\x23\x9E', 'LLIL_INTRINSIC([s22],vcvth_f16_u16,[LLIL_REG.q(x14)])'),
+ (b'\xD6\x01\x23\x9E', 'LLIL_SET_REG.d(s22,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.q(x14))))'),
# ucvtf s10, x11 UCVTF_S64_float2int
- (b'\x6A\x01\x23\x9E', 'LLIL_INTRINSIC([s10],vcvth_f16_u16,[LLIL_REG.q(x11)])'),
+ (b'\x6A\x01\x23\x9E', 'LLIL_SET_REG.d(s10,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.q(x11))))'),
# 64-bit GPR to 16-bit FP
# ucvtf h3, x2 UCVTF_H64_float2int
- (b'\x43\x00\xE3\x9E', 'LLIL_INTRINSIC([h3],vcvth_f16_u64,[LLIL_REG.q(x2)])'),
+ (b'\x43\x00\xE3\x9E', 'LLIL_SET_REG.w(h3,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.q(x2))))'),
# ucvtf h18, x21 UCVTF_H64_float2int
- (b'\xB2\x02\xE3\x9E', 'LLIL_INTRINSIC([h18],vcvth_f16_u64,[LLIL_REG.q(x21)])'),
+ (b'\xB2\x02\xE3\x9E', 'LLIL_SET_REG.w(h18,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.q(x21))))'),
# ucvtf h18, x7 UCVTF_H64_float2int
- (b'\xF2\x00\xE3\x9E', 'LLIL_INTRINSIC([h18],vcvth_f16_u64,[LLIL_REG.q(x7)])'),
+ (b'\xF2\x00\xE3\x9E', 'LLIL_SET_REG.w(h18,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.q(x7))))'),
# ucvtf h27, x29 UCVTF_H64_float2int
- (b'\xBB\x03\xE3\x9E', 'LLIL_INTRINSIC([h27],vcvth_f16_u64,[LLIL_REG.q(x29)])'),
+ (b'\xBB\x03\xE3\x9E', 'LLIL_SET_REG.w(h27,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.q(x29))))'),
# 32-bit GPR to 64-bit FP
# ucvtf d0, w7 UCVTF_D32_float2int
- (b'\xE0\x00\x63\x1E', 'LLIL_INTRINSIC([d0],vcvt_f64_u32,[LLIL_REG.d(w7)])'),
+ (b'\xE0\x00\x63\x1E', 'LLIL_SET_REG.q(d0,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.d(w7))))'),
# ucvtf d19, w25 UCVTF_D32_float2int
- (b'\x33\x03\x63\x1E', 'LLIL_INTRINSIC([d19],vcvt_f64_u32,[LLIL_REG.d(w25)])'),
+ (b'\x33\x03\x63\x1E', 'LLIL_SET_REG.q(d19,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.d(w25))))'),
# ucvtf d19, w5 UCVTF_D32_float2int
- (b'\xB3\x00\x63\x1E', 'LLIL_INTRINSIC([d19],vcvt_f64_u32,[LLIL_REG.d(w5)])'),
+ (b'\xB3\x00\x63\x1E', 'LLIL_SET_REG.q(d19,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.d(w5))))'),
# ucvtf d26, w16 UCVTF_D32_float2int
- (b'\x1A\x02\x63\x1E', 'LLIL_INTRINSIC([d26],vcvt_f64_u32,[LLIL_REG.d(w16)])'),
+ (b'\x1A\x02\x63\x1E', 'LLIL_SET_REG.q(d26,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.d(w16))))'),
# ucvtf d0, w7
- (b'\xE0\x00\x63\x1e', 'LLIL_INTRINSIC([d0],vcvt_f64_u32,[LLIL_REG.d(w7)])'),
+ (b'\xE0\x00\x63\x1E', 'LLIL_SET_REG.q(d0,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.d(w7))))'),
# 32-bit GPR to 64-bit FP + #<fbits>
# ucvtf d18, w3, #0x1f
(b'\x72\x84\x43\x1E', 'LLIL_INTRINSIC([d18],vcvtd_n_f64_u32,[LLIL_REG.d(w3),LLIL_CONST(31)])'),
# ucvtf d25, w5, #0x1c
(b'\xB9\x90\x43\x1E', 'LLIL_INTRINSIC([d25],vcvtd_n_f64_u32,[LLIL_REG.d(w5),LLIL_CONST(28)])'),
# ucvtf d22, w9, #0x2
- (b'\x36\xf9\x43\x1e', 'LLIL_INTRINSIC([d22],vcvtd_n_f64_u32,[LLIL_REG.d(w9),LLIL_CONST(2)])'),
+ (b'\x36\xF9\x43\x1E', 'LLIL_INTRINSIC([d22],vcvtd_n_f64_u32,[LLIL_REG.d(w9),LLIL_CONST(2)])'),
# ucvtf d12, w28, #0x3
- (b'\x8c\xf7\x43\x1e', 'LLIL_INTRINSIC([d12],vcvtd_n_f64_u32,[LLIL_REG.d(w28),LLIL_CONST(3)])'),
+ (b'\x8C\xF7\x43\x1E', 'LLIL_INTRINSIC([d12],vcvtd_n_f64_u32,[LLIL_REG.d(w28),LLIL_CONST(3)])'),
# 32-bit GPR to 32-bit FP
# ucvtf s29, w24 UCVTF_S32_float2int
- (b'\x1D\x03\x23\x1E', 'LLIL_INTRINSIC([s29],vcvts_f32_u32,[LLIL_REG.d(w24)])'),
+ (b'\x1D\x03\x23\x1E', 'LLIL_SET_REG.d(s29,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.d(w24))))'),
# ucvtf s6, w7 UCVTF_S32_float2int
- (b'\xE6\x00\x23\x1E', 'LLIL_INTRINSIC([s6],vcvts_f32_u32,[LLIL_REG.d(w7)])'),
+ (b'\xE6\x00\x23\x1E', 'LLIL_SET_REG.d(s6,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.d(w7))))'),
# ucvtf s31, w23 UCVTF_S32_float2int
- (b'\xFF\x02\x23\x1E', 'LLIL_INTRINSIC([s31],vcvts_f32_u32,[LLIL_REG.d(w23)])'),
+ (b'\xFF\x02\x23\x1E', 'LLIL_SET_REG.d(s31,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.d(w23))))'),
# ucvtf s21, w0 UCVTF_S32_float2int
- (b'\x15\x00\x23\x1E', 'LLIL_INTRINSIC([s21],vcvts_f32_u32,[LLIL_REG.d(w0)])'),
+ (b'\x15\x00\x23\x1E', 'LLIL_SET_REG.d(s21,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.d(w0))))'),
# 32-bit GPR to 16-bit FP
# ucvtf h5, w12 UCVTF_H32_float2int
- (b'\x85\x01\xE3\x1E', 'LLIL_INTRINSIC([h5],vcvth_f16_u32,[LLIL_REG.d(w12)])'),
+ (b'\x85\x01\xE3\x1E', 'LLIL_SET_REG.w(h5,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.d(w12))))'),
# ucvtf h30, w15 UCVTF_H32_float2int
- (b'\xFE\x01\xE3\x1E', 'LLIL_INTRINSIC([h30],vcvth_f16_u32,[LLIL_REG.d(w15)])'),
+ (b'\xFE\x01\xE3\x1E', 'LLIL_SET_REG.w(h30,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.d(w15))))'),
# ucvtf h7, w13 UCVTF_H32_float2int
- (b'\xA7\x01\xE3\x1E', 'LLIL_INTRINSIC([h7],vcvth_f16_u32,[LLIL_REG.d(w13)])'),
+ (b'\xA7\x01\xE3\x1E', 'LLIL_SET_REG.w(h7,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.d(w13))))'),
# ucvtf h26, w8 UCVTF_H32_float2int
- (b'\x1A\x01\xE3\x1E', 'LLIL_INTRINSIC([h26],vcvth_f16_u32,[LLIL_REG.d(w8)])'),
+ (b'\x1A\x01\xE3\x1E', 'LLIL_SET_REG.w(h26,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.d(w8))))'),
]
tests_ucvtf2 = [
@@ -516,37 +523,37 @@ tests_ucvtf2 = [
(b'\x72\x84\x43\x1E', 'LLIL_INTRINSIC([d18],vcvtd_n_f64_u32,[LLIL_REG.d(w3),LLIL_CONST(31)])'),
# UCVTF_D32_float2int 0001111001100011000000xxxxxxxxxx
# ucvtf d0, w7
- (b'\xE0\x00\x63\x1E', 'LLIL_INTRINSIC([d0],vcvt_f64_u32,[LLIL_REG.d(w7)])'),
+ (b'\xE0\x00\x63\x1E', 'LLIL_SET_REG.q(d0,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.d(w7))))'),
# UCVTF_D64_float2fix 1001111001000011xxxxxxxxxxxxxxxx
# ucvtf d19, x26, #0x23
(b'\x53\x77\x43\x9E', 'LLIL_INTRINSIC([d19],vcvtd_n_f64_u64,[LLIL_REG.q(x26),LLIL_CONST(35)])'),
# UCVTF_D64_float2int 1001111001100011000000xxxxxxxxxx
# ucvtf d30, x19
- (b'\x7E\x02\x63\x9E', 'LLIL_INTRINSIC([d30],vcvt_f64_u64,[LLIL_REG.q(x19)])'),
+ (b'\x7E\x02\x63\x9E', 'LLIL_SET_REG.q(d30,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.q(x19))))'),
# UCVTF_H32_float2fix 00011110110000111xxxxxxxxxxxxxxx
# ucvtf h3, w29, #0x13
(b'\xA3\xB7\xC3\x1E', 'LLIL_INTRINSIC([h3],vcvth_n_f16_u32,[LLIL_REG.d(w29),LLIL_CONST(19)])'),
# UCVTF_H32_float2int 0001111011100011000000xxxxxxxxxx
# ucvtf h5, w12
- (b'\x85\x01\xE3\x1E', 'LLIL_INTRINSIC([h5],vcvth_f16_u32,[LLIL_REG.d(w12)])'),
+ (b'\x85\x01\xE3\x1E', 'LLIL_SET_REG.w(h5,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.d(w12))))'),
# UCVTF_H64_float2fix 1001111011000011xxxxxxxxxxxxxxxx
# ucvtf h5, x13, #0x16
(b'\xA5\xA9\xC3\x9E', 'LLIL_INTRINSIC([h5],vcvth_n_f16_u64,[LLIL_REG.q(x13),LLIL_CONST(22)])'),
# UCVTF_H64_float2int 1001111011100011000000xxxxxxxxxx
# ucvtf h3, x2
- (b'\x43\x00\xE3\x9E', 'LLIL_INTRINSIC([h3],vcvth_f16_u64,[LLIL_REG.q(x2)])'),
+ (b'\x43\x00\xE3\x9E', 'LLIL_SET_REG.w(h3,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.q(x2))))'),
# UCVTF_S32_float2fix 00011110000000111xxxxxxxxxxxxxxx
# ucvtf s1, w22, #0x1
(b'\xC1\xFE\x03\x1E', 'LLIL_INTRINSIC([s1],vcvts_n_f32_u32,[LLIL_REG.d(w22),LLIL_CONST(1)])'),
# UCVTF_S32_float2int 0001111000100011000000xxxxxxxxxx
# ucvtf s29, w24
- (b'\x1D\x03\x23\x1E', 'LLIL_INTRINSIC([s29],vcvts_f32_u32,[LLIL_REG.d(w24)])'),
+ (b'\x1D\x03\x23\x1E', 'LLIL_SET_REG.d(s29,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.d(w24))))'),
# UCVTF_S64_float2fix 1001111000000011xxxxxxxxxxxxxxxx
# ucvtf s2, x27, #0xf
(b'\x62\xC7\x03\x9E', 'LLIL_INTRINSIC([s2],vcvts_n_f32_u64,[LLIL_REG.q(x27),LLIL_CONST(15)])'),
# UCVTF_S64_float2int 1001111000100011000000xxxxxxxxxx
# ucvtf s29, x5
- (b'\xBD\x00\x23\x9E', 'LLIL_INTRINSIC([s29],vcvth_f16_u16,[LLIL_REG.q(x5)])'),
+ (b'\xBD\x00\x23\x9E', 'LLIL_SET_REG.d(s29,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.q(x5))))'),
# UCVTF_asisdshf_C 011111110xxxxxxx111001xxxxxxxxxx
# ucvtf d20, d1, #0x2a
(b'\x34\xE4\x56\x7F', 'LLIL_INTRINSIC([d20],vcvt_n_f64_u64,[LLIL_REG.q(d1),LLIL_CONST(42)])'),
@@ -555,21 +562,81 @@ tests_ucvtf2 = [
(b'\xCF\xE5\x27\x2F', 'LLIL_INTRINSIC([v15],vcvt_n_f32_u32,[LLIL_REG.o(v14),LLIL_CONST(25)])'),
# UCVTF_asimdmisc_R 0x1011100x100001110110xxxxxxxxxx
# ucvtf v11.2d, v11.2d
- (b'\x6B\xD9\x61\x6E', 'LLIL_INTRINSIC([v11],vcvt_f32_u32,[LLIL_REG.o(v11)])'),
+ (b'\x6B\xD9\x61\x6E', 'LLIL_INTRINSIC([v11],vcvtq_f64_u64,[LLIL_REG.o(v11)])'),
# UCVTF_asimdmiscfp16_R 0x1011100111100111011xxxxxxxxxxx
# ucvtf v31.4h, v29.4h
- (b'\xBF\xDB\x79\x2E', 'LLIL_INTRINSIC([v31],vcvt_n_f16_u16,[LLIL_REG.o(v29)])'),
+ (b'\xBF\xDB\x79\x2E', 'LLIL_INTRINSIC([v31],vcvt_f16_u16,[LLIL_REG.o(v29)])'),
# UCVTF_asisdmisc_R 011111100x100001110110xxxxxxxxxx
# ucvtf s16, s7
- (b'\xF0\xD8\x21\x7E', 'LLIL_INTRINSIC([s16],vcvts_f32_u32,[LLIL_REG.d(s7)])'),
+ (b'\xF0\xD8\x21\x7E', 'LLIL_SET_REG.d(s16,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.d(s7))))'),
# UCVTF_asisdmiscfp16_R 0111111001111001110110xxxxxxxxxx
# ucvtf h30, h0
- (b'\x1E\xD8\x79\x7E', 'LLIL_INTRINSIC([h30],vcvth_f16_u16,[LLIL_REG.w(h0)])')
-]
+ (b'\x1E\xD8\x79\x7E', 'LLIL_SET_REG.w(h30,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.w(h0))))'),
-tests_scvtf = [
- # scvtf d1, x15 SCVTF_D64_float2int
- (b'\xe1\x01b\x9e', 'LLIL_INTRINSIC([d1],vcvtd_f64_s64,[LLIL_REG.q(x15)])')
+ # ucvtf d18, w3, #0x1f UCVTF_D32_float2fix
+ (b'\x72\x84\x43\x1E', 'LLIL_INTRINSIC([d18],vcvtd_n_f64_u32,[LLIL_REG.d(w3),LLIL_CONST(31)])'),
+ # ucvtf d25, w5, #0x1c UCVTF_D32_float2fix
+ (b'\xB9\x90\x43\x1E', 'LLIL_INTRINSIC([d25],vcvtd_n_f64_u32,[LLIL_REG.d(w5),LLIL_CONST(28)])'),
+ # ucvtf d0, w7 UCVTF_D32_float2int
+ (b'\xE0\x00\x63\x1E', 'LLIL_SET_REG.q(d0,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.d(w7))))'),
+ # ucvtf d19, w25 UCVTF_D32_float2int
+ (b'\x33\x03\x63\x1E', 'LLIL_SET_REG.q(d19,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.d(w25))))'),
+ # ucvtf d19, x26, #0x23 UCVTF_D64_float2fix
+ (b'\x53\x77\x43\x9E', 'LLIL_INTRINSIC([d19],vcvtd_n_f64_u64,[LLIL_REG.q(x26),LLIL_CONST(35)])'),
+ # ucvtf d9, x12, #0x38 UCVTF_D64_float2fix
+ (b'\x89\x21\x43\x9E', 'LLIL_INTRINSIC([d9],vcvtd_n_f64_u64,[LLIL_REG.q(x12),LLIL_CONST(56)])'),
+ # ucvtf d30, x19 UCVTF_D64_float2int
+ (b'\x7E\x02\x63\x9E', 'LLIL_SET_REG.q(d30,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.q(x19))))'),
+ # ucvtf d10, x28 UCVTF_D64_float2int
+ (b'\x8A\x03\x63\x9E', 'LLIL_SET_REG.q(d10,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.q(x28))))'),
+ # ucvtf h3, w29, #0x13 UCVTF_H32_float2fix
+ (b'\xA3\xB7\xC3\x1E', 'LLIL_INTRINSIC([h3],vcvth_n_f16_u32,[LLIL_REG.d(w29),LLIL_CONST(19)])'),
+ # ucvtf h16, w7, #0x1d UCVTF_H32_float2fix
+ (b'\xF0\x8C\xC3\x1E', 'LLIL_INTRINSIC([h16],vcvth_n_f16_u32,[LLIL_REG.d(w7),LLIL_CONST(29)])'),
+ # ucvtf h5, w12 UCVTF_H32_float2int
+ (b'\x85\x01\xE3\x1E', 'LLIL_SET_REG.w(h5,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.d(w12))))'),
+ # ucvtf h30, w15 UCVTF_H32_float2int
+ (b'\xFE\x01\xE3\x1E', 'LLIL_SET_REG.w(h30,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.d(w15))))'),
+ # ucvtf h5, x13, #0x16 UCVTF_H64_float2fix
+ (b'\xA5\xA9\xC3\x9E', 'LLIL_INTRINSIC([h5],vcvth_n_f16_u64,[LLIL_REG.q(x13),LLIL_CONST(22)])'),
+ # ucvtf h12, x18, #0x1c UCVTF_H64_float2fix
+ (b'\x4C\x92\xC3\x9E', 'LLIL_INTRINSIC([h12],vcvth_n_f16_u64,[LLIL_REG.q(x18),LLIL_CONST(28)])'),
+ # ucvtf h3, x2 UCVTF_H64_float2int
+ (b'\x43\x00\xE3\x9E', 'LLIL_SET_REG.w(h3,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.q(x2))))'),
+ # ucvtf h18, x21 UCVTF_H64_float2int
+ (b'\xB2\x02\xE3\x9E', 'LLIL_SET_REG.w(h18,LLIL_INT_TO_FLOAT.w(LLIL_ZX.w(LLIL_REG.q(x21))))'),
+ # ucvtf s1, w22, #0x1 UCVTF_S32_float2fix
+ (b'\xC1\xFE\x03\x1E', 'LLIL_INTRINSIC([s1],vcvts_n_f32_u32,[LLIL_REG.d(w22),LLIL_CONST(1)])'),
+ # ucvtf s6, w24, #0x8 UCVTF_S32_float2fix
+ (b'\x06\xE3\x03\x1E', 'LLIL_INTRINSIC([s6],vcvts_n_f32_u32,[LLIL_REG.d(w24),LLIL_CONST(8)])'),
+ # ucvtf s29, w24 UCVTF_S32_float2int
+ (b'\x1D\x03\x23\x1E', 'LLIL_SET_REG.d(s29,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.d(w24))))'),
+ # ucvtf s6, w7 UCVTF_S32_float2int
+ (b'\xE6\x00\x23\x1E', 'LLIL_SET_REG.d(s6,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.d(w7))))'),
+ # ucvtf s2, x27, #0xf UCVTF_S64_float2fix
+ (b'\x62\xC7\x03\x9E', 'LLIL_INTRINSIC([s2],vcvts_n_f32_u64,[LLIL_REG.q(x27),LLIL_CONST(15)])'),
+ # ucvtf s8, x27, #0xf UCVTF_S64_float2fix
+ (b'\x68\xC7\x03\x9E', 'LLIL_INTRINSIC([s8],vcvts_n_f32_u64,[LLIL_REG.q(x27),LLIL_CONST(15)])'),
+ # ucvtf s29, x5 UCVTF_S64_float2int
+ (b'\xBD\x00\x23\x9E', 'LLIL_SET_REG.d(s29,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.q(x5))))'),
+ # ucvtf s23, x8 UCVTF_S64_float2int
+ (b'\x17\x01\x23\x9E', 'LLIL_SET_REG.d(s23,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.q(x8))))'),
+ # ucvtf v11.2d, v11.2d UCVTF_asimdmisc_R
+ (b'\x6B\xD9\x61\x6E', 'LLIL_INTRINSIC([v11],vcvtq_f64_u64,[LLIL_REG.o(v11)])'),
+ # ucvtf v15.2s, v30.2s UCVTF_asimdmisc_R
+ (b'\xCF\xDB\x21\x2E', 'LLIL_INTRINSIC([v15],vcvt_f32_u32,[LLIL_REG.o(v30)])'),
+ # ucvtf v15.2s, v14.2s, #0x19 UCVTF_asimdshf_C
+ (b'\xCF\xE5\x27\x2F', 'LLIL_INTRINSIC([v15],vcvt_n_f32_u32,[LLIL_REG.o(v14),LLIL_CONST(25)])'),
+ # ucvtf v13.2s, v6.2s, #0x1 UCVTF_asimdshf_C
+ (b'\xCD\xE4\x3F\x2F', 'LLIL_INTRINSIC([v13],vcvt_n_f32_u32,[LLIL_REG.o(v6),LLIL_CONST(1)])'),
+ # ucvtf s16, s7 UCVTF_asisdmisc_R
+ (b'\xF0\xD8\x21\x7E', 'LLIL_SET_REG.d(s16,LLIL_INT_TO_FLOAT.d(LLIL_ZX.d(LLIL_REG.d(s7))))'),
+ # ucvtf d26, d30 UCVTF_asisdmisc_R
+ (b'\xDA\xDB\x61\x7E', 'LLIL_SET_REG.q(d26,LLIL_INT_TO_FLOAT.q(LLIL_ZX.q(LLIL_REG.q(d30))))'),
+ # ucvtf d20, d1, #0x2a UCVTF_asisdshf_C
+ (b'\x34\xE4\x56\x7F', 'LLIL_INTRINSIC([d20],vcvt_n_f64_u64,[LLIL_REG.q(d1),LLIL_CONST(42)])'),
+ # ucvtf h13, h28, #0x4 UCVTF_asisdshf_C
+ (b'\x8D\xE7\x1C\x7F', 'LLIL_INTRINSIC([h13],vcvt_n_f64_u64,[LLIL_REG.w(h28),LLIL_CONST(4)])'),
]
tests_ret = [
@@ -631,21 +698,21 @@ tests_clrex = [
tests_xtn_xtn2 = [
# xtn v17.4h, v24.4s XTN_ASIMDMISC_N
- (b'\x11\x2B\x61\x0E', 'LLIL_INTRINSIC([v17],vmovn_u32,[LLIL_REG.o(v24)])'),
+ (b'\x11\x2B\x61\x0E', 'LLIL_INTRINSIC([v17],vmovn_s32,[LLIL_REG.o(v24)])'),
# xtn v13.4h, v30.4s XTN_ASIMDMISC_N
- (b'\xCD\x2B\x61\x0E', 'LLIL_INTRINSIC([v13],vmovn_u32,[LLIL_REG.o(v30)])'),
+ (b'\xCD\x2B\x61\x0E', 'LLIL_INTRINSIC([v13],vmovn_s32,[LLIL_REG.o(v30)])'),
# xtn v30.4h, v20.4s XTN_ASIMDMISC_N
- (b'\x9E\x2A\x61\x0E', 'LLIL_INTRINSIC([v30],vmovn_u32,[LLIL_REG.o(v20)])'),
+ (b'\x9E\x2A\x61\x0E', 'LLIL_INTRINSIC([v30],vmovn_s32,[LLIL_REG.o(v20)])'),
# xtn v13.2s, v10.2d XTN_ASIMDMISC_N
- (b'\x4D\x29\xA1\x0E', 'LLIL_INTRINSIC([v13],vmovn_u64,[LLIL_REG.o(v10)])'),
+ (b'\x4D\x29\xA1\x0E', 'LLIL_INTRINSIC([v13],vmovn_s64,[LLIL_REG.o(v10)])'),
# xtn2 v27.8h, v19.4s XTN_ASIMDMISC_N
- (b'\x7B\x2A\x61\x4E', 'LLIL_INTRINSIC([v27],vmovn_high_u32,[LLIL_REG.o(v19)])'),
+ (b'\x7B\x2A\x61\x4E', 'LLIL_INTRINSIC([v27],vmovn_high_s32,[LLIL_REG.o(v19)])'),
# xtn2 v26.4s, v7.2d XTN_ASIMDMISC_N
- (b'\xFA\x28\xA1\x4E', 'LLIL_INTRINSIC([v26],vmovn_high_u64,[LLIL_REG.o(v7)])'),
+ (b'\xFA\x28\xA1\x4E', 'LLIL_INTRINSIC([v26],vmovn_high_s64,[LLIL_REG.o(v7)])'),
# xtn2 v3.4s, v22.2d XTN_ASIMDMISC_N
- (b'\xC3\x2A\xA1\x4E', 'LLIL_INTRINSIC([v3],vmovn_high_u64,[LLIL_REG.o(v22)])'),
+ (b'\xC3\x2A\xA1\x4E', 'LLIL_INTRINSIC([v3],vmovn_high_s64,[LLIL_REG.o(v22)])'),
# xtn2 v13.8h, v23.4s XTN_ASIMDMISC_N
- (b'\xED\x2A\x61\x4E', 'LLIL_INTRINSIC([v13],vmovn_high_u32,[LLIL_REG.o(v23)])'),
+ (b'\xED\x2A\x61\x4E', 'LLIL_INTRINSIC([v13],vmovn_high_s32,[LLIL_REG.o(v23)])'),
]
tests_dc = [
@@ -659,692 +726,692 @@ tests_dc = [
(b'\x52\x7E\x08\xD5', 'LLIL_INTRINSIC([],__dc,[LLIL_REG.q(x18)])'),
]
-tests_uxtl_uxtl2 = [
- # uxtl v2.2d, v8.2s UXTL_USHLL_ASIMDSHF_L
- (b'\x02\xA5\x20\x2F', 'LLIL_SET_REG.q(v2.d[0],LLIL_REG.d(v8.s[0]));' + \
- ' LLIL_SET_REG.q(v2.d[1],LLIL_REG.d(v8.s[1]))'),
- # uxtl v6.8h, v1.8b UXTL_USHLL_ASIMDSHF_L
- (b'\x26\xA4\x08\x2F', 'LLIL_SET_REG.w(v6.h[0],LLIL_REG.b(v1.b[0]));' + \
- ' LLIL_SET_REG.w(v6.h[1],LLIL_REG.b(v1.b[1]));' + \
- ' LLIL_SET_REG.w(v6.h[2],LLIL_REG.b(v1.b[2]));' + \
- ' LLIL_SET_REG.w(v6.h[3],LLIL_REG.b(v1.b[3]));' + \
- ' LLIL_SET_REG.w(v6.h[4],LLIL_REG.b(v1.b[4]));' + \
- ' LLIL_SET_REG.w(v6.h[5],LLIL_REG.b(v1.b[5]));' + \
- ' LLIL_SET_REG.w(v6.h[6],LLIL_REG.b(v1.b[6]));' + \
- ' LLIL_SET_REG.w(v6.h[7],LLIL_REG.b(v1.b[7]))'),
- # uxtl v11.8h, v29.8b UXTL_USHLL_ASIMDSHF_L
- (b'\xAB\xA7\x08\x2F', 'LLIL_SET_REG.w(v11.h[0],LLIL_REG.b(v29.b[0]));' + \
- ' LLIL_SET_REG.w(v11.h[1],LLIL_REG.b(v29.b[1]));' + \
- ' LLIL_SET_REG.w(v11.h[2],LLIL_REG.b(v29.b[2]));' + \
- ' LLIL_SET_REG.w(v11.h[3],LLIL_REG.b(v29.b[3]));' + \
- ' LLIL_SET_REG.w(v11.h[4],LLIL_REG.b(v29.b[4]));' + \
- ' LLIL_SET_REG.w(v11.h[5],LLIL_REG.b(v29.b[5]));' + \
- ' LLIL_SET_REG.w(v11.h[6],LLIL_REG.b(v29.b[6]));' + \
- ' LLIL_SET_REG.w(v11.h[7],LLIL_REG.b(v29.b[7]))'),
- # uxtl v9.2d, v8.2s UXTL_USHLL_ASIMDSHF_L
- (b'\x09\xA5\x20\x2F', 'LLIL_SET_REG.q(v9.d[0],LLIL_REG.d(v8.s[0]));' + \
- ' LLIL_SET_REG.q(v9.d[1],LLIL_REG.d(v8.s[1]))'),
- # uxtl2 v19.2d, v20.4s UXTL_USHLL_ASIMDSHF_L
- (b'\x93\xA6\x20\x6F', 'LLIL_SET_REG.q(v19.d[0],LLIL_REG.d(v20.s[2]));' + \
- ' LLIL_SET_REG.q(v19.d[1],LLIL_REG.d(v20.s[3]))'),
- # uxtl2 v11.2d, v18.4s UXTL_USHLL_ASIMDSHF_L
- (b'\x4B\xA6\x20\x6F', 'LLIL_SET_REG.q(v11.d[0],LLIL_REG.d(v18.s[2]));' + \
- ' LLIL_SET_REG.q(v11.d[1],LLIL_REG.d(v18.s[3]))'),
- # uxtl2 v11.8h, v10.16b UXTL_USHLL_ASIMDSHF_L
- (b'\x4B\xA5\x08\x6F', 'LLIL_SET_REG.w(v11.h[0],LLIL_REG.b(v10.b[8]));' + \
- ' LLIL_SET_REG.w(v11.h[1],LLIL_REG.b(v10.b[9]));' + \
- ' LLIL_SET_REG.w(v11.h[2],LLIL_REG.b(v10.b[10]));' + \
- ' LLIL_SET_REG.w(v11.h[3],LLIL_REG.b(v10.b[11]));' + \
- ' LLIL_SET_REG.w(v11.h[4],LLIL_REG.b(v10.b[12]));' + \
- ' LLIL_SET_REG.w(v11.h[5],LLIL_REG.b(v10.b[13]));' + \
- ' LLIL_SET_REG.w(v11.h[6],LLIL_REG.b(v10.b[14]));' + \
- ' LLIL_SET_REG.w(v11.h[7],LLIL_REG.b(v10.b[15]))'),
- # uxtl2 v0.4s, v13.8h UXTL_USHLL_ASIMDSHF_L
- (b'\xA0\xA5\x10\x6F', 'LLIL_SET_REG.d(v0.s[0],LLIL_REG.w(v13.h[4]));' + \
- ' LLIL_SET_REG.d(v0.s[1],LLIL_REG.w(v13.h[5]));' + \
- ' LLIL_SET_REG.d(v0.s[2],LLIL_REG.w(v13.h[6]));' + \
- ' LLIL_SET_REG.d(v0.s[3],LLIL_REG.w(v13.h[7]))'),
-]
+# tests_uxtl_uxtl2 = [
+# # uxtl v2.2d, v8.2s UXTL_USHLL_ASIMDSHF_L
+# (b'\x02\xA5\x20\x2F', 'LLIL_SET_REG.q(v2.d[0],LLIL_REG.d(v8.s[0]));' + \
+# ' LLIL_SET_REG.q(v2.d[1],LLIL_REG.d(v8.s[1]))'),
+# # uxtl v6.8h, v1.8b UXTL_USHLL_ASIMDSHF_L
+# (b'\x26\xA4\x08\x2F', 'LLIL_SET_REG.w(v6.h[0],LLIL_REG.b(v1.b[0]));' + \
+# ' LLIL_SET_REG.w(v6.h[1],LLIL_REG.b(v1.b[1]));' + \
+# ' LLIL_SET_REG.w(v6.h[2],LLIL_REG.b(v1.b[2]));' + \
+# ' LLIL_SET_REG.w(v6.h[3],LLIL_REG.b(v1.b[3]));' + \
+# ' LLIL_SET_REG.w(v6.h[4],LLIL_REG.b(v1.b[4]));' + \
+# ' LLIL_SET_REG.w(v6.h[5],LLIL_REG.b(v1.b[5]));' + \
+# ' LLIL_SET_REG.w(v6.h[6],LLIL_REG.b(v1.b[6]));' + \
+# ' LLIL_SET_REG.w(v6.h[7],LLIL_REG.b(v1.b[7]))'),
+# # uxtl v11.8h, v29.8b UXTL_USHLL_ASIMDSHF_L
+# (b'\xAB\xA7\x08\x2F', 'LLIL_SET_REG.w(v11.h[0],LLIL_REG.b(v29.b[0]));' + \
+# ' LLIL_SET_REG.w(v11.h[1],LLIL_REG.b(v29.b[1]));' + \
+# ' LLIL_SET_REG.w(v11.h[2],LLIL_REG.b(v29.b[2]));' + \
+# ' LLIL_SET_REG.w(v11.h[3],LLIL_REG.b(v29.b[3]));' + \
+# ' LLIL_SET_REG.w(v11.h[4],LLIL_REG.b(v29.b[4]));' + \
+# ' LLIL_SET_REG.w(v11.h[5],LLIL_REG.b(v29.b[5]));' + \
+# ' LLIL_SET_REG.w(v11.h[6],LLIL_REG.b(v29.b[6]));' + \
+# ' LLIL_SET_REG.w(v11.h[7],LLIL_REG.b(v29.b[7]))'),
+# # uxtl v9.2d, v8.2s UXTL_USHLL_ASIMDSHF_L
+# (b'\x09\xA5\x20\x2F', 'LLIL_SET_REG.q(v9.d[0],LLIL_REG.d(v8.s[0]));' + \
+# ' LLIL_SET_REG.q(v9.d[1],LLIL_REG.d(v8.s[1]))'),
+# # uxtl2 v19.2d, v20.4s UXTL_USHLL_ASIMDSHF_L
+# (b'\x93\xA6\x20\x6F', 'LLIL_SET_REG.q(v19.d[0],LLIL_REG.d(v20.s[2]));' + \
+# ' LLIL_SET_REG.q(v19.d[1],LLIL_REG.d(v20.s[3]))'),
+# # uxtl2 v11.2d, v18.4s UXTL_USHLL_ASIMDSHF_L
+# (b'\x4B\xA6\x20\x6F', 'LLIL_SET_REG.q(v11.d[0],LLIL_REG.d(v18.s[2]));' + \
+# ' LLIL_SET_REG.q(v11.d[1],LLIL_REG.d(v18.s[3]))'),
+# # uxtl2 v11.8h, v10.16b UXTL_USHLL_ASIMDSHF_L
+# (b'\x4B\xA5\x08\x6F', 'LLIL_SET_REG.w(v11.h[0],LLIL_REG.b(v10.b[8]));' + \
+# ' LLIL_SET_REG.w(v11.h[1],LLIL_REG.b(v10.b[9]));' + \
+# ' LLIL_SET_REG.w(v11.h[2],LLIL_REG.b(v10.b[10]));' + \
+# ' LLIL_SET_REG.w(v11.h[3],LLIL_REG.b(v10.b[11]));' + \
+# ' LLIL_SET_REG.w(v11.h[4],LLIL_REG.b(v10.b[12]));' + \
+# ' LLIL_SET_REG.w(v11.h[5],LLIL_REG.b(v10.b[13]));' + \
+# ' LLIL_SET_REG.w(v11.h[6],LLIL_REG.b(v10.b[14]));' + \
+# ' LLIL_SET_REG.w(v11.h[7],LLIL_REG.b(v10.b[15]))'),
+# # uxtl2 v0.4s, v13.8h UXTL_USHLL_ASIMDSHF_L
+# (b'\xA0\xA5\x10\x6F', 'LLIL_SET_REG.d(v0.s[0],LLIL_REG.w(v13.h[4]));' + \
+# ' LLIL_SET_REG.d(v0.s[1],LLIL_REG.w(v13.h[5]));' + \
+# ' LLIL_SET_REG.d(v0.s[2],LLIL_REG.w(v13.h[6]));' + \
+# ' LLIL_SET_REG.d(v0.s[3],LLIL_REG.w(v13.h[7]))'),
+# ]
tests_ldadd = [
- # ldaddab w13, w7, [x30] LDADDAB_32_memop
- (b'\xC7\x03\xAD\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x30))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x30),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w13)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w7,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddab w0, w22, [x28] LDADDAB_32_memop
- (b'\x96\x03\xA0\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x28))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x28),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w0)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w22,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddab w18, w23, [x18] LDADDAB_32_memop
- (b'\x57\x02\xB2\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x18))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x18),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w18)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w23,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddab w11, w18, [x19] LDADDAB_32_memop
- (b'\x72\x02\xAB\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x19))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x19),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w11)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w18,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddab w26, w2, [x22] LDADDAB_32_memop
- (b'\xC2\x02\xBA\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x22))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x22),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w26)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w2,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddab w15, w8, [x2] LDADDAB_32_memop
- (b'\x48\x00\xAF\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x2))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x2),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w15)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w8,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddab w10, w8, [x17] LDADDAB_32_memop
- (b'\x28\x02\xAA\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x17))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x17),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w10)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w8,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddab w12, w18, [x9] LDADDAB_32_memop
- (b'\x32\x01\xAC\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x9))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x9),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w12)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w18,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddah w9, w16, [x11] LDADDAH_32_memop
- (b'\x70\x01\xA9\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x11))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x11),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w9)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w16,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddah w14, w16, [x28] LDADDAH_32_memop
- (b'\x90\x03\xAE\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x28))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x28),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w14)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w16,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddah w15, w30, [x21] LDADDAH_32_memop
- (b'\xBE\x02\xAF\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x21))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x21),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w15)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w30,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddah w17, w23, [x22] LDADDAH_32_memop
- (b'\xD7\x02\xB1\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x22))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x22),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w17)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w23,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddah w7, w22, [x18] LDADDAH_32_memop
- (b'\x56\x02\xA7\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x18))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x18),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w7)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w22,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddah w4, w6, [x9] LDADDAH_32_memop
- (b'\x26\x01\xA4\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x9))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x9),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w4)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w6,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddah w8, w29, [x16] LDADDAH_32_memop
- (b'\x1D\x02\xA8\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x16))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x16),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w8)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w29,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddah w11, w28, [x8] LDADDAH_32_memop
- (b'\x1C\x01\xAB\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x8))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x8),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w11)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w28,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddalb w14, w2, [x14] LDADDALB_32_memop
- (b'\xC2\x01\xEE\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x14))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x14),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w14)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w2,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddalb w0, w24, [x16] LDADDALB_32_memop
- (b'\x18\x02\xE0\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x16))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x16),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w0)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w24,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddalb w14, w18, [x24] LDADDALB_32_memop
- (b'\x12\x03\xEE\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x24))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x24),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w14)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w18,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddalb w25, w28, [x24] LDADDALB_32_memop
- (b'\x1C\x03\xF9\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x24))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x24),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w25)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w28,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddalb w25, w19, [sp] LDADDALB_32_memop
- (b'\xF3\x03\xF9\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(sp))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(sp),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w25)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w19,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddalb w10, w15, [x24] LDADDALB_32_memop
- (b'\x0F\x03\xEA\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x24))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x24),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w10)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w15,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddalb w10, w10, [x10] LDADDALB_32_memop
- (b'\x4A\x01\xEA\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x10))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x10),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w10)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w10,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddalb w18, w12, [x28] LDADDALB_32_memop
- (b'\x8C\x03\xF2\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x28))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x28),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w18)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w12,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddalh w21, w30, [sp] LDADDALH_32_memop
- (b'\xFE\x03\xF5\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(sp))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(sp),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w21)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w30,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddalh w24, wzr, [x19] LDADDALH_32_memop
- (b'\x7F\x02\xF8\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x19))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x19),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w24)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddalh w27, w23, [x23] LDADDALH_32_memop
- (b'\xF7\x02\xFB\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x23))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x23),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w27)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w23,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddalh w28, w30, [x15] LDADDALH_32_memop
- (b'\xFE\x01\xFC\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x15))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x15),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w28)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w30,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddalh w5, w9, [x2] LDADDALH_32_memop
- (b'\x49\x00\xE5\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x2))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x2),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w5)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w9,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddalh w9, w29, [x1] LDADDALH_32_memop
- (b'\x3D\x00\xE9\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x1))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x1),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w9)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w29,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddalh w16, w14, [x11] LDADDALH_32_memop
- (b'\x6E\x01\xF0\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x11))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x11),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w16)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w14,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddalh w14, wzr, [x21] LDADDALH_32_memop
- (b'\xBF\x02\xEE\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x21))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x21),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w14)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddal w17, w13, [x7] LDADDAL_32_memop
- (b'\xED\x00\xF1\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x7))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x7),LLIL_ADD.d(LLIL_REG.d(w17),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w13,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddal w7, w27, [x3] LDADDAL_32_memop
- (b'\x7B\x00\xE7\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x3))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x3),LLIL_ADD.d(LLIL_REG.d(w7),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w27,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddal w21, w5, [x0] LDADDAL_32_memop
- (b'\x05\x00\xF5\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x0))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x0),LLIL_ADD.d(LLIL_REG.d(w21),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w5,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddal w2, w28, [x7] LDADDAL_32_memop
- (b'\xFC\x00\xE2\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x7))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x7),LLIL_ADD.d(LLIL_REG.d(w2),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w28,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddal w0, w21, [x16] LDADDAL_32_memop
- (b'\x15\x02\xE0\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x16))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x16),LLIL_ADD.d(LLIL_REG.d(w0),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w21,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddal wzr, w16, [x11] LDADDAL_32_memop
- (b'\x70\x01\xFF\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x11))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x11),LLIL_ADD.d(LLIL_CONST.d(0x0),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w16,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddal w29, w16, [x10] LDADDAL_32_memop
- (b'\x50\x01\xFD\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x10))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x10),LLIL_ADD.d(LLIL_REG.d(w29),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w16,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddal w22, w30, [x12] LDADDAL_32_memop
- (b'\x9E\x01\xF6\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x12))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x12),LLIL_ADD.d(LLIL_REG.d(w22),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w30,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddal x0, x5, [x1] LDADDAL_64_memop
- (b'\x25\x00\xE0\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x1))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x1),LLIL_ADD.q(LLIL_REG.q(x0),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x5,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldaddal x6, x13, [x13] LDADDAL_64_memop
- (b'\xAD\x01\xE6\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x13))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x13),LLIL_ADD.q(LLIL_REG.q(x6),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x13,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldaddal x10, x4, [x18] LDADDAL_64_memop
- (b'\x44\x02\xEA\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x18))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x18),LLIL_ADD.q(LLIL_REG.q(x10),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x4,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldaddal x12, x2, [x5] LDADDAL_64_memop
- (b'\xA2\x00\xEC\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x5))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x5),LLIL_ADD.q(LLIL_REG.q(x12),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x2,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldaddal x11, x19, [x17] LDADDAL_64_memop
- (b'\x33\x02\xEB\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x17))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x17),LLIL_ADD.q(LLIL_REG.q(x11),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x19,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldaddal x12, x28, [x23] LDADDAL_64_memop
- (b'\xFC\x02\xEC\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x23))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x23),LLIL_ADD.q(LLIL_REG.q(x12),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x28,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldaddal x6, x7, [x22] LDADDAL_64_memop
- (b'\xC7\x02\xE6\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x22))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x22),LLIL_ADD.q(LLIL_REG.q(x6),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x7,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldaddal x10, x21, [x8] LDADDAL_64_memop
- (b'\x15\x01\xEA\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x8))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x8),LLIL_ADD.q(LLIL_REG.q(x10),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x21,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadda w9, w4, [x4] LDADDA_32_memop
- (b'\x84\x00\xA9\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x4))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x4),LLIL_ADD.d(LLIL_REG.d(w9),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w4,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadda w17, w29, [x27] LDADDA_32_memop
- (b'\x7D\x03\xB1\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x27))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x27),LLIL_ADD.d(LLIL_REG.d(w17),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w29,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadda w5, w9, [x7] LDADDA_32_memop
- (b'\xE9\x00\xA5\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x7))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x7),LLIL_ADD.d(LLIL_REG.d(w5),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w9,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadda w12, w22, [x25] LDADDA_32_memop
- (b'\x36\x03\xAC\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x25))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x25),LLIL_ADD.d(LLIL_REG.d(w12),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w22,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadda w19, w12, [x11] LDADDA_32_memop
- (b'\x6C\x01\xB3\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x11))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x11),LLIL_ADD.d(LLIL_REG.d(w19),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w12,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadda w16, w14, [x10] LDADDA_32_memop
- (b'\x4E\x01\xB0\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x10))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x10),LLIL_ADD.d(LLIL_REG.d(w16),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w14,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadda w21, w5, [x4] LDADDA_32_memop
- (b'\x85\x00\xB5\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x4))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x4),LLIL_ADD.d(LLIL_REG.d(w21),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w5,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadda w22, w14, [x16] LDADDA_32_memop
- (b'\x0E\x02\xB6\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x16))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x16),LLIL_ADD.d(LLIL_REG.d(w22),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w14,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadda x5, x9, [x22] LDADDA_64_memop
- (b'\xC9\x02\xA5\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x22))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x22),LLIL_ADD.q(LLIL_REG.q(x5),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x9,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadda x6, x2, [x4] LDADDA_64_memop
- (b'\x82\x00\xA6\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x4))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x4),LLIL_ADD.q(LLIL_REG.q(x6),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x2,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadda x0, x25, [x24] LDADDA_64_memop
- (b'\x19\x03\xA0\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x24))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x24),LLIL_ADD.q(LLIL_REG.q(x0),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x25,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadda x1, x20, [sp] LDADDA_64_memop
- (b'\xF4\x03\xA1\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(sp))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(sp),LLIL_ADD.q(LLIL_REG.q(x1),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x20,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadda x27, x16, [x20] LDADDA_64_memop
- (b'\x90\x02\xBB\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x20))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x20),LLIL_ADD.q(LLIL_REG.q(x27),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x16,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadda xzr, x15, [x16] LDADDA_64_memop
- (b'\x0F\x02\xBF\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x16))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x16),LLIL_ADD.q(LLIL_CONST.q(0x0),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x15,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadda x9, x8, [x1] LDADDA_64_memop
- (b'\x28\x00\xA9\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x1))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x1),LLIL_ADD.q(LLIL_REG.q(x9),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x8,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadda x18, x23, [x17] LDADDA_64_memop
- (b'\x37\x02\xB2\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x17))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x17),LLIL_ADD.q(LLIL_REG.q(x18),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x23,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldaddb w16, w24, [x10] LDADDB_32_memop
- (b'\x58\x01\x30\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x10))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x10),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w16)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w24,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddb w4, w0, [x27] LDADDB_32_memop
- (b'\x60\x03\x24\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x27))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x27),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w4)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w0,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddb w9, w7, [x21] LDADDB_32_memop
- (b'\xA7\x02\x29\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x21))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x21),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w9)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w7,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddb w8, w30, [x11] LDADDB_32_memop
- (b'\x7E\x01\x28\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x11))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x11),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w8)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w30,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddb w4, w13, [x19] LDADDB_32_memop
- (b'\x6D\x02\x24\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x19))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x19),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w4)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w13,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddb w2, w29, [x14] LDADDB_32_memop
- (b'\xDD\x01\x22\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x14))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x14),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w2)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w29,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddb w4, w22, [x27] LDADDB_32_memop
- (b'\x76\x03\x24\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x27))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x27),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w4)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w22,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddb w8, w29, [x29] LDADDB_32_memop
- (b'\xBD\x03\x28\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x29))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x29),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w8)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w29,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddh w30, w28, [x27] LDADDH_32_memop
- (b'\x7C\x03\x3E\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x27))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x27),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w30)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w28,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddh w20, w5, [x24] LDADDH_32_memop
- (b'\x05\x03\x34\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x24))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x24),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w20)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w5,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddh w7, w13, [x28] LDADDH_32_memop
- (b'\x8D\x03\x27\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x28))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x28),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w7)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w13,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddh w18, w12, [x17] LDADDH_32_memop
- (b'\x2C\x02\x32\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x17))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x17),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w18)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w12,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddh w17, w3, [x4] LDADDH_32_memop
- (b'\x83\x00\x31\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x4))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x4),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w17)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w3,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddh w8, w9, [x12] LDADDH_32_memop
- (b'\x89\x01\x28\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x12))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x12),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w8)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w9,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddh w8, w7, [x22] LDADDH_32_memop
- (b'\xC7\x02\x28\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x22))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x22),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w8)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w7,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddh w5, w23, [x30] LDADDH_32_memop
- (b'\xD7\x03\x25\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x30))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x30),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w5)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w23,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddlb w9, w24, [x5] LDADDLB_32_memop
- (b'\xB8\x00\x69\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x5))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x5),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w9)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w24,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddlb w3, w9, [x11] LDADDLB_32_memop
- (b'\x69\x01\x63\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x11))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x11),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w3)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w9,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddlb w29, w7, [x27] LDADDLB_32_memop
- (b'\x67\x03\x7D\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x27))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x27),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w29)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w7,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddlb w8, w4, [x11] LDADDLB_32_memop
- (b'\x64\x01\x68\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x11))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x11),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w8)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w4,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddlb w30, w2, [x13] LDADDLB_32_memop
- (b'\xA2\x01\x7E\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x13))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x13),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w30)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w2,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddlb w19, w11, [x24] LDADDLB_32_memop
- (b'\x0B\x03\x73\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x24))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x24),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w19)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w11,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddlb w9, w15, [x17] LDADDLB_32_memop
- (b'\x2F\x02\x69\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x17))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x17),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w9)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w15,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddlb w20, w7, [x15] LDADDLB_32_memop
- (b'\xE7\x01\x74\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x15))));' + \
- ' LLIL_STORE.b(LLIL_REG.q(x15),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w20)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
- ' LLIL_SET_REG.d(w7,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
- # ldaddlh w17, w18, [x1] LDADDLH_32_memop
- (b'\x32\x00\x71\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x1))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x1),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w17)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w18,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddlh w16, w8, [x1] LDADDLH_32_memop
- (b'\x28\x00\x70\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x1))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x1),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w16)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w8,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddlh w18, w1, [x28] LDADDLH_32_memop
- (b'\x81\x03\x72\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x28))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x28),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w18)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w1,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddlh w11, w8, [x25] LDADDLH_32_memop
- (b'\x28\x03\x6B\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x25))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x25),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w11)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w8,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddlh w11, w7, [x1] LDADDLH_32_memop
- (b'\x27\x00\x6B\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x1))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x1),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w11)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w7,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddlh w21, w8, [x28] LDADDLH_32_memop
- (b'\x88\x03\x75\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x28))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x28),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w21)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w8,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddlh w16, w21, [x2] LDADDLH_32_memop
- (b'\x55\x00\x70\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x2))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x2),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w16)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w21,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddlh w6, w14, [x25] LDADDLH_32_memop
- (b'\x2E\x03\x66\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x25))));' + \
- ' LLIL_STORE.w(LLIL_REG.q(x25),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w6)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
- ' LLIL_SET_REG.d(w14,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
- # ldaddl w8, w6, [x4] LDADDL_32_memop
- (b'\x86\x00\x68\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x4))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x4),LLIL_ADD.d(LLIL_REG.d(w8),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w6,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddl w15, w23, [x28] LDADDL_32_memop
- (b'\x97\x03\x6F\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x28))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x28),LLIL_ADD.d(LLIL_REG.d(w15),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w23,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddl w18, w7, [x0] LDADDL_32_memop
- (b'\x07\x00\x72\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x0))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x0),LLIL_ADD.d(LLIL_REG.d(w18),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w7,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddl w11, w17, [x25] LDADDL_32_memop
- (b'\x31\x03\x6B\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x25))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x25),LLIL_ADD.d(LLIL_REG.d(w11),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w17,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddl w14, w3, [x8] LDADDL_32_memop
- (b'\x03\x01\x6E\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x8))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x8),LLIL_ADD.d(LLIL_REG.d(w14),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w3,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddl w15, w18, [x12] LDADDL_32_memop
- (b'\x92\x01\x6F\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x12))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x12),LLIL_ADD.d(LLIL_REG.d(w15),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w18,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddl w19, w5, [x18] LDADDL_32_memop
- (b'\x45\x02\x73\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x18))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x18),LLIL_ADD.d(LLIL_REG.d(w19),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w5,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddl w21, w24, [x7] LDADDL_32_memop
- (b'\xF8\x00\x75\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x7))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x7),LLIL_ADD.d(LLIL_REG.d(w21),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w24,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldaddl x19, x17, [x26] LDADDL_64_memop
- (b'\x51\x03\x73\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x26))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x26),LLIL_ADD.q(LLIL_REG.q(x19),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x17,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldaddl x4, x17, [x20] LDADDL_64_memop
- (b'\x91\x02\x64\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x20))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x20),LLIL_ADD.q(LLIL_REG.q(x4),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x17,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldaddl x23, x22, [x1] LDADDL_64_memop
- (b'\x36\x00\x77\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x1))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x1),LLIL_ADD.q(LLIL_REG.q(x23),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x22,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldaddl x9, x6, [x30] LDADDL_64_memop
- (b'\xC6\x03\x69\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x30))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x30),LLIL_ADD.q(LLIL_REG.q(x9),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x6,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldaddl x2, x20, [x0] LDADDL_64_memop
- (b'\x14\x00\x62\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x0))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x0),LLIL_ADD.q(LLIL_REG.q(x2),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x20,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldaddl x1, x19, [x26] LDADDL_64_memop
- (b'\x53\x03\x61\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x26))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x26),LLIL_ADD.q(LLIL_REG.q(x1),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x19,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldaddl x22, x30, [x7] LDADDL_64_memop
- (b'\xFE\x00\x76\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x7))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x7),LLIL_ADD.q(LLIL_REG.q(x22),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x30,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldaddl x12, x9, [x15] LDADDL_64_memop
- (b'\xE9\x01\x6C\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x15))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x15),LLIL_ADD.q(LLIL_REG.q(x12),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x9,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadd w24, w11, [x29] LDADD_32_memop
- (b'\xAB\x03\x38\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x29))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x29),LLIL_ADD.d(LLIL_REG.d(w24),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w11,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadd w17, w22, [x12] LDADD_32_memop
- (b'\x96\x01\x31\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x12))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x12),LLIL_ADD.d(LLIL_REG.d(w17),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w22,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadd w24, w16, [x5] LDADD_32_memop
- (b'\xB0\x00\x38\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x5))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x5),LLIL_ADD.d(LLIL_REG.d(w24),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w16,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadd w1, w26, [x16] LDADD_32_memop
- (b'\x1A\x02\x21\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x16))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x16),LLIL_ADD.d(LLIL_REG.d(w1),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w26,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadd w18, w4, [x4] LDADD_32_memop
- (b'\x84\x00\x32\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x4))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x4),LLIL_ADD.d(LLIL_REG.d(w18),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w4,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadd w6, w14, [x23] LDADD_32_memop
- (b'\xEE\x02\x26\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x23))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x23),LLIL_ADD.d(LLIL_REG.d(w6),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w14,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadd w25, w29, [x9] LDADD_32_memop
- (b'\x3D\x01\x39\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x9))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x9),LLIL_ADD.d(LLIL_REG.d(w25),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w29,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadd w4, w22, [x15] LDADD_32_memop
- (b'\xF6\x01\x24\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x15))));' + \
- ' LLIL_STORE.d(LLIL_REG.q(x15),LLIL_ADD.d(LLIL_REG.d(w4),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
- ' LLIL_SET_REG.d(w22,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
- # ldadd x4, x24, [x5] LDADD_64_memop
- (b'\xB8\x00\x24\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x5))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x5),LLIL_ADD.q(LLIL_REG.q(x4),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x24,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadd x25, x4, [x7] LDADD_64_memop
- (b'\xE4\x00\x39\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x7))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x7),LLIL_ADD.q(LLIL_REG.q(x25),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x4,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadd x16, x20, [x8] LDADD_64_memop
- (b'\x14\x01\x30\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x8))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x8),LLIL_ADD.q(LLIL_REG.q(x16),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x20,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadd x15, x14, [x28] LDADD_64_memop
- (b'\x8E\x03\x2F\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x28))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x28),LLIL_ADD.q(LLIL_REG.q(x15),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x14,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadd x6, x10, [x29] LDADD_64_memop
- (b'\xAA\x03\x26\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x29))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x29),LLIL_ADD.q(LLIL_REG.q(x6),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x10,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadd x27, x27, [x19] LDADD_64_memop
- (b'\x7B\x02\x3B\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x19))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x19),LLIL_ADD.q(LLIL_REG.q(x27),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x27,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadd x27, x0, [x23] LDADD_64_memop
- (b'\xE0\x02\x3B\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x23))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x23),LLIL_ADD.q(LLIL_REG.q(x27),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x0,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # ldadd x13, x29, [x26] LDADD_64_memop
- (b'\x5D\x03\x2D\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x26))));' + \
- ' LLIL_STORE.q(LLIL_REG.q(x26),LLIL_ADD.q(LLIL_REG.q(x13),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
- ' LLIL_SET_REG.q(x29,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
- # staddb w24, [x23] STADDB_LDADDB_32_memop
- (b'\xFF\x02\x38\x38', 'LLIL_STORE.b(LLIL_REG.q(x23),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w24)),LLIL_LOAD.b(LLIL_REG.q(x23))))'),
- # staddb w7, [x2] STADDB_LDADDB_32_memop
- (b'\x5F\x00\x27\x38', 'LLIL_STORE.b(LLIL_REG.q(x2),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w7)),LLIL_LOAD.b(LLIL_REG.q(x2))))'),
- # staddb w0, [x0] STADDB_LDADDB_32_memop
- (b'\x1F\x00\x20\x38', 'LLIL_STORE.b(LLIL_REG.q(x0),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w0)),LLIL_LOAD.b(LLIL_REG.q(x0))))'),
- # staddb w29, [x19] STADDB_LDADDB_32_memop
- (b'\x7F\x02\x3D\x38', 'LLIL_STORE.b(LLIL_REG.q(x19),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w29)),LLIL_LOAD.b(LLIL_REG.q(x19))))'),
- # staddb w13, [x16] STADDB_LDADDB_32_memop
- (b'\x1F\x02\x2D\x38', 'LLIL_STORE.b(LLIL_REG.q(x16),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w13)),LLIL_LOAD.b(LLIL_REG.q(x16))))'),
- # staddb w25, [x18] STADDB_LDADDB_32_memop
- (b'\x5F\x02\x39\x38', 'LLIL_STORE.b(LLIL_REG.q(x18),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w25)),LLIL_LOAD.b(LLIL_REG.q(x18))))'),
- # staddb w3, [x16] STADDB_LDADDB_32_memop
- (b'\x1F\x02\x23\x38', 'LLIL_STORE.b(LLIL_REG.q(x16),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w3)),LLIL_LOAD.b(LLIL_REG.q(x16))))'),
- # staddb w11, [x11] STADDB_LDADDB_32_memop
- (b'\x7F\x01\x2B\x38', 'LLIL_STORE.b(LLIL_REG.q(x11),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w11)),LLIL_LOAD.b(LLIL_REG.q(x11))))'),
- # staddh w4, [x16] STADDH_LDADDH_32_memop
- (b'\x1F\x02\x24\x78', 'LLIL_STORE.w(LLIL_REG.q(x16),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w4)),LLIL_LOAD.w(LLIL_REG.q(x16))))'),
- # staddh w14, [x12] STADDH_LDADDH_32_memop
- (b'\x9F\x01\x2E\x78', 'LLIL_STORE.w(LLIL_REG.q(x12),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w14)),LLIL_LOAD.w(LLIL_REG.q(x12))))'),
- # staddh w12, [x18] STADDH_LDADDH_32_memop
- (b'\x5F\x02\x2C\x78', 'LLIL_STORE.w(LLIL_REG.q(x18),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w12)),LLIL_LOAD.w(LLIL_REG.q(x18))))'),
- # staddh w2, [x20] STADDH_LDADDH_32_memop
- (b'\x9F\x02\x22\x78', 'LLIL_STORE.w(LLIL_REG.q(x20),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w2)),LLIL_LOAD.w(LLIL_REG.q(x20))))'),
- # staddh w5, [x26] STADDH_LDADDH_32_memop
- (b'\x5F\x03\x25\x78', 'LLIL_STORE.w(LLIL_REG.q(x26),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w5)),LLIL_LOAD.w(LLIL_REG.q(x26))))'),
- # staddh w3, [x16] STADDH_LDADDH_32_memop
- (b'\x1F\x02\x23\x78', 'LLIL_STORE.w(LLIL_REG.q(x16),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w3)),LLIL_LOAD.w(LLIL_REG.q(x16))))'),
- # staddh w1, [x29] STADDH_LDADDH_32_memop
- (b'\xBF\x03\x21\x78', 'LLIL_STORE.w(LLIL_REG.q(x29),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w1)),LLIL_LOAD.w(LLIL_REG.q(x29))))'),
- # staddh w7, [x30] STADDH_LDADDH_32_memop
- (b'\xDF\x03\x27\x78', 'LLIL_STORE.w(LLIL_REG.q(x30),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w7)),LLIL_LOAD.w(LLIL_REG.q(x30))))'),
- # staddlb w11, [x18] STADDLB_LDADDLB_32_memop
- (b'\x5F\x02\x6B\x38', 'LLIL_STORE.b(LLIL_REG.q(x18),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w11)),LLIL_LOAD.b(LLIL_REG.q(x18))))'),
- # staddlb w25, [x28] STADDLB_LDADDLB_32_memop
- (b'\x9F\x03\x79\x38', 'LLIL_STORE.b(LLIL_REG.q(x28),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w25)),LLIL_LOAD.b(LLIL_REG.q(x28))))'),
- # staddlb w14, [x1] STADDLB_LDADDLB_32_memop
- (b'\x3F\x00\x6E\x38', 'LLIL_STORE.b(LLIL_REG.q(x1),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w14)),LLIL_LOAD.b(LLIL_REG.q(x1))))'),
- # staddlb w17, [x21] STADDLB_LDADDLB_32_memop
- (b'\xBF\x02\x71\x38', 'LLIL_STORE.b(LLIL_REG.q(x21),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w17)),LLIL_LOAD.b(LLIL_REG.q(x21))))'),
- # staddlb w30, [x7] STADDLB_LDADDLB_32_memop
- (b'\xFF\x00\x7E\x38', 'LLIL_STORE.b(LLIL_REG.q(x7),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w30)),LLIL_LOAD.b(LLIL_REG.q(x7))))'),
- # staddlb w19, [x27] STADDLB_LDADDLB_32_memop
- (b'\x7F\x03\x73\x38', 'LLIL_STORE.b(LLIL_REG.q(x27),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w19)),LLIL_LOAD.b(LLIL_REG.q(x27))))'),
- # staddlb w15, [x7] STADDLB_LDADDLB_32_memop
- (b'\xFF\x00\x6F\x38', 'LLIL_STORE.b(LLIL_REG.q(x7),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w15)),LLIL_LOAD.b(LLIL_REG.q(x7))))'),
- # staddlb w21, [x18] STADDLB_LDADDLB_32_memop
- (b'\x5F\x02\x75\x38', 'LLIL_STORE.b(LLIL_REG.q(x18),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w21)),LLIL_LOAD.b(LLIL_REG.q(x18))))'),
- # staddlh w12, [x21] STADDLH_LDADDLH_32_memop
- (b'\xBF\x02\x6C\x78', 'LLIL_STORE.w(LLIL_REG.q(x21),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w12)),LLIL_LOAD.w(LLIL_REG.q(x21))))'),
- # staddlh w9, [x4] STADDLH_LDADDLH_32_memop
- (b'\x9F\x00\x69\x78', 'LLIL_STORE.w(LLIL_REG.q(x4),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w9)),LLIL_LOAD.w(LLIL_REG.q(x4))))'),
- # staddlh w1, [x30] STADDLH_LDADDLH_32_memop
- (b'\xDF\x03\x61\x78', 'LLIL_STORE.w(LLIL_REG.q(x30),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w1)),LLIL_LOAD.w(LLIL_REG.q(x30))))'),
- # staddlh w25, [x16] STADDLH_LDADDLH_32_memop
- (b'\x1F\x02\x79\x78', 'LLIL_STORE.w(LLIL_REG.q(x16),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w25)),LLIL_LOAD.w(LLIL_REG.q(x16))))'),
- # staddlh w11, [x9] STADDLH_LDADDLH_32_memop
- (b'\x3F\x01\x6B\x78', 'LLIL_STORE.w(LLIL_REG.q(x9),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w11)),LLIL_LOAD.w(LLIL_REG.q(x9))))'),
- # staddlh w10, [x20] STADDLH_LDADDLH_32_memop
- (b'\x9F\x02\x6A\x78', 'LLIL_STORE.w(LLIL_REG.q(x20),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w10)),LLIL_LOAD.w(LLIL_REG.q(x20))))'),
- # staddlh w1, [x15] STADDLH_LDADDLH_32_memop
- (b'\xFF\x01\x61\x78', 'LLIL_STORE.w(LLIL_REG.q(x15),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w1)),LLIL_LOAD.w(LLIL_REG.q(x15))))'),
- # staddlh w27, [x2] STADDLH_LDADDLH_32_memop
- (b'\x5F\x00\x7B\x78', 'LLIL_STORE.w(LLIL_REG.q(x2),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w27)),LLIL_LOAD.w(LLIL_REG.q(x2))))'),
- # staddl w28, [x8] STADDL_LDADDL_32_memop
- (b'\x1F\x01\x7C\xB8', 'LLIL_STORE.q(LLIL_REG.q(x8),LLIL_ADD.d(LLIL_REG.d(w28),LLIL_LOAD.d(LLIL_REG.q(x8))))'),
- # staddl w16, [x16] STADDL_LDADDL_32_memop
- (b'\x1F\x02\x70\xB8', 'LLIL_STORE.q(LLIL_REG.q(x16),LLIL_ADD.d(LLIL_REG.d(w16),LLIL_LOAD.d(LLIL_REG.q(x16))))'),
- # staddl w15, [x30] STADDL_LDADDL_32_memop
- (b'\xDF\x03\x6F\xB8', 'LLIL_STORE.q(LLIL_REG.q(x30),LLIL_ADD.d(LLIL_REG.d(w15),LLIL_LOAD.d(LLIL_REG.q(x30))))'),
- # staddl w8, [x5] STADDL_LDADDL_32_memop
- (b'\xBF\x00\x68\xB8', 'LLIL_STORE.q(LLIL_REG.q(x5),LLIL_ADD.d(LLIL_REG.d(w8),LLIL_LOAD.d(LLIL_REG.q(x5))))'),
- # staddl w20, [x1] STADDL_LDADDL_32_memop
- (b'\x3F\x00\x74\xB8', 'LLIL_STORE.q(LLIL_REG.q(x1),LLIL_ADD.d(LLIL_REG.d(w20),LLIL_LOAD.d(LLIL_REG.q(x1))))'),
- # staddl wzr, [x6] STADDL_LDADDL_32_memop
- (b'\xDF\x00\x7F\xB8', 'LLIL_STORE.q(LLIL_REG.q(x6),LLIL_ADD.d(LLIL_CONST.d(0x0),LLIL_LOAD.d(LLIL_REG.q(x6))))'),
- # staddl w11, [x13] STADDL_LDADDL_32_memop
- (b'\xBF\x01\x6B\xB8', 'LLIL_STORE.q(LLIL_REG.q(x13),LLIL_ADD.d(LLIL_REG.d(w11),LLIL_LOAD.d(LLIL_REG.q(x13))))'),
- # staddl w16, [x25] STADDL_LDADDL_32_memop
- (b'\x3F\x03\x70\xB8', 'LLIL_STORE.q(LLIL_REG.q(x25),LLIL_ADD.d(LLIL_REG.d(w16),LLIL_LOAD.d(LLIL_REG.q(x25))))'),
- # staddl x24, [x4] STADDL_LDADDL_64_memop
- (b'\x9F\x00\x78\xF8', 'LLIL_STORE.q(LLIL_REG.q(x4),LLIL_ADD.q(LLIL_REG.q(x24),LLIL_LOAD.q(LLIL_REG.q(x4))))'),
- # staddl x20, [x12] STADDL_LDADDL_64_memop
- (b'\x9F\x01\x74\xF8', 'LLIL_STORE.q(LLIL_REG.q(x12),LLIL_ADD.q(LLIL_REG.q(x20),LLIL_LOAD.q(LLIL_REG.q(x12))))'),
- # staddl x28, [x8] STADDL_LDADDL_64_memop
- (b'\x1F\x01\x7C\xF8', 'LLIL_STORE.q(LLIL_REG.q(x8),LLIL_ADD.q(LLIL_REG.q(x28),LLIL_LOAD.q(LLIL_REG.q(x8))))'),
- # staddl x16, [x7] STADDL_LDADDL_64_memop
- (b'\xFF\x00\x70\xF8', 'LLIL_STORE.q(LLIL_REG.q(x7),LLIL_ADD.q(LLIL_REG.q(x16),LLIL_LOAD.q(LLIL_REG.q(x7))))'),
- # staddl x23, [x3] STADDL_LDADDL_64_memop
- (b'\x7F\x00\x77\xF8', 'LLIL_STORE.q(LLIL_REG.q(x3),LLIL_ADD.q(LLIL_REG.q(x23),LLIL_LOAD.q(LLIL_REG.q(x3))))'),
- # staddl x19, [x12] STADDL_LDADDL_64_memop
- (b'\x9F\x01\x73\xF8', 'LLIL_STORE.q(LLIL_REG.q(x12),LLIL_ADD.q(LLIL_REG.q(x19),LLIL_LOAD.q(LLIL_REG.q(x12))))'),
- # staddl x29, [x21] STADDL_LDADDL_64_memop
- (b'\xBF\x02\x7D\xF8', 'LLIL_STORE.q(LLIL_REG.q(x21),LLIL_ADD.q(LLIL_REG.q(x29),LLIL_LOAD.q(LLIL_REG.q(x21))))'),
- # staddl x6, [x29] STADDL_LDADDL_64_memop
- (b'\xBF\x03\x66\xF8', 'LLIL_STORE.q(LLIL_REG.q(x29),LLIL_ADD.q(LLIL_REG.q(x6),LLIL_LOAD.q(LLIL_REG.q(x29))))'),
- # stadd w3, [x6] STADD_LDADD_32_memop
- (b'\xDF\x00\x23\xB8', 'LLIL_STORE.q(LLIL_REG.q(x6),LLIL_ADD.d(LLIL_REG.d(w3),LLIL_LOAD.d(LLIL_REG.q(x6))))'),
- # stadd w29, [x12] STADD_LDADD_32_memop
- (b'\x9F\x01\x3D\xB8', 'LLIL_STORE.q(LLIL_REG.q(x12),LLIL_ADD.d(LLIL_REG.d(w29),LLIL_LOAD.d(LLIL_REG.q(x12))))'),
- # stadd w27, [x5] STADD_LDADD_32_memop
- (b'\xBF\x00\x3B\xB8', 'LLIL_STORE.q(LLIL_REG.q(x5),LLIL_ADD.d(LLIL_REG.d(w27),LLIL_LOAD.d(LLIL_REG.q(x5))))'),
- # stadd wzr, [x30] STADD_LDADD_32_memop
- (b'\xDF\x03\x3F\xB8', 'LLIL_STORE.q(LLIL_REG.q(x30),LLIL_ADD.d(LLIL_CONST.d(0x0),LLIL_LOAD.d(LLIL_REG.q(x30))))'),
- # stadd wzr, [sp] STADD_LDADD_32_memop
- (b'\xFF\x03\x3F\xB8', 'LLIL_STORE.q(LLIL_REG.q(sp),LLIL_ADD.d(LLIL_CONST.d(0x0),LLIL_LOAD.d(LLIL_REG.q(sp))))'),
- # stadd wzr, [x9] STADD_LDADD_32_memop
- (b'\x3F\x01\x3F\xB8', 'LLIL_STORE.q(LLIL_REG.q(x9),LLIL_ADD.d(LLIL_CONST.d(0x0),LLIL_LOAD.d(LLIL_REG.q(x9))))'),
- # stadd w11, [x21] STADD_LDADD_32_memop
- (b'\xBF\x02\x2B\xB8', 'LLIL_STORE.q(LLIL_REG.q(x21),LLIL_ADD.d(LLIL_REG.d(w11),LLIL_LOAD.d(LLIL_REG.q(x21))))'),
- # stadd w4, [x15] STADD_LDADD_32_memop
- (b'\xFF\x01\x24\xB8', 'LLIL_STORE.q(LLIL_REG.q(x15),LLIL_ADD.d(LLIL_REG.d(w4),LLIL_LOAD.d(LLIL_REG.q(x15))))'),
- # stadd xzr, [x16] STADD_LDADD_64_memop
- (b'\x1F\x02\x3F\xF8', 'LLIL_STORE.q(LLIL_REG.q(x16),LLIL_ADD.q(LLIL_CONST.q(0x0),LLIL_LOAD.q(LLIL_REG.q(x16))))'),
- # stadd x19, [x15] STADD_LDADD_64_memop
- (b'\xFF\x01\x33\xF8', 'LLIL_STORE.q(LLIL_REG.q(x15),LLIL_ADD.q(LLIL_REG.q(x19),LLIL_LOAD.q(LLIL_REG.q(x15))))'),
- # stadd xzr, [x24] STADD_LDADD_64_memop
- (b'\x1F\x03\x3F\xF8', 'LLIL_STORE.q(LLIL_REG.q(x24),LLIL_ADD.q(LLIL_CONST.q(0x0),LLIL_LOAD.q(LLIL_REG.q(x24))))'),
- # stadd x8, [x25] STADD_LDADD_64_memop
- (b'\x3F\x03\x28\xF8', 'LLIL_STORE.q(LLIL_REG.q(x25),LLIL_ADD.q(LLIL_REG.q(x8),LLIL_LOAD.q(LLIL_REG.q(x25))))'),
- # stadd x26, [x4] STADD_LDADD_64_memop
- (b'\x9F\x00\x3A\xF8', 'LLIL_STORE.q(LLIL_REG.q(x4),LLIL_ADD.q(LLIL_REG.q(x26),LLIL_LOAD.q(LLIL_REG.q(x4))))'),
- # stadd x28, [x9] STADD_LDADD_64_memop
- (b'\x3F\x01\x3C\xF8', 'LLIL_STORE.q(LLIL_REG.q(x9),LLIL_ADD.q(LLIL_REG.q(x28),LLIL_LOAD.q(LLIL_REG.q(x9))))'),
- # stadd x28, [x22] STADD_LDADD_64_memop
- (b'\xDF\x02\x3C\xF8', 'LLIL_STORE.q(LLIL_REG.q(x22),LLIL_ADD.q(LLIL_REG.q(x28),LLIL_LOAD.q(LLIL_REG.q(x22))))'),
- # stadd x19, [x22] STADD_LDADD_64_memop
- (b'\xDF\x02\x33\xF8', 'LLIL_STORE.q(LLIL_REG.q(x22),LLIL_ADD.q(LLIL_REG.q(x19),LLIL_LOAD.q(LLIL_REG.q(x22))))'),
+ # ldaddab w13, w7, [x30] LDADDAB_32_memop
+ (b'\xC7\x03\xAD\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x30))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x30),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w13)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w7,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddab w0, w22, [x28] LDADDAB_32_memop
+ (b'\x96\x03\xA0\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x28))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x28),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w0)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w22,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddab w18, w23, [x18] LDADDAB_32_memop
+ (b'\x57\x02\xB2\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x18))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x18),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w18)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w23,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddab w11, w18, [x19] LDADDAB_32_memop
+ (b'\x72\x02\xAB\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x19))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x19),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w11)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w18,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddab w26, w2, [x22] LDADDAB_32_memop
+ (b'\xC2\x02\xBA\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x22))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x22),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w26)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w2,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddab w15, w8, [x2] LDADDAB_32_memop
+ (b'\x48\x00\xAF\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x2))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x2),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w15)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w8,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddab w10, w8, [x17] LDADDAB_32_memop
+ (b'\x28\x02\xAA\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x17))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x17),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w10)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w8,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddab w12, w18, [x9] LDADDAB_32_memop
+ (b'\x32\x01\xAC\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x9))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x9),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w12)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w18,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddah w9, w16, [x11] LDADDAH_32_memop
+ (b'\x70\x01\xA9\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x11))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x11),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w9)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w16,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddah w14, w16, [x28] LDADDAH_32_memop
+ (b'\x90\x03\xAE\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x28))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x28),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w14)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w16,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddah w15, w30, [x21] LDADDAH_32_memop
+ (b'\xBE\x02\xAF\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x21))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x21),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w15)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w30,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddah w17, w23, [x22] LDADDAH_32_memop
+ (b'\xD7\x02\xB1\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x22))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x22),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w17)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w23,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddah w7, w22, [x18] LDADDAH_32_memop
+ (b'\x56\x02\xA7\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x18))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x18),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w7)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w22,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddah w4, w6, [x9] LDADDAH_32_memop
+ (b'\x26\x01\xA4\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x9))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x9),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w4)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w6,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddah w8, w29, [x16] LDADDAH_32_memop
+ (b'\x1D\x02\xA8\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x16))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x16),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w8)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w29,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddah w11, w28, [x8] LDADDAH_32_memop
+ (b'\x1C\x01\xAB\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x8))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x8),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w11)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w28,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddalb w14, w2, [x14] LDADDALB_32_memop
+ (b'\xC2\x01\xEE\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x14))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x14),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w14)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w2,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddalb w0, w24, [x16] LDADDALB_32_memop
+ (b'\x18\x02\xE0\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x16))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x16),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w0)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w24,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddalb w14, w18, [x24] LDADDALB_32_memop
+ (b'\x12\x03\xEE\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x24))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x24),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w14)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w18,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddalb w25, w28, [x24] LDADDALB_32_memop
+ (b'\x1C\x03\xF9\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x24))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x24),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w25)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w28,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddalb w25, w19, [sp] LDADDALB_32_memop
+ (b'\xF3\x03\xF9\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(sp))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(sp),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w25)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w19,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddalb w10, w15, [x24] LDADDALB_32_memop
+ (b'\x0F\x03\xEA\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x24))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x24),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w10)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w15,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddalb w10, w10, [x10] LDADDALB_32_memop
+ (b'\x4A\x01\xEA\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x10))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x10),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w10)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w10,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddalb w18, w12, [x28] LDADDALB_32_memop
+ (b'\x8C\x03\xF2\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x28))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x28),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w18)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w12,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddalh w21, w30, [sp] LDADDALH_32_memop
+ (b'\xFE\x03\xF5\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(sp))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(sp),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w21)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w30,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddalh w24, wzr, [x19] LDADDALH_32_memop
+ (b'\x7F\x02\xF8\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x19))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x19),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w24)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddalh w27, w23, [x23] LDADDALH_32_memop
+ (b'\xF7\x02\xFB\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x23))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x23),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w27)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w23,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddalh w28, w30, [x15] LDADDALH_32_memop
+ (b'\xFE\x01\xFC\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x15))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x15),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w28)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w30,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddalh w5, w9, [x2] LDADDALH_32_memop
+ (b'\x49\x00\xE5\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x2))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x2),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w5)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w9,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddalh w9, w29, [x1] LDADDALH_32_memop
+ (b'\x3D\x00\xE9\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x1))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x1),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w9)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w29,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddalh w16, w14, [x11] LDADDALH_32_memop
+ (b'\x6E\x01\xF0\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x11))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x11),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w16)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w14,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddalh w14, wzr, [x21] LDADDALH_32_memop
+ (b'\xBF\x02\xEE\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x21))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x21),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w14)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddal w17, w13, [x7] LDADDAL_32_memop
+ (b'\xED\x00\xF1\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x7))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x7),LLIL_ADD.d(LLIL_REG.d(w17),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w13,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddal w7, w27, [x3] LDADDAL_32_memop
+ (b'\x7B\x00\xE7\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x3))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x3),LLIL_ADD.d(LLIL_REG.d(w7),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w27,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddal w21, w5, [x0] LDADDAL_32_memop
+ (b'\x05\x00\xF5\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x0))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x0),LLIL_ADD.d(LLIL_REG.d(w21),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w5,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddal w2, w28, [x7] LDADDAL_32_memop
+ (b'\xFC\x00\xE2\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x7))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x7),LLIL_ADD.d(LLIL_REG.d(w2),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w28,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddal w0, w21, [x16] LDADDAL_32_memop
+ (b'\x15\x02\xE0\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x16))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x16),LLIL_ADD.d(LLIL_REG.d(w0),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w21,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddal wzr, w16, [x11] LDADDAL_32_memop
+ (b'\x70\x01\xFF\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x11))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x11),LLIL_ADD.d(LLIL_CONST.d(0x0),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w16,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddal w29, w16, [x10] LDADDAL_32_memop
+ (b'\x50\x01\xFD\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x10))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x10),LLIL_ADD.d(LLIL_REG.d(w29),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w16,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddal w22, w30, [x12] LDADDAL_32_memop
+ (b'\x9E\x01\xF6\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x12))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x12),LLIL_ADD.d(LLIL_REG.d(w22),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w30,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddal x0, x5, [x1] LDADDAL_64_memop
+ (b'\x25\x00\xE0\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x1))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x1),LLIL_ADD.q(LLIL_REG.q(x0),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x5,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldaddal x6, x13, [x13] LDADDAL_64_memop
+ (b'\xAD\x01\xE6\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x13))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x13),LLIL_ADD.q(LLIL_REG.q(x6),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x13,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldaddal x10, x4, [x18] LDADDAL_64_memop
+ (b'\x44\x02\xEA\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x18))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x18),LLIL_ADD.q(LLIL_REG.q(x10),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x4,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldaddal x12, x2, [x5] LDADDAL_64_memop
+ (b'\xA2\x00\xEC\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x5))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x5),LLIL_ADD.q(LLIL_REG.q(x12),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x2,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldaddal x11, x19, [x17] LDADDAL_64_memop
+ (b'\x33\x02\xEB\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x17))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x17),LLIL_ADD.q(LLIL_REG.q(x11),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x19,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldaddal x12, x28, [x23] LDADDAL_64_memop
+ (b'\xFC\x02\xEC\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x23))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x23),LLIL_ADD.q(LLIL_REG.q(x12),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x28,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldaddal x6, x7, [x22] LDADDAL_64_memop
+ (b'\xC7\x02\xE6\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x22))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x22),LLIL_ADD.q(LLIL_REG.q(x6),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x7,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldaddal x10, x21, [x8] LDADDAL_64_memop
+ (b'\x15\x01\xEA\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x8))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x8),LLIL_ADD.q(LLIL_REG.q(x10),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x21,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadda w9, w4, [x4] LDADDA_32_memop
+ (b'\x84\x00\xA9\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x4))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x4),LLIL_ADD.d(LLIL_REG.d(w9),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w4,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadda w17, w29, [x27] LDADDA_32_memop
+ (b'\x7D\x03\xB1\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x27))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x27),LLIL_ADD.d(LLIL_REG.d(w17),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w29,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadda w5, w9, [x7] LDADDA_32_memop
+ (b'\xE9\x00\xA5\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x7))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x7),LLIL_ADD.d(LLIL_REG.d(w5),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w9,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadda w12, w22, [x25] LDADDA_32_memop
+ (b'\x36\x03\xAC\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x25))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x25),LLIL_ADD.d(LLIL_REG.d(w12),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w22,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadda w19, w12, [x11] LDADDA_32_memop
+ (b'\x6C\x01\xB3\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x11))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x11),LLIL_ADD.d(LLIL_REG.d(w19),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w12,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadda w16, w14, [x10] LDADDA_32_memop
+ (b'\x4E\x01\xB0\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x10))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x10),LLIL_ADD.d(LLIL_REG.d(w16),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w14,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadda w21, w5, [x4] LDADDA_32_memop
+ (b'\x85\x00\xB5\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x4))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x4),LLIL_ADD.d(LLIL_REG.d(w21),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w5,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadda w22, w14, [x16] LDADDA_32_memop
+ (b'\x0E\x02\xB6\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x16))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x16),LLIL_ADD.d(LLIL_REG.d(w22),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w14,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadda x5, x9, [x22] LDADDA_64_memop
+ (b'\xC9\x02\xA5\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x22))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x22),LLIL_ADD.q(LLIL_REG.q(x5),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x9,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadda x6, x2, [x4] LDADDA_64_memop
+ (b'\x82\x00\xA6\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x4))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x4),LLIL_ADD.q(LLIL_REG.q(x6),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x2,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadda x0, x25, [x24] LDADDA_64_memop
+ (b'\x19\x03\xA0\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x24))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x24),LLIL_ADD.q(LLIL_REG.q(x0),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x25,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadda x1, x20, [sp] LDADDA_64_memop
+ (b'\xF4\x03\xA1\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(sp))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(sp),LLIL_ADD.q(LLIL_REG.q(x1),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x20,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadda x27, x16, [x20] LDADDA_64_memop
+ (b'\x90\x02\xBB\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x20))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x20),LLIL_ADD.q(LLIL_REG.q(x27),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x16,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadda xzr, x15, [x16] LDADDA_64_memop
+ (b'\x0F\x02\xBF\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x16))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x16),LLIL_ADD.q(LLIL_CONST.q(0x0),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x15,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadda x9, x8, [x1] LDADDA_64_memop
+ (b'\x28\x00\xA9\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x1))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x1),LLIL_ADD.q(LLIL_REG.q(x9),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x8,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadda x18, x23, [x17] LDADDA_64_memop
+ (b'\x37\x02\xB2\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x17))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x17),LLIL_ADD.q(LLIL_REG.q(x18),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x23,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldaddb w16, w24, [x10] LDADDB_32_memop
+ (b'\x58\x01\x30\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x10))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x10),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w16)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w24,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddb w4, w0, [x27] LDADDB_32_memop
+ (b'\x60\x03\x24\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x27))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x27),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w4)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w0,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddb w9, w7, [x21] LDADDB_32_memop
+ (b'\xA7\x02\x29\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x21))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x21),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w9)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w7,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddb w8, w30, [x11] LDADDB_32_memop
+ (b'\x7E\x01\x28\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x11))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x11),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w8)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w30,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddb w4, w13, [x19] LDADDB_32_memop
+ (b'\x6D\x02\x24\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x19))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x19),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w4)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w13,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddb w2, w29, [x14] LDADDB_32_memop
+ (b'\xDD\x01\x22\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x14))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x14),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w2)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w29,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddb w4, w22, [x27] LDADDB_32_memop
+ (b'\x76\x03\x24\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x27))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x27),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w4)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w22,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddb w8, w29, [x29] LDADDB_32_memop
+ (b'\xBD\x03\x28\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x29))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x29),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w8)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w29,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddh w30, w28, [x27] LDADDH_32_memop
+ (b'\x7C\x03\x3E\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x27))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x27),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w30)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w28,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddh w20, w5, [x24] LDADDH_32_memop
+ (b'\x05\x03\x34\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x24))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x24),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w20)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w5,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddh w7, w13, [x28] LDADDH_32_memop
+ (b'\x8D\x03\x27\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x28))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x28),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w7)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w13,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddh w18, w12, [x17] LDADDH_32_memop
+ (b'\x2C\x02\x32\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x17))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x17),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w18)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w12,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddh w17, w3, [x4] LDADDH_32_memop
+ (b'\x83\x00\x31\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x4))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x4),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w17)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w3,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddh w8, w9, [x12] LDADDH_32_memop
+ (b'\x89\x01\x28\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x12))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x12),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w8)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w9,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddh w8, w7, [x22] LDADDH_32_memop
+ (b'\xC7\x02\x28\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x22))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x22),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w8)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w7,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddh w5, w23, [x30] LDADDH_32_memop
+ (b'\xD7\x03\x25\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x30))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x30),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w5)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w23,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddlb w9, w24, [x5] LDADDLB_32_memop
+ (b'\xB8\x00\x69\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x5))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x5),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w9)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w24,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddlb w3, w9, [x11] LDADDLB_32_memop
+ (b'\x69\x01\x63\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x11))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x11),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w3)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w9,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddlb w29, w7, [x27] LDADDLB_32_memop
+ (b'\x67\x03\x7D\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x27))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x27),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w29)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w7,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddlb w8, w4, [x11] LDADDLB_32_memop
+ (b'\x64\x01\x68\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x11))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x11),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w8)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w4,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddlb w30, w2, [x13] LDADDLB_32_memop
+ (b'\xA2\x01\x7E\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x13))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x13),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w30)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w2,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddlb w19, w11, [x24] LDADDLB_32_memop
+ (b'\x0B\x03\x73\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x24))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x24),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w19)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w11,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddlb w9, w15, [x17] LDADDLB_32_memop
+ (b'\x2F\x02\x69\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x17))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x17),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w9)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w15,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddlb w20, w7, [x15] LDADDLB_32_memop
+ (b'\xE7\x01\x74\x38', 'LLIL_SET_REG(temp0,LLIL_ZX.b(LLIL_LOAD.b(LLIL_REG.q(x15))));' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x15),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w20)),LLIL_LOW_PART.b(LLIL_REG.b(temp0))));' + \
+ ' LLIL_SET_REG.d(w7,LLIL_ZX.d(LLIL_LOW_PART.b(LLIL_REG.b(temp0))))'),
+ # ldaddlh w17, w18, [x1] LDADDLH_32_memop
+ (b'\x32\x00\x71\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x1))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x1),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w17)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w18,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddlh w16, w8, [x1] LDADDLH_32_memop
+ (b'\x28\x00\x70\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x1))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x1),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w16)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w8,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddlh w18, w1, [x28] LDADDLH_32_memop
+ (b'\x81\x03\x72\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x28))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x28),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w18)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w1,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddlh w11, w8, [x25] LDADDLH_32_memop
+ (b'\x28\x03\x6B\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x25))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x25),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w11)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w8,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddlh w11, w7, [x1] LDADDLH_32_memop
+ (b'\x27\x00\x6B\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x1))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x1),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w11)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w7,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddlh w21, w8, [x28] LDADDLH_32_memop
+ (b'\x88\x03\x75\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x28))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x28),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w21)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w8,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddlh w16, w21, [x2] LDADDLH_32_memop
+ (b'\x55\x00\x70\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x2))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x2),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w16)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w21,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddlh w6, w14, [x25] LDADDLH_32_memop
+ (b'\x2E\x03\x66\x78', 'LLIL_SET_REG(temp0,LLIL_ZX.w(LLIL_LOAD.w(LLIL_REG.q(x25))));' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x25),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w6)),LLIL_LOW_PART.w(LLIL_REG.w(temp0))));' + \
+ ' LLIL_SET_REG.d(w14,LLIL_ZX.d(LLIL_LOW_PART.w(LLIL_REG.w(temp0))))'),
+ # ldaddl w8, w6, [x4] LDADDL_32_memop
+ (b'\x86\x00\x68\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x4))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x4),LLIL_ADD.d(LLIL_REG.d(w8),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w6,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddl w15, w23, [x28] LDADDL_32_memop
+ (b'\x97\x03\x6F\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x28))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x28),LLIL_ADD.d(LLIL_REG.d(w15),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w23,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddl w18, w7, [x0] LDADDL_32_memop
+ (b'\x07\x00\x72\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x0))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x0),LLIL_ADD.d(LLIL_REG.d(w18),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w7,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddl w11, w17, [x25] LDADDL_32_memop
+ (b'\x31\x03\x6B\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x25))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x25),LLIL_ADD.d(LLIL_REG.d(w11),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w17,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddl w14, w3, [x8] LDADDL_32_memop
+ (b'\x03\x01\x6E\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x8))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x8),LLIL_ADD.d(LLIL_REG.d(w14),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w3,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddl w15, w18, [x12] LDADDL_32_memop
+ (b'\x92\x01\x6F\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x12))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x12),LLIL_ADD.d(LLIL_REG.d(w15),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w18,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddl w19, w5, [x18] LDADDL_32_memop
+ (b'\x45\x02\x73\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x18))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x18),LLIL_ADD.d(LLIL_REG.d(w19),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w5,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddl w21, w24, [x7] LDADDL_32_memop
+ (b'\xF8\x00\x75\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x7))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x7),LLIL_ADD.d(LLIL_REG.d(w21),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w24,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldaddl x19, x17, [x26] LDADDL_64_memop
+ (b'\x51\x03\x73\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x26))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x26),LLIL_ADD.q(LLIL_REG.q(x19),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x17,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldaddl x4, x17, [x20] LDADDL_64_memop
+ (b'\x91\x02\x64\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x20))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x20),LLIL_ADD.q(LLIL_REG.q(x4),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x17,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldaddl x23, x22, [x1] LDADDL_64_memop
+ (b'\x36\x00\x77\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x1))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x1),LLIL_ADD.q(LLIL_REG.q(x23),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x22,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldaddl x9, x6, [x30] LDADDL_64_memop
+ (b'\xC6\x03\x69\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x30))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x30),LLIL_ADD.q(LLIL_REG.q(x9),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x6,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldaddl x2, x20, [x0] LDADDL_64_memop
+ (b'\x14\x00\x62\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x0))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x0),LLIL_ADD.q(LLIL_REG.q(x2),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x20,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldaddl x1, x19, [x26] LDADDL_64_memop
+ (b'\x53\x03\x61\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x26))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x26),LLIL_ADD.q(LLIL_REG.q(x1),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x19,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldaddl x22, x30, [x7] LDADDL_64_memop
+ (b'\xFE\x00\x76\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x7))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x7),LLIL_ADD.q(LLIL_REG.q(x22),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x30,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldaddl x12, x9, [x15] LDADDL_64_memop
+ (b'\xE9\x01\x6C\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x15))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x15),LLIL_ADD.q(LLIL_REG.q(x12),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x9,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadd w24, w11, [x29] LDADD_32_memop
+ (b'\xAB\x03\x38\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x29))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x29),LLIL_ADD.d(LLIL_REG.d(w24),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w11,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadd w17, w22, [x12] LDADD_32_memop
+ (b'\x96\x01\x31\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x12))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x12),LLIL_ADD.d(LLIL_REG.d(w17),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w22,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadd w24, w16, [x5] LDADD_32_memop
+ (b'\xB0\x00\x38\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x5))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x5),LLIL_ADD.d(LLIL_REG.d(w24),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w16,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadd w1, w26, [x16] LDADD_32_memop
+ (b'\x1A\x02\x21\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x16))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x16),LLIL_ADD.d(LLIL_REG.d(w1),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w26,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadd w18, w4, [x4] LDADD_32_memop
+ (b'\x84\x00\x32\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x4))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x4),LLIL_ADD.d(LLIL_REG.d(w18),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w4,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadd w6, w14, [x23] LDADD_32_memop
+ (b'\xEE\x02\x26\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x23))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x23),LLIL_ADD.d(LLIL_REG.d(w6),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w14,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadd w25, w29, [x9] LDADD_32_memop
+ (b'\x3D\x01\x39\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x9))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x9),LLIL_ADD.d(LLIL_REG.d(w25),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w29,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadd w4, w22, [x15] LDADD_32_memop
+ (b'\xF6\x01\x24\xB8', 'LLIL_SET_REG(temp0,LLIL_ZX.d(LLIL_LOAD.d(LLIL_REG.q(x15))));' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x15),LLIL_ADD.d(LLIL_REG.d(w4),LLIL_ZX.d(LLIL_REG.d(temp0))));' + \
+ ' LLIL_SET_REG.d(w22,LLIL_ZX.d(LLIL_REG.d(temp0)))'),
+ # ldadd x4, x24, [x5] LDADD_64_memop
+ (b'\xB8\x00\x24\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x5))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x5),LLIL_ADD.q(LLIL_REG.q(x4),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x24,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadd x25, x4, [x7] LDADD_64_memop
+ (b'\xE4\x00\x39\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x7))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x7),LLIL_ADD.q(LLIL_REG.q(x25),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x4,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadd x16, x20, [x8] LDADD_64_memop
+ (b'\x14\x01\x30\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x8))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x8),LLIL_ADD.q(LLIL_REG.q(x16),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x20,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadd x15, x14, [x28] LDADD_64_memop
+ (b'\x8E\x03\x2F\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x28))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x28),LLIL_ADD.q(LLIL_REG.q(x15),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x14,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadd x6, x10, [x29] LDADD_64_memop
+ (b'\xAA\x03\x26\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x29))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x29),LLIL_ADD.q(LLIL_REG.q(x6),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x10,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadd x27, x27, [x19] LDADD_64_memop
+ (b'\x7B\x02\x3B\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x19))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x19),LLIL_ADD.q(LLIL_REG.q(x27),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x27,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadd x27, x0, [x23] LDADD_64_memop
+ (b'\xE0\x02\x3B\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x23))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x23),LLIL_ADD.q(LLIL_REG.q(x27),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x0,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # ldadd x13, x29, [x26] LDADD_64_memop
+ (b'\x5D\x03\x2D\xF8', 'LLIL_SET_REG(temp0,LLIL_ZX.q(LLIL_LOAD.q(LLIL_REG.q(x26))));' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x26),LLIL_ADD.q(LLIL_REG.q(x13),LLIL_ZX.q(LLIL_REG.q(temp0))));' + \
+ ' LLIL_SET_REG.q(x29,LLIL_ZX.q(LLIL_REG.q(temp0)))'),
+ # staddb w24, [x23] STADDB_LDADDB_32_memop
+ (b'\xFF\x02\x38\x38', 'LLIL_STORE.b(LLIL_REG.q(x23),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w24)),LLIL_LOAD.b(LLIL_REG.q(x23))))'),
+ # staddb w7, [x2] STADDB_LDADDB_32_memop
+ (b'\x5F\x00\x27\x38', 'LLIL_STORE.b(LLIL_REG.q(x2),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w7)),LLIL_LOAD.b(LLIL_REG.q(x2))))'),
+ # staddb w0, [x0] STADDB_LDADDB_32_memop
+ (b'\x1F\x00\x20\x38', 'LLIL_STORE.b(LLIL_REG.q(x0),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w0)),LLIL_LOAD.b(LLIL_REG.q(x0))))'),
+ # staddb w29, [x19] STADDB_LDADDB_32_memop
+ (b'\x7F\x02\x3D\x38', 'LLIL_STORE.b(LLIL_REG.q(x19),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w29)),LLIL_LOAD.b(LLIL_REG.q(x19))))'),
+ # staddb w13, [x16] STADDB_LDADDB_32_memop
+ (b'\x1F\x02\x2D\x38', 'LLIL_STORE.b(LLIL_REG.q(x16),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w13)),LLIL_LOAD.b(LLIL_REG.q(x16))))'),
+ # staddb w25, [x18] STADDB_LDADDB_32_memop
+ (b'\x5F\x02\x39\x38', 'LLIL_STORE.b(LLIL_REG.q(x18),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w25)),LLIL_LOAD.b(LLIL_REG.q(x18))))'),
+ # staddb w3, [x16] STADDB_LDADDB_32_memop
+ (b'\x1F\x02\x23\x38', 'LLIL_STORE.b(LLIL_REG.q(x16),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w3)),LLIL_LOAD.b(LLIL_REG.q(x16))))'),
+ # staddb w11, [x11] STADDB_LDADDB_32_memop
+ (b'\x7F\x01\x2B\x38', 'LLIL_STORE.b(LLIL_REG.q(x11),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w11)),LLIL_LOAD.b(LLIL_REG.q(x11))))'),
+ # staddh w4, [x16] STADDH_LDADDH_32_memop
+ (b'\x1F\x02\x24\x78', 'LLIL_STORE.w(LLIL_REG.q(x16),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w4)),LLIL_LOAD.w(LLIL_REG.q(x16))))'),
+ # staddh w14, [x12] STADDH_LDADDH_32_memop
+ (b'\x9F\x01\x2E\x78', 'LLIL_STORE.w(LLIL_REG.q(x12),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w14)),LLIL_LOAD.w(LLIL_REG.q(x12))))'),
+ # staddh w12, [x18] STADDH_LDADDH_32_memop
+ (b'\x5F\x02\x2C\x78', 'LLIL_STORE.w(LLIL_REG.q(x18),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w12)),LLIL_LOAD.w(LLIL_REG.q(x18))))'),
+ # staddh w2, [x20] STADDH_LDADDH_32_memop
+ (b'\x9F\x02\x22\x78', 'LLIL_STORE.w(LLIL_REG.q(x20),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w2)),LLIL_LOAD.w(LLIL_REG.q(x20))))'),
+ # staddh w5, [x26] STADDH_LDADDH_32_memop
+ (b'\x5F\x03\x25\x78', 'LLIL_STORE.w(LLIL_REG.q(x26),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w5)),LLIL_LOAD.w(LLIL_REG.q(x26))))'),
+ # staddh w3, [x16] STADDH_LDADDH_32_memop
+ (b'\x1F\x02\x23\x78', 'LLIL_STORE.w(LLIL_REG.q(x16),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w3)),LLIL_LOAD.w(LLIL_REG.q(x16))))'),
+ # staddh w1, [x29] STADDH_LDADDH_32_memop
+ (b'\xBF\x03\x21\x78', 'LLIL_STORE.w(LLIL_REG.q(x29),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w1)),LLIL_LOAD.w(LLIL_REG.q(x29))))'),
+ # staddh w7, [x30] STADDH_LDADDH_32_memop
+ (b'\xDF\x03\x27\x78', 'LLIL_STORE.w(LLIL_REG.q(x30),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w7)),LLIL_LOAD.w(LLIL_REG.q(x30))))'),
+ # staddlb w11, [x18] STADDLB_LDADDLB_32_memop
+ (b'\x5F\x02\x6B\x38', 'LLIL_STORE.b(LLIL_REG.q(x18),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w11)),LLIL_LOAD.b(LLIL_REG.q(x18))))'),
+ # staddlb w25, [x28] STADDLB_LDADDLB_32_memop
+ (b'\x9F\x03\x79\x38', 'LLIL_STORE.b(LLIL_REG.q(x28),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w25)),LLIL_LOAD.b(LLIL_REG.q(x28))))'),
+ # staddlb w14, [x1] STADDLB_LDADDLB_32_memop
+ (b'\x3F\x00\x6E\x38', 'LLIL_STORE.b(LLIL_REG.q(x1),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w14)),LLIL_LOAD.b(LLIL_REG.q(x1))))'),
+ # staddlb w17, [x21] STADDLB_LDADDLB_32_memop
+ (b'\xBF\x02\x71\x38', 'LLIL_STORE.b(LLIL_REG.q(x21),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w17)),LLIL_LOAD.b(LLIL_REG.q(x21))))'),
+ # staddlb w30, [x7] STADDLB_LDADDLB_32_memop
+ (b'\xFF\x00\x7E\x38', 'LLIL_STORE.b(LLIL_REG.q(x7),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w30)),LLIL_LOAD.b(LLIL_REG.q(x7))))'),
+ # staddlb w19, [x27] STADDLB_LDADDLB_32_memop
+ (b'\x7F\x03\x73\x38', 'LLIL_STORE.b(LLIL_REG.q(x27),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w19)),LLIL_LOAD.b(LLIL_REG.q(x27))))'),
+ # staddlb w15, [x7] STADDLB_LDADDLB_32_memop
+ (b'\xFF\x00\x6F\x38', 'LLIL_STORE.b(LLIL_REG.q(x7),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w15)),LLIL_LOAD.b(LLIL_REG.q(x7))))'),
+ # staddlb w21, [x18] STADDLB_LDADDLB_32_memop
+ (b'\x5F\x02\x75\x38', 'LLIL_STORE.b(LLIL_REG.q(x18),LLIL_ADD.b(LLIL_LOW_PART.b(LLIL_REG.d(w21)),LLIL_LOAD.b(LLIL_REG.q(x18))))'),
+ # staddlh w12, [x21] STADDLH_LDADDLH_32_memop
+ (b'\xBF\x02\x6C\x78', 'LLIL_STORE.w(LLIL_REG.q(x21),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w12)),LLIL_LOAD.w(LLIL_REG.q(x21))))'),
+ # staddlh w9, [x4] STADDLH_LDADDLH_32_memop
+ (b'\x9F\x00\x69\x78', 'LLIL_STORE.w(LLIL_REG.q(x4),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w9)),LLIL_LOAD.w(LLIL_REG.q(x4))))'),
+ # staddlh w1, [x30] STADDLH_LDADDLH_32_memop
+ (b'\xDF\x03\x61\x78', 'LLIL_STORE.w(LLIL_REG.q(x30),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w1)),LLIL_LOAD.w(LLIL_REG.q(x30))))'),
+ # staddlh w25, [x16] STADDLH_LDADDLH_32_memop
+ (b'\x1F\x02\x79\x78', 'LLIL_STORE.w(LLIL_REG.q(x16),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w25)),LLIL_LOAD.w(LLIL_REG.q(x16))))'),
+ # staddlh w11, [x9] STADDLH_LDADDLH_32_memop
+ (b'\x3F\x01\x6B\x78', 'LLIL_STORE.w(LLIL_REG.q(x9),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w11)),LLIL_LOAD.w(LLIL_REG.q(x9))))'),
+ # staddlh w10, [x20] STADDLH_LDADDLH_32_memop
+ (b'\x9F\x02\x6A\x78', 'LLIL_STORE.w(LLIL_REG.q(x20),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w10)),LLIL_LOAD.w(LLIL_REG.q(x20))))'),
+ # staddlh w1, [x15] STADDLH_LDADDLH_32_memop
+ (b'\xFF\x01\x61\x78', 'LLIL_STORE.w(LLIL_REG.q(x15),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w1)),LLIL_LOAD.w(LLIL_REG.q(x15))))'),
+ # staddlh w27, [x2] STADDLH_LDADDLH_32_memop
+ (b'\x5F\x00\x7B\x78', 'LLIL_STORE.w(LLIL_REG.q(x2),LLIL_ADD.w(LLIL_LOW_PART.w(LLIL_REG.d(w27)),LLIL_LOAD.w(LLIL_REG.q(x2))))'),
+ # staddl w28, [x8] STADDL_LDADDL_32_memop
+ (b'\x1F\x01\x7C\xB8', 'LLIL_STORE.q(LLIL_REG.q(x8),LLIL_ADD.d(LLIL_REG.d(w28),LLIL_LOAD.d(LLIL_REG.q(x8))))'),
+ # staddl w16, [x16] STADDL_LDADDL_32_memop
+ (b'\x1F\x02\x70\xB8', 'LLIL_STORE.q(LLIL_REG.q(x16),LLIL_ADD.d(LLIL_REG.d(w16),LLIL_LOAD.d(LLIL_REG.q(x16))))'),
+ # staddl w15, [x30] STADDL_LDADDL_32_memop
+ (b'\xDF\x03\x6F\xB8', 'LLIL_STORE.q(LLIL_REG.q(x30),LLIL_ADD.d(LLIL_REG.d(w15),LLIL_LOAD.d(LLIL_REG.q(x30))))'),
+ # staddl w8, [x5] STADDL_LDADDL_32_memop
+ (b'\xBF\x00\x68\xB8', 'LLIL_STORE.q(LLIL_REG.q(x5),LLIL_ADD.d(LLIL_REG.d(w8),LLIL_LOAD.d(LLIL_REG.q(x5))))'),
+ # staddl w20, [x1] STADDL_LDADDL_32_memop
+ (b'\x3F\x00\x74\xB8', 'LLIL_STORE.q(LLIL_REG.q(x1),LLIL_ADD.d(LLIL_REG.d(w20),LLIL_LOAD.d(LLIL_REG.q(x1))))'),
+ # staddl wzr, [x6] STADDL_LDADDL_32_memop
+ (b'\xDF\x00\x7F\xB8', 'LLIL_STORE.q(LLIL_REG.q(x6),LLIL_ADD.d(LLIL_CONST.d(0x0),LLIL_LOAD.d(LLIL_REG.q(x6))))'),
+ # staddl w11, [x13] STADDL_LDADDL_32_memop
+ (b'\xBF\x01\x6B\xB8', 'LLIL_STORE.q(LLIL_REG.q(x13),LLIL_ADD.d(LLIL_REG.d(w11),LLIL_LOAD.d(LLIL_REG.q(x13))))'),
+ # staddl w16, [x25] STADDL_LDADDL_32_memop
+ (b'\x3F\x03\x70\xB8', 'LLIL_STORE.q(LLIL_REG.q(x25),LLIL_ADD.d(LLIL_REG.d(w16),LLIL_LOAD.d(LLIL_REG.q(x25))))'),
+ # staddl x24, [x4] STADDL_LDADDL_64_memop
+ (b'\x9F\x00\x78\xF8', 'LLIL_STORE.q(LLIL_REG.q(x4),LLIL_ADD.q(LLIL_REG.q(x24),LLIL_LOAD.q(LLIL_REG.q(x4))))'),
+ # staddl x20, [x12] STADDL_LDADDL_64_memop
+ (b'\x9F\x01\x74\xF8', 'LLIL_STORE.q(LLIL_REG.q(x12),LLIL_ADD.q(LLIL_REG.q(x20),LLIL_LOAD.q(LLIL_REG.q(x12))))'),
+ # staddl x28, [x8] STADDL_LDADDL_64_memop
+ (b'\x1F\x01\x7C\xF8', 'LLIL_STORE.q(LLIL_REG.q(x8),LLIL_ADD.q(LLIL_REG.q(x28),LLIL_LOAD.q(LLIL_REG.q(x8))))'),
+ # staddl x16, [x7] STADDL_LDADDL_64_memop
+ (b'\xFF\x00\x70\xF8', 'LLIL_STORE.q(LLIL_REG.q(x7),LLIL_ADD.q(LLIL_REG.q(x16),LLIL_LOAD.q(LLIL_REG.q(x7))))'),
+ # staddl x23, [x3] STADDL_LDADDL_64_memop
+ (b'\x7F\x00\x77\xF8', 'LLIL_STORE.q(LLIL_REG.q(x3),LLIL_ADD.q(LLIL_REG.q(x23),LLIL_LOAD.q(LLIL_REG.q(x3))))'),
+ # staddl x19, [x12] STADDL_LDADDL_64_memop
+ (b'\x9F\x01\x73\xF8', 'LLIL_STORE.q(LLIL_REG.q(x12),LLIL_ADD.q(LLIL_REG.q(x19),LLIL_LOAD.q(LLIL_REG.q(x12))))'),
+ # staddl x29, [x21] STADDL_LDADDL_64_memop
+ (b'\xBF\x02\x7D\xF8', 'LLIL_STORE.q(LLIL_REG.q(x21),LLIL_ADD.q(LLIL_REG.q(x29),LLIL_LOAD.q(LLIL_REG.q(x21))))'),
+ # staddl x6, [x29] STADDL_LDADDL_64_memop
+ (b'\xBF\x03\x66\xF8', 'LLIL_STORE.q(LLIL_REG.q(x29),LLIL_ADD.q(LLIL_REG.q(x6),LLIL_LOAD.q(LLIL_REG.q(x29))))'),
+ # stadd w3, [x6] STADD_LDADD_32_memop
+ (b'\xDF\x00\x23\xB8', 'LLIL_STORE.q(LLIL_REG.q(x6),LLIL_ADD.d(LLIL_REG.d(w3),LLIL_LOAD.d(LLIL_REG.q(x6))))'),
+ # stadd w29, [x12] STADD_LDADD_32_memop
+ (b'\x9F\x01\x3D\xB8', 'LLIL_STORE.q(LLIL_REG.q(x12),LLIL_ADD.d(LLIL_REG.d(w29),LLIL_LOAD.d(LLIL_REG.q(x12))))'),
+ # stadd w27, [x5] STADD_LDADD_32_memop
+ (b'\xBF\x00\x3B\xB8', 'LLIL_STORE.q(LLIL_REG.q(x5),LLIL_ADD.d(LLIL_REG.d(w27),LLIL_LOAD.d(LLIL_REG.q(x5))))'),
+ # stadd wzr, [x30] STADD_LDADD_32_memop
+ (b'\xDF\x03\x3F\xB8', 'LLIL_STORE.q(LLIL_REG.q(x30),LLIL_ADD.d(LLIL_CONST.d(0x0),LLIL_LOAD.d(LLIL_REG.q(x30))))'),
+ # stadd wzr, [sp] STADD_LDADD_32_memop
+ (b'\xFF\x03\x3F\xB8', 'LLIL_STORE.q(LLIL_REG.q(sp),LLIL_ADD.d(LLIL_CONST.d(0x0),LLIL_LOAD.d(LLIL_REG.q(sp))))'),
+ # stadd wzr, [x9] STADD_LDADD_32_memop
+ (b'\x3F\x01\x3F\xB8', 'LLIL_STORE.q(LLIL_REG.q(x9),LLIL_ADD.d(LLIL_CONST.d(0x0),LLIL_LOAD.d(LLIL_REG.q(x9))))'),
+ # stadd w11, [x21] STADD_LDADD_32_memop
+ (b'\xBF\x02\x2B\xB8', 'LLIL_STORE.q(LLIL_REG.q(x21),LLIL_ADD.d(LLIL_REG.d(w11),LLIL_LOAD.d(LLIL_REG.q(x21))))'),
+ # stadd w4, [x15] STADD_LDADD_32_memop
+ (b'\xFF\x01\x24\xB8', 'LLIL_STORE.q(LLIL_REG.q(x15),LLIL_ADD.d(LLIL_REG.d(w4),LLIL_LOAD.d(LLIL_REG.q(x15))))'),
+ # stadd xzr, [x16] STADD_LDADD_64_memop
+ (b'\x1F\x02\x3F\xF8', 'LLIL_STORE.q(LLIL_REG.q(x16),LLIL_ADD.q(LLIL_CONST.q(0x0),LLIL_LOAD.q(LLIL_REG.q(x16))))'),
+ # stadd x19, [x15] STADD_LDADD_64_memop
+ (b'\xFF\x01\x33\xF8', 'LLIL_STORE.q(LLIL_REG.q(x15),LLIL_ADD.q(LLIL_REG.q(x19),LLIL_LOAD.q(LLIL_REG.q(x15))))'),
+ # stadd xzr, [x24] STADD_LDADD_64_memop
+ (b'\x1F\x03\x3F\xF8', 'LLIL_STORE.q(LLIL_REG.q(x24),LLIL_ADD.q(LLIL_CONST.q(0x0),LLIL_LOAD.q(LLIL_REG.q(x24))))'),
+ # stadd x8, [x25] STADD_LDADD_64_memop
+ (b'\x3F\x03\x28\xF8', 'LLIL_STORE.q(LLIL_REG.q(x25),LLIL_ADD.q(LLIL_REG.q(x8),LLIL_LOAD.q(LLIL_REG.q(x25))))'),
+ # stadd x26, [x4] STADD_LDADD_64_memop
+ (b'\x9F\x00\x3A\xF8', 'LLIL_STORE.q(LLIL_REG.q(x4),LLIL_ADD.q(LLIL_REG.q(x26),LLIL_LOAD.q(LLIL_REG.q(x4))))'),
+ # stadd x28, [x9] STADD_LDADD_64_memop
+ (b'\x3F\x01\x3C\xF8', 'LLIL_STORE.q(LLIL_REG.q(x9),LLIL_ADD.q(LLIL_REG.q(x28),LLIL_LOAD.q(LLIL_REG.q(x9))))'),
+ # stadd x28, [x22] STADD_LDADD_64_memop
+ (b'\xDF\x02\x3C\xF8', 'LLIL_STORE.q(LLIL_REG.q(x22),LLIL_ADD.q(LLIL_REG.q(x28),LLIL_LOAD.q(LLIL_REG.q(x22))))'),
+ # stadd x19, [x22] STADD_LDADD_64_memop
+ (b'\xDF\x02\x33\xF8', 'LLIL_STORE.q(LLIL_REG.q(x22),LLIL_ADD.q(LLIL_REG.q(x19),LLIL_LOAD.q(LLIL_REG.q(x22))))'),
]
tests_swp = [
@@ -1447,7 +1514,137 @@ tests_swp = [
]
tests_dup = [
- # dup v7.16b, w30 DUP_ASIMDINS_DR_R
+ # # dup v7.16b, w30 DUP_ASIMDINS_DR_R
+ # (b'\xC7\x0F\x15\x4E', 'LLIL_SET_REG.b(v7.b[0],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ # ' LLIL_SET_REG.b(v7.b[1],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ # ' LLIL_SET_REG.b(v7.b[2],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ # ' LLIL_SET_REG.b(v7.b[3],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ # ' LLIL_SET_REG.b(v7.b[4],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ # ' LLIL_SET_REG.b(v7.b[5],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ # ' LLIL_SET_REG.b(v7.b[6],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ # ' LLIL_SET_REG.b(v7.b[7],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ # ' LLIL_SET_REG.b(v7.b[8],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ # ' LLIL_SET_REG.b(v7.b[9],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ # ' LLIL_SET_REG.b(v7.b[10],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ # ' LLIL_SET_REG.b(v7.b[11],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ # ' LLIL_SET_REG.b(v7.b[12],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ # ' LLIL_SET_REG.b(v7.b[13],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ # ' LLIL_SET_REG.b(v7.b[14],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ # ' LLIL_SET_REG.b(v7.b[15],LLIL_LOW_PART.b(LLIL_REG.d(w30)))'),
+ # # dup v4.8b, w12 DUP_ASIMDINS_DR_R
+ # (b'\x84\x0D\x07\x0E', 'LLIL_SET_REG.b(v4.b[0],LLIL_LOW_PART.b(LLIL_REG.d(w12)));' + \
+ # ' LLIL_SET_REG.b(v4.b[1],LLIL_LOW_PART.b(LLIL_REG.d(w12)));' + \
+ # ' LLIL_SET_REG.b(v4.b[2],LLIL_LOW_PART.b(LLIL_REG.d(w12)));' + \
+ # ' LLIL_SET_REG.b(v4.b[3],LLIL_LOW_PART.b(LLIL_REG.d(w12)));' + \
+ # ' LLIL_SET_REG.b(v4.b[4],LLIL_LOW_PART.b(LLIL_REG.d(w12)));' + \
+ # ' LLIL_SET_REG.b(v4.b[5],LLIL_LOW_PART.b(LLIL_REG.d(w12)));' + \
+ # ' LLIL_SET_REG.b(v4.b[6],LLIL_LOW_PART.b(LLIL_REG.d(w12)));' + \
+ # ' LLIL_SET_REG.b(v4.b[7],LLIL_LOW_PART.b(LLIL_REG.d(w12)))'),
+ # # dup v24.4h, w11 DUP_ASIMDINS_DR_R
+ # (b'\x78\x0D\x02\x0E', 'LLIL_SET_REG.w(v24.h[0],LLIL_LOW_PART.w(LLIL_REG.d(w11)));' + \
+ # ' LLIL_SET_REG.w(v24.h[1],LLIL_LOW_PART.w(LLIL_REG.d(w11)));' + \
+ # ' LLIL_SET_REG.w(v24.h[2],LLIL_LOW_PART.w(LLIL_REG.d(w11)));' + \
+ # ' LLIL_SET_REG.w(v24.h[3],LLIL_LOW_PART.w(LLIL_REG.d(w11)))'),
+ # # dup v27.8h, w3 DUP_ASIMDINS_DR_R
+ # (b'\x7B\x0C\x0A\x4E', 'LLIL_SET_REG.w(v27.h[0],LLIL_LOW_PART.w(LLIL_REG.d(w3)));' + \
+ # ' LLIL_SET_REG.w(v27.h[1],LLIL_LOW_PART.w(LLIL_REG.d(w3)));' + \
+ # ' LLIL_SET_REG.w(v27.h[2],LLIL_LOW_PART.w(LLIL_REG.d(w3)));' + \
+ # ' LLIL_SET_REG.w(v27.h[3],LLIL_LOW_PART.w(LLIL_REG.d(w3)));' + \
+ # ' LLIL_SET_REG.w(v27.h[4],LLIL_LOW_PART.w(LLIL_REG.d(w3)));' + \
+ # ' LLIL_SET_REG.w(v27.h[5],LLIL_LOW_PART.w(LLIL_REG.d(w3)));' + \
+ # ' LLIL_SET_REG.w(v27.h[6],LLIL_LOW_PART.w(LLIL_REG.d(w3)));' + \
+ # ' LLIL_SET_REG.w(v27.h[7],LLIL_LOW_PART.w(LLIL_REG.d(w3)))'),
+ # # dup v1.16b, v0.b[1]
+ # (b'\x01\x04\x03\x4E', 'LLIL_INTRINSIC([v1],vdupq_laneq_s8,[LLIL_REG.o(v0),LLIL_CONST.b(0x1)])'),
+ # # dup V3.8B, V23.B[2]
+ # (b'\xE3\x06\x05\x0E', 'LLIL_INTRINSIC([v3],vdup_laneq_s8,[LLIL_REG.o(v23),LLIL_CONST.b(0x2)])'),
+ # # dup v5.4s, v3.s[3]
+ # (b'\x65\x04\x1C\x4E', 'LLIL_INTRINSIC([v5],vdupq_laneq_s32,[LLIL_REG.o(v3),LLIL_CONST.b(0x3)])'),
+ # # dup V30.2S, V18.S[0]
+ # (b'\x5E\x06\x04\x0E', 'LLIL_INTRINSIC([v30],vdup_laneq_s32,[LLIL_REG.o(v18),LLIL_CONST.b(0x0)])'),
+ # # dup v16.2d, v16.d[0]
+ # (b'\x10\x06\x08\x4E', 'LLIL_INTRINSIC([v16],vdupq_laneq_s64,[LLIL_REG.o(v16),LLIL_CONST.b(0x0)])'),
+ # # dup V24.4H, V6.H[3]
+ # (b'\xD8\x04\x0E\x0E', 'LLIL_INTRINSIC([v24],vdup_laneq_s16,[LLIL_REG.o(v6),LLIL_CONST.b(0x3)])'),
+ # # dup v24.8h, v6.h[3]
+ # (b'\xd8\x04\x0e\x4e', 'LLIL_INTRINSIC([v24],vdupq_laneq_s16,[LLIL_REG.o(v6),LLIL_CONST.b(0x3)])'),
+ # # dup s6, v8.s[0]
+ # (b'\x06\x05\x04\x5E', 'LLIL_INTRINSIC([s6],vdups_laneq_s32,[LLIL_REG.o(v8),LLIL_CONST.b(0x0)])'),
+ # # dup b1, v4.b[9]
+ # (b'\x81\x04\x13\x5E', 'LLIL_INTRINSIC([b1],vdupb_laneq_s8,[LLIL_REG.o(v4),LLIL_CONST.b(0x9)])'),
+ # # dup h24, v13.h[0]
+ # (b'\xB8\x05\x02\x5E', 'LLIL_INTRINSIC([h24],vduph_laneq_s16,[LLIL_REG.o(v13),LLIL_CONST.b(0x0)])'),
+ # # dup d4, v13.d[0]
+ # (b'\xA4\x05\x08\x5E', 'LLIL_INTRINSIC([d4],vdupd_laneq_s64,[LLIL_REG.o(v13),LLIL_CONST.b(0x0)])')
+
+ # dup v3.16b, v23.b[2] DUP_asimdins_DV_v
+ (b'\xE3\x06\x05\x4E', 'LLIL_INTRINSIC([v3],vdupq_laneq_s8,[LLIL_REG.o(v23),LLIL_CONST.b(0x2)])'),
+ # dup v18.16b, v11.b[11] DUP_asimdins_DV_v
+ (b'\x72\x05\x17\x4E', 'LLIL_INTRINSIC([v18],vdupq_laneq_s8,[LLIL_REG.o(v11),LLIL_CONST.b(0xB)])'),
+ # dup v30.4s, v18.s[0] DUP_asimdins_DV_v
+ (b'\x5E\x06\x04\x4E', 'LLIL_INTRINSIC([v30],vdupq_laneq_s32,[LLIL_REG.o(v18),LLIL_CONST.b(0x0)])'),
+ # dup v24.8h, v6.h[3] DUP_asimdins_DV_v
+ (b'\xD8\x04\x0E\x4E', 'LLIL_INTRINSIC([v24],vdupq_laneq_s16,[LLIL_REG.o(v6),LLIL_CONST.b(0x3)])'),
+ # dup v20.16b, v28.b[9] DUP_asimdins_DV_v
+ (b'\x94\x07\x13\x4E', 'LLIL_INTRINSIC([v20],vdupq_laneq_s8,[LLIL_REG.o(v28),LLIL_CONST.b(0x9)])'),
+ # dup v13.2d, v16.d[1] DUP_asimdins_DV_v
+ (b'\x0D\x06\x18\x4E', 'LLIL_INTRINSIC([v13],vdupq_laneq_s64,[LLIL_REG.o(v16),LLIL_CONST.b(0x1)])'),
+ # dup v1.16b, v1.b[14] DUP_asimdins_DV_v
+ (b'\x21\x04\x1D\x4E', 'LLIL_INTRINSIC([v1],vdupq_laneq_s8,[LLIL_REG.o(v1),LLIL_CONST.b(0xE)])'),
+ # dup v6.16b, v30.b[12] DUP_asimdins_DV_v
+ (b'\xC6\x07\x19\x4E', 'LLIL_INTRINSIC([v6],vdupq_laneq_s8,[LLIL_REG.o(v30),LLIL_CONST.b(0xC)])'),
+ # dup v29.16b, w17 DUP_asimdins_DR_r
+ (b'\x3D\x0E\x01\x4E', 'LLIL_SET_REG.b(v29.b[0],LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_SET_REG.b(v29.b[1],LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_SET_REG.b(v29.b[2],LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_SET_REG.b(v29.b[3],LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_SET_REG.b(v29.b[4],LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_SET_REG.b(v29.b[5],LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_SET_REG.b(v29.b[6],LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_SET_REG.b(v29.b[7],LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_SET_REG.b(v29.b[8],LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_SET_REG.b(v29.b[9],LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_SET_REG.b(v29.b[10],LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_SET_REG.b(v29.b[11],LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_SET_REG.b(v29.b[12],LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_SET_REG.b(v29.b[13],LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_SET_REG.b(v29.b[14],LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_SET_REG.b(v29.b[15],LLIL_LOW_PART.b(LLIL_REG.d(w17)))'),
+ # dup v1.16b, w10 DUP_asimdins_DR_r
+ (b'\x41\x0D\x03\x4E', 'LLIL_SET_REG.b(v1.b[0],LLIL_LOW_PART.b(LLIL_REG.d(w10)));' + \
+ ' LLIL_SET_REG.b(v1.b[1],LLIL_LOW_PART.b(LLIL_REG.d(w10)));' + \
+ ' LLIL_SET_REG.b(v1.b[2],LLIL_LOW_PART.b(LLIL_REG.d(w10)));' + \
+ ' LLIL_SET_REG.b(v1.b[3],LLIL_LOW_PART.b(LLIL_REG.d(w10)));' + \
+ ' LLIL_SET_REG.b(v1.b[4],LLIL_LOW_PART.b(LLIL_REG.d(w10)));' + \
+ ' LLIL_SET_REG.b(v1.b[5],LLIL_LOW_PART.b(LLIL_REG.d(w10)));' + \
+ ' LLIL_SET_REG.b(v1.b[6],LLIL_LOW_PART.b(LLIL_REG.d(w10)));' + \
+ ' LLIL_SET_REG.b(v1.b[7],LLIL_LOW_PART.b(LLIL_REG.d(w10)));' + \
+ ' LLIL_SET_REG.b(v1.b[8],LLIL_LOW_PART.b(LLIL_REG.d(w10)));' + \
+ ' LLIL_SET_REG.b(v1.b[9],LLIL_LOW_PART.b(LLIL_REG.d(w10)));' + \
+ ' LLIL_SET_REG.b(v1.b[10],LLIL_LOW_PART.b(LLIL_REG.d(w10)));' + \
+ ' LLIL_SET_REG.b(v1.b[11],LLIL_LOW_PART.b(LLIL_REG.d(w10)));' + \
+ ' LLIL_SET_REG.b(v1.b[12],LLIL_LOW_PART.b(LLIL_REG.d(w10)));' + \
+ ' LLIL_SET_REG.b(v1.b[13],LLIL_LOW_PART.b(LLIL_REG.d(w10)));' + \
+ ' LLIL_SET_REG.b(v1.b[14],LLIL_LOW_PART.b(LLIL_REG.d(w10)));' + \
+ ' LLIL_SET_REG.b(v1.b[15],LLIL_LOW_PART.b(LLIL_REG.d(w10)))'),
+ # dup v10.16b, w29 DUP_asimdins_DR_r
+ (b'\xAA\x0F\x15\x4E', 'LLIL_SET_REG.b(v10.b[0],LLIL_LOW_PART.b(LLIL_REG.d(w29)));' + \
+ ' LLIL_SET_REG.b(v10.b[1],LLIL_LOW_PART.b(LLIL_REG.d(w29)));' + \
+ ' LLIL_SET_REG.b(v10.b[2],LLIL_LOW_PART.b(LLIL_REG.d(w29)));' + \
+ ' LLIL_SET_REG.b(v10.b[3],LLIL_LOW_PART.b(LLIL_REG.d(w29)));' + \
+ ' LLIL_SET_REG.b(v10.b[4],LLIL_LOW_PART.b(LLIL_REG.d(w29)));' + \
+ ' LLIL_SET_REG.b(v10.b[5],LLIL_LOW_PART.b(LLIL_REG.d(w29)));' + \
+ ' LLIL_SET_REG.b(v10.b[6],LLIL_LOW_PART.b(LLIL_REG.d(w29)));' + \
+ ' LLIL_SET_REG.b(v10.b[7],LLIL_LOW_PART.b(LLIL_REG.d(w29)));' + \
+ ' LLIL_SET_REG.b(v10.b[8],LLIL_LOW_PART.b(LLIL_REG.d(w29)));' + \
+ ' LLIL_SET_REG.b(v10.b[9],LLIL_LOW_PART.b(LLIL_REG.d(w29)));' + \
+ ' LLIL_SET_REG.b(v10.b[10],LLIL_LOW_PART.b(LLIL_REG.d(w29)));' + \
+ ' LLIL_SET_REG.b(v10.b[11],LLIL_LOW_PART.b(LLIL_REG.d(w29)));' + \
+ ' LLIL_SET_REG.b(v10.b[12],LLIL_LOW_PART.b(LLIL_REG.d(w29)));' + \
+ ' LLIL_SET_REG.b(v10.b[13],LLIL_LOW_PART.b(LLIL_REG.d(w29)));' + \
+ ' LLIL_SET_REG.b(v10.b[14],LLIL_LOW_PART.b(LLIL_REG.d(w29)));' + \
+ ' LLIL_SET_REG.b(v10.b[15],LLIL_LOW_PART.b(LLIL_REG.d(w29)))'),
+ # dup v7.16b, w30 DUP_asimdins_DR_r
(b'\xC7\x0F\x15\x4E', 'LLIL_SET_REG.b(v7.b[0],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
' LLIL_SET_REG.b(v7.b[1],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
' LLIL_SET_REG.b(v7.b[2],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
@@ -1464,7 +1661,7 @@ tests_dup = [
' LLIL_SET_REG.b(v7.b[13],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
' LLIL_SET_REG.b(v7.b[14],LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
' LLIL_SET_REG.b(v7.b[15],LLIL_LOW_PART.b(LLIL_REG.d(w30)))'),
- # dup v4.8b, w12 DUP_ASIMDINS_DR_R
+ # dup v4.8b, w12 DUP_asimdins_DR_r
(b'\x84\x0D\x07\x0E', 'LLIL_SET_REG.b(v4.b[0],LLIL_LOW_PART.b(LLIL_REG.d(w12)));' + \
' LLIL_SET_REG.b(v4.b[1],LLIL_LOW_PART.b(LLIL_REG.d(w12)));' + \
' LLIL_SET_REG.b(v4.b[2],LLIL_LOW_PART.b(LLIL_REG.d(w12)));' + \
@@ -1473,12 +1670,21 @@ tests_dup = [
' LLIL_SET_REG.b(v4.b[5],LLIL_LOW_PART.b(LLIL_REG.d(w12)));' + \
' LLIL_SET_REG.b(v4.b[6],LLIL_LOW_PART.b(LLIL_REG.d(w12)));' + \
' LLIL_SET_REG.b(v4.b[7],LLIL_LOW_PART.b(LLIL_REG.d(w12)))'),
- # dup v24.4h, w11 DUP_ASIMDINS_DR_R
+ # dup v24.4h, w11 DUP_asimdins_DR_r
(b'\x78\x0D\x02\x0E', 'LLIL_SET_REG.w(v24.h[0],LLIL_LOW_PART.w(LLIL_REG.d(w11)));' + \
' LLIL_SET_REG.w(v24.h[1],LLIL_LOW_PART.w(LLIL_REG.d(w11)));' + \
' LLIL_SET_REG.w(v24.h[2],LLIL_LOW_PART.w(LLIL_REG.d(w11)));' + \
' LLIL_SET_REG.w(v24.h[3],LLIL_LOW_PART.w(LLIL_REG.d(w11)))'),
- # dup v27.8h, w3 DUP_ASIMDINS_DR_R
+ # dup v18.8h, w2 DUP_asimdins_DR_r
+ (b'\x52\x0C\x0E\x4E', 'LLIL_SET_REG.w(v18.h[0],LLIL_LOW_PART.w(LLIL_REG.d(w2)));' + \
+ ' LLIL_SET_REG.w(v18.h[1],LLIL_LOW_PART.w(LLIL_REG.d(w2)));' + \
+ ' LLIL_SET_REG.w(v18.h[2],LLIL_LOW_PART.w(LLIL_REG.d(w2)));' + \
+ ' LLIL_SET_REG.w(v18.h[3],LLIL_LOW_PART.w(LLIL_REG.d(w2)));' + \
+ ' LLIL_SET_REG.w(v18.h[4],LLIL_LOW_PART.w(LLIL_REG.d(w2)));' + \
+ ' LLIL_SET_REG.w(v18.h[5],LLIL_LOW_PART.w(LLIL_REG.d(w2)));' + \
+ ' LLIL_SET_REG.w(v18.h[6],LLIL_LOW_PART.w(LLIL_REG.d(w2)));' + \
+ ' LLIL_SET_REG.w(v18.h[7],LLIL_LOW_PART.w(LLIL_REG.d(w2)))'),
+ # dup v27.8h, w3 DUP_asimdins_DR_r
(b'\x7B\x0C\x0A\x4E', 'LLIL_SET_REG.w(v27.h[0],LLIL_LOW_PART.w(LLIL_REG.d(w3)));' + \
' LLIL_SET_REG.w(v27.h[1],LLIL_LOW_PART.w(LLIL_REG.d(w3)));' + \
' LLIL_SET_REG.w(v27.h[2],LLIL_LOW_PART.w(LLIL_REG.d(w3)));' + \
@@ -1487,28 +1693,22 @@ tests_dup = [
' LLIL_SET_REG.w(v27.h[5],LLIL_LOW_PART.w(LLIL_REG.d(w3)));' + \
' LLIL_SET_REG.w(v27.h[6],LLIL_LOW_PART.w(LLIL_REG.d(w3)));' + \
' LLIL_SET_REG.w(v27.h[7],LLIL_LOW_PART.w(LLIL_REG.d(w3)))'),
- # dup v1.16b, v0.b[1]
- (b'\x01\x04\x03\x4E', 'LLIL_INTRINSIC([v1],vdupq_laneq_s8,[LLIL_REG.o(v0),LLIL_CONST.b(0x1)])'),
- # dup V3.8B, V23.B[2]
- (b'\xE3\x06\x05\x0E', 'LLIL_INTRINSIC([v3],vdup_laneq_s8,[LLIL_REG.o(v23),LLIL_CONST.b(0x2)])'),
- # dup v5.4s, v3.s[3]
- (b'\x65\x04\x1C\x4E', 'LLIL_INTRINSIC([v5],vdupq_laneq_s32,[LLIL_REG.o(v3),LLIL_CONST.b(0x3)])'),
- # dup V30.2S, V18.S[0]
- (b'\x5E\x06\x04\x0E', 'LLIL_INTRINSIC([v30],vdup_laneq_s32,[LLIL_REG.o(v18),LLIL_CONST.b(0x0)])'),
- # dup v16.2d, v16.d[0]
- (b'\x10\x06\x08\x4E', 'LLIL_INTRINSIC([v16],vdupq_laneq_s64,[LLIL_REG.o(v16),LLIL_CONST.b(0x0)])'),
- # dup V24.4H, V6.H[3]
- (b'\xD8\x04\x0E\x0E', 'LLIL_INTRINSIC([v24],vdup_laneq_s16,[LLIL_REG.o(v6),LLIL_CONST.b(0x3)])'),
- # dup v24.8h, v6.h[3]
- (b'\xd8\x04\x0e\x4e', 'LLIL_INTRINSIC([v24],vdupq_laneq_s16,[LLIL_REG.o(v6),LLIL_CONST.b(0x3)])'),
- # dup s6, v8.s[0]
- (b'\x06\x05\x04\x5E', 'LLIL_INTRINSIC([s6],vdups_laneq_s32,[LLIL_REG.o(v8),LLIL_CONST.b(0x0)])'),
- # dup b1, v4.b[9]
- (b'\x81\x04\x13\x5E', 'LLIL_INTRINSIC([b1],vdupb_laneq_s8,[LLIL_REG.o(v4),LLIL_CONST.b(0x9)])'),
- # dup h24, v13.h[0]
- (b'\xB8\x05\x02\x5E', 'LLIL_INTRINSIC([h24],vduph_laneq_s16,[LLIL_REG.o(v13),LLIL_CONST.b(0x0)])'),
- # dup d4, v13.d[0]
- (b'\xA4\x05\x08\x5E', 'LLIL_INTRINSIC([d4],vdupd_laneq_s64,[LLIL_REG.o(v13),LLIL_CONST.b(0x0)])')
+ # mov s6, v8.s[0] MOV_DUP_asisdone_only
+ (b'\x06\x05\x04\x5E', 'LLIL_SET_REG.d(s6,LLIL_REG.d(v8.s[0]))'),
+ # mov b1, v4.b[9] MOV_DUP_asisdone_only
+ (b'\x81\x04\x13\x5E', 'LLIL_SET_REG.b(b1,LLIL_REG.b(v4.b[9]))'),
+ # mov h24, v13.h[0] MOV_DUP_asisdone_only
+ (b'\xB8\x05\x02\x5E', 'LLIL_SET_REG.w(h24,LLIL_REG.w(v13.h[0]))'),
+ # mov h16, v19.h[7] MOV_DUP_asisdone_only
+ (b'\x70\x06\x1E\x5E', 'LLIL_SET_REG.w(h16,LLIL_REG.w(v19.h[7]))'),
+ # mov h16, v6.h[6] MOV_DUP_asisdone_only
+ (b'\xD0\x04\x1A\x5E', 'LLIL_SET_REG.w(h16,LLIL_REG.w(v6.h[6]))'),
+ # mov b27, v2.b[1] MOV_DUP_asisdone_only
+ (b'\x5B\x04\x03\x5E', 'LLIL_SET_REG.b(b27,LLIL_REG.b(v2.b[1]))'),
+ # mov b14, v22.b[6] MOV_DUP_asisdone_only
+ (b'\xCE\x06\x0D\x5E', 'LLIL_SET_REG.b(b14,LLIL_REG.b(v22.b[6]))'),
+ # mov b4, v3.b[11] MOV_DUP_asisdone_only
+ (b'\x64\x04\x17\x5E', 'LLIL_SET_REG.b(b4,LLIL_REG.b(v3.b[11]))'),
]
tests_stlr = [
@@ -1607,6 +1807,47 @@ tests_mov = [
(b'\x20\x1C\xA1\x0E', 'LLIL_SET_REG.q(v0.d[0],LLIL_REG.q(v1.d[0]))'),
]
+tests_mov_add = [
+ # mov w14, wsp MOV_ADD_32_addsub_imm
+ (b'\xEE\x03\x00\x11', 'LLIL_SET_REG.d(w14,LLIL_REG.d(wsp))'),
+ # mov wsp, w28 MOV_ADD_32_addsub_imm
+ (b'\x9F\x03\x00\x11', 'LLIL_SET_REG.d(wsp,LLIL_REG.d(w28))'),
+ # mov w29, wsp MOV_ADD_32_addsub_imm
+ (b'\xFD\x03\x00\x11', 'LLIL_SET_REG.d(w29,LLIL_REG.d(wsp))'),
+ # mov x5, sp MOV_ADD_64_addsub_imm
+ (b'\xE5\x03\x00\x91', 'LLIL_SET_REG.q(x5,LLIL_REG.q(sp))'),
+ # mov sp, x6 MOV_ADD_64_addsub_imm
+ (b'\xDF\x00\x00\x91', 'LLIL_SET_REG.q(sp,LLIL_REG.q(x6))'),
+ # mov x20, sp MOV_ADD_64_addsub_imm
+ (b'\xF4\x03\x00\x91', 'LLIL_SET_REG.q(x20,LLIL_REG.q(sp))'),
+]
+
+tests_mov_dup_ins = [
+ # mov s6, v8.s[0] MOV_DUP_asisdone_only
+ (b'\x06\x05\x04\x5E', 'LLIL_SET_REG.d(s6,LLIL_REG.d(v8.s[0]))'),
+ # mov b1, v4.b[9] MOV_DUP_asisdone_only
+ (b'\x81\x04\x13\x5E', 'LLIL_SET_REG.b(b1,LLIL_REG.b(v4.b[9]))'),
+ # mov h24, v13.h[0] MOV_DUP_asisdone_only
+ (b'\xB8\x05\x02\x5E', 'LLIL_SET_REG.w(h24,LLIL_REG.w(v13.h[0]))'),
+ # mov v5.h[3], w29 MOV_INS_asimdins_IR_r
+ (b'\xA5\x1F\x0E\x4E', 'LLIL_SET_REG.w(v5.h[3],LLIL_REG.d(w29))'),
+ # mov v25.h[3], w10 MOV_INS_asimdins_IR_r
+ (b'\x59\x1D\x0E\x4E', 'LLIL_SET_REG.w(v25.h[3],LLIL_REG.d(w10))'),
+ # mov v3.b[14], w12 MOV_INS_asimdins_IR_r
+ (b'\x83\x1D\x1D\x4E', 'LLIL_SET_REG.b(v3.b[14],LLIL_REG.d(w12))'),
+ # mov v7.b[5], w11 MOV_INS_asimdins_IR_r
+ (b'\x67\x1D\x0B\x4E', 'LLIL_SET_REG.b(v7.b[5],LLIL_REG.d(w11))'),
+ # mov v4.h[1], v7.h[0] MOV_INS_asimdins_IV_v
+ (b'\xE4\x0C\x06\x6E', 'LLIL_SET_REG.w(v4.h[1],LLIL_REG.w(v7.h[0]))'),
+ # mov v17.h[5], v14.h[3] MOV_INS_asimdins_IV_v
+ (b'\xD1\x3D\x16\x6E', 'LLIL_SET_REG.w(v17.h[5],LLIL_REG.w(v14.h[3]))'),
+ # mov v6.b[15], v3.b[0] MOV_INS_asimdins_IV_v
+ (b'\x66\x04\x1F\x6E', 'LLIL_SET_REG.b(v6.b[15],LLIL_REG.b(v3.b[0]))'),
+ # mov v24.b[4], v12.b[12] MOV_INS_asimdins_IV_v
+ (b'\x98\x65\x09\x6E', 'LLIL_SET_REG.b(v24.b[4],LLIL_REG.b(v12.b[12]))'),
+]
+
+
tests_movi = [
# movi v4.2d, #0xffffff0000ffff MOVI_ASIMDIMM_D2_D
(b'\x64\xE6\x03\x6F', 'LLIL_SET_REG.q(v4.d[0],LLIL_CONST.q(0xFFFFFF0000FFFF));' + \
@@ -1682,6 +1923,162 @@ tests_movi = [
' LLIL_SET_REG.b(v19.b[15],LLIL_CONST.b(0x80))'),
]
+tests_movn = [
+ # movn w6, #0xffff MOVN_32_movewide
+ (b'\xE6\xFF\x9F\x12', 'LLIL_SET_REG.d(w6,LLIL_CONST.d(0xFFFF))'),
+ # movn w28, #0xffff, lsl #0x10 MOVN_32_movewide
+ (b'\xFC\xFF\xBF\x12', 'LLIL_SET_REG.d(w28,LLIL_CONST.d(0xFFFF0000))'),
+ # movn w9, #0xffff MOVN_32_movewide
+ (b'\xE9\xFF\x9F\x12', 'LLIL_SET_REG.d(w9,LLIL_CONST.d(0xFFFF))'),
+ # mov w0, #-0x5000 MOV_MOVN_32_movewide
+ (b'\xE0\xFF\x89\x12', 'LLIL_SET_REG.d(w0,LLIL_CONST.d(0xFFFFB000))'),
+ # mov w6, #0x74fbffff MOV_MOVN_32_movewide
+ (b'\x86\x60\xB1\x12', 'LLIL_SET_REG.d(w6,LLIL_CONST.d(0x74FBFFFF))'),
+ # mov w1, #-0xf160 MOV_MOVN_32_movewide
+ (b'\xE1\x2B\x9E\x12', 'LLIL_SET_REG.d(w1,LLIL_CONST.d(0xFFFF0EA0))'),
+ # movn x13, #0x0, lsl #0x30 MOVN_64_movewide
+ (b'\x0D\x00\xE0\x92', 'LLIL_SET_REG.q(x13,LLIL_CONST.q(0x0))'),
+ # movn x25, #0x0, lsl #0x10 MOVN_64_movewide
+ (b'\x19\x00\xA0\x92', 'LLIL_SET_REG.q(x25,LLIL_CONST.q(0x0))'),
+ # movn x17, #0x0, lsl #0x30 MOVN_64_movewide
+ (b'\x11\x00\xE0\x92', 'LLIL_SET_REG.q(x17,LLIL_CONST.q(0x0))'),
+ # mov x18, #0x6ad7ffffffffffff MOV_MOVN_64_movewide
+ (b'\x12\xA5\xF2\x92', 'LLIL_SET_REG.q(x18,LLIL_CONST.q(0x6AD7FFFFFFFFFFFF))'),
+ # mov x11, #-0x16310001 MOV_MOVN_64_movewide
+ (b'\x2B\xC6\xA2\x92', 'LLIL_SET_REG.q(x11,LLIL_CONST.q(0xFFFFFFFFE9CEFFFF))'),
+ # mov x9, #-0x3be100000001 MOV_MOVN_64_movewide
+ (b'\x29\x7C\xC7\x92', 'LLIL_SET_REG.q(x9,LLIL_CONST.q(0xFFFFC41EFFFFFFFF))'),
+]
+
+tests_movz = [
+ # mov w18, #0xe7b0000 MOV_MOVZ_32_movewide
+ (b'\x72\xCF\xA1\x52', 'LLIL_SET_REG.d(w18,LLIL_CONST.d(0xE7B0000))'),
+ # mov w6, #0x24180000 MOV_MOVZ_32_movewide
+ (b'\x06\x83\xA4\x52', 'LLIL_SET_REG.d(w6,LLIL_CONST.d(0x24180000))'),
+ # mov w21, #-0x2130000 MOV_MOVZ_32_movewide
+ (b'\xB5\xBD\xBF\x52', 'LLIL_SET_REG.d(w21,LLIL_CONST.d(0xFDED0000))'),
+ # mov x8, #-0x28a000000000000 MOV_MOVZ_64_movewide
+ (b'\xC8\xAE\xFF\xD2', 'LLIL_SET_REG.q(x8,LLIL_CONST.q(0xFD76000000000000))'),
+ # mov x27, #0x7edb00000000 MOV_MOVZ_64_movewide
+ (b'\x7B\xDB\xCF\xD2', 'LLIL_SET_REG.q(x27,LLIL_CONST.q(0x7EDB00000000))'),
+ # mov x18, #0x92c200000000 MOV_MOVZ_64_movewide
+ (b'\x52\x58\xD2\xD2', 'LLIL_SET_REG.q(x18,LLIL_CONST.q(0x92C200000000))'),
+]
+
+tests_orr = [
+ # mov w1, #0x10001 MOV_ORR_32_log_imm
+ (b'\xE1\x83\x30\x32', 'LLIL_SET_REG.d(w1,LLIL_CONST.d(0x10001))'),
+ # mov w6, #-0x3e003e01 MOV_ORR_32_log_imm
+ (b'\xE6\xAB\x32\x32', 'LLIL_SET_REG.d(w6,LLIL_CONST.d(0xC1FFC1FF))'),
+ # mov w22, #-0x3f3f3f40 MOV_ORR_32_log_imm
+ (b'\xF6\xC7\x32\x32', 'LLIL_SET_REG.d(w22,LLIL_CONST.d(0xC0C0C0C0))'),
+ # mov w7, w21 MOV_ORR_32_log_shift
+ (b'\xE7\x03\x15\x2A', 'LLIL_SET_REG.d(w7,LLIL_REG.d(w21))'),
+ # mov w8, w24 MOV_ORR_32_log_shift
+ (b'\xE8\x03\x18\x2A', 'LLIL_SET_REG.d(w8,LLIL_REG.d(w24))'),
+ # mov wzr, w13 MOV_ORR_32_log_shift
+ (b'\xFF\x03\x0D\x2A', 'LLIL_REG.d(w13)'),
+ # mov x5, #0xffffff00000000 MOV_ORR_64_log_imm
+ (b'\xE5\x5F\x60\xB2', 'LLIL_SET_REG.q(x5,LLIL_CONST.q(0xFFFFFF00000000))'),
+ # mov x30, #-0xffffffffffff01 MOV_ORR_64_log_imm
+ (b'\xFE\x3F\x48\xB2', 'LLIL_SET_REG.q(x30,LLIL_CONST.q(0xFF000000000000FF))'),
+ # mov x9, #0x7fffffffffffffe MOV_ORR_64_log_imm
+ (b'\xE9\xE7\x7F\xB2', 'LLIL_SET_REG.q(x9,LLIL_CONST.q(0x7FFFFFFFFFFFFFE))'),
+ # mov x9, xzr MOV_ORR_64_log_shift
+ (b'\xE9\x03\x1F\xAA', 'LLIL_SET_REG.q(x9,LLIL_CONST.q(0x0))'),
+ # mov x24, x17 MOV_ORR_64_log_shift
+ (b'\xF8\x03\x11\xAA', 'LLIL_SET_REG.q(x24,LLIL_REG.q(x17))'),
+ # mov x24, x23 MOV_ORR_64_log_shift
+ (b'\xF8\x03\x17\xAA', 'LLIL_SET_REG.q(x24,LLIL_REG.q(x23))'),
+ # mov v18.16b, v10.16b MOV_ORR_asimdsame_only
+ (b'\x52\x1D\xAA\x4E', 'LLIL_SET_REG.o(v18,LLIL_REG.o(v10))'),
+ # mov v31.8b, v6.8b MOV_ORR_asimdsame_only
+ (b'\xDF\x1C\xA6\x0E', 'LLIL_SET_REG.q(v31.d[0],LLIL_REG.q(v6.d[0]))'),
+ # mov v19.16b, v27.16b MOV_ORR_asimdsame_only
+ (b'\x73\x1F\xBB\x4E', 'LLIL_SET_REG.o(v19,LLIL_REG.o(v27))'),
+ # mov v19.8b, v8.8b MOV_ORR_asimdsame_only
+ (b'\x13\x1D\xA8\x0E', 'LLIL_SET_REG.q(v19.d[0],LLIL_REG.q(v8.d[0]))'),
+ # orr w25, w11, #0x2020202 ORR_32_log_imm
+ (b'\x79\xC1\x27\x32', 'LLIL_SET_REG.d(w25,LLIL_OR.d(LLIL_REG.d(w11),LLIL_CONST.d(0x2020202)))'),
+ # orr w16, w6, #0xfe000003 ORR_32_log_imm
+ (b'\xD0\x20\x27\x32', 'LLIL_SET_REG.d(w16,LLIL_OR.d(LLIL_REG.d(w6),LLIL_CONST.d(0xFE000003)))'),
+ # orr w20, w24, w3, asr #0x10 ORR_32_log_shift
+ (b'\x14\x43\x83\x2A', 'LLIL_SET_REG.d(w20,LLIL_OR.d(LLIL_REG.d(w24),LLIL_ASR.d(LLIL_REG.d(w3),LLIL_CONST.b(0x10))))'),
+ # orr w23, w27, w4, lsr #0x11 ORR_32_log_shift
+ (b'\x77\x47\x44\x2A', 'LLIL_SET_REG.d(w23,LLIL_OR.d(LLIL_REG.d(w27),LLIL_LSR.d(LLIL_REG.d(w4),LLIL_CONST.b(0x11))))'),
+ # orr w2, w25, w22, ror #0x1b ORR_32_log_shift
+ (b'\x22\x6F\xD6\x2A', 'LLIL_SET_REG.d(w2,LLIL_OR.d(LLIL_REG.d(w25),LLIL_ROR.d(LLIL_REG.d(w22),LLIL_CONST.b(0x1B))))'),
+ # orr x15, x16, #0x1fe01fe01fe01fe ORR_64_log_imm
+ (b'\x0F\x9E\x3F\xB2', 'LLIL_SET_REG.q(x15,LLIL_OR.q(LLIL_REG.q(x16),LLIL_CONST.q(0x1FE01FE01FE01FE)))'),
+ # orr x2, x28, #0xffffffffffffff8f ORR_64_log_imm
+ (b'\x82\xF3\x79\xB2', 'LLIL_SET_REG.q(x2,LLIL_OR.q(LLIL_REG.q(x28),LLIL_CONST.q(0xFFFFFFFFFFFFFF8F)))'),
+ # orr x20, x28, x0, asr #0x9 ORR_64_log_shift
+ (b'\x94\x27\x80\xAA', 'LLIL_SET_REG.q(x20,LLIL_OR.q(LLIL_REG.q(x28),LLIL_ASR.q(LLIL_REG.q(x0),LLIL_CONST.b(0x9))))'),
+ # orr x0, x10, x27, ror #0xb ORR_64_log_shift
+ (b'\x40\x2D\xDB\xAA', 'LLIL_SET_REG.q(x0,LLIL_OR.q(LLIL_REG.q(x10),LLIL_ROR.q(LLIL_REG.q(x27),LLIL_CONST.b(0xB))))'),
+ # orr x24, x0, x26, lsr #0xc ORR_64_log_shift
+ (b'\x18\x30\x5A\xAA', 'LLIL_SET_REG.q(x24,LLIL_OR.q(LLIL_REG.q(x0),LLIL_LSR.q(LLIL_REG.q(x26),LLIL_CONST.b(0xC))))'),
+ # orr v22.4h, #0x93, lsl #0x8 ORR_asimdimm_L_hl
+ (b'\x76\xB6\x04\x0F', 'LLIL_SET_REG.w(v22.h[0],LLIL_CONST.w(0x9300));' + \
+ ' LLIL_SET_REG.w(v22.h[1],LLIL_CONST.w(0x9300));' + \
+ ' LLIL_SET_REG.w(v22.h[2],LLIL_CONST.w(0x9300));' + \
+ ' LLIL_SET_REG.w(v22.h[3],LLIL_CONST.w(0x9300))'),
+ # orr v7.4h, #0xa9 ORR_asimdimm_L_hl
+ (b'\x27\x95\x05\x0F', 'LLIL_SET_REG.w(v7.h[0],LLIL_CONST.w(0xA9));' + \
+ ' LLIL_SET_REG.w(v7.h[1],LLIL_CONST.w(0xA9));' + \
+ ' LLIL_SET_REG.w(v7.h[2],LLIL_CONST.w(0xA9));' + \
+ ' LLIL_SET_REG.w(v7.h[3],LLIL_CONST.w(0xA9))'),
+ # orr v10.8h, #0x86 ORR_asimdimm_L_hl
+ (b'\xCA\x94\x04\x4F', 'LLIL_SET_REG.w(v10.h[0],LLIL_CONST.w(0x86));' + \
+ ' LLIL_SET_REG.w(v10.h[1],LLIL_CONST.w(0x86));' + \
+ ' LLIL_SET_REG.w(v10.h[2],LLIL_CONST.w(0x86));' + \
+ ' LLIL_SET_REG.w(v10.h[3],LLIL_CONST.w(0x86));' + \
+ ' LLIL_SET_REG.w(v10.h[4],LLIL_CONST.w(0x86));' + \
+ ' LLIL_SET_REG.w(v10.h[5],LLIL_CONST.w(0x86));' + \
+ ' LLIL_SET_REG.w(v10.h[6],LLIL_CONST.w(0x86));' + \
+ ' LLIL_SET_REG.w(v10.h[7],LLIL_CONST.w(0x86))'),
+ # orr v22.8h, #0x93, lsl #0x8 ORR_asimdimm_L_hl
+ (b'\x76\xB6\x04\x4F', 'LLIL_SET_REG.w(v22.h[0],LLIL_CONST.w(0x9300));' + \
+ ' LLIL_SET_REG.w(v22.h[1],LLIL_CONST.w(0x9300));' + \
+ ' LLIL_SET_REG.w(v22.h[2],LLIL_CONST.w(0x9300));' + \
+ ' LLIL_SET_REG.w(v22.h[3],LLIL_CONST.w(0x9300));' + \
+ ' LLIL_SET_REG.w(v22.h[4],LLIL_CONST.w(0x9300));' + \
+ ' LLIL_SET_REG.w(v22.h[5],LLIL_CONST.w(0x9300));' + \
+ ' LLIL_SET_REG.w(v22.h[6],LLIL_CONST.w(0x9300));' + \
+ ' LLIL_SET_REG.w(v22.h[7],LLIL_CONST.w(0x9300))'),
+ # orr v10.4s, #0x8 ORR_asimdimm_L_sl
+ (b'\x0A\x15\x00\x4F', 'LLIL_SET_REG.d(v10.s[0],LLIL_CONST.d(0x8));' + \
+ ' LLIL_SET_REG.d(v10.s[1],LLIL_CONST.d(0x8));' + \
+ ' LLIL_SET_REG.d(v10.s[2],LLIL_CONST.d(0x8));' + \
+ ' LLIL_SET_REG.d(v10.s[3],LLIL_CONST.d(0x8))'),
+ # orr v6.2s, #0x59, lsl #0x10 ORR_asimdimm_L_sl
+ (b'\x26\x57\x02\x0F', 'LLIL_SET_REG.d(v6.s[0],LLIL_CONST.d(0x590000));' + \
+ ' LLIL_SET_REG.d(v6.s[1],LLIL_CONST.d(0x590000))'),
+ # orr v31.2s, #0xca, lsl #0x8 ORR_asimdimm_L_sl
+ (b'\x5F\x35\x06\x0F', 'LLIL_SET_REG.d(v31.s[0],LLIL_CONST.d(0xCA00));' + \
+ ' LLIL_SET_REG.d(v31.s[1],LLIL_CONST.d(0xCA00))'),
+ # orr v20.4s, #0x59, lsl #0x18 ORR_asimdimm_L_sl
+ (b'\x34\x77\x02\x4F', 'LLIL_SET_REG.d(v20.s[0],LLIL_CONST.d(0x59000000));' + \
+ ' LLIL_SET_REG.d(v20.s[1],LLIL_CONST.d(0x59000000));' + \
+ ' LLIL_SET_REG.d(v20.s[2],LLIL_CONST.d(0x59000000));' + \
+ ' LLIL_SET_REG.d(v20.s[3],LLIL_CONST.d(0x59000000))'),
+]
+
+tests_umov = [
+ # mov w26, v25.s[0] MOV_UMOV_asimdins_W_w
+ (b'\x3A\x3F\x04\x0E', 'LLIL_SET_REG.d(w26,LLIL_ZX.d(LLIL_REG.d(v25.s[0])))'),
+ # mov w2, v29.s[1] MOV_UMOV_asimdins_W_w
+ (b'\xA2\x3F\x0C\x0E', 'LLIL_SET_REG.d(w2,LLIL_ZX.d(LLIL_REG.d(v29.s[1])))'),
+ # mov w6, v3.s[3] MOV_UMOV_asimdins_W_w
+ (b'\x66\x3C\x1C\x0E', 'LLIL_SET_REG.d(w6,LLIL_ZX.d(LLIL_REG.d(v3.s[3])))'),
+ # mov w24, v2.s[2] MOV_UMOV_asimdins_W_w
+ (b'\x58\x3C\x14\x0E', 'LLIL_SET_REG.d(w24,LLIL_ZX.d(LLIL_REG.d(v2.s[2])))'),
+ # mov x1, v16.d[0] MOV_UMOV_asimdins_X_x
+ (b'\x01\x3E\x08\x4E', 'LLIL_SET_REG.q(x1,LLIL_ZX.q(LLIL_REG.q(v16.d[0])))'),
+ # mov x2, v31.d[1] MOV_UMOV_asimdins_X_x
+ (b'\xE2\x3F\x18\x4E', 'LLIL_SET_REG.q(x2,LLIL_ZX.q(LLIL_REG.q(v31.d[1])))'),
+]
+
tests_fsub = [
# fsub d9, d7, d11 FSUB_D_FLOATDP2
(b'\xE9\x38\x6B\x1E', 'LLIL_SET_REG.q(d9,LLIL_FSUB.q(LLIL_REG.q(d7),LLIL_REG.q(d11)))'),
@@ -1696,114 +2093,48 @@ tests_fsub = [
# fsub s11, s12, s23 FSUB_S_FLOATDP2
(b'\x8B\x39\x37\x1E', 'LLIL_SET_REG.d(s11,LLIL_FSUB.d(LLIL_REG.d(s12),LLIL_REG.d(s23)))'),
# fsub v24.2s, v27.2s, v20.2s FSUB_ASIMDSAME_ONLY
- (b'\x78\xD7\xB4\x0E', 'LLIL_FSUB.d(LLIL_REG.d(v24.s[0]),LLIL_REG.d(v27.s[0]));' + \
- ' LLIL_FSUB.d(LLIL_REG.d(v24.s[1]),LLIL_REG.d(v27.s[1]))'),
+ (b'\x78\xD7\xB4\x0E', 'LLIL_INTRINSIC([v24],vsub_f32,[LLIL_REG.o(v27),LLIL_REG.o(v20)])'),
# fsub v5.4s, v16.4s, v15.4s FSUB_ASIMDSAME_ONLY
- (b'\x05\xD6\xAF\x4E', 'LLIL_FSUB.d(LLIL_REG.d(v5.s[0]),LLIL_REG.d(v16.s[0]));' + \
- ' LLIL_FSUB.d(LLIL_REG.d(v5.s[1]),LLIL_REG.d(v16.s[1]));' + \
- ' LLIL_FSUB.d(LLIL_REG.d(v5.s[2]),LLIL_REG.d(v16.s[2]));' + \
- ' LLIL_FSUB.d(LLIL_REG.d(v5.s[3]),LLIL_REG.d(v16.s[3]))'),
+ (b'\x05\xD6\xAF\x4E', 'LLIL_INTRINSIC([v5],vsubq_f32,[LLIL_REG.o(v16),LLIL_REG.o(v15)])'),
# fsub v10.8h, v29.8h, v3.8h FSUB_ASIMDSAMEFP16_ONLY
- (b'\xAA\x17\xC3\x4E', 'LLIL_FSUB.w(LLIL_REG.w(v10.h[0]),LLIL_REG.w(v29.h[0]));' + \
- ' LLIL_FSUB.w(LLIL_REG.w(v10.h[1]),LLIL_REG.w(v29.h[1]));' + \
- ' LLIL_FSUB.w(LLIL_REG.w(v10.h[2]),LLIL_REG.w(v29.h[2]));' + \
- ' LLIL_FSUB.w(LLIL_REG.w(v10.h[3]),LLIL_REG.w(v29.h[3]));' + \
- ' LLIL_FSUB.w(LLIL_REG.w(v10.h[4]),LLIL_REG.w(v29.h[4]));' + \
- ' LLIL_FSUB.w(LLIL_REG.w(v10.h[5]),LLIL_REG.w(v29.h[5]));' + \
- ' LLIL_FSUB.w(LLIL_REG.w(v10.h[6]),LLIL_REG.w(v29.h[6]));' + \
- ' LLIL_FSUB.w(LLIL_REG.w(v10.h[7]),LLIL_REG.w(v29.h[7]))'),
+ (b'\xAA\x17\xC3\x4E', 'LLIL_INTRINSIC([v10],vsubq_f16,[LLIL_REG.o(v29),LLIL_REG.o(v3)])'),
# fsub v24.4h, v27.4h, v17.4h FSUB_ASIMDSAMEFP16_ONLY
- (b'\x78\x17\xD1\x0E', 'LLIL_FSUB.w(LLIL_REG.w(v24.h[0]),LLIL_REG.w(v27.h[0]));' + \
- ' LLIL_FSUB.w(LLIL_REG.w(v24.h[1]),LLIL_REG.w(v27.h[1]));' + \
- ' LLIL_FSUB.w(LLIL_REG.w(v24.h[2]),LLIL_REG.w(v27.h[2]));' + \
- ' LLIL_FSUB.w(LLIL_REG.w(v24.h[3]),LLIL_REG.w(v27.h[3]))'),
+ (b'\x78\x17\xD1\x0E', 'LLIL_INTRINSIC([v24],vsub_f16,[LLIL_REG.o(v27),LLIL_REG.o(v17)])'),
]
tests_fmul = [
# fmul v7.2d, v20.2d, v1.2d FMUL_asimdsame_only
- (b'\x87\xDE\x61\x6E', 'LLIL_SET_REG.q(v7.d[0],LLIL_FMUL.q(LLIL_REG.q(v20.d[0]),LLIL_REG.q(v1.d[0])));' + \
- ' LLIL_SET_REG.q(v7.d[1],LLIL_FMUL.q(LLIL_REG.q(v20.d[1]),LLIL_REG.q(v1.d[1])))'),
+ (b'\x87\xDE\x61\x6E', 'LLIL_INTRINSIC([v7],vmulq_f64,[LLIL_REG.o(v20),LLIL_REG.o(v1),LLIL_CONST.b(0x0)])'),
# fmul v28.2s, v21.2s, v1.2s FMUL_asimdsame_only
- (b'\xBC\xDE\x21\x2E', 'LLIL_SET_REG.d(v28.s[0],LLIL_FMUL.d(LLIL_REG.d(v21.s[0]),LLIL_REG.d(v1.s[0])));' + \
- ' LLIL_SET_REG.d(v28.s[1],LLIL_FMUL.d(LLIL_REG.d(v21.s[1]),LLIL_REG.d(v1.s[1])))'),
+ (b'\xBC\xDE\x21\x2E', 'LLIL_INTRINSIC([v28],vmul_f32,[LLIL_REG.o(v21),LLIL_REG.o(v1),LLIL_CONST.b(0x0)])'),
# fmul v6.2s, v21.2s, v1.2s FMUL_asimdsame_only
- (b'\xA6\xDE\x21\x2E', 'LLIL_SET_REG.d(v6.s[0],LLIL_FMUL.d(LLIL_REG.d(v21.s[0]),LLIL_REG.d(v1.s[0])));' + \
- ' LLIL_SET_REG.d(v6.s[1],LLIL_FMUL.d(LLIL_REG.d(v21.s[1]),LLIL_REG.d(v1.s[1])))'),
+ (b'\xA6\xDE\x21\x2E', 'LLIL_INTRINSIC([v6],vmul_f32,[LLIL_REG.o(v21),LLIL_REG.o(v1),LLIL_CONST.b(0x0)])'),
# fmul v22.4s, v15.4s, v26.4s FMUL_asimdsame_only
- (b'\xF6\xDD\x3A\x6E', 'LLIL_SET_REG.d(v22.s[0],LLIL_FMUL.d(LLIL_REG.d(v15.s[0]),LLIL_REG.d(v26.s[0])));' + \
- ' LLIL_SET_REG.d(v22.s[1],LLIL_FMUL.d(LLIL_REG.d(v15.s[1]),LLIL_REG.d(v26.s[1])));' + \
- ' LLIL_SET_REG.d(v22.s[2],LLIL_FMUL.d(LLIL_REG.d(v15.s[2]),LLIL_REG.d(v26.s[2])));' + \
- ' LLIL_SET_REG.d(v22.s[3],LLIL_FMUL.d(LLIL_REG.d(v15.s[3]),LLIL_REG.d(v26.s[3])))'),
+ (b'\xF6\xDD\x3A\x6E', 'LLIL_INTRINSIC([v22],vmulq_f32,[LLIL_REG.o(v15),LLIL_REG.o(v26),LLIL_CONST.b(0x0)])'),
# fmul v13.2s, v10.2s, v21.2s FMUL_asimdsame_only
- (b'\x4D\xDD\x35\x2E', 'LLIL_SET_REG.d(v13.s[0],LLIL_FMUL.d(LLIL_REG.d(v10.s[0]),LLIL_REG.d(v21.s[0])));' + \
- ' LLIL_SET_REG.d(v13.s[1],LLIL_FMUL.d(LLIL_REG.d(v10.s[1]),LLIL_REG.d(v21.s[1])))'),
+ (b'\x4D\xDD\x35\x2E', 'LLIL_INTRINSIC([v13],vmul_f32,[LLIL_REG.o(v10),LLIL_REG.o(v21),LLIL_CONST.b(0x0)])'),
# fmul v22.4s, v6.4s, v31.4s FMUL_asimdsame_only
- (b'\xD6\xDC\x3F\x6E', 'LLIL_SET_REG.d(v22.s[0],LLIL_FMUL.d(LLIL_REG.d(v6.s[0]),LLIL_REG.d(v31.s[0])));' + \
- ' LLIL_SET_REG.d(v22.s[1],LLIL_FMUL.d(LLIL_REG.d(v6.s[1]),LLIL_REG.d(v31.s[1])));' + \
- ' LLIL_SET_REG.d(v22.s[2],LLIL_FMUL.d(LLIL_REG.d(v6.s[2]),LLIL_REG.d(v31.s[2])));' + \
- ' LLIL_SET_REG.d(v22.s[3],LLIL_FMUL.d(LLIL_REG.d(v6.s[3]),LLIL_REG.d(v31.s[3])))'),
+ (b'\xD6\xDC\x3F\x6E', 'LLIL_INTRINSIC([v22],vmulq_f32,[LLIL_REG.o(v6),LLIL_REG.o(v31),LLIL_CONST.b(0x0)])'),
# fmul v18.2d, v3.2d, v26.2d FMUL_asimdsame_only
- (b'\x72\xDC\x7A\x6E', 'LLIL_SET_REG.q(v18.d[0],LLIL_FMUL.q(LLIL_REG.q(v3.d[0]),LLIL_REG.q(v26.d[0])));' + \
- ' LLIL_SET_REG.q(v18.d[1],LLIL_FMUL.q(LLIL_REG.q(v3.d[1]),LLIL_REG.q(v26.d[1])))'),
+ (b'\x72\xDC\x7A\x6E', 'LLIL_INTRINSIC([v18],vmulq_f64,[LLIL_REG.o(v3),LLIL_REG.o(v26),LLIL_CONST.b(0x0)])'),
# fmul v14.2d, v19.2d, v23.2d FMUL_asimdsame_only
- (b'\x6E\xDE\x77\x6E', 'LLIL_SET_REG.q(v14.d[0],LLIL_FMUL.q(LLIL_REG.q(v19.d[0]),LLIL_REG.q(v23.d[0])));' + \
- ' LLIL_SET_REG.q(v14.d[1],LLIL_FMUL.q(LLIL_REG.q(v19.d[1]),LLIL_REG.q(v23.d[1])))'),
+ (b'\x6E\xDE\x77\x6E', 'LLIL_INTRINSIC([v14],vmulq_f64,[LLIL_REG.o(v19),LLIL_REG.o(v23),LLIL_CONST.b(0x0)])'),
# fmul v14.4h, v25.4h, v26.4h FMUL_asimdsamefp16_only
- (b'\x2E\x1F\x5A\x2E', 'LLIL_SET_REG.w(v14.h[0],LLIL_FMUL.w(LLIL_REG.w(v25.h[0]),LLIL_REG.w(v26.h[0])));' + \
- ' LLIL_SET_REG.w(v14.h[1],LLIL_FMUL.w(LLIL_REG.w(v25.h[1]),LLIL_REG.w(v26.h[1])));' + \
- ' LLIL_SET_REG.w(v14.h[2],LLIL_FMUL.w(LLIL_REG.w(v25.h[2]),LLIL_REG.w(v26.h[2])));' + \
- ' LLIL_SET_REG.w(v14.h[3],LLIL_FMUL.w(LLIL_REG.w(v25.h[3]),LLIL_REG.w(v26.h[3])))'),
+ (b'\x2E\x1F\x5A\x2E', 'LLIL_INTRINSIC([v14],vmul_f16,[LLIL_REG.o(v25),LLIL_CONST.b(0x0)])'),
# fmul v24.4h, v21.4h, v29.4h FMUL_asimdsamefp16_only
- (b'\xB8\x1E\x5D\x2E', 'LLIL_SET_REG.w(v24.h[0],LLIL_FMUL.w(LLIL_REG.w(v21.h[0]),LLIL_REG.w(v29.h[0])));' + \
- ' LLIL_SET_REG.w(v24.h[1],LLIL_FMUL.w(LLIL_REG.w(v21.h[1]),LLIL_REG.w(v29.h[1])));' + \
- ' LLIL_SET_REG.w(v24.h[2],LLIL_FMUL.w(LLIL_REG.w(v21.h[2]),LLIL_REG.w(v29.h[2])));' + \
- ' LLIL_SET_REG.w(v24.h[3],LLIL_FMUL.w(LLIL_REG.w(v21.h[3]),LLIL_REG.w(v29.h[3])))'),
+ (b'\xB8\x1E\x5D\x2E', 'LLIL_INTRINSIC([v24],vmul_f16,[LLIL_REG.o(v21),LLIL_CONST.b(0x0)])'),
# fmul v22.8h, v17.8h, v26.8h FMUL_asimdsamefp16_only
- (b'\x36\x1E\x5A\x6E', 'LLIL_SET_REG.w(v22.h[0],LLIL_FMUL.w(LLIL_REG.w(v17.h[0]),LLIL_REG.w(v26.h[0])));' + \
- ' LLIL_SET_REG.w(v22.h[1],LLIL_FMUL.w(LLIL_REG.w(v17.h[1]),LLIL_REG.w(v26.h[1])));' + \
- ' LLIL_SET_REG.w(v22.h[2],LLIL_FMUL.w(LLIL_REG.w(v17.h[2]),LLIL_REG.w(v26.h[2])));' + \
- ' LLIL_SET_REG.w(v22.h[3],LLIL_FMUL.w(LLIL_REG.w(v17.h[3]),LLIL_REG.w(v26.h[3])));' + \
- ' LLIL_SET_REG.w(v22.h[4],LLIL_FMUL.w(LLIL_REG.w(v17.h[4]),LLIL_REG.w(v26.h[4])));' + \
- ' LLIL_SET_REG.w(v22.h[5],LLIL_FMUL.w(LLIL_REG.w(v17.h[5]),LLIL_REG.w(v26.h[5])));' + \
- ' LLIL_SET_REG.w(v22.h[6],LLIL_FMUL.w(LLIL_REG.w(v17.h[6]),LLIL_REG.w(v26.h[6])));' + \
- ' LLIL_SET_REG.w(v22.h[7],LLIL_FMUL.w(LLIL_REG.w(v17.h[7]),LLIL_REG.w(v26.h[7])))'),
+ (b'\x36\x1E\x5A\x6E', 'LLIL_INTRINSIC([v22],vmulq_f16,[LLIL_REG.o(v17),LLIL_CONST.b(0x0)])'),
# fmul v9.8h, v2.8h, v17.8h FMUL_asimdsamefp16_only
- (b'\x49\x1C\x51\x6E', 'LLIL_SET_REG.w(v9.h[0],LLIL_FMUL.w(LLIL_REG.w(v2.h[0]),LLIL_REG.w(v17.h[0])));' + \
- ' LLIL_SET_REG.w(v9.h[1],LLIL_FMUL.w(LLIL_REG.w(v2.h[1]),LLIL_REG.w(v17.h[1])));' + \
- ' LLIL_SET_REG.w(v9.h[2],LLIL_FMUL.w(LLIL_REG.w(v2.h[2]),LLIL_REG.w(v17.h[2])));' + \
- ' LLIL_SET_REG.w(v9.h[3],LLIL_FMUL.w(LLIL_REG.w(v2.h[3]),LLIL_REG.w(v17.h[3])));' + \
- ' LLIL_SET_REG.w(v9.h[4],LLIL_FMUL.w(LLIL_REG.w(v2.h[4]),LLIL_REG.w(v17.h[4])));' + \
- ' LLIL_SET_REG.w(v9.h[5],LLIL_FMUL.w(LLIL_REG.w(v2.h[5]),LLIL_REG.w(v17.h[5])));' + \
- ' LLIL_SET_REG.w(v9.h[6],LLIL_FMUL.w(LLIL_REG.w(v2.h[6]),LLIL_REG.w(v17.h[6])));' + \
- ' LLIL_SET_REG.w(v9.h[7],LLIL_FMUL.w(LLIL_REG.w(v2.h[7]),LLIL_REG.w(v17.h[7])))'),
+ (b'\x49\x1C\x51\x6E', 'LLIL_INTRINSIC([v9],vmulq_f16,[LLIL_REG.o(v2),LLIL_CONST.b(0x0)])'),
# fmul v9.8h, v31.8h, v4.8h FMUL_asimdsamefp16_only
- (b'\xE9\x1F\x44\x6E', 'LLIL_SET_REG.w(v9.h[0],LLIL_FMUL.w(LLIL_REG.w(v31.h[0]),LLIL_REG.w(v4.h[0])));' + \
- ' LLIL_SET_REG.w(v9.h[1],LLIL_FMUL.w(LLIL_REG.w(v31.h[1]),LLIL_REG.w(v4.h[1])));' + \
- ' LLIL_SET_REG.w(v9.h[2],LLIL_FMUL.w(LLIL_REG.w(v31.h[2]),LLIL_REG.w(v4.h[2])));' + \
- ' LLIL_SET_REG.w(v9.h[3],LLIL_FMUL.w(LLIL_REG.w(v31.h[3]),LLIL_REG.w(v4.h[3])));' + \
- ' LLIL_SET_REG.w(v9.h[4],LLIL_FMUL.w(LLIL_REG.w(v31.h[4]),LLIL_REG.w(v4.h[4])));' + \
- ' LLIL_SET_REG.w(v9.h[5],LLIL_FMUL.w(LLIL_REG.w(v31.h[5]),LLIL_REG.w(v4.h[5])));' + \
- ' LLIL_SET_REG.w(v9.h[6],LLIL_FMUL.w(LLIL_REG.w(v31.h[6]),LLIL_REG.w(v4.h[6])));' + \
- ' LLIL_SET_REG.w(v9.h[7],LLIL_FMUL.w(LLIL_REG.w(v31.h[7]),LLIL_REG.w(v4.h[7])))'),
+ (b'\xE9\x1F\x44\x6E', 'LLIL_INTRINSIC([v9],vmulq_f16,[LLIL_REG.o(v31),LLIL_CONST.b(0x0)])'),
# fmul v21.4h, v19.4h, v2.4h FMUL_asimdsamefp16_only
- (b'\x75\x1E\x42\x2E', 'LLIL_SET_REG.w(v21.h[0],LLIL_FMUL.w(LLIL_REG.w(v19.h[0]),LLIL_REG.w(v2.h[0])));' + \
- ' LLIL_SET_REG.w(v21.h[1],LLIL_FMUL.w(LLIL_REG.w(v19.h[1]),LLIL_REG.w(v2.h[1])));' + \
- ' LLIL_SET_REG.w(v21.h[2],LLIL_FMUL.w(LLIL_REG.w(v19.h[2]),LLIL_REG.w(v2.h[2])));' + \
- ' LLIL_SET_REG.w(v21.h[3],LLIL_FMUL.w(LLIL_REG.w(v19.h[3]),LLIL_REG.w(v2.h[3])))'),
+ (b'\x75\x1E\x42\x2E', 'LLIL_INTRINSIC([v21],vmul_f16,[LLIL_REG.o(v19),LLIL_CONST.b(0x0)])'),
# fmul v24.8h, v4.8h, v20.8h FMUL_asimdsamefp16_only
- (b'\x98\x1C\x54\x6E', 'LLIL_SET_REG.w(v24.h[0],LLIL_FMUL.w(LLIL_REG.w(v4.h[0]),LLIL_REG.w(v20.h[0])));' + \
- ' LLIL_SET_REG.w(v24.h[1],LLIL_FMUL.w(LLIL_REG.w(v4.h[1]),LLIL_REG.w(v20.h[1])));' + \
- ' LLIL_SET_REG.w(v24.h[2],LLIL_FMUL.w(LLIL_REG.w(v4.h[2]),LLIL_REG.w(v20.h[2])));' + \
- ' LLIL_SET_REG.w(v24.h[3],LLIL_FMUL.w(LLIL_REG.w(v4.h[3]),LLIL_REG.w(v20.h[3])));' + \
- ' LLIL_SET_REG.w(v24.h[4],LLIL_FMUL.w(LLIL_REG.w(v4.h[4]),LLIL_REG.w(v20.h[4])));' + \
- ' LLIL_SET_REG.w(v24.h[5],LLIL_FMUL.w(LLIL_REG.w(v4.h[5]),LLIL_REG.w(v20.h[5])));' + \
- ' LLIL_SET_REG.w(v24.h[6],LLIL_FMUL.w(LLIL_REG.w(v4.h[6]),LLIL_REG.w(v20.h[6])));' + \
- ' LLIL_SET_REG.w(v24.h[7],LLIL_FMUL.w(LLIL_REG.w(v4.h[7]),LLIL_REG.w(v20.h[7])))'),
+ (b'\x98\x1C\x54\x6E', 'LLIL_INTRINSIC([v24],vmulq_f16,[LLIL_REG.o(v4),LLIL_CONST.b(0x0)])'),
# fmul v29.4h, v12.4h, v5.4h FMUL_asimdsamefp16_only
- (b'\x9D\x1D\x45\x2E', 'LLIL_SET_REG.w(v29.h[0],LLIL_FMUL.w(LLIL_REG.w(v12.h[0]),LLIL_REG.w(v5.h[0])));' + \
- ' LLIL_SET_REG.w(v29.h[1],LLIL_FMUL.w(LLIL_REG.w(v12.h[1]),LLIL_REG.w(v5.h[1])));' + \
- ' LLIL_SET_REG.w(v29.h[2],LLIL_FMUL.w(LLIL_REG.w(v12.h[2]),LLIL_REG.w(v5.h[2])));' + \
- ' LLIL_SET_REG.w(v29.h[3],LLIL_FMUL.w(LLIL_REG.w(v12.h[3]),LLIL_REG.w(v5.h[3])))'),
+ (b'\x9D\x1D\x45\x2E', 'LLIL_INTRINSIC([v29],vmul_f16,[LLIL_REG.o(v12),LLIL_CONST.b(0x0)])'),
# fmul v2.4h, v23.4h, v15.h[0] FMUL_asimdelem_RH_H
(b'\xE2\x92\x0F\x0F', 'LLIL_SET_REG.w(v2.h[0],LLIL_FMUL.w(LLIL_REG.w(v23.h[0]),LLIL_REG.w(v15.h[0])));' + \
' LLIL_SET_REG.w(v2.h[1],LLIL_FMUL.w(LLIL_REG.w(v23.h[1]),LLIL_REG.w(v15.h[0])));' + \
@@ -1860,8 +2191,7 @@ tests_fmul = [
(b'\x21\x90\x80\x0F', 'LLIL_SET_REG.d(v1.s[0],LLIL_FMUL.d(LLIL_REG.d(v1.s[0]),LLIL_REG.d(v0.s[0])));' + \
' LLIL_SET_REG.d(v1.s[1],LLIL_FMUL.d(LLIL_REG.d(v1.s[1]),LLIL_REG.d(v0.s[0])))'),
# fmul v5.2d, v11.2d, v3.d[1] FMUL_asimdelem_R_SD
- (b'\x65\x99\xC3\x4F', 'LLIL_SET_REG.q(v5.d[0],LLIL_FMUL.q(LLIL_REG.q(v11.d[0]),LLIL_REG.q(v3.d[1])));' + \
- ' LLIL_SET_REG.q(v5.d[1],LLIL_FMUL.q(LLIL_REG.q(v11.d[1]),LLIL_REG.q(v3.d[1])))'),
+ (b'\x65\x99\xC3\x4F', 'LLIL_INTRINSIC([v5],vmulq_lane_f64,[LLIL_REG.o(v11),LLIL_REG.o(v3),LLIL_CONST.b(0x1)])'),
# fmul v23.4s, v4.4s, v3.s[3] FMUL_asimdelem_R_SD
(b'\x97\x98\xA3\x4F', 'LLIL_SET_REG.d(v23.s[0],LLIL_FMUL.d(LLIL_REG.d(v4.s[0]),LLIL_REG.d(v3.s[3])));' + \
' LLIL_SET_REG.d(v23.s[1],LLIL_FMUL.d(LLIL_REG.d(v4.s[1]),LLIL_REG.d(v3.s[3])));' + \
@@ -1874,8 +2204,7 @@ tests_fmul = [
(b'\x58\x92\xA5\x0F', 'LLIL_SET_REG.d(v24.s[0],LLIL_FMUL.d(LLIL_REG.d(v18.s[0]),LLIL_REG.d(v5.s[1])));' + \
' LLIL_SET_REG.d(v24.s[1],LLIL_FMUL.d(LLIL_REG.d(v18.s[1]),LLIL_REG.d(v5.s[1])))'),
# fmul v24.2d, v11.2d, v8.d[0] FMUL_asimdelem_R_SD
- (b'\x78\x91\xC8\x4F', 'LLIL_SET_REG.q(v24.d[0],LLIL_FMUL.q(LLIL_REG.q(v11.d[0]),LLIL_REG.q(v8.d[0])));' + \
- ' LLIL_SET_REG.q(v24.d[1],LLIL_FMUL.q(LLIL_REG.q(v11.d[1]),LLIL_REG.q(v8.d[0])))'),
+ (b'\x78\x91\xC8\x4F', 'LLIL_INTRINSIC([v24],vmulq_lane_f64,[LLIL_REG.o(v11),LLIL_REG.o(v8),LLIL_CONST.b(0x0)])'),
# fmul v7.2s, v0.2s, v12.s[0] FMUL_asimdelem_R_SD
(b'\x07\x90\x8C\x0F', 'LLIL_SET_REG.d(v7.s[0],LLIL_FMUL.d(LLIL_REG.d(v0.s[0]),LLIL_REG.d(v12.s[0])));' + \
' LLIL_SET_REG.d(v7.s[1],LLIL_FMUL.d(LLIL_REG.d(v0.s[1]),LLIL_REG.d(v12.s[0])))'),
@@ -1885,11 +2214,9 @@ tests_fmul = [
' LLIL_SET_REG.d(v9.s[2],LLIL_FMUL.d(LLIL_REG.d(v9.s[2]),LLIL_REG.d(v25.s[2])));' + \
' LLIL_SET_REG.d(v9.s[3],LLIL_FMUL.d(LLIL_REG.d(v9.s[3]),LLIL_REG.d(v25.s[2])))'),
# fmul v7.2d, v20.2d, v1.2d FMUL_asimdsame_only
- (b'\x87\xDE\x61\x6E', 'LLIL_SET_REG.q(v7.d[0],LLIL_FMUL.q(LLIL_REG.q(v20.d[0]),LLIL_REG.q(v1.d[0])));' + \
- ' LLIL_SET_REG.q(v7.d[1],LLIL_FMUL.q(LLIL_REG.q(v20.d[1]),LLIL_REG.q(v1.d[1])))'),
+ (b'\x87\xDE\x61\x6E', 'LLIL_INTRINSIC([v7],vmulq_f64,[LLIL_REG.o(v20),LLIL_REG.o(v1),LLIL_CONST.b(0x0)])'),
# fmul v28.2s, v21.2s, v1.2s FMUL_asimdsame_only
- (b'\xBC\xDE\x21\x2E', 'LLIL_SET_REG.d(v28.s[0],LLIL_FMUL.d(LLIL_REG.d(v21.s[0]),LLIL_REG.d(v1.s[0])));' + \
- ' LLIL_SET_REG.d(v28.s[1],LLIL_FMUL.d(LLIL_REG.d(v21.s[1]),LLIL_REG.d(v1.s[1])))'),
+ (b'\xBC\xDE\x21\x2E', 'LLIL_INTRINSIC([v28],vmul_f32,[LLIL_REG.o(v21),LLIL_REG.o(v1),LLIL_CONST.b(0x0)])'),
# fmul h19, h5, v4.h[3] FMUL_asisdelem_RH_H
(b'\xB3\x90\x34\x5F', 'LLIL_SET_REG.w(h19,LLIL_FMUL.w(LLIL_REG.w(h5),LLIL_REG.w(v4.h[3])))'),
# fmul h0, h5, v2.h[7] FMUL_asisdelem_RH_H
@@ -1913,9 +2240,9 @@ tests_fmul = [
# fmul s25, s8, v30.s[1] FMUL_asisdelem_R_SD
(b'\x19\x91\xBE\x5F', 'LLIL_SET_REG.d(s25,LLIL_FMUL.d(LLIL_REG.d(s8),LLIL_REG.d(v30.s[1])))'),
# fmul d2, d27, v4.d[0] FMUL_asisdelem_R_SD
- (b'\x62\x93\xC4\x5F', 'LLIL_SET_REG.q(d2,LLIL_FMUL.q(LLIL_REG.q(d27),LLIL_REG.q(v4.d[0])))'),
+ (b'\x62\x93\xC4\x5F', 'LLIL_INTRINSIC([d2],vmul_lane_f64,[LLIL_REG.q(d27),LLIL_REG.o(v4),LLIL_CONST.b(0x0)])'),
# fmul d26, d3, v27.d[1] FMUL_asisdelem_R_SD
- (b'\x7A\x98\xDB\x5F', 'LLIL_SET_REG.q(d26,LLIL_FMUL.q(LLIL_REG.q(d3),LLIL_REG.q(v27.d[1])))'),
+ (b'\x7A\x98\xDB\x5F', 'LLIL_INTRINSIC([d26],vmul_lane_f64,[LLIL_REG.q(d3),LLIL_REG.o(v27),LLIL_CONST.b(0x1)])'),
# fmul s26, s30, v13.s[3] FMUL_asisdelem_R_SD
(b'\xDA\x9B\xAD\x5F', 'LLIL_SET_REG.d(s26,LLIL_FMUL.d(LLIL_REG.d(s30),LLIL_REG.d(v13.s[3])))'),
# fmul s4, s24, v8.s[3] FMUL_asisdelem_R_SD
@@ -1924,6 +2251,296 @@ tests_fmul = [
(b'\x7C\x91\x89\x5F', 'LLIL_SET_REG.d(s28,LLIL_FMUL.d(LLIL_REG.d(s11),LLIL_REG.d(v9.s[0])))'),
]
+tests_fcm = [
+ # fcmeq v26.2s, v16.2s, v16.2s FCMEQ_asimdsame_only
+ (b'\x1A\xE6\x30\x0E', 'LLIL_INTRINSIC([v26],vceq_f32,[LLIL_REG.o(v16),LLIL_REG.o(v16)])'),
+ # fcmeq v21.2d, v13.2d, v27.2d FCMEQ_asimdsame_only
+ (b'\xB5\xE5\x7B\x4E', 'LLIL_INTRINSIC([v21],vceqq_f64,[LLIL_REG.o(v13),LLIL_REG.o(v27)])'),
+ # fcmeq v21.4s, v18.4s, v22.4s FCMEQ_asimdsame_only
+ (b'\x55\xE6\x36\x4E', 'LLIL_INTRINSIC([v21],vceqq_f32,[LLIL_REG.o(v18),LLIL_REG.o(v22)])'),
+ # fcmeq v29.2d, v0.2d, v30.2d FCMEQ_asimdsame_only
+ (b'\x1D\xE4\x7E\x4E', 'LLIL_INTRINSIC([v29],vceqq_f64,[LLIL_REG.o(v0),LLIL_REG.o(v30)])'),
+ # fcmeq v22.4h, v19.4h, v11.4h FCMEQ_asimdsamefp16_only
+ (b'\x76\x26\x4B\x0E', 'LLIL_INTRINSIC([v22],vceq_f16,[LLIL_REG.o(v19),LLIL_REG.o(v11)])'),
+ # fcmeq v1.8h, v3.8h, v15.8h FCMEQ_asimdsamefp16_only
+ (b'\x61\x24\x4F\x4E', 'LLIL_INTRINSIC([v1],vceqq_f16,[LLIL_REG.o(v3),LLIL_REG.o(v15)])'),
+ # fcmeq v16.4h, v14.4h, v25.4h FCMEQ_asimdsamefp16_only
+ (b'\xD0\x25\x59\x0E', 'LLIL_INTRINSIC([v16],vceq_f16,[LLIL_REG.o(v14),LLIL_REG.o(v25)])'),
+ # fcmeq v4.8h, v24.8h, v16.8h FCMEQ_asimdsamefp16_only
+ (b'\x04\x27\x50\x4E', 'LLIL_INTRINSIC([v4],vceqq_f16,[LLIL_REG.o(v24),LLIL_REG.o(v16)])'),
+ # fcmeq s20, s31, s6 FCMEQ_asisdsame_only
+ (b'\xF4\xE7\x26\x5E', 'LLIL_INTRINSIC([s20],vceqs_f32,[LLIL_REG.d(s31),LLIL_REG.d(s6)])'),
+ # fcmeq d11, d27, d9 FCMEQ_asisdsame_only
+ (b'\x6B\xE7\x69\x5E', 'LLIL_INTRINSIC([d11],vceq_f64,[LLIL_REG.q(d27),LLIL_REG.q(d9)])'),
+ # fcmeq d3, d5, d8 FCMEQ_asisdsame_only
+ (b'\xA3\xE4\x68\x5E', 'LLIL_INTRINSIC([d3],vceq_f64,[LLIL_REG.q(d5),LLIL_REG.q(d8)])'),
+ # fcmeq d16, d26, d10 FCMEQ_asisdsame_only
+ (b'\x50\xE7\x6A\x5E', 'LLIL_INTRINSIC([d16],vceq_f64,[LLIL_REG.q(d26),LLIL_REG.q(d10)])'),
+ # fcmeq h17, h22, h7 FCMEQ_asisdsamefp16_only
+ (b'\xD1\x26\x47\x5E', 'LLIL_INTRINSIC([h17],vceqh_f16,[LLIL_REG.w(h22),LLIL_REG.w(h7)])'),
+ # fcmeq h21, h20, h22 FCMEQ_asisdsamefp16_only
+ (b'\x95\x26\x56\x5E', 'LLIL_INTRINSIC([h21],vceqh_f16,[LLIL_REG.w(h20),LLIL_REG.w(h22)])'),
+ # fcmeq h27, h20, h9 FCMEQ_asisdsamefp16_only
+ (b'\x9B\x26\x49\x5E', 'LLIL_INTRINSIC([h27],vceqh_f16,[LLIL_REG.w(h20),LLIL_REG.w(h9)])'),
+ # fcmeq h17, h20, h1 FCMEQ_asisdsamefp16_only
+ (b'\x91\x26\x41\x5E', 'LLIL_INTRINSIC([h17],vceqh_f16,[LLIL_REG.w(h20),LLIL_REG.w(h1)])'),
+ # fcmge v19.2s, v20.2s, v30.2s FCMGE_asimdsame_only
+ (b'\x93\xE6\x3E\x2E', 'LLIL_INTRINSIC([v19],vcle_f32,[LLIL_REG.o(v20),LLIL_REG.o(v30)])'),
+ # fcmge v14.4s, v24.4s, v26.4s FCMGE_asimdsame_only
+ (b'\x0E\xE7\x3A\x6E', 'LLIL_INTRINSIC([v14],vcleq_f32,[LLIL_REG.o(v24),LLIL_REG.o(v26)])'),
+ # fcmge v16.4s, v12.4s, v9.4s FCMGE_asimdsame_only
+ (b'\x90\xE5\x29\x6E', 'LLIL_INTRINSIC([v16],vcleq_f32,[LLIL_REG.o(v12),LLIL_REG.o(v9)])'),
+ # fcmge v25.2d, v9.2d, v10.2d FCMGE_asimdsame_only
+ (b'\x39\xE5\x6A\x6E', 'LLIL_INTRINSIC([v25],vcleq_f64,[LLIL_REG.o(v9),LLIL_REG.o(v10)])'),
+ # fcmge v30.4h, v8.4h, v25.4h FCMGE_asimdsamefp16_only
+ (b'\x1E\x25\x59\x2E', 'LLIL_INTRINSIC([v30],vcle_f16,[LLIL_REG.o(v8),LLIL_REG.o(v25)])'),
+ # fcmge v8.4h, v21.4h, v13.4h FCMGE_asimdsamefp16_only
+ (b'\xA8\x26\x4D\x2E', 'LLIL_INTRINSIC([v8],vcle_f16,[LLIL_REG.o(v21),LLIL_REG.o(v13)])'),
+ # fcmge v1.4h, v6.4h, v21.4h FCMGE_asimdsamefp16_only
+ (b'\xC1\x24\x55\x2E', 'LLIL_INTRINSIC([v1],vcle_f16,[LLIL_REG.o(v6),LLIL_REG.o(v21)])'),
+ # fcmge v5.8h, v17.8h, v22.8h FCMGE_asimdsamefp16_only
+ (b'\x25\x26\x56\x6E', 'LLIL_INTRINSIC([v5],vcleq_f16,[LLIL_REG.o(v17),LLIL_REG.o(v22)])'),
+ # fcmge d14, d18, d31 FCMGE_asisdsame_only
+ (b'\x4E\xE6\x7F\x7E', 'LLIL_INTRINSIC([d14],vcged_f64,[LLIL_REG.q(d18),LLIL_REG.q(d31)])'),
+ # fcmge d5, d20, d1 FCMGE_asisdsame_only
+ (b'\x85\xE6\x61\x7E', 'LLIL_INTRINSIC([d5],vcged_f64,[LLIL_REG.q(d20),LLIL_REG.q(d1)])'),
+ # fcmge d5, d31, d19 FCMGE_asisdsame_only
+ (b'\xE5\xE7\x73\x7E', 'LLIL_INTRINSIC([d5],vcged_f64,[LLIL_REG.q(d31),LLIL_REG.q(d19)])'),
+ # fcmge s22, s29, s1 FCMGE_asisdsame_only
+ (b'\xB6\xE7\x21\x7E', 'LLIL_INTRINSIC([s22],vcges_f32,[LLIL_REG.d(s29),LLIL_REG.d(s1)])'),
+ # fcmge h14, h31, h0 FCMGE_asisdsamefp16_only
+ (b'\xEE\x27\x40\x7E', 'LLIL_INTRINSIC([h14],vcleh_f16,[LLIL_REG.w(h31),LLIL_REG.w(h0)])'),
+ # fcmge h15, h10, h6 FCMGE_asisdsamefp16_only
+ (b'\x4F\x25\x46\x7E', 'LLIL_INTRINSIC([h15],vcleh_f16,[LLIL_REG.w(h10),LLIL_REG.w(h6)])'),
+ # fcmge h30, h22, h10 FCMGE_asisdsamefp16_only
+ (b'\xDE\x26\x4A\x7E', 'LLIL_INTRINSIC([h30],vcleh_f16,[LLIL_REG.w(h22),LLIL_REG.w(h10)])'),
+ # fcmge h2, h8, h29 FCMGE_asisdsamefp16_only
+ (b'\x02\x25\x5D\x7E', 'LLIL_INTRINSIC([h2],vcleh_f16,[LLIL_REG.w(h8),LLIL_REG.w(h29)])'),
+ # fcmgt v24.2d, v5.2d, v23.2d FCMGT_asimdsame_only
+ (b'\xB8\xE4\xF7\x6E', 'LLIL_INTRINSIC([v24],vcgtq_f64,[LLIL_REG.o(v5),LLIL_REG.o(v23)])'),
+ # fcmgt v19.2d, v15.2d, v9.2d FCMGT_asimdsame_only
+ (b'\xF3\xE5\xE9\x6E', 'LLIL_INTRINSIC([v19],vcgtq_f64,[LLIL_REG.o(v15),LLIL_REG.o(v9)])'),
+ # fcmgt v24.2d, v7.2d, v12.2d FCMGT_asimdsame_only
+ (b'\xF8\xE4\xEC\x6E', 'LLIL_INTRINSIC([v24],vcgtq_f64,[LLIL_REG.o(v7),LLIL_REG.o(v12)])'),
+ # fcmgt v29.2s, v3.2s, v0.2s FCMGT_asimdsame_only
+ (b'\x7D\xE4\xA0\x2E', 'LLIL_INTRINSIC([v29],vcgt_f32,[LLIL_REG.o(v3),LLIL_REG.o(v0)])'),
+ # fcmgt v0.8h, v31.8h, v10.8h FCMGT_asimdsamefp16_only
+ (b'\xE0\x27\xCA\x6E', 'LLIL_INTRINSIC([v0],vcltq_f16,[LLIL_REG.o(v31),LLIL_REG.o(v10)])'),
+ # fcmgt v26.4h, v15.4h, v17.4h FCMGT_asimdsamefp16_only
+ (b'\xFA\x25\xD1\x2E', 'LLIL_INTRINSIC([v26],vclt_f16,[LLIL_REG.o(v15),LLIL_REG.o(v17)])'),
+ # fcmgt v9.4h, v21.4h, v31.4h FCMGT_asimdsamefp16_only
+ (b'\xA9\x26\xDF\x2E', 'LLIL_INTRINSIC([v9],vclt_f16,[LLIL_REG.o(v21),LLIL_REG.o(v31)])'),
+ # fcmgt v2.8h, v26.8h, v11.8h FCMGT_asimdsamefp16_only
+ (b'\x42\x27\xCB\x6E', 'LLIL_INTRINSIC([v2],vcltq_f16,[LLIL_REG.o(v26),LLIL_REG.o(v11)])'),
+ # fcmgt d26, d9, d10 FCMGT_asisdsame_only
+ (b'\x3A\xE5\xEA\x7E', 'LLIL_INTRINSIC([d26],vcgtd_f64,[LLIL_REG.q(d9),LLIL_REG.q(d10)])'),
+ # fcmgt s31, s12, s18 FCMGT_asisdsame_only
+ (b'\x9F\xE5\xB2\x7E', 'LLIL_INTRINSIC([s31],vcgts_f32,[LLIL_REG.d(s12),LLIL_REG.d(s18)])'),
+ # fcmgt s22, s12, s23 FCMGT_asisdsame_only
+ (b'\x96\xE5\xB7\x7E', 'LLIL_INTRINSIC([s22],vcgts_f32,[LLIL_REG.d(s12),LLIL_REG.d(s23)])'),
+ # fcmgt s6, s30, s22 FCMGT_asisdsame_only
+ (b'\xC6\xE7\xB6\x7E', 'LLIL_INTRINSIC([s6],vcgts_f32,[LLIL_REG.d(s30),LLIL_REG.d(s22)])'),
+ # fcmgt h6, h0, h25 FCMGT_asisdsamefp16_only
+ (b'\x06\x24\xD9\x7E', 'LLIL_INTRINSIC([h6],vclth_f16,[LLIL_REG.w(h0)])'),
+ # fcmgt h25, h0, h23 FCMGT_asisdsamefp16_only
+ (b'\x19\x24\xD7\x7E', 'LLIL_INTRINSIC([h25],vclth_f16,[LLIL_REG.w(h0)])'),
+ # fcmgt h5, h8, h9 FCMGT_asisdsamefp16_only
+ (b'\x05\x25\xC9\x7E', 'LLIL_INTRINSIC([h5],vclth_f16,[LLIL_REG.w(h8)])'),
+ # fcmgt h25, h2, h18 FCMGT_asisdsamefp16_only
+ (b'\x59\x24\xD2\x7E', 'LLIL_INTRINSIC([h25],vclth_f16,[LLIL_REG.w(h2)])'),
+]
+
+tests_fcmla = [
+ # fcmla v4.8h, v22.8h, v5.h[0], #0x0 FCMLA_asimdelem_C_H
+ (b'\xC4\x12\x45\x6F', 'LLIL_INTRINSIC([v4],vcmlaq_laneq_f16,[LLIL_REG.o(v4),LLIL_REG.o(v22),LLIL_REG.o(v5),LLIL_CONST.b(0x0),LLIL_CONST(0)])'),
+ # fcmla v11.8h, v1.8h, v18.h[0], #0x5a FCMLA_asimdelem_C_H
+ (b'\x2B\x30\x52\x6F', 'LLIL_INTRINSIC([v11],vcmlaq_rot90_laneq_f16,[LLIL_REG.o(v11),LLIL_REG.o(v1),LLIL_REG.o(v18),LLIL_CONST.b(0x0),LLIL_CONST(90)])'),
+ # fcmla v23.8h, v7.8h, v22.h[0], #0xb4 FCMLA_asimdelem_C_H
+ (b'\xF7\x50\x56\x6F', 'LLIL_INTRINSIC([v23],vcmlaq_rot180_laneq_f16,[LLIL_REG.o(v23),LLIL_REG.o(v7),LLIL_REG.o(v22),LLIL_CONST.b(0x0),LLIL_CONST(180)])'),
+ # fcmla v21.4h, v13.4h, v19.h[0], #0xb4 FCMLA_asimdelem_C_H
+ (b'\xB5\x51\x53\x2F', 'LLIL_INTRINSIC([v21],vcmla_rot180_laneq_f16,[LLIL_REG.o(v21),LLIL_REG.o(v13),LLIL_REG.o(v19),LLIL_CONST.b(0x0),LLIL_CONST(180)])'),
+ # fcmla v24.4s, v7.4s, v16.s[1], #0x5a FCMLA_asimdelem_C_S
+ (b'\xF8\x38\x90\x6F', 'LLIL_INTRINSIC([v24],vcmlaq_rot90_laneq_f32,[LLIL_REG.o(v24),LLIL_REG.o(v7),LLIL_REG.o(v16),LLIL_CONST.b(0x1),LLIL_CONST(90)])'),
+ # fcmla v23.4s, v8.4s, v0.s[1], #0x10e FCMLA_asimdelem_C_S
+ (b'\x17\x79\x80\x6F', 'LLIL_INTRINSIC([v23],vcmlaq_rot270_laneq_f32,[LLIL_REG.o(v23),LLIL_REG.o(v8),LLIL_REG.o(v0),LLIL_CONST.b(0x1),LLIL_CONST(270)])'),
+ # fcmla v16.4s, v0.4s, v31.s[0], #0xb4 FCMLA_asimdelem_C_S
+ (b'\x10\x50\x9F\x6F', 'LLIL_INTRINSIC([v16],vcmlaq_rot180_laneq_f32,[LLIL_REG.o(v16),LLIL_REG.o(v0),LLIL_REG.o(v31),LLIL_CONST.b(0x0),LLIL_CONST(180)])'),
+ # fcmla v26.4s, v23.4s, v1.s[1], #0x0 FCMLA_asimdelem_C_S
+ (b'\xFA\x1A\x81\x6F', 'LLIL_INTRINSIC([v26],vcmlaq_laneq_f32,[LLIL_REG.o(v26),LLIL_REG.o(v23),LLIL_REG.o(v1),LLIL_CONST.b(0x1),LLIL_CONST(0)])'),
+ # fcmla v9.4s, v2.4s, v31.4s, #0x0 FCMLA_asimdsame2_C
+ (b'\x49\xC4\x9F\x6E', 'LLIL_INTRINSIC([v9],vcmlaq_f32,[LLIL_REG.o(v9),LLIL_REG.o(v2),LLIL_REG.o(v31),LLIL_CONST(0)])'),
+ # fcmla v18.2s, v22.2s, v16.2s, #0x5a FCMLA_asimdsame2_C
+ (b'\xD2\xCE\x90\x2E', 'LLIL_INTRINSIC([v18],vcmla_rot90_f32,[LLIL_REG.o(v18),LLIL_REG.o(v22),LLIL_REG.o(v16),LLIL_CONST(90)])'),
+ # fcmla v2.4h, v15.4h, v7.4h, #0x0 FCMLA_asimdsame2_C
+ (b'\xE2\xC5\x47\x2E', 'LLIL_INTRINSIC([v2],vcmla_f16,[LLIL_REG.o(v2),LLIL_REG.o(v15),LLIL_REG.o(v7),LLIL_CONST(0)])'),
+ # fcmla v13.2s, v10.2s, v1.2s, #0x5a FCMLA_asimdsame2_C
+ (b'\x4D\xCD\x81\x2E', 'LLIL_INTRINSIC([v13],vcmla_rot90_f32,[LLIL_REG.o(v13),LLIL_REG.o(v10),LLIL_REG.o(v1),LLIL_CONST(90)])'),
+]
+
+
+tests_fml = [
+ # fmlal2 v12.2s, v26.2h, v15.h[2] FMLAL2_asimdelem_LH
+ (b'\x4C\x83\xAF\x2F', 'LLIL_INTRINSIC([v12],vfmlal_lane_high_f16,[LLIL_REG.o(v12),LLIL_REG.o(v26),LLIL_REG.o(v15),LLIL_CONST.b(0x2)])'),
+ # fmlal2 v5.2s, v10.2h, v3.h[2] FMLAL2_asimdelem_LH
+ (b'\x45\x81\xA3\x2F', 'LLIL_INTRINSIC([v5],vfmlal_lane_high_f16,[LLIL_REG.o(v5),LLIL_REG.o(v10),LLIL_REG.o(v3),LLIL_CONST.b(0x2)])'),
+ # fmlal2 v20.4s, v9.4h, v12.h[7] FMLAL2_asimdelem_LH
+ (b'\x34\x89\xBC\x6F', 'LLIL_INTRINSIC([v20],vfmlalq_lane_high_f16,[LLIL_REG.o(v20),LLIL_REG.o(v9),LLIL_REG.o(v12),LLIL_CONST.b(0x7)])'),
+ # fmlal2 v6.2s, v7.2h, v12.h[2] FMLAL2_asimdelem_LH
+ (b'\xE6\x80\xAC\x2F', 'LLIL_INTRINSIC([v6],vfmlal_lane_high_f16,[LLIL_REG.o(v6),LLIL_REG.o(v7),LLIL_REG.o(v12),LLIL_CONST.b(0x2)])'),
+ # fmlal2 v9.2s, v30.2h, v7.2h FMLAL2_asimdsame_F
+ (b'\xC9\xCF\x27\x2E', 'LLIL_INTRINSIC([v9],vfmlal_high_f16,[LLIL_REG.o(v9),LLIL_REG.o(v30),LLIL_REG.o(v7)])'),
+ # fmlal2 v1.4s, v0.4h, v16.4h FMLAL2_asimdsame_F
+ (b'\x01\xCC\x30\x6E', 'LLIL_INTRINSIC([v1],vfmlalq_high_f16,[LLIL_REG.o(v1),LLIL_REG.o(v0),LLIL_REG.o(v16)])'),
+ # fmlal2 v28.4s, v11.4h, v12.4h FMLAL2_asimdsame_F
+ (b'\x7C\xCD\x2C\x6E', 'LLIL_INTRINSIC([v28],vfmlalq_high_f16,[LLIL_REG.o(v28),LLIL_REG.o(v11),LLIL_REG.o(v12)])'),
+ # fmlal2 v26.2s, v29.2h, v13.2h FMLAL2_asimdsame_F
+ (b'\xBA\xCF\x2D\x2E', 'LLIL_INTRINSIC([v26],vfmlal_high_f16,[LLIL_REG.o(v26),LLIL_REG.o(v29),LLIL_REG.o(v13)])'),
+ # fmlal v5.2s, v5.2h, v4.h[1] FMLAL_asimdelem_LH
+ (b'\xA5\x00\x94\x0F', 'LLIL_INTRINSIC([v5],vfmlal_lane_low_f16,[LLIL_REG.o(v5),LLIL_REG.o(v5),LLIL_REG.o(v4),LLIL_CONST.b(0x1)])'),
+ # fmlal v28.4s, v25.4h, v5.h[7] FMLAL_asimdelem_LH
+ (b'\x3C\x0B\xB5\x4F', 'LLIL_INTRINSIC([v28],vfmlalq_lane_low_f16,[LLIL_REG.o(v28),LLIL_REG.o(v25),LLIL_REG.o(v5),LLIL_CONST.b(0x7)])'),
+ # fmlal v6.2s, v31.2h, v13.h[0] FMLAL_asimdelem_LH
+ (b'\xE6\x03\x8D\x0F', 'LLIL_INTRINSIC([v6],vfmlal_lane_low_f16,[LLIL_REG.o(v6),LLIL_REG.o(v31),LLIL_REG.o(v13),LLIL_CONST.b(0x0)])'),
+ # fmlal v14.4s, v10.4h, v4.h[3] FMLAL_asimdelem_LH
+ (b'\x4E\x01\xB4\x4F', 'LLIL_INTRINSIC([v14],vfmlalq_lane_low_f16,[LLIL_REG.o(v14),LLIL_REG.o(v10),LLIL_REG.o(v4),LLIL_CONST.b(0x3)])'),
+ # fmlal v18.4s, v25.4h, v16.4h FMLAL_asimdsame_F
+ (b'\x32\xEF\x30\x4E', 'LLIL_INTRINSIC([v18],vfmlalq_low_f16,[LLIL_REG.o(v18),LLIL_REG.o(v25),LLIL_REG.o(v16)])'),
+ # fmlal v19.2s, v0.2h, v11.2h FMLAL_asimdsame_F
+ (b'\x13\xEC\x2B\x0E', 'LLIL_INTRINSIC([v19],vfmlal_low_f16,[LLIL_REG.o(v19),LLIL_REG.o(v0),LLIL_REG.o(v11)])'),
+ # fmlal v7.2s, v20.2h, v3.2h FMLAL_asimdsame_F
+ (b'\x87\xEE\x23\x0E', 'LLIL_INTRINSIC([v7],vfmlal_low_f16,[LLIL_REG.o(v7),LLIL_REG.o(v20),LLIL_REG.o(v3)])'),
+ # fmlal v10.4s, v15.4h, v19.4h FMLAL_asimdsame_F
+ (b'\xEA\xED\x33\x4E', 'LLIL_INTRINSIC([v10],vfmlalq_low_f16,[LLIL_REG.o(v10),LLIL_REG.o(v15),LLIL_REG.o(v19)])'),
+ # fmla v22.8h, v31.8h, v9.h[2] FMLA_asimdelem_RH_H
+ (b'\xF6\x13\x29\x4F', 'LLIL_INTRINSIC([v22],vfmaq_laneq_f16,[LLIL_REG.o(v22),LLIL_REG.o(v31),LLIL_REG.o(v9),LLIL_CONST.b(0x2)])'),
+ # fmla v23.8h, v19.8h, v9.h[2] FMLA_asimdelem_RH_H
+ (b'\x77\x12\x29\x4F', 'LLIL_INTRINSIC([v23],vfmaq_laneq_f16,[LLIL_REG.o(v23),LLIL_REG.o(v19),LLIL_REG.o(v9),LLIL_CONST.b(0x2)])'),
+ # fmla v28.4h, v13.4h, v11.h[7] FMLA_asimdelem_RH_H
+ (b'\xBC\x19\x3B\x0F', 'LLIL_INTRINSIC([v28],vfma_laneq_f16,[LLIL_REG.o(v28),LLIL_REG.o(v13),LLIL_REG.o(v11),LLIL_CONST.b(0x7)])'),
+ # fmla v19.4h, v19.4h, v6.h[6] FMLA_asimdelem_RH_H
+ (b'\x73\x1A\x26\x0F', 'LLIL_INTRINSIC([v19],vfma_laneq_f16,[LLIL_REG.o(v19),LLIL_REG.o(v19),LLIL_REG.o(v6),LLIL_CONST.b(0x6)])'),
+ # fmla v28.4s, v5.4s, v23.s[0] FMLA_asimdelem_R_SD
+ (b'\xBC\x10\x97\x4F', 'LLIL_INTRINSIC([v28],vfmaq_n_f32,[LLIL_REG.o(v28),LLIL_REG.o(v5),LLIL_CONST.b(0x0)])'),
+ # fmla v21.4s, v24.4s, v7.s[1] FMLA_asimdelem_R_SD
+ (b'\x15\x13\xA7\x4F', 'LLIL_INTRINSIC([v21],vfmaq_n_f32,[LLIL_REG.o(v21),LLIL_REG.o(v24),LLIL_CONST.b(0x1)])'),
+ # fmla v29.2s, v3.2s, v23.s[0] FMLA_asimdelem_R_SD
+ (b'\x7D\x10\x97\x0F', 'LLIL_INTRINSIC([v29],vfma_n_f32,[LLIL_REG.o(v29),LLIL_REG.o(v3),LLIL_CONST.b(0x0)])'),
+ # fmla v4.2s, v20.2s, v0.s[1] FMLA_asimdelem_R_SD
+ (b'\x84\x12\xA0\x0F', 'LLIL_INTRINSIC([v4],vfma_n_f32,[LLIL_REG.o(v4),LLIL_REG.o(v20),LLIL_CONST.b(0x1)])'),
+ # fmla v13.4s, v26.4s, v21.4s FMLA_asimdsame_only
+ (b'\x4D\xCF\x35\x4E', 'LLIL_INTRINSIC([v13],vfmaq_f32,[LLIL_REG.o(v13),LLIL_REG.o(v26),LLIL_REG.o(v21)])'),
+ # fmla v3.4s, v18.4s, v14.4s FMLA_asimdsame_only
+ (b'\x43\xCE\x2E\x4E', 'LLIL_INTRINSIC([v3],vfmaq_f32,[LLIL_REG.o(v3),LLIL_REG.o(v18),LLIL_REG.o(v14)])'),
+ # fmla v1.4s, v29.4s, v31.4s FMLA_asimdsame_only
+ (b'\xA1\xCF\x3F\x4E', 'LLIL_INTRINSIC([v1],vfmaq_f32,[LLIL_REG.o(v1),LLIL_REG.o(v29),LLIL_REG.o(v31)])'),
+ # fmla v13.4s, v21.4s, v25.4s FMLA_asimdsame_only
+ (b'\xAD\xCE\x39\x4E', 'LLIL_INTRINSIC([v13],vfmaq_f32,[LLIL_REG.o(v13),LLIL_REG.o(v21),LLIL_REG.o(v25)])'),
+ # fmla v27.8h, v13.8h, v0.8h FMLA_asimdsamefp16_only
+ (b'\xBB\x0D\x40\x4E', 'LLIL_INTRINSIC([v27],vfmaq_f16,[LLIL_REG.o(v27),LLIL_REG.o(v13),LLIL_REG.o(v0),LLIL_CONST.b(0x0)])'),
+ # fmla v5.8h, v22.8h, v22.8h FMLA_asimdsamefp16_only
+ (b'\xC5\x0E\x56\x4E', 'LLIL_INTRINSIC([v5],vfmaq_f16,[LLIL_REG.o(v5),LLIL_REG.o(v22),LLIL_REG.o(v22),LLIL_CONST.b(0x0)])'),
+ # fmla v15.8h, v16.8h, v11.8h FMLA_asimdsamefp16_only
+ (b'\x0F\x0E\x4B\x4E', 'LLIL_INTRINSIC([v15],vfmaq_f16,[LLIL_REG.o(v15),LLIL_REG.o(v16),LLIL_REG.o(v11),LLIL_CONST.b(0x0)])'),
+ # fmla v13.8h, v7.8h, v8.8h FMLA_asimdsamefp16_only
+ (b'\xED\x0C\x48\x4E', 'LLIL_INTRINSIC([v13],vfmaq_f16,[LLIL_REG.o(v13),LLIL_REG.o(v7),LLIL_REG.o(v8),LLIL_CONST.b(0x0)])'),
+ # fmla h17, h23, v2.h[4] FMLA_asisdelem_RH_H
+ (b'\xF1\x1A\x02\x5F', 'LLIL_INTRINSIC([h17],vfmah_laneq_f16,[LLIL_REG.w(h17),LLIL_REG.w(h23),LLIL_REG.o(v2),LLIL_CONST.b(0x4)])'),
+ # fmla h22, h12, v13.h[1] FMLA_asisdelem_RH_H
+ (b'\x96\x11\x1D\x5F', 'LLIL_INTRINSIC([h22],vfmah_laneq_f16,[LLIL_REG.w(h22),LLIL_REG.w(h12),LLIL_REG.o(v13),LLIL_CONST.b(0x1)])'),
+ # fmla h3, h30, v9.h[0] FMLA_asisdelem_RH_H
+ (b'\xC3\x13\x09\x5F', 'LLIL_INTRINSIC([h3],vfmah_laneq_f16,[LLIL_REG.w(h3),LLIL_REG.w(h30),LLIL_REG.o(v9),LLIL_CONST.b(0x0)])'),
+ # fmla h19, h14, v13.h[3] FMLA_asisdelem_RH_H
+ (b'\xD3\x11\x3D\x5F', 'LLIL_INTRINSIC([h19],vfmah_laneq_f16,[LLIL_REG.w(h19),LLIL_REG.w(h14),LLIL_REG.o(v13),LLIL_CONST.b(0x3)])'),
+ # fmla s16, s6, v18.s[2] FMLA_asisdelem_R_SD
+ (b'\xD0\x18\x92\x5F', 'LLIL_INTRINSIC([s16],vfmas_laneq_f32,[LLIL_REG.d(s16),LLIL_REG.d(s6),LLIL_REG.o(v18),LLIL_CONST.b(0x2)])'),
+ # fmla s20, s26, v19.s[0] FMLA_asisdelem_R_SD
+ (b'\x54\x13\x93\x5F', 'LLIL_INTRINSIC([s20],vfmas_laneq_f32,[LLIL_REG.d(s20),LLIL_REG.d(s26),LLIL_REG.o(v19),LLIL_CONST.b(0x0)])'),
+ # fmla s19, s31, v31.s[0] FMLA_asisdelem_R_SD
+ (b'\xF3\x13\x9F\x5F', 'LLIL_INTRINSIC([s19],vfmas_laneq_f32,[LLIL_REG.d(s19),LLIL_REG.d(s31),LLIL_REG.o(v31),LLIL_CONST.b(0x0)])'),
+ # fmla s16, s13, v14.s[0] FMLA_asisdelem_R_SD
+ (b'\xB0\x11\x8E\x5F', 'LLIL_INTRINSIC([s16],vfmas_laneq_f32,[LLIL_REG.d(s16),LLIL_REG.d(s13),LLIL_REG.o(v14),LLIL_CONST.b(0x0)])'),
+ # fmlsl2 v26.2s, v8.2h, v10.h[0] FMLSL2_asimdelem_LH
+ (b'\x1A\xC1\x8A\x2F', 'LLIL_INTRINSIC([v26],vfmlsl_lane_high_f16,[LLIL_REG.o(v26),LLIL_REG.o(v8),LLIL_REG.o(v10),LLIL_CONST.b(0x0)])'),
+ # fmlsl2 v18.2s, v25.2h, v8.h[0] FMLSL2_asimdelem_LH
+ (b'\x32\xC3\x88\x2F', 'LLIL_INTRINSIC([v18],vfmlsl_lane_high_f16,[LLIL_REG.o(v18),LLIL_REG.o(v25),LLIL_REG.o(v8),LLIL_CONST.b(0x0)])'),
+ # fmlsl2 v13.4s, v16.4h, v1.h[0] FMLSL2_asimdelem_LH
+ (b'\x0D\xC2\x81\x6F', 'LLIL_INTRINSIC([v13],vfmlslq_lane_high_f16,[LLIL_REG.o(v13),LLIL_REG.o(v16),LLIL_REG.o(v1),LLIL_CONST.b(0x0)])'),
+ # fmlsl2 v9.4s, v28.4h, v2.h[3] FMLSL2_asimdelem_LH
+ (b'\x89\xC3\xB2\x6F', 'LLIL_INTRINSIC([v9],vfmlslq_lane_high_f16,[LLIL_REG.o(v9),LLIL_REG.o(v28),LLIL_REG.o(v2),LLIL_CONST.b(0x3)])'),
+ # fmlsl2 v0.4s, v10.4h, v1.4h FMLSL2_asimdsame_F
+ (b'\x40\xCD\xA1\x6E', 'LLIL_INTRINSIC([v0],vfmlslq_high_f16,[LLIL_REG.o(v0),LLIL_REG.o(v10),LLIL_REG.o(v1)])'),
+ # fmlsl2 v18.4s, v4.4h, v16.4h FMLSL2_asimdsame_F
+ (b'\x92\xCC\xB0\x6E', 'LLIL_INTRINSIC([v18],vfmlslq_high_f16,[LLIL_REG.o(v18),LLIL_REG.o(v4),LLIL_REG.o(v16)])'),
+ # fmlsl2 v21.2s, v24.2h, v28.2h FMLSL2_asimdsame_F
+ (b'\x15\xCF\xBC\x2E', 'LLIL_INTRINSIC([v21],vfmlsl_high_f16,[LLIL_REG.o(v21),LLIL_REG.o(v24),LLIL_REG.o(v28)])'),
+ # fmlsl2 v13.2s, v24.2h, v18.2h FMLSL2_asimdsame_F
+ (b'\x0D\xCF\xB2\x2E', 'LLIL_INTRINSIC([v13],vfmlsl_high_f16,[LLIL_REG.o(v13),LLIL_REG.o(v24),LLIL_REG.o(v18)])'),
+ # fmlsl v25.2s, v9.2h, v13.h[0] FMLSL_asimdelem_LH
+ (b'\x39\x41\x8D\x0F', 'LLIL_INTRINSIC([v25],vfmlsl_lane_low_f16,[LLIL_REG.o(v25),LLIL_REG.o(v9),LLIL_REG.o(v13),LLIL_CONST.b(0x0)])'),
+ # fmlsl v0.4s, v16.4h, v3.h[1] FMLSL_asimdelem_LH
+ (b'\x00\x42\x93\x4F', 'LLIL_INTRINSIC([v0],vfmlslq_lane_low_f16,[LLIL_REG.o(v0),LLIL_REG.o(v16),LLIL_REG.o(v3),LLIL_CONST.b(0x1)])'),
+ # fmlsl v12.4s, v7.4h, v7.h[6] FMLSL_asimdelem_LH
+ (b'\xEC\x48\xA7\x4F', 'LLIL_INTRINSIC([v12],vfmlslq_lane_low_f16,[LLIL_REG.o(v12),LLIL_REG.o(v7),LLIL_REG.o(v7),LLIL_CONST.b(0x6)])'),
+ # fmlsl v31.2s, v1.2h, v15.h[0] FMLSL_asimdelem_LH
+ (b'\x3F\x40\x8F\x0F', 'LLIL_INTRINSIC([v31],vfmlsl_lane_low_f16,[LLIL_REG.o(v31),LLIL_REG.o(v1),LLIL_REG.o(v15),LLIL_CONST.b(0x0)])'),
+ # fmlsl v15.2s, v26.2h, v6.2h FMLSL_asimdsame_F
+ (b'\x4F\xEF\xA6\x0E', 'LLIL_INTRINSIC([v15],vfmlsl_low_f16,[LLIL_REG.o(v15),LLIL_REG.o(v26),LLIL_REG.o(v6)])'),
+ # fmlsl v16.2s, v10.2h, v8.2h FMLSL_asimdsame_F
+ (b'\x50\xED\xA8\x0E', 'LLIL_INTRINSIC([v16],vfmlsl_low_f16,[LLIL_REG.o(v16),LLIL_REG.o(v10),LLIL_REG.o(v8)])'),
+ # fmlsl v16.2s, v13.2h, v6.2h FMLSL_asimdsame_F
+ (b'\xB0\xED\xA6\x0E', 'LLIL_INTRINSIC([v16],vfmlsl_low_f16,[LLIL_REG.o(v16),LLIL_REG.o(v13),LLIL_REG.o(v6)])'),
+ # fmlsl v9.4s, v16.4h, v20.4h FMLSL_asimdsame_F
+ (b'\x09\xEE\xB4\x4E', 'LLIL_INTRINSIC([v9],vfmlslq_low_f16,[LLIL_REG.o(v9),LLIL_REG.o(v16),LLIL_REG.o(v20)])'),
+ # fmls v16.8h, v8.8h, v1.h[4] FMLS_asimdelem_RH_H
+ (b'\x10\x59\x01\x4F', 'LLIL_INTRINSIC([v16],vfmsq_laneq_f16,[LLIL_REG.o(v16),LLIL_REG.o(v8),LLIL_REG.o(v1),LLIL_CONST.b(0x4)])'),
+ # fmls v22.4h, v17.4h, v8.h[1] FMLS_asimdelem_RH_H
+ (b'\x36\x52\x18\x0F', 'LLIL_INTRINSIC([v22],vfms_laneq_f16,[LLIL_REG.o(v22),LLIL_REG.o(v17),LLIL_REG.o(v8),LLIL_CONST.b(0x1)])'),
+ # fmls v27.4h, v31.4h, v6.h[1] FMLS_asimdelem_RH_H
+ (b'\xFB\x53\x16\x0F', 'LLIL_INTRINSIC([v27],vfms_laneq_f16,[LLIL_REG.o(v27),LLIL_REG.o(v31),LLIL_REG.o(v6),LLIL_CONST.b(0x1)])'),
+ # fmls v6.8h, v28.8h, v6.h[6] FMLS_asimdelem_RH_H
+ (b'\x86\x5B\x26\x4F', 'LLIL_INTRINSIC([v6],vfmsq_laneq_f16,[LLIL_REG.o(v6),LLIL_REG.o(v28),LLIL_REG.o(v6),LLIL_CONST.b(0x6)])'),
+ # fmls v26.4s, v31.4s, v24.s[3] FMLS_asimdelem_R_SD
+ (b'\xFA\x5B\xB8\x4F', 'LLIL_INTRINSIC([v26],vfmsq_laneq_f32,[LLIL_REG.o(v26),LLIL_REG.o(v31),LLIL_REG.o(v24),LLIL_CONST.b(0x3)])'),
+ # fmls v30.2s, v18.2s, v4.s[3] FMLS_asimdelem_R_SD
+ (b'\x5E\x5A\xA4\x0F', 'LLIL_INTRINSIC([v30],vfms_laneq_f32,[LLIL_REG.o(v30),LLIL_REG.o(v18),LLIL_REG.o(v4),LLIL_CONST.b(0x3)])'),
+ # fmls v27.2s, v0.2s, v29.s[2] FMLS_asimdelem_R_SD
+ (b'\x1B\x58\x9D\x0F', 'LLIL_INTRINSIC([v27],vfms_laneq_f32,[LLIL_REG.o(v27),LLIL_REG.o(v0),LLIL_REG.o(v29),LLIL_CONST.b(0x2)])'),
+ # fmls v8.4s, v22.4s, v0.s[0] FMLS_asimdelem_R_SD
+ (b'\xC8\x52\x80\x4F', 'LLIL_INTRINSIC([v8],vfmsq_laneq_f32,[LLIL_REG.o(v8),LLIL_REG.o(v22),LLIL_REG.o(v0),LLIL_CONST.b(0x0)])'),
+ # fmls v26.4s, v28.4s, v1.4s FMLS_asimdsame_only
+ (b'\x9A\xCF\xA1\x4E', 'LLIL_INTRINSIC([v26],vfmsq_f32,[LLIL_REG.o(v26),LLIL_REG.o(v28),LLIL_CONST.b(0x0)])'),
+ # fmls v0.2s, v8.2s, v1.2s FMLS_asimdsame_only
+ (b'\x00\xCD\xA1\x0E', 'LLIL_INTRINSIC([v0],vfms_f32,[LLIL_REG.o(v0),LLIL_REG.o(v8),LLIL_CONST.b(0x0)])'),
+ # fmls v18.2d, v29.2d, v21.2d FMLS_asimdsame_only
+ (b'\xB2\xCF\xF5\x4E', 'LLIL_INTRINSIC([v18],vfmsq_f64,[LLIL_REG.o(v18),LLIL_REG.o(v29),LLIL_CONST.b(0x0)])'),
+ # fmls v23.2s, v7.2s, v3.2s FMLS_asimdsame_only
+ (b'\xF7\xCC\xA3\x0E', 'LLIL_INTRINSIC([v23],vfms_f32,[LLIL_REG.o(v23),LLIL_REG.o(v7),LLIL_CONST.b(0x0)])'),
+ # fmls v22.4h, v25.4h, v4.4h FMLS_asimdsamefp16_only
+ (b'\x36\x0F\xC4\x0E', 'LLIL_INTRINSIC([v22],vfms_f16,[LLIL_REG.o(v22),LLIL_REG.o(v25),LLIL_CONST.b(0x0)])'),
+ # fmls v26.4h, v15.4h, v12.4h FMLS_asimdsamefp16_only
+ (b'\xFA\x0D\xCC\x0E', 'LLIL_INTRINSIC([v26],vfms_f16,[LLIL_REG.o(v26),LLIL_REG.o(v15),LLIL_CONST.b(0x0)])'),
+ # fmls v20.4h, v13.4h, v21.4h FMLS_asimdsamefp16_only
+ (b'\xB4\x0D\xD5\x0E', 'LLIL_INTRINSIC([v20],vfms_f16,[LLIL_REG.o(v20),LLIL_REG.o(v13),LLIL_CONST.b(0x0)])'),
+ # fmls v3.8h, v10.8h, v22.8h FMLS_asimdsamefp16_only
+ (b'\x43\x0D\xD6\x4E', 'LLIL_INTRINSIC([v3],vfmsq_f16,[LLIL_REG.o(v3),LLIL_REG.o(v10),LLIL_CONST.b(0x0)])'),
+ # fmls h16, h6, v2.h[4] FMLS_asisdelem_RH_H
+ (b'\xD0\x58\x02\x5F', 'LLIL_INTRINSIC([h16],vfmsh_laneq_f16,[LLIL_REG.w(h16),LLIL_REG.w(h6),LLIL_REG.o(v2),LLIL_CONST.b(0x4)])'),
+ # fmls h21, h10, v3.h[7] FMLS_asisdelem_RH_H
+ (b'\x55\x59\x33\x5F', 'LLIL_INTRINSIC([h21],vfmsh_laneq_f16,[LLIL_REG.w(h21),LLIL_REG.w(h10),LLIL_REG.o(v3),LLIL_CONST.b(0x7)])'),
+ # fmls h5, h26, v4.h[3] FMLS_asisdelem_RH_H
+ (b'\x45\x53\x34\x5F', 'LLIL_INTRINSIC([h5],vfmsh_laneq_f16,[LLIL_REG.w(h5),LLIL_REG.w(h26),LLIL_REG.o(v4),LLIL_CONST.b(0x3)])'),
+ # fmls h18, h14, v3.h[6] FMLS_asisdelem_RH_H
+ (b'\xD2\x59\x23\x5F', 'LLIL_INTRINSIC([h18],vfmsh_laneq_f16,[LLIL_REG.w(h18),LLIL_REG.w(h14),LLIL_REG.o(v3),LLIL_CONST.b(0x6)])'),
+ # fmls d25, d21, v24.d[1] FMLS_asisdelem_R_SD
+ (b'\xB9\x5A\xD8\x5F', 'LLIL_INTRINSIC([d25],vfmsd_laneq_f64,[LLIL_REG.q(d25),LLIL_REG.q(d21),LLIL_REG.o(v24),LLIL_CONST.b(0x1)])'),
+ # fmls s6, s31, v5.s[0] FMLS_asisdelem_R_SD
+ (b'\xE6\x53\x85\x5F', 'LLIL_INTRINSIC([s6],vfmss_laneq_f32,[LLIL_REG.d(s6),LLIL_REG.d(s31),LLIL_REG.o(v5),LLIL_CONST.b(0x0)])'),
+ # fmls s3, s4, v7.s[2] FMLS_asisdelem_R_SD
+ (b'\x83\x58\x87\x5F', 'LLIL_INTRINSIC([s3],vfmss_laneq_f32,[LLIL_REG.d(s3),LLIL_REG.d(s4),LLIL_REG.o(v7),LLIL_CONST.b(0x2)])'),
+ # fmls s27, s25, v23.s[3] FMLS_asisdelem_R_SD
+ (b'\x3B\x5B\xB7\x5F', 'LLIL_INTRINSIC([s27],vfmss_laneq_f32,[LLIL_REG.d(s27),LLIL_REG.d(s25),LLIL_REG.o(v23),LLIL_CONST.b(0x3)])'),
+]
+
tests_fadd = [
# fadd d30, d9, d18 FADD_D_FLOATDP2
(b'\x3E\x29\x72\x1E', 'LLIL_SET_REG.q(d30,LLIL_FADD.q(LLIL_REG.q(d9),LLIL_REG.q(d18)))'),
@@ -1938,219 +2555,1400 @@ tests_fadd = [
# fadd s30, s2, s14 FADD_S_FLOATDP2
(b'\x5E\x28\x2E\x1E', 'LLIL_SET_REG.d(s30,LLIL_FADD.d(LLIL_REG.d(s2),LLIL_REG.d(s14)))'),
# fadd v25.2s, v15.2s, v27.2s FADD_ASIMDSAME_ONLY
- (b'\xF9\xD5\x3B\x0E', 'LLIL_SET_REG.d(v25.s[0],LLIL_FADD.d(LLIL_REG.d(v15.s[0]),LLIL_REG.d(v27.s[0])));' + \
- ' LLIL_SET_REG.d(v25.s[1],LLIL_FADD.d(LLIL_REG.d(v15.s[1]),LLIL_REG.d(v27.s[1])))'),
+ (b'\xF9\xD5\x3B\x0E', 'LLIL_INTRINSIC([v25],vadd_f32,[LLIL_REG.o(v15),LLIL_REG.o(v27)])'),
# fadd v26.2s, v15.2s, v21.2s FADD_ASIMDSAME_ONLY
- (b'\xFA\xD5\x35\x0E', 'LLIL_SET_REG.d(v26.s[0],LLIL_FADD.d(LLIL_REG.d(v15.s[0]),LLIL_REG.d(v21.s[0])));' + \
- ' LLIL_SET_REG.d(v26.s[1],LLIL_FADD.d(LLIL_REG.d(v15.s[1]),LLIL_REG.d(v21.s[1])))'),
+ (b'\xFA\xD5\x35\x0E', 'LLIL_INTRINSIC([v26],vadd_f32,[LLIL_REG.o(v15),LLIL_REG.o(v21)])'),
# fadd v21.8h, v20.8h, v16.8h FADD_ASIMDSAMEFP16_ONLY
- (b'\x95\x16\x50\x4E', 'LLIL_SET_REG.w(v21.h[0],LLIL_FADD.w(LLIL_REG.w(v20.h[0]),LLIL_REG.w(v16.h[0])));' + \
- ' LLIL_SET_REG.w(v21.h[1],LLIL_FADD.w(LLIL_REG.w(v20.h[1]),LLIL_REG.w(v16.h[1])));' + \
- ' LLIL_SET_REG.w(v21.h[2],LLIL_FADD.w(LLIL_REG.w(v20.h[2]),LLIL_REG.w(v16.h[2])));' + \
- ' LLIL_SET_REG.w(v21.h[3],LLIL_FADD.w(LLIL_REG.w(v20.h[3]),LLIL_REG.w(v16.h[3])));' + \
- ' LLIL_SET_REG.w(v21.h[4],LLIL_FADD.w(LLIL_REG.w(v20.h[4]),LLIL_REG.w(v16.h[4])));' + \
- ' LLIL_SET_REG.w(v21.h[5],LLIL_FADD.w(LLIL_REG.w(v20.h[5]),LLIL_REG.w(v16.h[5])));' + \
- ' LLIL_SET_REG.w(v21.h[6],LLIL_FADD.w(LLIL_REG.w(v20.h[6]),LLIL_REG.w(v16.h[6])));' + \
- ' LLIL_SET_REG.w(v21.h[7],LLIL_FADD.w(LLIL_REG.w(v20.h[7]),LLIL_REG.w(v16.h[7])))'),
+ (b'\x95\x16\x50\x4E', 'LLIL_INTRINSIC([v21],vaddq_f16,[LLIL_REG.o(v20),LLIL_REG.o(v16)])'),
# fadd v22.8h, v10.8h, v7.8h FADD_ASIMDSAMEFP16_ONLY
- (b'\x56\x15\x47\x4E', 'LLIL_SET_REG.w(v22.h[0],LLIL_FADD.w(LLIL_REG.w(v10.h[0]),LLIL_REG.w(v7.h[0])));' + \
- ' LLIL_SET_REG.w(v22.h[1],LLIL_FADD.w(LLIL_REG.w(v10.h[1]),LLIL_REG.w(v7.h[1])));' + \
- ' LLIL_SET_REG.w(v22.h[2],LLIL_FADD.w(LLIL_REG.w(v10.h[2]),LLIL_REG.w(v7.h[2])));' + \
- ' LLIL_SET_REG.w(v22.h[3],LLIL_FADD.w(LLIL_REG.w(v10.h[3]),LLIL_REG.w(v7.h[3])));' + \
- ' LLIL_SET_REG.w(v22.h[4],LLIL_FADD.w(LLIL_REG.w(v10.h[4]),LLIL_REG.w(v7.h[4])));' + \
- ' LLIL_SET_REG.w(v22.h[5],LLIL_FADD.w(LLIL_REG.w(v10.h[5]),LLIL_REG.w(v7.h[5])));' + \
- ' LLIL_SET_REG.w(v22.h[6],LLIL_FADD.w(LLIL_REG.w(v10.h[6]),LLIL_REG.w(v7.h[6])));' + \
- ' LLIL_SET_REG.w(v22.h[7],LLIL_FADD.w(LLIL_REG.w(v10.h[7]),LLIL_REG.w(v7.h[7])))'),
+ (b'\x56\x15\x47\x4E', 'LLIL_INTRINSIC([v22],vaddq_f16,[LLIL_REG.o(v10),LLIL_REG.o(v7)])'),
+]
+
+tests_f_mathops = [
+ # fabd v5.4s, v18.4s, v1.4s FABD_asimdsame_only
+ (b'\x45\xD6\xA1\x6E', 'LLIL_INTRINSIC([v5],vabdq_f32,[LLIL_REG.o(v18),LLIL_REG.o(v1)])'),
+ # fabd v20.2d, v13.2d, v29.2d FABD_asimdsame_only
+ (b'\xB4\xD5\xFD\x6E', 'LLIL_INTRINSIC([v20],vabdq_f64,[LLIL_REG.o(v13),LLIL_REG.o(v29)])'),
+ # fabd v9.2d, v30.2d, v20.2d FABD_asimdsame_only
+ (b'\xC9\xD7\xF4\x6E', 'LLIL_INTRINSIC([v9],vabdq_f64,[LLIL_REG.o(v30),LLIL_REG.o(v20)])'),
+ # fabd v24.4s, v1.4s, v16.4s FABD_asimdsame_only
+ (b'\x38\xD4\xB0\x6E', 'LLIL_INTRINSIC([v24],vabdq_f32,[LLIL_REG.o(v1),LLIL_REG.o(v16)])'),
+ # fabd v22.8h, v27.8h, v18.8h FABD_asimdsamefp16_only
+ (b'\x76\x17\xD2\x6E', 'LLIL_INTRINSIC([v22],vabdq_f16,[LLIL_REG.o(v27),LLIL_REG.o(v18)])'),
+ # fabd v5.8h, v15.8h, v20.8h FABD_asimdsamefp16_only
+ (b'\xE5\x15\xD4\x6E', 'LLIL_INTRINSIC([v5],vabdq_f16,[LLIL_REG.o(v15),LLIL_REG.o(v20)])'),
+ # fabd v31.8h, v28.8h, v7.8h FABD_asimdsamefp16_only
+ (b'\x9F\x17\xC7\x6E', 'LLIL_INTRINSIC([v31],vabdq_f16,[LLIL_REG.o(v28),LLIL_REG.o(v7)])'),
+ # fabd v28.8h, v2.8h, v26.8h FABD_asimdsamefp16_only
+ (b'\x5C\x14\xDA\x6E', 'LLIL_INTRINSIC([v28],vabdq_f16,[LLIL_REG.o(v2),LLIL_REG.o(v26)])'),
+ # fabd s0, s6, s10 FABD_asisdsame_only
+ (b'\xC0\xD4\xAA\x7E', 'LLIL_SET_REG.d(s0,LLIL_FABS.d(LLIL_FSUB.d(LLIL_REG.d(s6),LLIL_REG.d(s10))))'),
+ # fabd s12, s17, s2 FABD_asisdsame_only
+ (b'\x2C\xD6\xA2\x7E', 'LLIL_SET_REG.d(s12,LLIL_FABS.d(LLIL_FSUB.d(LLIL_REG.d(s17),LLIL_REG.d(s2))))'),
+ # fabd s10, s25, s8 FABD_asisdsame_only
+ (b'\x2A\xD7\xA8\x7E', 'LLIL_SET_REG.d(s10,LLIL_FABS.d(LLIL_FSUB.d(LLIL_REG.d(s25),LLIL_REG.d(s8))))'),
+ # fabd d25, d6, d31 FABD_asisdsame_only
+ (b'\xD9\xD4\xFF\x7E', 'LLIL_SET_REG.q(d25,LLIL_FABS.q(LLIL_FSUB.q(LLIL_REG.q(d6),LLIL_REG.q(d31))))'),
+ # fabd h9, h1, h5 FABD_asisdsamefp16_only
+ (b'\x29\x14\xC5\x7E', 'LLIL_SET_REG.w(h9,LLIL_FABS.w(LLIL_FSUB.w(LLIL_REG.w(h1),LLIL_REG.w(h5))))'),
+ # fabd h24, h21, h17 FABD_asisdsamefp16_only
+ (b'\xB8\x16\xD1\x7E', 'LLIL_SET_REG.w(h24,LLIL_FABS.w(LLIL_FSUB.w(LLIL_REG.w(h21),LLIL_REG.w(h17))))'),
+ # fabd h28, h22, h9 FABD_asisdsamefp16_only
+ (b'\xDC\x16\xC9\x7E', 'LLIL_SET_REG.w(h28,LLIL_FABS.w(LLIL_FSUB.w(LLIL_REG.w(h22),LLIL_REG.w(h9))))'),
+ # fabd h0, h18, h28 FABD_asisdsamefp16_only
+ (b'\x40\x16\xDC\x7E', 'LLIL_SET_REG.w(h0,LLIL_FABS.w(LLIL_FSUB.w(LLIL_REG.w(h18),LLIL_REG.w(h28))))'),
+ # fabs d15, d0 FABS_D_floatdp1
+ (b'\x0F\xC0\x60\x1E', 'LLIL_SET_REG.q(d15,LLIL_FABS.q(LLIL_REG.q(d0)))'),
+ # fabs d13, d28 FABS_D_floatdp1
+ (b'\x8D\xC3\x60\x1E', 'LLIL_SET_REG.q(d13,LLIL_FABS.q(LLIL_REG.q(d28)))'),
+ # fabs d14, d31 FABS_D_floatdp1
+ (b'\xEE\xC3\x60\x1E', 'LLIL_SET_REG.q(d14,LLIL_FABS.q(LLIL_REG.q(d31)))'),
+ # fabs d8, d23 FABS_D_floatdp1
+ (b'\xE8\xC2\x60\x1E', 'LLIL_SET_REG.q(d8,LLIL_FABS.q(LLIL_REG.q(d23)))'),
+ # fabs h26, h26 FABS_H_floatdp1
+ (b'\x5A\xC3\xE0\x1E', 'LLIL_SET_REG.w(h26,LLIL_FABS.w(LLIL_REG.w(h26)))'),
+ # fabs h26, h28 FABS_H_floatdp1
+ (b'\x9A\xC3\xE0\x1E', 'LLIL_SET_REG.w(h26,LLIL_FABS.w(LLIL_REG.w(h28)))'),
+ # fabs h6, h23 FABS_H_floatdp1
+ (b'\xE6\xC2\xE0\x1E', 'LLIL_SET_REG.w(h6,LLIL_FABS.w(LLIL_REG.w(h23)))'),
+ # fabs h26, h4 FABS_H_floatdp1
+ (b'\x9A\xC0\xE0\x1E', 'LLIL_SET_REG.w(h26,LLIL_FABS.w(LLIL_REG.w(h4)))'),
+ # fabs s15, s22 FABS_S_floatdp1
+ (b'\xCF\xC2\x20\x1E', 'LLIL_SET_REG.d(s15,LLIL_FABS.d(LLIL_REG.d(s22)))'),
+ # fabs s10, s2 FABS_S_floatdp1
+ (b'\x4A\xC0\x20\x1E', 'LLIL_SET_REG.d(s10,LLIL_FABS.d(LLIL_REG.d(s2)))'),
+ # fabs s9, s26 FABS_S_floatdp1
+ (b'\x49\xC3\x20\x1E', 'LLIL_SET_REG.d(s9,LLIL_FABS.d(LLIL_REG.d(s26)))'),
+ # fabs s3, s1 FABS_S_floatdp1
+ (b'\x23\xC0\x20\x1E', 'LLIL_SET_REG.d(s3,LLIL_FABS.d(LLIL_REG.d(s1)))'),
+ # fabs v30.4s, v3.4s FABS_asimdmisc_R
+ (b'\x7E\xF8\xA0\x4E', 'LLIL_INTRINSIC([v30],vabsq_f32,[LLIL_REG.o(v3)])'),
+ # fabs v30.2s, v21.2s FABS_asimdmisc_R
+ (b'\xBE\xFA\xA0\x0E', 'LLIL_INTRINSIC([v30],vabs_f32,[LLIL_REG.o(v21)])'),
+ # fabs v13.2d, v31.2d FABS_asimdmisc_R
+ (b'\xED\xFB\xE0\x4E', 'LLIL_INTRINSIC([v13],vabsq_f64,[LLIL_REG.o(v31)])'),
+ # fabs v20.4s, v28.4s FABS_asimdmisc_R
+ (b'\x94\xFB\xA0\x4E', 'LLIL_INTRINSIC([v20],vabsq_f32,[LLIL_REG.o(v28)])'),
+ # fabs v23.8h, v2.8h FABS_asimdmiscfp16_R
+ (b'\x57\xF8\xF8\x4E', 'LLIL_INTRINSIC([v23],vabsq_f16,[LLIL_REG.o(v2)])'),
+ # fabs v25.8h, v12.8h FABS_asimdmiscfp16_R
+ (b'\x99\xF9\xF8\x4E', 'LLIL_INTRINSIC([v25],vabsq_f16,[LLIL_REG.o(v12)])'),
+ # fabs v27.4h, v16.4h FABS_asimdmiscfp16_R
+ (b'\x1B\xFA\xF8\x0E', 'LLIL_INTRINSIC([v27],vabs_f16,[LLIL_REG.o(v16)])'),
+ # fabs v20.8h, v22.8h FABS_asimdmiscfp16_R
+ (b'\xD4\xFA\xF8\x4E', 'LLIL_INTRINSIC([v20],vabsq_f16,[LLIL_REG.o(v22)])'),
+ # faddp v21.4s, v1.4s, v10.4s FADDP_asimdsame_only
+ (b'\x35\xD4\x2A\x6E', 'LLIL_INTRINSIC([v21],vpaddq_f32,[LLIL_REG.o(v1),LLIL_REG.o(v10)])'),
+ # faddp v31.4s, v1.4s, v15.4s FADDP_asimdsame_only
+ (b'\x3F\xD4\x2F\x6E', 'LLIL_INTRINSIC([v31],vpaddq_f32,[LLIL_REG.o(v1),LLIL_REG.o(v15)])'),
+ # faddp v28.4s, v16.4s, v5.4s FADDP_asimdsame_only
+ (b'\x1C\xD6\x25\x6E', 'LLIL_INTRINSIC([v28],vpaddq_f32,[LLIL_REG.o(v16),LLIL_REG.o(v5)])'),
+ # faddp v7.2d, v5.2d, v2.2d FADDP_asimdsame_only
+ (b'\xA7\xD4\x62\x6E', 'LLIL_INTRINSIC([v7],vpaddq_f64,[LLIL_REG.o(v5),LLIL_REG.o(v2)])'),
+ # faddp v9.8h, v27.8h, v27.8h FADDP_asimdsamefp16_only
+ (b'\x69\x17\x5B\x6E', 'LLIL_INTRINSIC([v9],vpaddq_f16,[LLIL_REG.o(v27),LLIL_REG.o(v27)])'),
+ # faddp v29.8h, v15.8h, v25.8h FADDP_asimdsamefp16_only
+ (b'\xFD\x15\x59\x6E', 'LLIL_INTRINSIC([v29],vpaddq_f16,[LLIL_REG.o(v15),LLIL_REG.o(v25)])'),
+ # faddp v17.8h, v20.8h, v24.8h FADDP_asimdsamefp16_only
+ (b'\x91\x16\x58\x6E', 'LLIL_INTRINSIC([v17],vpaddq_f16,[LLIL_REG.o(v20),LLIL_REG.o(v24)])'),
+ # faddp v7.8h, v22.8h, v25.8h FADDP_asimdsamefp16_only
+ (b'\xC7\x16\x59\x6E', 'LLIL_INTRINSIC([v7],vpaddq_f16,[LLIL_REG.o(v22),LLIL_REG.o(v25)])'),
+ # faddp h21, v31.2h FADDP_asisdpair_only_H
+ (b'\xF5\xDB\x30\x5E', 'LLIL_SET_REG.w(h21,LLIL_FADD.w(LLIL_REG.w(v31.h[0]),LLIL_REG.w(v31.h[1])))'),
+ # faddp h3, v31.2h FADDP_asisdpair_only_H
+ (b'\xE3\xDB\x30\x5E', 'LLIL_SET_REG.w(h3,LLIL_FADD.w(LLIL_REG.w(v31.h[0]),LLIL_REG.w(v31.h[1])))'),
+ # faddp h23, v7.2h FADDP_asisdpair_only_H
+ (b'\xF7\xD8\x30\x5E', 'LLIL_SET_REG.w(h23,LLIL_FADD.w(LLIL_REG.w(v7.h[0]),LLIL_REG.w(v7.h[1])))'),
+ # faddp h5, v17.2h FADDP_asisdpair_only_H
+ (b'\x25\xDA\x30\x5E', 'LLIL_SET_REG.w(h5,LLIL_FADD.w(LLIL_REG.w(v17.h[0]),LLIL_REG.w(v17.h[1])))'),
+ # faddp d29, v25.2d FADDP_asisdpair_only_SD
+ (b'\x3D\xDB\x70\x7E', 'LLIL_SET_REG.q(d29,LLIL_FADD.q(LLIL_REG.q(v25.d[0]),LLIL_REG.q(v25.d[1])))'),
+ # faddp d6, v16.2d FADDP_asisdpair_only_SD
+ (b'\x06\xDA\x70\x7E', 'LLIL_SET_REG.q(d6,LLIL_FADD.q(LLIL_REG.q(v16.d[0]),LLIL_REG.q(v16.d[1])))'),
+ # faddp s26, v8.2s FADDP_asisdpair_only_SD
+ (b'\x1A\xD9\x30\x7E', 'LLIL_SET_REG.d(s26,LLIL_FADD.d(LLIL_REG.d(v8.s[0]),LLIL_REG.d(v8.s[1])))'),
+ # faddp d15, v7.2d FADDP_asisdpair_only_SD
+ (b'\xEF\xD8\x70\x7E', 'LLIL_SET_REG.q(d15,LLIL_FADD.q(LLIL_REG.q(v7.d[0]),LLIL_REG.q(v7.d[1])))'),
+ # fmaxnmp v15.4s, v11.4s, v8.4s FMAXNMP_asimdsame_only
+ (b'\x6F\xC5\x28\x6E', 'LLIL_INTRINSIC([v15],vpmaxnmq_f32,[LLIL_REG.o(v11),LLIL_REG.o(v8)])'),
+ # fmaxnmp v30.4s, v31.4s, v2.4s FMAXNMP_asimdsame_only
+ (b'\xFE\xC7\x22\x6E', 'LLIL_INTRINSIC([v30],vpmaxnmq_f32,[LLIL_REG.o(v31),LLIL_REG.o(v2)])'),
+ # fmaxnmp v11.4s, v17.4s, v31.4s FMAXNMP_asimdsame_only
+ (b'\x2B\xC6\x3F\x6E', 'LLIL_INTRINSIC([v11],vpmaxnmq_f32,[LLIL_REG.o(v17),LLIL_REG.o(v31)])'),
+ # fmaxnmp v10.2s, v3.2s, v10.2s FMAXNMP_asimdsame_only
+ (b'\x6A\xC4\x2A\x2E', 'LLIL_INTRINSIC([v10],vpmaxnm_f32,[LLIL_REG.o(v3),LLIL_REG.o(v10)])'),
+ # fmaxnmp v16.4h, v16.4h, v29.4h FMAXNMP_asimdsamefp16_only
+ (b'\x10\x06\x5D\x2E', 'LLIL_INTRINSIC([v16],vpmaxnm_f16,[LLIL_REG.o(v16),LLIL_REG.o(v29)])'),
+ # fmaxnmp v2.8h, v18.8h, v4.8h FMAXNMP_asimdsamefp16_only
+ (b'\x42\x06\x44\x6E', 'LLIL_INTRINSIC([v2],vpmaxnmq_f16,[LLIL_REG.o(v18),LLIL_REG.o(v4)])'),
+ # fmaxnmp v22.4h, v22.4h, v3.4h FMAXNMP_asimdsamefp16_only
+ (b'\xD6\x06\x43\x2E', 'LLIL_INTRINSIC([v22],vpmaxnm_f16,[LLIL_REG.o(v22),LLIL_REG.o(v3)])'),
+ # fmaxnmp v18.4h, v0.4h, v17.4h FMAXNMP_asimdsamefp16_only
+ (b'\x12\x04\x51\x2E', 'LLIL_INTRINSIC([v18],vpmaxnm_f16,[LLIL_REG.o(v0),LLIL_REG.o(v17)])'),
+ # fmaxnmp h12, v1.2h FMAXNMP_asisdpair_only_H
+ (b'\x2C\xC8\x30\x5E', 'LLIL_INTRINSIC([h12],vmaxnmv_f16,[LLIL_REG.o(v1)])'),
+ # fmaxnmp h28, v1.2h FMAXNMP_asisdpair_only_H
+ (b'\x3C\xC8\x30\x5E', 'LLIL_INTRINSIC([h28],vmaxnmv_f16,[LLIL_REG.o(v1)])'),
+ # fmaxnmp h7, v8.2h FMAXNMP_asisdpair_only_H
+ (b'\x07\xC9\x30\x5E', 'LLIL_INTRINSIC([h7],vmaxnmv_f16,[LLIL_REG.o(v8)])'),
+ # fmaxnmp h15, v25.2h FMAXNMP_asisdpair_only_H
+ (b'\x2F\xCB\x30\x5E', 'LLIL_INTRINSIC([h15],vmaxnmv_f16,[LLIL_REG.o(v25)])'),
+ # fmaxnmp d21, v24.2d FMAXNMP_asisdpair_only_SD
+ (b'\x15\xCB\x70\x7E', 'LLIL_INTRINSIC([d21],vpmaxnmqd_f64,[LLIL_REG.o(v24)])'),
+ # fmaxnmp s27, v11.2s FMAXNMP_asisdpair_only_SD
+ (b'\x7B\xC9\x30\x7E', 'LLIL_INTRINSIC([s27],vpmaxnms_f32,[LLIL_REG.o(v11)])'),
+ # fmaxnmp s4, v30.2s FMAXNMP_asisdpair_only_SD
+ (b'\xC4\xCB\x30\x7E', 'LLIL_INTRINSIC([s4],vpmaxnms_f32,[LLIL_REG.o(v30)])'),
+ # fmaxnmp d12, v27.2d FMAXNMP_asisdpair_only_SD
+ (b'\x6C\xCB\x70\x7E', 'LLIL_INTRINSIC([d12],vpmaxnmqd_f64,[LLIL_REG.o(v27)])'),
+ # fmaxnmv h31, v22.4h FMAXNMV_asimdall_only_H
+ (b'\xDF\xCA\x30\x0E', 'LLIL_INTRINSIC([h31],vmaxnmvq_f16,[LLIL_REG.o(v22)])'),
+ # fmaxnmv h31, v6.8h FMAXNMV_asimdall_only_H
+ (b'\xDF\xC8\x30\x4E', 'LLIL_INTRINSIC([h31],vmaxnmvq_f16,[LLIL_REG.o(v6)])'),
+ # fmaxnmv h25, v22.8h FMAXNMV_asimdall_only_H
+ (b'\xD9\xCA\x30\x4E', 'LLIL_INTRINSIC([h25],vmaxnmvq_f16,[LLIL_REG.o(v22)])'),
+ # fmaxnmv h5, v25.8h FMAXNMV_asimdall_only_H
+ (b'\x25\xCB\x30\x4E', 'LLIL_INTRINSIC([h5],vmaxnmvq_f16,[LLIL_REG.o(v25)])'),
+ # fmaxnmv s21, v0.4s FMAXNMV_asimdall_only_SD
+ (b'\x15\xC8\x30\x6E', 'LLIL_INTRINSIC([s21],vmaxnmvq_f32,[LLIL_REG.o(v0)])'),
+ # fmaxnmv s22, v1.4s FMAXNMV_asimdall_only_SD
+ (b'\x36\xC8\x30\x6E', 'LLIL_INTRINSIC([s22],vmaxnmvq_f32,[LLIL_REG.o(v1)])'),
+ # fmaxnmv s1, v26.4s FMAXNMV_asimdall_only_SD
+ (b'\x41\xCB\x30\x6E', 'LLIL_INTRINSIC([s1],vmaxnmvq_f32,[LLIL_REG.o(v26)])'),
+ # fmaxnmv s0, v15.4s FMAXNMV_asimdall_only_SD
+ (b'\xE0\xC9\x30\x6E', 'LLIL_INTRINSIC([s0],vmaxnmvq_f32,[LLIL_REG.o(v15)])'),
+ # fmaxnm d2, d13, d24 FMAXNM_D_floatdp2
+ (b'\xA2\x69\x78\x1E', 'LLIL_INTRINSIC([d2],vmaxnm_f64,[LLIL_REG.q(d13),LLIL_REG.q(d24)])'),
+ # fmaxnm d10, d0, d17 FMAXNM_D_floatdp2
+ (b'\x0A\x68\x71\x1E', 'LLIL_INTRINSIC([d10],vmaxnm_f64,[LLIL_REG.q(d0),LLIL_REG.q(d17)])'),
+ # fmaxnm d25, d23, d24 FMAXNM_D_floatdp2
+ (b'\xF9\x6A\x78\x1E', 'LLIL_INTRINSIC([d25],vmaxnm_f64,[LLIL_REG.q(d23),LLIL_REG.q(d24)])'),
+ # fmaxnm d31, d2, d22 FMAXNM_D_floatdp2
+ (b'\x5F\x68\x76\x1E', 'LLIL_INTRINSIC([d31],vmaxnm_f64,[LLIL_REG.q(d2),LLIL_REG.q(d22)])'),
+ # fmaxnm h11, h22, h27 FMAXNM_H_floatdp2
+ (b'\xCB\x6A\xFB\x1E', 'LLIL_INTRINSIC([h11],vmaxnmh_f16,[LLIL_REG.w(h22),LLIL_REG.w(h27)])'),
+ # fmaxnm h17, h8, h2 FMAXNM_H_floatdp2
+ (b'\x11\x69\xE2\x1E', 'LLIL_INTRINSIC([h17],vmaxnmh_f16,[LLIL_REG.w(h8),LLIL_REG.w(h2)])'),
+ # fmaxnm h20, h9, h26 FMAXNM_H_floatdp2
+ (b'\x34\x69\xFA\x1E', 'LLIL_INTRINSIC([h20],vmaxnmh_f16,[LLIL_REG.w(h9),LLIL_REG.w(h26)])'),
+ # fmaxnm h4, h1, h16 FMAXNM_H_floatdp2
+ (b'\x24\x68\xF0\x1E', 'LLIL_INTRINSIC([h4],vmaxnmh_f16,[LLIL_REG.w(h1),LLIL_REG.w(h16)])'),
+ # fmaxnm s31, s22, s6 FMAXNM_S_floatdp2
+ (b'\xDF\x6A\x26\x1E', 'LLIL_INTRINSIC([s31],vmaxnm_f32,[LLIL_REG.d(s22),LLIL_REG.d(s6)])'),
+ # fmaxnm s12, s25, s3 FMAXNM_S_floatdp2
+ (b'\x2C\x6B\x23\x1E', 'LLIL_INTRINSIC([s12],vmaxnm_f32,[LLIL_REG.d(s25),LLIL_REG.d(s3)])'),
+ # fmaxnm s12, s11, s6 FMAXNM_S_floatdp2
+ (b'\x6C\x69\x26\x1E', 'LLIL_INTRINSIC([s12],vmaxnm_f32,[LLIL_REG.d(s11),LLIL_REG.d(s6)])'),
+ # fmaxnm s6, s12, s22 FMAXNM_S_floatdp2
+ (b'\x86\x69\x36\x1E', 'LLIL_INTRINSIC([s6],vmaxnm_f32,[LLIL_REG.d(s12),LLIL_REG.d(s22)])'),
+ # fmaxnm v21.2s, v5.2s, v8.2s FMAXNM_asimdsame_only
+ (b'\xB5\xC4\x28\x0E', 'LLIL_INTRINSIC([v21],vmaxnm_f32,[LLIL_REG.o(v5),LLIL_REG.o(v8)])'),
+ # fmaxnm v15.4s, v14.4s, v2.4s FMAXNM_asimdsame_only
+ (b'\xCF\xC5\x22\x4E', 'LLIL_INTRINSIC([v15],vmaxnmq_f32,[LLIL_REG.o(v14),LLIL_REG.o(v2)])'),
+ # fmaxnm v30.2s, v0.2s, v16.2s FMAXNM_asimdsame_only
+ (b'\x1E\xC4\x30\x0E', 'LLIL_INTRINSIC([v30],vmaxnm_f32,[LLIL_REG.o(v0),LLIL_REG.o(v16)])'),
+ # fmaxnm v2.2s, v25.2s, v2.2s FMAXNM_asimdsame_only
+ (b'\x22\xC7\x22\x0E', 'LLIL_INTRINSIC([v2],vmaxnm_f32,[LLIL_REG.o(v25),LLIL_REG.o(v2)])'),
+ # fmaxnm v13.8h, v24.8h, v4.8h FMAXNM_asimdsamefp16_only
+ (b'\x0D\x07\x44\x4E', 'LLIL_INTRINSIC([v13],vmaxnmq_f16,[LLIL_REG.o(v24),LLIL_REG.o(v4)])'),
+ # fmaxnm v10.8h, v1.8h, v3.8h FMAXNM_asimdsamefp16_only
+ (b'\x2A\x04\x43\x4E', 'LLIL_INTRINSIC([v10],vmaxnmq_f16,[LLIL_REG.o(v1),LLIL_REG.o(v3)])'),
+ # fmaxnm v19.8h, v28.8h, v24.8h FMAXNM_asimdsamefp16_only
+ (b'\x93\x07\x58\x4E', 'LLIL_INTRINSIC([v19],vmaxnmq_f16,[LLIL_REG.o(v28),LLIL_REG.o(v24)])'),
+ # fmaxnm v8.4h, v31.4h, v11.4h FMAXNM_asimdsamefp16_only
+ (b'\xE8\x07\x4B\x0E', 'LLIL_INTRINSIC([v8],vmaxnm_f16,[LLIL_REG.o(v31),LLIL_REG.o(v11)])'),
+ # fmaxp v30.4s, v22.4s, v28.4s FMAXP_asimdsame_only
+ (b'\xDE\xF6\x3C\x6E', 'LLIL_INTRINSIC([v30],vpmaxq_f32,[LLIL_REG.o(v22),LLIL_REG.o(v28)])'),
+ # fmaxp v23.4s, v6.4s, v0.4s FMAXP_asimdsame_only
+ (b'\xD7\xF4\x20\x6E', 'LLIL_INTRINSIC([v23],vpmaxq_f32,[LLIL_REG.o(v6),LLIL_REG.o(v0)])'),
+ # fmaxp v7.4s, v17.4s, v1.4s FMAXP_asimdsame_only
+ (b'\x27\xF6\x21\x6E', 'LLIL_INTRINSIC([v7],vpmaxq_f32,[LLIL_REG.o(v17),LLIL_REG.o(v1)])'),
+ # fmaxp v30.2d, v28.2d, v0.2d FMAXP_asimdsame_only
+ (b'\x9E\xF7\x60\x6E', 'LLIL_INTRINSIC([v30],vpmaxq_f64,[LLIL_REG.o(v28),LLIL_REG.o(v0)])'),
+ # fmaxp v12.4h, v23.4h, v28.4h FMAXP_asimdsamefp16_only
+ (b'\xEC\x36\x5C\x2E', 'LLIL_INTRINSIC([v12],vpmax_f16,[LLIL_REG.o(v23),LLIL_REG.o(v28)])'),
+ # fmaxp v2.8h, v26.8h, v18.8h FMAXP_asimdsamefp16_only
+ (b'\x42\x37\x52\x6E', 'LLIL_INTRINSIC([v2],vpmaxq_f16,[LLIL_REG.o(v26),LLIL_REG.o(v18)])'),
+ # fmaxp v27.8h, v18.8h, v1.8h FMAXP_asimdsamefp16_only
+ (b'\x5B\x36\x41\x6E', 'LLIL_INTRINSIC([v27],vpmaxq_f16,[LLIL_REG.o(v18),LLIL_REG.o(v1)])'),
+ # fmaxp v10.8h, v15.8h, v4.8h FMAXP_asimdsamefp16_only
+ (b'\xEA\x35\x44\x6E', 'LLIL_INTRINSIC([v10],vpmaxq_f16,[LLIL_REG.o(v15),LLIL_REG.o(v4)])'),
+ # fmaxp h3, v10.2h FMAXP_asisdpair_only_H
+ (b'\x43\xF9\x30\x5E', 'LLIL_INTRINSIC([h3],vmaxv_f16,[LLIL_REG.o(v10)])'),
+ # fmaxp h23, v5.2h FMAXP_asisdpair_only_H
+ (b'\xB7\xF8\x30\x5E', 'LLIL_INTRINSIC([h23],vmaxv_f16,[LLIL_REG.o(v5)])'),
+ # fmaxp h6, v31.2h FMAXP_asisdpair_only_H
+ (b'\xE6\xFB\x30\x5E', 'LLIL_INTRINSIC([h6],vmaxv_f16,[LLIL_REG.o(v31)])'),
+ # fmaxp h24, v5.2h FMAXP_asisdpair_only_H
+ (b'\xB8\xF8\x30\x5E', 'LLIL_INTRINSIC([h24],vmaxv_f16,[LLIL_REG.o(v5)])'),
+ # fmaxp d19, v15.2d FMAXP_asisdpair_only_SD
+ (b'\xF3\xF9\x70\x7E', 'LLIL_INTRINSIC([d19],vpmaxqd_f64,[LLIL_REG.o(v15)])'),
+ # fmaxp d14, v6.2d FMAXP_asisdpair_only_SD
+ (b'\xCE\xF8\x70\x7E', 'LLIL_INTRINSIC([d14],vpmaxqd_f64,[LLIL_REG.o(v6)])'),
+ # fmaxp d1, v4.2d FMAXP_asisdpair_only_SD
+ (b'\x81\xF8\x70\x7E', 'LLIL_INTRINSIC([d1],vpmaxqd_f64,[LLIL_REG.o(v4)])'),
+ # fmaxp s29, v2.2s FMAXP_asisdpair_only_SD
+ (b'\x5D\xF8\x30\x7E', 'LLIL_INTRINSIC([s29],vpmaxs_f32,[LLIL_REG.o(v2)])'),
+ # fmaxv h28, v6.4h FMAXV_asimdall_only_H
+ (b'\xDC\xF8\x30\x0E', 'LLIL_INTRINSIC([h28],vmaxvq_f16,[LLIL_REG.o(v6)])'),
+ # fmaxv h6, v16.8h FMAXV_asimdall_only_H
+ (b'\x06\xFA\x30\x4E', 'LLIL_INTRINSIC([h6],vmaxvq_f16,[LLIL_REG.o(v16)])'),
+ # fmaxv h2, v24.4h FMAXV_asimdall_only_H
+ (b'\x02\xFB\x30\x0E', 'LLIL_INTRINSIC([h2],vmaxvq_f16,[LLIL_REG.o(v24)])'),
+ # fmaxv h20, v5.8h FMAXV_asimdall_only_H
+ (b'\xB4\xF8\x30\x4E', 'LLIL_INTRINSIC([h20],vmaxvq_f16,[LLIL_REG.o(v5)])'),
+ # fmaxv s24, v3.4s FMAXV_asimdall_only_SD
+ (b'\x78\xF8\x30\x6E', 'LLIL_INTRINSIC([s24],vmaxvq_f32,[LLIL_REG.o(v3)])'),
+ # fmaxv s12, v22.4s FMAXV_asimdall_only_SD
+ (b'\xCC\xFA\x30\x6E', 'LLIL_INTRINSIC([s12],vmaxvq_f32,[LLIL_REG.o(v22)])'),
+ # fmaxv s6, v20.4s FMAXV_asimdall_only_SD
+ (b'\x86\xFA\x30\x6E', 'LLIL_INTRINSIC([s6],vmaxvq_f32,[LLIL_REG.o(v20)])'),
+ # fmaxv s1, v7.4s FMAXV_asimdall_only_SD
+ (b'\xE1\xF8\x30\x6E', 'LLIL_INTRINSIC([s1],vmaxvq_f32,[LLIL_REG.o(v7)])'),
+ # fmax d5, d3, d24 FMAX_D_floatdp2
+ (b'\x65\x48\x78\x1E', 'LLIL_INTRINSIC([d5],vmax_f64,[LLIL_REG.q(d3),LLIL_REG.q(d24)])'),
+ # fmax d18, d1, d30 FMAX_D_floatdp2
+ (b'\x32\x48\x7E\x1E', 'LLIL_INTRINSIC([d18],vmax_f64,[LLIL_REG.q(d1),LLIL_REG.q(d30)])'),
+ # fmax d15, d28, d0 FMAX_D_floatdp2
+ (b'\x8F\x4B\x60\x1E', 'LLIL_INTRINSIC([d15],vmax_f64,[LLIL_REG.q(d28),LLIL_REG.q(d0)])'),
+ # fmax d1, d23, d7 FMAX_D_floatdp2
+ (b'\xE1\x4A\x67\x1E', 'LLIL_INTRINSIC([d1],vmax_f64,[LLIL_REG.q(d23),LLIL_REG.q(d7)])'),
+ # fmax h22, h21, h23 FMAX_H_floatdp2
+ (b'\xB6\x4A\xF7\x1E', 'LLIL_INTRINSIC([h22],vmaxh_f16,[LLIL_REG.w(h21),LLIL_REG.w(h23)])'),
+ # fmax h3, h0, h31 FMAX_H_floatdp2
+ (b'\x03\x48\xFF\x1E', 'LLIL_INTRINSIC([h3],vmaxh_f16,[LLIL_REG.w(h0),LLIL_REG.w(h31)])'),
+ # fmax h21, h2, h8 FMAX_H_floatdp2
+ (b'\x55\x48\xE8\x1E', 'LLIL_INTRINSIC([h21],vmaxh_f16,[LLIL_REG.w(h2),LLIL_REG.w(h8)])'),
+ # fmax h16, h13, h19 FMAX_H_floatdp2
+ (b'\xB0\x49\xF3\x1E', 'LLIL_INTRINSIC([h16],vmaxh_f16,[LLIL_REG.w(h13),LLIL_REG.w(h19)])'),
+ # fmax s6, s15, s15 FMAX_S_floatdp2
+ (b'\xE6\x49\x2F\x1E', 'LLIL_INTRINSIC([s6],vmax_f32,[LLIL_REG.d(s15),LLIL_REG.d(s15)])'),
+ # fmax s10, s15, s3 FMAX_S_floatdp2
+ (b'\xEA\x49\x23\x1E', 'LLIL_INTRINSIC([s10],vmax_f32,[LLIL_REG.d(s15),LLIL_REG.d(s3)])'),
+ # fmax s22, s13, s3 FMAX_S_floatdp2
+ (b'\xB6\x49\x23\x1E', 'LLIL_INTRINSIC([s22],vmax_f32,[LLIL_REG.d(s13),LLIL_REG.d(s3)])'),
+ # fmax s30, s20, s26 FMAX_S_floatdp2
+ (b'\x9E\x4A\x3A\x1E', 'LLIL_INTRINSIC([s30],vmax_f32,[LLIL_REG.d(s20),LLIL_REG.d(s26)])'),
+ # fmax v13.2s, v14.2s, v13.2s FMAX_asimdsame_only
+ (b'\xCD\xF5\x2D\x0E', 'LLIL_INTRINSIC([v13],vmax_f32,[LLIL_REG.o(v14),LLIL_REG.o(v13)])'),
+ # fmax v18.2s, v2.2s, v16.2s FMAX_asimdsame_only
+ (b'\x52\xF4\x30\x0E', 'LLIL_INTRINSIC([v18],vmax_f32,[LLIL_REG.o(v2),LLIL_REG.o(v16)])'),
+ # fmax v13.4s, v26.4s, v11.4s FMAX_asimdsame_only
+ (b'\x4D\xF7\x2B\x4E', 'LLIL_INTRINSIC([v13],vmaxq_f32,[LLIL_REG.o(v26),LLIL_REG.o(v11)])'),
+ # fmax v24.2d, v31.2d, v11.2d FMAX_asimdsame_only
+ (b'\xF8\xF7\x6B\x4E', 'LLIL_INTRINSIC([v24],vmaxq_f64,[LLIL_REG.o(v31),LLIL_REG.o(v11)])'),
+ # fmax v4.8h, v18.8h, v21.8h FMAX_asimdsamefp16_only
+ (b'\x44\x36\x55\x4E', 'LLIL_INTRINSIC([v4],vmaxq_f16,[LLIL_REG.o(v18),LLIL_REG.o(v21)])'),
+ # fmax v14.8h, v20.8h, v24.8h FMAX_asimdsamefp16_only
+ (b'\x8E\x36\x58\x4E', 'LLIL_INTRINSIC([v14],vmaxq_f16,[LLIL_REG.o(v20),LLIL_REG.o(v24)])'),
+ # fmax v9.8h, v15.8h, v7.8h FMAX_asimdsamefp16_only
+ (b'\xE9\x35\x47\x4E', 'LLIL_INTRINSIC([v9],vmaxq_f16,[LLIL_REG.o(v15),LLIL_REG.o(v7)])'),
+ # fmax v28.8h, v26.8h, v29.8h FMAX_asimdsamefp16_only
+ (b'\x5C\x37\x5D\x4E', 'LLIL_INTRINSIC([v28],vmaxq_f16,[LLIL_REG.o(v26),LLIL_REG.o(v29)])'),
+ # fminnmp v21.2s, v24.2s, v31.2s FMINNMP_asimdsame_only
+ (b'\x15\xC7\xBF\x2E', 'LLIL_INTRINSIC([v21],vpminnm_f32,[LLIL_REG.o(v24),LLIL_REG.o(v31)])'),
+ # fminnmp v6.2s, v18.2s, v4.2s FMINNMP_asimdsame_only
+ (b'\x46\xC6\xA4\x2E', 'LLIL_INTRINSIC([v6],vpminnm_f32,[LLIL_REG.o(v18),LLIL_REG.o(v4)])'),
+ # fminnmp v28.4s, v10.4s, v25.4s FMINNMP_asimdsame_only
+ (b'\x5C\xC5\xB9\x6E', 'LLIL_INTRINSIC([v28],vpminnmq_f32,[LLIL_REG.o(v10),LLIL_REG.o(v25)])'),
+ # fminnmp v20.2d, v31.2d, v16.2d FMINNMP_asimdsame_only
+ (b'\xF4\xC7\xF0\x6E', 'LLIL_INTRINSIC([v20],vpminnmq_f64,[LLIL_REG.o(v31),LLIL_REG.o(v16)])'),
+ # fminnmp v24.4h, v26.4h, v24.4h FMINNMP_asimdsamefp16_only
+ (b'\x58\x07\xD8\x2E', 'LLIL_INTRINSIC([v24],vpminnm_f16,[LLIL_REG.o(v26),LLIL_REG.o(v24)])'),
+ # fminnmp v17.4h, v8.4h, v12.4h FMINNMP_asimdsamefp16_only
+ (b'\x11\x05\xCC\x2E', 'LLIL_INTRINSIC([v17],vpminnm_f16,[LLIL_REG.o(v8),LLIL_REG.o(v12)])'),
+ # fminnmp v0.4h, v13.4h, v22.4h FMINNMP_asimdsamefp16_only
+ (b'\xA0\x05\xD6\x2E', 'LLIL_INTRINSIC([v0],vpminnm_f16,[LLIL_REG.o(v13),LLIL_REG.o(v22)])'),
+ # fminnmp v14.4h, v7.4h, v4.4h FMINNMP_asimdsamefp16_only
+ (b'\xEE\x04\xC4\x2E', 'LLIL_INTRINSIC([v14],vpminnm_f16,[LLIL_REG.o(v7),LLIL_REG.o(v4)])'),
+ # fminnmp h30, v28.2h FMINNMP_asisdpair_only_H
+ (b'\x9E\xCB\xB0\x5E', 'LLIL_INTRINSIC([h30],vminnmv_f16,[LLIL_REG.o(v28)])'),
+ # fminnmp h31, v20.2h FMINNMP_asisdpair_only_H
+ (b'\x9F\xCA\xB0\x5E', 'LLIL_INTRINSIC([h31],vminnmv_f16,[LLIL_REG.o(v20)])'),
+ # fminnmp h28, v24.2h FMINNMP_asisdpair_only_H
+ (b'\x1C\xCB\xB0\x5E', 'LLIL_INTRINSIC([h28],vminnmv_f16,[LLIL_REG.o(v24)])'),
+ # fminnmp h10, v7.2h FMINNMP_asisdpair_only_H
+ (b'\xEA\xC8\xB0\x5E', 'LLIL_INTRINSIC([h10],vminnmv_f16,[LLIL_REG.o(v7)])'),
+ # fminnmp s21, v7.2s FMINNMP_asisdpair_only_SD
+ (b'\xF5\xC8\xB0\x7E', 'LLIL_INTRINSIC([s21],vpminnms_f32,[LLIL_REG.o(v7)])'),
+ # fminnmp d14, v3.2d FMINNMP_asisdpair_only_SD
+ (b'\x6E\xC8\xF0\x7E', 'LLIL_INTRINSIC([d14],vpminnmqd_f64,[LLIL_REG.o(v3)])'),
+ # fminnmp s8, v3.2s FMINNMP_asisdpair_only_SD
+ (b'\x68\xC8\xB0\x7E', 'LLIL_INTRINSIC([s8],vpminnms_f32,[LLIL_REG.o(v3)])'),
+ # fminnmp s8, v0.2s FMINNMP_asisdpair_only_SD
+ (b'\x08\xC8\xB0\x7E', 'LLIL_INTRINSIC([s8],vpminnms_f32,[LLIL_REG.o(v0)])'),
+ # fminnmv h13, v26.8h FMINNMV_asimdall_only_H
+ (b'\x4D\xCB\xB0\x4E', 'LLIL_INTRINSIC([h13],vminnmvq_f16,[LLIL_REG.o(v26)])'),
+ # fminnmv h17, v24.4h FMINNMV_asimdall_only_H
+ (b'\x11\xCB\xB0\x0E', 'LLIL_INTRINSIC([h17],vminnmv_f16,[LLIL_REG.o(v24)])'),
+ # fminnmv h7, v25.8h FMINNMV_asimdall_only_H
+ (b'\x27\xCB\xB0\x4E', 'LLIL_INTRINSIC([h7],vminnmvq_f16,[LLIL_REG.o(v25)])'),
+ # fminnmv h29, v23.4h FMINNMV_asimdall_only_H
+ (b'\xFD\xCA\xB0\x0E', 'LLIL_INTRINSIC([h29],vminnmv_f16,[LLIL_REG.o(v23)])'),
+ # fminnmv s27, v3.4s FMINNMV_asimdall_only_SD
+ (b'\x7B\xC8\xB0\x6E', 'LLIL_INTRINSIC([s27],vminnmvq_f32,[LLIL_REG.o(v3)])'),
+ # fminnmv s28, v30.4s FMINNMV_asimdall_only_SD
+ (b'\xDC\xCB\xB0\x6E', 'LLIL_INTRINSIC([s28],vminnmvq_f32,[LLIL_REG.o(v30)])'),
+ # fminnmv s26, v4.4s FMINNMV_asimdall_only_SD
+ (b'\x9A\xC8\xB0\x6E', 'LLIL_INTRINSIC([s26],vminnmvq_f32,[LLIL_REG.o(v4)])'),
+ # fminnmv s6, v20.4s FMINNMV_asimdall_only_SD
+ (b'\x86\xCA\xB0\x6E', 'LLIL_INTRINSIC([s6],vminnmvq_f32,[LLIL_REG.o(v20)])'),
+ # fminnm d30, d29, d19 FMINNM_D_floatdp2
+ (b'\xBE\x7B\x73\x1E', 'LLIL_INTRINSIC([d30],vminnm_f64,[LLIL_REG.q(d29),LLIL_REG.q(d19)])'),
+ # fminnm d12, d14, d25 FMINNM_D_floatdp2
+ (b'\xCC\x79\x79\x1E', 'LLIL_INTRINSIC([d12],vminnm_f64,[LLIL_REG.q(d14),LLIL_REG.q(d25)])'),
+ # fminnm d12, d16, d26 FMINNM_D_floatdp2
+ (b'\x0C\x7A\x7A\x1E', 'LLIL_INTRINSIC([d12],vminnm_f64,[LLIL_REG.q(d16),LLIL_REG.q(d26)])'),
+ # fminnm d26, d23, d30 FMINNM_D_floatdp2
+ (b'\xFA\x7A\x7E\x1E', 'LLIL_INTRINSIC([d26],vminnm_f64,[LLIL_REG.q(d23),LLIL_REG.q(d30)])'),
+ # fminnm h1, h29, h19 FMINNM_H_floatdp2
+ (b'\xA1\x7B\xF3\x1E', 'LLIL_INTRINSIC([h1],vminnmh_f16,[LLIL_REG.w(h29),LLIL_REG.w(h19)])'),
+ # fminnm h4, h3, h19 FMINNM_H_floatdp2
+ (b'\x64\x78\xF3\x1E', 'LLIL_INTRINSIC([h4],vminnmh_f16,[LLIL_REG.w(h3),LLIL_REG.w(h19)])'),
+ # fminnm h22, h17, h19 FMINNM_H_floatdp2
+ (b'\x36\x7A\xF3\x1E', 'LLIL_INTRINSIC([h22],vminnmh_f16,[LLIL_REG.w(h17),LLIL_REG.w(h19)])'),
+ # fminnm h21, h8, h25 FMINNM_H_floatdp2
+ (b'\x15\x79\xF9\x1E', 'LLIL_INTRINSIC([h21],vminnmh_f16,[LLIL_REG.w(h8),LLIL_REG.w(h25)])'),
+ # fminnm s14, s27, s8 FMINNM_S_floatdp2
+ (b'\x6E\x7B\x28\x1E', 'LLIL_INTRINSIC([s14],vminnm_f32,[LLIL_REG.d(s27),LLIL_REG.d(s8)])'),
+ # fminnm s25, s16, s23 FMINNM_S_floatdp2
+ (b'\x19\x7A\x37\x1E', 'LLIL_INTRINSIC([s25],vminnm_f32,[LLIL_REG.d(s16),LLIL_REG.d(s23)])'),
+ # fminnm s31, s11, s18 FMINNM_S_floatdp2
+ (b'\x7F\x79\x32\x1E', 'LLIL_INTRINSIC([s31],vminnm_f32,[LLIL_REG.d(s11),LLIL_REG.d(s18)])'),
+ # fminnm s22, s13, s28 FMINNM_S_floatdp2
+ (b'\xB6\x79\x3C\x1E', 'LLIL_INTRINSIC([s22],vminnm_f32,[LLIL_REG.d(s13),LLIL_REG.d(s28)])'),
+ # fminnm v22.2s, v11.2s, v21.2s FMINNM_asimdsame_only
+ (b'\x76\xC5\xB5\x0E', 'LLIL_INTRINSIC([v22],vminnm_f32,[LLIL_REG.o(v11),LLIL_REG.o(v21)])'),
+ # fminnm v3.2s, v13.2s, v3.2s FMINNM_asimdsame_only
+ (b'\xA3\xC5\xA3\x0E', 'LLIL_INTRINSIC([v3],vminnm_f32,[LLIL_REG.o(v13),LLIL_REG.o(v3)])'),
+ # fminnm v11.2s, v27.2s, v10.2s FMINNM_asimdsame_only
+ (b'\x6B\xC7\xAA\x0E', 'LLIL_INTRINSIC([v11],vminnm_f32,[LLIL_REG.o(v27),LLIL_REG.o(v10)])'),
+ # fminnm v12.2s, v29.2s, v14.2s FMINNM_asimdsame_only
+ (b'\xAC\xC7\xAE\x0E', 'LLIL_INTRINSIC([v12],vminnm_f32,[LLIL_REG.o(v29),LLIL_REG.o(v14)])'),
+ # fminnm v15.4h, v30.4h, v18.4h FMINNM_asimdsamefp16_only
+ (b'\xCF\x07\xD2\x0E', 'LLIL_INTRINSIC([v15],vminnm_f16,[LLIL_REG.o(v30),LLIL_REG.o(v18)])'),
+ # fminnm v21.4h, v3.4h, v9.4h FMINNM_asimdsamefp16_only
+ (b'\x75\x04\xC9\x0E', 'LLIL_INTRINSIC([v21],vminnm_f16,[LLIL_REG.o(v3),LLIL_REG.o(v9)])'),
+ # fminnm v11.8h, v2.8h, v15.8h FMINNM_asimdsamefp16_only
+ (b'\x4B\x04\xCF\x4E', 'LLIL_INTRINSIC([v11],vminnmq_f16,[LLIL_REG.o(v2),LLIL_REG.o(v15)])'),
+ # fminnm v31.4h, v16.4h, v6.4h FMINNM_asimdsamefp16_only
+ (b'\x1F\x06\xC6\x0E', 'LLIL_INTRINSIC([v31],vminnm_f16,[LLIL_REG.o(v16),LLIL_REG.o(v6)])'),
+ # fminp v12.2s, v2.2s, v0.2s FMINP_asimdsame_only
+ (b'\x4C\xF4\xA0\x2E', 'LLIL_INTRINSIC([v12],vpmin_f32,[LLIL_REG.o(v2),LLIL_REG.o(v0)])'),
+ # fminp v10.2d, v13.2d, v2.2d FMINP_asimdsame_only
+ (b'\xAA\xF5\xE2\x6E', 'LLIL_INTRINSIC([v10],vpminq_f64,[LLIL_REG.o(v13),LLIL_REG.o(v2)])'),
+ # fminp v3.2d, v21.2d, v21.2d FMINP_asimdsame_only
+ (b'\xA3\xF6\xF5\x6E', 'LLIL_INTRINSIC([v3],vpminq_f64,[LLIL_REG.o(v21),LLIL_REG.o(v21)])'),
+ # fminp v28.4s, v7.4s, v7.4s FMINP_asimdsame_only
+ (b'\xFC\xF4\xA7\x6E', 'LLIL_INTRINSIC([v28],vpminq_f32,[LLIL_REG.o(v7),LLIL_REG.o(v7)])'),
+ # fminp v19.4h, v8.4h, v22.4h FMINP_asimdsamefp16_only
+ (b'\x13\x35\xD6\x2E', 'LLIL_INTRINSIC([v19],vpmin_f16,[LLIL_REG.o(v8),LLIL_REG.o(v22)])'),
+ # fminp v5.8h, v24.8h, v4.8h FMINP_asimdsamefp16_only
+ (b'\x05\x37\xC4\x6E', 'LLIL_INTRINSIC([v5],vpminq_f16,[LLIL_REG.o(v24),LLIL_REG.o(v4)])'),
+ # fminp v4.8h, v28.8h, v6.8h FMINP_asimdsamefp16_only
+ (b'\x84\x37\xC6\x6E', 'LLIL_INTRINSIC([v4],vpminq_f16,[LLIL_REG.o(v28),LLIL_REG.o(v6)])'),
+ # fminp v12.4h, v20.4h, v3.4h FMINP_asimdsamefp16_only
+ (b'\x8C\x36\xC3\x2E', 'LLIL_INTRINSIC([v12],vpmin_f16,[LLIL_REG.o(v20),LLIL_REG.o(v3)])'),
+ # fminp h7, v13.2h FMINP_asisdpair_only_H
+ (b'\xA7\xF9\xB0\x5E', 'LLIL_INTRINSIC([h7],vminv_f16,[LLIL_REG.o(v13)])'),
+ # fminp h26, v19.2h FMINP_asisdpair_only_H
+ (b'\x7A\xFA\xB0\x5E', 'LLIL_INTRINSIC([h26],vminv_f16,[LLIL_REG.o(v19)])'),
+ # fminp h21, v3.2h FMINP_asisdpair_only_H
+ (b'\x75\xF8\xB0\x5E', 'LLIL_INTRINSIC([h21],vminv_f16,[LLIL_REG.o(v3)])'),
+ # fminp h2, v30.2h FMINP_asisdpair_only_H
+ (b'\xC2\xFB\xB0\x5E', 'LLIL_INTRINSIC([h2],vminv_f16,[LLIL_REG.o(v30)])'),
+ # fminp s18, v30.2s FMINP_asisdpair_only_SD
+ (b'\xD2\xFB\xB0\x7E', 'LLIL_INTRINSIC([s18],vpmins_f32,[LLIL_REG.o(v30)])'),
+ # fminp s29, v11.2s FMINP_asisdpair_only_SD
+ (b'\x7D\xF9\xB0\x7E', 'LLIL_INTRINSIC([s29],vpmins_f32,[LLIL_REG.o(v11)])'),
+ # fminp d6, v9.2d FMINP_asisdpair_only_SD
+ (b'\x26\xF9\xF0\x7E', 'LLIL_INTRINSIC([d6],vpminqd_f64,[LLIL_REG.o(v9)])'),
+ # fminp d14, v29.2d FMINP_asisdpair_only_SD
+ (b'\xAE\xFB\xF0\x7E', 'LLIL_INTRINSIC([d14],vpminqd_f64,[LLIL_REG.o(v29)])'),
+ # fminv h3, v24.8h FMINV_asimdall_only_H
+ (b'\x03\xFB\xB0\x4E', 'LLIL_INTRINSIC([h3],vminvq_f16,[LLIL_REG.o(v24)])'),
+ # fminv h1, v19.8h FMINV_asimdall_only_H
+ (b'\x61\xFA\xB0\x4E', 'LLIL_INTRINSIC([h1],vminvq_f16,[LLIL_REG.o(v19)])'),
+ # fminv h4, v7.8h FMINV_asimdall_only_H
+ (b'\xE4\xF8\xB0\x4E', 'LLIL_INTRINSIC([h4],vminvq_f16,[LLIL_REG.o(v7)])'),
+ # fminv h16, v18.4h FMINV_asimdall_only_H
+ (b'\x50\xFA\xB0\x0E', 'LLIL_INTRINSIC([h16],vminv_f16,[LLIL_REG.o(v18)])'),
+ # fminv s13, v19.4s FMINV_asimdall_only_SD
+ (b'\x6D\xFA\xB0\x6E', 'LLIL_INTRINSIC([s13],vminvq_f32,[LLIL_REG.o(v19)])'),
+ # fminv s28, v7.4s FMINV_asimdall_only_SD
+ (b'\xFC\xF8\xB0\x6E', 'LLIL_INTRINSIC([s28],vminvq_f32,[LLIL_REG.o(v7)])'),
+ # fminv s31, v9.4s FMINV_asimdall_only_SD
+ (b'\x3F\xF9\xB0\x6E', 'LLIL_INTRINSIC([s31],vminvq_f32,[LLIL_REG.o(v9)])'),
+ # fminv s18, v6.4s FMINV_asimdall_only_SD
+ (b'\xD2\xF8\xB0\x6E', 'LLIL_INTRINSIC([s18],vminvq_f32,[LLIL_REG.o(v6)])'),
+ # fmin d24, d28, d27 FMIN_D_floatdp2
+ (b'\x98\x5B\x7B\x1E', 'LLIL_INTRINSIC([d24],vmin_f64,[LLIL_REG.q(d28),LLIL_REG.q(d27)])'),
+ # fmin d15, d0, d18 FMIN_D_floatdp2
+ (b'\x0F\x58\x72\x1E', 'LLIL_INTRINSIC([d15],vmin_f64,[LLIL_REG.q(d0),LLIL_REG.q(d18)])'),
+ # fmin d16, d9, d21 FMIN_D_floatdp2
+ (b'\x30\x59\x75\x1E', 'LLIL_INTRINSIC([d16],vmin_f64,[LLIL_REG.q(d9),LLIL_REG.q(d21)])'),
+ # fmin d13, d18, d17 FMIN_D_floatdp2
+ (b'\x4D\x5A\x71\x1E', 'LLIL_INTRINSIC([d13],vmin_f64,[LLIL_REG.q(d18),LLIL_REG.q(d17)])'),
+ # fmin h9, h10, h7 FMIN_H_floatdp2
+ (b'\x49\x59\xE7\x1E', 'LLIL_INTRINSIC([h9],vminh_f16,[LLIL_REG.w(h10),LLIL_REG.w(h7)])'),
+ # fmin h20, h16, h18 FMIN_H_floatdp2
+ (b'\x14\x5A\xF2\x1E', 'LLIL_INTRINSIC([h20],vminh_f16,[LLIL_REG.w(h16),LLIL_REG.w(h18)])'),
+ # fmin h15, h26, h6 FMIN_H_floatdp2
+ (b'\x4F\x5B\xE6\x1E', 'LLIL_INTRINSIC([h15],vminh_f16,[LLIL_REG.w(h26),LLIL_REG.w(h6)])'),
+ # fmin h27, h4, h14 FMIN_H_floatdp2
+ (b'\x9B\x58\xEE\x1E', 'LLIL_INTRINSIC([h27],vminh_f16,[LLIL_REG.w(h4),LLIL_REG.w(h14)])'),
+ # fmin s6, s7, s30 FMIN_S_floatdp2
+ (b'\xE6\x58\x3E\x1E', 'LLIL_INTRINSIC([s6],vmin_f32,[LLIL_REG.d(s7),LLIL_REG.d(s30)])'),
+ # fmin s25, s27, s8 FMIN_S_floatdp2
+ (b'\x79\x5B\x28\x1E', 'LLIL_INTRINSIC([s25],vmin_f32,[LLIL_REG.d(s27),LLIL_REG.d(s8)])'),
+ # fmin s9, s25, s16 FMIN_S_floatdp2
+ (b'\x29\x5B\x30\x1E', 'LLIL_INTRINSIC([s9],vmin_f32,[LLIL_REG.d(s25),LLIL_REG.d(s16)])'),
+ # fmin s12, s23, s28 FMIN_S_floatdp2
+ (b'\xEC\x5A\x3C\x1E', 'LLIL_INTRINSIC([s12],vmin_f32,[LLIL_REG.d(s23),LLIL_REG.d(s28)])'),
+ # fmin v7.2s, v19.2s, v4.2s FMIN_asimdsame_only
+ (b'\x67\xF6\xA4\x0E', 'LLIL_INTRINSIC([v7],vmin_f32,[LLIL_REG.o(v19),LLIL_REG.o(v4)])'),
+ # fmin v9.2s, v17.2s, v0.2s FMIN_asimdsame_only
+ (b'\x29\xF6\xA0\x0E', 'LLIL_INTRINSIC([v9],vmin_f32,[LLIL_REG.o(v17),LLIL_REG.o(v0)])'),
+ # fmin v21.2d, v12.2d, v26.2d FMIN_asimdsame_only
+ (b'\x95\xF5\xFA\x4E', 'LLIL_INTRINSIC([v21],vminq_f64,[LLIL_REG.o(v12),LLIL_REG.o(v26)])'),
+ # fmin v26.4s, v31.4s, v31.4s FMIN_asimdsame_only
+ (b'\xFA\xF7\xBF\x4E', 'LLIL_INTRINSIC([v26],vminq_f32,[LLIL_REG.o(v31),LLIL_REG.o(v31)])'),
+ # fmin v30.4h, v3.4h, v5.4h FMIN_asimdsamefp16_only
+ (b'\x7E\x34\xC5\x0E', 'LLIL_INTRINSIC([v30],vmin_f16,[LLIL_REG.o(v3),LLIL_REG.o(v5)])'),
+ # fmin v6.4h, v0.4h, v19.4h FMIN_asimdsamefp16_only
+ (b'\x06\x34\xD3\x0E', 'LLIL_INTRINSIC([v6],vmin_f16,[LLIL_REG.o(v0),LLIL_REG.o(v19)])'),
+ # fmin v28.4h, v3.4h, v30.4h FMIN_asimdsamefp16_only
+ (b'\x7C\x34\xDE\x0E', 'LLIL_INTRINSIC([v28],vmin_f16,[LLIL_REG.o(v3),LLIL_REG.o(v30)])'),
+ # fmin v24.8h, v3.8h, v30.8h FMIN_asimdsamefp16_only
+ (b'\x78\x34\xDE\x4E', 'LLIL_INTRINSIC([v24],vminq_f16,[LLIL_REG.o(v3),LLIL_REG.o(v30)])'),
+ # fneg d25, d7 FNEG_D_floatdp1
+ (b'\xF9\x40\x61\x1E', 'LLIL_SET_REG.q(d25,LLIL_FNEG.q(LLIL_REG.q(d7)))'),
+ # fneg d28, d17 FNEG_D_floatdp1
+ (b'\x3C\x42\x61\x1E', 'LLIL_SET_REG.q(d28,LLIL_FNEG.q(LLIL_REG.q(d17)))'),
+ # fneg d5, d16 FNEG_D_floatdp1
+ (b'\x05\x42\x61\x1E', 'LLIL_SET_REG.q(d5,LLIL_FNEG.q(LLIL_REG.q(d16)))'),
+ # fneg d23, d0 FNEG_D_floatdp1
+ (b'\x17\x40\x61\x1E', 'LLIL_SET_REG.q(d23,LLIL_FNEG.q(LLIL_REG.q(d0)))'),
+ # fneg h16, h22 FNEG_H_floatdp1
+ (b'\xD0\x42\xE1\x1E', 'LLIL_SET_REG.w(h16,LLIL_FNEG.w(LLIL_REG.w(h22)))'),
+ # fneg h20, h11 FNEG_H_floatdp1
+ (b'\x74\x41\xE1\x1E', 'LLIL_SET_REG.w(h20,LLIL_FNEG.w(LLIL_REG.w(h11)))'),
+ # fneg h23, h1 FNEG_H_floatdp1
+ (b'\x37\x40\xE1\x1E', 'LLIL_SET_REG.w(h23,LLIL_FNEG.w(LLIL_REG.w(h1)))'),
+ # fneg h21, h1 FNEG_H_floatdp1
+ (b'\x35\x40\xE1\x1E', 'LLIL_SET_REG.w(h21,LLIL_FNEG.w(LLIL_REG.w(h1)))'),
+ # fneg s21, s22 FNEG_S_floatdp1
+ (b'\xD5\x42\x21\x1E', 'LLIL_SET_REG.d(s21,LLIL_FNEG.d(LLIL_REG.d(s22)))'),
+ # fneg s10, s30 FNEG_S_floatdp1
+ (b'\xCA\x43\x21\x1E', 'LLIL_SET_REG.d(s10,LLIL_FNEG.d(LLIL_REG.d(s30)))'),
+ # fneg s6, s29 FNEG_S_floatdp1
+ (b'\xA6\x43\x21\x1E', 'LLIL_SET_REG.d(s6,LLIL_FNEG.d(LLIL_REG.d(s29)))'),
+ # fneg s0, s29 FNEG_S_floatdp1
+ (b'\xA0\x43\x21\x1E', 'LLIL_SET_REG.d(s0,LLIL_FNEG.d(LLIL_REG.d(s29)))'),
+ # fneg v20.2s, v13.2s FNEG_asimdmisc_R
+ (b'\xB4\xF9\xA0\x2E', 'LLIL_INTRINSIC([v20],vneg_f32,[LLIL_REG.o(v13)])'),
+ # fneg v19.4s, v4.4s FNEG_asimdmisc_R
+ (b'\x93\xF8\xA0\x6E', 'LLIL_INTRINSIC([v19],vnegq_f32,[LLIL_REG.o(v4)])'),
+ # fneg v10.4s, v25.4s FNEG_asimdmisc_R
+ (b'\x2A\xFB\xA0\x6E', 'LLIL_INTRINSIC([v10],vnegq_f32,[LLIL_REG.o(v25)])'),
+ # fneg v11.2s, v14.2s FNEG_asimdmisc_R
+ (b'\xCB\xF9\xA0\x2E', 'LLIL_INTRINSIC([v11],vneg_f32,[LLIL_REG.o(v14)])'),
+ # fneg v12.4h, v24.4h FNEG_asimdmiscfp16_R
+ (b'\x0C\xFB\xF8\x2E', 'LLIL_INTRINSIC([v12],vneg_f16,[LLIL_REG.o(v24)])'),
+ # fneg v2.8h, v29.8h FNEG_asimdmiscfp16_R
+ (b'\xA2\xFB\xF8\x6E', 'LLIL_INTRINSIC([v2],vnegq_f16,[LLIL_REG.o(v29)])'),
+ # fneg v23.8h, v19.8h FNEG_asimdmiscfp16_R
+ (b'\x77\xFA\xF8\x6E', 'LLIL_INTRINSIC([v23],vnegq_f16,[LLIL_REG.o(v19)])'),
+ # fneg v27.4h, v30.4h FNEG_asimdmiscfp16_R
+ (b'\xDB\xFB\xF8\x2E', 'LLIL_INTRINSIC([v27],vneg_f16,[LLIL_REG.o(v30)])'),
+ # fnmul d27, d21, d11 FNMUL_D_floatdp2
+ (b'\xBB\x8A\x6B\x1E', 'LLIL_SET_REG.q(d27,LLIL_FNEG.q(LLIL_FMUL.q(LLIL_REG.q(d21),LLIL_REG.q(d11))))'),
+ # fnmul d4, d14, d24 FNMUL_D_floatdp2
+ (b'\xC4\x89\x78\x1E', 'LLIL_SET_REG.q(d4,LLIL_FNEG.q(LLIL_FMUL.q(LLIL_REG.q(d14),LLIL_REG.q(d24))))'),
+ # fnmul d4, d19, d20 FNMUL_D_floatdp2
+ (b'\x64\x8A\x74\x1E', 'LLIL_SET_REG.q(d4,LLIL_FNEG.q(LLIL_FMUL.q(LLIL_REG.q(d19),LLIL_REG.q(d20))))'),
+ # fnmul d24, d23, d6 FNMUL_D_floatdp2
+ (b'\xF8\x8A\x66\x1E', 'LLIL_SET_REG.q(d24,LLIL_FNEG.q(LLIL_FMUL.q(LLIL_REG.q(d23),LLIL_REG.q(d6))))'),
+ # fnmul h31, h12, h2 FNMUL_H_floatdp2
+ (b'\x9F\x89\xE2\x1E', 'LLIL_SET_REG.w(h31,LLIL_FNEG.w(LLIL_FMUL.w(LLIL_REG.w(h12),LLIL_REG.w(h2))))'),
+ # fnmul h26, h27, h17 FNMUL_H_floatdp2
+ (b'\x7A\x8B\xF1\x1E', 'LLIL_SET_REG.w(h26,LLIL_FNEG.w(LLIL_FMUL.w(LLIL_REG.w(h27),LLIL_REG.w(h17))))'),
+ # fnmul h15, h11, h1 FNMUL_H_floatdp2
+ (b'\x6F\x89\xE1\x1E', 'LLIL_SET_REG.w(h15,LLIL_FNEG.w(LLIL_FMUL.w(LLIL_REG.w(h11),LLIL_REG.w(h1))))'),
+ # fnmul h17, h5, h2 FNMUL_H_floatdp2
+ (b'\xB1\x88\xE2\x1E', 'LLIL_SET_REG.w(h17,LLIL_FNEG.w(LLIL_FMUL.w(LLIL_REG.w(h5),LLIL_REG.w(h2))))'),
+ # fnmul s24, s29, s16 FNMUL_S_floatdp2
+ (b'\xB8\x8B\x30\x1E', 'LLIL_SET_REG.d(s24,LLIL_FNEG.d(LLIL_FMUL.d(LLIL_REG.d(s29),LLIL_REG.d(s16))))'),
+ # fnmul s19, s22, s28 FNMUL_S_floatdp2
+ (b'\xD3\x8A\x3C\x1E', 'LLIL_SET_REG.d(s19,LLIL_FNEG.d(LLIL_FMUL.d(LLIL_REG.d(s22),LLIL_REG.d(s28))))'),
+ # fnmul s4, s0, s30 FNMUL_S_floatdp2
+ (b'\x04\x88\x3E\x1E', 'LLIL_SET_REG.d(s4,LLIL_FNEG.d(LLIL_FMUL.d(LLIL_REG.d(s0),LLIL_REG.d(s30))))'),
+ # fnmul s10, s29, s26 FNMUL_S_floatdp2
+ (b'\xAA\x8B\x3A\x1E', 'LLIL_SET_REG.d(s10,LLIL_FNEG.d(LLIL_FMUL.d(LLIL_REG.d(s29),LLIL_REG.d(s26))))'),
]
tests_fcvt = [
- # fcvt d9, h29
- (b'\xA9\xC3\xE2\x1E', 'LLIL_SET_REG.q(d9,LLIL_FLOAT_CONV.q(LLIL_REG.w(h29)))'),
- # fcvt d11, h29
- (b'\xAB\xC3\xE2\x1E', 'LLIL_SET_REG.q(d11,LLIL_FLOAT_CONV.q(LLIL_REG.w(h29)))'),
- # fcvt d27, s12
- (b'\x9B\xC1\x22\x1E', 'LLIL_SET_REG.q(d27,LLIL_FLOAT_CONV.q(LLIL_REG.d(s12)))'),
- # fcvt d18, s7
- (b'\xF2\xC0\x22\x1E', 'LLIL_SET_REG.q(d18,LLIL_FLOAT_CONV.q(LLIL_REG.d(s7)))'),
- # fcvt h11, d15
- (b'\xEB\xC1\x63\x1E', 'LLIL_SET_REG.w(h11,LLIL_FLOAT_CONV.w(LLIL_REG.q(d15)))'),
- # fcvt h4, d8
- (b'\x04\xC1\x63\x1E', 'LLIL_SET_REG.w(h4,LLIL_FLOAT_CONV.w(LLIL_REG.q(d8)))'),
- # fcvt h14, s1
- (b'\x2E\xC0\x23\x1E', 'LLIL_SET_REG.w(h14,LLIL_FLOAT_CONV.w(LLIL_REG.d(s1)))'),
- # fcvt h7, s26
- (b'\x47\xC3\x23\x1E', 'LLIL_SET_REG.w(h7,LLIL_FLOAT_CONV.w(LLIL_REG.d(s26)))'),
- # fcvt s28, d16
- (b'\x1C\x42\x62\x1E', 'LLIL_SET_REG.d(s28,LLIL_FLOAT_CONV.d(LLIL_REG.q(d16)))'),
- # fcvt s28, d13
- (b'\xBC\x41\x62\x1E', 'LLIL_SET_REG.d(s28,LLIL_FLOAT_CONV.d(LLIL_REG.q(d13)))'),
- # fcvt s15, h17
- (b'\x2F\x42\xE2\x1E', 'LLIL_SET_REG.d(s15,LLIL_FLOAT_CONV.d(LLIL_REG.w(h17)))'),
- # fcvt s5, h14
- (b'\xC5\x41\xE2\x1E', 'LLIL_SET_REG.d(s5,LLIL_FLOAT_CONV.d(LLIL_REG.w(h14)))'),
- # fcvtzs x8, d0
- (b'\x08\x00\x78\x9E', 'LLIL_INTRINSIC([x8],vcvtd_s64_f64,[LLIL_REG.q(d0)])'),
- # fcvtzs x15, d0
- (b'\x0F\x00\x78\x9E', 'LLIL_INTRINSIC([x15],vcvtd_s64_f64,[LLIL_REG.q(d0)])'),
- # fcvtzs x9, d1
- (b'\x29\x00\x78\x9E', 'LLIL_INTRINSIC([x9],vcvtd_s64_f64,[LLIL_REG.q(d1)])'),
- # fcvtzu x10, d0
- (b'\x0A\x00\x79\x9E', 'LLIL_INTRINSIC([x10],vcvtd_u64_f64,[LLIL_REG.q(d0)])'),
- # fcvtzu X3, D0, #3
- (b'\x03\xF4\x59\x9E', 'LLIL_INTRINSIC([x3],vcvtd_n_u64_f64,[LLIL_REG.q(d0),LLIL_CONST(3)])'),
- # fcvtzu v23.4s, v22.4s
- (b'\xd7\xba\xa1\x6e', 'LLIL_INTRINSIC([v23],vcvtq_u32_f32,[LLIL_REG.o(v22)])'),
- # fcvtzu v24.2s, v20.2s
- (b'\x98\xba\xa1\x2e', 'LLIL_INTRINSIC([v24],vcvt_u32_f32,[LLIL_REG.o(v20)])'),
- # fcvtzu v9.2d, v18.2d
- (b'\x49\xba\xe1\x6e', 'LLIL_INTRINSIC([v9],vcvtq_u64_f64,[LLIL_REG.o(v18)])'),
- # fcvtzu v16.4h, v1.4h
- (b'\x30\xB8\xF9\x2E', 'LLIL_INTRINSIC([v16],vcvt_u16_f16,[LLIL_REG.o(v1)])'),
- # fcvtzu v28.8h, v5.8h
- (b'\xBC\xB8\xF9\x6E', 'LLIL_INTRINSIC([v28],vcvtq_u16_f16,[LLIL_REG.o(v5)])'),
- # fcvtzu v3.2d, v25.2d, #0x2f
- (b'\x23\xff\x51\x6f', 'LLIL_INTRINSIC([v3],vcvtq_n_u64_f64,[LLIL_REG.o(v25),LLIL_CONST(47)])'),
- # fcvtzu v16.4s, v14.4s, #0x15
- (b'\xd0\xfd\x2b\x6f', 'LLIL_INTRINSIC([v16],vcvtq_n_u32_f32,[LLIL_REG.o(v14),LLIL_CONST(21)])'),
- # fcvtzu v11.2s, v4.2s, #0xb
- (b'\x8b\xfc\x35\x2f', 'LLIL_INTRINSIC([v11],vcvt_n_u32_f32,[LLIL_REG.o(v4),LLIL_CONST(11)])'),
- # fcvtzu v11.4h, v20.4h, #2
- (b'\x8B\xFE\x1E\x2F', 'LLIL_INTRINSIC([v11],vcvt_n_u16_f16,[LLIL_REG.o(v20),LLIL_CONST(2)])'),
- # fcvtzu v11.8h, v4.8h, #0xb
- (b'\x8B\xFC\x15\x6F', 'LLIL_INTRINSIC([v11],vcvtq_n_u16_f16,[LLIL_REG.o(v4),LLIL_CONST(11)])'),
- # fcvtzu w4, s18
- (b'\x44\x02\x39\x1E', 'LLIL_INTRINSIC([w4],vcvts_u32_f32,[LLIL_REG.d(s18)])')
+ # fcvtas w14, d12 FCVTAS_32D_float2int
+ (b'\x8E\x01\x64\x1E', 'LLIL_INTRINSIC([w14],vcvtad_s32_f64,[LLIL_REG.q(d12)])'),
+ # fcvtas w0, d28 FCVTAS_32D_float2int
+ (b'\x80\x03\x64\x1E', 'LLIL_INTRINSIC([w0],vcvtad_s32_f64,[LLIL_REG.q(d28)])'),
+ # fcvtas wzr, s20 FCVTAS_32S_float2int
+ (b'\x9F\x02\x24\x1E', 'LLIL_INTRINSIC([wzr],vcvtas_s32_f32,[LLIL_REG.d(s20)])'),
+ # fcvtas w17, s19 FCVTAS_32S_float2int
+ (b'\x71\x02\x24\x1E', 'LLIL_INTRINSIC([w17],vcvtas_s32_f32,[LLIL_REG.d(s19)])'),
+ # fcvtas x27, d9 FCVTAS_64D_float2int
+ (b'\x3B\x01\x64\x9E', 'LLIL_INTRINSIC([x27],vcvtad_s64_f64,[LLIL_REG.q(d9)])'),
+ # fcvtas x8, d15 FCVTAS_64D_float2int
+ (b'\xE8\x01\x64\x9E', 'LLIL_INTRINSIC([x8],vcvtad_s64_f64,[LLIL_REG.q(d15)])'),
+ # fcvtas x30, s7 FCVTAS_64S_float2int
+ (b'\xFE\x00\x24\x9E', 'LLIL_INTRINSIC([x30],vcvtad_s64_f64,[LLIL_REG.d(s7)])'),
+ # fcvtas x15, s25 FCVTAS_64S_float2int
+ (b'\x2F\x03\x24\x9E', 'LLIL_INTRINSIC([x15],vcvtad_s64_f64,[LLIL_REG.d(s25)])'),
+ # fcvtas v11.2s, v9.2s FCVTAS_asimdmisc_R
+ (b'\x2B\xC9\x21\x0E', 'LLIL_INTRINSIC([v11],vcvta_s32_f32,[LLIL_REG.o(v9)])'),
+ # fcvtas v1.4s, v28.4s FCVTAS_asimdmisc_R
+ (b'\x81\xCB\x21\x4E', 'LLIL_INTRINSIC([v1],vcvtaq_s32_f32,[LLIL_REG.o(v28)])'),
+ # fcvtas d26, d14 FCVTAS_asisdmisc_R
+ (b'\xDA\xC9\x61\x5E', 'LLIL_INTRINSIC([d26],vcvtad_s64_f64,[LLIL_REG.q(d14)])'),
+ # fcvtas s11, s2 FCVTAS_asisdmisc_R
+ (b'\x4B\xC8\x21\x5E', 'LLIL_INTRINSIC([s11],vcvtas_s32_f32,[LLIL_REG.d(s2)])'),
+ # fcvtau w14, d7 FCVTAU_32D_float2int
+ (b'\xEE\x00\x65\x1E', 'LLIL_INTRINSIC([w14],vcvtad_u32_f64,[LLIL_REG.q(d7)])'),
+ # fcvtau w26, d6 FCVTAU_32D_float2int
+ (b'\xDA\x00\x65\x1E', 'LLIL_INTRINSIC([w26],vcvtad_u32_f64,[LLIL_REG.q(d6)])'),
+ # fcvtau w15, s28 FCVTAU_32S_float2int
+ (b'\x8F\x03\x25\x1E', 'LLIL_INTRINSIC([w15],vcvtas_u32_f32,[LLIL_REG.d(s28)])'),
+ # fcvtau w10, s0 FCVTAU_32S_float2int
+ (b'\x0A\x00\x25\x1E', 'LLIL_INTRINSIC([w10],vcvtas_u32_f32,[LLIL_REG.d(s0)])'),
+ # fcvtau x15, d28 FCVTAU_64D_float2int
+ (b'\x8F\x03\x65\x9E', 'LLIL_INTRINSIC([x15],vcvtad_u64_f64,[LLIL_REG.q(d28)])'),
+ # fcvtau x8, d0 FCVTAU_64D_float2int
+ (b'\x08\x00\x65\x9E', 'LLIL_INTRINSIC([x8],vcvtad_u64_f64,[LLIL_REG.q(d0)])'),
+ # fcvtau x23, s20 FCVTAU_64S_float2int
+ (b'\x97\x02\x25\x9E', 'LLIL_INTRINSIC([x23],vcvtad_u64_f64,[LLIL_REG.d(s20)])'),
+ # fcvtau x24, s4 FCVTAU_64S_float2int
+ (b'\x98\x00\x25\x9E', 'LLIL_INTRINSIC([x24],vcvtad_u64_f64,[LLIL_REG.d(s4)])'),
+ # fcvtau v26.2s, v16.2s FCVTAU_asimdmisc_R
+ (b'\x1A\xCA\x21\x2E', 'LLIL_INTRINSIC([v26],vcvta_u32_f32,[LLIL_REG.o(v16)])'),
+ # fcvtau v8.4s, v31.4s FCVTAU_asimdmisc_R
+ (b'\xE8\xCB\x21\x6E', 'LLIL_INTRINSIC([v8],vcvtaq_u32_f32,[LLIL_REG.o(v31)])'),
+ # fcvtau d29, d30 FCVTAU_asisdmisc_R
+ (b'\xDD\xCB\x61\x7E', 'LLIL_INTRINSIC([d29],vcvtad_u64_f64,[LLIL_REG.q(d30)])'),
+ # fcvtau s0, s4 FCVTAU_asisdmisc_R
+ (b'\x80\xC8\x21\x7E', 'LLIL_INTRINSIC([s0],vcvtas_u32_f32,[LLIL_REG.d(s4)])'),
+ # fcvtl v30.4s, v0.4h FCVTL_asimdmisc_L
+ (b'\x1E\x78\x21\x0E', 'LLIL_INTRINSIC([v30],vcvt_f32_f16,[LLIL_REG.o(v0)])'),
+ # fcvtl2 v25.4s, v24.8h FCVTL_asimdmisc_L
+ (b'\x19\x7B\x21\x4E', 'LLIL_INTRINSIC([v25],vcvt_high_f32_f16,[LLIL_REG.o(v24)])'),
+ # fcvtms w1, d17 FCVTMS_32D_float2int
+ (b'\x21\x02\x70\x1E', 'LLIL_INTRINSIC([w1],vcvtmd_s32_f64,[LLIL_REG.q(d17)])'),
+ # fcvtms w7, d7 FCVTMS_32D_float2int
+ (b'\xE7\x00\x70\x1E', 'LLIL_INTRINSIC([w7],vcvtmd_s32_f64,[LLIL_REG.q(d7)])'),
+ # fcvtms w19, s28 FCVTMS_32S_float2int
+ (b'\x93\x03\x30\x1E', 'LLIL_INTRINSIC([w19],vcvtms_s32_f32,[LLIL_REG.d(s28)])'),
+ # fcvtms w16, s26 FCVTMS_32S_float2int
+ (b'\x50\x03\x30\x1E', 'LLIL_INTRINSIC([w16],vcvtms_s32_f32,[LLIL_REG.d(s26)])'),
+ # fcvtms x22, d30 FCVTMS_64D_float2int
+ (b'\xD6\x03\x70\x9E', 'LLIL_INTRINSIC([x22],vcvtmd_s64_f64,[LLIL_REG.q(d30)])'),
+ # fcvtms x22, d22 FCVTMS_64D_float2int
+ (b'\xD6\x02\x70\x9E', 'LLIL_INTRINSIC([x22],vcvtmd_s64_f64,[LLIL_REG.q(d22)])'),
+ # fcvtms x13, s3 FCVTMS_64S_float2int
+ (b'\x6D\x00\x30\x9E', 'LLIL_INTRINSIC([x13],vcvtmd_s64_f64,[LLIL_REG.d(s3)])'),
+ # fcvtms x30, s13 FCVTMS_64S_float2int
+ (b'\xBE\x01\x30\x9E', 'LLIL_INTRINSIC([x30],vcvtmd_s64_f64,[LLIL_REG.d(s13)])'),
+ # fcvtms v31.4s, v28.4s FCVTMS_asimdmisc_R
+ (b'\x9F\xBB\x21\x4E', 'LLIL_INTRINSIC([v31],vcvtmq_s32_f32,[LLIL_REG.o(v28)])'),
+ # fcvtms v31.2s, v12.2s FCVTMS_asimdmisc_R
+ (b'\x9F\xB9\x21\x0E', 'LLIL_INTRINSIC([v31],vcvtm_s32_f32,[LLIL_REG.o(v12)])'),
+ # fcvtms d1, d28 FCVTMS_asisdmisc_R
+ (b'\x81\xBB\x61\x5E', 'LLIL_INTRINSIC([d1],vcvtmd_s64_f64,[LLIL_REG.q(d28)])'),
+ # fcvtms s27, s15 FCVTMS_asisdmisc_R
+ (b'\xFB\xB9\x21\x5E', 'LLIL_INTRINSIC([s27],vcvtms_s32_f32,[LLIL_REG.d(s15)])'),
+ # fcvtmu w1, d3 FCVTMU_32D_float2int
+ (b'\x61\x00\x71\x1E', 'LLIL_INTRINSIC([w1],vcvtmd_u32_f64,[LLIL_REG.q(d3)])'),
+ # fcvtmu w5, d13 FCVTMU_32D_float2int
+ (b'\xA5\x01\x71\x1E', 'LLIL_INTRINSIC([w5],vcvtmd_u32_f64,[LLIL_REG.q(d13)])'),
+ # fcvtmu w5, s23 FCVTMU_32S_float2int
+ (b'\xE5\x02\x31\x1E', 'LLIL_INTRINSIC([w5],vcvtms_u32_f32,[LLIL_REG.d(s23)])'),
+ # fcvtmu w28, s31 FCVTMU_32S_float2int
+ (b'\xFC\x03\x31\x1E', 'LLIL_INTRINSIC([w28],vcvtms_u32_f32,[LLIL_REG.d(s31)])'),
+ # fcvtmu x26, d24 FCVTMU_64D_float2int
+ (b'\x1A\x03\x71\x9E', 'LLIL_INTRINSIC([x26],vcvtmd_u64_f64,[LLIL_REG.q(d24)])'),
+ # fcvtmu x5, d20 FCVTMU_64D_float2int
+ (b'\x85\x02\x71\x9E', 'LLIL_INTRINSIC([x5],vcvtmd_u64_f64,[LLIL_REG.q(d20)])'),
+ # fcvtmu xzr, s3 FCVTMU_64S_float2int
+ (b'\x7F\x00\x31\x9E', 'LLIL_INTRINSIC([xzr],vcvtmd_u64_f64,[LLIL_REG.d(s3)])'),
+ # fcvtmu x23, s24 FCVTMU_64S_float2int
+ (b'\x17\x03\x31\x9E', 'LLIL_INTRINSIC([x23],vcvtmd_u64_f64,[LLIL_REG.d(s24)])'),
+ # fcvtmu v20.4s, v1.4s FCVTMU_asimdmisc_R
+ (b'\x34\xB8\x21\x6E', 'LLIL_INTRINSIC([v20],vcvtmq_u32_f32,[LLIL_REG.o(v1)])'),
+ # fcvtmu v29.2d, v19.2d FCVTMU_asimdmisc_R
+ (b'\x7D\xBA\x61\x6E', 'LLIL_INTRINSIC([v29],vcvtmq_u64_f64,[LLIL_REG.o(v19)])'),
+ # fcvtmu d13, d31 FCVTMU_asisdmisc_R
+ (b'\xED\xBB\x61\x7E', 'LLIL_INTRINSIC([d13],vcvtmd_u64_f64,[LLIL_REG.q(d31)])'),
+ # fcvtmu s10, s27 FCVTMU_asisdmisc_R
+ (b'\x6A\xBB\x21\x7E', 'LLIL_INTRINSIC([s10],vcvtms_u32_f32,[LLIL_REG.d(s27)])'),
+ # fcvtns w6, d2 FCVTNS_32D_float2int
+ (b'\x46\x00\x60\x1E', 'LLIL_INTRINSIC([w6],vcvtnd_s32_f64,[LLIL_REG.q(d2)])'),
+ # fcvtns w6, d14 FCVTNS_32D_float2int
+ (b'\xC6\x01\x60\x1E', 'LLIL_INTRINSIC([w6],vcvtnd_s32_f64,[LLIL_REG.q(d14)])'),
+ # fcvtns w28, s5 FCVTNS_32S_float2int
+ (b'\xBC\x00\x20\x1E', 'LLIL_INTRINSIC([w28],vcvtns_s32_f32,[LLIL_REG.d(s5)])'),
+ # fcvtns w29, s4 FCVTNS_32S_float2int
+ (b'\x9D\x00\x20\x1E', 'LLIL_INTRINSIC([w29],vcvtns_s32_f32,[LLIL_REG.d(s4)])'),
+ # fcvtns xzr, d7 FCVTNS_64D_float2int
+ (b'\xFF\x00\x60\x9E', 'LLIL_INTRINSIC([xzr],vcvtnd_s64_f64,[LLIL_REG.q(d7)])'),
+ # fcvtns x3, d25 FCVTNS_64D_float2int
+ (b'\x23\x03\x60\x9E', 'LLIL_INTRINSIC([x3],vcvtnd_s64_f64,[LLIL_REG.q(d25)])'),
+ # fcvtns x20, s28 FCVTNS_64S_float2int
+ (b'\x94\x03\x20\x9E', 'LLIL_INTRINSIC([x20],vcvtns_s64_f32,[LLIL_REG.d(s28)])'),
+ # fcvtns x0, s4 FCVTNS_64S_float2int
+ (b'\x80\x00\x20\x9E', 'LLIL_INTRINSIC([x0],vcvtns_s64_f32,[LLIL_REG.d(s4)])'),
+ # fcvtns v3.4s, v21.4s FCVTNS_asimdmisc_R
+ (b'\xA3\xAA\x21\x4E', 'LLIL_INTRINSIC([v3],vcvtnq_s32_f32,[LLIL_REG.o(v21)])'),
+ # fcvtns v10.2s, v9.2s FCVTNS_asimdmisc_R
+ (b'\x2A\xA9\x21\x0E', 'LLIL_INTRINSIC([v10],vcvtn_s32_f32,[LLIL_REG.o(v9)])'),
+ # fcvtns s18, s0 FCVTNS_asisdmisc_R
+ (b'\x12\xA8\x21\x5E', 'LLIL_INTRINSIC([s18],vcvtns_s32_f32,[LLIL_REG.d(s0)])'),
+ # fcvtns d7, d16 FCVTNS_asisdmisc_R
+ (b'\x07\xAA\x61\x5E', 'LLIL_INTRINSIC([d7],vcvtnd_s64_f64,[LLIL_REG.q(d16)])'),
+ # fcvtnu w17, d18 FCVTNU_32D_float2int
+ (b'\x51\x02\x61\x1E', 'LLIL_INTRINSIC([w17],vcvtnd_s32_f64,[LLIL_REG.q(d18)])'),
+ # fcvtnu w30, d16 FCVTNU_32D_float2int
+ (b'\x1E\x02\x61\x1E', 'LLIL_INTRINSIC([w30],vcvtnd_s32_f64,[LLIL_REG.q(d16)])'),
+ # fcvtnu w27, s6 FCVTNU_32S_float2int
+ (b'\xDB\x00\x21\x1E', 'LLIL_INTRINSIC([w27],vcvtns_u32_f32,[LLIL_REG.d(s6)])'),
+ # fcvtnu w4, s14 FCVTNU_32S_float2int
+ (b'\xC4\x01\x21\x1E', 'LLIL_INTRINSIC([w4],vcvtns_u32_f32,[LLIL_REG.d(s14)])'),
+ # fcvtnu x10, d11 FCVTNU_64D_float2int
+ (b'\x6A\x01\x61\x9E', 'LLIL_INTRINSIC([x10],vcvtnd_s64_f64,[LLIL_REG.q(d11)])'),
+ # fcvtnu x2, d27 FCVTNU_64D_float2int
+ (b'\x62\x03\x61\x9E', 'LLIL_INTRINSIC([x2],vcvtnd_s64_f64,[LLIL_REG.q(d27)])'),
+ # fcvtnu x17, s3 FCVTNU_64S_float2int
+ (b'\x71\x00\x21\x9E', 'LLIL_INTRINSIC([x17],vcvtns_u64_f32,[LLIL_REG.d(s3)])'),
+ # fcvtnu x30, s18 FCVTNU_64S_float2int
+ (b'\x5E\x02\x21\x9E', 'LLIL_INTRINSIC([x30],vcvtns_u64_f32,[LLIL_REG.d(s18)])'),
+ # fcvtnu v29.4s, v22.4s FCVTNU_asimdmisc_R
+ (b'\xDD\xAA\x21\x6E', 'LLIL_INTRINSIC([v29],vcvtnq_u32_f32,[LLIL_REG.o(v22)])'),
+ # fcvtnu v24.2s, v15.2s FCVTNU_asimdmisc_R
+ (b'\xF8\xA9\x21\x2E', 'LLIL_INTRINSIC([v24],vcvtn_u32_f32,[LLIL_REG.o(v15)])'),
+ # fcvtnu s9, s1 FCVTNU_asisdmisc_R
+ (b'\x29\xA8\x21\x7E', 'LLIL_INTRINSIC([s9],vcvtns_u32_f32,[LLIL_REG.d(s1)])'),
+ # fcvtnu s13, s14 FCVTNU_asisdmisc_R
+ (b'\xCD\xA9\x21\x7E', 'LLIL_INTRINSIC([s13],vcvtns_u32_f32,[LLIL_REG.d(s14)])'),
+ # fcvtn v2.2s, v13.2d FCVTN_asimdmisc_N
+ (b'\xA2\x69\x61\x0E', 'LLIL_INTRINSIC([v2],vcvt_f32_f64,[LLIL_REG.o(v2),LLIL_REG.o(v13)])'),
+ # fcvtn v15.2s, v14.2d FCVTN_asimdmisc_N
+ (b'\xCF\x69\x61\x0E', 'LLIL_INTRINSIC([v15],vcvt_f32_f64,[LLIL_REG.o(v15),LLIL_REG.o(v14)])'),
+ # fcvtps w22, d11 FCVTPS_32D_float2int
+ (b'\x76\x01\x68\x1E', 'LLIL_INTRINSIC([w22],vcvtpd_s32_f64,[LLIL_REG.q(d11)])'),
+ # fcvtps w17, d29 FCVTPS_32D_float2int
+ (b'\xB1\x03\x68\x1E', 'LLIL_INTRINSIC([w17],vcvtpd_s32_f64,[LLIL_REG.q(d29)])'),
+ # fcvtps w23, s11 FCVTPS_32S_float2int
+ (b'\x77\x01\x28\x1E', 'LLIL_INTRINSIC([w23],vcvtps_s32_f32,[LLIL_REG.d(s11)])'),
+ # fcvtps w3, s14 FCVTPS_32S_float2int
+ (b'\xC3\x01\x28\x1E', 'LLIL_INTRINSIC([w3],vcvtps_s32_f32,[LLIL_REG.d(s14)])'),
+ # fcvtps x28, d21 FCVTPS_64D_float2int
+ (b'\xBC\x02\x68\x9E', 'LLIL_INTRINSIC([x28],vcvtpd_s64_f64,[LLIL_REG.q(d21)])'),
+ # fcvtps xzr, d26 FCVTPS_64D_float2int
+ (b'\x5F\x03\x68\x9E', 'LLIL_INTRINSIC([xzr],vcvtpd_s64_f64,[LLIL_REG.q(d26)])'),
+ # fcvtps x3, s30 FCVTPS_64S_float2int
+ (b'\xC3\x03\x28\x9E', 'LLIL_INTRINSIC([x3],vcvtpd_s64_f64,[LLIL_REG.d(s30)])'),
+ # fcvtps x12, s25 FCVTPS_64S_float2int
+ (b'\x2C\x03\x28\x9E', 'LLIL_INTRINSIC([x12],vcvtpd_s64_f64,[LLIL_REG.d(s25)])'),
+ # fcvtps v4.2d, v7.2d FCVTPS_asimdmisc_R
+ (b'\xE4\xA8\xE1\x4E', 'LLIL_INTRINSIC([v4],vcvtpq_s64_f64,[LLIL_REG.o(v7)])'),
+ # fcvtps v1.4s, v3.4s FCVTPS_asimdmisc_R
+ (b'\x61\xA8\xA1\x4E', 'LLIL_INTRINSIC([v1],vcvtpq_s32_f32,[LLIL_REG.o(v3)])'),
+ # fcvtps d11, d17 FCVTPS_asisdmisc_R
+ (b'\x2B\xAA\xE1\x5E', 'LLIL_INTRINSIC([d11],vcvtpd_s64_f64,[LLIL_REG.q(d17)])'),
+ # fcvtps s23, s17 FCVTPS_asisdmisc_R
+ (b'\x37\xAA\xA1\x5E', 'LLIL_INTRINSIC([s23],vcvtps_s32_f32,[LLIL_REG.d(s17)])'),
+ # fcvtpu w1, d13 FCVTPU_32D_float2int
+ (b'\xA1\x01\x69\x1E', 'LLIL_INTRINSIC([w1],vcvtpd_u32_f64,[LLIL_REG.q(d13)])'),
+ # fcvtpu w17, d3 FCVTPU_32D_float2int
+ (b'\x71\x00\x69\x1E', 'LLIL_INTRINSIC([w17],vcvtpd_u32_f64,[LLIL_REG.q(d3)])'),
+ # fcvtpu w17, s3 FCVTPU_32S_float2int
+ (b'\x71\x00\x29\x1E', 'LLIL_INTRINSIC([w17],vcvtps_u32_f32,[LLIL_REG.d(s3)])'),
+ # fcvtpu w14, s26 FCVTPU_32S_float2int
+ (b'\x4E\x03\x29\x1E', 'LLIL_INTRINSIC([w14],vcvtps_u32_f32,[LLIL_REG.d(s26)])'),
+ # fcvtpu x5, d18 FCVTPU_64D_float2int
+ (b'\x45\x02\x69\x9E', 'LLIL_INTRINSIC([x5],vcvtpd_u64_f64,[LLIL_REG.q(d18)])'),
+ # fcvtpu x24, d30 FCVTPU_64D_float2int
+ (b'\xD8\x03\x69\x9E', 'LLIL_INTRINSIC([x24],vcvtpd_u64_f64,[LLIL_REG.q(d30)])'),
+ # fcvtpu x21, s18 FCVTPU_64S_float2int
+ (b'\x55\x02\x29\x9E', 'LLIL_INTRINSIC([x21],vcvtpd_u64_f64,[LLIL_REG.d(s18)])'),
+ # fcvtpu x3, s8 FCVTPU_64S_float2int
+ (b'\x03\x01\x29\x9E', 'LLIL_INTRINSIC([x3],vcvtpd_u64_f64,[LLIL_REG.d(s8)])'),
+ # fcvtpu v12.2s, v20.2s FCVTPU_asimdmisc_R
+ (b'\x8C\xAA\xA1\x2E', 'LLIL_INTRINSIC([v12],vcvtp_u32_f32,[LLIL_REG.o(v20)])'),
+ # fcvtpu v21.2s, v15.2s FCVTPU_asimdmisc_R
+ (b'\xF5\xA9\xA1\x2E', 'LLIL_INTRINSIC([v21],vcvtp_u32_f32,[LLIL_REG.o(v15)])'),
+ # fcvtpu d0, d11 FCVTPU_asisdmisc_R
+ (b'\x60\xA9\xE1\x7E', 'LLIL_INTRINSIC([d0],vcvtpd_u64_f64,[LLIL_REG.q(d11)])'),
+ # fcvtpu d21, d23 FCVTPU_asisdmisc_R
+ (b'\xF5\xAA\xE1\x7E', 'LLIL_INTRINSIC([d21],vcvtpd_u64_f64,[LLIL_REG.q(d23)])'),
+ # fcvtxn2 v27.4s, v24.2d FCVTXN_asimdmisc_N
+ (b'\x1B\x6B\x61\x6E', 'LLIL_INTRINSIC([v27],vcvtx_high_f32_f64,[LLIL_REG.o(v27),LLIL_REG.o(v24)])'),
+ # fcvtxn v4.2s, v11.2d FCVTXN_asimdmisc_N
+ (b'\x64\x69\x61\x2E', 'LLIL_INTRINSIC([v4],vcvtx_f32_f64,[LLIL_REG.o(v4),LLIL_REG.o(v11)])'),
+ # fcvtxn s4, d5 FCVTXN_asisdmisc_N
+ (b'\xA4\x68\x61\x7E', 'LLIL_INTRINSIC([s4],vcvtxd_f32_f64,[LLIL_REG.q(d5)])'),
+ # fcvtxn s22, d9 FCVTXN_asisdmisc_N
+ (b'\x36\x69\x61\x7E', 'LLIL_INTRINSIC([s22],vcvtxd_f32_f64,[LLIL_REG.q(d9)])'),
+ # fcvtzs w5, d23 FCVTZS_32D_float2int
+ (b'\xE5\x02\x78\x1E', 'LLIL_INTRINSIC([w5],vcvtd_s32_f64,[LLIL_REG.q(d23)])'),
+ # fcvtzs w16, d31 FCVTZS_32D_float2int
+ (b'\xF0\x03\x78\x1E', 'LLIL_INTRINSIC([w16],vcvtd_s32_f64,[LLIL_REG.q(d31)])'),
+ # fcvtzs w27, s20 FCVTZS_32S_float2int
+ (b'\x9B\x02\x38\x1E', 'LLIL_INTRINSIC([w27],vcvts_s32_f32,[LLIL_REG.d(s20)])'),
+ # fcvtzs w24, s21 FCVTZS_32S_float2int
+ (b'\xB8\x02\x38\x1E', 'LLIL_INTRINSIC([w24],vcvts_s32_f32,[LLIL_REG.d(s21)])'),
+ # fcvtzs x11, d7, #0x12 FCVTZS_64D_float2fix
+ (b'\xEB\xB8\x58\x9E', 'LLIL_INTRINSIC([x11],vcvtd_n_s64_f64,[LLIL_REG.q(d7),LLIL_CONST(18)])'),
+ # fcvtzs x8, d8, #0x3e FCVTZS_64D_float2fix
+ (b'\x08\x09\x58\x9E', 'LLIL_INTRINSIC([x8],vcvtd_n_s64_f64,[LLIL_REG.q(d8),LLIL_CONST(62)])'),
+ # fcvtzs x17, d10 FCVTZS_64D_float2int
+ (b'\x51\x01\x78\x9E', 'LLIL_INTRINSIC([x17],vcvtd_s64_f64,[LLIL_REG.q(d10)])'),
+ # fcvtzs x17, d6 FCVTZS_64D_float2int
+ (b'\xD1\x00\x78\x9E', 'LLIL_INTRINSIC([x17],vcvtd_s64_f64,[LLIL_REG.q(d6)])'),
+ # fcvtzs x19, s1 FCVTZS_64S_float2int
+ (b'\x33\x00\x38\x9E', 'LLIL_INTRINSIC([x19],vcvts_s64_f32,[LLIL_REG.d(s1)])'),
+ # fcvtzs x28, s16 FCVTZS_64S_float2int
+ (b'\x1C\x02\x38\x9E', 'LLIL_INTRINSIC([x28],vcvts_s64_f32,[LLIL_REG.d(s16)])'),
+ # fcvtzs v22.2s, v11.2s FCVTZS_asimdmisc_R
+ (b'\x76\xB9\xA1\x0E', 'LLIL_INTRINSIC([v22],vcvt_s32_f32,[LLIL_REG.o(v11)])'),
+ # fcvtzs v16.2d, v24.2d FCVTZS_asimdmisc_R
+ (b'\x10\xBB\xE1\x4E', 'LLIL_INTRINSIC([v16],vcvtq_s64_f64,[LLIL_REG.o(v24)])'),
+ # fcvtzs v31.8h, v29.8h, #0x10 FCVTZS_asimdshf_C
+ (b'\xBF\xFF\x10\x4F', 'LLIL_INTRINSIC([v31],vcvtq_n_s16_f16,[LLIL_REG.o(v29),LLIL_CONST(16)])'),
+ # fcvtzs v13.2d, v29.2d, #0x2f FCVTZS_asimdshf_C
+ (b'\xAD\xFF\x51\x4F', 'LLIL_INTRINSIC([v13],vcvtq_n_s64_f64,[LLIL_REG.o(v29),LLIL_CONST(47)])'),
+ # fcvtzs d4, d1 FCVTZS_asisdmisc_R
+ (b'\x24\xB8\xE1\x5E', 'LLIL_INTRINSIC([d4],vcvtd_s64_f64,[LLIL_REG.q(d1)])'),
+ # fcvtzs s9, s0 FCVTZS_asisdmisc_R
+ (b'\x09\xB8\xA1\x5E', 'LLIL_INTRINSIC([s9],vcvts_s32_f32,[LLIL_REG.d(s0)])'),
+ # fcvtzs d21, d4, #0x4 FCVTZS_asisdshf_C
+ (b'\x95\xFC\x7C\x5F', 'LLIL_INTRINSIC([d21],vcvtd_n_s64_f64,[LLIL_REG.q(d4),LLIL_CONST(4)])'),
+ # fcvtzs d27, d5, #0x2f FCVTZS_asisdshf_C
+ (b'\xBB\xFC\x51\x5F', 'LLIL_INTRINSIC([d27],vcvtd_n_s64_f64,[LLIL_REG.q(d5),LLIL_CONST(47)])'),
+ # fcvtzu w22, d30, #0x18 FCVTZU_32D_float2fix
+ (b'\xD6\xA3\x59\x1E', 'LLIL_INTRINSIC([w22],vcvts_n_u32_f64,[LLIL_REG.q(d30),LLIL_CONST(24)])'),
+ # fcvtzu w23, d16, #0x1d FCVTZU_32D_float2fix
+ (b'\x17\x8E\x59\x1E', 'LLIL_INTRINSIC([w23],vcvts_n_u32_f64,[LLIL_REG.q(d16),LLIL_CONST(29)])'),
+ # fcvtzu w8, d19 FCVTZU_32D_float2int
+ (b'\x68\x02\x79\x1E', 'LLIL_INTRINSIC([w8],vcvtd_u32_f64,[LLIL_REG.q(d19)])'),
+ # fcvtzu w11, d24 FCVTZU_32D_float2int
+ (b'\x0B\x03\x79\x1E', 'LLIL_INTRINSIC([w11],vcvtd_u32_f64,[LLIL_REG.q(d24)])'),
+ # fcvtzu w18, s24, #0x1f FCVTZU_32S_float2fix
+ (b'\x12\x87\x19\x1E', 'LLIL_INTRINSIC([w18],vcvts_n_u32_f32,[LLIL_REG.d(s24),LLIL_CONST(31)])'),
+ # fcvtzu w9, s9, #0x1b FCVTZU_32S_float2fix
+ (b'\x29\x95\x19\x1E', 'LLIL_INTRINSIC([w9],vcvts_n_u32_f32,[LLIL_REG.d(s9),LLIL_CONST(27)])'),
+ # fcvtzu w4, s18 FCVTZU_32S_float2int
+ (b'\x44\x02\x39\x1E', 'LLIL_INTRINSIC([w4],vcvts_u32_f32,[LLIL_REG.d(s18)])'),
+ # fcvtzu w17, s27 FCVTZU_32S_float2int
+ (b'\x71\x03\x39\x1E', 'LLIL_INTRINSIC([w17],vcvts_u32_f32,[LLIL_REG.d(s27)])'),
+ # fcvtzu x29, d13, #0x37 FCVTZU_64D_float2fix
+ (b'\xBD\x25\x59\x9E', 'LLIL_INTRINSIC([x29],vcvts_n_u32_f64,[LLIL_REG.q(d13),LLIL_CONST(55)])'),
+ # fcvtzu x4, d6, #0x17 FCVTZU_64D_float2fix
+ (b'\xC4\xA4\x59\x9E', 'LLIL_INTRINSIC([x4],vcvts_n_u32_f64,[LLIL_REG.q(d6),LLIL_CONST(23)])'),
+ # fcvtzu x9, d6 FCVTZU_64D_float2int
+ (b'\xC9\x00\x79\x9E', 'LLIL_INTRINSIC([x9],vcvtd_u64_f64,[LLIL_REG.q(d6)])'),
+ # fcvtzu x9, d25 FCVTZU_64D_float2int
+ (b'\x29\x03\x79\x9E', 'LLIL_INTRINSIC([x9],vcvtd_u64_f64,[LLIL_REG.q(d25)])'),
+ # fcvtzu x26, s31, #0x15 FCVTZU_64S_float2fix
+ (b'\xFA\xAF\x19\x9E', 'LLIL_INTRINSIC([x26],vcvts_n_u64_f32,[LLIL_REG.d(s31),LLIL_CONST(21)])'),
+ # fcvtzu x27, s11, #0x21 FCVTZU_64S_float2fix
+ (b'\x7B\x7D\x19\x9E', 'LLIL_INTRINSIC([x27],vcvts_n_u64_f32,[LLIL_REG.d(s11),LLIL_CONST(33)])'),
+ # fcvtzu x5, s19 FCVTZU_64S_float2int
+ (b'\x65\x02\x39\x9E', 'LLIL_INTRINSIC([x5],vcvt_n_u64_f32,[LLIL_REG.d(s19)])'),
+ # fcvtzu xzr, s22 FCVTZU_64S_float2int
+ (b'\xDF\x02\x39\x9E', 'LLIL_INTRINSIC([xzr],vcvt_n_u64_f32,[LLIL_REG.d(s22)])'),
+ # fcvtzu v23.4s, v22.4s FCVTZU_asimdmisc_R
+ (b'\xD7\xBA\xA1\x6E', 'LLIL_INTRINSIC([v23],vcvtq_u32_f32,[LLIL_REG.o(v22)])'),
+ # fcvtzu v25.4s, v15.4s FCVTZU_asimdmisc_R
+ (b'\xF9\xB9\xA1\x6E', 'LLIL_INTRINSIC([v25],vcvtq_u32_f32,[LLIL_REG.o(v15)])'),
+ # fcvtzu v3.2d, v25.2d, #0x2f FCVTZU_asimdshf_C
+ (b'\x23\xFF\x51\x6F', 'LLIL_INTRINSIC([v3],vcvtq_n_u64_f64,[LLIL_REG.o(v25),LLIL_CONST(47)])'),
+ # fcvtzu v10.4h, v26.4h, #0x7 FCVTZU_asimdshf_C
+ (b'\x4A\xFF\x19\x2F', 'LLIL_INTRINSIC([v10],vcvt_n_u16_f16,[LLIL_REG.o(v26),LLIL_CONST(7)])'),
+ # fcvtzu s25, s13 FCVTZU_asisdmisc_R
+ (b'\xB9\xB9\xA1\x7E', 'LLIL_INTRINSIC([s25],vcvts_u32_f32,[LLIL_REG.d(s13)])'),
+ # fcvtzu d10, d15 FCVTZU_asisdmisc_R
+ (b'\xEA\xB9\xE1\x7E', 'LLIL_INTRINSIC([d10],vcvtd_u64_f64,[LLIL_REG.q(d15)])'),
+ # fcvtzu d23, d15, #0x3 FCVTZU_asisdshf_C
+ (b'\xF7\xFD\x7D\x7F', 'LLIL_INTRINSIC([d23],vcvtd_n_u64_f64,[LLIL_REG.q(d15),LLIL_CONST(3)])'),
+ # fcvtzu s15, s2, #0x7 FCVTZU_asisdshf_C
+ (b'\x4F\xFC\x39\x7F', 'LLIL_INTRINSIC([s15],vcvts_n_u32_f32,[LLIL_REG.d(s2),LLIL_CONST(7)])'),
]
tests_scvtf = [
- # scvtf s10, s25 SCVTF_asisdmisc_R
- (b'\x2A\xDB\x21\x5E', 'LLIL_SET_REG.d(s10,LLIL_INT_TO_FLOAT.d(LLIL_REG.d(s25)))'),
- # scvtf s20, s11 SCVTF_asisdmisc_R
- (b'\x74\xD9\x21\x5E', 'LLIL_SET_REG.d(s20,LLIL_INT_TO_FLOAT.d(LLIL_REG.d(s11)))'),
- # scvtf d26, d29 SCVTF_asisdmisc_R
- (b'\xBA\xDB\x61\x5E', 'LLIL_SET_REG.q(d26,LLIL_INT_TO_FLOAT.q(LLIL_REG.q(d29)))'),
- # scvtf d29, d7 SCVTF_asisdmisc_R
- (b'\xFD\xD8\x61\x5E', 'LLIL_SET_REG.q(d29,LLIL_INT_TO_FLOAT.q(LLIL_REG.q(d7)))'),
- # scvtf s6, s20 SCVTF_asisdmisc_R
- (b'\x86\xDA\x21\x5E', 'LLIL_SET_REG.d(s6,LLIL_INT_TO_FLOAT.d(LLIL_REG.d(s20)))'),
- # scvtf s21, s24 SCVTF_asisdmisc_R
- (b'\x15\xDB\x21\x5E', 'LLIL_SET_REG.d(s21,LLIL_INT_TO_FLOAT.d(LLIL_REG.d(s24)))'),
- # scvtf s2, s29 SCVTF_asisdmisc_R
- (b'\xA2\xDB\x21\x5E', 'LLIL_SET_REG.d(s2,LLIL_INT_TO_FLOAT.d(LLIL_REG.d(s29)))'),
- # scvtf s1, s31 SCVTF_asisdmisc_R
- (b'\xE1\xDB\x21\x5E', 'LLIL_SET_REG.d(s1,LLIL_INT_TO_FLOAT.d(LLIL_REG.d(s31)))'),
- # scvtf h20, h5 SCVTF_asisdmiscfp16_R
- (b'\xB4\xD8\x79\x5E', 'LLIL_SET_REG.w(h20,LLIL_INT_TO_FLOAT.w(LLIL_REG.w(h5)))'),
- # scvtf h31, h28 SCVTF_asisdmiscfp16_R
- (b'\x9F\xDB\x79\x5E', 'LLIL_SET_REG.w(h31,LLIL_INT_TO_FLOAT.w(LLIL_REG.w(h28)))'),
- # scvtf h7, h7 SCVTF_asisdmiscfp16_R
- (b'\xE7\xD8\x79\x5E', 'LLIL_SET_REG.w(h7,LLIL_INT_TO_FLOAT.w(LLIL_REG.w(h7)))'),
- # scvtf h20, h14 SCVTF_asisdmiscfp16_R
- (b'\xD4\xD9\x79\x5E', 'LLIL_SET_REG.w(h20,LLIL_INT_TO_FLOAT.w(LLIL_REG.w(h14)))'),
- # scvtf h10, h23 SCVTF_asisdmiscfp16_R
- (b'\xEA\xDA\x79\x5E', 'LLIL_SET_REG.w(h10,LLIL_INT_TO_FLOAT.w(LLIL_REG.w(h23)))'),
- # scvtf h20, h29 SCVTF_asisdmiscfp16_R
- (b'\xB4\xDB\x79\x5E', 'LLIL_SET_REG.w(h20,LLIL_INT_TO_FLOAT.w(LLIL_REG.w(h29)))'),
- # scvtf h9, h26 SCVTF_asisdmiscfp16_R
- (b'\x49\xDB\x79\x5E', 'LLIL_SET_REG.w(h9,LLIL_INT_TO_FLOAT.w(LLIL_REG.w(h26)))'),
- # scvtf h10, h5 SCVTF_asisdmiscfp16_R
- (b'\xAA\xD8\x79\x5E', 'LLIL_SET_REG.w(h10,LLIL_INT_TO_FLOAT.w(LLIL_REG.w(h5)))'),
- # scvtf s22, w20 SCVTF_S32_float2int
- (b'\x96\x02\x22\x1E', 'LLIL_SET_REG.d(s22,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.d(w20))))'),
- # scvtf s11, w5 SCVTF_S32_float2int
- (b'\xAB\x00\x22\x1E', 'LLIL_SET_REG.d(s11,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.d(w5))))'),
- # scvtf s3, w29 SCVTF_S32_float2int
- (b'\xA3\x03\x22\x1E', 'LLIL_SET_REG.d(s3,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.d(w29))))'),
- # scvtf s9, w13 SCVTF_S32_float2int
- (b'\xA9\x01\x22\x1E', 'LLIL_SET_REG.d(s9,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.d(w13))))'),
- # scvtf s26, w6 SCVTF_S32_float2int
- (b'\xDA\x00\x22\x1E', 'LLIL_SET_REG.d(s26,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.d(w6))))'),
- # scvtf s16, w25 SCVTF_S32_float2int
- (b'\x30\x03\x22\x1E', 'LLIL_SET_REG.d(s16,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.d(w25))))'),
- # scvtf s25, w12 SCVTF_S32_float2int
- (b'\x99\x01\x22\x1E', 'LLIL_SET_REG.d(s25,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.d(w12))))'),
- # scvtf s24, w15 SCVTF_S32_float2int
- (b'\xF8\x01\x22\x1E', 'LLIL_SET_REG.d(s24,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.d(w15))))'),
- # scvtf s12, x1 SCVTF_S64_float2int
- (b'\x2C\x00\x22\x9E', 'LLIL_SET_REG.d(s12,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.q(x1))))'),
- # scvtf s24, x25 SCVTF_S64_float2int
- (b'\x38\x03\x22\x9E', 'LLIL_SET_REG.d(s24,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.q(x25))))'),
- # scvtf s2, x10 SCVTF_S64_float2int
- (b'\x42\x01\x22\x9E', 'LLIL_SET_REG.d(s2,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.q(x10))))'),
- # scvtf s0, x17 SCVTF_S64_float2int
- (b'\x20\x02\x22\x9E', 'LLIL_SET_REG.d(s0,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.q(x17))))'),
- # scvtf s18, x20 SCVTF_S64_float2int
- (b'\x92\x02\x22\x9E', 'LLIL_SET_REG.d(s18,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.q(x20))))'),
- # scvtf s30, x7 SCVTF_S64_float2int
- (b'\xFE\x00\x22\x9E', 'LLIL_SET_REG.d(s30,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.q(x7))))'),
- # scvtf s2, x26 SCVTF_S64_float2int
- (b'\x42\x03\x22\x9E', 'LLIL_SET_REG.d(s2,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.q(x26))))'),
- # scvtf s28, x18 SCVTF_S64_float2int
- (b'\x5C\x02\x22\x9E', 'LLIL_SET_REG.d(s28,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.q(x18))))'),
+ # scvtf d9, w19, #0x12 SCVTF_D32_float2fix
+ (b'\x69\xBA\x42\x1E', 'LLIL_INTRINSIC([d9],vcvts_n_f64_s32,[LLIL_REG.d(w19),LLIL_CONST(18)])'),
+ # scvtf d1, w24, #0x12 SCVTF_D32_float2fix
+ (b'\x01\xBB\x42\x1E', 'LLIL_INTRINSIC([d1],vcvts_n_f64_s32,[LLIL_REG.d(w24),LLIL_CONST(18)])'),
# scvtf d3, w3 SCVTF_D32_float2int
(b'\x63\x00\x62\x1E', 'LLIL_SET_REG.q(d3,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.d(w3))))'),
# scvtf d1, w2 SCVTF_D32_float2int
(b'\x41\x00\x62\x1E', 'LLIL_SET_REG.q(d1,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.d(w2))))'),
- # scvtf d28, w4 SCVTF_D32_float2int
- (b'\x9C\x00\x62\x1E', 'LLIL_SET_REG.q(d28,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.d(w4))))'),
- # scvtf d11, w9 SCVTF_D32_float2int
- (b'\x2B\x01\x62\x1E', 'LLIL_SET_REG.q(d11,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.d(w9))))'),
- # scvtf d28, w0 SCVTF_D32_float2int
- (b'\x1C\x00\x62\x1E', 'LLIL_SET_REG.q(d28,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.d(w0))))'),
- # scvtf d12, w12 SCVTF_D32_float2int
- (b'\x8C\x01\x62\x1E', 'LLIL_SET_REG.q(d12,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.d(w12))))'),
- # scvtf d4, w9 SCVTF_D32_float2int
- (b'\x24\x01\x62\x1E', 'LLIL_SET_REG.q(d4,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.d(w9))))'),
- # scvtf d12, w24 SCVTF_D32_float2int
- (b'\x0C\x03\x62\x1E', 'LLIL_SET_REG.q(d12,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.d(w24))))'),
+ # scvtf d1, x20, #0x20 SCVTF_D64_float2fix
+ (b'\x81\x82\x42\x9E', 'LLIL_INTRINSIC([d1],vcvtd_n_f64_s64,[LLIL_REG.q(x20),LLIL_CONST(32)])'),
+ # scvtf d3, x28, #0xd SCVTF_D64_float2fix
+ (b'\x83\xCF\x42\x9E', 'LLIL_INTRINSIC([d3],vcvtd_n_f64_s64,[LLIL_REG.q(x28),LLIL_CONST(13)])'),
# scvtf d16, x17 SCVTF_D64_float2int
(b'\x30\x02\x62\x9E', 'LLIL_SET_REG.q(d16,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.q(x17))))'),
# scvtf d15, x22 SCVTF_D64_float2int
(b'\xCF\x02\x62\x9E', 'LLIL_SET_REG.q(d15,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.q(x22))))'),
- # scvtf d3, x15 SCVTF_D64_float2int
- (b'\xE3\x01\x62\x9E', 'LLIL_SET_REG.q(d3,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.q(x15))))'),
- # scvtf d3, x9 SCVTF_D64_float2int
- (b'\x23\x01\x62\x9E', 'LLIL_SET_REG.q(d3,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.q(x9))))'),
- # scvtf d24, x1 SCVTF_D64_float2int
- (b'\x38\x00\x62\x9E', 'LLIL_SET_REG.q(d24,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.q(x1))))'),
- # scvtf d20, x19 SCVTF_D64_float2int
- (b'\x74\x02\x62\x9E', 'LLIL_SET_REG.q(d20,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.q(x19))))'),
- # scvtf d0, x12 SCVTF_D64_float2int
- (b'\x80\x01\x62\x9E', 'LLIL_SET_REG.q(d0,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.q(x12))))'),
- # scvtf d3, x19 SCVTF_D64_float2int
- (b'\x63\x02\x62\x9E', 'LLIL_SET_REG.q(d3,LLIL_INT_TO_FLOAT.q(LLIL_SX.q(LLIL_REG.q(x19))))'),
+ # scvtf h6, wzr, #0x1e SCVTF_H32_float2fix
+ (b'\xE6\x8B\xC2\x1E', 'LLIL_INTRINSIC([h6],vcvth_n_f16_s32,[LLIL_CONST.d(0x0),LLIL_CONST(30)])'),
+ # scvtf h20, w29, #0x1b SCVTF_H32_float2fix
+ (b'\xB4\x97\xC2\x1E', 'LLIL_INTRINSIC([h20],vcvth_n_f16_s32,[LLIL_REG.d(w29),LLIL_CONST(27)])'),
# scvtf h13, w7 SCVTF_H32_float2int
(b'\xED\x00\xE2\x1E', 'LLIL_SET_REG.w(h13,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_REG.d(w7))))'),
# scvtf h0, w23 SCVTF_H32_float2int
(b'\xE0\x02\xE2\x1E', 'LLIL_SET_REG.w(h0,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_REG.d(w23))))'),
- # scvtf h7, w22 SCVTF_H32_float2int
- (b'\xC7\x02\xE2\x1E', 'LLIL_SET_REG.w(h7,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_REG.d(w22))))'),
- # scvtf h17, w12 SCVTF_H32_float2int
- (b'\x91\x01\xE2\x1E', 'LLIL_SET_REG.w(h17,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_REG.d(w12))))'),
- # scvtf h19, w24 SCVTF_H32_float2int
- (b'\x13\x03\xE2\x1E', 'LLIL_SET_REG.w(h19,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_REG.d(w24))))'),
- # scvtf h12, w9 SCVTF_H32_float2int
- (b'\x2C\x01\xE2\x1E', 'LLIL_SET_REG.w(h12,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_REG.d(w9))))'),
- # scvtf h8, w6 SCVTF_H32_float2int
- (b'\xC8\x00\xE2\x1E', 'LLIL_SET_REG.w(h8,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_REG.d(w6))))'),
- # scvtf h22, w5 SCVTF_H32_float2int
- (b'\xB6\x00\xE2\x1E', 'LLIL_SET_REG.w(h22,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_REG.d(w5))))'),
+ # scvtf h19, x11, #0x12 SCVTF_H64_float2fix
+ (b'\x73\xB9\xC2\x9E', 'LLIL_INTRINSIC([h19],vcvth_n_f16_s64,[LLIL_REG.q(x11),LLIL_CONST(18)])'),
+ # scvtf h7, x4, #0x3a SCVTF_H64_float2fix
+ (b'\x87\x18\xC2\x9E', 'LLIL_INTRINSIC([h7],vcvth_n_f16_s64,[LLIL_REG.q(x4),LLIL_CONST(58)])'),
# scvtf h8, x29 SCVTF_H64_float2int
(b'\xA8\x03\xE2\x9E', 'LLIL_SET_REG.w(h8,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_REG.q(x29))))'),
# scvtf h28, xzr SCVTF_H64_float2int
(b'\xFC\x03\xE2\x9E', 'LLIL_SET_REG.w(h28,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_CONST.q(0x0))))'),
- # scvtf h16, x27 SCVTF_H64_float2int
- (b'\x70\x03\xE2\x9E', 'LLIL_SET_REG.w(h16,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_REG.q(x27))))'),
- # scvtf h17, x23 SCVTF_H64_float2int
- (b'\xF1\x02\xE2\x9E', 'LLIL_SET_REG.w(h17,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_REG.q(x23))))'),
- # scvtf h9, x24 SCVTF_H64_float2int
- (b'\x09\x03\xE2\x9E', 'LLIL_SET_REG.w(h9,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_REG.q(x24))))'),
- # scvtf h15, x26 SCVTF_H64_float2int
- (b'\x4F\x03\xE2\x9E', 'LLIL_SET_REG.w(h15,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_REG.q(x26))))'),
- # scvtf h8, x20 SCVTF_H64_float2int
- (b'\x88\x02\xE2\x9E', 'LLIL_SET_REG.w(h8,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_REG.q(x20))))'),
- # scvtf h1, x10 SCVTF_H64_float2int
- (b'\x41\x01\xE2\x9E', 'LLIL_SET_REG.w(h1,LLIL_INT_TO_FLOAT.w(LLIL_SX.w(LLIL_REG.q(x10))))'),
+ # scvtf s22, w4, #0x9 SCVTF_S32_float2fix
+ (b'\x96\xDC\x02\x1E', 'LLIL_INTRINSIC([s22],vcvts_n_f32_s32,[LLIL_REG.d(w4),LLIL_CONST(9)])'),
+ # scvtf s14, w11, #0x9 SCVTF_S32_float2fix
+ (b'\x6E\xDD\x02\x1E', 'LLIL_INTRINSIC([s14],vcvts_n_f32_s32,[LLIL_REG.d(w11),LLIL_CONST(9)])'),
+ # scvtf s22, w20 SCVTF_S32_float2int
+ (b'\x96\x02\x22\x1E', 'LLIL_SET_REG.d(s22,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.d(w20))))'),
+ # scvtf s11, w5 SCVTF_S32_float2int
+ (b'\xAB\x00\x22\x1E', 'LLIL_SET_REG.d(s11,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.d(w5))))'),
+ # scvtf s7, x11, #0x40 SCVTF_S64_float2fix
+ (b'\x67\x01\x02\x9E', 'LLIL_INTRINSIC([s7],vcvts_n_f32_s64,[LLIL_REG.q(x11),LLIL_CONST(64)])'),
+ # scvtf s8, x8, #0x6 SCVTF_S64_float2fix
+ (b'\x08\xE9\x02\x9E', 'LLIL_INTRINSIC([s8],vcvts_n_f32_s64,[LLIL_REG.q(x8),LLIL_CONST(6)])'),
+ # scvtf s12, x1 SCVTF_S64_float2int
+ (b'\x2C\x00\x22\x9E', 'LLIL_SET_REG.d(s12,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.q(x1))))'),
+ # scvtf s24, x25 SCVTF_S64_float2int
+ (b'\x38\x03\x22\x9E', 'LLIL_SET_REG.d(s24,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.q(x25))))'),
+ # scvtf v26.2s, v22.2s SCVTF_asimdmisc_R
+ (b'\xDA\xDA\x21\x0E', 'LLIL_INTRINSIC([v26],vcvt_f32_s32,[LLIL_REG.o(v22)])'),
+ # scvtf v13.4s, v31.4s SCVTF_asimdmisc_R
+ (b'\xED\xDB\x21\x4E', 'LLIL_INTRINSIC([v13],vcvtq_f32_s32,[LLIL_REG.o(v31)])'),
+ # scvtf v30.4h, v27.4h, #0xf SCVTF_asimdshf_C
+ (b'\x7E\xE7\x11\x0F', 'LLIL_INTRINSIC([v30],vcvt_n_f16_s16,[LLIL_REG.o(v27),LLIL_CONST(15)])'),
+ # scvtf v10.4h, v3.4h, #0x1 SCVTF_asimdshf_C
+ (b'\x6A\xE4\x1F\x0F', 'LLIL_INTRINSIC([v10],vcvt_n_f16_s16,[LLIL_REG.o(v3),LLIL_CONST(1)])'),
+ # scvtf s10, s25 SCVTF_asisdmisc_R
+ (b'\x2A\xDB\x21\x5E', 'LLIL_SET_REG.d(s10,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.d(s25))))'),
+ # scvtf s20, s11 SCVTF_asisdmisc_R
+ (b'\x74\xD9\x21\x5E', 'LLIL_SET_REG.d(s20,LLIL_INT_TO_FLOAT.d(LLIL_SX.d(LLIL_REG.d(s11))))'),
+ # scvtf h20, h11, #0xf SCVTF_asisdshf_C
+ (b'\x74\xE5\x11\x5F', 'LLIL_INTRINSIC([h20],vcvth_n_f16_s16,[LLIL_REG.w(h11),LLIL_CONST(15)])'),
+ # scvtf s10, s28, #0x9 SCVTF_asisdshf_C
+ (b'\x8A\xE7\x37\x5F', 'LLIL_INTRINSIC([s10],vcvts_n_f32_s32,[LLIL_REG.d(s28),LLIL_CONST(9)])'),
+]
+
+# tests_sshll = [
+# # sshll v11.2d, v25.2s, #0x9 SSHLL_asimdshf_L
+# (b'\x2B\xA7\x29\x0F', 'LLIL_SET_REG.q(v11.d[0],LLIL_SX.q(LLIL_LSL.q(LLIL_REG.d(v25.s[0]),LLIL_CONST.b(0x9))));' + \
+# ' LLIL_SET_REG.q(v11.d[1],LLIL_SX.q(LLIL_LSL.q(LLIL_REG.d(v25.s[1]),LLIL_CONST.b(0x9))))'),
+# # sshll2 v28.2d, v8.4s, #0x1d SSHLL_asimdshf_L
+# (b'\x1C\xA5\x3D\x4F', 'LLIL_SET_REG.q(v28.d[0],LLIL_SX.q(LLIL_LSL.q(LLIL_LSR.d(LLIL_REG.d(v8.s[0]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x1D))));' + \
+# ' LLIL_SET_REG.q(v28.d[1],LLIL_SX.q(LLIL_LSL.q(LLIL_LSR.d(LLIL_REG.d(v8.s[1]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x1D))))'),
+# # sshll2 v27.4s, v12.8h, #0x8 SSHLL_asimdshf_L
+# (b'\x9B\xA5\x18\x4F', 'LLIL_SET_REG.d(v27.s[0],LLIL_SX.d(LLIL_LSL.d(LLIL_LSR.w(LLIL_REG.w(v12.h[0]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x8))));' + \
+# ' LLIL_SET_REG.d(v27.s[1],LLIL_SX.d(LLIL_LSL.d(LLIL_LSR.w(LLIL_REG.w(v12.h[1]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x8))));' + \
+# ' LLIL_SET_REG.d(v27.s[2],LLIL_SX.d(LLIL_LSL.d(LLIL_LSR.w(LLIL_REG.w(v12.h[2]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x8))));' + \
+# ' LLIL_SET_REG.d(v27.s[3],LLIL_SX.d(LLIL_LSL.d(LLIL_LSR.w(LLIL_REG.w(v12.h[3]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x8))))'),
+# # sshll2 v5.8h, v27.16b, #0x1 SSHLL_asimdshf_L
+# (b'\x65\xA7\x09\x4F', 'LLIL_SET_REG.w(v5.h[0],LLIL_SX.w(LLIL_LSL.w(LLIL_LSR.b(LLIL_REG.b(v27.b[0]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x1))));' + \
+# ' LLIL_SET_REG.w(v5.h[1],LLIL_SX.w(LLIL_LSL.w(LLIL_LSR.b(LLIL_REG.b(v27.b[1]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x1))));' + \
+# ' LLIL_SET_REG.w(v5.h[2],LLIL_SX.w(LLIL_LSL.w(LLIL_LSR.b(LLIL_REG.b(v27.b[2]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x1))));' + \
+# ' LLIL_SET_REG.w(v5.h[3],LLIL_SX.w(LLIL_LSL.w(LLIL_LSR.b(LLIL_REG.b(v27.b[3]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x1))));' + \
+# ' LLIL_SET_REG.w(v5.h[4],LLIL_SX.w(LLIL_LSL.w(LLIL_LSR.b(LLIL_REG.b(v27.b[4]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x1))));' + \
+# ' LLIL_SET_REG.w(v5.h[5],LLIL_SX.w(LLIL_LSL.w(LLIL_LSR.b(LLIL_REG.b(v27.b[5]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x1))));' + \
+# ' LLIL_SET_REG.w(v5.h[6],LLIL_SX.w(LLIL_LSL.w(LLIL_LSR.b(LLIL_REG.b(v27.b[6]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x1))));' + \
+# ' LLIL_SET_REG.w(v5.h[7],LLIL_SX.w(LLIL_LSL.w(LLIL_LSR.b(LLIL_REG.b(v27.b[7]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x1))))'),
+# # sshll2 v26.2d, v27.4s, #0x8 SSHLL_asimdshf_L
+# (b'\x7A\xA7\x28\x4F', 'LLIL_SET_REG.q(v26.d[0],LLIL_SX.q(LLIL_LSL.q(LLIL_LSR.d(LLIL_REG.d(v27.s[0]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x8))));' + \
+# ' LLIL_SET_REG.q(v26.d[1],LLIL_SX.q(LLIL_LSL.q(LLIL_LSR.d(LLIL_REG.d(v27.s[1]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x8))))'),
+# # sshll2 v1.4s, v25.8h, #0x2 SSHLL_asimdshf_L
+# (b'\x21\xA7\x12\x4F', 'LLIL_SET_REG.d(v1.s[0],LLIL_SX.d(LLIL_LSL.d(LLIL_LSR.w(LLIL_REG.w(v25.h[0]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x2))));' + \
+# ' LLIL_SET_REG.d(v1.s[1],LLIL_SX.d(LLIL_LSL.d(LLIL_LSR.w(LLIL_REG.w(v25.h[1]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x2))));' + \
+# ' LLIL_SET_REG.d(v1.s[2],LLIL_SX.d(LLIL_LSL.d(LLIL_LSR.w(LLIL_REG.w(v25.h[2]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x2))));' + \
+# ' LLIL_SET_REG.d(v1.s[3],LLIL_SX.d(LLIL_LSL.d(LLIL_LSR.w(LLIL_REG.w(v25.h[3]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x2))))'),
+# # sshll2 v13.2d, v22.4s, #0x1e SSHLL_asimdshf_L
+# (b'\xCD\xA6\x3E\x4F', 'LLIL_SET_REG.q(v13.d[0],LLIL_SX.q(LLIL_LSL.q(LLIL_LSR.d(LLIL_REG.d(v22.s[0]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x1E))));' + \
+# ' LLIL_SET_REG.q(v13.d[1],LLIL_SX.q(LLIL_LSL.q(LLIL_LSR.d(LLIL_REG.d(v22.s[1]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x1E))))'),
+# # sshll2 v8.2d, v22.4s, #0x8 SSHLL_asimdshf_L
+# (b'\xC8\xA6\x28\x4F', 'LLIL_SET_REG.q(v8.d[0],LLIL_SX.q(LLIL_LSL.q(LLIL_LSR.d(LLIL_REG.d(v22.s[0]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x8))));' + \
+# ' LLIL_SET_REG.q(v8.d[1],LLIL_SX.q(LLIL_LSL.q(LLIL_LSR.d(LLIL_REG.d(v22.s[1]),LLIL_CONST.b(0x40)),LLIL_CONST.b(0x8))))'),
+# # sxtl2 v26.2d, v3.4s SXTL_SSHLL_asimdshf_L
+# (b'\x7A\xA4\x20\x4F', 'LLIL_SET_REG.q(v26.d[0],LLIL_SX.q(LLIL_LSR.d(LLIL_REG.d(v3.s[0]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.q(v26.d[1],LLIL_SX.q(LLIL_LSR.d(LLIL_REG.d(v3.s[1]),LLIL_CONST.b(0x40))))'),
+# # sxtl v16.8h, v28.8b SXTL_SSHLL_asimdshf_L
+# (b'\x90\xA7\x08\x0F', 'LLIL_SET_REG.w(v16.h[0],LLIL_SX.w(LLIL_REG.b(v28.b[0])));' + \
+# ' LLIL_SET_REG.w(v16.h[1],LLIL_SX.w(LLIL_REG.b(v28.b[1])));' + \
+# ' LLIL_SET_REG.w(v16.h[2],LLIL_SX.w(LLIL_REG.b(v28.b[2])));' + \
+# ' LLIL_SET_REG.w(v16.h[3],LLIL_SX.w(LLIL_REG.b(v28.b[3])));' + \
+# ' LLIL_SET_REG.w(v16.h[4],LLIL_SX.w(LLIL_REG.b(v28.b[4])));' + \
+# ' LLIL_SET_REG.w(v16.h[5],LLIL_SX.w(LLIL_REG.b(v28.b[5])));' + \
+# ' LLIL_SET_REG.w(v16.h[6],LLIL_SX.w(LLIL_REG.b(v28.b[6])));' + \
+# ' LLIL_SET_REG.w(v16.h[7],LLIL_SX.w(LLIL_REG.b(v28.b[7])))'),
+# # sxtl2 v27.4s, v15.8h SXTL_SSHLL_asimdshf_L
+# (b'\xFB\xA5\x10\x4F', 'LLIL_SET_REG.d(v27.s[0],LLIL_SX.d(LLIL_LSR.w(LLIL_REG.w(v15.h[0]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.d(v27.s[1],LLIL_SX.d(LLIL_LSR.w(LLIL_REG.w(v15.h[1]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.d(v27.s[2],LLIL_SX.d(LLIL_LSR.w(LLIL_REG.w(v15.h[2]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.d(v27.s[3],LLIL_SX.d(LLIL_LSR.w(LLIL_REG.w(v15.h[3]),LLIL_CONST.b(0x40))))'),
+# # sxtl2 v10.8h, v7.16b SXTL_SSHLL_asimdshf_L
+# (b'\xEA\xA4\x08\x4F', 'LLIL_SET_REG.w(v10.h[0],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v7.b[0]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.w(v10.h[1],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v7.b[1]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.w(v10.h[2],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v7.b[2]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.w(v10.h[3],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v7.b[3]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.w(v10.h[4],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v7.b[4]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.w(v10.h[5],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v7.b[5]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.w(v10.h[6],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v7.b[6]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.w(v10.h[7],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v7.b[7]),LLIL_CONST.b(0x40))))'),
+# # sxtl2 v22.8h, v20.16b SXTL_SSHLL_asimdshf_L
+# (b'\x96\xA6\x08\x4F', 'LLIL_SET_REG.w(v22.h[0],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v20.b[0]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.w(v22.h[1],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v20.b[1]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.w(v22.h[2],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v20.b[2]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.w(v22.h[3],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v20.b[3]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.w(v22.h[4],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v20.b[4]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.w(v22.h[5],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v20.b[5]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.w(v22.h[6],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v20.b[6]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.w(v22.h[7],LLIL_SX.w(LLIL_LSR.b(LLIL_REG.b(v20.b[7]),LLIL_CONST.b(0x40))))'),
+# # sxtl2 v19.4s, v11.8h SXTL_SSHLL_asimdshf_L
+# (b'\x73\xA5\x10\x4F', 'LLIL_SET_REG.d(v19.s[0],LLIL_SX.d(LLIL_LSR.w(LLIL_REG.w(v11.h[0]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.d(v19.s[1],LLIL_SX.d(LLIL_LSR.w(LLIL_REG.w(v11.h[1]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.d(v19.s[2],LLIL_SX.d(LLIL_LSR.w(LLIL_REG.w(v11.h[2]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.d(v19.s[3],LLIL_SX.d(LLIL_LSR.w(LLIL_REG.w(v11.h[3]),LLIL_CONST.b(0x40))))'),
+# # sxtl2 v29.2d, v9.4s SXTL_SSHLL_asimdshf_L
+# (b'\x3D\xA5\x20\x4F', 'LLIL_SET_REG.q(v29.d[0],LLIL_SX.q(LLIL_LSR.d(LLIL_REG.d(v9.s[0]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.q(v29.d[1],LLIL_SX.q(LLIL_LSR.d(LLIL_REG.d(v9.s[1]),LLIL_CONST.b(0x40))))'),
+# # sxtl2 v22.2d, v11.4s SXTL_SSHLL_asimdshf_L
+# (b'\x76\xA5\x20\x4F', 'LLIL_SET_REG.q(v22.d[0],LLIL_SX.q(LLIL_LSR.d(LLIL_REG.d(v11.s[0]),LLIL_CONST.b(0x40))));' + \
+# ' LLIL_SET_REG.q(v22.d[1],LLIL_SX.q(LLIL_LSR.d(LLIL_REG.d(v11.s[1]),LLIL_CONST.b(0x40))))'),
+# ]
+
+tests_shll = [
+ # shll v1.8h, v11.8b, #0x8 SHLL_asimdmisc_S
+ (b'\x61\x39\x21\x2E', 'LLIL_INTRINSIC([v1],vshll_n_s8,[LLIL_REG.o(v11)])'),
+ # shll v14.2d, v20.2s, #0x20 SHLL_asimdmisc_S
+ (b'\x8E\x3A\xA1\x2E', 'LLIL_INTRINSIC([v14],vshll_n_s32,[LLIL_REG.o(v20)])'),
+ # shll v22.2d, v23.2s, #0x20 SHLL_asimdmisc_S
+ (b'\xF6\x3A\xA1\x2E', 'LLIL_INTRINSIC([v22],vshll_n_s32,[LLIL_REG.o(v23)])'),
+ # shll v5.8h, v18.8b, #0x8 SHLL_asimdmisc_S
+ (b'\x45\x3A\x21\x2E', 'LLIL_INTRINSIC([v5],vshll_n_s8,[LLIL_REG.o(v18)])'),
+ # shll v7.2d, v3.2s, #0x20 SHLL_asimdmisc_S
+ (b'\x67\x38\xA1\x2E', 'LLIL_INTRINSIC([v7],vshll_n_s32,[LLIL_REG.o(v3)])'),
+ # shll v3.2d, v20.2s, #0x20 SHLL_asimdmisc_S
+ (b'\x83\x3A\xA1\x2E', 'LLIL_INTRINSIC([v3],vshll_n_s32,[LLIL_REG.o(v20)])'),
+ # shll2 v27.2d, v4.4s, #0x20 SHLL_asimdmisc_S
+ (b'\x9B\x38\xA1\x6E', 'LLIL_INTRINSIC([v27],vshll_high_n_s32,[LLIL_REG.o(v4)])'),
+ # shll2 v26.8h, v26.16b, #0x8 SHLL_asimdmisc_S
+ (b'\x5A\x3B\x21\x6E', 'LLIL_INTRINSIC([v26],vshll_high_n_s8,[LLIL_REG.o(v26)])'),
+ # shl v19.2d, v21.2d, #0x2 SHL_asimdshf_R
+ (b'\xB3\x56\x42\x4F', 'LLIL_SET_REG.q(v19.d[0],LLIL_LSL.q(LLIL_REG.q(v21.d[0]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.q(v19.d[1],LLIL_LSL.q(LLIL_REG.q(v21.d[1]),LLIL_CONST.b(0x2)))'),
+ # shl v7.4h, v8.4h, #0x7 SHL_asimdshf_R
+ (b'\x07\x55\x17\x0F', 'LLIL_SET_REG.w(v7.h[0],LLIL_LSL.w(LLIL_REG.w(v8.h[0]),LLIL_CONST.b(0x7)));' + \
+ ' LLIL_SET_REG.w(v7.h[1],LLIL_LSL.w(LLIL_REG.w(v8.h[1]),LLIL_CONST.b(0x7)));' + \
+ ' LLIL_SET_REG.w(v7.h[2],LLIL_LSL.w(LLIL_REG.w(v8.h[2]),LLIL_CONST.b(0x7)));' + \
+ ' LLIL_SET_REG.w(v7.h[3],LLIL_LSL.w(LLIL_REG.w(v8.h[3]),LLIL_CONST.b(0x7)))'),
+ # shl v2.8h, v20.8h, #0xc SHL_asimdshf_R
+ (b'\x82\x56\x1C\x4F', 'LLIL_SET_REG.w(v2.h[0],LLIL_LSL.w(LLIL_REG.w(v20.h[0]),LLIL_CONST.b(0xC)));' + \
+ ' LLIL_SET_REG.w(v2.h[1],LLIL_LSL.w(LLIL_REG.w(v20.h[1]),LLIL_CONST.b(0xC)));' + \
+ ' LLIL_SET_REG.w(v2.h[2],LLIL_LSL.w(LLIL_REG.w(v20.h[2]),LLIL_CONST.b(0xC)));' + \
+ ' LLIL_SET_REG.w(v2.h[3],LLIL_LSL.w(LLIL_REG.w(v20.h[3]),LLIL_CONST.b(0xC)));' + \
+ ' LLIL_SET_REG.w(v2.h[4],LLIL_LSL.w(LLIL_REG.w(v20.h[4]),LLIL_CONST.b(0xC)));' + \
+ ' LLIL_SET_REG.w(v2.h[5],LLIL_LSL.w(LLIL_REG.w(v20.h[5]),LLIL_CONST.b(0xC)));' + \
+ ' LLIL_SET_REG.w(v2.h[6],LLIL_LSL.w(LLIL_REG.w(v20.h[6]),LLIL_CONST.b(0xC)));' + \
+ ' LLIL_SET_REG.w(v2.h[7],LLIL_LSL.w(LLIL_REG.w(v20.h[7]),LLIL_CONST.b(0xC)))'),
+ # shl v17.2s, v9.2s, #0x5 SHL_asimdshf_R
+ (b'\x31\x55\x25\x0F', 'LLIL_SET_REG.d(v17.s[0],LLIL_LSL.d(LLIL_REG.d(v9.s[0]),LLIL_CONST.b(0x5)));' + \
+ ' LLIL_SET_REG.d(v17.s[1],LLIL_LSL.d(LLIL_REG.d(v9.s[1]),LLIL_CONST.b(0x5)))'),
+ # shl v28.16b, v7.16b, #0x0 SHL_asimdshf_R
+ (b'\xFC\x54\x08\x4F', 'LLIL_SET_REG.b(v28.b[0],LLIL_LSL.b(LLIL_REG.b(v7.b[0]),LLIL_CONST.b(0x0)));' + \
+ ' LLIL_SET_REG.b(v28.b[1],LLIL_LSL.b(LLIL_REG.b(v7.b[1]),LLIL_CONST.b(0x0)));' + \
+ ' LLIL_SET_REG.b(v28.b[2],LLIL_LSL.b(LLIL_REG.b(v7.b[2]),LLIL_CONST.b(0x0)));' + \
+ ' LLIL_SET_REG.b(v28.b[3],LLIL_LSL.b(LLIL_REG.b(v7.b[3]),LLIL_CONST.b(0x0)));' + \
+ ' LLIL_SET_REG.b(v28.b[4],LLIL_LSL.b(LLIL_REG.b(v7.b[4]),LLIL_CONST.b(0x0)));' + \
+ ' LLIL_SET_REG.b(v28.b[5],LLIL_LSL.b(LLIL_REG.b(v7.b[5]),LLIL_CONST.b(0x0)));' + \
+ ' LLIL_SET_REG.b(v28.b[6],LLIL_LSL.b(LLIL_REG.b(v7.b[6]),LLIL_CONST.b(0x0)));' + \
+ ' LLIL_SET_REG.b(v28.b[7],LLIL_LSL.b(LLIL_REG.b(v7.b[7]),LLIL_CONST.b(0x0)));' + \
+ ' LLIL_SET_REG.b(v28.b[8],LLIL_LSL.b(LLIL_REG.b(v7.b[8]),LLIL_CONST.b(0x0)));' + \
+ ' LLIL_SET_REG.b(v28.b[9],LLIL_LSL.b(LLIL_REG.b(v7.b[9]),LLIL_CONST.b(0x0)));' + \
+ ' LLIL_SET_REG.b(v28.b[10],LLIL_LSL.b(LLIL_REG.b(v7.b[10]),LLIL_CONST.b(0x0)));' + \
+ ' LLIL_SET_REG.b(v28.b[11],LLIL_LSL.b(LLIL_REG.b(v7.b[11]),LLIL_CONST.b(0x0)));' + \
+ ' LLIL_SET_REG.b(v28.b[12],LLIL_LSL.b(LLIL_REG.b(v7.b[12]),LLIL_CONST.b(0x0)));' + \
+ ' LLIL_SET_REG.b(v28.b[13],LLIL_LSL.b(LLIL_REG.b(v7.b[13]),LLIL_CONST.b(0x0)));' + \
+ ' LLIL_SET_REG.b(v28.b[14],LLIL_LSL.b(LLIL_REG.b(v7.b[14]),LLIL_CONST.b(0x0)));' + \
+ ' LLIL_SET_REG.b(v28.b[15],LLIL_LSL.b(LLIL_REG.b(v7.b[15]),LLIL_CONST.b(0x0)))'),
+ # shl v28.2d, v6.2d, #0x2d SHL_asimdshf_R
+ (b'\xDC\x54\x6D\x4F', 'LLIL_SET_REG.q(v28.d[0],LLIL_LSL.q(LLIL_REG.q(v6.d[0]),LLIL_CONST.b(0x2D)));' + \
+ ' LLIL_SET_REG.q(v28.d[1],LLIL_LSL.q(LLIL_REG.q(v6.d[1]),LLIL_CONST.b(0x2D)))'),
+ # shl v23.4s, v12.4s, #0xe SHL_asimdshf_R
+ (b'\x97\x55\x2E\x4F', 'LLIL_SET_REG.d(v23.s[0],LLIL_LSL.d(LLIL_REG.d(v12.s[0]),LLIL_CONST.b(0xE)));' + \
+ ' LLIL_SET_REG.d(v23.s[1],LLIL_LSL.d(LLIL_REG.d(v12.s[1]),LLIL_CONST.b(0xE)));' + \
+ ' LLIL_SET_REG.d(v23.s[2],LLIL_LSL.d(LLIL_REG.d(v12.s[2]),LLIL_CONST.b(0xE)));' + \
+ ' LLIL_SET_REG.d(v23.s[3],LLIL_LSL.d(LLIL_REG.d(v12.s[3]),LLIL_CONST.b(0xE)))'),
+ # shl v26.4s, v21.4s, #0x17 SHL_asimdshf_R
+ (b'\xBA\x56\x37\x4F', 'LLIL_SET_REG.d(v26.s[0],LLIL_LSL.d(LLIL_REG.d(v21.s[0]),LLIL_CONST.b(0x17)));' + \
+ ' LLIL_SET_REG.d(v26.s[1],LLIL_LSL.d(LLIL_REG.d(v21.s[1]),LLIL_CONST.b(0x17)));' + \
+ ' LLIL_SET_REG.d(v26.s[2],LLIL_LSL.d(LLIL_REG.d(v21.s[2]),LLIL_CONST.b(0x17)));' + \
+ ' LLIL_SET_REG.d(v26.s[3],LLIL_LSL.d(LLIL_REG.d(v21.s[3]),LLIL_CONST.b(0x17)))'),
+ # shl d18, d6, #0x3e SHL_asisdshf_R
+ (b'\xD2\x54\x7E\x5F', 'LLIL_SET_REG.q(d18,LLIL_LSL.q(LLIL_REG.q(d6),LLIL_CONST.b(0x3E)))'),
+ # shl d27, d3, #0x30 SHL_asisdshf_R
+ (b'\x7B\x54\x70\x5F', 'LLIL_SET_REG.q(d27,LLIL_LSL.q(LLIL_REG.q(d3),LLIL_CONST.b(0x30)))'),
+ # shl d4, d20, #0x32 SHL_asisdshf_R
+ (b'\x84\x56\x72\x5F', 'LLIL_SET_REG.q(d4,LLIL_LSL.q(LLIL_REG.q(d20),LLIL_CONST.b(0x32)))'),
+ # shl d4, d1, #0x2f SHL_asisdshf_R
+ (b'\x24\x54\x6F\x5F', 'LLIL_SET_REG.q(d4,LLIL_LSL.q(LLIL_REG.q(d1),LLIL_CONST.b(0x2F)))'),
+ # shl d21, d19, #0x30 SHL_asisdshf_R
+ (b'\x75\x56\x70\x5F', 'LLIL_SET_REG.q(d21,LLIL_LSL.q(LLIL_REG.q(d19),LLIL_CONST.b(0x30)))'),
+ # shl d4, d24, #0x32 SHL_asisdshf_R
+ (b'\x04\x57\x72\x5F', 'LLIL_SET_REG.q(d4,LLIL_LSL.q(LLIL_REG.q(d24),LLIL_CONST.b(0x32)))'),
+ # shl d11, d27, #0x39 SHL_asisdshf_R
+ (b'\x6B\x57\x79\x5F', 'LLIL_SET_REG.q(d11,LLIL_LSL.q(LLIL_REG.q(d27),LLIL_CONST.b(0x39)))'),
+ # shl d8, d8, #0x2f SHL_asisdshf_R
+ (b'\x08\x55\x6F\x5F', 'LLIL_SET_REG.q(d8,LLIL_LSL.q(LLIL_REG.q(d8),LLIL_CONST.b(0x2F)))'),
+ # sshll v11.2d, v25.2s, #0x9 SSHLL_asimdshf_L
+ (b'\x2B\xA7\x29\x0F', 'LLIL_INTRINSIC([v11],vshll_n_s32,[LLIL_REG.o(v25),LLIL_CONST(9)])'),
+ # sshll2 v28.2d, v8.4s, #0x1d SSHLL_asimdshf_L
+ (b'\x1C\xA5\x3D\x4F', 'LLIL_INTRINSIC([v28],vshll_high_n_s32,[LLIL_REG.o(v8),LLIL_CONST(29)])'),
+ # sshll2 v27.4s, v12.8h, #0x8 SSHLL_asimdshf_L
+ (b'\x9B\xA5\x18\x4F', 'LLIL_INTRINSIC([v27],vshll_high_n_s16,[LLIL_REG.o(v12),LLIL_CONST(8)])'),
+ # sshll2 v5.8h, v27.16b, #0x1 SSHLL_asimdshf_L
+ (b'\x65\xA7\x09\x4F', 'LLIL_INTRINSIC([v5],vshll_high_n_s8,[LLIL_REG.o(v27),LLIL_CONST(1)])'),
+ # sshll2 v26.2d, v27.4s, #0x8 SSHLL_asimdshf_L
+ (b'\x7A\xA7\x28\x4F', 'LLIL_INTRINSIC([v26],vshll_high_n_s32,[LLIL_REG.o(v27),LLIL_CONST(8)])'),
+ # sshll2 v1.4s, v25.8h, #0x2 SSHLL_asimdshf_L
+ (b'\x21\xA7\x12\x4F', 'LLIL_INTRINSIC([v1],vshll_high_n_s16,[LLIL_REG.o(v25),LLIL_CONST(2)])'),
+ # sshll2 v13.2d, v22.4s, #0x1e SSHLL_asimdshf_L
+ (b'\xCD\xA6\x3E\x4F', 'LLIL_INTRINSIC([v13],vshll_high_n_s32,[LLIL_REG.o(v22),LLIL_CONST(30)])'),
+ # sshll2 v8.2d, v22.4s, #0x8 SSHLL_asimdshf_L
+ (b'\xC8\xA6\x28\x4F', 'LLIL_INTRINSIC([v8],vshll_high_n_s32,[LLIL_REG.o(v22),LLIL_CONST(8)])'),
+ # sshl v28.4h, v14.4h, v27.4h SSHL_asimdsame_only
+ (b'\xDC\x45\x7B\x0E', 'LLIL_SET_REG.w(v28.h[0],LLIL_LSL.w(LLIL_SX.w(LLIL_REG.w(v14.h[0])),LLIL_REG.b(v27.h[0])));' + \
+ ' LLIL_SET_REG.w(v28.h[1],LLIL_LSL.w(LLIL_SX.w(LLIL_REG.w(v14.h[1])),LLIL_REG.b(v27.h[1])));' + \
+ ' LLIL_SET_REG.w(v28.h[2],LLIL_LSL.w(LLIL_SX.w(LLIL_REG.w(v14.h[2])),LLIL_REG.b(v27.h[2])));' + \
+ ' LLIL_SET_REG.w(v28.h[3],LLIL_LSL.w(LLIL_SX.w(LLIL_REG.w(v14.h[3])),LLIL_REG.b(v27.h[3])))'),
+ # sshl v11.2d, v30.2d, v24.2d SSHL_asimdsame_only
+ (b'\xCB\x47\xF8\x4E', 'LLIL_SET_REG.q(v11.d[0],LLIL_LSL.q(LLIL_SX.q(LLIL_REG.q(v30.d[0])),LLIL_REG.b(v24.d[0])));' + \
+ ' LLIL_SET_REG.q(v11.d[1],LLIL_LSL.q(LLIL_SX.q(LLIL_REG.q(v30.d[1])),LLIL_REG.b(v24.d[1])))'),
+ # sshl v21.4s, v3.4s, v10.4s SSHL_asimdsame_only
+ (b'\x75\x44\xAA\x4E', 'LLIL_SET_REG.d(v21.s[0],LLIL_LSL.d(LLIL_SX.d(LLIL_REG.d(v3.s[0])),LLIL_REG.b(v10.s[0])));' + \
+ ' LLIL_SET_REG.d(v21.s[1],LLIL_LSL.d(LLIL_SX.d(LLIL_REG.d(v3.s[1])),LLIL_REG.b(v10.s[1])));' + \
+ ' LLIL_SET_REG.d(v21.s[2],LLIL_LSL.d(LLIL_SX.d(LLIL_REG.d(v3.s[2])),LLIL_REG.b(v10.s[2])));' + \
+ ' LLIL_SET_REG.d(v21.s[3],LLIL_LSL.d(LLIL_SX.d(LLIL_REG.d(v3.s[3])),LLIL_REG.b(v10.s[3])))'),
+ # sshl v22.2s, v2.2s, v1.2s SSHL_asimdsame_only
+ (b'\x56\x44\xA1\x0E', 'LLIL_SET_REG.d(v22.s[0],LLIL_LSL.d(LLIL_SX.d(LLIL_REG.d(v2.s[0])),LLIL_REG.b(v1.s[0])));' + \
+ ' LLIL_SET_REG.d(v22.s[1],LLIL_LSL.d(LLIL_SX.d(LLIL_REG.d(v2.s[1])),LLIL_REG.b(v1.s[1])))'),
+ # sshl v10.4h, v20.4h, v20.4h SSHL_asimdsame_only
+ (b'\x8A\x46\x74\x0E', 'LLIL_SET_REG.w(v10.h[0],LLIL_LSL.w(LLIL_SX.w(LLIL_REG.w(v20.h[0])),LLIL_REG.b(v20.h[0])));' + \
+ ' LLIL_SET_REG.w(v10.h[1],LLIL_LSL.w(LLIL_SX.w(LLIL_REG.w(v20.h[1])),LLIL_REG.b(v20.h[1])));' + \
+ ' LLIL_SET_REG.w(v10.h[2],LLIL_LSL.w(LLIL_SX.w(LLIL_REG.w(v20.h[2])),LLIL_REG.b(v20.h[2])));' + \
+ ' LLIL_SET_REG.w(v10.h[3],LLIL_LSL.w(LLIL_SX.w(LLIL_REG.w(v20.h[3])),LLIL_REG.b(v20.h[3])))'),
+ # sshl v0.16b, v25.16b, v12.16b SSHL_asimdsame_only
+ (b'\x20\x47\x2C\x4E', 'LLIL_SET_REG.b(v0.b[0],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[0])),LLIL_REG.b(v12.b[0])));' + \
+ ' LLIL_SET_REG.b(v0.b[1],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[1])),LLIL_REG.b(v12.b[1])));' + \
+ ' LLIL_SET_REG.b(v0.b[2],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[2])),LLIL_REG.b(v12.b[2])));' + \
+ ' LLIL_SET_REG.b(v0.b[3],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[3])),LLIL_REG.b(v12.b[3])));' + \
+ ' LLIL_SET_REG.b(v0.b[4],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[4])),LLIL_REG.b(v12.b[4])));' + \
+ ' LLIL_SET_REG.b(v0.b[5],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[5])),LLIL_REG.b(v12.b[5])));' + \
+ ' LLIL_SET_REG.b(v0.b[6],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[6])),LLIL_REG.b(v12.b[6])));' + \
+ ' LLIL_SET_REG.b(v0.b[7],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[7])),LLIL_REG.b(v12.b[7])));' + \
+ ' LLIL_SET_REG.b(v0.b[8],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[8])),LLIL_REG.b(v12.b[8])));' + \
+ ' LLIL_SET_REG.b(v0.b[9],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[9])),LLIL_REG.b(v12.b[9])));' + \
+ ' LLIL_SET_REG.b(v0.b[10],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[10])),LLIL_REG.b(v12.b[10])));' + \
+ ' LLIL_SET_REG.b(v0.b[11],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[11])),LLIL_REG.b(v12.b[11])));' + \
+ ' LLIL_SET_REG.b(v0.b[12],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[12])),LLIL_REG.b(v12.b[12])));' + \
+ ' LLIL_SET_REG.b(v0.b[13],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[13])),LLIL_REG.b(v12.b[13])));' + \
+ ' LLIL_SET_REG.b(v0.b[14],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[14])),LLIL_REG.b(v12.b[14])));' + \
+ ' LLIL_SET_REG.b(v0.b[15],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v25.b[15])),LLIL_REG.b(v12.b[15])))'),
+ # sshl v2.2d, v13.2d, v17.2d SSHL_asimdsame_only
+ (b'\xA2\x45\xF1\x4E', 'LLIL_SET_REG.q(v2.d[0],LLIL_LSL.q(LLIL_SX.q(LLIL_REG.q(v13.d[0])),LLIL_REG.b(v17.d[0])));' + \
+ ' LLIL_SET_REG.q(v2.d[1],LLIL_LSL.q(LLIL_SX.q(LLIL_REG.q(v13.d[1])),LLIL_REG.b(v17.d[1])))'),
+ # sshl v28.8b, v20.8b, v7.8b SSHL_asimdsame_only
+ (b'\x9C\x46\x27\x0E', 'LLIL_SET_REG.b(v28.b[0],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v20.b[0])),LLIL_REG.b(v7.b[0])));' + \
+ ' LLIL_SET_REG.b(v28.b[1],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v20.b[1])),LLIL_REG.b(v7.b[1])));' + \
+ ' LLIL_SET_REG.b(v28.b[2],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v20.b[2])),LLIL_REG.b(v7.b[2])));' + \
+ ' LLIL_SET_REG.b(v28.b[3],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v20.b[3])),LLIL_REG.b(v7.b[3])));' + \
+ ' LLIL_SET_REG.b(v28.b[4],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v20.b[4])),LLIL_REG.b(v7.b[4])));' + \
+ ' LLIL_SET_REG.b(v28.b[5],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v20.b[5])),LLIL_REG.b(v7.b[5])));' + \
+ ' LLIL_SET_REG.b(v28.b[6],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v20.b[6])),LLIL_REG.b(v7.b[6])));' + \
+ ' LLIL_SET_REG.b(v28.b[7],LLIL_LSL.b(LLIL_SX.b(LLIL_REG.b(v20.b[7])),LLIL_REG.b(v7.b[7])))'),
+ # sshl d29, d6, d3 SSHL_asisdsame_only
+ (b'\xDD\x44\xE3\x5E', 'LLIL_SET_REG.q(d29,LLIL_LSL.q(LLIL_SX.q(LLIL_REG.q(d6)),LLIL_REG.b(d3)))'),
+ # sshl d23, d4, d10 SSHL_asisdsame_only
+ (b'\x97\x44\xEA\x5E', 'LLIL_SET_REG.q(d23,LLIL_LSL.q(LLIL_SX.q(LLIL_REG.q(d4)),LLIL_REG.b(d10)))'),
+ # sshl d13, d12, d4 SSHL_asisdsame_only
+ (b'\x8D\x45\xE4\x5E', 'LLIL_SET_REG.q(d13,LLIL_LSL.q(LLIL_SX.q(LLIL_REG.q(d12)),LLIL_REG.b(d4)))'),
+ # sshl d16, d6, d27 SSHL_asisdsame_only
+ (b'\xD0\x44\xFB\x5E', 'LLIL_SET_REG.q(d16,LLIL_LSL.q(LLIL_SX.q(LLIL_REG.q(d6)),LLIL_REG.b(d27)))'),
+ # sshl d19, d15, d19 SSHL_asisdsame_only
+ (b'\xF3\x45\xF3\x5E', 'LLIL_SET_REG.q(d19,LLIL_LSL.q(LLIL_SX.q(LLIL_REG.q(d15)),LLIL_REG.b(d19)))'),
+ # sshl d9, d29, d6 SSHL_asisdsame_only
+ (b'\xA9\x47\xE6\x5E', 'LLIL_SET_REG.q(d9,LLIL_LSL.q(LLIL_SX.q(LLIL_REG.q(d29)),LLIL_REG.b(d6)))'),
+ # sshl d29, d12, d22 SSHL_asisdsame_only
+ (b'\x9D\x45\xF6\x5E', 'LLIL_SET_REG.q(d29,LLIL_LSL.q(LLIL_SX.q(LLIL_REG.q(d12)),LLIL_REG.b(d22)))'),
+ # sshl d17, d28, d24 SSHL_asisdsame_only
+ (b'\x91\x47\xF8\x5E', 'LLIL_SET_REG.q(d17,LLIL_LSL.q(LLIL_SX.q(LLIL_REG.q(d28)),LLIL_REG.b(d24)))'),
+ # sshr v0.2d, v23.2d, #0x3 SSHR_asimdshf_R
+ (b'\xE0\x06\x7D\x4F', 'LLIL_SET_REG.q(v0.d[0],LLIL_ASR.q(LLIL_REG.q(v23.d[0]),LLIL_CONST.b(0x3)));' + \
+ ' LLIL_SET_REG.q(v0.d[1],LLIL_ASR.q(LLIL_REG.q(v23.d[1]),LLIL_CONST.b(0x3)))'),
+ # sshr v18.4h, v12.4h, #0x5 SSHR_asimdshf_R
+ (b'\x92\x05\x1B\x0F', 'LLIL_SET_REG.w(v18.h[0],LLIL_ASR.w(LLIL_REG.w(v12.h[0]),LLIL_CONST.b(0x5)));' + \
+ ' LLIL_SET_REG.w(v18.h[1],LLIL_ASR.w(LLIL_REG.w(v12.h[1]),LLIL_CONST.b(0x5)));' + \
+ ' LLIL_SET_REG.w(v18.h[2],LLIL_ASR.w(LLIL_REG.w(v12.h[2]),LLIL_CONST.b(0x5)));' + \
+ ' LLIL_SET_REG.w(v18.h[3],LLIL_ASR.w(LLIL_REG.w(v12.h[3]),LLIL_CONST.b(0x5)))'),
+ # sshr v30.4s, v19.4s, #0xc SSHR_asimdshf_R
+ (b'\x7E\x06\x34\x4F', 'LLIL_SET_REG.d(v30.s[0],LLIL_ASR.d(LLIL_REG.d(v19.s[0]),LLIL_CONST.b(0xC)));' + \
+ ' LLIL_SET_REG.d(v30.s[1],LLIL_ASR.d(LLIL_REG.d(v19.s[1]),LLIL_CONST.b(0xC)));' + \
+ ' LLIL_SET_REG.d(v30.s[2],LLIL_ASR.d(LLIL_REG.d(v19.s[2]),LLIL_CONST.b(0xC)));' + \
+ ' LLIL_SET_REG.d(v30.s[3],LLIL_ASR.d(LLIL_REG.d(v19.s[3]),LLIL_CONST.b(0xC)))'),
+ # sshr v19.16b, v19.16b, #0x2 SSHR_asimdshf_R
+ (b'\x73\x06\x0E\x4F', 'LLIL_SET_REG.b(v19.b[0],LLIL_ASR.b(LLIL_REG.b(v19.b[0]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.b(v19.b[1],LLIL_ASR.b(LLIL_REG.b(v19.b[1]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.b(v19.b[2],LLIL_ASR.b(LLIL_REG.b(v19.b[2]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.b(v19.b[3],LLIL_ASR.b(LLIL_REG.b(v19.b[3]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.b(v19.b[4],LLIL_ASR.b(LLIL_REG.b(v19.b[4]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.b(v19.b[5],LLIL_ASR.b(LLIL_REG.b(v19.b[5]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.b(v19.b[6],LLIL_ASR.b(LLIL_REG.b(v19.b[6]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.b(v19.b[7],LLIL_ASR.b(LLIL_REG.b(v19.b[7]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.b(v19.b[8],LLIL_ASR.b(LLIL_REG.b(v19.b[8]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.b(v19.b[9],LLIL_ASR.b(LLIL_REG.b(v19.b[9]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.b(v19.b[10],LLIL_ASR.b(LLIL_REG.b(v19.b[10]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.b(v19.b[11],LLIL_ASR.b(LLIL_REG.b(v19.b[11]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.b(v19.b[12],LLIL_ASR.b(LLIL_REG.b(v19.b[12]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.b(v19.b[13],LLIL_ASR.b(LLIL_REG.b(v19.b[13]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.b(v19.b[14],LLIL_ASR.b(LLIL_REG.b(v19.b[14]),LLIL_CONST.b(0x2)));' + \
+ ' LLIL_SET_REG.b(v19.b[15],LLIL_ASR.b(LLIL_REG.b(v19.b[15]),LLIL_CONST.b(0x2)))'),
+ # sshr v21.2d, v31.2d, #0x15 SSHR_asimdshf_R
+ (b'\xF5\x07\x6B\x4F', 'LLIL_SET_REG.q(v21.d[0],LLIL_ASR.q(LLIL_REG.q(v31.d[0]),LLIL_CONST.b(0x15)));' + \
+ ' LLIL_SET_REG.q(v21.d[1],LLIL_ASR.q(LLIL_REG.q(v31.d[1]),LLIL_CONST.b(0x15)))'),
+ # sshr v6.2d, v30.2d, #0x38 SSHR_asimdshf_R
+ (b'\xC6\x07\x48\x4F', 'LLIL_SET_REG.q(v6.d[0],LLIL_ASR.q(LLIL_REG.q(v30.d[0]),LLIL_CONST.b(0x38)));' + \
+ ' LLIL_SET_REG.q(v6.d[1],LLIL_ASR.q(LLIL_REG.q(v30.d[1]),LLIL_CONST.b(0x38)))'),
+ # sshr v12.2d, v18.2d, #0x11 SSHR_asimdshf_R
+ (b'\x4C\x06\x6F\x4F', 'LLIL_SET_REG.q(v12.d[0],LLIL_ASR.q(LLIL_REG.q(v18.d[0]),LLIL_CONST.b(0x11)));' + \
+ ' LLIL_SET_REG.q(v12.d[1],LLIL_ASR.q(LLIL_REG.q(v18.d[1]),LLIL_CONST.b(0x11)))'),
+ # sshr v11.2d, v13.2d, #0x32 SSHR_asimdshf_R
+ (b'\xAB\x05\x4E\x4F', 'LLIL_SET_REG.q(v11.d[0],LLIL_ASR.q(LLIL_REG.q(v13.d[0]),LLIL_CONST.b(0x32)));' + \
+ ' LLIL_SET_REG.q(v11.d[1],LLIL_ASR.q(LLIL_REG.q(v13.d[1]),LLIL_CONST.b(0x32)))'),
+ # sshr d16, d10, #0x3b SSHR_asisdshf_R
+ (b'\x50\x05\x45\x5F', 'LLIL_SET_REG.q(d16,LLIL_ASR.q(LLIL_REG.q(d10),LLIL_CONST.b(0x3B)))'),
+ # sshr d18, d11, #0x35 SSHR_asisdshf_R
+ (b'\x72\x05\x4B\x5F', 'LLIL_SET_REG.q(d18,LLIL_ASR.q(LLIL_REG.q(d11),LLIL_CONST.b(0x35)))'),
+ # sshr d23, d5, #0x2b SSHR_asisdshf_R
+ (b'\xB7\x04\x55\x5F', 'LLIL_SET_REG.q(d23,LLIL_ASR.q(LLIL_REG.q(d5),LLIL_CONST.b(0x2B)))'),
+ # sshr d30, d14, #0xd SSHR_asisdshf_R
+ (b'\xDE\x05\x73\x5F', 'LLIL_SET_REG.q(d30,LLIL_ASR.q(LLIL_REG.q(d14),LLIL_CONST.b(0xD)))'),
+ # sshr d1, d4, #0x1c SSHR_asisdshf_R
+ (b'\x81\x04\x64\x5F', 'LLIL_SET_REG.q(d1,LLIL_ASR.q(LLIL_REG.q(d4),LLIL_CONST.b(0x1C)))'),
+ # sshr d17, d14, #0x3b SSHR_asisdshf_R
+ (b'\xD1\x05\x45\x5F', 'LLIL_SET_REG.q(d17,LLIL_ASR.q(LLIL_REG.q(d14),LLIL_CONST.b(0x3B)))'),
+ # sshr d12, d25, #0xe SSHR_asisdshf_R
+ (b'\x2C\x07\x72\x5F', 'LLIL_SET_REG.q(d12,LLIL_ASR.q(LLIL_REG.q(d25),LLIL_CONST.b(0xE)))'),
+ # sshr d27, d15, #0x38 SSHR_asisdshf_R
+ (b'\xFB\x05\x48\x5F', 'LLIL_SET_REG.q(d27,LLIL_ASR.q(LLIL_REG.q(d15),LLIL_CONST.b(0x38)))'),
+ # sxtl2 v26.2d, v3.4s SXTL_SSHLL_asimdshf_L
+ (b'\x7A\xA4\x20\x4F', 'LLIL_SET_REG.q(v26.d[0],LLIL_SX.q(LLIL_REG.d(v3.s[2])));' + \
+ ' LLIL_SET_REG.q(v26.d[1],LLIL_SX.q(LLIL_REG.d(v3.s[3])))'),
+ # sxtl v16.8h, v28.8b SXTL_SSHLL_asimdshf_L
+ (b'\x90\xA7\x08\x0F', 'LLIL_SET_REG.w(v16.h[0],LLIL_SX.w(LLIL_REG.b(v28.b[0])));' + \
+ ' LLIL_SET_REG.w(v16.h[1],LLIL_SX.w(LLIL_REG.b(v28.b[1])));' + \
+ ' LLIL_SET_REG.w(v16.h[2],LLIL_SX.w(LLIL_REG.b(v28.b[2])));' + \
+ ' LLIL_SET_REG.w(v16.h[3],LLIL_SX.w(LLIL_REG.b(v28.b[3])));' + \
+ ' LLIL_SET_REG.w(v16.h[4],LLIL_SX.w(LLIL_REG.b(v28.b[4])));' + \
+ ' LLIL_SET_REG.w(v16.h[5],LLIL_SX.w(LLIL_REG.b(v28.b[5])));' + \
+ ' LLIL_SET_REG.w(v16.h[6],LLIL_SX.w(LLIL_REG.b(v28.b[6])));' + \
+ ' LLIL_SET_REG.w(v16.h[7],LLIL_SX.w(LLIL_REG.b(v28.b[7])))'),
+ # sxtl2 v27.4s, v15.8h SXTL_SSHLL_asimdshf_L
+ (b'\xFB\xA5\x10\x4F', 'LLIL_SET_REG.d(v27.s[0],LLIL_SX.d(LLIL_REG.w(v15.h[4])));' + \
+ ' LLIL_SET_REG.d(v27.s[1],LLIL_SX.d(LLIL_REG.w(v15.h[5])));' + \
+ ' LLIL_SET_REG.d(v27.s[2],LLIL_SX.d(LLIL_REG.w(v15.h[6])));' + \
+ ' LLIL_SET_REG.d(v27.s[3],LLIL_SX.d(LLIL_REG.w(v15.h[7])))'),
+ # sxtl2 v10.8h, v7.16b SXTL_SSHLL_asimdshf_L
+ (b'\xEA\xA4\x08\x4F', 'LLIL_SET_REG.w(v10.h[0],LLIL_SX.w(LLIL_REG.b(v7.b[8])));' + \
+ ' LLIL_SET_REG.w(v10.h[1],LLIL_SX.w(LLIL_REG.b(v7.b[9])));' + \
+ ' LLIL_SET_REG.w(v10.h[2],LLIL_SX.w(LLIL_REG.b(v7.b[10])));' + \
+ ' LLIL_SET_REG.w(v10.h[3],LLIL_SX.w(LLIL_REG.b(v7.b[11])));' + \
+ ' LLIL_SET_REG.w(v10.h[4],LLIL_SX.w(LLIL_REG.b(v7.b[12])));' + \
+ ' LLIL_SET_REG.w(v10.h[5],LLIL_SX.w(LLIL_REG.b(v7.b[13])));' + \
+ ' LLIL_SET_REG.w(v10.h[6],LLIL_SX.w(LLIL_REG.b(v7.b[14])));' + \
+ ' LLIL_SET_REG.w(v10.h[7],LLIL_SX.w(LLIL_REG.b(v7.b[15])))'),
+ # sxtl2 v22.8h, v20.16b SXTL_SSHLL_asimdshf_L
+ (b'\x96\xA6\x08\x4F', 'LLIL_SET_REG.w(v22.h[0],LLIL_SX.w(LLIL_REG.b(v20.b[8])));' + \
+ ' LLIL_SET_REG.w(v22.h[1],LLIL_SX.w(LLIL_REG.b(v20.b[9])));' + \
+ ' LLIL_SET_REG.w(v22.h[2],LLIL_SX.w(LLIL_REG.b(v20.b[10])));' + \
+ ' LLIL_SET_REG.w(v22.h[3],LLIL_SX.w(LLIL_REG.b(v20.b[11])));' + \
+ ' LLIL_SET_REG.w(v22.h[4],LLIL_SX.w(LLIL_REG.b(v20.b[12])));' + \
+ ' LLIL_SET_REG.w(v22.h[5],LLIL_SX.w(LLIL_REG.b(v20.b[13])));' + \
+ ' LLIL_SET_REG.w(v22.h[6],LLIL_SX.w(LLIL_REG.b(v20.b[14])));' + \
+ ' LLIL_SET_REG.w(v22.h[7],LLIL_SX.w(LLIL_REG.b(v20.b[15])))'),
+ # sxtl2 v19.4s, v11.8h SXTL_SSHLL_asimdshf_L
+ (b'\x73\xA5\x10\x4F', 'LLIL_SET_REG.d(v19.s[0],LLIL_SX.d(LLIL_REG.w(v11.h[4])));' + \
+ ' LLIL_SET_REG.d(v19.s[1],LLIL_SX.d(LLIL_REG.w(v11.h[5])));' + \
+ ' LLIL_SET_REG.d(v19.s[2],LLIL_SX.d(LLIL_REG.w(v11.h[6])));' + \
+ ' LLIL_SET_REG.d(v19.s[3],LLIL_SX.d(LLIL_REG.w(v11.h[7])))'),
+ # sxtl2 v29.2d, v9.4s SXTL_SSHLL_asimdshf_L
+ (b'\x3D\xA5\x20\x4F', 'LLIL_SET_REG.q(v29.d[0],LLIL_SX.q(LLIL_REG.d(v9.s[2])));' + \
+ ' LLIL_SET_REG.q(v29.d[1],LLIL_SX.q(LLIL_REG.d(v9.s[3])))'),
+ # sxtl2 v22.2d, v11.4s SXTL_SSHLL_asimdshf_L
+ (b'\x76\xA5\x20\x4F', 'LLIL_SET_REG.q(v22.d[0],LLIL_SX.q(LLIL_REG.d(v11.s[2])));' + \
+ ' LLIL_SET_REG.q(v22.d[1],LLIL_SX.q(LLIL_REG.d(v11.s[3])))'),
+ # ushll v1.2d, v11.2s, #0x10 USHLL_asimdshf_L
+ (b'\x61\xA5\x30\x2F', 'LLIL_INTRINSIC([v1],vshll_n_u32,[LLIL_REG.o(v11),LLIL_CONST(16)])'),
+ # ushll v1.2d, v23.2s, #0x2 USHLL_asimdshf_L
+ (b'\xE1\xA6\x22\x2F', 'LLIL_INTRINSIC([v1],vshll_n_u32,[LLIL_REG.o(v23),LLIL_CONST(2)])'),
+ # ushll2 v25.4s, v17.8h, #0x7 USHLL_asimdshf_L
+ (b'\x39\xA6\x17\x6F', 'LLIL_INTRINSIC([v25],vshll_high_n_u16,[LLIL_REG.o(v17),LLIL_CONST(7)])'),
+ # ushll2 v13.2d, v1.4s, #0x2 USHLL_asimdshf_L
+ (b'\x2D\xA4\x22\x6F', 'LLIL_INTRINSIC([v13],vshll_high_n_u32,[LLIL_REG.o(v1),LLIL_CONST(2)])'),
+ # ushll v12.8h, v6.8b, #0x1 USHLL_asimdshf_L
+ (b'\xCC\xA4\x09\x2F', 'LLIL_INTRINSIC([v12],vshll_n_u8,[LLIL_REG.o(v6),LLIL_CONST(1)])'),
+ # ushll v31.2d, v22.2s, #0x1 USHLL_asimdshf_L
+ (b'\xDF\xA6\x21\x2F', 'LLIL_INTRINSIC([v31],vshll_n_u32,[LLIL_REG.o(v22),LLIL_CONST(1)])'),
+ # ushll2 v2.2d, v8.4s, #0x1e USHLL_asimdshf_L
+ (b'\x02\xA5\x3E\x6F', 'LLIL_INTRINSIC([v2],vshll_high_n_u32,[LLIL_REG.o(v8),LLIL_CONST(30)])'),
+ # ushll v13.2d, v3.2s, #0x10 USHLL_asimdshf_L
+ (b'\x6D\xA4\x30\x2F', 'LLIL_INTRINSIC([v13],vshll_n_u32,[LLIL_REG.o(v3),LLIL_CONST(16)])'),
+ # ushl v20.4s, v13.4s, v30.4s USHL_asimdsame_only
+ (b'\xB4\x45\xBE\x6E', 'LLIL_INTRINSIC([v20],vshlq_u32,[LLIL_REG.o(v13),LLIL_REG.o(v30)])'),
+ # ushl v6.16b, v7.16b, v2.16b USHL_asimdsame_only
+ (b'\xE6\x44\x22\x6E', 'LLIL_INTRINSIC([v6],vshlq_u8,[LLIL_REG.o(v7),LLIL_REG.o(v2)])'),
+ # ushl v30.8b, v20.8b, v1.8b USHL_asimdsame_only
+ (b'\x9E\x46\x21\x2E', 'LLIL_INTRINSIC([v30],vshl_u8,[LLIL_REG.o(v20),LLIL_REG.o(v1)])'),
+ # ushl v11.16b, v5.16b, v22.16b USHL_asimdsame_only
+ (b'\xAB\x44\x36\x6E', 'LLIL_INTRINSIC([v11],vshlq_u8,[LLIL_REG.o(v5),LLIL_REG.o(v22)])'),
+ # ushl v2.2d, v5.2d, v22.2d USHL_asimdsame_only
+ (b'\xA2\x44\xF6\x6E', 'LLIL_INTRINSIC([v2],vshlq_u64,[LLIL_REG.o(v5),LLIL_REG.o(v22)])'),
+ # ushl v4.4s, v20.4s, v20.4s USHL_asimdsame_only
+ (b'\x84\x46\xB4\x6E', 'LLIL_INTRINSIC([v4],vshlq_u32,[LLIL_REG.o(v20),LLIL_REG.o(v20)])'),
+ # ushl v9.16b, v10.16b, v29.16b USHL_asimdsame_only
+ (b'\x49\x45\x3D\x6E', 'LLIL_INTRINSIC([v9],vshlq_u8,[LLIL_REG.o(v10),LLIL_REG.o(v29)])'),
+ # ushl v25.2d, v22.2d, v23.2d USHL_asimdsame_only
+ (b'\xD9\x46\xF7\x6E', 'LLIL_INTRINSIC([v25],vshlq_u64,[LLIL_REG.o(v22),LLIL_REG.o(v23)])'),
+ # ushl d22, d15, d19 USHL_asisdsame_only
+ (b'\xF6\x45\xF3\x7E', 'LLIL_SET_REG.q(d22,LLIL_LSL.q(LLIL_REG.q(d15),LLIL_REG.b(d19)))'),
+ # ushl d15, d3, d20 USHL_asisdsame_only
+ (b'\x6F\x44\xF4\x7E', 'LLIL_SET_REG.q(d15,LLIL_LSL.q(LLIL_REG.q(d3),LLIL_REG.b(d20)))'),
+ # ushl d27, d30, d26 USHL_asisdsame_only
+ (b'\xDB\x47\xFA\x7E', 'LLIL_SET_REG.q(d27,LLIL_LSL.q(LLIL_REG.q(d30),LLIL_REG.b(d26)))'),
+ # ushl d16, d16, d11 USHL_asisdsame_only
+ (b'\x10\x46\xEB\x7E', 'LLIL_SET_REG.q(d16,LLIL_LSL.q(LLIL_REG.q(d16),LLIL_REG.b(d11)))'),
+ # ushl d1, d16, d22 USHL_asisdsame_only
+ (b'\x01\x46\xF6\x7E', 'LLIL_SET_REG.q(d1,LLIL_LSL.q(LLIL_REG.q(d16),LLIL_REG.b(d22)))'),
+ # ushl d12, d3, d29 USHL_asisdsame_only
+ (b'\x6C\x44\xFD\x7E', 'LLIL_SET_REG.q(d12,LLIL_LSL.q(LLIL_REG.q(d3),LLIL_REG.b(d29)))'),
+ # ushl d17, d26, d9 USHL_asisdsame_only
+ (b'\x51\x47\xE9\x7E', 'LLIL_SET_REG.q(d17,LLIL_LSL.q(LLIL_REG.q(d26),LLIL_REG.b(d9)))'),
+ # ushl d14, d18, d8 USHL_asisdsame_only
+ (b'\x4E\x46\xE8\x7E', 'LLIL_SET_REG.q(d14,LLIL_LSL.q(LLIL_REG.q(d18),LLIL_REG.b(d8)))'),
+ # ushr v25.4h, v11.4h, #0x4 USHR_asimdshf_R
+ (b'\x79\x05\x1C\x2F', 'LLIL_SET_REG.w(v25.h[0],LLIL_LSR.w(LLIL_REG.w(v11.h[0]),LLIL_CONST.b(0x4)));' + \
+ ' LLIL_SET_REG.w(v25.h[1],LLIL_LSR.w(LLIL_REG.w(v11.h[1]),LLIL_CONST.b(0x4)));' + \
+ ' LLIL_SET_REG.w(v25.h[2],LLIL_LSR.w(LLIL_REG.w(v11.h[2]),LLIL_CONST.b(0x4)));' + \
+ ' LLIL_SET_REG.w(v25.h[3],LLIL_LSR.w(LLIL_REG.w(v11.h[3]),LLIL_CONST.b(0x4)))'),
+ # ushr v23.2s, v29.2s, #0x8 USHR_asimdshf_R
+ (b'\xB7\x07\x38\x2F', 'LLIL_SET_REG.d(v23.s[0],LLIL_LSR.d(LLIL_REG.d(v29.s[0]),LLIL_CONST.b(0x8)));' + \
+ ' LLIL_SET_REG.d(v23.s[1],LLIL_LSR.d(LLIL_REG.d(v29.s[1]),LLIL_CONST.b(0x8)))'),
+ # ushr v21.8b, v15.8b, #0x7 USHR_asimdshf_R
+ (b'\xF5\x05\x09\x2F', 'LLIL_SET_REG.b(v21.b[0],LLIL_LSR.b(LLIL_REG.b(v15.b[0]),LLIL_CONST.b(0x7)));' + \
+ ' LLIL_SET_REG.b(v21.b[1],LLIL_LSR.b(LLIL_REG.b(v15.b[1]),LLIL_CONST.b(0x7)));' + \
+ ' LLIL_SET_REG.b(v21.b[2],LLIL_LSR.b(LLIL_REG.b(v15.b[2]),LLIL_CONST.b(0x7)));' + \
+ ' LLIL_SET_REG.b(v21.b[3],LLIL_LSR.b(LLIL_REG.b(v15.b[3]),LLIL_CONST.b(0x7)));' + \
+ ' LLIL_SET_REG.b(v21.b[4],LLIL_LSR.b(LLIL_REG.b(v15.b[4]),LLIL_CONST.b(0x7)));' + \
+ ' LLIL_SET_REG.b(v21.b[5],LLIL_LSR.b(LLIL_REG.b(v15.b[5]),LLIL_CONST.b(0x7)));' + \
+ ' LLIL_SET_REG.b(v21.b[6],LLIL_LSR.b(LLIL_REG.b(v15.b[6]),LLIL_CONST.b(0x7)));' + \
+ ' LLIL_SET_REG.b(v21.b[7],LLIL_LSR.b(LLIL_REG.b(v15.b[7]),LLIL_CONST.b(0x7)))'),
+ # ushr v13.8h, v26.8h, #0xa USHR_asimdshf_R
+ (b'\x4D\x07\x16\x6F', 'LLIL_SET_REG.w(v13.h[0],LLIL_LSR.w(LLIL_REG.w(v26.h[0]),LLIL_CONST.b(0xA)));' + \
+ ' LLIL_SET_REG.w(v13.h[1],LLIL_LSR.w(LLIL_REG.w(v26.h[1]),LLIL_CONST.b(0xA)));' + \
+ ' LLIL_SET_REG.w(v13.h[2],LLIL_LSR.w(LLIL_REG.w(v26.h[2]),LLIL_CONST.b(0xA)));' + \
+ ' LLIL_SET_REG.w(v13.h[3],LLIL_LSR.w(LLIL_REG.w(v26.h[3]),LLIL_CONST.b(0xA)));' + \
+ ' LLIL_SET_REG.w(v13.h[4],LLIL_LSR.w(LLIL_REG.w(v26.h[4]),LLIL_CONST.b(0xA)));' + \
+ ' LLIL_SET_REG.w(v13.h[5],LLIL_LSR.w(LLIL_REG.w(v26.h[5]),LLIL_CONST.b(0xA)));' + \
+ ' LLIL_SET_REG.w(v13.h[6],LLIL_LSR.w(LLIL_REG.w(v26.h[6]),LLIL_CONST.b(0xA)));' + \
+ ' LLIL_SET_REG.w(v13.h[7],LLIL_LSR.w(LLIL_REG.w(v26.h[7]),LLIL_CONST.b(0xA)))'),
+ # ushr v16.2s, v19.2s, #0x15 USHR_asimdshf_R
+ (b'\x70\x06\x2B\x2F', 'LLIL_SET_REG.d(v16.s[0],LLIL_LSR.d(LLIL_REG.d(v19.s[0]),LLIL_CONST.b(0x15)));' + \
+ ' LLIL_SET_REG.d(v16.s[1],LLIL_LSR.d(LLIL_REG.d(v19.s[1]),LLIL_CONST.b(0x15)))'),
+ # ushr v16.2s, v26.2s, #0x14 USHR_asimdshf_R
+ (b'\x50\x07\x2C\x2F', 'LLIL_SET_REG.d(v16.s[0],LLIL_LSR.d(LLIL_REG.d(v26.s[0]),LLIL_CONST.b(0x14)));' + \
+ ' LLIL_SET_REG.d(v16.s[1],LLIL_LSR.d(LLIL_REG.d(v26.s[1]),LLIL_CONST.b(0x14)))'),
+ # ushr v3.4s, v8.4s, #0x1a USHR_asimdshf_R
+ (b'\x03\x05\x26\x6F', 'LLIL_SET_REG.d(v3.s[0],LLIL_LSR.d(LLIL_REG.d(v8.s[0]),LLIL_CONST.b(0x1A)));' + \
+ ' LLIL_SET_REG.d(v3.s[1],LLIL_LSR.d(LLIL_REG.d(v8.s[1]),LLIL_CONST.b(0x1A)));' + \
+ ' LLIL_SET_REG.d(v3.s[2],LLIL_LSR.d(LLIL_REG.d(v8.s[2]),LLIL_CONST.b(0x1A)));' + \
+ ' LLIL_SET_REG.d(v3.s[3],LLIL_LSR.d(LLIL_REG.d(v8.s[3]),LLIL_CONST.b(0x1A)))'),
+ # ushr v23.2s, v6.2s, #0xf USHR_asimdshf_R
+ (b'\xD7\x04\x31\x2F', 'LLIL_SET_REG.d(v23.s[0],LLIL_LSR.d(LLIL_REG.d(v6.s[0]),LLIL_CONST.b(0xF)));' + \
+ ' LLIL_SET_REG.d(v23.s[1],LLIL_LSR.d(LLIL_REG.d(v6.s[1]),LLIL_CONST.b(0xF)))'),
+ # ushr d2, d25, #0x26 USHR_asisdshf_R
+ (b'\x22\x07\x5A\x7F', 'LLIL_SET_REG.q(d2,LLIL_LSR.q(LLIL_REG.q(d25),LLIL_CONST.b(0x26)))'),
+ # ushr d31, d13, #0x8 USHR_asisdshf_R
+ (b'\xBF\x05\x78\x7F', 'LLIL_SET_REG.q(d31,LLIL_LSR.q(LLIL_REG.q(d13),LLIL_CONST.b(0x8)))'),
+ # ushr d26, d10, #0x2 USHR_asisdshf_R
+ (b'\x5A\x05\x7E\x7F', 'LLIL_SET_REG.q(d26,LLIL_LSR.q(LLIL_REG.q(d10),LLIL_CONST.b(0x2)))'),
+ # ushr d1, d28, #0x2b USHR_asisdshf_R
+ (b'\x81\x07\x55\x7F', 'LLIL_SET_REG.q(d1,LLIL_LSR.q(LLIL_REG.q(d28),LLIL_CONST.b(0x2B)))'),
+ # ushr d2, d2, #0x3 USHR_asisdshf_R
+ (b'\x42\x04\x7D\x7F', 'LLIL_SET_REG.q(d2,LLIL_LSR.q(LLIL_REG.q(d2),LLIL_CONST.b(0x3)))'),
+ # ushr d12, d7, #0x1f USHR_asisdshf_R
+ (b'\xEC\x04\x61\x7F', 'LLIL_SET_REG.q(d12,LLIL_LSR.q(LLIL_REG.q(d7),LLIL_CONST.b(0x1F)))'),
+ # ushr d0, d14, #0x20 USHR_asisdshf_R
+ (b'\xC0\x05\x60\x7F', 'LLIL_SET_REG.q(d0,LLIL_LSR.q(LLIL_REG.q(d14),LLIL_CONST.b(0x20)))'),
+ # ushr d10, d14, #0x3f USHR_asisdshf_R
+ (b'\xCA\x05\x41\x7F', 'LLIL_SET_REG.q(d10,LLIL_LSR.q(LLIL_REG.q(d14),LLIL_CONST.b(0x3F)))'),
+ # uxtl2 v19.2d, v20.4s UXTL_USHLL_asimdshf_L
+ (b'\x93\xA6\x20\x6F', 'LLIL_SET_REG.q(v19.d[0],LLIL_ZX.q(LLIL_REG.d(v20.s[2])));' + \
+ ' LLIL_SET_REG.q(v19.d[1],LLIL_ZX.q(LLIL_REG.d(v20.s[3])))'),
+ # uxtl v2.2d, v8.2s UXTL_USHLL_asimdshf_L
+ (b'\x02\xA5\x20\x2F', 'LLIL_SET_REG.q(v2.d[0],LLIL_ZX.q(LLIL_REG.d(v8.s[0])));' + \
+ ' LLIL_SET_REG.q(v2.d[1],LLIL_ZX.q(LLIL_REG.d(v8.s[1])))'),
+ # uxtl2 v11.2d, v18.4s UXTL_USHLL_asimdshf_L
+ (b'\x4B\xA6\x20\x6F', 'LLIL_SET_REG.q(v11.d[0],LLIL_ZX.q(LLIL_REG.d(v18.s[2])));' + \
+ ' LLIL_SET_REG.q(v11.d[1],LLIL_ZX.q(LLIL_REG.d(v18.s[3])))'),
+ # uxtl v6.8h, v1.8b UXTL_USHLL_asimdshf_L
+ (b'\x26\xA4\x08\x2F', 'LLIL_SET_REG.w(v6.h[0],LLIL_ZX.w(LLIL_REG.b(v1.b[0])));' + \
+ ' LLIL_SET_REG.w(v6.h[1],LLIL_ZX.w(LLIL_REG.b(v1.b[1])));' + \
+ ' LLIL_SET_REG.w(v6.h[2],LLIL_ZX.w(LLIL_REG.b(v1.b[2])));' + \
+ ' LLIL_SET_REG.w(v6.h[3],LLIL_ZX.w(LLIL_REG.b(v1.b[3])));' + \
+ ' LLIL_SET_REG.w(v6.h[4],LLIL_ZX.w(LLIL_REG.b(v1.b[4])));' + \
+ ' LLIL_SET_REG.w(v6.h[5],LLIL_ZX.w(LLIL_REG.b(v1.b[5])));' + \
+ ' LLIL_SET_REG.w(v6.h[6],LLIL_ZX.w(LLIL_REG.b(v1.b[6])));' + \
+ ' LLIL_SET_REG.w(v6.h[7],LLIL_ZX.w(LLIL_REG.b(v1.b[7])))'),
+ # uxtl v11.8h, v29.8b UXTL_USHLL_asimdshf_L
+ (b'\xAB\xA7\x08\x2F', 'LLIL_SET_REG.w(v11.h[0],LLIL_ZX.w(LLIL_REG.b(v29.b[0])));' + \
+ ' LLIL_SET_REG.w(v11.h[1],LLIL_ZX.w(LLIL_REG.b(v29.b[1])));' + \
+ ' LLIL_SET_REG.w(v11.h[2],LLIL_ZX.w(LLIL_REG.b(v29.b[2])));' + \
+ ' LLIL_SET_REG.w(v11.h[3],LLIL_ZX.w(LLIL_REG.b(v29.b[3])));' + \
+ ' LLIL_SET_REG.w(v11.h[4],LLIL_ZX.w(LLIL_REG.b(v29.b[4])));' + \
+ ' LLIL_SET_REG.w(v11.h[5],LLIL_ZX.w(LLIL_REG.b(v29.b[5])));' + \
+ ' LLIL_SET_REG.w(v11.h[6],LLIL_ZX.w(LLIL_REG.b(v29.b[6])));' + \
+ ' LLIL_SET_REG.w(v11.h[7],LLIL_ZX.w(LLIL_REG.b(v29.b[7])))'),
+ # uxtl2 v11.8h, v10.16b UXTL_USHLL_asimdshf_L
+ (b'\x4B\xA5\x08\x6F', 'LLIL_SET_REG.w(v11.h[0],LLIL_ZX.w(LLIL_REG.b(v10.b[8])));' + \
+ ' LLIL_SET_REG.w(v11.h[1],LLIL_ZX.w(LLIL_REG.b(v10.b[9])));' + \
+ ' LLIL_SET_REG.w(v11.h[2],LLIL_ZX.w(LLIL_REG.b(v10.b[10])));' + \
+ ' LLIL_SET_REG.w(v11.h[3],LLIL_ZX.w(LLIL_REG.b(v10.b[11])));' + \
+ ' LLIL_SET_REG.w(v11.h[4],LLIL_ZX.w(LLIL_REG.b(v10.b[12])));' + \
+ ' LLIL_SET_REG.w(v11.h[5],LLIL_ZX.w(LLIL_REG.b(v10.b[13])));' + \
+ ' LLIL_SET_REG.w(v11.h[6],LLIL_ZX.w(LLIL_REG.b(v10.b[14])));' + \
+ ' LLIL_SET_REG.w(v11.h[7],LLIL_ZX.w(LLIL_REG.b(v10.b[15])))'),
+ # uxtl v9.2d, v8.2s UXTL_USHLL_asimdshf_L
+ (b'\x09\xA5\x20\x2F', 'LLIL_SET_REG.q(v9.d[0],LLIL_ZX.q(LLIL_REG.d(v8.s[0])));' + \
+ ' LLIL_SET_REG.q(v9.d[1],LLIL_ZX.q(LLIL_REG.d(v8.s[1])))'),
+ # uxtl2 v0.4s, v13.8h UXTL_USHLL_asimdshf_L
+ (b'\xA0\xA5\x10\x6F', 'LLIL_SET_REG.d(v0.s[0],LLIL_ZX.d(LLIL_REG.w(v13.h[4])));' + \
+ ' LLIL_SET_REG.d(v0.s[1],LLIL_ZX.d(LLIL_REG.w(v13.h[5])));' + \
+ ' LLIL_SET_REG.d(v0.s[2],LLIL_ZX.d(LLIL_REG.w(v13.h[6])));' + \
+ ' LLIL_SET_REG.d(v0.s[3],LLIL_ZX.d(LLIL_REG.w(v13.h[7])))'),
]
tests_fccmp_fccmpe = [
@@ -2356,95 +4154,95 @@ tests_fcmp_fcmpe = [
tests_fmov = [
# fmov w2, h17
- (b'\x22\x02\xE6\x1E', 'LLIL_SET_REG.d(w2,LLIL_FLOAT_TO_INT.d(LLIL_REG.w(h17)))'),
+ (b'\x22\x02\xE6\x1E', 'LLIL_SET_REG.d(w2,LLIL_ZX.d(LLIL_REG.w(h17)))'),
# fmov w24, h20
- (b'\x98\x02\xE6\x1E', 'LLIL_SET_REG.d(w24,LLIL_FLOAT_TO_INT.d(LLIL_REG.w(h20)))'),
+ (b'\x98\x02\xE6\x1E', 'LLIL_SET_REG.d(w24,LLIL_ZX.d(LLIL_REG.w(h20)))'),
# fmov w10, s23
- (b'\xEA\x02\x26\x1E', 'LLIL_SET_REG.d(w10,LLIL_FLOAT_TO_INT.d(LLIL_REG.d(s23)))'),
+ (b'\xEA\x02\x26\x1E', 'LLIL_SET_REG.d(w10,LLIL_ZX.d(LLIL_REG.d(s23)))'),
# fmov w12, s23
- (b'\xEC\x02\x26\x1E', 'LLIL_SET_REG.d(w12,LLIL_FLOAT_TO_INT.d(LLIL_REG.d(s23)))'),
+ (b'\xEC\x02\x26\x1E', 'LLIL_SET_REG.d(w12,LLIL_ZX.d(LLIL_REG.d(s23)))'),
# fmov x25, d31
- (b'\xF9\x03\x66\x9E', 'LLIL_SET_REG.q(x25,LLIL_FLOAT_TO_INT.q(LLIL_REG.q(d31)))'),
+ (b'\xF9\x03\x66\x9E', 'LLIL_SET_REG.q(x25,LLIL_ZX.q(LLIL_REG.q(d31)))'),
# fmov x21, d24
- (b'\x15\x03\x66\x9E', 'LLIL_SET_REG.q(x21,LLIL_FLOAT_TO_INT.q(LLIL_REG.q(d24)))'),
+ (b'\x15\x03\x66\x9E', 'LLIL_SET_REG.q(x21,LLIL_ZX.q(LLIL_REG.q(d24)))'),
# fmov x26, h11
- (b'\x7A\x01\xE6\x9E', 'LLIL_SET_REG.q(x26,LLIL_FLOAT_TO_INT.q(LLIL_REG.w(h11)))'),
+ (b'\x7A\x01\xE6\x9E', 'LLIL_SET_REG.q(x26,LLIL_ZX.q(LLIL_REG.w(h11)))'),
# fmov x21, h3
- (b'\x75\x00\xE6\x9E', 'LLIL_SET_REG.q(x21,LLIL_FLOAT_TO_INT.q(LLIL_REG.w(h3)))'),
+ (b'\x75\x00\xE6\x9E', 'LLIL_SET_REG.q(x21,LLIL_ZX.q(LLIL_REG.w(h3)))'),
# fmov x4, v28.d[1]
- (b'\x84\x03\xAE\x9E', 'LLIL_SET_REG.q(x4,LLIL_FLOAT_TO_INT.q(LLIL_REG.q(v28.d[1])))'),
+ (b'\x84\x03\xAE\x9E', 'LLIL_SET_REG.q(x4,LLIL_ZX.q(LLIL_REG.q(v28.d[1])))'),
# fmov x7, v8.d[1]
- (b'\x07\x01\xAE\x9E', 'LLIL_SET_REG.q(x7,LLIL_FLOAT_TO_INT.q(LLIL_REG.q(v8.d[1])))'),
+ (b'\x07\x01\xAE\x9E', 'LLIL_SET_REG.q(x7,LLIL_ZX.q(LLIL_REG.q(v8.d[1])))'),
# fmov d19, x0
- (b'\x13\x00\x67\x9E', 'LLIL_SET_REG.q(d19,LLIL_FLOAT_TO_INT.q(LLIL_REG.q(x0)))'),
+ (b'\x13\x00\x67\x9E', 'LLIL_SET_REG.q(d19,LLIL_INT_TO_FLOAT.q(LLIL_REG.q(x0)))'),
# fmov d8, x21
- (b'\xA8\x02\x67\x9E', 'LLIL_SET_REG.q(d8,LLIL_FLOAT_TO_INT.q(LLIL_REG.q(x21)))'),
+ (b'\xA8\x02\x67\x9E', 'LLIL_SET_REG.q(d8,LLIL_INT_TO_FLOAT.q(LLIL_REG.q(x21)))'),
# fmov d24, d27
(b'\x78\x43\x60\x1E', 'LLIL_SET_REG.q(d24,LLIL_REG.q(d27))'),
# fmov d19, d19
(b'\x73\x42\x60\x1E', 'LLIL_SET_REG.q(d19,LLIL_REG.q(d19))'),
# TODO fmov d17, #-1.9375
- (b'\x11\xF0\x7F\x1E', 'LLIL_SET_REG.q(d17,LLIL_FLOAT_CONST.q(-1.9375))'),
+ (b'\x11\xF0\x7F\x1E', 'LLIL_SET_REG.q(d17,LLIL_FLOAT_CONV.q(LLIL_FLOAT_CONST.q(-1.9375)))'),
# TODO fmov d19, #-3.125
- (b'\x13\x30\x71\x1E', 'LLIL_SET_REG.q(d19,LLIL_FLOAT_CONST.q(-3.125))'),
+ (b'\x13\x30\x71\x1E', 'LLIL_SET_REG.q(d19,LLIL_FLOAT_CONV.q(LLIL_FLOAT_CONST.q(-3.125)))'),
# fmov h28, w19
- (b'\x7C\x02\xE7\x1E', 'LLIL_SET_REG.w(h28,LLIL_FLOAT_TO_INT.w(LLIL_REG.d(w19)))'),
+ (b'\x7C\x02\xE7\x1E', 'LLIL_SET_REG.w(h28,LLIL_INT_TO_FLOAT.w(LLIL_REG.d(w19)))'),
# fmov h2, w5
- (b'\xA2\x00\xE7\x1E', 'LLIL_SET_REG.w(h2,LLIL_FLOAT_TO_INT.w(LLIL_REG.d(w5)))'),
+ (b'\xA2\x00\xE7\x1E', 'LLIL_SET_REG.w(h2,LLIL_INT_TO_FLOAT.w(LLIL_REG.d(w5)))'),
# fmov h10, x14
- (b'\xCA\x01\xE7\x9E', 'LLIL_SET_REG.w(h10,LLIL_FLOAT_TO_INT.w(LLIL_REG.q(x14)))'),
+ (b'\xCA\x01\xE7\x9E', 'LLIL_SET_REG.w(h10,LLIL_INT_TO_FLOAT.w(LLIL_REG.q(x14)))'),
# fmov h9, x29
- (b'\xA9\x03\xE7\x9E', 'LLIL_SET_REG.w(h9,LLIL_FLOAT_TO_INT.w(LLIL_REG.q(x29)))'),
+ (b'\xA9\x03\xE7\x9E', 'LLIL_SET_REG.w(h9,LLIL_INT_TO_FLOAT.w(LLIL_REG.q(x29)))'),
# fmov h6, h23
(b'\xE6\x42\xE0\x1E', 'LLIL_SET_REG.w(h6,LLIL_REG.w(h23))'),
# fmov h6, h28
(b'\x86\x43\xE0\x1E', 'LLIL_SET_REG.w(h6,LLIL_REG.w(h28))'),
# fmov h23, #-5.25
- (b'\x17\xB0\xF2\x1E', 'LLIL_SET_REG.w(h23,LLIL_FLOAT_CONST.w(3232235520))'),
+ (b'\x17\xB0\xF2\x1E', 'LLIL_SET_REG.w(h23,LLIL_FLOAT_CONV.w(LLIL_FLOAT_CONST.d(-5.25)))'),
# fmov h25, #11.0
- (b'\x19\xD0\xE4\x1E', 'LLIL_SET_REG.w(h25,LLIL_FLOAT_CONST.w(1093664768))'),
+ (b'\x19\xD0\xE4\x1E', 'LLIL_SET_REG.w(h25,LLIL_FLOAT_CONV.w(LLIL_FLOAT_CONST.d(11.0)))'),
# fmov s17, w2
- (b'\x51\x00\x27\x1E', 'LLIL_SET_REG.d(s17,LLIL_FLOAT_TO_INT.d(LLIL_REG.d(w2)))'),
+ (b'\x51\x00\x27\x1E', 'LLIL_SET_REG.d(s17,LLIL_INT_TO_FLOAT.d(LLIL_REG.d(w2)))'),
# fmov s1, wzr
- (b'\xE1\x03\x27\x1E', 'LLIL_SET_REG.d(s1,LLIL_FLOAT_TO_INT.d(LLIL_CONST.d(0x0)))'),
+ (b'\xE1\x03\x27\x1E', 'LLIL_SET_REG.d(s1,LLIL_INT_TO_FLOAT.d(LLIL_CONST.d(0x0)))'),
# fmov s4, s11
(b'\x64\x41\x20\x1E', 'LLIL_SET_REG.d(s4,LLIL_REG.d(s11))'),
# fmov s23, s2
(b'\x57\x40\x20\x1E', 'LLIL_SET_REG.d(s23,LLIL_REG.d(s2))'),
# fmov s17, #-1.5
- (b'\x11\x10\x3F\x1E', 'LLIL_SET_REG.d(s17,LLIL_FLOAT_CONST.d(-1.5))'),
+ (b'\x11\x10\x3F\x1E', 'LLIL_SET_REG.d(s17,LLIL_FLOAT_CONV.d(LLIL_FLOAT_CONST.d(-1.5)))'),
# fmov s14, #21.0
- (b'\x0E\xB0\x26\x1E', 'LLIL_SET_REG.d(s14,LLIL_FLOAT_CONST.d(21.0))'),
+ (b'\x0E\xB0\x26\x1E', 'LLIL_SET_REG.d(s14,LLIL_FLOAT_CONV.d(LLIL_FLOAT_CONST.d(21.0)))'),
# fmov v14.d[1], x26
- (b'\x4E\x03\xAF\x9E', 'LLIL_SET_REG.q(v14.d[1],LLIL_FLOAT_TO_INT.o(LLIL_REG.q(x26)))'),
+ (b'\x4E\x03\xAF\x9E', 'LLIL_SET_REG.q(v14.d[1],LLIL_REG.o(x26))'),
# fmov v28.d[1], x14
- (b'\xDC\x01\xAF\x9E', 'LLIL_SET_REG.q(v28.d[1],LLIL_FLOAT_TO_INT.o(LLIL_REG.q(x14)))'),
+ (b'\xDC\x01\xAF\x9E', 'LLIL_SET_REG.q(v28.d[1],LLIL_REG.o(x14))'),
# TODO fmov v13.2d, #-3.0 (.d in arm namespace is 64-bit, .q in binja namespce is 64-bit)
- (b'\x0D\xF5\x04\x6F', 'LLIL_SET_REG.q(v13.d[0],LLIL_FLOAT_CONST.q(-3.0));' + \
- ' LLIL_SET_REG.q(v13.d[1],LLIL_FLOAT_CONST.q(-3.0))'),
+ (b'\x0D\xF5\x04\x6F', 'LLIL_SET_REG.q(v13.d[0],LLIL_FLOAT_CONV.q(LLIL_FLOAT_CONST.q(-3.0)));' + \
+ ' LLIL_SET_REG.q(v13.d[1],LLIL_FLOAT_CONV.q(LLIL_FLOAT_CONST.q(-3.0)))'),
# TODO fmov v24.2d, #-22.0
- (b'\xD8\xF6\x05\x6F', 'LLIL_SET_REG.q(v24.d[0],LLIL_FLOAT_CONST.q(-22.0));' + \
- ' LLIL_SET_REG.q(v24.d[1],LLIL_FLOAT_CONST.q(-22.0))'),
+ (b'\xD8\xF6\x05\x6F', 'LLIL_SET_REG.q(v24.d[0],LLIL_FLOAT_CONV.q(LLIL_FLOAT_CONST.q(-22.0)));' + \
+ ' LLIL_SET_REG.q(v24.d[1],LLIL_FLOAT_CONV.q(LLIL_FLOAT_CONST.q(-22.0)))'),
# TODO fmov v29.4h, #13.5
- (b'\x7D\xFD\x01\x0F', 'LLIL_SET_REG.w(v29.h[0],LLIL_FLOAT_CONST.w(1096286208));' + \
- ' LLIL_SET_REG.w(v29.h[1],LLIL_FLOAT_CONST.w(1096286208));' + \
- ' LLIL_SET_REG.w(v29.h[2],LLIL_FLOAT_CONST.w(1096286208));' + \
- ' LLIL_SET_REG.w(v29.h[3],LLIL_FLOAT_CONST.w(1096286208))'),
+ (b'\x7D\xFD\x01\x0F', 'LLIL_SET_REG.w(v29.h[0],LLIL_FLOAT_CONV.w(LLIL_FLOAT_CONST.d(13.5)));' + \
+ ' LLIL_SET_REG.w(v29.h[1],LLIL_FLOAT_CONV.w(LLIL_FLOAT_CONST.d(13.5)));' + \
+ ' LLIL_SET_REG.w(v29.h[2],LLIL_FLOAT_CONV.w(LLIL_FLOAT_CONST.d(13.5)));' + \
+ ' LLIL_SET_REG.w(v29.h[3],LLIL_FLOAT_CONV.w(LLIL_FLOAT_CONST.d(13.5)))'),
# TODO fmov v16.8h, #-0.1953125
- (b'\x30\xFD\x06\x4F', 'LLIL_SET_REG.w(v16.h[0],LLIL_FLOAT_CONST.w(3192389632));' + \
- ' LLIL_SET_REG.w(v16.h[1],LLIL_FLOAT_CONST.w(3192389632));' + \
- ' LLIL_SET_REG.w(v16.h[2],LLIL_FLOAT_CONST.w(3192389632));' + \
- ' LLIL_SET_REG.w(v16.h[3],LLIL_FLOAT_CONST.w(3192389632));' + \
- ' LLIL_SET_REG.w(v16.h[4],LLIL_FLOAT_CONST.w(3192389632));' + \
- ' LLIL_SET_REG.w(v16.h[5],LLIL_FLOAT_CONST.w(3192389632));' + \
- ' LLIL_SET_REG.w(v16.h[6],LLIL_FLOAT_CONST.w(3192389632));' + \
- ' LLIL_SET_REG.w(v16.h[7],LLIL_FLOAT_CONST.w(3192389632))'),
+ (b'\x30\xFD\x06\x4F', 'LLIL_SET_REG.w(v16.h[0],LLIL_FLOAT_CONV.w(LLIL_FLOAT_CONST.d(-0.1953125)));' + \
+ ' LLIL_SET_REG.w(v16.h[1],LLIL_FLOAT_CONV.w(LLIL_FLOAT_CONST.d(-0.1953125)));' + \
+ ' LLIL_SET_REG.w(v16.h[2],LLIL_FLOAT_CONV.w(LLIL_FLOAT_CONST.d(-0.1953125)));' + \
+ ' LLIL_SET_REG.w(v16.h[3],LLIL_FLOAT_CONV.w(LLIL_FLOAT_CONST.d(-0.1953125)));' + \
+ ' LLIL_SET_REG.w(v16.h[4],LLIL_FLOAT_CONV.w(LLIL_FLOAT_CONST.d(-0.1953125)));' + \
+ ' LLIL_SET_REG.w(v16.h[5],LLIL_FLOAT_CONV.w(LLIL_FLOAT_CONST.d(-0.1953125)));' + \
+ ' LLIL_SET_REG.w(v16.h[6],LLIL_FLOAT_CONV.w(LLIL_FLOAT_CONST.d(-0.1953125)));' + \
+ ' LLIL_SET_REG.w(v16.h[7],LLIL_FLOAT_CONV.w(LLIL_FLOAT_CONST.d(-0.1953125)))'),
# TODO fmov v23.2s, #-6.25
- (b'\x37\xF7\x04\x0F', 'LLIL_SET_REG.d(v23.s[0],LLIL_FLOAT_CONST.d(-6.25));' + \
- ' LLIL_SET_REG.d(v23.s[1],LLIL_FLOAT_CONST.d(-6.25))'),
+ (b'\x37\xF7\x04\x0F', 'LLIL_SET_REG.d(v23.s[0],LLIL_FLOAT_CONV.d(LLIL_FLOAT_CONST.d(-6.25)));' + \
+ ' LLIL_SET_REG.d(v23.s[1],LLIL_FLOAT_CONV.d(LLIL_FLOAT_CONST.d(-6.25)))'),
# TODO fmov v13.2s, #-2.0
- (b'\x0D\xF4\x04\x0F', 'LLIL_SET_REG.d(v13.s[0],LLIL_FLOAT_CONST.d(-2.0));' + \
- ' LLIL_SET_REG.d(v13.s[1],LLIL_FLOAT_CONST.d(-2.0))'),
+ (b'\x0D\xF4\x04\x0F', 'LLIL_SET_REG.d(v13.s[0],LLIL_FLOAT_CONV.d(LLIL_FLOAT_CONST.d(-2.0)));' + \
+ ' LLIL_SET_REG.d(v13.s[1],LLIL_FLOAT_CONV.d(LLIL_FLOAT_CONST.d(-2.0)))'),
]
tests_sha = [
@@ -2517,21 +4315,21 @@ tests_rev = [
# rev16 x14, x17
(b'\x2E\x06\xC0\xDA', 'LLIL_INTRINSIC([x14],_byteswap,[LLIL_REG.q(x17)])'),
# rev16 v8.16b, v26.16b
- (b'\x48\x1B\x20\x4E', 'LLIL_INTRINSIC([v8],_byteswap,[LLIL_REG.o(v26)])'),
+ (b'\x48\x1B\x20\x4E', 'LLIL_INTRINSIC([v8],vrev16q_s8,[LLIL_REG.o(v26)])'),
# rev16 v4.8b, v27.8b
- (b'\x64\x1B\x20\x0E', 'LLIL_INTRINSIC([v4],_byteswap,[LLIL_REG.o(v27)])'),
+ (b'\x64\x1B\x20\x0E', 'LLIL_INTRINSIC([v4],vrev16_s8,[LLIL_REG.o(v27)])'),
# rev32 x29, x8
(b'\x1D\x09\xC0\xDA', 'LLIL_INTRINSIC([x29],_byteswap,[LLIL_REG.q(x8)])'),
# rev32 x18, x26
(b'\x52\x0B\xC0\xDA', 'LLIL_INTRINSIC([x18],_byteswap,[LLIL_REG.q(x26)])'),
# rev32 v18.4h, v15.4h
- (b'\xF2\x09\x60\x2E', 'LLIL_INTRINSIC([v18],_byteswap,[LLIL_REG.o(v15)])'),
+ (b'\xF2\x09\x60\x2E', 'LLIL_INTRINSIC([v18],vrev32_s16,[LLIL_REG.o(v15)])'),
# rev32 v20.8h, v26.8h
- (b'\x54\x0B\x60\x6E', 'LLIL_INTRINSIC([v20],_byteswap,[LLIL_REG.o(v26)])'),
+ (b'\x54\x0B\x60\x6E', 'LLIL_INTRINSIC([v20],vrev32q_s16,[LLIL_REG.o(v26)])'),
# rev64 v9.2s, v26.2s
- (b'\x49\x0B\xA0\x0E', 'LLIL_INTRINSIC([v9],_byteswap,[LLIL_REG.o(v26)])'),
+ (b'\x49\x0B\xA0\x0E', 'LLIL_INTRINSIC([v9],vrev64_s32,[LLIL_REG.o(v26)])'),
# rev64 v17.16b, v18.16b
- (b'\x51\x0A\x20\x4E', 'LLIL_INTRINSIC([v17],_byteswap,[LLIL_REG.o(v18)])'),
+ (b'\x51\x0A\x20\x4E', 'LLIL_INTRINSIC([v17],vrev64q_s8,[LLIL_REG.o(v18)])'),
# rev w14, w21
(b'\xAE\x0A\xC0\x5A', 'LLIL_INTRINSIC([w14],_byteswap,[LLIL_REG.d(w21)])'),
# rev w23, w3
@@ -2741,7 +4539,7 @@ tests_ld2 = [
# LD2 {V8.16B-V9.16B}, [X18]
(b'\x48\x82\x40\x4C', 'LLIL_INTRINSIC([v8],vld2q_s8,[LLIL_REG.q(x18)])'),
# LD2 {V26.2D-V27.2D}, [X0]
- (b'\x1A\x8C\x40\x4C', 'LLIL_INTRINSIC([v26],vld2q_s64,[LLIL_REG.q(x0)])')
+ (b'\x1A\x8C\x40\x4C', 'LLIL_INTRINSIC([v26],vld2q_s64,[LLIL_REG.q(x0)])'),
]
tests_st1 = [
@@ -2909,45 +4707,894 @@ tests_st1 = [
' LLIL_SET_REG.q(x29,LLIL_ADD.q(LLIL_REG.q(x29),LLIL_REG.q(x21)))'),
]
-test_cases = \
- tests_udf + \
- tests_pac + \
- tests_load_acquire_store_release + \
- tests_movk + \
- tests_mvni + \
- tests_2791 + \
- tests_ucvtf + \
- tests_ucvtf2 + \
- tests_scvtf + \
- tests_ret + \
- tests_svc_hvc_smc + \
- tests_clrex + \
- tests_xtn_xtn2 + \
- tests_dc + \
- tests_uxtl_uxtl2 + \
- tests_ldadd + \
- tests_swp + \
- tests_dup + \
- tests_stlr + \
- tests_ldnp + \
- tests_stnp + \
- tests_mov + \
- tests_movi + \
- tests_fsub + \
- tests_fadd + \
- tests_fmul + \
- tests_fcvt + \
- tests_fccmp_fccmpe + \
- tests_fcmp_fcmpe + \
- tests_fcsel + \
- tests_fmov + \
- tests_sha + \
- tests_rev + \
- tests_ld1 + \
- tests_ld2 + \
- tests_st1 + \
- tests_scvtf + \
- [
+tests_tbl = [
+ # tbl v3.16b, {v13.16b}, v17.16b TBL_asimdtbl_L1_1
+ (b'\xA3\x01\x11\x4E', 'LLIL_INTRINSIC([v3],vqtbl1q_s8,[LLIL_REG.o(v13),LLIL_REG.o(v17)])'),
+ # tbl v28.16b, {v5.16b}, v2.16b TBL_asimdtbl_L1_1
+ (b'\xBC\x00\x02\x4E', 'LLIL_INTRINSIC([v28],vqtbl1q_s8,[LLIL_REG.o(v5),LLIL_REG.o(v2)])'),
+ # tbl v30.8b, {v14.16b}, v10.8b TBL_asimdtbl_L1_1
+ (b'\xDE\x01\x0A\x0E', 'LLIL_INTRINSIC([v30],vtbl1_s8,[LLIL_REG.o(v14),LLIL_REG.o(v10)])'),
+ # tbl v20.16b, {v30.16b}, v26.16b TBL_asimdtbl_L1_1
+ (b'\xD4\x03\x1A\x4E', 'LLIL_INTRINSIC([v20],vqtbl1q_s8,[LLIL_REG.o(v30),LLIL_REG.o(v26)])'),
+ # tbl v5.8b, {v3.16b, v4.16b}, v2.8b TBL_asimdtbl_L2_2
+ (b'\x65\x20\x02\x0E', 'LLIL_INTRINSIC([v5],vtbl2_s8,[LLIL_REG.o(v4),LLIL_REG.o(v3),LLIL_REG.o(v2)])'),
+ # tbl v13.8b, {v19.16b, v20.16b}, v3.8b TBL_asimdtbl_L2_2
+ (b'\x6D\x22\x03\x0E', 'LLIL_INTRINSIC([v13],vtbl2_s8,[LLIL_REG.o(v20),LLIL_REG.o(v19),LLIL_REG.o(v3)])'),
+ # tbl v1.16b, {v19.16b, v20.16b}, v6.16b TBL_asimdtbl_L2_2
+ (b'\x61\x22\x06\x4E', 'LLIL_INTRINSIC([v1],vqtbl2q_s8,[LLIL_REG.o(v20),LLIL_REG.o(v19),LLIL_REG.o(v6)])'),
+ # tbl v17.8b, {v17.16b, v18.16b}, v20.8b TBL_asimdtbl_L2_2
+ (b'\x31\x22\x14\x0E', 'LLIL_INTRINSIC([v17],vtbl2_s8,[LLIL_REG.o(v18),LLIL_REG.o(v17),LLIL_REG.o(v20)])'),
+ # tbl v24.8b, {v9.16b, v10.16b, v11.16b}, v7.8b TBL_asimdtbl_L3_3
+ (b'\x38\x41\x07\x0E', 'LLIL_INTRINSIC([v24],vtbl3_s8,[LLIL_REG.o(v9),LLIL_REG.o(v10),LLIL_REG.o(v11),LLIL_REG.o(v7)])'),
+ # tbl v13.16b, {v0.16b, v1.16b, v2.16b}, v3.16b TBL_asimdtbl_L3_3
+ (b'\x0D\x40\x03\x4E', 'LLIL_INTRINSIC([v13],vqtbl3q_s8,[LLIL_REG.o(v0),LLIL_REG.o(v1),LLIL_REG.o(v2),LLIL_REG.o(v3)])'),
+ # tbl v1.8b, {v1.16b, v2.16b, v3.16b}, v23.8b TBL_asimdtbl_L3_3
+ (b'\x21\x40\x17\x0E', 'LLIL_INTRINSIC([v1],vtbl3_s8,[LLIL_REG.o(v1),LLIL_REG.o(v2),LLIL_REG.o(v3),LLIL_REG.o(v23)])'),
+ # tbl v3.16b, {v23.16b, v24.16b, v25.16b}, v6.16b TBL_asimdtbl_L3_3
+ (b'\xE3\x42\x06\x4E', 'LLIL_INTRINSIC([v3],vqtbl3q_s8,[LLIL_REG.o(v23),LLIL_REG.o(v24),LLIL_REG.o(v25),LLIL_REG.o(v6)])'),
+ # tbl v31.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b TBL_asimdtbl_L4_4
+ (b'\xFF\x63\x02\x0E', 'LLIL_INTRINSIC([v31],vtbl4_s8,[LLIL_REG.o(v31),LLIL_REG.b(b0),LLIL_REG.b(b1),LLIL_REG.b(b2),LLIL_REG.o(v2)])'),
+ # tbl v4.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v29.16b TBL_asimdtbl_L4_4
+ (b'\x24\x60\x1D\x4E', 'LLIL_INTRINSIC([v4],vqtbl4q_s8,[LLIL_REG.o(v1),LLIL_REG.o(v2),LLIL_REG.o(v3),LLIL_REG.o(v4),LLIL_REG.o(v29)])'),
+ # tbl v12.8b, {v11.16b, v12.16b, v13.16b, v14.16b}, v4.8b TBL_asimdtbl_L4_4
+ (b'\x6C\x61\x04\x0E', 'LLIL_INTRINSIC([v12],vtbl4_s8,[LLIL_REG.o(v11),LLIL_REG.o(v12),LLIL_REG.o(v13),LLIL_REG.o(v14),LLIL_REG.o(v4)])'),
+ # tbl v6.8b, {v0.16b, v1.16b, v2.16b, v3.16b}, v26.8b TBL_asimdtbl_L4_4
+ (b'\x06\x60\x1A\x0E', 'LLIL_INTRINSIC([v6],vtbl4_s8,[LLIL_REG.o(v0),LLIL_REG.o(v1),LLIL_REG.o(v2),LLIL_REG.o(v3),LLIL_REG.o(v26)])'),
+ # tbx v4.8b, {v2.16b}, v6.8b TBX_asimdtbl_L1_1
+ (b'\x44\x10\x06\x0E', 'LLIL_INTRINSIC([v4],vtbx1_s8,[LLIL_REG.o(v2),LLIL_REG.o(v6)])'),
+ # tbx v27.16b, {v23.16b}, v12.16b TBX_asimdtbl_L1_1
+ (b'\xFB\x12\x0C\x4E', 'LLIL_INTRINSIC([v27],vqtbx1q_s8,[LLIL_REG.o(v23),LLIL_REG.o(v12)])'),
+ # tbx v8.16b, {v13.16b}, v9.16b TBX_asimdtbl_L1_1
+ (b'\xA8\x11\x09\x4E', 'LLIL_INTRINSIC([v8],vqtbx1q_s8,[LLIL_REG.o(v13),LLIL_REG.o(v9)])'),
+ # tbx v26.16b, {v21.16b}, v25.16b TBX_asimdtbl_L1_1
+ (b'\xBA\x12\x19\x4E', 'LLIL_INTRINSIC([v26],vqtbx1q_s8,[LLIL_REG.o(v21),LLIL_REG.o(v25)])'),
+ # tbx v2.8b, {v19.16b, v20.16b}, v29.8b TBX_asimdtbl_L2_2
+ (b'\x62\x32\x1D\x0E', 'LLIL_INTRINSIC([v2],vtbx2_s8,[LLIL_REG.o(v20),LLIL_REG.o(v19),LLIL_REG.o(v29)])'),
+ # tbx v19.8b, {v19.16b, v20.16b}, v15.8b TBX_asimdtbl_L2_2
+ (b'\x73\x32\x0F\x0E', 'LLIL_INTRINSIC([v19],vtbx2_s8,[LLIL_REG.o(v20),LLIL_REG.o(v19),LLIL_REG.o(v15)])'),
+ # tbx v11.8b, {v6.16b, v7.16b}, v6.8b TBX_asimdtbl_L2_2
+ (b'\xCB\x30\x06\x0E', 'LLIL_INTRINSIC([v11],vtbx2_s8,[LLIL_REG.o(v7),LLIL_REG.o(v6),LLIL_REG.o(v6)])'),
+ # tbx v1.16b, {v14.16b, v15.16b}, v10.16b TBX_asimdtbl_L2_2
+ (b'\xC1\x31\x0A\x4E', 'LLIL_INTRINSIC([v1],vqtbx2q_s8,[LLIL_REG.o(v15),LLIL_REG.o(v14),LLIL_REG.o(v10)])'),
+ # tbx v25.16b, {v25.16b, v26.16b, v27.16b}, v5.16b TBX_asimdtbl_L3_3
+ (b'\x39\x53\x05\x4E', 'LLIL_INTRINSIC([v25],vqtbx3q_s8,[LLIL_REG.o(v25),LLIL_REG.o(v26),LLIL_REG.o(v27),LLIL_REG.o(v5)])'),
+ # tbx v8.8b, {v13.16b, v14.16b, v15.16b}, v19.8b TBX_asimdtbl_L3_3
+ (b'\xA8\x51\x13\x0E', 'LLIL_INTRINSIC([v8],vtbx3_s8,[LLIL_REG.o(v13),LLIL_REG.o(v14),LLIL_REG.o(v15),LLIL_REG.o(v19)])'),
+ # tbx v15.8b, {v16.16b, v17.16b, v18.16b}, v29.8b TBX_asimdtbl_L3_3
+ (b'\x0F\x52\x1D\x0E', 'LLIL_INTRINSIC([v15],vtbx3_s8,[LLIL_REG.o(v16),LLIL_REG.o(v17),LLIL_REG.o(v18),LLIL_REG.o(v29)])'),
+ # tbx v9.8b, {v27.16b, v28.16b, v29.16b}, v6.8b TBX_asimdtbl_L3_3
+ (b'\x69\x53\x06\x0E', 'LLIL_INTRINSIC([v9],vtbx3_s8,[LLIL_REG.o(v27),LLIL_REG.o(v28),LLIL_REG.o(v29),LLIL_REG.o(v6)])'),
+ # tbx v5.16b, {v28.16b, v29.16b, v30.16b, v31.16b}, v25.16b TBX_asimdtbl_L4_4
+ (b'\x85\x73\x19\x4E', 'LLIL_INTRINSIC([v5],vqtbx4q_s8,[LLIL_REG.o(v28),LLIL_REG.o(v29),LLIL_REG.o(v30),LLIL_REG.o(v31),LLIL_REG.o(v25)])'),
+ # tbx v8.8b, {v29.16b, v30.16b, v31.16b, v0.16b}, v3.8b TBX_asimdtbl_L4_4
+ (b'\xA8\x73\x03\x0E', 'LLIL_INTRINSIC([v8],vtbx4_s8,[LLIL_REG.o(v29),LLIL_REG.o(v30),LLIL_REG.o(v31),LLIL_REG.b(b0),LLIL_REG.o(v3)])'),
+ # tbx v14.8b, {v17.16b, v18.16b, v19.16b, v20.16b}, v12.8b TBX_asimdtbl_L4_4
+ (b'\x2E\x72\x0C\x0E', 'LLIL_INTRINSIC([v14],vtbx4_s8,[LLIL_REG.o(v17),LLIL_REG.o(v18),LLIL_REG.o(v19),LLIL_REG.o(v20),LLIL_REG.o(v12)])'),
+ # tbx v27.16b, {v13.16b, v14.16b, v15.16b, v16.16b}, v3.16b TBX_asimdtbl_L4_4
+ (b'\xBB\x71\x03\x4E', 'LLIL_INTRINSIC([v27],vqtbx4q_s8,[LLIL_REG.o(v13),LLIL_REG.o(v14),LLIL_REG.o(v15),LLIL_REG.o(v16),LLIL_REG.o(v3)])'),
+]
+
+tests_cas = [
+ # casp w28, w29, w10, w11, [x29] CASP_CP32_comswappr
+ (b'\xAA\x7F\x3C\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x29)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w29,w28),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x29),LLIL_REG_SPLIT.d(w11,w10));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w29,w28,LLIL_REG.q(temp0))'),
+ # casp w14, w15, w16, w17, [x6] CASP_CP32_comswappr
+ (b'\xD0\x7C\x2E\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x6)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w15,w14),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x6),LLIL_REG_SPLIT.d(w17,w16));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w15,w14,LLIL_REG.q(temp0))'),
+ # casp w16, w17, w12, w13, [x29] CASP_CP32_comswappr
+ (b'\xAC\x7F\x30\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x29)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w17,w16),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x29),LLIL_REG_SPLIT.d(w13,w12));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w17,w16,LLIL_REG.q(temp0))'),
+ # caspa w8, w9, w26, w27, [x11] CASPA_CP32_comswappr
+ (b'\x7A\x7D\x68\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x11)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w9,w8),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x11),LLIL_REG_SPLIT.d(w27,w26));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w9,w8,LLIL_REG.q(temp0))'),
+ # caspa w14, w15, w24, w25, [x24] CASPA_CP32_comswappr
+ (b'\x18\x7F\x6E\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x24)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w15,w14),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x24),LLIL_REG_SPLIT.d(w25,w24));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w15,w14,LLIL_REG.q(temp0))'),
+ # caspa w8, w9, w28, w29, [x14] CASPA_CP32_comswappr
+ (b'\xDC\x7D\x68\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x14)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w9,w8),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x14),LLIL_REG_SPLIT.d(w29,w28));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w9,w8,LLIL_REG.q(temp0))'),
+ # caspal w30, wzr, w6, w7, [x14] CASPAL_CP32_comswappr
+ (b'\xC6\xFD\x7E\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x14)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(wzr,w30),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x14),LLIL_REG_SPLIT.d(w7,w6));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(wzr,w30,LLIL_REG.q(temp0))'),
+ # caspal w4, w5, w20, w21, [x18] CASPAL_CP32_comswappr
+ (b'\x54\xFE\x64\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x18)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w5,w4),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x18),LLIL_REG_SPLIT.d(w21,w20));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w5,w4,LLIL_REG.q(temp0))'),
+ # caspal w16, w17, w12, w13, [x20] CASPAL_CP32_comswappr
+ (b'\x8C\xFE\x70\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x20)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w17,w16),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x20),LLIL_REG_SPLIT.d(w13,w12));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w17,w16,LLIL_REG.q(temp0))'),
+ # caspl w0, w1, w22, w23, [x4] CASPL_CP32_comswappr
+ (b'\x96\xFC\x20\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x4)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w1,w0),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x4),LLIL_REG_SPLIT.d(w23,w22));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w1,w0,LLIL_REG.q(temp0))'),
+ # caspl w12, w13, w12, w13, [x17] CASPL_CP32_comswappr
+ (b'\x2C\xFE\x2C\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x17)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w13,w12),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x17),LLIL_REG_SPLIT.d(w13,w12));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w13,w12,LLIL_REG.q(temp0))'),
+ # caspl w4, w5, w22, w23, [x22] CASPL_CP32_comswappr
+ (b'\xD6\xFE\x24\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x22)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w5,w4),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x22),LLIL_REG_SPLIT.d(w23,w22));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w5,w4,LLIL_REG.q(temp0))'),
+ # casp x14, x15, x30, xzr, [sp] CASP_CP64_comswappr
+ (b'\xFE\x7F\x2E\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(sp)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x15,x14),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(sp),LLIL_REG_SPLIT.q(xzr,x30));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x15,x14,LLIL_REG.o(temp0))'),
+ # casp x22, x23, x2, x3, [x5] CASP_CP64_comswappr
+ (b'\xA2\x7C\x36\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x5)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x23,x22),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x5),LLIL_REG_SPLIT.q(x3,x2));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x23,x22,LLIL_REG.o(temp0))'),
+ # casp x30, xzr, x16, x17, [x16] CASP_CP64_comswappr
+ (b'\x10\x7E\x3E\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x16)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(xzr,x30),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x16),LLIL_REG_SPLIT.q(x17,x16));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(xzr,x30,LLIL_REG.o(temp0))'),
+ # caspa x10, x11, x0, x1, [x15] CASPA_CP64_comswappr
+ (b'\xE0\x7D\x6A\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x15)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x11,x10),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x15),LLIL_REG_SPLIT.q(x1,x0));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x11,x10,LLIL_REG.o(temp0))'),
+ # caspa x4, x5, x14, x15, [x13] CASPA_CP64_comswappr
+ (b'\xAE\x7D\x64\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x13)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x5,x4),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x13),LLIL_REG_SPLIT.q(x15,x14));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x5,x4,LLIL_REG.o(temp0))'),
+ # caspa x14, x15, x22, x23, [x19] CASPA_CP64_comswappr
+ (b'\x76\x7E\x6E\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x19)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x15,x14),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x19),LLIL_REG_SPLIT.q(x23,x22));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x15,x14,LLIL_REG.o(temp0))'),
+ # caspal x8, x9, x28, x29, [x20] CASPAL_CP64_comswappr
+ (b'\x9C\xFE\x68\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x20)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x9,x8),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x20),LLIL_REG_SPLIT.q(x29,x28));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x9,x8,LLIL_REG.o(temp0))'),
+ # caspal x4, x5, x14, x15, [x19] CASPAL_CP64_comswappr
+ (b'\x6E\xFE\x64\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x19)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x5,x4),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x19),LLIL_REG_SPLIT.q(x15,x14));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x5,x4,LLIL_REG.o(temp0))'),
+ # caspal x4, x5, x12, x13, [x0] CASPAL_CP64_comswappr
+ (b'\x0C\xFC\x64\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x0)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x5,x4),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x0),LLIL_REG_SPLIT.q(x13,x12));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x5,x4,LLIL_REG.o(temp0))'),
+ # caspl x26, x27, x2, x3, [x18] CASPL_CP64_comswappr
+ (b'\x42\xFE\x3A\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x18)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x27,x26),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x18),LLIL_REG_SPLIT.q(x3,x2));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x27,x26,LLIL_REG.o(temp0))'),
+ # caspl x2, x3, x28, x29, [x1] CASPL_CP64_comswappr
+ (b'\x3C\xFC\x22\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x1)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x3,x2),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x1),LLIL_REG_SPLIT.q(x29,x28));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x3,x2,LLIL_REG.o(temp0))'),
+ # caspl x26, x27, x8, x9, [x16] CASPL_CP64_comswappr
+ (b'\x08\xFE\x3A\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x16)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x27,x26),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x16),LLIL_REG_SPLIT.q(x9,x8));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x27,x26,LLIL_REG.o(temp0))'),
+ # casab w23, w14, [x1] CASAB_C32_ldstexcl
+ (b'\x2E\x7C\xF7\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x1)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w23)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x1),LLIL_LOW_PART.b(LLIL_REG.d(w14)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w23,LLIL_REG.b(temp0))'),
+ # casab w15, w24, [sp] CASAB_C32_ldstexcl
+ (b'\xF8\x7F\xEF\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(sp)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w15)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(sp),LLIL_LOW_PART.b(LLIL_REG.d(w24)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w15,LLIL_REG.b(temp0))'),
+ # casab w10, w30, [x19] CASAB_C32_ldstexcl
+ (b'\x7E\x7E\xEA\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x19)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w10)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x19),LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w10,LLIL_REG.b(temp0))'),
+ # casah w5, w3, [x2] CASAH_C32_ldstexcl
+ (b'\x43\x7C\xE5\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x2)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w5)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x2),LLIL_LOW_PART.w(LLIL_REG.d(w3)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w5,LLIL_REG.w(temp0))'),
+ # casah w13, w26, [sp] CASAH_C32_ldstexcl
+ (b'\xFA\x7F\xED\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(sp)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w13)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(sp),LLIL_LOW_PART.w(LLIL_REG.d(w26)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w13,LLIL_REG.w(temp0))'),
+ # casah w3, w11, [x12] CASAH_C32_ldstexcl
+ (b'\x8B\x7D\xE3\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x12)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w3)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x12),LLIL_LOW_PART.w(LLIL_REG.d(w11)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w3,LLIL_REG.w(temp0))'),
+ # casalb w6, w7, [x25] CASALB_C32_ldstexcl
+ (b'\x27\xFF\xE6\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x25)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w6)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x25),LLIL_LOW_PART.b(LLIL_REG.d(w7)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w6,LLIL_REG.b(temp0))'),
+ # casalb w18, w9, [x15] CASALB_C32_ldstexcl
+ (b'\xE9\xFD\xF2\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x15)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w18)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x15),LLIL_LOW_PART.b(LLIL_REG.d(w9)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w18,LLIL_REG.b(temp0))'),
+ # casalb w1, w27, [x3] CASALB_C32_ldstexcl
+ (b'\x7B\xFC\xE1\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x3)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w1)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x3),LLIL_LOW_PART.b(LLIL_REG.d(w27)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w1,LLIL_REG.b(temp0))'),
+ # casalh w18, w30, [x6] CASALH_C32_ldstexcl
+ (b'\xDE\xFC\xF2\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x6)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w18)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x6),LLIL_LOW_PART.w(LLIL_REG.d(w30)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w18,LLIL_REG.w(temp0))'),
+ # casalh w0, w12, [x14] CASALH_C32_ldstexcl
+ (b'\xCC\xFD\xE0\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x14)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w0)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x14),LLIL_LOW_PART.w(LLIL_REG.d(w12)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w0,LLIL_REG.w(temp0))'),
+ # casalh w1, w5, [x27] CASALH_C32_ldstexcl
+ (b'\x65\xFF\xE1\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x27)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w1)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x27),LLIL_LOW_PART.w(LLIL_REG.d(w5)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w1,LLIL_REG.w(temp0))'),
+ # casal w13, w30, [x3] CASAL_C32_ldstexcl
+ (b'\x7E\xFC\xED\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x3)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w13),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x3),LLIL_REG.d(w30));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w13,LLIL_REG.d(temp0))'),
+ # casal w27, w22, [x0] CASAL_C32_ldstexcl
+ (b'\x16\xFC\xFB\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x0)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w27),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x0),LLIL_REG.d(w22));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w27,LLIL_REG.d(temp0))'),
+ # casal w18, w10, [x23] CASAL_C32_ldstexcl
+ (b'\xEA\xFE\xF2\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x23)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w18),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x23),LLIL_REG.d(w10));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w18,LLIL_REG.d(temp0))'),
+ # casal x18, xzr, [x15] CASAL_C64_ldstexcl
+ (b'\xFF\xFD\xF2\xC8', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x15)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG.q(x18),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x15),LLIL_CONST.q(0x0));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.q(x18,LLIL_REG.q(temp0))'),
+ # casal x22, x8, [x27] CASAL_C64_ldstexcl
+ (b'\x68\xFF\xF6\xC8', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x27)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG.q(x22),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x27),LLIL_REG.q(x8));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.q(x22,LLIL_REG.q(temp0))'),
+ # casal x16, x22, [x2] CASAL_C64_ldstexcl
+ (b'\x56\xFC\xF0\xC8', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x2)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG.q(x16),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x2),LLIL_REG.q(x22));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.q(x16,LLIL_REG.q(temp0))'),
+ # casa w17, w12, [x8] CASA_C32_ldstexcl
+ (b'\x0C\x7D\xF1\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x8)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w17),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x8),LLIL_REG.d(w12));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w17,LLIL_REG.d(temp0))'),
+ # casa w23, wzr, [x21] CASA_C32_ldstexcl
+ (b'\xBF\x7E\xF7\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x21)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w23),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x21),LLIL_CONST.d(0x0));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w23,LLIL_REG.d(temp0))'),
+ # casa w29, w28, [x13] CASA_C32_ldstexcl
+ (b'\xBC\x7D\xFD\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x13)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w29),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x13),LLIL_REG.d(w28));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w29,LLIL_REG.d(temp0))'),
+ # casa x10, xzr, [x29] CASA_C64_ldstexcl
+ (b'\xBF\x7F\xEA\xC8', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x29)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG.q(x10),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x29),LLIL_CONST.q(0x0));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.q(x10,LLIL_REG.q(temp0))'),
+ # casa x13, xzr, [x19] CASA_C64_ldstexcl
+ (b'\x7F\x7E\xED\xC8', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x19)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG.q(x13),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x19),LLIL_CONST.q(0x0));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.q(x13,LLIL_REG.q(temp0))'),
+ # casa x8, x20, [x7] CASA_C64_ldstexcl
+ (b'\xF4\x7C\xE8\xC8', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x7)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG.q(x8),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x7),LLIL_REG.q(x20));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.q(x8,LLIL_REG.q(temp0))'),
+ # casb w24, w30, [x16] CASB_C32_ldstexcl
+ (b'\x1E\x7E\xB8\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x16)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w24)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x16),LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w24,LLIL_REG.b(temp0))'),
+ # casb w22, w30, [x26] CASB_C32_ldstexcl
+ (b'\x5E\x7F\xB6\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x26)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w22)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x26),LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w22,LLIL_REG.b(temp0))'),
+ # casb w14, w20, [x11] CASB_C32_ldstexcl
+ (b'\x74\x7D\xAE\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x11)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w14)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x11),LLIL_LOW_PART.b(LLIL_REG.d(w20)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w14,LLIL_REG.b(temp0))'),
+ # cash w3, w23, [x29] CASH_C32_ldstexcl
+ (b'\xB7\x7F\xA3\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x29)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w3)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x29),LLIL_LOW_PART.w(LLIL_REG.d(w23)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w3,LLIL_REG.w(temp0))'),
+ # cash w21, w0, [x28] CASH_C32_ldstexcl
+ (b'\x80\x7F\xB5\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x28)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w21)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x28),LLIL_LOW_PART.w(LLIL_REG.d(w0)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w21,LLIL_REG.w(temp0))'),
+ # cash w8, w26, [x3] CASH_C32_ldstexcl
+ (b'\x7A\x7C\xA8\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x3)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w8)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x3),LLIL_LOW_PART.w(LLIL_REG.d(w26)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w8,LLIL_REG.w(temp0))'),
+ # caslb w14, w6, [x13] CASLB_C32_ldstexcl
+ (b'\xA6\xFD\xAE\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x13)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w14)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x13),LLIL_LOW_PART.b(LLIL_REG.d(w6)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w14,LLIL_REG.b(temp0))'),
+ # caslb w21, w0, [x14] CASLB_C32_ldstexcl
+ (b'\xC0\xFD\xB5\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x14)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w21)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x14),LLIL_LOW_PART.b(LLIL_REG.d(w0)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w21,LLIL_REG.b(temp0))'),
+ # caslb w19, w17, [x22] CASLB_C32_ldstexcl
+ (b'\xD1\xFE\xB3\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x22)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w19)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x22),LLIL_LOW_PART.b(LLIL_REG.d(w17)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w19,LLIL_REG.b(temp0))'),
+ # caslh w24, w10, [x24] CASLH_C32_ldstexcl
+ (b'\x0A\xFF\xB8\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x24)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w24)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x24),LLIL_LOW_PART.w(LLIL_REG.d(w10)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w24,LLIL_REG.w(temp0))'),
+ # caslh w5, w11, [x15] CASLH_C32_ldstexcl
+ (b'\xEB\xFD\xA5\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x15)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w5)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x15),LLIL_LOW_PART.w(LLIL_REG.d(w11)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w5,LLIL_REG.w(temp0))'),
+ # caslh w16, w28, [x27] CASLH_C32_ldstexcl
+ (b'\x7C\xFF\xB0\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x27)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w16)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x27),LLIL_LOW_PART.w(LLIL_REG.d(w28)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w16,LLIL_REG.w(temp0))'),
+ # casl wzr, w23, [x3] CASL_C32_ldstexcl
+ (b'\x77\xFC\xBF\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x3)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_CONST.d(0x0),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x3),LLIL_REG.d(w23));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_REG.d(temp0)'),
+ # casl w27, w6, [x30] CASL_C32_ldstexcl
+ (b'\xC6\xFF\xBB\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x30)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w27),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x30),LLIL_REG.d(w6));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w27,LLIL_REG.d(temp0))'),
+ # casl w27, w25, [x14] CASL_C32_ldstexcl
+ (b'\xD9\xFD\xBB\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x14)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w27),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x14),LLIL_REG.d(w25));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w27,LLIL_REG.d(temp0))'),
+ # casl x20, x12, [x26] CASL_C64_ldstexcl
+ (b'\x4C\xFF\xB4\xC8', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x26)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG.q(x20),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x26),LLIL_REG.q(x12));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.q(x20,LLIL_REG.q(temp0))'),
+ # casl x8, x30, [x30] CASL_C64_ldstexcl
+ (b'\xDE\xFF\xA8\xC8', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x30)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG.q(x8),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x30),LLIL_REG.q(x30));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.q(x8,LLIL_REG.q(temp0))'),
+ # casl x11, x14, [x5] CASL_C64_ldstexcl
+ (b'\xAE\xFC\xAB\xC8', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x5)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG.q(x11),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x5),LLIL_REG.q(x14));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.q(x11,LLIL_REG.q(temp0))'),
+ # caspal w28, w29, w24, w25, [x17] CASPAL_CP32_ldstexcl
+ (b'\x38\xFE\x7C\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x17)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w29,w28),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x17),LLIL_REG_SPLIT.d(w25,w24));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w29,w28,LLIL_REG.q(temp0))'),
+ # caspal w2, w3, w10, w11, [x12] CASPAL_CP32_ldstexcl
+ (b'\x8A\xFD\x62\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x12)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w3,w2),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x12),LLIL_REG_SPLIT.d(w11,w10));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w3,w2,LLIL_REG.q(temp0))'),
+ # caspal w12, w13, w14, w15, [x1] CASPAL_CP32_ldstexcl
+ (b'\x2E\xFC\x6C\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x1)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w13,w12),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x1),LLIL_REG_SPLIT.d(w15,w14));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w13,w12,LLIL_REG.q(temp0))'),
+ # caspal x6, x7, x4, x5, [x25] CASPAL_CP64_ldstexcl
+ (b'\x24\xFF\x66\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x25)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x7,x6),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x25),LLIL_REG_SPLIT.q(x5,x4));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x7,x6,LLIL_REG.o(temp0))'),
+ # caspal x2, x3, x14, x15, [x13] CASPAL_CP64_ldstexcl
+ (b'\xAE\xFD\x62\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x13)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x3,x2),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x13),LLIL_REG_SPLIT.q(x15,x14));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x3,x2,LLIL_REG.o(temp0))'),
+ # caspal x26, x27, x2, x3, [x26] CASPAL_CP64_ldstexcl
+ (b'\x42\xFF\x7A\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x26)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x27,x26),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x26),LLIL_REG_SPLIT.q(x3,x2));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x27,x26,LLIL_REG.o(temp0))'),
+ # caspa w26, w27, w4, w5, [x13] CASPA_CP32_ldstexcl
+ (b'\xA4\x7D\x7A\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x13)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w27,w26),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x13),LLIL_REG_SPLIT.d(w5,w4));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w27,w26,LLIL_REG.q(temp0))'),
+ # caspa w10, w11, w8, w9, [x25] CASPA_CP32_ldstexcl
+ (b'\x28\x7F\x6A\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x25)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w11,w10),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x25),LLIL_REG_SPLIT.d(w9,w8));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w11,w10,LLIL_REG.q(temp0))'),
+ # caspa w8, w9, w10, w11, [x9] CASPA_CP32_ldstexcl
+ (b'\x2A\x7D\x68\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x9)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w9,w8),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x9),LLIL_REG_SPLIT.d(w11,w10));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w9,w8,LLIL_REG.q(temp0))'),
+ # caspa x30, xzr, x16, x17, [x8] CASPA_CP64_ldstexcl
+ (b'\x10\x7D\x7E\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x8)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(xzr,x30),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x8),LLIL_REG_SPLIT.q(x17,x16));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(xzr,x30,LLIL_REG.o(temp0))'),
+ # caspa x6, x7, x20, x21, [x8] CASPA_CP64_ldstexcl
+ (b'\x14\x7D\x66\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x8)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x7,x6),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x8),LLIL_REG_SPLIT.q(x21,x20));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x7,x6,LLIL_REG.o(temp0))'),
+ # caspa x12, x13, x26, x27, [x12] CASPA_CP64_ldstexcl
+ (b'\x9A\x7D\x6C\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x12)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x13,x12),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x12),LLIL_REG_SPLIT.q(x27,x26));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x13,x12,LLIL_REG.o(temp0))'),
+ # caspl w18, w19, w2, w3, [x16] CASPL_CP32_ldstexcl
+ (b'\x02\xFE\x32\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x16)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w19,w18),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x16),LLIL_REG_SPLIT.d(w3,w2));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w19,w18,LLIL_REG.q(temp0))'),
+ # caspl w12, w13, w18, w19, [x25] CASPL_CP32_ldstexcl
+ (b'\x32\xFF\x2C\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x25)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w13,w12),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x25),LLIL_REG_SPLIT.d(w19,w18));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w13,w12,LLIL_REG.q(temp0))'),
+ # caspl w6, w7, w12, w13, [x7] CASPL_CP32_ldstexcl
+ (b'\xEC\xFC\x26\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x7)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w7,w6),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x7),LLIL_REG_SPLIT.d(w13,w12));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w7,w6,LLIL_REG.q(temp0))'),
+ # caspl x26, x27, x4, x5, [x4] CASPL_CP64_ldstexcl
+ (b'\x84\xFC\x3A\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x4)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x27,x26),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x4),LLIL_REG_SPLIT.q(x5,x4));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x27,x26,LLIL_REG.o(temp0))'),
+ # caspl x26, x27, x24, x25, [x8] CASPL_CP64_ldstexcl
+ (b'\x18\xFD\x3A\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x8)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x27,x26),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x8),LLIL_REG_SPLIT.q(x25,x24));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x27,x26,LLIL_REG.o(temp0))'),
+ # caspl x6, x7, x2, x3, [x3] CASPL_CP64_ldstexcl
+ (b'\x62\xFC\x26\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x3)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x7,x6),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x3),LLIL_REG_SPLIT.q(x3,x2));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x7,x6,LLIL_REG.o(temp0))'),
+ # casp w28, w29, w4, w5, [x3] CASP_CP32_ldstexcl
+ (b'\x64\x7C\x3C\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x3)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w29,w28),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x3),LLIL_REG_SPLIT.d(w5,w4));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w29,w28,LLIL_REG.q(temp0))'),
+ # casp w2, w3, w16, w17, [x17] CASP_CP32_ldstexcl
+ (b'\x30\x7E\x22\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x17)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w3,w2),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x17),LLIL_REG_SPLIT.d(w17,w16));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w3,w2,LLIL_REG.q(temp0))'),
+ # casp w2, w3, w30, wzr, [x3] CASP_CP32_ldstexcl
+ (b'\x7E\x7C\x22\x08', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x3)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG_SPLIT.d(w3,w2),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x3),LLIL_REG_SPLIT.d(wzr,w30));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.q(w3,w2,LLIL_REG.q(temp0))'),
+ # casp x2, x3, x10, x11, [x24] CASP_CP64_ldstexcl
+ (b'\x0A\x7F\x22\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x24)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x3,x2),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x24),LLIL_REG_SPLIT.q(x11,x10));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x3,x2,LLIL_REG.o(temp0))'),
+ # casp x24, x25, x10, x11, [x19] CASP_CP64_ldstexcl
+ (b'\x6A\x7E\x38\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x19)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x25,x24),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x19),LLIL_REG_SPLIT.q(x11,x10));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x25,x24,LLIL_REG.o(temp0))'),
+ # casp x14, x15, x12, x13, [x11] CASP_CP64_ldstexcl
+ (b'\x6C\x7D\x2E\x48', 'LLIL_SET_REG.o(temp0,LLIL_LOAD.o(LLIL_REG.q(x11)));' + \
+ ' LLIL_IF(LLIL_CMP_E.o(LLIL_REG_SPLIT.q(x15,x14),LLIL_REG.o(temp0)),2,4);' + \
+ ' LLIL_STORE.o(LLIL_REG.q(x11),LLIL_REG_SPLIT.q(x13,x12));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG_SPLIT.o(x15,x14,LLIL_REG.o(temp0))'),
+ # cas w22, w27, [x25] CAS_C32_ldstexcl
+ (b'\x3B\x7F\xB6\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x25)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w22),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x25),LLIL_REG.d(w27));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w22,LLIL_REG.d(temp0))'),
+ # cas w13, w0, [x22] CAS_C32_ldstexcl
+ (b'\xC0\x7E\xAD\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x22)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w13),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x22),LLIL_REG.d(w0));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w13,LLIL_REG.d(temp0))'),
+ # cas w8, w5, [x28] CAS_C32_ldstexcl
+ (b'\x85\x7F\xA8\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x28)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w8),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x28),LLIL_REG.d(w5));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w8,LLIL_REG.d(temp0))'),
+ # cas x27, x21, [x16] CAS_C64_ldstexcl
+ (b'\x15\x7E\xBB\xC8', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x16)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG.q(x27),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x16),LLIL_REG.q(x21));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.q(x27,LLIL_REG.q(temp0))'),
+ # cas xzr, xzr, [x16] CAS_C64_ldstexcl
+ (b'\x1F\x7E\xBF\xC8', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x16)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_CONST.q(0x0),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x16),LLIL_CONST.q(0x0));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_REG.q(temp0)'),
+ # cas x8, x23, [x1] CAS_C64_ldstexcl
+ (b'\x37\x7C\xA8\xC8', 'LLIL_SET_REG.q(temp0,LLIL_LOAD.q(LLIL_REG.q(x1)));' + \
+ ' LLIL_IF(LLIL_CMP_E.q(LLIL_REG.q(x8),LLIL_REG.q(temp0)),2,4);' + \
+ ' LLIL_STORE.q(LLIL_REG.q(x1),LLIL_REG.q(x23));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.q(x8,LLIL_REG.q(temp0))'),
+]
+
+tests_umul_uadd = [
+ # uaddlv h21, v18.8b UADDLV_asimdall_only
+ (b'\x55\x3A\x30\x2E', 'LLIL_INTRINSIC([h21],vaddlv_u8,[LLIL_REG.o(v18)])'),
+ # uaddlv h18, v4.8b UADDLV_asimdall_only
+ (b'\x92\x38\x30\x2E', 'LLIL_INTRINSIC([h18],vaddlv_u8,[LLIL_REG.o(v4)])'),
+ # uaddlv s0, v7.8h UADDLV_asimdall_only
+ (b'\xE0\x38\x70\x6E', 'LLIL_INTRINSIC([s0],vaddlvq_u16,[LLIL_REG.o(v7)])'),
+ # uaddl v13.8h, v22.8b, v22.8b UADDL_asimddiff_L
+ (b'\xCD\x02\x36\x2E', 'LLIL_INTRINSIC([v13],vaddl_u8,[LLIL_REG.o(v22),LLIL_REG.o(v22)])'),
+ # uaddl v30.4s, v7.4h, v24.4h UADDL_asimddiff_L
+ (b'\xFE\x00\x78\x2E', 'LLIL_INTRINSIC([v30],vaddl_u16,[LLIL_REG.o(v7),LLIL_REG.o(v24)])'),
+ # uaddl v14.2d, v18.2s, v24.2s UADDL_asimddiff_L
+ (b'\x4E\x02\xB8\x2E', 'LLIL_INTRINSIC([v14],vaddl_u32,[LLIL_REG.o(v18),LLIL_REG.o(v24)])'),
+ # uaddw2 v22.2d, v16.2d, v7.4s UADDW_asimddiff_W
+ (b'\x16\x12\xA7\x6E', 'LLIL_INTRINSIC([v22],vaddw_high_u32,[LLIL_REG.o(v16),LLIL_REG.o(v7)])'),
+ # uaddw2 v30.2d, v0.2d, v2.4s UADDW_asimddiff_W
+ (b'\x1E\x10\xA2\x6E', 'LLIL_INTRINSIC([v30],vaddw_high_u32,[LLIL_REG.o(v0),LLIL_REG.o(v2)])'),
+ # uaddw v13.2d, v7.2d, v25.2s UADDW_asimddiff_W
+ (b'\xED\x10\xB9\x2E', 'LLIL_INTRINSIC([v13],vaddw_u32,[LLIL_REG.o(v7),LLIL_REG.o(v25)])'),
+ # umulh x2, x10, x29 UMULH_64_dp_3src
+ (b'\x42\x55\xDD\x9B', 'LLIL_SET_REG.q(x2,LLIL_LOW_PART.q(LLIL_LSR.o(LLIL_MULU_DP.q(LLIL_REG.q(x10),LLIL_REG.q(x29)),LLIL_CONST.b(0x40))))'),
+ # umulh x1, x23, x27 UMULH_64_dp_3src
+ (b'\xE1\x66\xDB\x9B', 'LLIL_SET_REG.q(x1,LLIL_LOW_PART.q(LLIL_LSR.o(LLIL_MULU_DP.q(LLIL_REG.q(x23),LLIL_REG.q(x27)),LLIL_CONST.b(0x40))))'),
+ # umulh x3, x12, x3 UMULH_64_dp_3src
+ (b'\x83\x49\xC3\x9B', 'LLIL_SET_REG.q(x3,LLIL_LOW_PART.q(LLIL_LSR.o(LLIL_MULU_DP.q(LLIL_REG.q(x12),LLIL_REG.q(x3)),LLIL_CONST.b(0x40))))'),
+ # umull x3, w24, w16 UMULL_UMADDL_64WA_dp_3src
+ (b'\x03\x7F\xB0\x9B', 'LLIL_SET_REG.q(x3,LLIL_MULU_DP.q(LLIL_REG.d(w24),LLIL_REG.d(w16)))'),
+ # umull x17, w1, w16 UMULL_UMADDL_64WA_dp_3src
+ (b'\x31\x7C\xB0\x9B', 'LLIL_SET_REG.q(x17,LLIL_MULU_DP.q(LLIL_REG.d(w1),LLIL_REG.d(w16)))'),
+ # umull x29, w19, w2 UMULL_UMADDL_64WA_dp_3src
+ (b'\x7D\x7E\xA2\x9B', 'LLIL_SET_REG.q(x29,LLIL_MULU_DP.q(LLIL_REG.d(w19),LLIL_REG.d(w2)))'),
+ # umull v27.2d, v28.2s, v8.2s UMULL_asimddiff_L
+ (b'\x9B\xC3\xA8\x2E', 'LLIL_SET_REG.o(v27,LLIL_MULU_DP.o(LLIL_REG.o(v28),LLIL_REG.o(v8)))'),
+ # umull2 v12.4s, v14.8h, v26.8h UMULL_asimddiff_L
+ (b'\xCC\xC1\x7A\x6E', 'LLIL_INTRINSIC([v12],vmull_high_u16,[LLIL_REG.o(v14),LLIL_REG.o(v26)])'),
+ # umull v8.8h, v4.8b, v14.8b UMULL_asimddiff_L
+ (b'\x88\xC0\x2E\x2E', 'LLIL_SET_REG.o(v8,LLIL_MULU_DP.o(LLIL_REG.o(v4),LLIL_REG.o(v14)))'),
+ # umull2 v26.2d, v6.4s, v5.s[0] UMULL_asimdelem_L
+ (b'\xDA\xA0\x85\x6F', 'LLIL_INTRINSIC([v26],vmull_high_laneq_u32,[LLIL_REG.o(v6),LLIL_REG.o(v5),LLIL_CONST.b(0x0)])'),
+ # umull2 v19.2d, v29.4s, v18.s[1] UMULL_asimdelem_L
+ (b'\xB3\xA3\xB2\x6F', 'LLIL_INTRINSIC([v19],vmull_high_laneq_u32,[LLIL_REG.o(v29),LLIL_REG.o(v18),LLIL_CONST.b(0x1)])'),
+ # umull2 v3.2d, v15.4s, v14.s[2] UMULL_asimdelem_L
+ (b'\xE3\xA9\x8E\x6F', 'LLIL_INTRINSIC([v3],vmull_high_laneq_u32,[LLIL_REG.o(v15),LLIL_REG.o(v14),LLIL_CONST.b(0x2)])'),
+]
+
+tests_smov = [
+ # smov w2, v23.h[1] SMOV_asimdins_W_w
+ (b'\xE2\x2E\x06\x0E', 'LLIL_SET_REG.d(w2,LLIL_SX.d(LLIL_REG.w(v23.h[1])))'),
+ # smov w9, v0.b[14] SMOV_asimdins_W_w
+ (b'\x09\x2C\x1D\x0E', 'LLIL_SET_REG.d(w9,LLIL_SX.d(LLIL_REG.b(v0.b[14])))'),
+ # smov w27, v31.b[14] SMOV_asimdins_W_w
+ (b'\xFB\x2F\x1D\x0E', 'LLIL_SET_REG.d(w27,LLIL_SX.d(LLIL_REG.b(v31.b[14])))'),
+ # smov w9, v9.b[6] SMOV_asimdins_W_w
+ (b'\x29\x2D\x0D\x0E', 'LLIL_SET_REG.d(w9,LLIL_SX.d(LLIL_REG.b(v9.b[6])))'),
+ # smov x25, v30.b[13] SMOV_asimdins_X_x
+ (b'\xD9\x2F\x1B\x4E', 'LLIL_SET_REG.q(x25,LLIL_SX.q(LLIL_REG.b(v30.b[13])))'),
+ # smov x11, v4.s[3] SMOV_asimdins_X_x
+ (b'\x8B\x2C\x1C\x4E', 'LLIL_SET_REG.q(x11,LLIL_SX.q(LLIL_REG.d(v4.s[3])))'),
+ # smov x27, v18.b[11] SMOV_asimdins_X_x
+ (b'\x5B\x2E\x17\x4E', 'LLIL_SET_REG.q(x27,LLIL_SX.q(LLIL_REG.b(v18.b[11])))'),
+ # smov xzr, v6.b[3] SMOV_asimdins_X_x
+ (b'\xDF\x2C\x07\x4E', 'LLIL_SX.q(LLIL_REG.b(v6.b[3]))'),
+]
+
+tests_raddhn_rshrn = [
+ # raddhn2 v20.16b, v7.8h, v13.8h RADDHN_asimddiff_N
+ (b'\xF4\x40\x2D\x6E', 'LLIL_INTRINSIC([v20],vraddhn_high_u16,[LLIL_REG.o(v7),LLIL_REG.o(v13)])'),
+ # raddhn2 v9.16b, v6.8h, v26.8h RADDHN_asimddiff_N
+ (b'\xC9\x40\x3A\x6E', 'LLIL_INTRINSIC([v9],vraddhn_high_u16,[LLIL_REG.o(v6),LLIL_REG.o(v26)])'),
+ # raddhn v28.2s, v10.2d, v19.2d RADDHN_asimddiff_N
+ (b'\x5C\x41\xB3\x2E', 'LLIL_INTRINSIC([v28],vraddhn_u64,[LLIL_REG.o(v10),LLIL_REG.o(v19)])'),
+ # raddhn2 v22.16b, v26.8h, v7.8h RADDHN_asimddiff_N
+ (b'\x56\x43\x27\x6E', 'LLIL_INTRINSIC([v22],vraddhn_high_u16,[LLIL_REG.o(v26),LLIL_REG.o(v7)])'),
+ # rshrn v8.8b, v11.8h, #0x5 RSHRN_asimdshf_N
+ (b'\x68\x8D\x0B\x0F', 'LLIL_INTRINSIC([v8],vrshrn_n_u16,[LLIL_REG.o(v11),LLIL_CONST(5)])'),
+ # rshrn2 v10.8h, v28.4s, #0x6 RSHRN_asimdshf_N
+ (b'\x8A\x8F\x1A\x4F', 'LLIL_INTRINSIC([v10],vrshrn_high_n_u32,[LLIL_REG.o(v28),LLIL_CONST(6)])'),
+ # rshrn2 v13.8h, v12.4s, #0x2 RSHRN_asimdshf_N
+ (b'\x8D\x8D\x1E\x4F', 'LLIL_INTRINSIC([v13],vrshrn_high_n_u32,[LLIL_REG.o(v12),LLIL_CONST(2)])'),
+ # rshrn2 v27.4s, v29.2d, #0x12 RSHRN_asimdshf_N
+ (b'\xBB\x8F\x2E\x4F', 'LLIL_INTRINSIC([v27],vrshrn_high_n_u64,[LLIL_REG.o(v29),LLIL_CONST(18)])'),
+]
+
+tests_ngc_sbc = [
+ # ngcs w17, w21 NGCS_SBCS_32_addsub_carry
+ (b'\xF1\x03\x15\x7A', 'LLIL_SET_REG.d(w17,LLIL_SBB.d{*}(LLIL_CONST.d(0x0),LLIL_REG.d(w21),LLIL_NOT(LLIL_FLAG(c))))'),
+ # ngcs w2, w18 NGCS_SBCS_32_addsub_carry
+ (b'\xE2\x03\x12\x7A', 'LLIL_SET_REG.d(w2,LLIL_SBB.d{*}(LLIL_CONST.d(0x0),LLIL_REG.d(w18),LLIL_NOT(LLIL_FLAG(c))))'),
+ # ngcs w30, w18 NGCS_SBCS_32_addsub_carry
+ (b'\xFE\x03\x12\x7A', 'LLIL_SET_REG.d(w30,LLIL_SBB.d{*}(LLIL_CONST.d(0x0),LLIL_REG.d(w18),LLIL_NOT(LLIL_FLAG(c))))'),
+ # ngcs w20, w1 NGCS_SBCS_32_addsub_carry
+ (b'\xF4\x03\x01\x7A', 'LLIL_SET_REG.d(w20,LLIL_SBB.d{*}(LLIL_CONST.d(0x0),LLIL_REG.d(w1),LLIL_NOT(LLIL_FLAG(c))))'),
+ # ngcs x17, x7 NGCS_SBCS_64_addsub_carry
+ (b'\xF1\x03\x07\xFA', 'LLIL_SET_REG.q(x17,LLIL_SBB.q{*}(LLIL_CONST.q(0x0),LLIL_REG.q(x7),LLIL_NOT(LLIL_FLAG(c))))'),
+ # ngcs x19, x24 NGCS_SBCS_64_addsub_carry
+ (b'\xF3\x03\x18\xFA', 'LLIL_SET_REG.q(x19,LLIL_SBB.q{*}(LLIL_CONST.q(0x0),LLIL_REG.q(x24),LLIL_NOT(LLIL_FLAG(c))))'),
+ # ngcs x3, x29 NGCS_SBCS_64_addsub_carry
+ (b'\xE3\x03\x1D\xFA', 'LLIL_SET_REG.q(x3,LLIL_SBB.q{*}(LLIL_CONST.q(0x0),LLIL_REG.q(x29),LLIL_NOT(LLIL_FLAG(c))))'),
+ # ngcs xzr, x13 NGCS_SBCS_64_addsub_carry
+ (b'\xFF\x03\x0D\xFA', 'LLIL_SBB.q{*}(LLIL_CONST.q(0x0),LLIL_REG.q(x13),LLIL_NOT(LLIL_FLAG(c)))'),
+ # ngc w8, w22 NGC_SBC_32_addsub_carry
+ (b'\xE8\x03\x16\x5A', 'LLIL_SET_REG.d(w8,LLIL_SBB.d(LLIL_CONST.d(0x0),LLIL_REG.d(w22),LLIL_NOT(LLIL_FLAG(c))))'),
+ # ngc w30, w0 NGC_SBC_32_addsub_carry
+ (b'\xFE\x03\x00\x5A', 'LLIL_SET_REG.d(w30,LLIL_SBB.d(LLIL_CONST.d(0x0),LLIL_REG.d(w0),LLIL_NOT(LLIL_FLAG(c))))'),
+ # ngc w9, w15 NGC_SBC_32_addsub_carry
+ (b'\xE9\x03\x0F\x5A', 'LLIL_SET_REG.d(w9,LLIL_SBB.d(LLIL_CONST.d(0x0),LLIL_REG.d(w15),LLIL_NOT(LLIL_FLAG(c))))'),
+ # ngc w9, w21 NGC_SBC_32_addsub_carry
+ (b'\xE9\x03\x15\x5A', 'LLIL_SET_REG.d(w9,LLIL_SBB.d(LLIL_CONST.d(0x0),LLIL_REG.d(w21),LLIL_NOT(LLIL_FLAG(c))))'),
+ # ngc x2, x27 NGC_SBC_64_addsub_carry
+ (b'\xE2\x03\x1B\xDA', 'LLIL_SET_REG.q(x2,LLIL_SBB.q(LLIL_CONST.q(0x0),LLIL_REG.q(x27),LLIL_NOT(LLIL_FLAG(c))))'),
+ # ngc x18, x21 NGC_SBC_64_addsub_carry
+ (b'\xF2\x03\x15\xDA', 'LLIL_SET_REG.q(x18,LLIL_SBB.q(LLIL_CONST.q(0x0),LLIL_REG.q(x21),LLIL_NOT(LLIL_FLAG(c))))'),
+ # ngc x13, x12 NGC_SBC_64_addsub_carry
+ (b'\xED\x03\x0C\xDA', 'LLIL_SET_REG.q(x13,LLIL_SBB.q(LLIL_CONST.q(0x0),LLIL_REG.q(x12),LLIL_NOT(LLIL_FLAG(c))))'),
+ # ngc x6, x24 NGC_SBC_64_addsub_carry
+ (b'\xE6\x03\x18\xDA', 'LLIL_SET_REG.q(x6,LLIL_SBB.q(LLIL_CONST.q(0x0),LLIL_REG.q(x24),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbcs w13, w9, w14 SBCS_32_addsub_carry
+ (b'\x2D\x01\x0E\x7A', 'LLIL_SET_REG.d(w13,LLIL_SBB.d{*}(LLIL_REG.d(w9),LLIL_REG.d(w14),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbcs w28, w17, w10 SBCS_32_addsub_carry
+ (b'\x3C\x02\x0A\x7A', 'LLIL_SET_REG.d(w28,LLIL_SBB.d{*}(LLIL_REG.d(w17),LLIL_REG.d(w10),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbcs w18, w19, w21 SBCS_32_addsub_carry
+ (b'\x72\x02\x15\x7A', 'LLIL_SET_REG.d(w18,LLIL_SBB.d{*}(LLIL_REG.d(w19),LLIL_REG.d(w21),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbcs w19, w29, w9 SBCS_32_addsub_carry
+ (b'\xB3\x03\x09\x7A', 'LLIL_SET_REG.d(w19,LLIL_SBB.d{*}(LLIL_REG.d(w29),LLIL_REG.d(w9),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbcs x22, x1, xzr SBCS_64_addsub_carry
+ (b'\x36\x00\x1F\xFA', 'LLIL_SET_REG.q(x22,LLIL_SBB.q{*}(LLIL_REG.q(x1),LLIL_CONST.q(0x0),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbcs x15, x11, x22 SBCS_64_addsub_carry
+ (b'\x6F\x01\x16\xFA', 'LLIL_SET_REG.q(x15,LLIL_SBB.q{*}(LLIL_REG.q(x11),LLIL_REG.q(x22),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbcs x11, x25, x22 SBCS_64_addsub_carry
+ (b'\x2B\x03\x16\xFA', 'LLIL_SET_REG.q(x11,LLIL_SBB.q{*}(LLIL_REG.q(x25),LLIL_REG.q(x22),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbcs x4, x16, x27 SBCS_64_addsub_carry
+ (b'\x04\x02\x1B\xFA', 'LLIL_SET_REG.q(x4,LLIL_SBB.q{*}(LLIL_REG.q(x16),LLIL_REG.q(x27),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbc w13, w28, w30 SBC_32_addsub_carry
+ (b'\x8D\x03\x1E\x5A', 'LLIL_SET_REG.d(w13,LLIL_SBB.d(LLIL_REG.d(w28),LLIL_REG.d(w30),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbc w7, w8, w0 SBC_32_addsub_carry
+ (b'\x07\x01\x00\x5A', 'LLIL_SET_REG.d(w7,LLIL_SBB.d(LLIL_REG.d(w8),LLIL_REG.d(w0),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbc w28, w8, w24 SBC_32_addsub_carry
+ (b'\x1C\x01\x18\x5A', 'LLIL_SET_REG.d(w28,LLIL_SBB.d(LLIL_REG.d(w8),LLIL_REG.d(w24),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbc w10, w22, w10 SBC_32_addsub_carry
+ (b'\xCA\x02\x0A\x5A', 'LLIL_SET_REG.d(w10,LLIL_SBB.d(LLIL_REG.d(w22),LLIL_REG.d(w10),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbc x19, x20, x16 SBC_64_addsub_carry
+ (b'\x93\x02\x10\xDA', 'LLIL_SET_REG.q(x19,LLIL_SBB.q(LLIL_REG.q(x20),LLIL_REG.q(x16),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbc x16, x11, x12 SBC_64_addsub_carry
+ (b'\x70\x01\x0C\xDA', 'LLIL_SET_REG.q(x16,LLIL_SBB.q(LLIL_REG.q(x11),LLIL_REG.q(x12),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbc x25, x7, x29 SBC_64_addsub_carry
+ (b'\xF9\x00\x1D\xDA', 'LLIL_SET_REG.q(x25,LLIL_SBB.q(LLIL_REG.q(x7),LLIL_REG.q(x29),LLIL_NOT(LLIL_FLAG(c))))'),
+ # sbc x25, x9, x18 SBC_64_addsub_carry
+ (b'\x39\x01\x12\xDA', 'LLIL_SET_REG.q(x25,LLIL_SBB.q(LLIL_REG.q(x9),LLIL_REG.q(x18),LLIL_NOT(LLIL_FLAG(c))))'),
+]
+
+tests_sbf = [
+ # asr w21, w7, #0x7 ASR_SBFM_32M_bitfield
+ (b'\xF5\x7C\x07\x13', 'LLIL_SET_REG.d(w21,LLIL_ASR.d(LLIL_REG.d(w7),LLIL_CONST.d(0x7)))'),
+ # asr w15, w5, #0x1e ASR_SBFM_32M_bitfield
+ (b'\xAF\x7C\x1E\x13', 'LLIL_SET_REG.d(w15,LLIL_ASR.d(LLIL_REG.d(w5),LLIL_CONST.d(0x1E)))'),
+ # asr w8, w17, #0xe ASR_SBFM_32M_bitfield
+ (b'\x28\x7E\x0E\x13', 'LLIL_SET_REG.d(w8,LLIL_ASR.d(LLIL_REG.d(w17),LLIL_CONST.d(0xE)))'),
+ # asr w7, w5, #0x1a ASR_SBFM_32M_bitfield
+ (b'\xA7\x7C\x1A\x13', 'LLIL_SET_REG.d(w7,LLIL_ASR.d(LLIL_REG.d(w5),LLIL_CONST.d(0x1A)))'),
+ # asr x24, x10, #0x21 ASR_SBFM_64M_bitfield
+ (b'\x58\xFD\x61\x93', 'LLIL_SET_REG.q(x24,LLIL_ASR.q(LLIL_REG.q(x10),LLIL_CONST.q(0x21)))'),
+ # asr x8, x30, #0x3b ASR_SBFM_64M_bitfield
+ (b'\xC8\xFF\x7B\x93', 'LLIL_SET_REG.q(x8,LLIL_ASR.q(LLIL_REG.q(x30),LLIL_CONST.q(0x3B)))'),
+ # asr x7, x9, #0x33 ASR_SBFM_64M_bitfield
+ (b'\x27\xFD\x73\x93', 'LLIL_SET_REG.q(x7,LLIL_ASR.q(LLIL_REG.q(x9),LLIL_CONST.q(0x33)))'),
+ # asr x17, x21, #0x1a ASR_SBFM_64M_bitfield
+ (b'\xB1\xFE\x5A\x93', 'LLIL_SET_REG.q(x17,LLIL_ASR.q(LLIL_REG.q(x21),LLIL_CONST.q(0x1A)))'),
+ # sbfiz w0, w9, #0x1c, #0x3 SBFIZ_SBFM_32M_bitfield
+ (b'\x20\x09\x04\x13', 'LLIL_SET_REG.d(w0,LLIL_ASR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_REG.d(w9),LLIL_CONST.d(0x7)),LLIL_CONST.b(0x1D)),LLIL_CONST.b(0x1)))'),
+ # sbfiz w5, w27, #0x1b, #0x1 SBFIZ_SBFM_32M_bitfield
+ (b'\x65\x03\x05\x13', 'LLIL_SET_REG.d(w5,LLIL_ASR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_REG.d(w27),LLIL_CONST.d(0x1)),LLIL_CONST.b(0x1F)),LLIL_CONST.b(0x4)))'),
+ # sbfiz w7, w2, #0x9, #0xd SBFIZ_SBFM_32M_bitfield
+ (b'\x47\x30\x17\x13', 'LLIL_SET_REG.d(w7,LLIL_ASR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_REG.d(w2),LLIL_CONST.d(0x1FFF)),LLIL_CONST.b(0x13)),LLIL_CONST.b(0xA)))'),
+ # sbfiz w1, w20, #0x12, #0x9 SBFIZ_SBFM_32M_bitfield
+ (b'\x81\x22\x0E\x13', 'LLIL_SET_REG.d(w1,LLIL_ASR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_REG.d(w20),LLIL_CONST.d(0x1FF)),LLIL_CONST.b(0x17)),LLIL_CONST.b(0x5)))'),
+ # sbfiz x22, x23, #0x10, #0x26 SBFIZ_SBFM_64M_bitfield
+ (b'\xF6\x96\x70\x93', 'LLIL_SET_REG.q(x22,LLIL_ASR.q(LLIL_LSL.q(LLIL_AND.q(LLIL_REG.q(x23),LLIL_CONST.q(0x3FFFFFFFFF)),LLIL_CONST.b(0x1A)),LLIL_CONST.b(0xA)))'),
+ # sbfiz x23, x19, #0x20, #0x3 SBFIZ_SBFM_64M_bitfield
+ (b'\x77\x0A\x60\x93', 'LLIL_SET_REG.q(x23,LLIL_ASR.q(LLIL_LSL.q(LLIL_AND.q(LLIL_REG.q(x19),LLIL_CONST.q(0x7)),LLIL_CONST.b(0x3D)),LLIL_CONST.b(0x1D)))'),
+ # sbfiz x6, x25, #0x1, #0x37 SBFIZ_SBFM_64M_bitfield
+ (b'\x26\xDB\x7F\x93', 'LLIL_SET_REG.q(x6,LLIL_ASR.q(LLIL_LSL.q(LLIL_AND.q(LLIL_REG.q(x25),LLIL_CONST.q(0x7FFFFFFFFFFFFF)),LLIL_CONST.b(0x9)),LLIL_CONST.b(0x8)))'),
+ # sbfiz x23, x16, #0x5, #0xb SBFIZ_SBFM_64M_bitfield
+ (b'\x17\x2A\x7B\x93', 'LLIL_SET_REG.q(x23,LLIL_ASR.q(LLIL_LSL.q(LLIL_AND.q(LLIL_REG.q(x16),LLIL_CONST.q(0x7FF)),LLIL_CONST.b(0x35)),LLIL_CONST.b(0x30)))'),
+ # sbfx w6, w9, #0x1, #0x19 SBFX_SBFM_32M_bitfield
+ (b'\x26\x65\x01\x13', 'LLIL_SET_REG.d(w6,LLIL_ASR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_REG.d(w9),LLIL_CONST.d(0x3FFFFFE)),LLIL_CONST.b(0x6)),LLIL_CONST.b(0x7)))'),
+ # sbfx w30, w23, #0xb, #0x5 SBFX_SBFM_32M_bitfield
+ (b'\xFE\x3E\x0B\x13', 'LLIL_SET_REG.d(w30,LLIL_ASR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_REG.d(w23),LLIL_CONST.d(0xF800)),LLIL_CONST.b(0x10)),LLIL_CONST.b(0x1B)))'),
+ # sbfx w22, w28, #0xa, #0x13 SBFX_SBFM_32M_bitfield
+ (b'\x96\x73\x0A\x13', 'LLIL_SET_REG.d(w22,LLIL_ASR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_REG.d(w28),LLIL_CONST.d(0x1FFFFC00)),LLIL_CONST.b(0x3)),LLIL_CONST.b(0xD)))'),
+ # sbfx w29, w12, #0x12, #0x5 SBFX_SBFM_32M_bitfield
+ (b'\x9D\x59\x12\x13', 'LLIL_SET_REG.d(w29,LLIL_ASR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_REG.d(w12),LLIL_CONST.d(0x7C0000)),LLIL_CONST.b(0x9)),LLIL_CONST.b(0x1B)))'),
+ # sbfx x5, x1, #0xb, #0x13 SBFX_SBFM_64M_bitfield
+ (b'\x25\x74\x4B\x93', 'LLIL_SET_REG.q(x5,LLIL_ASR.q(LLIL_LSL.q(LLIL_AND.q(LLIL_REG.q(x1),LLIL_CONST.q(0x3FFFF800)),LLIL_CONST.b(0x22)),LLIL_CONST.b(0x2D)))'),
+ # sbfx x4, x16, #0x1e, #0x3 SBFX_SBFM_64M_bitfield
+ (b'\x04\x82\x5E\x93', 'LLIL_SET_REG.q(x4,LLIL_ASR.q(LLIL_LSL.q(LLIL_AND.q(LLIL_REG.q(x16),LLIL_CONST.q(0x1C0000000)),LLIL_CONST.b(0x1F)),LLIL_CONST.b(0x3D)))'),
+ # sbfx x26, x7, #0x11, #0x1e SBFX_SBFM_64M_bitfield
+ (b'\xFA\xB8\x51\x93', 'LLIL_SET_REG.q(x26,LLIL_ASR.q(LLIL_LSL.q(LLIL_AND.q(LLIL_REG.q(x7),LLIL_CONST.q(0x7FFFFFFE0000)),LLIL_CONST.b(0x11)),LLIL_CONST.b(0x22)))'),
+ # sbfx xzr, x5, #0x9, #0x32 SBFX_SBFM_64M_bitfield
+ (b'\xBF\xE8\x49\x93', 'LLIL_ASR.q(LLIL_LSL.q(LLIL_AND.q(LLIL_REG.q(x5),LLIL_CONST.q(0x7FFFFFFFFFFFE00)),LLIL_CONST.b(0x5)),LLIL_CONST.b(0xE))'),
+ # sxtb w10, w4 SXTB_SBFM_32M_bitfield
+ (b'\x8A\x1C\x00\x13', 'LLIL_SET_REG.d(w10,LLIL_SX.d(LLIL_LOW_PART.b(LLIL_REG.d(w4))))'),
+ # sxtb w30, w20 SXTB_SBFM_32M_bitfield
+ (b'\x9E\x1E\x00\x13', 'LLIL_SET_REG.d(w30,LLIL_SX.d(LLIL_LOW_PART.b(LLIL_REG.d(w20))))'),
+ # sxtb w26, w22 SXTB_SBFM_32M_bitfield
+ (b'\xDA\x1E\x00\x13', 'LLIL_SET_REG.d(w26,LLIL_SX.d(LLIL_LOW_PART.b(LLIL_REG.d(w22))))'),
+ # sxtb w0, w11 SXTB_SBFM_32M_bitfield
+ (b'\x60\x1D\x00\x13', 'LLIL_SET_REG.d(w0,LLIL_SX.d(LLIL_LOW_PART.b(LLIL_REG.d(w11))))'),
+ # sxtb x1, w19 SXTB_SBFM_64M_bitfield
+ (b'\x61\x1E\x40\x93', 'LLIL_SET_REG.q(x1,LLIL_SX.q(LLIL_LOW_PART.b(LLIL_REG.d(w19))))'),
+ # sxtb x20, w16 SXTB_SBFM_64M_bitfield
+ (b'\x14\x1E\x40\x93', 'LLIL_SET_REG.q(x20,LLIL_SX.q(LLIL_LOW_PART.b(LLIL_REG.d(w16))))'),
+ # sxtb x19, w17 SXTB_SBFM_64M_bitfield
+ (b'\x33\x1E\x40\x93', 'LLIL_SET_REG.q(x19,LLIL_SX.q(LLIL_LOW_PART.b(LLIL_REG.d(w17))))'),
+ # sxtb x19, w2 SXTB_SBFM_64M_bitfield
+ (b'\x53\x1C\x40\x93', 'LLIL_SET_REG.q(x19,LLIL_SX.q(LLIL_LOW_PART.b(LLIL_REG.d(w2))))'),
+ # sxth w26, w23 SXTH_SBFM_32M_bitfield
+ (b'\xFA\x3E\x00\x13', 'LLIL_SET_REG.d(w26,LLIL_SX.d(LLIL_LOW_PART.w(LLIL_REG.d(w23))))'),
+ # sxth wzr, w18 SXTH_SBFM_32M_bitfield
+ (b'\x5F\x3E\x00\x13', 'LLIL_SX.d(LLIL_LOW_PART.w(LLIL_REG.d(w18)))'),
+ # sxth w23, wzr SXTH_SBFM_32M_bitfield
+ (b'\xF7\x3F\x00\x13', 'LLIL_SET_REG.d(w23,LLIL_CONST.d(0x0))'),
+ # sxth w12, w4 SXTH_SBFM_32M_bitfield
+ (b'\x8C\x3C\x00\x13', 'LLIL_SET_REG.d(w12,LLIL_SX.d(LLIL_LOW_PART.w(LLIL_REG.d(w4))))'),
+ # sxth x2, w13 SXTH_SBFM_64M_bitfield
+ (b'\xA2\x3D\x40\x93', 'LLIL_SET_REG.q(x2,LLIL_SX.q(LLIL_LOW_PART.w(LLIL_REG.d(w13))))'),
+ # sxth x2, w19 SXTH_SBFM_64M_bitfield
+ (b'\x62\x3E\x40\x93', 'LLIL_SET_REG.q(x2,LLIL_SX.q(LLIL_LOW_PART.w(LLIL_REG.d(w19))))'),
+ # sxth x26, w27 SXTH_SBFM_64M_bitfield
+ (b'\x7A\x3F\x40\x93', 'LLIL_SET_REG.q(x26,LLIL_SX.q(LLIL_LOW_PART.w(LLIL_REG.d(w27))))'),
+ # sxth x2, w11 SXTH_SBFM_64M_bitfield
+ (b'\x62\x3D\x40\x93', 'LLIL_SET_REG.q(x2,LLIL_SX.q(LLIL_LOW_PART.w(LLIL_REG.d(w11))))'),
+ # sxtw x16, w15 SXTW_SBFM_64M_bitfield
+ (b'\xF0\x7D\x40\x93', 'LLIL_SET_REG.q(x16,LLIL_SX.q(LLIL_REG.d(w15)))'),
+ # sxtw x15, w15 SXTW_SBFM_64M_bitfield
+ (b'\xEF\x7D\x40\x93', 'LLIL_SET_REG.q(x15,LLIL_SX.q(LLIL_REG.d(w15)))'),
+ # sxtw x0, w25 SXTW_SBFM_64M_bitfield
+ (b'\x20\x7F\x40\x93', 'LLIL_SET_REG.q(x0,LLIL_SX.q(LLIL_REG.d(w25)))'),
+ # sxtw x0, w20 SXTW_SBFM_64M_bitfield
+ (b'\x80\x7E\x40\x93', 'LLIL_SET_REG.q(x0,LLIL_SX.q(LLIL_REG.d(w20)))'),
+]
+
+tests_grab_bag = [
# some vectors loads/stores that do not fill the entire register
# TODO: ld1/st1 with different addressing modes
# ld1 {v0.8b, v1.8b}, [x0]
@@ -2999,30 +5646,66 @@ test_cases = \
# ushr d31, d13, #0x8
(b'\xBF\x05\x78\x7F', 'LLIL_SET_REG.q(d31,LLIL_LSR.q(LLIL_REG.q(d13),LLIL_CONST.b(0x8)))'),
#
- (b'\x3B\x7F\xB6\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x25))); LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w22),LLIL_REG.d(temp0)),2,4);' + \
- ' LLIL_STORE.d(LLIL_REG.q(x25),LLIL_REG.d(w27)); LLIL_GOTO(4); LLIL_SET_REG.d(w22,LLIL_REG.d(temp0))'), # casa w22, w27, [x25]
- (b'\x0C\x7D\xF1\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x8))); LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w17),LLIL_REG.d(temp0)),2,4);' + \
- ' LLIL_STORE.d(LLIL_REG.q(x8),LLIL_REG.d(w12)); LLIL_GOTO(4); LLIL_SET_REG.d(w17,LLIL_REG.d(temp0))'), # casa w17, w12, [x8]
- (b'\xC6\xFF\xBB\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x30))); LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w27),LLIL_REG.d(temp0)),2,4);' + \
- ' LLIL_STORE.d(LLIL_REG.q(x30),LLIL_REG.d(w6)); LLIL_GOTO(4); LLIL_SET_REG.d(w27,LLIL_REG.d(temp0))'), # casl w27, w6, [x30]
- (b'\x7E\xFC\xED\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x3))); LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w13),LLIL_REG.d(temp0)),2,4);' + \
- ' LLIL_STORE.d(LLIL_REG.q(x3),LLIL_REG.d(w30)); LLIL_GOTO(4); LLIL_SET_REG.d(w13,LLIL_REG.d(temp0))'), # casal w13, w30, [x3]
- (b'\x43\x7C\xE5\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x2))); LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w5)),LLIL_NOP()),2,4);' + \
- ' LLIL_STORE.w(LLIL_REG.q(x2),LLIL_LOW_PART.w(LLIL_REG.d(w3))); LLIL_GOTO(4); LLIL_SET_REG.d(w5,LLIL_REG.w(temp0))'), # casah w5, w3, [x2]
- (b'\xDE\xFC\xF2\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x6))); LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w18)),LLIL_NOP()),2,4);' + \
- ' LLIL_STORE.w(LLIL_REG.q(x6),LLIL_LOW_PART.w(LLIL_REG.d(w30))); LLIL_GOTO(4); LLIL_SET_REG.d(w18,LLIL_REG.w(temp0))'), # casalh w18, w30, [x6]
- (b'\x80\x7F\xB5\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x28))); LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w21)),LLIL_NOP()),2,4);' + \
- ' LLIL_STORE.w(LLIL_REG.q(x28),LLIL_LOW_PART.w(LLIL_REG.d(w0))); LLIL_GOTO(4); LLIL_SET_REG.d(w21,LLIL_REG.w(temp0))'), # cash w21, w0, [x28]
- (b'\xEB\xFD\xA5\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x15))); LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w5)),LLIL_NOP()),2,4);' + \
- ' LLIL_STORE.w(LLIL_REG.q(x15),LLIL_LOW_PART.w(LLIL_REG.d(w11))); LLIL_GOTO(4); LLIL_SET_REG.d(w5,LLIL_REG.w(temp0))'), # caslh w5, w11, [x15]
- (b'\x2E\x7C\xF7\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x1))); LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w23)),LLIL_NOP()),2,4);' + \
- ' LLIL_STORE.b(LLIL_REG.q(x1),LLIL_LOW_PART.b(LLIL_REG.d(w14))); LLIL_GOTO(4); LLIL_SET_REG.d(w23,LLIL_REG.b(temp0))'), # casab w23, w14, [x1]
- (b'\x27\xFF\xE6\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x25))); LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w6)),LLIL_NOP()),2,4);' + \
- ' LLIL_STORE.b(LLIL_REG.q(x25),LLIL_LOW_PART.b(LLIL_REG.d(w7))); LLIL_GOTO(4); LLIL_SET_REG.d(w6,LLIL_REG.b(temp0))'), # casalb w6, w7, [x25]
- (b'\x1E\x7E\xB8\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x16))); LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w24)),LLIL_NOP()),2,4);' + \
- ' LLIL_STORE.b(LLIL_REG.q(x16),LLIL_LOW_PART.b(LLIL_REG.d(w30))); LLIL_GOTO(4); LLIL_SET_REG.d(w24,LLIL_REG.b(temp0))'), # casb w24, w30, [x16]
- (b'\xA6\xFD\xAE\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x13))); LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w14)),LLIL_NOP()),2,4);' + \
- ' LLIL_STORE.b(LLIL_REG.q(x13),LLIL_LOW_PART.b(LLIL_REG.d(w6))); LLIL_GOTO(4); LLIL_SET_REG.d(w14,LLIL_REG.b(temp0))'), # caslb w14, w6, [x13]
+ (b'\x3B\x7F\xB6\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x25)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w22),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x25),LLIL_REG.d(w27));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w22,LLIL_REG.d(temp0))'), # casa w22, w27, [x25]
+ (b'\x0C\x7D\xF1\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x8)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w17),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x8),LLIL_REG.d(w12));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w17,LLIL_REG.d(temp0))'), # casa w17, w12, [x8]
+ (b'\xC6\xFF\xBB\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x30)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w27),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x30),LLIL_REG.d(w6));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w27,LLIL_REG.d(temp0))'), # casl w27, w6, [x30]
+ (b'\x7E\xFC\xED\x88', 'LLIL_SET_REG.d(temp0,LLIL_LOAD.d(LLIL_REG.q(x3)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_REG.d(w13),LLIL_REG.d(temp0)),2,4);' + \
+ ' LLIL_STORE.d(LLIL_REG.q(x3),LLIL_REG.d(w30));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w13,LLIL_REG.d(temp0))'), # casal w13, w30, [x3]
+ (b'\x43\x7C\xE5\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x2)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w5)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x2),LLIL_LOW_PART.w(LLIL_REG.d(w3)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w5,LLIL_REG.w(temp0))'), # casah w5, w3, [x2]
+ (b'\xDE\xFC\xF2\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x6)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w18)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x6),LLIL_LOW_PART.w(LLIL_REG.d(w30)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w18,LLIL_REG.w(temp0))'), # casalh w18, w30, [x6]
+ (b'\x80\x7F\xB5\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x28)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w21)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x28),LLIL_LOW_PART.w(LLIL_REG.d(w0)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w21,LLIL_REG.w(temp0))'), # cash w21, w0, [x28]
+ (b'\xEB\xFD\xA5\x48', 'LLIL_SET_REG.w(temp0,LLIL_LOAD.w(LLIL_REG.q(x15)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.w(LLIL_REG.d(w5)),LLIL_REG.w(temp0)),2,4);' + \
+ ' LLIL_STORE.w(LLIL_REG.q(x15),LLIL_LOW_PART.w(LLIL_REG.d(w11)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w5,LLIL_REG.w(temp0))'), # caslh w5, w11, [x15]
+ (b'\x2E\x7C\xF7\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x1)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w23)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x1),LLIL_LOW_PART.b(LLIL_REG.d(w14)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w23,LLIL_REG.b(temp0))'), # casab w23, w14, [x1]
+ (b'\x27\xFF\xE6\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x25)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w6)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x25),LLIL_LOW_PART.b(LLIL_REG.d(w7)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w6,LLIL_REG.b(temp0))'), # casalb w6, w7, [x25]
+ (b'\x1E\x7E\xB8\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x16)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w24)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x16),LLIL_LOW_PART.b(LLIL_REG.d(w30)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w24,LLIL_REG.b(temp0))'), # casb w24, w30, [x16]
+ (b'\xA6\xFD\xAE\x08', 'LLIL_SET_REG.b(temp0,LLIL_LOAD.b(LLIL_REG.q(x13)));' + \
+ ' LLIL_IF(LLIL_CMP_E.d(LLIL_LOW_PART.b(LLIL_REG.d(w14)),LLIL_REG.b(temp0)),2,4);' + \
+ ' LLIL_STORE.b(LLIL_REG.q(x13),LLIL_LOW_PART.b(LLIL_REG.d(w6)));' + \
+ ' LLIL_GOTO(4);' + \
+ ' LLIL_SET_REG.d(w14,LLIL_REG.b(temp0))'), # caslb w14, w6, [x13]
# store pair
(b'\xFD\x7B\x01\xA9', 'LLIL_STORE.q(LLIL_ADD.q(LLIL_REG.q(sp),LLIL_CONST.q(0x10)),LLIL_REG.q(x29));' + \
' LLIL_STORE.q(LLIL_ADD.q(LLIL_REG.q(sp),LLIL_CONST.q(0x18)),LLIL_REG.q(x30))'),
@@ -3123,8 +5806,7 @@ test_cases = \
# Unknown system register
(b'\x41\x00\x1B\xD5', 'LLIL_INTRINSIC([sysreg_unknown],_WriteStatusReg,[LLIL_REG.q(x1)])'), # msr s3_3_c0_c0_2, x1
(b'\x43\x00\x3B\xD5', 'LLIL_INTRINSIC([x3],_ReadStatusReg,[LLIL_REG.q(sysreg_unknown)])'), # mrs x3, s3_3_c0_c0_2
- (b'\xE0\x03\x9F\xD6', 'LLIL_INTRINSIC([],_eret,[]);' + \
- ' LLIL_TRAP(0)'), # eret
+ (b'\xE0\x03\x9F\xD6', 'LLIL_INTRINSIC([],_eret,[]); LLIL_TRAP(0)'), # eret
(b'\x00\x08\x21\x1E', 'LLIL_SET_REG.d(s0,LLIL_FMUL.d(LLIL_REG.d(s0),LLIL_REG.d(s1)))'), # fmul s0, s0, s1
(b'\x00\x18\x21\x1E', 'LLIL_SET_REG.d(s0,LLIL_FDIV.d(LLIL_REG.d(s0),LLIL_REG.d(s1)))'), # fdiv s0, s0, s1
(b'\xE0\x0F\x40\xBD', 'LLIL_SET_REG.d(s0,LLIL_LOAD.d(LLIL_ADD.q(LLIL_REG.q(sp),LLIL_CONST.q(0xC))))'), # ldr s0, [sp, #0xc]
@@ -3426,7 +6108,7 @@ test_cases = \
(b'\x41\x00\x03\xEA', 'LLIL_SET_REG.q(x1,LLIL_AND.q{*}(LLIL_REG.q(x2),LLIL_REG.q(x3)))'), # ands x1,x2,x3 with IL_FLAGWRITE_ALL
(b'\x41\x00\x03\xDA', 'LLIL_SET_REG.q(x1,LLIL_SBB.q(LLIL_REG.q(x2),LLIL_REG.q(x3),LLIL_NOT(LLIL_FLAG(c))))'), # sbc x1,x2,x3
(b'\x41\x00\x03\xFA', 'LLIL_SET_REG.q(x1,LLIL_SBB.q{*}(LLIL_REG.q(x2),LLIL_REG.q(x3),LLIL_NOT(LLIL_FLAG(c))))'), # sbcs x1,x2,x3 with IL_FLAGWRITE_ALL
- (b'\xe9\x03\x1f\xfa', 'LLIL_SET_REG.q(x9,LLIL_SBB.q{*}(LLIL_CONST.q(0x0),LLIL_CONST.q(0x0),LLIL_NOT(LLIL_FLAG(c))))'), # ngcs x9, xzr
+ (b'\xE9\x03\x1F\xFA', 'LLIL_SET_REG.q(x9,LLIL_SBB.q{*}(LLIL_CONST.q(0x0),LLIL_CONST.q(0x0),LLIL_NOT(LLIL_FLAG(c))))'), # ngcs x9, xzr
(b'\x01\x00\x00\xD4', 'LLIL_SET_REG.d(syscall_info,LLIL_CONST.d(0x40000000));' + \
' LLIL_SYSCALL()'), # svc #0; ret; ZwAccessCheck() on win-arm64
(b'\x21\x00\x00\xD4', 'LLIL_SET_REG.d(syscall_info,LLIL_CONST.d(0x40000001));' + \
@@ -3524,6 +6206,61 @@ test_cases = \
(b'\x1F\x20\x03\xD5', 'LLIL_NOP()'), # nop, gets optimized from function
]
+test_cases = \
+ tests_shll + \
+ tests_udf + \
+ tests_pac + \
+ tests_load_acquire_store_release + \
+ tests_movk + \
+ tests_mvni + \
+ tests_2791 + \
+ tests_msr + \
+ tests_ucvtf + \
+ tests_ucvtf2 + \
+ tests_scvtf + \
+ tests_ret + \
+ tests_svc_hvc_smc + \
+ tests_clrex + \
+ tests_xtn_xtn2 + \
+ tests_dc + \
+ tests_ldadd + \
+ tests_swp + \
+ tests_dup + \
+ tests_stlr + \
+ tests_ldnp + \
+ tests_stnp + \
+ tests_mov + \
+ tests_mov_add + \
+ tests_mov_dup_ins + \
+ tests_movi + \
+ tests_movn + \
+ tests_movz + \
+ tests_orr + \
+ tests_umov + \
+ tests_fsub + \
+ tests_fadd + \
+ tests_f_mathops + \
+ tests_fml + \
+ tests_fmul + \
+ tests_fcvt + \
+ tests_fcm + \
+ tests_fcmla + \
+ tests_fccmp_fccmpe + \
+ tests_fcmp_fcmpe + \
+ tests_fcsel + \
+ tests_fmov + \
+ tests_sha + \
+ tests_rev + \
+ tests_ld1 + \
+ tests_ld2 + \
+ tests_st1 + \
+ tests_tbl + \
+ tests_cas + \
+ tests_smov + \
+ tests_raddhn_rshrn + \
+ tests_ngc_sbc + \
+ tests_grab_bag
+
def il2str(il):
sz_lookup = {1:'.b', 2:'.w', 4:'.d', 8:'.q', 16:'.o'}
if isinstance(il, lowlevelil.LowLevelILInstruction):
@@ -3544,7 +6281,7 @@ def il2str(il):
return str(il)
# TODO: make this less hacky
-def lift(data):
+def lift(data, disasm=False):
EPILOG = b'\xa0\xd5\x9b\xd2' + b'\xc0\x03\x5f\xd6' # mov x0, 0xDEAD; return
platform = binaryninja.Platform['linux-aarch64']
@@ -3553,6 +6290,8 @@ def lift(data):
bv.add_function(0, plat=platform)
assert len(bv.functions) == 1
+ asm = []
+
tokens = []
attributes = set()
#for block in bv.functions[0].low_level_il:
@@ -3560,16 +6299,24 @@ def lift(data):
for il in block:
attributes = attributes.union(il.attributes)
tokens.append(il2str(il))
+ if disasm:
+ info = block.arch.get_instruction_info(bv[il.address:il.address+block.arch._get_max_instruction_length(None)], il.address)
+ asm.append(''.join(map(str, block.arch.get_instruction_text(bv[il.address:il.address + info.length], il.address)[0])))
il_str = '; '.join(tokens)
+ i = len(il_str)
try:
i = il_str.rindex('; LLIL_SET_REG.q(x0,LLIL_CONST.q(0xDEAD))')
- il_str = il_str[0:i]
except:
# ValueError: substring not found
pass
+ il_str = il_str[0:i]
+ asm = asm[0:1]
- return il_str, attributes
+ if disasm:
+ return il_str, attributes, asm
+ else:
+ return il_str, attributes
def il_str_to_tree(ilstr):
result = ''
@@ -3589,7 +6336,7 @@ def il_str_to_tree(ilstr):
result += c
return result
-def test_all_lifts():
+def test_all_lifts(no_fail=False):
for test_i, test_info in enumerate(test_cases):
if (test_i+1) % 25 == 0:
print(f'on test {test_i+1}/{len(test_cases)}')
@@ -3597,15 +6344,16 @@ def test_all_lifts():
data, expected_lift = test_info[0], test_info[1]
il_attrs = test_info[2] if len(test_info) == 3 else None
- actual_lift, actual_attrs = lift(data)
+ actual_lift, actual_attrs, asm = lift(data, True)
if actual_lift != expected_lift:
print('LIFT MISMATCH AT TEST %d!' % test_i)
- print('\t input: %s' % data.hex())
+ print('\t input: %s %s' % (data.hex(), '\n'.join(asm)))
print('\texpected: %s' % expected_lift)
print('\t actual: %s' % actual_lift)
print('\t tree:')
print(il_str_to_tree(actual_lift))
- return False
+ if not no_fail:
+ return False
# if IL attributes given, verify those too
if len(test_info) == 3:
@@ -3615,17 +6363,22 @@ def test_all_lifts():
print('\t input: %s' % data.hex())
print('\texpected: 0x%X' % expected_attr)
print('\t actual: ' + str(actual_attrs))
- return False
+ if not no_fail:
+ return False
return True
if __name__ == '__main__':
- if test_all_lifts():
+ no_fail = False
+ if len(sys.argv) > 1:
+ if sys.argv[1] == '--no-fail':
+ no_fail = True
+ if test_all_lifts(no_fail):
print('success!')
sys.exit(0)
else:
sys.exit(-1)
-if __name__ == 'arm64test':
- if test_all_lifts():
- print('success!')
+# if __name__ == 'arm64test':
+# if test_all_lifts():
+# print('success!')
diff --git a/arch/arm64/disassembler/test_cases.txt b/arch/arm64/disassembler/test_cases.txt
index f5cee0ad..4ff5e89a 100644
--- a/arch/arm64/disassembler/test_cases.txt
+++ b/arch/arm64/disassembler/test_cases.txt
@@ -22944,6 +22944,7 @@ AA87DFC4 orr x4, x30, x7, asr #0x37
AACAA00F orr x15, x0, x10, ror #0x28
AADF5572 orr x18, x11, xzr, ror #0x15
// ORR_asimdimm_L_hl 0x00111100000xxx10x1xxxxxxxxxxxx
+4F04B676 orr v22.8h, #0x93, lsl #0x8
0F04B676 orr v22.4h, #0x93, lsl #0x8
0F059527 orr v7.4h, #0xa9
4F0494CA orr v10.8h, #0x86
diff --git a/arch/arm64/il.cpp b/arch/arm64/il.cpp
index 12865568..8ab06a06 100644
--- a/arch/arm64/il.cpp
+++ b/arch/arm64/il.cpp
@@ -1150,7 +1150,7 @@ enum Arm64Intrinsic operation_to_intrinsic(int operation)
bool GetLowLevelILForInstruction(
- Architecture* arch, uint64_t addr, LowLevelILFunction& il, Instruction& instr, size_t addrSize, bool requireAlignment)
+ Architecture* arch, uint64_t addr, LowLevelILFunction& il, Instruction& instr, size_t addrSize, bool requireAlignment, std::function<bool()> _preferIntrinsics)
{
bool SetPacAttr = false;
@@ -1158,6 +1158,10 @@ bool GetLowLevelILForInstruction(
InstructionOperand& operand2 = instr.operands[1];
InstructionOperand& operand3 = instr.operands[2];
InstructionOperand& operand4 = instr.operands[3];
+ InstructionOperand& operand5 = instr.operands[4];
+
+ const size_t pairedSize = REGSZ_O(operand1) * 2;
+
if (requireAlignment && (addr % 4 != 0)) {
return false;
@@ -1165,6 +1169,15 @@ bool GetLowLevelILForInstruction(
int n_instrs_before = il.GetInstructionCount();
+ auto preferIntrinsics = [&]() -> bool {
+ if (_preferIntrinsics())
+ {
+ NeonGetLowLevelILForInstruction(arch, addr, il, instr, addrSize);
+ return (il.GetInstructionCount() > n_instrs_before);
+ }
+ return false;
+ };
+
// printf("%s() operation:%d encoding:%d\n", __func__, instr.operation, instr.encoding);
LowLevelILLabel trueLabel, falseLabel;
@@ -1317,6 +1330,37 @@ bool GetLowLevelILForInstruction(
il.Not(REGSZ_O(operand2), ReadILOperand(il, operand3, REGSZ_O(operand2))), SETFLAGS)));
}
break;
+ // TODO: some representation of the Acquire/Release semantics of the CAS* instructions... attribute?
+ case ARM64_CASP: // these compare-and-swaps can be pairs of 32 bit words or 64 bit doublewords
+ case ARM64_CASPA:
+ case ARM64_CASPAL:
+ case ARM64_CASPL:
+ {
+ // the ordering of the register pairing depends on the byte order (endianness) of memory
+ bool bigEndian = arch->GetEndianness() == BigEndian;
+ auto hi1 = bigEndian ? operand1 : operand2;
+ auto lo1 = bigEndian ? operand2 : operand1;
+ auto hi2 = bigEndian ? operand3 : operand4;
+ auto lo2 = bigEndian ? operand4 : operand3;
+ il.AddInstruction(il.SetRegister(pairedSize, LLIL_TEMP(0), il.Load(pairedSize, ILREG_O(operand5))));
+
+ GenIfElse(il,
+ il.CompareEqual(pairedSize,
+ il.RegisterSplit(REGSZ_O(operand1),
+ hi1.reg[0], lo1.reg[0]),
+ il.Register(pairedSize, LLIL_TEMP(0))),
+ il.Store(pairedSize,
+ ILREG_O(operand5),
+ il.RegisterSplit(REGSZ_O(operand1), hi2.reg[0], lo2.reg[0])),
+ 0);
+
+ il.AddInstruction(
+ il.SetRegisterSplit(pairedSize,
+ hi1.reg[0],
+ lo1.reg[0],
+ il.Register(pairedSize, LLIL_TEMP(0))));
+ break;
+ }
case ARM64_CAS: // these compare-and-swaps can be 32 or 64 bit
case ARM64_CASA:
case ARM64_CASAL:
@@ -1337,7 +1381,7 @@ bool GetLowLevelILForInstruction(
il.AddInstruction(il.SetRegister(2, LLIL_TEMP(0), il.Load(2, ILREG_O(operand3))));
GenIfElse(il,
- il.CompareEqual(REGSZ_O(operand1), ExtractRegister(il, operand1, 0, 2, false, 2), LLIL_TEMP(0)),
+ il.CompareEqual(REGSZ_O(operand1), ExtractRegister(il, operand1, 0, 2, false, 2), il.Register(2, LLIL_TEMP(0))),
il.Store(2, ILREG_O(operand3), ExtractRegister(il, operand2, 0, 2, false, 2)),
0);
@@ -1350,7 +1394,7 @@ bool GetLowLevelILForInstruction(
il.AddInstruction(il.SetRegister(1, LLIL_TEMP(0), il.Load(1, ILREG_O(operand3))));
GenIfElse(il,
- il.CompareEqual(REGSZ_O(operand1), ExtractRegister(il, operand1, 0, 1, false, 1), LLIL_TEMP(0)),
+ il.CompareEqual(REGSZ_O(operand1), ExtractRegister(il, operand1, 0, 1, false, 1), il.Register(1, LLIL_TEMP(0))),
il.Store(1, ILREG_O(operand3), ExtractRegister(il, operand2, 0, 1, false, 1)),
0);
@@ -1491,13 +1535,47 @@ bool GetLowLevelILForInstruction(
break;
case ARM64_EXTR:
il.AddInstruction(
- ILSETREG_O(operand1, il.LogicalShiftRight(REGSZ_O(operand1) * 2,
- il.Or(REGSZ_O(operand1) * 2,
- il.ShiftLeft(REGSZ_O(operand1) * 2, ILREG_O(operand2),
+ ILSETREG_O(operand1, il.LogicalShiftRight(pairedSize,
+ il.Or(pairedSize,
+ il.ShiftLeft(pairedSize, ILREG_O(operand2),
il.Const(1, REGSZ_O(operand1) * 8)),
ILREG_O(operand3)),
il.Const(1, IMM_O(operand4)))));
break;
+ case ARM64_FABD:
+ switch (instr.encoding)
+ {
+ case ENC_FABD_ASISDSAMEFP16_ONLY:
+ case ENC_FABD_ASISDSAME_ONLY:
+ il.AddInstruction(ILSETREG_O(operand1,
+ il.FloatAbs(REGSZ_O(operand1),
+ il.FloatSub(REGSZ_O(operand1), ILREG_O(operand2), ILREG_O(operand3)))));
+ break;
+ case ENC_FABD_ASIMDSAMEFP16_ONLY:
+ case ENC_FABD_ASIMDSAME_ONLY:
+ // covered by intrinsics
+ break;
+ case ENC_FABD_Z_P_ZZ_:
+ default:
+ ABORT_LIFT;
+ }
+ break;
+ case ARM64_FABS:
+ switch (instr.encoding)
+ {
+ case ENC_FABS_D_FLOATDP1:
+ case ENC_FABS_S_FLOATDP1:
+ case ENC_FABS_H_FLOATDP1:
+ il.AddInstruction(ILSETREG_O(operand1, il.FloatAbs(REGSZ_O(operand1), ILREG_O(operand2))));
+ break;
+ case ENC_FABS_ASIMDMISC_R:
+ case ENC_FABS_ASIMDMISCFP16_R:
+ // covered by intrinsics
+ break;
+ default:
+ ABORT_LIFT;
+ }
+ break;
case ARM64_FADD:
switch (instr.encoding)
{
@@ -1510,6 +1588,8 @@ bool GetLowLevelILForInstruction(
case ENC_FADD_ASIMDSAME_ONLY:
case ENC_FADD_ASIMDSAMEFP16_ONLY:
{
+ if (preferIntrinsics())
+ return true;
Register srcs1[16], srcs2[16], dsts[16];
int dst_n = unpack_vector(operand1, dsts);
int src1_n = unpack_vector(operand2, srcs1);
@@ -1524,7 +1604,54 @@ bool GetLowLevelILForInstruction(
}
break;
default:
+ ABORT_LIFT;
+ }
+ break;
+ case ARM64_FADDP:
+ switch (instr.encoding)
+ {
+ case ENC_FADDP_ASISDPAIR_ONLY_H:
+ case ENC_FADDP_ASISDPAIR_ONLY_SD:
+ {
+ Register srcs[16];
+ int src_n = unpack_vector(operand2, srcs);
+ if (src_n != 2)
+ ABORT_LIFT;
+ il.AddInstruction(ILSETREG_O(operand1,
+ il.FloatAdd(REGSZ_O(operand1), ILREG(srcs[0]), ILREG(srcs[1]))
+ ));
+ break;
+ }
+ case ENC_FADDP_ASIMDSAME_ONLY:
+ case ENC_FADDP_ASIMDSAMEFP16_ONLY:
+ {
+ if (preferIntrinsics())
+ return true;
+
+ Register srcs1[16], srcs2[16], dsts[16];
+ int dst_n = unpack_vector(operand1, dsts);
+ int src1_n = unpack_vector(operand2, srcs1);
+ int src2_n = unpack_vector(operand3, srcs2);
+ if ((dst_n != src1_n) || (src1_n != src2_n) || dst_n == 0)
+ ABORT_LIFT;
+
+ int rsize = get_register_size(dsts[0]);
+ for (int i = 0; i < dst_n; ++i)
+ {
+ auto srcs = i < dst_n / 2 ? srcs1 : srcs2;
+ auto index = i % (dst_n / 2);
+ il.AddInstruction(il.SetRegister(REGSZ(dsts[i]),
+ LLIL_TEMP(i), il.FloatAdd(rsize, ILREG(srcs[2 * index]), ILREG(srcs[2 * index + 1]))));
+ }
+ for (int i = 0; i < dst_n; ++i)
+ il.AddInstruction(ILSETREG(dsts[i], il.Register(REGSZ(dsts[i]), LLIL_TEMP(i))));
+
+ break;
+ }
+ case ENC_FADDP_Z_P_ZZ_:
il.AddInstruction(il.Unimplemented());
+ default:
+ ABORT_LIFT;
}
break;
case ARM64_FCCMP:
@@ -1555,6 +1682,23 @@ bool GetLowLevelILForInstruction(
il.AddInstruction(il.FloatSub(REGSZ_O(operand1), ILREG_O(operand1),
ReadILOperand(il, operand2, REGSZ_O(operand1)), SETFLAGS));
break;
+ case ARM64_FSQRT:
+ switch (instr.encoding)
+ {
+ case ENC_FSQRT_D_FLOATDP1:
+ case ENC_FSQRT_H_FLOATDP1:
+ case ENC_FSQRT_S_FLOATDP1:
+ il.AddInstruction(ILSETREG_O(
+ operand1, il.FloatSqrt(REGSZ_O(operand1), ILREG_O(operand2))));
+ break;
+ case ENC_FSQRT_ASIMDMISCFP16_R:
+ case ENC_FSQRT_ASIMDMISC_R:
+ // Intrinsics
+ break;
+ default:
+ ABORT_LIFT;
+ }
+ break;
case ARM64_FSUB:
switch (instr.encoding)
{
@@ -1567,6 +1711,9 @@ bool GetLowLevelILForInstruction(
case ENC_FSUB_ASIMDSAME_ONLY:
case ENC_FSUB_ASIMDSAMEFP16_ONLY:
{
+ if (preferIntrinsics())
+ return true;
+
Register srcs[16], dsts[16];
int dst_n = unpack_vector(operand1, dsts);
int src_n = unpack_vector(operand2, srcs);
@@ -1575,9 +1722,9 @@ bool GetLowLevelILForInstruction(
int rsize = get_register_size(dsts[0]);
for (int i = 0; i < dst_n; ++i)
- il.AddInstruction(il.FloatSub(rsize, ILREG(dsts[i]), ILREG(srcs[i])));
+ il.AddInstruction(ILSETREG(dsts[i], il.FloatSub(rsize, ILREG(dsts[i]), ILREG(srcs[i]))));
+ break;
}
- break;
default:
il.AddInstruction(il.Unimplemented());
}
@@ -1616,34 +1763,58 @@ bool GetLowLevelILForInstruction(
il.AddInstruction(ILSETREG_O(
operand1, il.FloatDiv(REGSZ_O(operand1), ILREG_O(operand2), ILREG_O(operand3))));
break;
+ case ENC_FDIV_ASIMDSAMEFP16_ONLY:
+ case ENC_FDIV_ASIMDSAME_ONLY:
+ {
+ if (preferIntrinsics())
+ return true;
+
+ Register srcs1[16], srcs2[16], dsts[16];
+ int dst_n = unpack_vector(operand1, dsts);
+ int src1_n = unpack_vector(operand2, srcs1);
+ int src2_n = unpack_vector(operand3, srcs2);
+ if ((dst_n != src1_n) || (src1_n != src2_n) || dst_n == 0)
+ ABORT_LIFT;
+ int rsize = get_register_size(dsts[0]);
+ for (int i = 0; i < dst_n; ++i)
+ il.AddInstruction(ILSETREG(
+ dsts[i], il.FloatDiv(rsize, ILREG(srcs1[i]), ILREG(srcs2[i]))));
+ break;
+ }
default:
il.AddInstruction(il.Unimplemented());
}
break;
case ARM64_FMOV:
+
switch (instr.encoding)
{
case ENC_FMOV_64VX_FLOAT2INT:
il.AddInstruction(ILSETREG_O(operand1,
- il.FloatToInt(REGSZ_O(operand1), ILREG(vector_reg_minimize(instr.operands[1])))));
+ il.ZeroExtend(REGSZ_O(operand1), ILREG(vector_reg_minimize(instr.operands[1])))));
break;
case ENC_FMOV_V64I_FLOAT2INT:
{
Register minreg = vector_reg_minimize(instr.operands[0]);
il.AddInstruction(il.SetRegister(get_register_size(minreg), minreg,
- il.FloatToInt(REGSZ_O(operand1), ILREG_O(instr.operands[1]))));
+ il.Register(REGSZ_O(operand1), instr.operands[1].reg[0])));
break;
}
case ENC_FMOV_32H_FLOAT2INT:
case ENC_FMOV_32S_FLOAT2INT:
case ENC_FMOV_64H_FLOAT2INT:
case ENC_FMOV_64D_FLOAT2INT:
+ // <Rd> <- <Vn> (copy from FP register to general register, with no conversion)
+ il.AddInstruction(
+ ILSETREG_O(operand1, il.ZeroExtend(REGSZ_O(operand1), ILREG_O(instr.operands[1]))));
+ break;
case ENC_FMOV_D64_FLOAT2INT:
case ENC_FMOV_H32_FLOAT2INT:
case ENC_FMOV_H64_FLOAT2INT:
case ENC_FMOV_S32_FLOAT2INT:
+ // <Vd> <- <Rn> (copy from general register to FP register, with no conversion)
il.AddInstruction(
- ILSETREG_O(operand1, il.FloatToInt(REGSZ_O(operand1), ILREG_O(instr.operands[1]))));
+ ILSETREG_O(operand1, il.IntToFloat(REGSZ_O(operand1), ILREG_O(instr.operands[1]))));
break;
case ENC_FMOV_H_FLOATIMM:
case ENC_FMOV_S_FLOATIMM:
@@ -1654,7 +1825,8 @@ bool GetLowLevelILForInstruction(
float_sz = 4;
if (instr.encoding == ENC_FMOV_D_FLOATIMM)
float_sz = 8;
- il.AddInstruction(ILSETREG_O(operand1, GetFloat(il, operand2, float_sz)));
+ // Technically, we should use 2 bytes to GetFloat for half-precision registers, but that causes MLIL and HLIL to lift the constant to 0
+ il.AddInstruction(ILSETREG_O(operand1, il.FloatConvert(float_sz, GetFloat(il, operand2, float_sz == 2 ? 4 : float_sz))));
break;
}
case ENC_FMOV_H_FLOATDP1:
@@ -1666,6 +1838,9 @@ bool GetLowLevelILForInstruction(
case ENC_FMOV_ASIMDIMM_H_H:
case ENC_FMOV_ASIMDIMM_S_S:
{
+ if (preferIntrinsics())
+ return true;
+
int float_sz = 2;
if (instr.encoding == ENC_FMOV_ASIMDIMM_S_S)
float_sz = 4;
@@ -1675,7 +1850,8 @@ bool GetLowLevelILForInstruction(
Register regs[16];
int dst_n = unpack_vector(operand1, regs);
for (int i = 0; i < dst_n; ++i)
- il.AddInstruction(ILSETREG(regs[i], GetFloat(il, operand2, float_sz)));
+ // Technically, we should use 2 bytes to GetFloat for half-precision registers, but that causes MLIL and HLIL to lift the constant to 0
+ il.AddInstruction(ILSETREG(regs[i], il.FloatConvert(float_sz, GetFloat(il, operand2, float_sz == 2 ? 4 : float_sz))));
break;
}
default:
@@ -1694,6 +1870,9 @@ bool GetLowLevelILForInstruction(
case ENC_FMUL_ASIMDSAME_ONLY:
case ENC_FMUL_ASIMDSAMEFP16_ONLY:
{
+ if (preferIntrinsics())
+ return true;
+
Register srcs1[16], srcs2[16], dsts[16];
int dst_n = unpack_vector(operand1, dsts);
int src1_n = unpack_vector(operand2, srcs1);
@@ -1704,13 +1883,16 @@ bool GetLowLevelILForInstruction(
for (int i = 0; i < dst_n; ++i)
il.AddInstruction(ILSETREG(
dsts[i], il.FloatMult(rsize, ILREG(srcs1[i]), ILREG(srcs2[i]))));
+ break;
}
- break;
case ENC_FMUL_ASIMDELEM_RH_H:
case ENC_FMUL_ASIMDELEM_R_SD:
case ENC_FMUL_ASISDELEM_RH_H:
case ENC_FMUL_ASISDELEM_R_SD:
{
+ if (preferIntrinsics())
+ return true;
+
Register srcs1[16], srcs2[16], dsts[16];
int dst_n = unpack_vector(operand1, dsts);
int src1_n = unpack_vector(operand2, srcs1);
@@ -1721,12 +1903,47 @@ bool GetLowLevelILForInstruction(
for (int i = 0; i < dst_n; ++i)
il.AddInstruction(ILSETREG(
dsts[i], il.FloatMult(rsize, ILREG(srcs1[i]), ILREG(srcs2[0]))));
+ break;
+ }
+ default:
+ il.AddInstruction(il.Unimplemented());
}
break;
+ case ARM64_FNEG:
+ switch (instr.encoding)
+ {
+ case ENC_FNEG_D_FLOATDP1:
+ case ENC_FNEG_S_FLOATDP1:
+ case ENC_FNEG_H_FLOATDP1:
+ il.AddInstruction(ILSETREG_O(
+ operand1, il.FloatNeg(REGSZ_O(operand1), ILREG_O(operand2))));
+ break;
+ case ENC_FNEG_ASIMDMISCFP16_R:
+ case ENC_FNEG_ASIMDMISC_R:
+ {
+ if (preferIntrinsics())
+ return true;
+
+ Register srcs[16], dsts[16];
+ int dst_n = unpack_vector(operand1, dsts);
+ int src_n = unpack_vector(operand2, srcs);
+ if ((dst_n != src_n) || dst_n == 0)
+ ABORT_LIFT;
+
+ int rsize = get_register_size(dsts[0]);
+ for (int i = 0; i < dst_n; ++i)
+ il.AddInstruction(ILSETREG(dsts[i], il.FloatNeg(rsize, ILREG(srcs[i]))));
+ break;
+ }
default:
il.AddInstruction(il.Unimplemented());
}
break;
+ case ARM64_FNMUL:
+ il.AddInstruction(ILSETREG_O(operand1,
+ il.FloatNeg(REGSZ_O(operand1),
+ il.FloatMult(REGSZ_O(operand1), ILREG_O(operand2), ILREG_O(operand3)))));
+ break;
case ARM64_ERET:
case ARM64_ERETAA:
case ARM64_ERETAB:
@@ -1737,7 +1954,6 @@ bool GetLowLevelILForInstruction(
il.AddInstruction(il.Intrinsic({}, ARM64_INTRIN_ISB, {}));
break;
case ARM64_LDAR:
-
case ARM64_LDAPR:
case ARM64_LDAPUR:
LoadStoreOperand(il, true, instr.operands[0], instr.operands[1], 0);
@@ -1914,29 +2130,97 @@ bool GetLowLevelILForInstruction(
ILSETREG_O(operand1, il.LogicalShiftRight(REGSZ_O(operand2), ILREG_O(operand2),
ReadILOperand(il, operand3, REGSZ_O(operand2)))));
break;
+ case ARM64_DUP:
case ARM64_MOV:
+ case ARM64_MOVN:
+ case ARM64_UMOV:
+ case ARM64_INS:
+ case ARM64_MOVS:
{
- // Small hack... it doesn't seem the lifter ever see the ENC_DUP_ASISDONE_ONLY,
- // but instead ENC_MOV_DUP_ASISDONE_ONLY
- if (instr.encoding == ENC_MOV_DUP_ASISDONE_ONLY &&
- instr.operands[1].laneUsed)
- // Specific use case. e.g: [mov/dup] h16, v19.h[7].
+ bool zero_extend = false;
+ switch (instr.encoding)
+ {
+ case ENC_DUP_ASIMDINS_DR_R:
+ {
+ // if (preferIntrinsics())
+ // return true;
+
+ Register regs[16];
+ int regs_n = unpack_vector(operand1, regs);
+ if (regs_n <= 0)
+ ABORT_LIFT;
+ int lane_sz = REGSZ(regs[0]);
+ for (int i = 0; i < regs_n; ++i)
+ il.AddInstruction(ILSETREG(regs[i], ExtractRegister(il, operand2, 0, lane_sz, 0, lane_sz)));
+ break;
+ }
+ case ENC_DUP_ASIMDINS_DV_V:
// We let the Neon intrinsic lifter take care of this case.
break;
+ case ENC_MOV_UMOV_ASIMDINS_W_W:
+ case ENC_MOV_UMOV_ASIMDINS_X_X:
+ case ENC_UMOV_ASIMDINS_W_W:
+ case ENC_UMOV_ASIMDINS_X_X:
+ zero_extend = true;
+ case ENC_MOV_DUP_ASISDONE_ONLY:
+ case ENC_DUP_ASISDONE_ONLY:
+ case ENC_MOV_INS_ASIMDINS_IV_V:
+ case ENC_INS_ASIMDINS_IV_V:
+ {
+ Register srcs[16], dsts[16];
+ int dst_n = unpack_vector(operand1, dsts);
+ int src_n = unpack_vector(operand2, srcs);
+ if ((dst_n != src_n) || dst_n == 0)
+ ABORT_LIFT;
- Register regs[16];
- int n = unpack_vector(operand1, regs);
+ // if (dst_n > 1 && preferIntrinsics())
+ // return true;
- if (n == 1) {
- il.AddInstruction(ILSETREG(regs[0], ReadILOperand(il, operand2, get_register_size(regs[0]))));
- } else {
- Register cregs[2];
- if (consolidate_vector(operand1, operand2, cregs))
- il.AddInstruction(ILSETREG(cregs[0], ILREG(cregs[1])));
- else
- ABORT_LIFT;
+ for (int i = 0; i < dst_n; ++i)
+ il.AddInstruction(ILSETREG(dsts[i], zero_extend
+ ? il.ZeroExtend(REGSZ(dsts[i]), ILREG(srcs[i]))
+ : ILREG(srcs[i])));
+
+ break;
}
+ case ENC_MOV_MOVN_32_MOVEWIDE:
+ case ENC_MOV_MOVN_64_MOVEWIDE:
+ case ENC_MOVN_32_MOVEWIDE:
+ case ENC_MOVN_64_MOVEWIDE:
+ il.AddInstruction(ILSETREG_O(operand1,
+ ReadILOperand(il, operand2, REGSZ_O(operand1))));
+ break;
+ case ENC_MOV_INS_ASIMDINS_IR_R:
+ case ENC_INS_ASIMDINS_IR_R:
+ case ENC_MOV_ORR_32_LOG_IMM:
+ case ENC_MOV_ORR_32_LOG_SHIFT:
+ case ENC_MOV_ORR_64_LOG_IMM:
+ case ENC_MOV_ORR_64_LOG_SHIFT:
+ case ENC_MOV_ADD_32_ADDSUB_IMM:
+ case ENC_MOV_ADD_64_ADDSUB_IMM:
+ case ENC_MOV_ORR_ASIMDSAME_ONLY:
+ case ENC_MOV_MOVZ_32_MOVEWIDE:
+ case ENC_MOV_MOVZ_64_MOVEWIDE:
+ {
+ Register regs[16];
+ int n = unpack_vector(operand1, regs);
+ if (n == 1) {
+ il.AddInstruction(ILSETREG(regs[0], ReadILOperand(il, operand2, get_register_size(regs[0]))));
+ } else {
+ Register cregs[2];
+ if (consolidate_vector(operand1, operand2, cregs))
+ il.AddInstruction(ILSETREG(cregs[0], ILREG(cregs[1])));
+ else
+ ABORT_LIFT;
+ }
+ break;
+ }
+ default:
+ // case ENC_MOVS_ORRS_P_P_PP_Z:
+ // il.AddInstruction(il.Unimplemented());
+ break;
+ }
break;
}
case ARM64_MOVI:
@@ -1956,8 +2240,7 @@ bool GetLowLevelILForInstruction(
// zero the underling register slice
il.AddInstruction(ILSETREG_O(
operand1, il.And(REGSZ_O(operand1), ILREG_O(operand1),
- il.Not(REGSZ_O(operand1),
- il.Const(REGSZ_O(operand1), 0xffffULL << operand2.shiftValue)))));
+ il.Const(REGSZ_O(operand1), ~(0xffffULL << operand2.shiftValue)))));
// mov the immediate into it
il.AddInstruction(ILSETREG_O(
operand1, il.Or(REGSZ_O(operand1), ILREG_O(operand1),
@@ -1968,8 +2251,15 @@ bool GetLowLevelILForInstruction(
ILSETREG_O(operand1, il.Const(REGSZ_O(operand1), IMM_O(operand2) << operand2.shiftValue)));
break;
case ARM64_MUL:
- il.AddInstruction(
- ILSETREG_O(operand1, il.Mult(REGSZ_O(operand1), ILREG_O(operand2), ILREG_O(operand3))));
+ switch (instr.encoding)
+ {
+ case ENC_MUL_ASIMDSAME_ONLY:
+ case ENC_MUL_ASIMDELEM_R:
+ break;
+ default:
+ il.AddInstruction(
+ ILSETREG_O(operand1, il.Mult(REGSZ_O(operand1), ILREG_O(operand2), ILREG_O(operand3))));
+ }
break;
case ARM64_MADD:
il.AddInstruction(ILSETREG_O(operand1,
@@ -2167,9 +2457,32 @@ bool GetLowLevelILForInstruction(
break;
case ARM64_ORR:
case ARM64_ORRS:
- il.AddInstruction(
- ILSETREG_O(operand1, il.Or(REGSZ_O(operand1), ILREG_O(operand2),
- ReadILOperand(il, operand3, REGSZ_O(operand1)), SETFLAGS)));
+ switch (instr.encoding)
+ {
+ case ENC_ORR_32_LOG_IMM:
+ case ENC_ORR_32_LOG_SHIFT:
+ case ENC_ORR_64_LOG_IMM:
+ case ENC_ORR_64_LOG_SHIFT:
+ il.AddInstruction(
+ ILSETREG_O(operand1, il.Or(REGSZ_O(operand1), ILREG_O(operand2),
+ ReadILOperand(il, operand3, REGSZ_O(operand1)), SETFLAGS)));
+ break;
+ case ENC_ORR_ASIMDIMM_L_HL:
+ case ENC_ORR_ASIMDIMM_L_SL:
+ {
+ Register regs[16];
+ int n = unpack_vector(operand1, regs);
+ for (int i = 0; i < n; ++i)
+ il.AddInstruction(ILSETREG(regs[i], ILCONST_O(get_register_size(regs[i]), operand2)));
+ break;
+ }
+ case ENC_ORR_ASIMDSAME_ONLY:
+ // Let the neon intrinsic lifter take over.
+ break;
+ default:
+ il.AddInstruction(il.Unimplemented());
+ break;
+ }
break;
case ARM64_PSB:
il.AddInstruction(il.Intrinsic({}, ARM64_INTRIN_PSBCSYNC, {}));
@@ -2194,18 +2507,30 @@ bool GetLowLevelILForInstruction(
case ARM64_REV32:
case ARM64_REV64:
case ARM64_REV:
- if (IS_SVE_O(operand1))
- {
- il.AddInstruction(il.Unimplemented());
+ switch (instr.encoding) {
+ case ENC_REV16_ASIMDMISC_R:
+ case ENC_REV32_ASIMDMISC_R:
+ case ENC_REV64_ASIMDMISC_R:
break;
+ default:
+ if (IS_SVE_O(operand1))
+ {
+ il.AddInstruction(il.Unimplemented());
+ break;
+ }
+ // if LLIL_BSWAP ever gets added, replace
+ il.AddInstruction(il.Intrinsic(
+ {RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_REV, {ILREG_O(operand2)}));
}
- // if LLIL_BSWAP ever gets added, replace
- il.AddInstruction(il.Intrinsic(
- {RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_REV, {ILREG_O(operand2)}));
break;
case ARM64_RBIT:
- il.AddInstruction(il.Intrinsic(
- {RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_RBIT, {ILREG_O(operand2)}));
+ switch (instr.encoding) {
+ case ENC_RBIT_ASIMDMISC_R:
+ break;
+ default:
+ il.AddInstruction(il.Intrinsic(
+ {RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_RBIT, {ILREG_O(operand2)}));
+ }
break;
case ARM64_ROR:
il.AddInstruction(ILSETREG_O(operand1, il.RotateRight(REGSZ_O(operand2), ILREG_O(operand2),
@@ -2233,18 +2558,33 @@ bool GetLowLevelILForInstruction(
il.Const(1, (REGSZ_O(operand1) * 8) - IMM_O(operand4)))));
break;
case ARM64_SCVTF:
+ case ARM64_UCVTF:
+ {
+ bool zero_extend = false;
switch (instr.encoding)
{
// Scalar, float
+ case ENC_UCVTF_ASISDMISCFP16_R:
+ case ENC_UCVTF_ASISDMISC_R:
+ zero_extend = true;
case ENC_SCVTF_ASISDMISCFP16_R:
case ENC_SCVTF_ASISDMISC_R:
{
il.AddInstruction(ILSETREG_O(
operand1, il.IntToFloat(REGSZ_O(operand1),
- ILREG_O(operand2))));
+ zero_extend
+ ? il.ZeroExtend(REGSZ_O(operand1), ILREG_O(operand2))
+ : il.SignExtend(REGSZ_O(operand1), ILREG_O(operand2)))));
break;
}
// Scalar, integer
+ case ENC_UCVTF_D32_FLOAT2INT:
+ case ENC_UCVTF_D64_FLOAT2INT:
+ case ENC_UCVTF_H32_FLOAT2INT:
+ case ENC_UCVTF_H64_FLOAT2INT:
+ case ENC_UCVTF_S32_FLOAT2INT:
+ case ENC_UCVTF_S64_FLOAT2INT:
+ zero_extend = true;
case ENC_SCVTF_D32_FLOAT2INT:
case ENC_SCVTF_D64_FLOAT2INT:
case ENC_SCVTF_H32_FLOAT2INT:
@@ -2254,23 +2594,72 @@ bool GetLowLevelILForInstruction(
{
il.AddInstruction(ILSETREG_O(
operand1, il.IntToFloat(REGSZ_O(operand1),
- il.SignExtend(REGSZ_O(operand1), ILREG_O(operand2)))));
+ zero_extend
+ ? il.ZeroExtend(REGSZ_O(operand1), ILREG_O(operand2))
+ : il.SignExtend(REGSZ_O(operand1), ILREG_O(operand2)))));
+ break;
+ }
+ // Vector, single-precision and double-precision unsigned
+ case ENC_UCVTF_ASIMDMISC_R:
+ // Vector, half precision unsigned
+ case ENC_UCVTF_ASIMDMISCFP16_R:
+ zero_extend = true;
+ // Vector, single-precision and double-precision
+ case ENC_SCVTF_ASIMDMISC_R:
+ // Vector, half precision
+ case ENC_SCVTF_ASIMDMISCFP16_R:
+ {
+ if (preferIntrinsics())
+ return true;
+
+ Register cregs[2];
+ if (false && consolidate_vector(operand1, operand2, cregs))
+ il.AddInstruction(ILSETREG(cregs[0],
+ il.IntToFloat(REGSZ(cregs[0]),
+ zero_extend
+ ? il.ZeroExtend(REGSZ(cregs[0]), ILREG(cregs[1]))
+ : il.SignExtend(REGSZ(cregs[0]), ILREG(cregs[1])))));
+ else
+ {
+ // SCVTF <Vd>.<T>, <Vn>.<T>
+ Register srcs[16], dsts[16];
+ int dst_n = unpack_vector(operand1, dsts);
+ int src_n = unpack_vector(operand2, srcs);
+ if ((dst_n != src_n) || dst_n == 0)
+ ABORT_LIFT;
+
+ int rsize = get_register_size(dsts[0]);
+ for (int i = 0; i < dst_n; ++i)
+ il.AddInstruction(ILSETREG(dsts[i], il.IntToFloat(rsize,
+ zero_extend
+ ? il.ZeroExtend(rsize, ILREG(srcs[i]))
+ : il.SignExtend(rsize, ILREG(srcs[i])))));
+
+ }
break;
}
// Scalar, fixed-point (in SIMD&FP register)
case ENC_SCVTF_ASISDSHF_C:
- // Scalar, fixed-point (in GP register)
+ case ENC_UCVTF_ASISDSHF_C:
+ // Scalar, fixed-point (in GP register) [will fail because no intrinsics]
case ENC_SCVTF_D32_FLOAT2FIX:
case ENC_SCVTF_D64_FLOAT2FIX:
case ENC_SCVTF_H32_FLOAT2FIX:
case ENC_SCVTF_H64_FLOAT2FIX:
case ENC_SCVTF_S32_FLOAT2FIX:
case ENC_SCVTF_S64_FLOAT2FIX:
- // Vector, integer
- case ENC_SCVTF_ASIMDMISCFP16_R:
- case ENC_SCVTF_ASIMDMISC_R:
+ case ENC_UCVTF_D32_FLOAT2FIX:
+ case ENC_UCVTF_D64_FLOAT2FIX:
+ case ENC_UCVTF_H32_FLOAT2FIX:
+ case ENC_UCVTF_H64_FLOAT2FIX:
+ case ENC_UCVTF_S32_FLOAT2FIX:
+ case ENC_UCVTF_S64_FLOAT2FIX:
// Vector, fixed-point
case ENC_SCVTF_ASIMDSHF_C:
+ // Lift to instrinsics (except there are none)
+ case ENC_UCVTF_ASIMDSHF_C:
+ // Lift to instrinsics
+ break;
// SVE: Vector, integer
case ENC_SCVTF_Z_P_Z_H2FP16:
case ENC_SCVTF_Z_P_Z_W2D:
@@ -2279,12 +2668,19 @@ bool GetLowLevelILForInstruction(
case ENC_SCVTF_Z_P_Z_X2D:
case ENC_SCVTF_Z_P_Z_X2FP16:
case ENC_SCVTF_Z_P_Z_X2S:
- ABORT_LIFT;
+ case ENC_UCVTF_Z_P_Z_H2FP16:
+ case ENC_UCVTF_Z_P_Z_W2D:
+ case ENC_UCVTF_Z_P_Z_W2FP16:
+ case ENC_UCVTF_Z_P_Z_W2S:
+ case ENC_UCVTF_Z_P_Z_X2D:
+ case ENC_UCVTF_Z_P_Z_X2FP16:
+ case ENC_UCVTF_Z_P_Z_X2S:
break;
default:
break;
}
break;
+ }
case ARM64_SDIV:
il.AddInstruction(ILSETREG_O(
operand1, il.DivSigned(REGSZ_O(operand2), ILREG_O(operand2), ILREG_O(operand3))));
@@ -2313,6 +2709,102 @@ bool GetLowLevelILForInstruction(
break;
}
+ case ARM64_SSHL:
+ {
+ Register srcs1[16], srcs2[16], dsts[16];
+ int dst_n = unpack_vector(operand1, dsts);
+ int src1_n = unpack_vector(operand2, srcs1);
+ int src2_n = unpack_vector(operand3, srcs2);
+ if ((dst_n != src1_n) || (src1_n != src2_n) || dst_n == 0)
+ ABORT_LIFT;
+
+ int rsize = get_register_size(dsts[0]);
+ for (int i = 0; i < dst_n; ++i)
+ {
+ il.AddInstruction(il.SetRegister(rsize, dsts[i],
+ il.ShiftLeft(rsize,
+ il.SignExtend(rsize, il.Register(rsize, srcs1[i])),
+ il.Register(1, srcs2[i]))));
+ }
+
+ break;
+ }
+ case ARM64_SSHR:
+ {
+ // Note: we don't lift SRSHR, because it requires rounding the shifted results
+
+ Register srcs[16], dsts[16];
+ int dst_n = unpack_vector(operand1, dsts);
+ int src_n = unpack_vector(operand2, srcs);
+
+ if ((dst_n != src_n) || dst_n == 0)
+ ABORT_LIFT;
+
+ int rsize = get_register_size(dsts[0]);
+ for (int i = 0; i < dst_n; ++i)
+ {
+ il.AddInstruction(il.SetRegister(rsize, dsts[i],
+ il.ArithShiftRight(rsize, il.Register(rsize, srcs[i]), il.Const(1, IMM_O(operand3)))));
+ }
+
+ break;
+ }
+ case ARM64_SSHLL:
+ case ARM64_SSHLL2:
+ case ARM64_SXTL:
+ case ARM64_SXTL2:
+ if ((instr.encoding == ENC_SSHLL_ASIMDSHF_L || instr.encoding == ENC_SXTL_SSHLL_ASIMDSHF_L) && preferIntrinsics())
+ {
+ // // Not all valid operand combinations have intrinsics and we have to try it here in case it fails
+ // NeonGetLowLevelILForInstruction(arch, addr, il, instr, addrSize);
+ // LogWarn("NeonGetLowLevelILForInstruction: %d -> %d\n", n_instrs_before, il.GetInstructionCount());
+ // if (il.GetInstructionCount() > n_instrs_before)
+ // return true;
+ return true;
+ }
+ // SHLL{2} is the same as SHLL{2}, except the extension is signed or unsigned "without change of functionality"
+ // (The shift amount is the element size, but is still disassembled to the immediate value in the third operand)
+ case ARM64_SHLL:
+ case ARM64_SHLL2:
+ {
+ if (preferIntrinsics())
+ return true;
+
+ Register srcs[16], dsts[16];
+ int dst_n = unpack_vector(operand1, dsts);
+ int src_n = unpack_vector(operand2, srcs);
+
+ // We cannot check that the src and dst counts are the same here
+ // because the 2 variants use different count arrange specs, e.g.
+ // sxtl2 v0.2d, v1.4s
+ // (void) src_n;
+
+ int left_shift = 0;
+ if (instr.operation == ARM64_SSHLL || instr.operation == ARM64_SSHLL2 ||
+ instr.operation == ARM64_SHLL || instr.operation == ARM64_SHLL2)
+ left_shift = IMM_O(operand3);
+
+ int two_variant_offset = 0;
+ if (instr.operation == ARM64_SXTL2 || instr.operation == ARM64_SSHLL2 || instr.operation == ARM64_SHLL2)
+ two_variant_offset = src_n / 2;
+
+ int dst_size = get_register_size(dsts[0]);
+ int src_size = get_register_size(srcs[0]);
+
+ for (int i = 0; i < dst_n; ++i)
+ if (left_shift)
+ il.AddInstruction(il.SetRegister(dst_size, dsts[i],
+ il.ShiftLeft(dst_size,
+ il.SignExtend(dst_size,
+ il.Register(src_size, srcs[i + two_variant_offset])),
+ il.Const(1, left_shift))));
+ else
+ il.AddInstruction(il.SetRegister(dst_size, dsts[i],
+ il.SignExtend(dst_size,
+ il.Register(src_size, srcs[i + two_variant_offset]))));
+
+ break;
+ }
case ARM64_ST1:
LoadStoreVector(il, false, instr.operands[0], instr.operands[1]);
break;
@@ -2362,6 +2854,19 @@ bool GetLowLevelILForInstruction(
il.AddInstruction(il.SystemCall());
break;
}
+
+ case ARM64_SMOV:
+ {
+ Register srcs[16], dsts[16];
+ int dst_n = unpack_vector(operand1, dsts);
+ int src_n = unpack_vector(operand2, srcs);
+ if ((dst_n != src_n) || dst_n == 0)
+ ABORT_LIFT;
+
+ for (int i = 0; i < dst_n; ++i)
+ il.AddInstruction(ILSETREG(dsts[i], il.SignExtend(REGSZ(dsts[i]), ILREG(srcs[i]))));
+ break;
+ }
case ARM64_SWP: /* word (4) or doubleword (8) */
case ARM64_SWPA:
case ARM64_SWPL:
@@ -2432,25 +2937,50 @@ bool GetLowLevelILForInstruction(
break;
case ARM64_UXTL:
case ARM64_UXTL2:
+ case ARM64_USHLL:
+ case ARM64_USHLL2:
{
+ if ((instr.encoding == ENC_USHLL_ASIMDSHF_L || instr.encoding == ENC_UXTL_USHLL_ASIMDSHF_L) && preferIntrinsics())
+ {
+ // // Not all valid operand combinations have intrinsics and we have to try it here in case it fails
+ // NeonGetLowLevelILForInstruction(arch, addr, il, instr, addrSize);
+ // LogWarn("NeonGetLowLevelILForInstruction: %d -> %d\n", n_instrs_before, il.GetInstructionCount());
+ // if (il.GetInstructionCount() > n_instrs_before)
+ // return true;
+ return true;
+ }
+
Register srcs[16], dsts[16];
int dst_n = unpack_vector(operand1, dsts);
int src_n = unpack_vector(operand2, srcs);
- if (src_n == 0 || dst_n == 0)
- ABORT_LIFT;
- if (instr.operation == ARM64_UXTL && (src_n != dst_n))
- ABORT_LIFT;
- if (instr.operation == ARM64_UXTL2 && (src_n != 2 * dst_n))
- ABORT_LIFT;
+ // We cannot check that the src and dst counts are the same here
+ // because the 2 variants use different count arrange specs, e.g.
+ // uxtl2 v0.2d, v1.4s
+ (void) src_n;
+
+ int left_shift = 0;
+ if (instr.operation == ARM64_USHLL || instr.operation == ARM64_USHLL2)
+ left_shift = IMM_O(operand3);
+
+ int two_variant_offset = 0;
+ if (instr.operation == ARM64_UXTL2 || instr.operation == ARM64_USHLL2)
+ two_variant_offset = src_n / 2;
+
+ int dst_size = get_register_size(dsts[0]);
+ int src_size = get_register_size(srcs[0]);
for (int i = 0; i < dst_n; ++i)
- {
- if (instr.operation == ARM64_UXTL)
- il.AddInstruction(ILSETREG(dsts[i], ILREG(srcs[i])));
+ if (left_shift)
+ il.AddInstruction(il.SetRegister(dst_size, dsts[i],
+ il.ShiftLeft(dst_size,
+ il.ZeroExtend(dst_size,
+ il.Register(src_size, srcs[i + two_variant_offset])),
+ il.Const(1, left_shift))));
else
- il.AddInstruction(ILSETREG(dsts[i], ILREG(srcs[i + src_n / 2])));
- }
+ il.AddInstruction(il.SetRegister(dst_size, dsts[i],
+ il.ZeroExtend(dst_size,
+ il.Register(src_size, srcs[i + two_variant_offset]))));
break;
}
@@ -2459,8 +2989,43 @@ bool GetLowLevelILForInstruction(
il.Add(REGSZ_O(operand1), ILREG_O(operand4),
il.MultDoublePrecSigned(REGSZ_O(operand1), ILREG_O(operand2), ILREG_O(operand3)))));
break;
+ case ARM64_USHL:
+ {
+ switch (instr.encoding)
+ {
+ case ENC_USHL_ASIMDSAME_ONLY:
+ if (preferIntrinsics())
+ return true;
+
+ case ENC_USHL_ASISDSAME_ONLY:
+ default:
+ {
+ Register srcs1[16], srcs2[16], dsts[16];
+ int dst_n = unpack_vector(operand1, dsts);
+ int src1_n = unpack_vector(operand2, srcs1);
+ int src2_n = unpack_vector(operand3, srcs2);
+ if ((dst_n != src1_n) || (src1_n != src2_n) || dst_n == 0)
+ ABORT_LIFT;
+
+ int rsize = get_register_size(dsts[0]);
+ for (int i = 0; i < dst_n; ++i)
+ {
+ il.AddInstruction(il.SetRegister(rsize, dsts[i],
+ il.ShiftLeft(rsize,
+ il.Register(rsize, srcs1[i]),
+ il.Register(1, srcs2[i]))));
+ }
+ }
+ }
+ break;
+ }
case ARM64_USHR:
{
+ // Note: we don't lift URSHR, because it requires rounding the shifted results
+
+ if (preferIntrinsics())
+ return true;
+
Register srcs[16], dsts[16];
int dst_n = unpack_vector(operand1, dsts);
int src_n = unpack_vector(operand2, srcs);
@@ -2555,19 +3120,6 @@ bool GetLowLevelILForInstruction(
il.AddInstruction(
il.Trap(IMM_O(operand1))); // FIXME Breakpoint may need a parameter (IMM_O(operand1)));
return false;
- case ARM64_DUP:
- {
- if (instr.encoding != ENC_DUP_ASIMDINS_DR_R)
- break; // Abort lifting and let the neon intrinsic lifter take over.
- Register regs[16];
- int regs_n = unpack_vector(operand1, regs);
- if (regs_n <= 0)
- ABORT_LIFT;
- int lane_sz = REGSZ(regs[0]);
- for (int i = 0; i < regs_n; ++i)
- il.AddInstruction(ILSETREG(regs[i], ExtractRegister(il, operand2, 0, lane_sz, 0, lane_sz)));
- }
- break;
case ARM64_DGH:
il.AddInstruction(il.Intrinsic({}, ARM64_INTRIN_HINT_DGH, {}));
break;
diff --git a/arch/arm64/il.h b/arch/arm64/il.h
index 4ce5904c..e345e395 100644
--- a/arch/arm64/il.h
+++ b/arch/arm64/il.h
@@ -101,7 +101,7 @@ enum Arm64FakeRegister : uint32_t
};
bool GetLowLevelILForInstruction(BinaryNinja::Architecture* arch, uint64_t addr,
- BinaryNinja::LowLevelILFunction& il, Instruction& instr, size_t addrSize, bool alignmentRequired);
+ BinaryNinja::LowLevelILFunction& il, Instruction& instr, size_t addrSize, bool alignmentRequired, std::function<bool()> preferIntrinsics);
BinaryNinja::ExprId ExtractRegister(BinaryNinja::LowLevelILFunction& il,
InstructionOperand& operand, size_t regNum, size_t extractSize, bool signExtend,
diff --git a/arch/arm64/il_macros.h b/arch/arm64/il_macros.h
index c946e827..dfac029d 100644
--- a/arch/arm64/il_macros.h
+++ b/arch/arm64/il_macros.h
@@ -6,7 +6,7 @@
/* construct IL from a register id, immediate */
#define ILREG(R) il.Register(get_register_size(R), (R))
-#define ILSETREG(R, VALUE) il.SetRegister(get_register_size(R), (R), (VALUE))
+#define ILSETREG(R, VALUE) IS_ZERO_REG(R) ? (VALUE) : il.SetRegister(get_register_size(R), (R), (VALUE))
#define ILCONST(SZ, VAL) il.Const((SZ), (VAL))
/* helpers given a register id */
diff --git a/arch/arm64/misc/neon_intrins.c b/arch/arm64/misc/neon_intrins.c
index 181ee74e..ff0e5efc 100644
--- a/arch/arm64/misc/neon_intrins.c
+++ b/arch/arm64/misc/neon_intrins.c
@@ -1245,10 +1245,13 @@ float32x2_t vcvt_f32_s32(int32x2_t a); // SCVT
float32x4_t vcvtq_f32_s32(int32x4_t a); // SCVTF Vd.4S,Vn.4S
float32x2_t vcvt_f32_u32(uint32x2_t a); // UCVTF Vd.2S,Vn.2S
float32x4_t vcvtq_f32_u32(uint32x4_t a); // UCVTF Vd.4S,Vn.4S
+float32_t vcvts_f32_s32(int32_t a); // SCVTF Sd,Sn
float32_t vcvts_f32_u32(uint32_t a); // UCVTF Sd,Sn
+float64x1_t vcvt_f64_s64(int64x1_t a); // SCVTF Dd,Dn
float64x2_t vcvtq_f64_s64(int64x2_t a); // SCVTF Vd.2D,Vn.2D
float64x1_t vcvt_f64_u64(uint64x1_t a); // UCVTF Dd,Dn
float64x2_t vcvtq_f64_u64(uint64x2_t a); // UCVTF Vd.2D,Vn.2D
+float64_t vcvtd_f64_s64(int64_t a); // SCVTF Dd,Dn
float64_t vcvtd_f64_u64(uint64_t a); // UCVTF Dd,Dn
float32x2_t vcvt_n_f32_s32(int32x2_t a, const int n); // SCVTF Vd.2S,Vn.2S,#n
float32x4_t vcvtq_n_f32_s32(int32x4_t a, const int n); // SCVTF Vd.4S,Vn.4S,#n
@@ -4281,6 +4284,9 @@ uint16_t vcgezh_f16(float16_t a); // FCMGE Hd
uint16_t vcgtzh_f16(float16_t a); // FCMGT Hd,Hn,#0
uint16_t vclezh_f16(float16_t a); // FCMLE Hd,Hn,#0
uint16_t vcltzh_f16(float16_t a); // FCMLT Hd,Hn,#0
+float16_t vcvth_f16_s16(int16_t a); // SCVTF Hd,Hn
+float16_t vcvth_f16_s32(int32_t a); // SCVTF Hd,Hn
+float16_t vcvth_f16_s64(int64_t a); // SCVTF Hd,Hn
float16_t vcvth_f16_u16(uint16_t a); // UCVTF Hd,Hn
float16_t vcvth_f16_u32(uint32_t a); // UCVTF Hd,Hn
float16_t vcvth_f16_u64(uint64_t a); // UCVTF Hd,Hn
diff --git a/arch/arm64/neon_intrinsics.cpp b/arch/arm64/neon_intrinsics.cpp
index c8058137..84a4a146 100644
--- a/arch/arm64/neon_intrinsics.cpp
+++ b/arch/arm64/neon_intrinsics.cpp
@@ -1493,6 +1493,7 @@ string NeonGetIntrinsicName(uint32_t intrinsic)
return "vmax_u32";
case ARM64_INTRIN_VMAXQ_U32:
return "vmaxq_u32";
+ case ARM64_INTRIN_VMAX__F32:
case ARM64_INTRIN_VMAX_F32:
return "vmax_f32";
case ARM64_INTRIN_VMAXQ_F32:
@@ -1534,6 +1535,7 @@ string NeonGetIntrinsicName(uint32_t intrinsic)
case ARM64_INTRIN_VMINQ_F64:
return "vminq_f64";
case ARM64_INTRIN_VMAXNM_F32:
+ case ARM64_INTRIN_VMAXNM__F32:
return "vmaxnm_f32";
case ARM64_INTRIN_VMAXNMQ_F32:
return "vmaxnmq_f32";
@@ -3395,8 +3397,6 @@ string NeonGetIntrinsicName(uint32_t intrinsic)
return "vand_s32";
case ARM64_INTRIN_VANDQ_S32:
return "vandq_s32";
- case ARM64_INTRIN_VAND_S64:
- return "vand_s64";
case ARM64_INTRIN_VANDQ_S64:
return "vandq_s64";
case ARM64_INTRIN_VAND_U8:
@@ -7821,6 +7821,115 @@ string NeonGetIntrinsicName(uint32_t intrinsic)
return "vbfmlaltq_lane_f32";
case ARM64_INTRIN_VBFMLALTQ_LANEQ_F32:
return "vbfmlaltq_laneq_f32";
+ // fake
+ case ARM64_INTRIN_VCVTNS_S64_F32:
+ return "vcvtns_s64_f32";
+ case ARM64_INTRIN_VCVTN_S32_F64:
+ return "vcvtns_s32_f64";
+ case ARM64_INTRIN_VCVTD_N_F64_S32:
+ return "vcvts_n_f64_s32";
+ case ARM64_INTRIN_VCVTS_N_F32_S64:
+ return "vcvts_n_f32_s64";
+ case ARM64_INTRIN_VCVT_S32_F64:
+ return "vcvt_s32_f64";
+ case ARM64_INTRIN_VCVT_U32_F64:
+ return "vcvt_u32_f64";
+ case ARM64_INTRIN_VCVTA_S32_F64:
+ return "vcvta_s32_f64";
+ case ARM64_INTRIN_VCVTA_U32_F64:
+ return "vcvta_u32_f64";
+ case ARM64_INTRIN_VCVTAD_S32_F64:
+ return "vcvtad_s32_f64";
+ case ARM64_INTRIN_VCVTAD_U32_F64:
+ return "vcvtad_u32_f64";
+ case ARM64_INTRIN_VCVTAS_N_S32_F32:
+ return "vcvtas_n_s32_f32";
+ case ARM64_INTRIN_VCVTAS_N_U32_F32:
+ return "vcvtas_n_u32_f32";
+ case ARM64_INTRIN_VCVTD_S32_F64:
+ return "vcvtd_s32_f64";
+ case ARM64_INTRIN_VCVTD_U32_F64:
+ return "vcvtd_u32_f64";
+ case ARM64_INTRIN_VCVTM_S32_F64:
+ return "vcvtm_s32_f64";
+ case ARM64_INTRIN_VCVTM_U32_F64:
+ return "vcvtm_u32_f64";
+ case ARM64_INTRIN_VCVTMD_S32_F64:
+ return "vcvtmd_s32_f64";
+ case ARM64_INTRIN_VCVTMD_U32_F64:
+ return "vcvtmd_u32_f64";
+ case ARM64_INTRIN_VCVTMS_N_S32_F32:
+ return "vcvtms_n_s32_f32";
+ case ARM64_INTRIN_VCVTMS_N_U32_F32:
+ return "vcvtms_n_u32_f32";
+ case ARM64_INTRIN_VCVTN_U32_F64:
+ return "vcvtn_u32_f64";
+ case ARM64_INTRIN_VCVTND_S32_F64:
+ return "vcvtnd_s32_f64";
+ case ARM64_INTRIN_VCVTND_U32_F64:
+ return "vcvtnd_u32_f64";
+ case ARM64_INTRIN_VCVTP_S32_F64:
+ return "vcvtp_s32_f64";
+ case ARM64_INTRIN_VCVTP_U32_F64:
+ return "vcvtp_u32_f64";
+ case ARM64_INTRIN_VCVTPD_S32_F64:
+ return "vcvtpd_s32_f64";
+ case ARM64_INTRIN_VCVTPD_U32_F64:
+ return "vcvtpd_u32_f64";
+ case ARM64_INTRIN_VCVTPS_N_S32_F32:
+ return "vcvtps_n_s32_f32";
+ case ARM64_INTRIN_VCVTPS_N_U32_F32:
+ return "vcvtps_n_u32_f32";
+ case ARM64_INTRIN_VCVTA_N_S64_F64:
+ return "vcvta_n_s64_f64";
+ case ARM64_INTRIN_VCVTA_N_U64_F64:
+ return "vcvta_n_u64_f64";
+ case ARM64_INTRIN_VCVTAD_N_S64_F64:
+ return "vcvtad_n_s64_f64";
+ case ARM64_INTRIN_VCVTAD_N_U64_F64:
+ return "vcvtad_n_u64_f64";
+ case ARM64_INTRIN_VCVTM_N_S64_F64:
+ return "vcvtm_n_s64_f64";
+ case ARM64_INTRIN_VCVTM_N_U64_F64:
+ return "vcvtm_n_u64_f64";
+ case ARM64_INTRIN_VCVTMD_N_S64_F64:
+ return "vcvtmd_n_s64_f64";
+ case ARM64_INTRIN_VCVTMD_N_U64_F64:
+ return "vcvtmd_n_u64_f64";
+ case ARM64_INTRIN_VCVTP_N_S64_F64:
+ return "vcvtp_n_s64_f64";
+ case ARM64_INTRIN_VCVTP_N_U64_F64:
+ return "vcvtp_n_u64_f64";
+ case ARM64_INTRIN_VCVTPD_N_S64_F64:
+ return "vcvtpd_n_s64_f64";
+ case ARM64_INTRIN_VCVTPD_N_U64_F64:
+ return "vcvtpd_n_u64_f64";
+ case ARM64_INTRIN_VCVTNS_U64_F32:
+ return "vcvtns_u64_f32";
+ case ARM64_INTRIN_VCVTPS_U64_F32:
+ return "vcvtps_u64_f32";
+ case ARM64_INTRIN_VCVTPS_S64_F32:
+ return "vcvtps_s64_f32";
+ case ARM64_INTRIN_VCVTS_S64_F32:
+ return "vcvts_s64_f32";
+ case ARM64_INTRIN_VCVTS_U64_F32:
+ return "vcvts_u64_f32";
+ case ARM64_INTRIN_VCVTD_N_U32_F64:
+ return "vcvts_n_u32_f64";
+ case ARM64_INTRIN_VCVTS_N_U64_F32:
+ return "vcvts_n_u64_f32";
+ case ARM64_INTRIN_VCVTS_N_U32_F64:
+ return "vcvts_n_u32_f64";
+ case ARM64_INTRIN_VCVTS_N_U64_F64:
+ return "vcvts_n_u64_f64";
+ case ARM64_INTRIN_VCVT_U64_F32:
+ return "vcvt_n_u64_f32";
+ case ARM64_INTRIN_VCVTD_N_F64_F64:
+ return "vcvtd_n_f64_f64";
+ case ARM64_INTRIN_VAND_S64:
+ return "vand_s64";
+ case ARM64_INTRIN_VCVTD_N_U64_F32:
+ return "vcvtd_n_u64_f32";
default:
return "";
}
@@ -7830,3069 +7939,3266 @@ vector<NameAndType> NeonGetIntrinsicInputs(uint32_t intrinsic)
{
switch (intrinsic)
{
- case ARM64_INTRIN_VABSQ_F16:
- case ARM64_INTRIN_VABSQ_F32:
- case ARM64_INTRIN_VABSQ_F64:
- case ARM64_INTRIN_VADDVQ_F64:
- case ARM64_INTRIN_VCEQZQ_F16:
- case ARM64_INTRIN_VCEQZQ_F32:
- case ARM64_INTRIN_VCEQZQ_F64:
- case ARM64_INTRIN_VCGEZQ_F16:
- case ARM64_INTRIN_VCGEZQ_F32:
- case ARM64_INTRIN_VCGEZQ_F64:
- case ARM64_INTRIN_VCGTZQ_F16:
- case ARM64_INTRIN_VCGTZQ_F32:
- case ARM64_INTRIN_VCGTZQ_F64:
- case ARM64_INTRIN_VCLEZQ_F16:
- case ARM64_INTRIN_VCLEZQ_F32:
- case ARM64_INTRIN_VCLEZQ_F64:
- case ARM64_INTRIN_VCLTZQ_F16:
- case ARM64_INTRIN_VCLTZQ_F32:
- case ARM64_INTRIN_VCLTZQ_F64:
- case ARM64_INTRIN_VCVT_BF16_F32:
- case ARM64_INTRIN_VCVT_F16_F32:
- case ARM64_INTRIN_VCVT_F32_F64:
- case ARM64_INTRIN_VCVT_HIGH_F32_F16:
- case ARM64_INTRIN_VCVT_HIGH_F64_F32:
- case ARM64_INTRIN_VCVTAQ_S16_F16:
- case ARM64_INTRIN_VCVTAQ_S32_F32:
- case ARM64_INTRIN_VCVTAQ_S64_F64:
- case ARM64_INTRIN_VCVTAQ_U16_F16:
- case ARM64_INTRIN_VCVTAQ_U32_F32:
- case ARM64_INTRIN_VCVTAQ_U64_F64:
- case ARM64_INTRIN_VCVTMQ_S16_F16:
- case ARM64_INTRIN_VCVTMQ_S32_F32:
- case ARM64_INTRIN_VCVTMQ_S64_F64:
- case ARM64_INTRIN_VCVTMQ_U16_F16:
- case ARM64_INTRIN_VCVTMQ_U32_F32:
- case ARM64_INTRIN_VCVTMQ_U64_F64:
- case ARM64_INTRIN_VCVTNQ_S16_F16:
- case ARM64_INTRIN_VCVTNQ_S32_F32:
- case ARM64_INTRIN_VCVTNQ_S64_F64:
- case ARM64_INTRIN_VCVTNQ_U16_F16:
- case ARM64_INTRIN_VCVTNQ_U32_F32:
- case ARM64_INTRIN_VCVTNQ_U64_F64:
- case ARM64_INTRIN_VCVTPQ_S16_F16:
- case ARM64_INTRIN_VCVTPQ_S32_F32:
- case ARM64_INTRIN_VCVTPQ_S64_F64:
- case ARM64_INTRIN_VCVTPQ_U16_F16:
- case ARM64_INTRIN_VCVTPQ_U32_F32:
- case ARM64_INTRIN_VCVTPQ_U64_F64:
- case ARM64_INTRIN_VCVTQ_HIGH_F32_BF16:
- case ARM64_INTRIN_VCVTQ_LOW_BF16_F32:
- case ARM64_INTRIN_VCVTQ_LOW_F32_BF16:
- case ARM64_INTRIN_VCVTQ_S16_F16:
- case ARM64_INTRIN_VCVTQ_S32_F32:
- case ARM64_INTRIN_VCVTQ_S64_F64:
- case ARM64_INTRIN_VCVTQ_U16_F16:
- case ARM64_INTRIN_VCVTQ_U32_F32:
- case ARM64_INTRIN_VCVTQ_U64_F64:
- case ARM64_INTRIN_VCVTX_F32_F64:
- case ARM64_INTRIN_VGET_HIGH_BF16:
- case ARM64_INTRIN_VGET_HIGH_F16:
- case ARM64_INTRIN_VGET_HIGH_F32:
- case ARM64_INTRIN_VGET_HIGH_F64:
- case ARM64_INTRIN_VGET_LOW_BF16:
- case ARM64_INTRIN_VGET_LOW_F16:
- case ARM64_INTRIN_VGET_LOW_F32:
- case ARM64_INTRIN_VGET_LOW_F64:
- case ARM64_INTRIN_VMAXNMVQ_F16:
- case ARM64_INTRIN_VMAXNMVQ_F32:
- case ARM64_INTRIN_VMAXNMVQ_F64:
- case ARM64_INTRIN_VMAXVQ_F16:
- case ARM64_INTRIN_VMAXVQ_F32:
- case ARM64_INTRIN_VMAXVQ_F64:
- case ARM64_INTRIN_VMINNMVQ_F16:
- case ARM64_INTRIN_VMINNMVQ_F32:
- case ARM64_INTRIN_VMINNMVQ_F64:
- case ARM64_INTRIN_VMINVQ_F16:
- case ARM64_INTRIN_VMINVQ_F32:
- case ARM64_INTRIN_VMINVQ_F64:
- case ARM64_INTRIN_VNEGQ_F16:
- case ARM64_INTRIN_VNEGQ_F32:
- case ARM64_INTRIN_VNEGQ_F64:
- case ARM64_INTRIN_VPADDD_F64:
- case ARM64_INTRIN_VPMAXNMQD_F64:
- case ARM64_INTRIN_VPMAXQD_F64:
- case ARM64_INTRIN_VPMINNMQD_F64:
- case ARM64_INTRIN_VPMINQD_F64:
- case ARM64_INTRIN_VRECPEQ_F16:
- case ARM64_INTRIN_VRECPEQ_F32:
- case ARM64_INTRIN_VRECPEQ_F64:
- case ARM64_INTRIN_VREV64Q_F16:
- case ARM64_INTRIN_VREV64Q_F32:
- case ARM64_INTRIN_VRND32XQ_F32:
- case ARM64_INTRIN_VRND32XQ_F64:
- case ARM64_INTRIN_VRND32ZQ_F32:
- case ARM64_INTRIN_VRND32ZQ_F64:
- case ARM64_INTRIN_VRND64XQ_F32:
- case ARM64_INTRIN_VRND64XQ_F64:
- case ARM64_INTRIN_VRND64ZQ_F32:
- case ARM64_INTRIN_VRND64ZQ_F64:
- case ARM64_INTRIN_VRNDAQ_F16:
- case ARM64_INTRIN_VRNDAQ_F32:
- case ARM64_INTRIN_VRNDAQ_F64:
- case ARM64_INTRIN_VRNDIQ_F16:
- case ARM64_INTRIN_VRNDIQ_F32:
- case ARM64_INTRIN_VRNDIQ_F64:
- case ARM64_INTRIN_VRNDMQ_F16:
- case ARM64_INTRIN_VRNDMQ_F32:
- case ARM64_INTRIN_VRNDMQ_F64:
- case ARM64_INTRIN_VRNDNQ_F16:
- case ARM64_INTRIN_VRNDNQ_F32:
- case ARM64_INTRIN_VRNDNQ_F64:
- case ARM64_INTRIN_VRNDPQ_F16:
- case ARM64_INTRIN_VRNDPQ_F32:
- case ARM64_INTRIN_VRNDPQ_F64:
- case ARM64_INTRIN_VRNDQ_F16:
- case ARM64_INTRIN_VRNDQ_F32:
- case ARM64_INTRIN_VRNDQ_F64:
- case ARM64_INTRIN_VRNDXQ_F16:
- case ARM64_INTRIN_VRNDXQ_F32:
- case ARM64_INTRIN_VRNDXQ_F64:
- case ARM64_INTRIN_VRSQRTEQ_F16:
- case ARM64_INTRIN_VRSQRTEQ_F32:
- case ARM64_INTRIN_VRSQRTEQ_F64:
- case ARM64_INTRIN_VSQRTQ_F16:
- case ARM64_INTRIN_VSQRTQ_F32:
- case ARM64_INTRIN_VSQRTQ_F64:
- return {NameAndType(Type::FloatType(16))};
- case ARM64_INTRIN_VABDQ_F16:
- case ARM64_INTRIN_VABDQ_F32:
- case ARM64_INTRIN_VABDQ_F64:
- case ARM64_INTRIN_VADDQ_F16:
- case ARM64_INTRIN_VADDQ_F32:
- case ARM64_INTRIN_VADDQ_F64:
- case ARM64_INTRIN_VCADDQ_ROT270_F16:
- case ARM64_INTRIN_VCADDQ_ROT270_F32:
- case ARM64_INTRIN_VCADDQ_ROT270_F64:
- case ARM64_INTRIN_VCADDQ_ROT90_F16:
- case ARM64_INTRIN_VCADDQ_ROT90_F32:
- case ARM64_INTRIN_VCADDQ_ROT90_F64:
- case ARM64_INTRIN_VCAGEQ_F16:
- case ARM64_INTRIN_VCAGEQ_F32:
- case ARM64_INTRIN_VCAGEQ_F64:
- case ARM64_INTRIN_VCAGTQ_F16:
- case ARM64_INTRIN_VCAGTQ_F32:
- case ARM64_INTRIN_VCAGTQ_F64:
- case ARM64_INTRIN_VCALEQ_F16:
- case ARM64_INTRIN_VCALEQ_F32:
- case ARM64_INTRIN_VCALEQ_F64:
- case ARM64_INTRIN_VCALTQ_F16:
- case ARM64_INTRIN_VCALTQ_F32:
- case ARM64_INTRIN_VCALTQ_F64:
- case ARM64_INTRIN_VCEQQ_F16:
- case ARM64_INTRIN_VCEQQ_F32:
- case ARM64_INTRIN_VCEQQ_F64:
- case ARM64_INTRIN_VCGEQ_F16:
- case ARM64_INTRIN_VCGEQ_F32:
- case ARM64_INTRIN_VCGEQ_F64:
- case ARM64_INTRIN_VCGTQ_F16:
- case ARM64_INTRIN_VCGTQ_F32:
- case ARM64_INTRIN_VCGTQ_F64:
- case ARM64_INTRIN_VCLEQ_F16:
- case ARM64_INTRIN_VCLEQ_F32:
- case ARM64_INTRIN_VCLEQ_F64:
- case ARM64_INTRIN_VCLTQ_F16:
- case ARM64_INTRIN_VCLTQ_F32:
- case ARM64_INTRIN_VCLTQ_F64:
- case ARM64_INTRIN_VCVTQ_HIGH_BF16_F32:
- case ARM64_INTRIN_VDIVQ_F16:
- case ARM64_INTRIN_VDIVQ_F32:
- case ARM64_INTRIN_VDIVQ_F64:
- case ARM64_INTRIN_VMAXNMQ_F16:
- case ARM64_INTRIN_VMAXNMQ_F32:
- case ARM64_INTRIN_VMAXNMQ_F64:
- case ARM64_INTRIN_VMAXQ_F16:
- case ARM64_INTRIN_VMAXQ_F32:
- case ARM64_INTRIN_VMAXQ_F64:
- case ARM64_INTRIN_VMINNMQ_F16:
- case ARM64_INTRIN_VMINNMQ_F32:
- case ARM64_INTRIN_VMINNMQ_F64:
- case ARM64_INTRIN_VMINQ_F16:
- case ARM64_INTRIN_VMINQ_F32:
- case ARM64_INTRIN_VMINQ_F64:
- case ARM64_INTRIN_VMULQ_F16:
- case ARM64_INTRIN_VMULQ_F32:
- case ARM64_INTRIN_VMULQ_F64:
- case ARM64_INTRIN_VMULXQ_F16:
- case ARM64_INTRIN_VMULXQ_F32:
- case ARM64_INTRIN_VMULXQ_F64:
- case ARM64_INTRIN_VPADDQ_F16:
- case ARM64_INTRIN_VPADDQ_F32:
- case ARM64_INTRIN_VPADDQ_F64:
- case ARM64_INTRIN_VPMAXNMQ_F16:
- case ARM64_INTRIN_VPMAXNMQ_F32:
- case ARM64_INTRIN_VPMAXNMQ_F64:
- case ARM64_INTRIN_VPMAXQ_F16:
- case ARM64_INTRIN_VPMAXQ_F32:
- case ARM64_INTRIN_VPMAXQ_F64:
- case ARM64_INTRIN_VPMINNMQ_F16:
- case ARM64_INTRIN_VPMINNMQ_F32:
- case ARM64_INTRIN_VPMINNMQ_F64:
- case ARM64_INTRIN_VPMINQ_F16:
- case ARM64_INTRIN_VPMINQ_F32:
- case ARM64_INTRIN_VPMINQ_F64:
- case ARM64_INTRIN_VRECPSQ_F16:
- case ARM64_INTRIN_VRECPSQ_F32:
- case ARM64_INTRIN_VRECPSQ_F64:
- case ARM64_INTRIN_VRSQRTSQ_F16:
- case ARM64_INTRIN_VRSQRTSQ_F32:
- case ARM64_INTRIN_VRSQRTSQ_F64:
- case ARM64_INTRIN_VSUBQ_F16:
- case ARM64_INTRIN_VSUBQ_F32:
- case ARM64_INTRIN_VSUBQ_F64:
- case ARM64_INTRIN_VTRN1Q_F16:
- case ARM64_INTRIN_VTRN1Q_F32:
- case ARM64_INTRIN_VTRN1Q_F64:
- case ARM64_INTRIN_VTRN2Q_F16:
- case ARM64_INTRIN_VTRN2Q_F32:
- case ARM64_INTRIN_VTRN2Q_F64:
- case ARM64_INTRIN_VUZP1Q_F16:
- case ARM64_INTRIN_VUZP1Q_F32:
- case ARM64_INTRIN_VUZP1Q_F64:
- case ARM64_INTRIN_VUZP2Q_F16:
- case ARM64_INTRIN_VUZP2Q_F32:
- case ARM64_INTRIN_VUZP2Q_F64:
- case ARM64_INTRIN_VZIP1Q_F16:
- case ARM64_INTRIN_VZIP1Q_F32:
- case ARM64_INTRIN_VZIP1Q_F64:
- case ARM64_INTRIN_VZIP2Q_F16:
- case ARM64_INTRIN_VZIP2Q_F32:
- case ARM64_INTRIN_VZIP2Q_F64:
- return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16))};
- case ARM64_INTRIN_VBFDOTQ_F32:
- case ARM64_INTRIN_VBFMLALBQ_F32:
- case ARM64_INTRIN_VBFMLALTQ_F32:
- case ARM64_INTRIN_VBFMMLAQ_F32:
- case ARM64_INTRIN_VCMLAQ_F16:
- case ARM64_INTRIN_VCMLAQ_F32:
- case ARM64_INTRIN_VCMLAQ_F64:
- case ARM64_INTRIN_VCMLAQ_ROT180_F16:
- case ARM64_INTRIN_VCMLAQ_ROT180_F32:
- case ARM64_INTRIN_VCMLAQ_ROT180_F64:
- case ARM64_INTRIN_VCMLAQ_ROT270_F16:
- case ARM64_INTRIN_VCMLAQ_ROT270_F32:
- case ARM64_INTRIN_VCMLAQ_ROT270_F64:
- case ARM64_INTRIN_VCMLAQ_ROT90_F16:
- case ARM64_INTRIN_VCMLAQ_ROT90_F32:
- case ARM64_INTRIN_VCMLAQ_ROT90_F64:
- case ARM64_INTRIN_VFMAQ_F16:
- case ARM64_INTRIN_VFMAQ_F32:
- case ARM64_INTRIN_VFMAQ_F64:
- case ARM64_INTRIN_VFMLALQ_HIGH_F16:
- case ARM64_INTRIN_VFMLALQ_LOW_F16:
- case ARM64_INTRIN_VFMLSLQ_HIGH_F16:
- case ARM64_INTRIN_VFMLSLQ_LOW_F16:
- case ARM64_INTRIN_VFMSQ_F16:
- case ARM64_INTRIN_VFMSQ_F32:
- case ARM64_INTRIN_VFMSQ_F64:
- return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16)),
- NameAndType(Type::FloatType(16))};
- case ARM64_INTRIN_VBFDOTQ_LANEQ_F32:
- case ARM64_INTRIN_VBFMLALBQ_LANEQ_F32:
- case ARM64_INTRIN_VBFMLALTQ_LANEQ_F32:
- case ARM64_INTRIN_VCMLAQ_LANEQ_F16:
- case ARM64_INTRIN_VCMLAQ_LANEQ_F32:
- case ARM64_INTRIN_VCMLAQ_ROT180_LANEQ_F16:
- case ARM64_INTRIN_VCMLAQ_ROT180_LANEQ_F32:
- case ARM64_INTRIN_VCMLAQ_ROT270_LANEQ_F16:
- case ARM64_INTRIN_VCMLAQ_ROT270_LANEQ_F32:
- case ARM64_INTRIN_VCMLAQ_ROT90_LANEQ_F16:
- case ARM64_INTRIN_VCMLAQ_ROT90_LANEQ_F32:
- case ARM64_INTRIN_VFMAQ_LANEQ_F16:
- case ARM64_INTRIN_VFMAQ_LANEQ_F32:
- case ARM64_INTRIN_VFMAQ_LANEQ_F64:
- case ARM64_INTRIN_VFMLALQ_LANEQ_HIGH_F16:
- case ARM64_INTRIN_VFMLALQ_LANEQ_LOW_F16:
- case ARM64_INTRIN_VFMLSLQ_LANEQ_HIGH_F16:
- case ARM64_INTRIN_VFMLSLQ_LANEQ_LOW_F16:
- case ARM64_INTRIN_VFMSQ_LANEQ_F16:
- case ARM64_INTRIN_VFMSQ_LANEQ_F32:
- case ARM64_INTRIN_VFMSQ_LANEQ_F64:
- return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16)),
- NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VFMAQ_N_F16:
- case ARM64_INTRIN_VFMSQ_N_F16:
- return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16)),
- NameAndType(Type::FloatType(2))};
- case ARM64_INTRIN_VFMAQ_N_F32:
- case ARM64_INTRIN_VFMSQ_N_F32:
- return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16)),
- NameAndType(Type::FloatType(4))};
- case ARM64_INTRIN_VFMAQ_N_F64:
- case ARM64_INTRIN_VFMSQ_N_F64:
- return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16)),
- NameAndType(Type::FloatType(8))};
- case ARM64_INTRIN_VBFDOTQ_LANE_F32:
- case ARM64_INTRIN_VBFMLALBQ_LANE_F32:
- case ARM64_INTRIN_VBFMLALTQ_LANE_F32:
- case ARM64_INTRIN_VCMLAQ_LANE_F16:
- case ARM64_INTRIN_VCMLAQ_LANE_F32:
- case ARM64_INTRIN_VCMLAQ_ROT180_LANE_F16:
- case ARM64_INTRIN_VCMLAQ_ROT180_LANE_F32:
- case ARM64_INTRIN_VCMLAQ_ROT270_LANE_F16:
- case ARM64_INTRIN_VCMLAQ_ROT270_LANE_F32:
- case ARM64_INTRIN_VCMLAQ_ROT90_LANE_F16:
- case ARM64_INTRIN_VCMLAQ_ROT90_LANE_F32:
- case ARM64_INTRIN_VFMAQ_LANE_F16:
- case ARM64_INTRIN_VFMAQ_LANE_F32:
- case ARM64_INTRIN_VFMAQ_LANE_F64:
- case ARM64_INTRIN_VFMLALQ_LANE_HIGH_F16:
- case ARM64_INTRIN_VFMLALQ_LANE_LOW_F16:
- case ARM64_INTRIN_VFMLSLQ_LANE_HIGH_F16:
- case ARM64_INTRIN_VFMLSLQ_LANE_LOW_F16:
- case ARM64_INTRIN_VFMSQ_LANE_F16:
- case ARM64_INTRIN_VFMSQ_LANE_F32:
- case ARM64_INTRIN_VFMSQ_LANE_F64:
- return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16)),
- NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VEXTQ_F16:
- case ARM64_INTRIN_VEXTQ_F32:
- case ARM64_INTRIN_VEXTQ_F64:
- case ARM64_INTRIN_VMULQ_LANEQ_F16:
- case ARM64_INTRIN_VMULQ_LANEQ_F32:
- case ARM64_INTRIN_VMULQ_LANEQ_F64:
- case ARM64_INTRIN_VMULXQ_LANEQ_F16:
- case ARM64_INTRIN_VMULXQ_LANEQ_F32:
- case ARM64_INTRIN_VMULXQ_LANEQ_F64:
- return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VMULQ_N_F16:
- case ARM64_INTRIN_VMULXQ_N_F16:
- return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(2))};
- case ARM64_INTRIN_VMULQ_N_F32:
- return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(4))};
- case ARM64_INTRIN_VMULQ_N_F64:
- return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(8))};
- case ARM64_INTRIN_VMULQ_LANE_F16:
- case ARM64_INTRIN_VMULQ_LANE_F32:
- case ARM64_INTRIN_VMULQ_LANE_F64:
- case ARM64_INTRIN_VMULXQ_LANE_F16:
- case ARM64_INTRIN_VMULXQ_LANE_F32:
- case ARM64_INTRIN_VMULXQ_LANE_F64:
- return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(8)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VCVTQ_N_S16_F16:
- case ARM64_INTRIN_VCVTQ_N_S32_F32:
- case ARM64_INTRIN_VCVTQ_N_S64_F64:
- case ARM64_INTRIN_VCVTQ_N_U16_F16:
- case ARM64_INTRIN_VCVTQ_N_U32_F32:
- case ARM64_INTRIN_VCVTQ_N_U64_F64:
- case ARM64_INTRIN_VDUP_LANEQ_BF16:
- case ARM64_INTRIN_VDUP_LANEQ_F16:
- case ARM64_INTRIN_VDUP_LANEQ_F32:
- case ARM64_INTRIN_VDUP_LANEQ_F64:
- case ARM64_INTRIN_VDUPD_LANEQ_F64:
- case ARM64_INTRIN_VDUPH_LANEQ_BF16:
- case ARM64_INTRIN_VDUPH_LANEQ_F16:
- case ARM64_INTRIN_VDUPQ_LANEQ_BF16:
- case ARM64_INTRIN_VDUPQ_LANEQ_F16:
- case ARM64_INTRIN_VDUPQ_LANEQ_F32:
- case ARM64_INTRIN_VDUPQ_LANEQ_F64:
- case ARM64_INTRIN_VDUPS_LANEQ_F32:
- case ARM64_INTRIN_VGETQ_LANE_BF16:
- case ARM64_INTRIN_VGETQ_LANE_F16:
- case ARM64_INTRIN_VGETQ_LANE_F32:
- case ARM64_INTRIN_VGETQ_LANE_F64:
- return {NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VABSH_F16:
- case ARM64_INTRIN_VCEQZH_F16:
- case ARM64_INTRIN_VCGEZH_F16:
- case ARM64_INTRIN_VCGTZH_F16:
- case ARM64_INTRIN_VCLEZH_F16:
- case ARM64_INTRIN_VCLTZH_F16:
- case ARM64_INTRIN_VCVTAH_F32_BF16:
- case ARM64_INTRIN_VCVTAH_S16_F16:
- case ARM64_INTRIN_VCVTAH_S32_F16:
- case ARM64_INTRIN_VCVTAH_S64_F16:
- case ARM64_INTRIN_VCVTAH_U16_F16:
- case ARM64_INTRIN_VCVTAH_U32_F16:
- case ARM64_INTRIN_VCVTAH_U64_F16:
- case ARM64_INTRIN_VCVTH_S16_F16:
- case ARM64_INTRIN_VCVTH_S32_F16:
- case ARM64_INTRIN_VCVTH_S64_F16:
- case ARM64_INTRIN_VCVTH_U16_F16:
- case ARM64_INTRIN_VCVTH_U32_F16:
- case ARM64_INTRIN_VCVTH_U64_F16:
- case ARM64_INTRIN_VCVTMH_S16_F16:
- case ARM64_INTRIN_VCVTMH_S32_F16:
- case ARM64_INTRIN_VCVTMH_S64_F16:
- case ARM64_INTRIN_VCVTMH_U16_F16:
- case ARM64_INTRIN_VCVTMH_U32_F16:
- case ARM64_INTRIN_VCVTMH_U64_F16:
- case ARM64_INTRIN_VCVTNH_S16_F16:
- case ARM64_INTRIN_VCVTNH_S32_F16:
- case ARM64_INTRIN_VCVTNH_S64_F16:
- case ARM64_INTRIN_VCVTNH_U16_F16:
- case ARM64_INTRIN_VCVTNH_U32_F16:
- case ARM64_INTRIN_VCVTNH_U64_F16:
- case ARM64_INTRIN_VCVTPH_S16_F16:
- case ARM64_INTRIN_VCVTPH_S32_F16:
- case ARM64_INTRIN_VCVTPH_S64_F16:
- case ARM64_INTRIN_VCVTPH_U16_F16:
- case ARM64_INTRIN_VCVTPH_U32_F16:
- case ARM64_INTRIN_VCVTPH_U64_F16:
- case ARM64_INTRIN_VDUP_N_BF16:
- case ARM64_INTRIN_VDUP_N_F16:
- case ARM64_INTRIN_VDUPQ_N_BF16:
- case ARM64_INTRIN_VDUPQ_N_F16:
- case ARM64_INTRIN_VMOV_N_F16:
- case ARM64_INTRIN_VMOVQ_N_F16:
- case ARM64_INTRIN_VNEGH_F16:
- case ARM64_INTRIN_VRECPEH_F16:
- case ARM64_INTRIN_VRECPXH_F16:
- case ARM64_INTRIN_VRNDAH_F16:
- case ARM64_INTRIN_VRNDH_F16:
- case ARM64_INTRIN_VRNDIH_F16:
- case ARM64_INTRIN_VRNDMH_F16:
- case ARM64_INTRIN_VRNDNH_F16:
- case ARM64_INTRIN_VRNDPH_F16:
- case ARM64_INTRIN_VRNDXH_F16:
- case ARM64_INTRIN_VRSQRTEH_F16:
- case ARM64_INTRIN_VSQRTH_F16:
- return {NameAndType(Type::FloatType(2))};
- case ARM64_INTRIN_VMULH_LANEQ_F16:
- case ARM64_INTRIN_VMULXH_LANEQ_F16:
- case ARM64_INTRIN_VSETQ_LANE_BF16:
- case ARM64_INTRIN_VSETQ_LANE_F16:
- return {NameAndType(Type::FloatType(2)), NameAndType(Type::FloatType(16)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VABDH_F16:
- case ARM64_INTRIN_VADDH_F16:
- case ARM64_INTRIN_VCAGEH_F16:
- case ARM64_INTRIN_VCAGTH_F16:
- case ARM64_INTRIN_VCALEH_F16:
- case ARM64_INTRIN_VCALTH_F16:
- case ARM64_INTRIN_VCEQH_F16:
- case ARM64_INTRIN_VCGEH_F16:
- case ARM64_INTRIN_VCGTH_F16:
- case ARM64_INTRIN_VCLEH_F16:
- case ARM64_INTRIN_VCLTH_F16:
- case ARM64_INTRIN_VDIVH_F16:
- case ARM64_INTRIN_VMAXH_F16:
- case ARM64_INTRIN_VMAXNMH_F16:
- case ARM64_INTRIN_VMINH_F16:
- case ARM64_INTRIN_VMINNMH_F16:
- case ARM64_INTRIN_VMULH_F16:
- case ARM64_INTRIN_VMULXH_F16:
- case ARM64_INTRIN_VRECPSH_F16:
- case ARM64_INTRIN_VRSQRTSH_F16:
- case ARM64_INTRIN_VSUBH_F16:
- return {NameAndType(Type::FloatType(2)), NameAndType(Type::FloatType(2))};
- case ARM64_INTRIN_VFMAH_LANEQ_F16:
- case ARM64_INTRIN_VFMSH_LANEQ_F16:
- return {NameAndType(Type::FloatType(2)), NameAndType(Type::FloatType(2)),
- NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VFMAH_F16:
- case ARM64_INTRIN_VFMSH_F16:
- return {NameAndType(Type::FloatType(2)), NameAndType(Type::FloatType(2)),
- NameAndType(Type::FloatType(2))};
- case ARM64_INTRIN_VFMAH_LANE_F16:
- case ARM64_INTRIN_VFMSH_LANE_F16:
- return {NameAndType(Type::FloatType(2)), NameAndType(Type::FloatType(2)),
- NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VMULH_LANE_F16:
- case ARM64_INTRIN_VMULXH_LANE_F16:
- case ARM64_INTRIN_VSET_LANE_BF16:
- case ARM64_INTRIN_VSET_LANE_F16:
- return {NameAndType(Type::FloatType(2)), NameAndType(Type::FloatType(8)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VCVTH_N_S16_F16:
- case ARM64_INTRIN_VCVTH_N_S32_F16:
- case ARM64_INTRIN_VCVTH_N_S64_F16:
- case ARM64_INTRIN_VCVTH_N_U16_F16:
- case ARM64_INTRIN_VCVTH_N_U32_F16:
- case ARM64_INTRIN_VCVTH_N_U64_F16:
- return {NameAndType(Type::FloatType(2)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VCEQZS_F32:
- case ARM64_INTRIN_VCGEZS_F32:
- case ARM64_INTRIN_VCGTZS_F32:
- case ARM64_INTRIN_VCLEZS_F32:
- case ARM64_INTRIN_VCLTZS_F32:
- case ARM64_INTRIN_VCVTAS_S32_F32:
- case ARM64_INTRIN_VCVTAS_U32_F32:
- case ARM64_INTRIN_VCVTH_BF16_F32:
- case ARM64_INTRIN_VCVTMS_S32_F32:
- case ARM64_INTRIN_VCVTMS_U32_F32:
- case ARM64_INTRIN_VCVTNS_S32_F32:
- case ARM64_INTRIN_VCVTNS_U32_F32:
- case ARM64_INTRIN_VCVTPS_S32_F32:
- case ARM64_INTRIN_VCVTPS_U32_F32:
- case ARM64_INTRIN_VCVTS_S32_F32:
- case ARM64_INTRIN_VCVTS_U32_F32:
- case ARM64_INTRIN_VDUP_N_F32:
- case ARM64_INTRIN_VDUPQ_N_F32:
- case ARM64_INTRIN_VMOV_N_F32:
- case ARM64_INTRIN_VMOVQ_N_F32:
- case ARM64_INTRIN_VRECPES_F32:
- case ARM64_INTRIN_VRECPXS_F32:
- case ARM64_INTRIN_VRNDNS_F32:
- case ARM64_INTRIN_VRSQRTES_F32:
- return {NameAndType(Type::FloatType(4))};
- case ARM64_INTRIN_VMULS_LANEQ_F32:
- case ARM64_INTRIN_VMULXS_LANEQ_F32:
- case ARM64_INTRIN_VSETQ_LANE_F32:
- return {NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(16)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VABDS_F32:
- case ARM64_INTRIN_VCAGES_F32:
- case ARM64_INTRIN_VCAGTS_F32:
- case ARM64_INTRIN_VCALES_F32:
- case ARM64_INTRIN_VCALTS_F32:
- case ARM64_INTRIN_VCEQS_F32:
- case ARM64_INTRIN_VCGES_F32:
- case ARM64_INTRIN_VCGTS_F32:
- case ARM64_INTRIN_VCLES_F32:
- case ARM64_INTRIN_VCLTS_F32:
- case ARM64_INTRIN_VMULXS_F32:
- case ARM64_INTRIN_VRECPSS_F32:
- case ARM64_INTRIN_VRSQRTSS_F32:
- return {NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(4))};
- case ARM64_INTRIN_VFMAS_LANEQ_F32:
- case ARM64_INTRIN_VFMSS_LANEQ_F32:
- return {NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(4)),
- NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VFMAS_LANE_F32:
- case ARM64_INTRIN_VFMSS_LANE_F32:
- return {NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(4)),
- NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VMULS_LANE_F32:
- case ARM64_INTRIN_VMULXS_LANE_F32:
- case ARM64_INTRIN_VSET_LANE_F32:
- return {NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(8)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VCVTS_N_S32_F32:
- case ARM64_INTRIN_VCVTS_N_U32_F32:
- return {NameAndType(Type::FloatType(4)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VABS_F16:
- case ARM64_INTRIN_VABS_F32:
- case ARM64_INTRIN_VABS_F64:
- case ARM64_INTRIN_VADDV_F32:
- case ARM64_INTRIN_VCEQZ_F16:
- case ARM64_INTRIN_VCEQZ_F32:
- case ARM64_INTRIN_VCEQZ_F64:
- case ARM64_INTRIN_VCEQZD_F64:
- case ARM64_INTRIN_VCGEZ_F16:
- case ARM64_INTRIN_VCGEZ_F32:
- case ARM64_INTRIN_VCGEZ_F64:
- case ARM64_INTRIN_VCGEZD_F64:
- case ARM64_INTRIN_VCGTZ_F16:
- case ARM64_INTRIN_VCGTZ_F32:
- case ARM64_INTRIN_VCGTZ_F64:
- case ARM64_INTRIN_VCGTZD_F64:
- case ARM64_INTRIN_VCLEZ_F16:
- case ARM64_INTRIN_VCLEZ_F32:
- case ARM64_INTRIN_VCLEZ_F64:
- case ARM64_INTRIN_VCLEZD_F64:
- case ARM64_INTRIN_VCLTZ_F16:
- case ARM64_INTRIN_VCLTZ_F32:
- case ARM64_INTRIN_VCLTZ_F64:
- case ARM64_INTRIN_VCLTZD_F64:
- case ARM64_INTRIN_VCVT_F32_BF16:
- case ARM64_INTRIN_VCVT_F32_F16:
- case ARM64_INTRIN_VCVT_F64_F32:
- case ARM64_INTRIN_VCVT_S16_F16:
- case ARM64_INTRIN_VCVT_S32_F32:
- case ARM64_INTRIN_VCVT_S64_F64:
- case ARM64_INTRIN_VCVT_U16_F16:
- case ARM64_INTRIN_VCVT_U32_F32:
- case ARM64_INTRIN_VCVT_U64_F64:
- case ARM64_INTRIN_VCVTA_S16_F16:
- case ARM64_INTRIN_VCVTA_S32_F32:
- case ARM64_INTRIN_VCVTA_S64_F64:
- case ARM64_INTRIN_VCVTA_U16_F16:
- case ARM64_INTRIN_VCVTA_U32_F32:
- case ARM64_INTRIN_VCVTA_U64_F64:
- case ARM64_INTRIN_VCVTAD_S64_F64:
- case ARM64_INTRIN_VCVTAD_U64_F64:
- case ARM64_INTRIN_VCVTD_S64_F64:
- case ARM64_INTRIN_VCVTD_U64_F64:
- case ARM64_INTRIN_VCVTM_S16_F16:
- case ARM64_INTRIN_VCVTM_S32_F32:
- case ARM64_INTRIN_VCVTM_S64_F64:
- case ARM64_INTRIN_VCVTM_U16_F16:
- case ARM64_INTRIN_VCVTM_U32_F32:
- case ARM64_INTRIN_VCVTM_U64_F64:
- case ARM64_INTRIN_VCVTMD_S64_F64:
- case ARM64_INTRIN_VCVTMD_U64_F64:
- case ARM64_INTRIN_VCVTN_S16_F16:
- case ARM64_INTRIN_VCVTN_S32_F32:
- case ARM64_INTRIN_VCVTN_S64_F64:
- case ARM64_INTRIN_VCVTN_U16_F16:
- case ARM64_INTRIN_VCVTN_U32_F32:
- case ARM64_INTRIN_VCVTN_U64_F64:
- case ARM64_INTRIN_VCVTND_S64_F64:
- case ARM64_INTRIN_VCVTND_U64_F64:
- case ARM64_INTRIN_VCVTP_S16_F16:
- case ARM64_INTRIN_VCVTP_S32_F32:
- case ARM64_INTRIN_VCVTP_S64_F64:
- case ARM64_INTRIN_VCVTP_U16_F16:
- case ARM64_INTRIN_VCVTP_U32_F32:
- case ARM64_INTRIN_VCVTP_U64_F64:
- case ARM64_INTRIN_VCVTPD_S64_F64:
- case ARM64_INTRIN_VCVTPD_U64_F64:
- case ARM64_INTRIN_VCVTXD_F32_F64:
- case ARM64_INTRIN_VDUP_N_F64:
- case ARM64_INTRIN_VDUPQ_N_F64:
- case ARM64_INTRIN_VMAXNMV_F16:
- case ARM64_INTRIN_VMAXNMV_F32:
- case ARM64_INTRIN_VMAXV_F16:
- case ARM64_INTRIN_VMAXV_F32:
- case ARM64_INTRIN_VMINNMV_F16:
- case ARM64_INTRIN_VMINNMV_F32:
- case ARM64_INTRIN_VMINV_F16:
- case ARM64_INTRIN_VMINV_F32:
- case ARM64_INTRIN_VMOV_N_F64:
- case ARM64_INTRIN_VMOVQ_N_F64:
- case ARM64_INTRIN_VNEG_F16:
- case ARM64_INTRIN_VNEG_F32:
- case ARM64_INTRIN_VNEG_F64:
- case ARM64_INTRIN_VPADDS_F32:
- case ARM64_INTRIN_VPMAXNMS_F32:
- case ARM64_INTRIN_VPMAXS_F32:
- case ARM64_INTRIN_VPMINNMS_F32:
- case ARM64_INTRIN_VPMINS_F32:
- case ARM64_INTRIN_VRECPE_F16:
- case ARM64_INTRIN_VRECPE_F32:
- case ARM64_INTRIN_VRECPE_F64:
- case ARM64_INTRIN_VRECPED_F64:
- case ARM64_INTRIN_VRECPXD_F64:
- case ARM64_INTRIN_VREV64_F16:
- case ARM64_INTRIN_VREV64_F32:
- case ARM64_INTRIN_VRND32X_F32:
- case ARM64_INTRIN_VRND32X_F64:
- case ARM64_INTRIN_VRND32Z_F32:
- case ARM64_INTRIN_VRND32Z_F64:
- case ARM64_INTRIN_VRND64X_F32:
- case ARM64_INTRIN_VRND64X_F64:
- case ARM64_INTRIN_VRND64Z_F32:
- case ARM64_INTRIN_VRND64Z_F64:
- case ARM64_INTRIN_VRND_F16:
- case ARM64_INTRIN_VRND_F32:
- case ARM64_INTRIN_VRND_F64:
- case ARM64_INTRIN_VRNDA_F16:
- case ARM64_INTRIN_VRNDA_F32:
- case ARM64_INTRIN_VRNDA_F64:
- case ARM64_INTRIN_VRNDI_F16:
- case ARM64_INTRIN_VRNDI_F32:
- case ARM64_INTRIN_VRNDI_F64:
- case ARM64_INTRIN_VRNDM_F16:
- case ARM64_INTRIN_VRNDM_F32:
- case ARM64_INTRIN_VRNDM_F64:
- case ARM64_INTRIN_VRNDN_F16:
- case ARM64_INTRIN_VRNDN_F32:
- case ARM64_INTRIN_VRNDN_F64:
- case ARM64_INTRIN_VRNDP_F16:
- case ARM64_INTRIN_VRNDP_F32:
- case ARM64_INTRIN_VRNDP_F64:
- case ARM64_INTRIN_VRNDX_F16:
- case ARM64_INTRIN_VRNDX_F32:
- case ARM64_INTRIN_VRNDX_F64:
- case ARM64_INTRIN_VRSQRTE_F16:
- case ARM64_INTRIN_VRSQRTE_F32:
- case ARM64_INTRIN_VRSQRTE_F64:
- case ARM64_INTRIN_VRSQRTED_F64:
- case ARM64_INTRIN_VSQRT_F16:
- case ARM64_INTRIN_VSQRT_F32:
- case ARM64_INTRIN_VSQRT_F64:
- return {NameAndType(Type::FloatType(8))};
- case ARM64_INTRIN_VCVT_HIGH_F16_F32:
- case ARM64_INTRIN_VCVT_HIGH_F32_F64:
- case ARM64_INTRIN_VCVTX_HIGH_F32_F64:
- return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(16))};
- case ARM64_INTRIN_VMUL_LANEQ_F16:
- case ARM64_INTRIN_VMUL_LANEQ_F32:
- case ARM64_INTRIN_VMUL_LANEQ_F64:
- case ARM64_INTRIN_VMULD_LANEQ_F64:
- case ARM64_INTRIN_VMULX_LANEQ_F16:
- case ARM64_INTRIN_VMULX_LANEQ_F32:
- case ARM64_INTRIN_VMULX_LANEQ_F64:
- case ARM64_INTRIN_VMULXD_LANEQ_F64:
- case ARM64_INTRIN_VSETQ_LANE_F64:
- return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(16)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VMUL_N_F16:
- case ARM64_INTRIN_VMULX_N_F16:
- return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(2))};
- case ARM64_INTRIN_VMUL_N_F32:
- return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(4))};
- case ARM64_INTRIN_VABD_F16:
- case ARM64_INTRIN_VABD_F32:
- case ARM64_INTRIN_VABD_F64:
- case ARM64_INTRIN_VABDD_F64:
- case ARM64_INTRIN_VADD_F16:
- case ARM64_INTRIN_VADD_F32:
- case ARM64_INTRIN_VADD_F64:
- case ARM64_INTRIN_VCADD_ROT270_F16:
- case ARM64_INTRIN_VCADD_ROT270_F32:
- case ARM64_INTRIN_VCADD_ROT90_F16:
- case ARM64_INTRIN_VCADD_ROT90_F32:
- case ARM64_INTRIN_VCAGE_F16:
- case ARM64_INTRIN_VCAGE_F32:
- case ARM64_INTRIN_VCAGE_F64:
- case ARM64_INTRIN_VCAGED_F64:
- case ARM64_INTRIN_VCAGT_F16:
- case ARM64_INTRIN_VCAGT_F32:
- case ARM64_INTRIN_VCAGT_F64:
- case ARM64_INTRIN_VCAGTD_F64:
- case ARM64_INTRIN_VCALE_F16:
- case ARM64_INTRIN_VCALE_F32:
- case ARM64_INTRIN_VCALE_F64:
- case ARM64_INTRIN_VCALED_F64:
- case ARM64_INTRIN_VCALT_F16:
- case ARM64_INTRIN_VCALT_F32:
- case ARM64_INTRIN_VCALT_F64:
- case ARM64_INTRIN_VCALTD_F64:
- case ARM64_INTRIN_VCEQ_F16:
- case ARM64_INTRIN_VCEQ_F32:
- case ARM64_INTRIN_VCEQ_F64:
- case ARM64_INTRIN_VCEQD_F64:
- case ARM64_INTRIN_VCGE_F16:
- case ARM64_INTRIN_VCGE_F32:
- case ARM64_INTRIN_VCGE_F64:
- case ARM64_INTRIN_VCGED_F64:
- case ARM64_INTRIN_VCGT_F16:
- case ARM64_INTRIN_VCGT_F32:
- case ARM64_INTRIN_VCGT_F64:
- case ARM64_INTRIN_VCGTD_F64:
- case ARM64_INTRIN_VCLE_F16:
- case ARM64_INTRIN_VCLE_F32:
- case ARM64_INTRIN_VCLE_F64:
- case ARM64_INTRIN_VCLED_F64:
- case ARM64_INTRIN_VCLT_F16:
- case ARM64_INTRIN_VCLT_F32:
- case ARM64_INTRIN_VCLT_F64:
- case ARM64_INTRIN_VCLTD_F64:
- case ARM64_INTRIN_VDIV_F16:
- case ARM64_INTRIN_VDIV_F32:
- case ARM64_INTRIN_VDIV_F64:
- case ARM64_INTRIN_VMAX_F16:
- case ARM64_INTRIN_VMAX_F32:
- case ARM64_INTRIN_VMAX_F64:
- case ARM64_INTRIN_VMAXNM_F16:
- case ARM64_INTRIN_VMAXNM_F32:
- case ARM64_INTRIN_VMAXNM_F64:
- case ARM64_INTRIN_VMIN_F16:
- case ARM64_INTRIN_VMIN_F32:
- case ARM64_INTRIN_VMIN_F64:
- case ARM64_INTRIN_VMINNM_F16:
- case ARM64_INTRIN_VMINNM_F32:
- case ARM64_INTRIN_VMINNM_F64:
- case ARM64_INTRIN_VMUL_F16:
- case ARM64_INTRIN_VMUL_F32:
- case ARM64_INTRIN_VMUL_F64:
- case ARM64_INTRIN_VMUL_N_F64:
- case ARM64_INTRIN_VMULX_F16:
- case ARM64_INTRIN_VMULX_F32:
- case ARM64_INTRIN_VMULX_F64:
- case ARM64_INTRIN_VMULXD_F64:
- case ARM64_INTRIN_VPADD_F16:
- case ARM64_INTRIN_VPADD_F32:
- case ARM64_INTRIN_VPMAX_F16:
- case ARM64_INTRIN_VPMAX_F32:
- case ARM64_INTRIN_VPMAXNM_F16:
- case ARM64_INTRIN_VPMAXNM_F32:
- case ARM64_INTRIN_VPMIN_F16:
- case ARM64_INTRIN_VPMIN_F32:
- case ARM64_INTRIN_VPMINNM_F16:
- case ARM64_INTRIN_VPMINNM_F32:
- case ARM64_INTRIN_VRECPS_F16:
- case ARM64_INTRIN_VRECPS_F32:
- case ARM64_INTRIN_VRECPS_F64:
- case ARM64_INTRIN_VRECPSD_F64:
- case ARM64_INTRIN_VRSQRTS_F16:
- case ARM64_INTRIN_VRSQRTS_F32:
- case ARM64_INTRIN_VRSQRTS_F64:
- case ARM64_INTRIN_VRSQRTSD_F64:
- case ARM64_INTRIN_VSUB_F16:
- case ARM64_INTRIN_VSUB_F32:
- case ARM64_INTRIN_VSUB_F64:
- case ARM64_INTRIN_VTRN1_F16:
- case ARM64_INTRIN_VTRN1_F32:
- case ARM64_INTRIN_VTRN2_F16:
- case ARM64_INTRIN_VTRN2_F32:
- case ARM64_INTRIN_VUZP1_F16:
- case ARM64_INTRIN_VUZP1_F32:
- case ARM64_INTRIN_VUZP2_F16:
- case ARM64_INTRIN_VUZP2_F32:
- case ARM64_INTRIN_VZIP1_F16:
- case ARM64_INTRIN_VZIP1_F32:
- case ARM64_INTRIN_VZIP2_F16:
- case ARM64_INTRIN_VZIP2_F32:
- return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8))};
- case ARM64_INTRIN_VBFDOT_LANEQ_F32:
- case ARM64_INTRIN_VCMLA_LANEQ_F16:
- case ARM64_INTRIN_VCMLA_ROT180_LANEQ_F16:
- case ARM64_INTRIN_VCMLA_ROT270_LANEQ_F16:
- case ARM64_INTRIN_VCMLA_ROT90_LANEQ_F16:
- case ARM64_INTRIN_VFMA_LANEQ_F16:
- case ARM64_INTRIN_VFMA_LANEQ_F32:
- case ARM64_INTRIN_VFMA_LANEQ_F64:
- case ARM64_INTRIN_VFMAD_LANEQ_F64:
- case ARM64_INTRIN_VFMLAL_LANEQ_HIGH_F16:
- case ARM64_INTRIN_VFMLAL_LANEQ_LOW_F16:
- case ARM64_INTRIN_VFMLSL_LANEQ_HIGH_F16:
- case ARM64_INTRIN_VFMLSL_LANEQ_LOW_F16:
- case ARM64_INTRIN_VFMS_LANEQ_F16:
- case ARM64_INTRIN_VFMS_LANEQ_F32:
- case ARM64_INTRIN_VFMS_LANEQ_F64:
- case ARM64_INTRIN_VFMSD_LANEQ_F64:
- return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)),
- NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VFMA_N_F16:
- case ARM64_INTRIN_VFMS_N_F16:
- return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)),
- NameAndType(Type::FloatType(2))};
- case ARM64_INTRIN_VFMA_N_F32:
- case ARM64_INTRIN_VFMS_N_F32:
- return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)),
- NameAndType(Type::FloatType(4))};
- case ARM64_INTRIN_VBFDOT_F32:
- case ARM64_INTRIN_VCMLA_F16:
- case ARM64_INTRIN_VCMLA_F32:
- case ARM64_INTRIN_VCMLA_ROT180_F16:
- case ARM64_INTRIN_VCMLA_ROT180_F32:
- case ARM64_INTRIN_VCMLA_ROT270_F16:
- case ARM64_INTRIN_VCMLA_ROT270_F32:
- case ARM64_INTRIN_VCMLA_ROT90_F16:
- case ARM64_INTRIN_VCMLA_ROT90_F32:
- case ARM64_INTRIN_VFMA_F16:
- case ARM64_INTRIN_VFMA_F32:
- case ARM64_INTRIN_VFMA_F64:
- case ARM64_INTRIN_VFMA_N_F64:
- case ARM64_INTRIN_VFMLAL_HIGH_F16:
- case ARM64_INTRIN_VFMLAL_LOW_F16:
- case ARM64_INTRIN_VFMLSL_HIGH_F16:
- case ARM64_INTRIN_VFMLSL_LOW_F16:
- case ARM64_INTRIN_VFMS_F16:
- case ARM64_INTRIN_VFMS_F32:
- case ARM64_INTRIN_VFMS_F64:
- case ARM64_INTRIN_VFMS_N_F64:
- return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)),
- NameAndType(Type::FloatType(8))};
- case ARM64_INTRIN_VBFDOT_LANE_F32:
- case ARM64_INTRIN_VCMLA_LANE_F16:
- case ARM64_INTRIN_VCMLA_LANE_F32:
- case ARM64_INTRIN_VCMLA_ROT180_LANE_F16:
- case ARM64_INTRIN_VCMLA_ROT180_LANE_F32:
- case ARM64_INTRIN_VCMLA_ROT270_LANE_F16:
- case ARM64_INTRIN_VCMLA_ROT270_LANE_F32:
- case ARM64_INTRIN_VCMLA_ROT90_LANE_F16:
- case ARM64_INTRIN_VCMLA_ROT90_LANE_F32:
- case ARM64_INTRIN_VFMA_LANE_F16:
- case ARM64_INTRIN_VFMA_LANE_F32:
- case ARM64_INTRIN_VFMA_LANE_F64:
- case ARM64_INTRIN_VFMAD_LANE_F64:
- case ARM64_INTRIN_VFMLAL_LANE_HIGH_F16:
- case ARM64_INTRIN_VFMLAL_LANE_LOW_F16:
- case ARM64_INTRIN_VFMLSL_LANE_HIGH_F16:
- case ARM64_INTRIN_VFMLSL_LANE_LOW_F16:
- case ARM64_INTRIN_VFMS_LANE_F16:
- case ARM64_INTRIN_VFMS_LANE_F32:
- case ARM64_INTRIN_VFMS_LANE_F64:
- case ARM64_INTRIN_VFMSD_LANE_F64:
- return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)),
- NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VEXT_F16:
- case ARM64_INTRIN_VEXT_F32:
- case ARM64_INTRIN_VEXT_F64:
- case ARM64_INTRIN_VMUL_LANE_F16:
- case ARM64_INTRIN_VMUL_LANE_F32:
- case ARM64_INTRIN_VMUL_LANE_F64:
- case ARM64_INTRIN_VMULD_LANE_F64:
- case ARM64_INTRIN_VMULX_LANE_F16:
- case ARM64_INTRIN_VMULX_LANE_F32:
- case ARM64_INTRIN_VMULX_LANE_F64:
- case ARM64_INTRIN_VMULXD_LANE_F64:
- case ARM64_INTRIN_VSET_LANE_F64:
- return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VCVT_N_S16_F16:
- case ARM64_INTRIN_VCVT_N_S32_F32:
- case ARM64_INTRIN_VCVT_N_S64_F64:
- case ARM64_INTRIN_VCVT_N_U16_F16:
- case ARM64_INTRIN_VCVT_N_U32_F32:
- case ARM64_INTRIN_VCVT_N_U64_F64:
- case ARM64_INTRIN_VCVTD_N_S64_F64:
- case ARM64_INTRIN_VCVTD_N_U64_F64:
- case ARM64_INTRIN_VDUP_LANE_BF16:
- case ARM64_INTRIN_VDUP_LANE_F16:
- case ARM64_INTRIN_VDUP_LANE_F32:
- case ARM64_INTRIN_VDUP_LANE_F64:
- case ARM64_INTRIN_VDUPD_LANE_F64:
- case ARM64_INTRIN_VDUPH_LANE_BF16:
- case ARM64_INTRIN_VDUPH_LANE_F16:
- case ARM64_INTRIN_VDUPQ_LANE_BF16:
- case ARM64_INTRIN_VDUPQ_LANE_F16:
- case ARM64_INTRIN_VDUPQ_LANE_F32:
- case ARM64_INTRIN_VDUPQ_LANE_F64:
- case ARM64_INTRIN_VDUPS_LANE_F32:
- case ARM64_INTRIN_VGET_LANE_BF16:
- case ARM64_INTRIN_VGET_LANE_F16:
- case ARM64_INTRIN_VGET_LANE_F32:
- case ARM64_INTRIN_VGET_LANE_F64:
- return {NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VDUP_N_P8:
- case ARM64_INTRIN_VDUP_N_S8:
- case ARM64_INTRIN_VDUP_N_U8:
- case ARM64_INTRIN_VDUPQ_N_P8:
- case ARM64_INTRIN_VDUPQ_N_S8:
- case ARM64_INTRIN_VDUPQ_N_U8:
- case ARM64_INTRIN_VMOV_N_P8:
- case ARM64_INTRIN_VMOV_N_S8:
- case ARM64_INTRIN_VMOV_N_U8:
- case ARM64_INTRIN_VMOVQ_N_P8:
- case ARM64_INTRIN_VMOVQ_N_S8:
- case ARM64_INTRIN_VMOVQ_N_U8:
- case ARM64_INTRIN_VQABSB_S8:
- case ARM64_INTRIN_VQNEGB_S8:
- return {NameAndType(Type::IntegerType(1, false))};
- case ARM64_INTRIN_VQADDB_S8:
- case ARM64_INTRIN_VQADDB_U8:
- case ARM64_INTRIN_VQRSHLB_S8:
- case ARM64_INTRIN_VQRSHLB_U8:
- case ARM64_INTRIN_VQSHLB_S8:
- case ARM64_INTRIN_VQSHLB_U8:
- case ARM64_INTRIN_VQSUBB_S8:
- case ARM64_INTRIN_VQSUBB_U8:
- case ARM64_INTRIN_VSQADDB_U8:
- case ARM64_INTRIN_VUQADDB_S8:
- return {NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(1, false))};
- case ARM64_INTRIN_VSETQ_LANE_P8:
- case ARM64_INTRIN_VSETQ_LANE_S8:
- case ARM64_INTRIN_VSETQ_LANE_U8:
- return {NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(16, false)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VQSHLB_N_S8:
- case ARM64_INTRIN_VQSHLB_N_U8:
- case ARM64_INTRIN_VQSHLUB_N_S8:
- return {NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VSET_LANE_P8:
- case ARM64_INTRIN_VSET_LANE_S8:
- case ARM64_INTRIN_VSET_LANE_U8:
- return {NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(8, false)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VABSQ_S16:
- case ARM64_INTRIN_VABSQ_S32:
- case ARM64_INTRIN_VABSQ_S64:
- case ARM64_INTRIN_VABSQ_S8:
- case ARM64_INTRIN_VADDLVQ_S16:
- case ARM64_INTRIN_VADDLVQ_S32:
- case ARM64_INTRIN_VADDLVQ_S8:
- case ARM64_INTRIN_VADDLVQ_U16:
- case ARM64_INTRIN_VADDLVQ_U32:
- case ARM64_INTRIN_VADDLVQ_U8:
- case ARM64_INTRIN_VADDVQ_S16:
- case ARM64_INTRIN_VADDVQ_S32:
- case ARM64_INTRIN_VADDVQ_S64:
- case ARM64_INTRIN_VADDVQ_S8:
- case ARM64_INTRIN_VADDVQ_U16:
- case ARM64_INTRIN_VADDVQ_U32:
- case ARM64_INTRIN_VADDVQ_U64:
- case ARM64_INTRIN_VADDVQ_U8:
- case ARM64_INTRIN_VAESIMCQ_U8:
- case ARM64_INTRIN_VAESMCQ_U8:
- case ARM64_INTRIN_VCEQZQ_P64:
- case ARM64_INTRIN_VCEQZQ_P8:
- case ARM64_INTRIN_VCEQZQ_S16:
- case ARM64_INTRIN_VCEQZQ_S32:
- case ARM64_INTRIN_VCEQZQ_S64:
- case ARM64_INTRIN_VCEQZQ_S8:
- case ARM64_INTRIN_VCEQZQ_U16:
- case ARM64_INTRIN_VCEQZQ_U32:
- case ARM64_INTRIN_VCEQZQ_U64:
- case ARM64_INTRIN_VCEQZQ_U8:
- case ARM64_INTRIN_VCGEZQ_S16:
- case ARM64_INTRIN_VCGEZQ_S32:
- case ARM64_INTRIN_VCGEZQ_S64:
- case ARM64_INTRIN_VCGEZQ_S8:
- case ARM64_INTRIN_VCGTZQ_S16:
- case ARM64_INTRIN_VCGTZQ_S32:
- case ARM64_INTRIN_VCGTZQ_S64:
- case ARM64_INTRIN_VCGTZQ_S8:
- case ARM64_INTRIN_VCLEZQ_S16:
- case ARM64_INTRIN_VCLEZQ_S32:
- case ARM64_INTRIN_VCLEZQ_S64:
- case ARM64_INTRIN_VCLEZQ_S8:
- case ARM64_INTRIN_VCLSQ_S16:
- case ARM64_INTRIN_VCLSQ_S32:
- case ARM64_INTRIN_VCLSQ_S8:
- case ARM64_INTRIN_VCLSQ_U16:
- case ARM64_INTRIN_VCLSQ_U32:
- case ARM64_INTRIN_VCLSQ_U8:
- case ARM64_INTRIN_VCLTZQ_S16:
- case ARM64_INTRIN_VCLTZQ_S32:
- case ARM64_INTRIN_VCLTZQ_S64:
- case ARM64_INTRIN_VCLTZQ_S8:
- case ARM64_INTRIN_VCLZQ_S16:
- case ARM64_INTRIN_VCLZQ_S32:
- case ARM64_INTRIN_VCLZQ_S8:
- case ARM64_INTRIN_VCLZQ_U16:
- case ARM64_INTRIN_VCLZQ_U32:
- case ARM64_INTRIN_VCLZQ_U8:
- case ARM64_INTRIN_VCNTQ_P8:
- case ARM64_INTRIN_VCNTQ_S8:
- case ARM64_INTRIN_VCNTQ_U8:
- case ARM64_INTRIN_VCVTQ_F16_S16:
- case ARM64_INTRIN_VCVTQ_F16_U16:
- case ARM64_INTRIN_VCVTQ_F32_S32:
- case ARM64_INTRIN_VCVTQ_F32_U32:
- case ARM64_INTRIN_VCVTQ_F64_S64:
- case ARM64_INTRIN_VCVTQ_F64_U64:
- case ARM64_INTRIN_VGET_HIGH_P16:
- case ARM64_INTRIN_VGET_HIGH_P64:
- case ARM64_INTRIN_VGET_HIGH_P8:
- case ARM64_INTRIN_VGET_HIGH_S16:
- case ARM64_INTRIN_VGET_HIGH_S32:
- case ARM64_INTRIN_VGET_HIGH_S64:
- case ARM64_INTRIN_VGET_HIGH_S8:
- case ARM64_INTRIN_VGET_HIGH_U16:
- case ARM64_INTRIN_VGET_HIGH_U32:
- case ARM64_INTRIN_VGET_HIGH_U64:
- case ARM64_INTRIN_VGET_HIGH_U8:
- case ARM64_INTRIN_VGET_LOW_P16:
- case ARM64_INTRIN_VGET_LOW_P64:
- case ARM64_INTRIN_VGET_LOW_P8:
- case ARM64_INTRIN_VGET_LOW_S16:
- case ARM64_INTRIN_VGET_LOW_S32:
- case ARM64_INTRIN_VGET_LOW_S64:
- case ARM64_INTRIN_VGET_LOW_S8:
- case ARM64_INTRIN_VGET_LOW_U16:
- case ARM64_INTRIN_VGET_LOW_U32:
- case ARM64_INTRIN_VGET_LOW_U64:
- case ARM64_INTRIN_VGET_LOW_U8:
- case ARM64_INTRIN_VLDRQ_P128:
- case ARM64_INTRIN_VMAXVQ_S16:
- case ARM64_INTRIN_VMAXVQ_S32:
- case ARM64_INTRIN_VMAXVQ_S8:
- case ARM64_INTRIN_VMAXVQ_U16:
- case ARM64_INTRIN_VMAXVQ_U32:
- case ARM64_INTRIN_VMAXVQ_U8:
- case ARM64_INTRIN_VMINVQ_S16:
- case ARM64_INTRIN_VMINVQ_S32:
- case ARM64_INTRIN_VMINVQ_S8:
- case ARM64_INTRIN_VMINVQ_U16:
- case ARM64_INTRIN_VMINVQ_U32:
- case ARM64_INTRIN_VMINVQ_U8:
- case ARM64_INTRIN_VMOVL_HIGH_S16:
- case ARM64_INTRIN_VMOVL_HIGH_S32:
- case ARM64_INTRIN_VMOVL_HIGH_S8:
- case ARM64_INTRIN_VMOVL_HIGH_U16:
- case ARM64_INTRIN_VMOVL_HIGH_U32:
- case ARM64_INTRIN_VMOVL_HIGH_U8:
- case ARM64_INTRIN_VMOVN_S16:
- case ARM64_INTRIN_VMOVN_S32:
- case ARM64_INTRIN_VMOVN_S64:
- case ARM64_INTRIN_VMOVN_U16:
- case ARM64_INTRIN_VMOVN_U32:
- case ARM64_INTRIN_VMOVN_U64:
- case ARM64_INTRIN_VMVNQ_P8:
- case ARM64_INTRIN_VMVNQ_S16:
- case ARM64_INTRIN_VMVNQ_S32:
- case ARM64_INTRIN_VMVNQ_S8:
- case ARM64_INTRIN_VMVNQ_U16:
- case ARM64_INTRIN_VMVNQ_U32:
- case ARM64_INTRIN_VMVNQ_U8:
- case ARM64_INTRIN_VNEGQ_S16:
- case ARM64_INTRIN_VNEGQ_S32:
- case ARM64_INTRIN_VNEGQ_S64:
- case ARM64_INTRIN_VNEGQ_S8:
- case ARM64_INTRIN_VPADDD_S64:
- case ARM64_INTRIN_VPADDD_U64:
- case ARM64_INTRIN_VPADDLQ_S16:
- case ARM64_INTRIN_VPADDLQ_S32:
- case ARM64_INTRIN_VPADDLQ_S8:
- case ARM64_INTRIN_VPADDLQ_U16:
- case ARM64_INTRIN_VPADDLQ_U32:
- case ARM64_INTRIN_VPADDLQ_U8:
- case ARM64_INTRIN_VQABSQ_S16:
- case ARM64_INTRIN_VQABSQ_S32:
- case ARM64_INTRIN_VQABSQ_S64:
- case ARM64_INTRIN_VQABSQ_S8:
- case ARM64_INTRIN_VQMOVN_S16:
- case ARM64_INTRIN_VQMOVN_S32:
- case ARM64_INTRIN_VQMOVN_S64:
- case ARM64_INTRIN_VQMOVN_U16:
- case ARM64_INTRIN_VQMOVN_U32:
- case ARM64_INTRIN_VQMOVN_U64:
- case ARM64_INTRIN_VQMOVUN_S16:
- case ARM64_INTRIN_VQMOVUN_S32:
- case ARM64_INTRIN_VQMOVUN_S64:
- case ARM64_INTRIN_VQNEGQ_S16:
- case ARM64_INTRIN_VQNEGQ_S32:
- case ARM64_INTRIN_VQNEGQ_S64:
- case ARM64_INTRIN_VQNEGQ_S8:
- case ARM64_INTRIN_VRBITQ_P8:
- case ARM64_INTRIN_VRBITQ_S8:
- case ARM64_INTRIN_VRBITQ_U8:
- case ARM64_INTRIN_VRECPEQ_U32:
- case ARM64_INTRIN_VREV16Q_P8:
- case ARM64_INTRIN_VREV16Q_S8:
- case ARM64_INTRIN_VREV16Q_U8:
- case ARM64_INTRIN_VREV32Q_P16:
- case ARM64_INTRIN_VREV32Q_P8:
- case ARM64_INTRIN_VREV32Q_S16:
- case ARM64_INTRIN_VREV32Q_S8:
- case ARM64_INTRIN_VREV32Q_U16:
- case ARM64_INTRIN_VREV32Q_U8:
- case ARM64_INTRIN_VREV64Q_P16:
- case ARM64_INTRIN_VREV64Q_P8:
- case ARM64_INTRIN_VREV64Q_S16:
- case ARM64_INTRIN_VREV64Q_S32:
- case ARM64_INTRIN_VREV64Q_S8:
- case ARM64_INTRIN_VREV64Q_U16:
- case ARM64_INTRIN_VREV64Q_U32:
- case ARM64_INTRIN_VREV64Q_U8:
- case ARM64_INTRIN_VRSQRTEQ_U32:
- return {NameAndType(Type::IntegerType(16, false))};
- case ARM64_INTRIN_VBSLQ_F16:
- case ARM64_INTRIN_VBSLQ_F32:
- case ARM64_INTRIN_VBSLQ_F64:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::FloatType(16)),
- NameAndType(Type::FloatType(16))};
- case ARM64_INTRIN_VABDL_HIGH_S16:
- case ARM64_INTRIN_VABDL_HIGH_S32:
- case ARM64_INTRIN_VABDL_HIGH_S8:
- case ARM64_INTRIN_VABDL_HIGH_U16:
- case ARM64_INTRIN_VABDL_HIGH_U32:
- case ARM64_INTRIN_VABDL_HIGH_U8:
- case ARM64_INTRIN_VABDQ_S16:
- case ARM64_INTRIN_VABDQ_S32:
- case ARM64_INTRIN_VABDQ_S8:
- case ARM64_INTRIN_VABDQ_U16:
- case ARM64_INTRIN_VABDQ_U32:
- case ARM64_INTRIN_VABDQ_U8:
- case ARM64_INTRIN_VADDHN_S16:
- case ARM64_INTRIN_VADDHN_S32:
- case ARM64_INTRIN_VADDHN_S64:
- case ARM64_INTRIN_VADDHN_U16:
- case ARM64_INTRIN_VADDHN_U32:
- case ARM64_INTRIN_VADDHN_U64:
- case ARM64_INTRIN_VADDL_HIGH_S16:
- case ARM64_INTRIN_VADDL_HIGH_S32:
- case ARM64_INTRIN_VADDL_HIGH_S8:
- case ARM64_INTRIN_VADDL_HIGH_U16:
- case ARM64_INTRIN_VADDL_HIGH_U32:
- case ARM64_INTRIN_VADDL_HIGH_U8:
- case ARM64_INTRIN_VADDQ_P128:
- case ARM64_INTRIN_VADDQ_P16:
- case ARM64_INTRIN_VADDQ_P64:
- case ARM64_INTRIN_VADDQ_P8:
- case ARM64_INTRIN_VADDQ_S16:
- case ARM64_INTRIN_VADDQ_S32:
- case ARM64_INTRIN_VADDQ_S64:
- case ARM64_INTRIN_VADDQ_S8:
- case ARM64_INTRIN_VADDQ_U16:
- case ARM64_INTRIN_VADDQ_U32:
- case ARM64_INTRIN_VADDQ_U64:
- case ARM64_INTRIN_VADDQ_U8:
- case ARM64_INTRIN_VADDW_HIGH_S16:
- case ARM64_INTRIN_VADDW_HIGH_S32:
- case ARM64_INTRIN_VADDW_HIGH_S8:
- case ARM64_INTRIN_VADDW_HIGH_U16:
- case ARM64_INTRIN_VADDW_HIGH_U32:
- case ARM64_INTRIN_VADDW_HIGH_U8:
- case ARM64_INTRIN_VAESDQ_U8:
- case ARM64_INTRIN_VAESEQ_U8:
- case ARM64_INTRIN_VANDQ_S16:
- case ARM64_INTRIN_VANDQ_S32:
- case ARM64_INTRIN_VANDQ_S64:
- case ARM64_INTRIN_VANDQ_S8:
- case ARM64_INTRIN_VANDQ_U16:
- case ARM64_INTRIN_VANDQ_U32:
- case ARM64_INTRIN_VANDQ_U64:
- case ARM64_INTRIN_VANDQ_U8:
- case ARM64_INTRIN_VBICQ_S16:
- case ARM64_INTRIN_VBICQ_S32:
- case ARM64_INTRIN_VBICQ_S64:
- case ARM64_INTRIN_VBICQ_S8:
- case ARM64_INTRIN_VBICQ_U16:
- case ARM64_INTRIN_VBICQ_U32:
- case ARM64_INTRIN_VBICQ_U64:
- case ARM64_INTRIN_VBICQ_U8:
- case ARM64_INTRIN_VCEQQ_P64:
- case ARM64_INTRIN_VCEQQ_P8:
- case ARM64_INTRIN_VCEQQ_S16:
- case ARM64_INTRIN_VCEQQ_S32:
- case ARM64_INTRIN_VCEQQ_S64:
- case ARM64_INTRIN_VCEQQ_S8:
- case ARM64_INTRIN_VCEQQ_U16:
- case ARM64_INTRIN_VCEQQ_U32:
- case ARM64_INTRIN_VCEQQ_U64:
- case ARM64_INTRIN_VCEQQ_U8:
- case ARM64_INTRIN_VCGEQ_S16:
- case ARM64_INTRIN_VCGEQ_S32:
- case ARM64_INTRIN_VCGEQ_S64:
- case ARM64_INTRIN_VCGEQ_S8:
- case ARM64_INTRIN_VCGEQ_U16:
- case ARM64_INTRIN_VCGEQ_U32:
- case ARM64_INTRIN_VCGEQ_U64:
- case ARM64_INTRIN_VCGEQ_U8:
- case ARM64_INTRIN_VCGTQ_S16:
- case ARM64_INTRIN_VCGTQ_S32:
- case ARM64_INTRIN_VCGTQ_S64:
- case ARM64_INTRIN_VCGTQ_S8:
- case ARM64_INTRIN_VCGTQ_U16:
- case ARM64_INTRIN_VCGTQ_U32:
- case ARM64_INTRIN_VCGTQ_U64:
- case ARM64_INTRIN_VCGTQ_U8:
- case ARM64_INTRIN_VCLEQ_S16:
- case ARM64_INTRIN_VCLEQ_S32:
- case ARM64_INTRIN_VCLEQ_S64:
- case ARM64_INTRIN_VCLEQ_S8:
- case ARM64_INTRIN_VCLEQ_U16:
- case ARM64_INTRIN_VCLEQ_U32:
- case ARM64_INTRIN_VCLEQ_U64:
- case ARM64_INTRIN_VCLEQ_U8:
- case ARM64_INTRIN_VCLTQ_S16:
- case ARM64_INTRIN_VCLTQ_S32:
- case ARM64_INTRIN_VCLTQ_S64:
- case ARM64_INTRIN_VCLTQ_S8:
- case ARM64_INTRIN_VCLTQ_U16:
- case ARM64_INTRIN_VCLTQ_U32:
- case ARM64_INTRIN_VCLTQ_U64:
- case ARM64_INTRIN_VCLTQ_U8:
- case ARM64_INTRIN_VEORQ_S16:
- case ARM64_INTRIN_VEORQ_S32:
- case ARM64_INTRIN_VEORQ_S64:
- case ARM64_INTRIN_VEORQ_S8:
- case ARM64_INTRIN_VEORQ_U16:
- case ARM64_INTRIN_VEORQ_U32:
- case ARM64_INTRIN_VEORQ_U64:
- case ARM64_INTRIN_VEORQ_U8:
- case ARM64_INTRIN_VHADDQ_S16:
- case ARM64_INTRIN_VHADDQ_S32:
- case ARM64_INTRIN_VHADDQ_S8:
- case ARM64_INTRIN_VHADDQ_U16:
- case ARM64_INTRIN_VHADDQ_U32:
- case ARM64_INTRIN_VHADDQ_U8:
- case ARM64_INTRIN_VHSUBQ_S16:
- case ARM64_INTRIN_VHSUBQ_S32:
- case ARM64_INTRIN_VHSUBQ_S8:
- case ARM64_INTRIN_VHSUBQ_U16:
- case ARM64_INTRIN_VHSUBQ_U32:
- case ARM64_INTRIN_VHSUBQ_U8:
- case ARM64_INTRIN_VMAXQ_S16:
- case ARM64_INTRIN_VMAXQ_S32:
- case ARM64_INTRIN_VMAXQ_S8:
- case ARM64_INTRIN_VMAXQ_U16:
- case ARM64_INTRIN_VMAXQ_U32:
- case ARM64_INTRIN_VMAXQ_U8:
- case ARM64_INTRIN_VMINQ_S16:
- case ARM64_INTRIN_VMINQ_S32:
- case ARM64_INTRIN_VMINQ_S8:
- case ARM64_INTRIN_VMINQ_U16:
- case ARM64_INTRIN_VMINQ_U32:
- case ARM64_INTRIN_VMINQ_U8:
- case ARM64_INTRIN_VMULL_HIGH_P64:
- case ARM64_INTRIN_VMULL_HIGH_P8:
- case ARM64_INTRIN_VMULL_HIGH_S16:
- case ARM64_INTRIN_VMULL_HIGH_S32:
- case ARM64_INTRIN_VMULL_HIGH_S8:
- case ARM64_INTRIN_VMULL_HIGH_U16:
- case ARM64_INTRIN_VMULL_HIGH_U32:
- case ARM64_INTRIN_VMULL_HIGH_U8:
- case ARM64_INTRIN_VMULQ_P8:
- case ARM64_INTRIN_VMULQ_S16:
- case ARM64_INTRIN_VMULQ_S32:
- case ARM64_INTRIN_VMULQ_S8:
- case ARM64_INTRIN_VMULQ_U16:
- case ARM64_INTRIN_VMULQ_U32:
- case ARM64_INTRIN_VMULQ_U8:
- case ARM64_INTRIN_VORNQ_S16:
- case ARM64_INTRIN_VORNQ_S32:
- case ARM64_INTRIN_VORNQ_S64:
- case ARM64_INTRIN_VORNQ_S8:
- case ARM64_INTRIN_VORNQ_U16:
- case ARM64_INTRIN_VORNQ_U32:
- case ARM64_INTRIN_VORNQ_U64:
- case ARM64_INTRIN_VORNQ_U8:
- case ARM64_INTRIN_VORRQ_S16:
- case ARM64_INTRIN_VORRQ_S32:
- case ARM64_INTRIN_VORRQ_S64:
- case ARM64_INTRIN_VORRQ_S8:
- case ARM64_INTRIN_VORRQ_U16:
- case ARM64_INTRIN_VORRQ_U32:
- case ARM64_INTRIN_VORRQ_U64:
- case ARM64_INTRIN_VORRQ_U8:
- case ARM64_INTRIN_VPADALQ_S16:
- case ARM64_INTRIN_VPADALQ_S32:
- case ARM64_INTRIN_VPADALQ_S8:
- case ARM64_INTRIN_VPADALQ_U16:
- case ARM64_INTRIN_VPADALQ_U32:
- case ARM64_INTRIN_VPADALQ_U8:
- case ARM64_INTRIN_VPADDQ_S16:
- case ARM64_INTRIN_VPADDQ_S32:
- case ARM64_INTRIN_VPADDQ_S64:
- case ARM64_INTRIN_VPADDQ_S8:
- case ARM64_INTRIN_VPADDQ_U16:
- case ARM64_INTRIN_VPADDQ_U32:
- case ARM64_INTRIN_VPADDQ_U64:
- case ARM64_INTRIN_VPADDQ_U8:
- case ARM64_INTRIN_VPMAXQ_S16:
- case ARM64_INTRIN_VPMAXQ_S32:
- case ARM64_INTRIN_VPMAXQ_S8:
- case ARM64_INTRIN_VPMAXQ_U16:
- case ARM64_INTRIN_VPMAXQ_U32:
- case ARM64_INTRIN_VPMAXQ_U8:
- case ARM64_INTRIN_VPMINQ_S16:
- case ARM64_INTRIN_VPMINQ_S32:
- case ARM64_INTRIN_VPMINQ_S8:
- case ARM64_INTRIN_VPMINQ_U16:
- case ARM64_INTRIN_VPMINQ_U32:
- case ARM64_INTRIN_VPMINQ_U8:
- case ARM64_INTRIN_VQADDQ_S16:
- case ARM64_INTRIN_VQADDQ_S32:
- case ARM64_INTRIN_VQADDQ_S64:
- case ARM64_INTRIN_VQADDQ_S8:
- case ARM64_INTRIN_VQADDQ_U16:
- case ARM64_INTRIN_VQADDQ_U32:
- case ARM64_INTRIN_VQADDQ_U64:
- case ARM64_INTRIN_VQADDQ_U8:
- case ARM64_INTRIN_VQDMULHQ_S16:
- case ARM64_INTRIN_VQDMULHQ_S32:
- case ARM64_INTRIN_VQDMULL_HIGH_S16:
- case ARM64_INTRIN_VQDMULL_HIGH_S32:
- case ARM64_INTRIN_VQRDMULHQ_S16:
- case ARM64_INTRIN_VQRDMULHQ_S32:
- case ARM64_INTRIN_VQRSHLQ_S16:
- case ARM64_INTRIN_VQRSHLQ_S32:
- case ARM64_INTRIN_VQRSHLQ_S64:
- case ARM64_INTRIN_VQRSHLQ_S8:
- case ARM64_INTRIN_VQRSHLQ_U16:
- case ARM64_INTRIN_VQRSHLQ_U32:
- case ARM64_INTRIN_VQRSHLQ_U64:
- case ARM64_INTRIN_VQRSHLQ_U8:
- case ARM64_INTRIN_VQSHLQ_S16:
- case ARM64_INTRIN_VQSHLQ_S32:
- case ARM64_INTRIN_VQSHLQ_S64:
- case ARM64_INTRIN_VQSHLQ_S8:
- case ARM64_INTRIN_VQSHLQ_U16:
- case ARM64_INTRIN_VQSHLQ_U32:
- case ARM64_INTRIN_VQSHLQ_U64:
- case ARM64_INTRIN_VQSHLQ_U8:
- case ARM64_INTRIN_VQSUBQ_S16:
- case ARM64_INTRIN_VQSUBQ_S32:
- case ARM64_INTRIN_VQSUBQ_S64:
- case ARM64_INTRIN_VQSUBQ_S8:
- case ARM64_INTRIN_VQSUBQ_U16:
- case ARM64_INTRIN_VQSUBQ_U32:
- case ARM64_INTRIN_VQSUBQ_U64:
- case ARM64_INTRIN_VQSUBQ_U8:
- case ARM64_INTRIN_VRADDHN_S16:
- case ARM64_INTRIN_VRADDHN_S32:
- case ARM64_INTRIN_VRADDHN_S64:
- case ARM64_INTRIN_VRADDHN_U16:
- case ARM64_INTRIN_VRADDHN_U32:
- case ARM64_INTRIN_VRADDHN_U64:
- case ARM64_INTRIN_VRAX1Q_U64:
- case ARM64_INTRIN_VRHADDQ_S16:
- case ARM64_INTRIN_VRHADDQ_S32:
- case ARM64_INTRIN_VRHADDQ_S8:
- case ARM64_INTRIN_VRHADDQ_U16:
- case ARM64_INTRIN_VRHADDQ_U32:
- case ARM64_INTRIN_VRHADDQ_U8:
- case ARM64_INTRIN_VRSHLQ_S16:
- case ARM64_INTRIN_VRSHLQ_S32:
- case ARM64_INTRIN_VRSHLQ_S64:
- case ARM64_INTRIN_VRSHLQ_S8:
- case ARM64_INTRIN_VRSHLQ_U16:
- case ARM64_INTRIN_VRSHLQ_U32:
- case ARM64_INTRIN_VRSHLQ_U64:
- case ARM64_INTRIN_VRSHLQ_U8:
- case ARM64_INTRIN_VRSUBHN_S16:
- case ARM64_INTRIN_VRSUBHN_S32:
- case ARM64_INTRIN_VRSUBHN_S64:
- case ARM64_INTRIN_VRSUBHN_U16:
- case ARM64_INTRIN_VRSUBHN_U32:
- case ARM64_INTRIN_VRSUBHN_U64:
- case ARM64_INTRIN_VSHA1SU1Q_U32:
- case ARM64_INTRIN_VSHA256SU0Q_U32:
- case ARM64_INTRIN_VSHA512SU0Q_U64:
- case ARM64_INTRIN_VSHLQ_S16:
- case ARM64_INTRIN_VSHLQ_S32:
- case ARM64_INTRIN_VSHLQ_S64:
- case ARM64_INTRIN_VSHLQ_S8:
- case ARM64_INTRIN_VSHLQ_U16:
- case ARM64_INTRIN_VSHLQ_U32:
- case ARM64_INTRIN_VSHLQ_U64:
- case ARM64_INTRIN_VSHLQ_U8:
- case ARM64_INTRIN_VSM4EKEYQ_U32:
- case ARM64_INTRIN_VSM4EQ_U32:
- case ARM64_INTRIN_VSQADDQ_U16:
- case ARM64_INTRIN_VSQADDQ_U32:
- case ARM64_INTRIN_VSQADDQ_U64:
- case ARM64_INTRIN_VSQADDQ_U8:
- case ARM64_INTRIN_VSUBHN_S16:
- case ARM64_INTRIN_VSUBHN_S32:
- case ARM64_INTRIN_VSUBHN_S64:
- case ARM64_INTRIN_VSUBHN_U16:
- case ARM64_INTRIN_VSUBHN_U32:
- case ARM64_INTRIN_VSUBHN_U64:
- case ARM64_INTRIN_VSUBL_HIGH_S16:
- case ARM64_INTRIN_VSUBL_HIGH_S32:
- case ARM64_INTRIN_VSUBL_HIGH_S8:
- case ARM64_INTRIN_VSUBL_HIGH_U16:
- case ARM64_INTRIN_VSUBL_HIGH_U32:
- case ARM64_INTRIN_VSUBL_HIGH_U8:
- case ARM64_INTRIN_VSUBQ_S16:
- case ARM64_INTRIN_VSUBQ_S32:
- case ARM64_INTRIN_VSUBQ_S64:
- case ARM64_INTRIN_VSUBQ_S8:
- case ARM64_INTRIN_VSUBQ_U16:
- case ARM64_INTRIN_VSUBQ_U32:
- case ARM64_INTRIN_VSUBQ_U64:
- case ARM64_INTRIN_VSUBQ_U8:
- case ARM64_INTRIN_VSUBW_HIGH_S16:
- case ARM64_INTRIN_VSUBW_HIGH_S32:
- case ARM64_INTRIN_VSUBW_HIGH_S8:
- case ARM64_INTRIN_VSUBW_HIGH_U16:
- case ARM64_INTRIN_VSUBW_HIGH_U32:
- case ARM64_INTRIN_VSUBW_HIGH_U8:
- case ARM64_INTRIN_VTRN1Q_P16:
- case ARM64_INTRIN_VTRN1Q_P64:
- case ARM64_INTRIN_VTRN1Q_P8:
- case ARM64_INTRIN_VTRN1Q_S16:
- case ARM64_INTRIN_VTRN1Q_S32:
- case ARM64_INTRIN_VTRN1Q_S64:
- case ARM64_INTRIN_VTRN1Q_S8:
- case ARM64_INTRIN_VTRN1Q_U16:
- case ARM64_INTRIN_VTRN1Q_U32:
- case ARM64_INTRIN_VTRN1Q_U64:
- case ARM64_INTRIN_VTRN1Q_U8:
- case ARM64_INTRIN_VTRN2Q_P16:
- case ARM64_INTRIN_VTRN2Q_P64:
- case ARM64_INTRIN_VTRN2Q_P8:
- case ARM64_INTRIN_VTRN2Q_S16:
- case ARM64_INTRIN_VTRN2Q_S32:
- case ARM64_INTRIN_VTRN2Q_S64:
- case ARM64_INTRIN_VTRN2Q_S8:
- case ARM64_INTRIN_VTRN2Q_U16:
- case ARM64_INTRIN_VTRN2Q_U32:
- case ARM64_INTRIN_VTRN2Q_U64:
- case ARM64_INTRIN_VTRN2Q_U8:
- case ARM64_INTRIN_VTSTQ_P64:
- case ARM64_INTRIN_VTSTQ_P8:
- case ARM64_INTRIN_VTSTQ_S16:
- case ARM64_INTRIN_VTSTQ_S32:
- case ARM64_INTRIN_VTSTQ_S64:
- case ARM64_INTRIN_VTSTQ_S8:
- case ARM64_INTRIN_VTSTQ_U16:
- case ARM64_INTRIN_VTSTQ_U32:
- case ARM64_INTRIN_VTSTQ_U64:
- case ARM64_INTRIN_VTSTQ_U8:
- case ARM64_INTRIN_VUQADDQ_S16:
- case ARM64_INTRIN_VUQADDQ_S32:
- case ARM64_INTRIN_VUQADDQ_S64:
- case ARM64_INTRIN_VUQADDQ_S8:
- case ARM64_INTRIN_VUZP1Q_P16:
- case ARM64_INTRIN_VUZP1Q_P64:
- case ARM64_INTRIN_VUZP1Q_P8:
- case ARM64_INTRIN_VUZP1Q_S16:
- case ARM64_INTRIN_VUZP1Q_S32:
- case ARM64_INTRIN_VUZP1Q_S64:
- case ARM64_INTRIN_VUZP1Q_S8:
- case ARM64_INTRIN_VUZP1Q_U16:
- case ARM64_INTRIN_VUZP1Q_U32:
- case ARM64_INTRIN_VUZP1Q_U64:
- case ARM64_INTRIN_VUZP1Q_U8:
- case ARM64_INTRIN_VUZP2Q_P16:
- case ARM64_INTRIN_VUZP2Q_P64:
- case ARM64_INTRIN_VUZP2Q_P8:
- case ARM64_INTRIN_VUZP2Q_S16:
- case ARM64_INTRIN_VUZP2Q_S32:
- case ARM64_INTRIN_VUZP2Q_S64:
- case ARM64_INTRIN_VUZP2Q_S8:
- case ARM64_INTRIN_VUZP2Q_U16:
- case ARM64_INTRIN_VUZP2Q_U32:
- case ARM64_INTRIN_VUZP2Q_U64:
- case ARM64_INTRIN_VUZP2Q_U8:
- case ARM64_INTRIN_VZIP1Q_P16:
- case ARM64_INTRIN_VZIP1Q_P64:
- case ARM64_INTRIN_VZIP1Q_P8:
- case ARM64_INTRIN_VZIP1Q_S16:
- case ARM64_INTRIN_VZIP1Q_S32:
- case ARM64_INTRIN_VZIP1Q_S64:
- case ARM64_INTRIN_VZIP1Q_S8:
- case ARM64_INTRIN_VZIP1Q_U16:
- case ARM64_INTRIN_VZIP1Q_U32:
- case ARM64_INTRIN_VZIP1Q_U64:
- case ARM64_INTRIN_VZIP1Q_U8:
- case ARM64_INTRIN_VZIP2Q_P16:
- case ARM64_INTRIN_VZIP2Q_P64:
- case ARM64_INTRIN_VZIP2Q_P8:
- case ARM64_INTRIN_VZIP2Q_S16:
- case ARM64_INTRIN_VZIP2Q_S32:
- case ARM64_INTRIN_VZIP2Q_S64:
- case ARM64_INTRIN_VZIP2Q_S8:
- case ARM64_INTRIN_VZIP2Q_U16:
- case ARM64_INTRIN_VZIP2Q_U32:
- case ARM64_INTRIN_VZIP2Q_U64:
- case ARM64_INTRIN_VZIP2Q_U8:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false))};
- case ARM64_INTRIN_VABAL_HIGH_S16:
- case ARM64_INTRIN_VABAL_HIGH_S32:
- case ARM64_INTRIN_VABAL_HIGH_S8:
- case ARM64_INTRIN_VABAL_HIGH_U16:
- case ARM64_INTRIN_VABAL_HIGH_U32:
- case ARM64_INTRIN_VABAL_HIGH_U8:
- case ARM64_INTRIN_VABAQ_S16:
- case ARM64_INTRIN_VABAQ_S32:
- case ARM64_INTRIN_VABAQ_S8:
- case ARM64_INTRIN_VABAQ_U16:
- case ARM64_INTRIN_VABAQ_U32:
- case ARM64_INTRIN_VABAQ_U8:
- case ARM64_INTRIN_VBCAXQ_S16:
- case ARM64_INTRIN_VBCAXQ_S32:
- case ARM64_INTRIN_VBCAXQ_S64:
- case ARM64_INTRIN_VBCAXQ_S8:
- case ARM64_INTRIN_VBCAXQ_U16:
- case ARM64_INTRIN_VBCAXQ_U32:
- case ARM64_INTRIN_VBCAXQ_U64:
- case ARM64_INTRIN_VBCAXQ_U8:
- case ARM64_INTRIN_VBSLQ_P16:
- case ARM64_INTRIN_VBSLQ_P64:
- case ARM64_INTRIN_VBSLQ_P8:
- case ARM64_INTRIN_VBSLQ_S16:
- case ARM64_INTRIN_VBSLQ_S32:
- case ARM64_INTRIN_VBSLQ_S64:
- case ARM64_INTRIN_VBSLQ_S8:
- case ARM64_INTRIN_VBSLQ_U16:
- case ARM64_INTRIN_VBSLQ_U32:
- case ARM64_INTRIN_VBSLQ_U64:
- case ARM64_INTRIN_VBSLQ_U8:
- case ARM64_INTRIN_VDOTQ_S32:
- case ARM64_INTRIN_VDOTQ_U32:
- case ARM64_INTRIN_VEOR3Q_S16:
- case ARM64_INTRIN_VEOR3Q_S32:
- case ARM64_INTRIN_VEOR3Q_S64:
- case ARM64_INTRIN_VEOR3Q_S8:
- case ARM64_INTRIN_VEOR3Q_U16:
- case ARM64_INTRIN_VEOR3Q_U32:
- case ARM64_INTRIN_VEOR3Q_U64:
- case ARM64_INTRIN_VEOR3Q_U8:
- case ARM64_INTRIN_VMLAL_HIGH_S16:
- case ARM64_INTRIN_VMLAL_HIGH_S32:
- case ARM64_INTRIN_VMLAL_HIGH_S8:
- case ARM64_INTRIN_VMLAL_HIGH_U16:
- case ARM64_INTRIN_VMLAL_HIGH_U32:
- case ARM64_INTRIN_VMLAL_HIGH_U8:
- case ARM64_INTRIN_VMLAQ_S16:
- case ARM64_INTRIN_VMLAQ_S32:
- case ARM64_INTRIN_VMLAQ_S8:
- case ARM64_INTRIN_VMLAQ_U16:
- case ARM64_INTRIN_VMLAQ_U32:
- case ARM64_INTRIN_VMLAQ_U8:
- case ARM64_INTRIN_VMLSL_HIGH_S16:
- case ARM64_INTRIN_VMLSL_HIGH_S32:
- case ARM64_INTRIN_VMLSL_HIGH_S8:
- case ARM64_INTRIN_VMLSL_HIGH_U16:
- case ARM64_INTRIN_VMLSL_HIGH_U32:
- case ARM64_INTRIN_VMLSL_HIGH_U8:
- case ARM64_INTRIN_VMLSQ_S16:
- case ARM64_INTRIN_VMLSQ_S32:
- case ARM64_INTRIN_VMLSQ_S8:
- case ARM64_INTRIN_VMLSQ_U16:
- case ARM64_INTRIN_VMLSQ_U32:
- case ARM64_INTRIN_VMLSQ_U8:
- case ARM64_INTRIN_VMMLAQ_S32:
- case ARM64_INTRIN_VMMLAQ_U32:
- case ARM64_INTRIN_VQDMLAL_HIGH_S16:
- case ARM64_INTRIN_VQDMLAL_HIGH_S32:
- case ARM64_INTRIN_VQDMLSL_HIGH_S16:
- case ARM64_INTRIN_VQDMLSL_HIGH_S32:
- case ARM64_INTRIN_VQRDMLAHQ_S16:
- case ARM64_INTRIN_VQRDMLAHQ_S32:
- case ARM64_INTRIN_VQRDMLSHQ_S16:
- case ARM64_INTRIN_VQRDMLSHQ_S32:
- case ARM64_INTRIN_VSHA1SU0Q_U32:
- case ARM64_INTRIN_VSHA256H2Q_U32:
- case ARM64_INTRIN_VSHA256HQ_U32:
- case ARM64_INTRIN_VSHA256SU1Q_U32:
- case ARM64_INTRIN_VSHA512H2Q_U64:
- case ARM64_INTRIN_VSHA512HQ_U64:
- case ARM64_INTRIN_VSHA512SU1Q_U64:
- case ARM64_INTRIN_VSM3PARTW1Q_U32:
- case ARM64_INTRIN_VSM3PARTW2Q_U32:
- case ARM64_INTRIN_VSM3SS1Q_U32:
- case ARM64_INTRIN_VUSDOTQ_S32:
- case ARM64_INTRIN_VUSMMLAQ_S32:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false)),
- NameAndType(Type::IntegerType(16, false))};
- case ARM64_INTRIN_VDOTQ_LANEQ_S32:
- case ARM64_INTRIN_VDOTQ_LANEQ_U32:
- case ARM64_INTRIN_VMLAL_HIGH_LANEQ_S16:
- case ARM64_INTRIN_VMLAL_HIGH_LANEQ_S32:
- case ARM64_INTRIN_VMLAL_HIGH_LANEQ_U16:
- case ARM64_INTRIN_VMLAL_HIGH_LANEQ_U32:
- case ARM64_INTRIN_VMLAQ_LANEQ_S16:
- case ARM64_INTRIN_VMLAQ_LANEQ_S32:
- case ARM64_INTRIN_VMLAQ_LANEQ_U16:
- case ARM64_INTRIN_VMLAQ_LANEQ_U32:
- case ARM64_INTRIN_VMLSL_HIGH_LANEQ_S16:
- case ARM64_INTRIN_VMLSL_HIGH_LANEQ_S32:
- case ARM64_INTRIN_VMLSL_HIGH_LANEQ_U16:
- case ARM64_INTRIN_VMLSL_HIGH_LANEQ_U32:
- case ARM64_INTRIN_VMLSQ_LANEQ_S16:
- case ARM64_INTRIN_VMLSQ_LANEQ_S32:
- case ARM64_INTRIN_VMLSQ_LANEQ_U16:
- case ARM64_INTRIN_VMLSQ_LANEQ_U32:
- case ARM64_INTRIN_VQDMLAL_HIGH_LANEQ_S16:
- case ARM64_INTRIN_VQDMLAL_HIGH_LANEQ_S32:
- case ARM64_INTRIN_VQDMLSL_HIGH_LANEQ_S16:
- case ARM64_INTRIN_VQDMLSL_HIGH_LANEQ_S32:
- case ARM64_INTRIN_VQRDMLAHQ_LANEQ_S16:
- case ARM64_INTRIN_VQRDMLAHQ_LANEQ_S32:
- case ARM64_INTRIN_VQRDMLSHQ_LANEQ_S16:
- case ARM64_INTRIN_VQRDMLSHQ_LANEQ_S32:
- case ARM64_INTRIN_VSM3TT1AQ_U32:
- case ARM64_INTRIN_VSM3TT1BQ_U32:
- case ARM64_INTRIN_VSM3TT2AQ_U32:
- case ARM64_INTRIN_VSM3TT2BQ_U32:
- case ARM64_INTRIN_VSUDOTQ_LANEQ_S32:
- case ARM64_INTRIN_VUSDOTQ_LANEQ_S32:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false)),
- NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VMLAL_HIGH_N_S16:
- case ARM64_INTRIN_VMLAL_HIGH_N_U16:
- case ARM64_INTRIN_VMLAQ_N_S16:
- case ARM64_INTRIN_VMLAQ_N_U16:
- case ARM64_INTRIN_VMLSL_HIGH_N_S16:
- case ARM64_INTRIN_VMLSL_HIGH_N_U16:
- case ARM64_INTRIN_VMLSQ_N_S16:
- case ARM64_INTRIN_VMLSQ_N_U16:
- case ARM64_INTRIN_VQDMLAL_HIGH_N_S16:
- case ARM64_INTRIN_VQDMLSL_HIGH_N_S16:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false)),
- NameAndType(Type::IntegerType(2, false))};
- case ARM64_INTRIN_VEXTQ_P16:
- case ARM64_INTRIN_VEXTQ_P64:
- case ARM64_INTRIN_VEXTQ_P8:
- case ARM64_INTRIN_VEXTQ_S16:
- case ARM64_INTRIN_VEXTQ_S32:
- case ARM64_INTRIN_VEXTQ_S64:
- case ARM64_INTRIN_VEXTQ_S8:
- case ARM64_INTRIN_VEXTQ_U16:
- case ARM64_INTRIN_VEXTQ_U32:
- case ARM64_INTRIN_VEXTQ_U64:
- case ARM64_INTRIN_VEXTQ_U8:
- case ARM64_INTRIN_VMLAL_HIGH_N_S32:
- case ARM64_INTRIN_VMLAL_HIGH_N_U32:
- case ARM64_INTRIN_VMLAQ_N_S32:
- case ARM64_INTRIN_VMLAQ_N_U32:
- case ARM64_INTRIN_VMLSL_HIGH_N_S32:
- case ARM64_INTRIN_VMLSL_HIGH_N_U32:
- case ARM64_INTRIN_VMLSQ_N_S32:
- case ARM64_INTRIN_VMLSQ_N_U32:
- case ARM64_INTRIN_VMULL_HIGH_LANEQ_S16:
- case ARM64_INTRIN_VMULL_HIGH_LANEQ_S32:
- case ARM64_INTRIN_VMULL_HIGH_LANEQ_U16:
- case ARM64_INTRIN_VMULL_HIGH_LANEQ_U32:
- case ARM64_INTRIN_VMULQ_LANEQ_S16:
- case ARM64_INTRIN_VMULQ_LANEQ_S32:
- case ARM64_INTRIN_VMULQ_LANEQ_U16:
- case ARM64_INTRIN_VMULQ_LANEQ_U32:
- case ARM64_INTRIN_VQDMLAL_HIGH_N_S32:
- case ARM64_INTRIN_VQDMLSL_HIGH_N_S32:
- case ARM64_INTRIN_VQDMULHQ_LANEQ_S16:
- case ARM64_INTRIN_VQDMULHQ_LANEQ_S32:
- case ARM64_INTRIN_VQDMULL_HIGH_LANEQ_S16:
- case ARM64_INTRIN_VQDMULL_HIGH_LANEQ_S32:
- case ARM64_INTRIN_VQRDMULHQ_LANEQ_S16:
- case ARM64_INTRIN_VQRDMULHQ_LANEQ_S32:
- case ARM64_INTRIN_VRSRAQ_N_S16:
- case ARM64_INTRIN_VRSRAQ_N_S32:
- case ARM64_INTRIN_VRSRAQ_N_S64:
- case ARM64_INTRIN_VRSRAQ_N_S8:
- case ARM64_INTRIN_VRSRAQ_N_U16:
- case ARM64_INTRIN_VRSRAQ_N_U32:
- case ARM64_INTRIN_VRSRAQ_N_U64:
- case ARM64_INTRIN_VRSRAQ_N_U8:
- case ARM64_INTRIN_VSLIQ_N_P16:
- case ARM64_INTRIN_VSLIQ_N_P64:
- case ARM64_INTRIN_VSLIQ_N_P8:
- case ARM64_INTRIN_VSLIQ_N_S16:
- case ARM64_INTRIN_VSLIQ_N_S32:
- case ARM64_INTRIN_VSLIQ_N_S64:
- case ARM64_INTRIN_VSLIQ_N_S8:
- case ARM64_INTRIN_VSLIQ_N_U16:
- case ARM64_INTRIN_VSLIQ_N_U32:
- case ARM64_INTRIN_VSLIQ_N_U64:
- case ARM64_INTRIN_VSLIQ_N_U8:
- case ARM64_INTRIN_VSRAQ_N_S16:
- case ARM64_INTRIN_VSRAQ_N_S32:
- case ARM64_INTRIN_VSRAQ_N_S64:
- case ARM64_INTRIN_VSRAQ_N_S8:
- case ARM64_INTRIN_VSRAQ_N_U16:
- case ARM64_INTRIN_VSRAQ_N_U32:
- case ARM64_INTRIN_VSRAQ_N_U64:
- case ARM64_INTRIN_VSRAQ_N_U8:
- case ARM64_INTRIN_VSRIQ_N_P16:
- case ARM64_INTRIN_VSRIQ_N_P64:
- case ARM64_INTRIN_VSRIQ_N_P8:
- case ARM64_INTRIN_VSRIQ_N_S16:
- case ARM64_INTRIN_VSRIQ_N_S32:
- case ARM64_INTRIN_VSRIQ_N_S64:
- case ARM64_INTRIN_VSRIQ_N_S8:
- case ARM64_INTRIN_VSRIQ_N_U16:
- case ARM64_INTRIN_VSRIQ_N_U32:
- case ARM64_INTRIN_VSRIQ_N_U64:
- case ARM64_INTRIN_VSRIQ_N_U8:
- case ARM64_INTRIN_VXARQ_U64:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VDOTQ_LANE_S32:
- case ARM64_INTRIN_VDOTQ_LANE_U32:
- case ARM64_INTRIN_VMLAL_HIGH_LANE_S16:
- case ARM64_INTRIN_VMLAL_HIGH_LANE_S32:
- case ARM64_INTRIN_VMLAL_HIGH_LANE_U16:
- case ARM64_INTRIN_VMLAL_HIGH_LANE_U32:
- case ARM64_INTRIN_VMLAQ_LANE_S16:
- case ARM64_INTRIN_VMLAQ_LANE_S32:
- case ARM64_INTRIN_VMLAQ_LANE_U16:
- case ARM64_INTRIN_VMLAQ_LANE_U32:
- case ARM64_INTRIN_VMLSL_HIGH_LANE_S16:
- case ARM64_INTRIN_VMLSL_HIGH_LANE_S32:
- case ARM64_INTRIN_VMLSL_HIGH_LANE_U16:
- case ARM64_INTRIN_VMLSL_HIGH_LANE_U32:
- case ARM64_INTRIN_VMLSQ_LANE_S16:
- case ARM64_INTRIN_VMLSQ_LANE_S32:
- case ARM64_INTRIN_VMLSQ_LANE_U16:
- case ARM64_INTRIN_VMLSQ_LANE_U32:
- case ARM64_INTRIN_VQDMLAL_HIGH_LANE_S16:
- case ARM64_INTRIN_VQDMLAL_HIGH_LANE_S32:
- case ARM64_INTRIN_VQDMLSL_HIGH_LANE_S16:
- case ARM64_INTRIN_VQDMLSL_HIGH_LANE_S32:
- case ARM64_INTRIN_VQRDMLAHQ_LANE_S16:
- case ARM64_INTRIN_VQRDMLAHQ_LANE_S32:
- case ARM64_INTRIN_VQRDMLSHQ_LANE_S16:
- case ARM64_INTRIN_VQRDMLSHQ_LANE_S32:
- case ARM64_INTRIN_VSUDOTQ_LANE_S32:
- case ARM64_INTRIN_VUSDOTQ_LANE_S32:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false)),
- NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VMULL_HIGH_N_S16:
- case ARM64_INTRIN_VMULL_HIGH_N_U16:
- case ARM64_INTRIN_VMULQ_N_S16:
- case ARM64_INTRIN_VMULQ_N_U16:
- case ARM64_INTRIN_VQDMULHQ_N_S16:
- case ARM64_INTRIN_VQDMULL_HIGH_N_S16:
- case ARM64_INTRIN_VQRDMULHQ_N_S16:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(2, false))};
- case ARM64_INTRIN_VCVTQ_N_F16_S16:
- case ARM64_INTRIN_VCVTQ_N_F16_U16:
- case ARM64_INTRIN_VCVTQ_N_F32_S32:
- case ARM64_INTRIN_VCVTQ_N_F32_U32:
- case ARM64_INTRIN_VCVTQ_N_F64_S64:
- case ARM64_INTRIN_VCVTQ_N_F64_U64:
- case ARM64_INTRIN_VDUP_LANEQ_P16:
- case ARM64_INTRIN_VDUP_LANEQ_P64:
- case ARM64_INTRIN_VDUP_LANEQ_P8:
- case ARM64_INTRIN_VDUP_LANEQ_S16:
- case ARM64_INTRIN_VDUP_LANEQ_S32:
- case ARM64_INTRIN_VDUP_LANEQ_S64:
- case ARM64_INTRIN_VDUP_LANEQ_S8:
- case ARM64_INTRIN_VDUP_LANEQ_U16:
- case ARM64_INTRIN_VDUP_LANEQ_U32:
- case ARM64_INTRIN_VDUP_LANEQ_U64:
- case ARM64_INTRIN_VDUP_LANEQ_U8:
- case ARM64_INTRIN_VDUPB_LANEQ_P8:
- case ARM64_INTRIN_VDUPB_LANEQ_S8:
- case ARM64_INTRIN_VDUPB_LANEQ_U8:
- case ARM64_INTRIN_VDUPD_LANEQ_S64:
- case ARM64_INTRIN_VDUPD_LANEQ_U64:
- case ARM64_INTRIN_VDUPH_LANEQ_P16:
- case ARM64_INTRIN_VDUPH_LANEQ_S16:
- case ARM64_INTRIN_VDUPH_LANEQ_U16:
- case ARM64_INTRIN_VDUPQ_LANEQ_P16:
- case ARM64_INTRIN_VDUPQ_LANEQ_P64:
- case ARM64_INTRIN_VDUPQ_LANEQ_P8:
- case ARM64_INTRIN_VDUPQ_LANEQ_S16:
- case ARM64_INTRIN_VDUPQ_LANEQ_S32:
- case ARM64_INTRIN_VDUPQ_LANEQ_S64:
- case ARM64_INTRIN_VDUPQ_LANEQ_S8:
- case ARM64_INTRIN_VDUPQ_LANEQ_U16:
- case ARM64_INTRIN_VDUPQ_LANEQ_U32:
- case ARM64_INTRIN_VDUPQ_LANEQ_U64:
- case ARM64_INTRIN_VDUPQ_LANEQ_U8:
- case ARM64_INTRIN_VDUPS_LANEQ_S32:
- case ARM64_INTRIN_VDUPS_LANEQ_U32:
- case ARM64_INTRIN_VGETQ_LANE_P16:
- case ARM64_INTRIN_VGETQ_LANE_P64:
- case ARM64_INTRIN_VGETQ_LANE_P8:
- case ARM64_INTRIN_VGETQ_LANE_S16:
- case ARM64_INTRIN_VGETQ_LANE_S32:
- case ARM64_INTRIN_VGETQ_LANE_S64:
- case ARM64_INTRIN_VGETQ_LANE_S8:
- case ARM64_INTRIN_VGETQ_LANE_U16:
- case ARM64_INTRIN_VGETQ_LANE_U32:
- case ARM64_INTRIN_VGETQ_LANE_U64:
- case ARM64_INTRIN_VGETQ_LANE_U8:
- case ARM64_INTRIN_VMULL_HIGH_N_S32:
- case ARM64_INTRIN_VMULL_HIGH_N_U32:
- case ARM64_INTRIN_VMULQ_N_S32:
- case ARM64_INTRIN_VMULQ_N_U32:
- case ARM64_INTRIN_VQDMULHQ_N_S32:
- case ARM64_INTRIN_VQDMULL_HIGH_N_S32:
- case ARM64_INTRIN_VQRDMULHQ_N_S32:
- case ARM64_INTRIN_VQRSHRN_N_S16:
- case ARM64_INTRIN_VQRSHRN_N_S32:
- case ARM64_INTRIN_VQRSHRN_N_S64:
- case ARM64_INTRIN_VQRSHRN_N_U16:
- case ARM64_INTRIN_VQRSHRN_N_U32:
- case ARM64_INTRIN_VQRSHRN_N_U64:
- case ARM64_INTRIN_VQRSHRUN_N_S16:
- case ARM64_INTRIN_VQRSHRUN_N_S32:
- case ARM64_INTRIN_VQRSHRUN_N_S64:
- case ARM64_INTRIN_VQSHLQ_N_S16:
- case ARM64_INTRIN_VQSHLQ_N_S32:
- case ARM64_INTRIN_VQSHLQ_N_S64:
- case ARM64_INTRIN_VQSHLQ_N_S8:
- case ARM64_INTRIN_VQSHLQ_N_U16:
- case ARM64_INTRIN_VQSHLQ_N_U32:
- case ARM64_INTRIN_VQSHLQ_N_U64:
- case ARM64_INTRIN_VQSHLQ_N_U8:
- case ARM64_INTRIN_VQSHLUQ_N_S16:
- case ARM64_INTRIN_VQSHLUQ_N_S32:
- case ARM64_INTRIN_VQSHLUQ_N_S64:
- case ARM64_INTRIN_VQSHLUQ_N_S8:
- case ARM64_INTRIN_VQSHRN_N_S16:
- case ARM64_INTRIN_VQSHRN_N_S32:
- case ARM64_INTRIN_VQSHRN_N_S64:
- case ARM64_INTRIN_VQSHRN_N_U16:
- case ARM64_INTRIN_VQSHRN_N_U32:
- case ARM64_INTRIN_VQSHRN_N_U64:
- case ARM64_INTRIN_VQSHRUN_N_S16:
- case ARM64_INTRIN_VQSHRUN_N_S32:
- case ARM64_INTRIN_VQSHRUN_N_S64:
- case ARM64_INTRIN_VRSHRN_N_S16:
- case ARM64_INTRIN_VRSHRN_N_S32:
- case ARM64_INTRIN_VRSHRN_N_S64:
- case ARM64_INTRIN_VRSHRN_N_U16:
- case ARM64_INTRIN_VRSHRN_N_U32:
- case ARM64_INTRIN_VRSHRN_N_U64:
- case ARM64_INTRIN_VRSHRQ_N_S16:
- case ARM64_INTRIN_VRSHRQ_N_S32:
- case ARM64_INTRIN_VRSHRQ_N_S64:
- case ARM64_INTRIN_VRSHRQ_N_S8:
- case ARM64_INTRIN_VRSHRQ_N_U16:
- case ARM64_INTRIN_VRSHRQ_N_U32:
- case ARM64_INTRIN_VRSHRQ_N_U64:
- case ARM64_INTRIN_VRSHRQ_N_U8:
- case ARM64_INTRIN_VSHLL_HIGH_N_S16:
- case ARM64_INTRIN_VSHLL_HIGH_N_S32:
- case ARM64_INTRIN_VSHLL_HIGH_N_S8:
- case ARM64_INTRIN_VSHLL_HIGH_N_U16:
- case ARM64_INTRIN_VSHLL_HIGH_N_U32:
- case ARM64_INTRIN_VSHLL_HIGH_N_U8:
- case ARM64_INTRIN_VSHLQ_N_S16:
- case ARM64_INTRIN_VSHLQ_N_S32:
- case ARM64_INTRIN_VSHLQ_N_S64:
- case ARM64_INTRIN_VSHLQ_N_S8:
- case ARM64_INTRIN_VSHLQ_N_U16:
- case ARM64_INTRIN_VSHLQ_N_U32:
- case ARM64_INTRIN_VSHLQ_N_U64:
- case ARM64_INTRIN_VSHLQ_N_U8:
- case ARM64_INTRIN_VSHRN_N_S16:
- case ARM64_INTRIN_VSHRN_N_S32:
- case ARM64_INTRIN_VSHRN_N_S64:
- case ARM64_INTRIN_VSHRN_N_U16:
- case ARM64_INTRIN_VSHRN_N_U32:
- case ARM64_INTRIN_VSHRN_N_U64:
- case ARM64_INTRIN_VSHRQ_N_S16:
- case ARM64_INTRIN_VSHRQ_N_S32:
- case ARM64_INTRIN_VSHRQ_N_S64:
- case ARM64_INTRIN_VSHRQ_N_S8:
- case ARM64_INTRIN_VSHRQ_N_U16:
- case ARM64_INTRIN_VSHRQ_N_U32:
- case ARM64_INTRIN_VSHRQ_N_U64:
- case ARM64_INTRIN_VSHRQ_N_U8:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VSHA1CQ_U32:
- case ARM64_INTRIN_VSHA1MQ_U32:
- case ARM64_INTRIN_VSHA1PQ_U32:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false)),
- NameAndType(Type::IntegerType(16, false))};
- case ARM64_INTRIN_VADDW_S16:
- case ARM64_INTRIN_VADDW_S32:
- case ARM64_INTRIN_VADDW_S8:
- case ARM64_INTRIN_VADDW_U16:
- case ARM64_INTRIN_VADDW_U32:
- case ARM64_INTRIN_VADDW_U8:
- case ARM64_INTRIN_VSUBW_S16:
- case ARM64_INTRIN_VSUBW_S32:
- case ARM64_INTRIN_VSUBW_S8:
- case ARM64_INTRIN_VSUBW_U16:
- case ARM64_INTRIN_VSUBW_U32:
- case ARM64_INTRIN_VSUBW_U8:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(8, false))};
- case ARM64_INTRIN_VMLAL_LANEQ_S16:
- case ARM64_INTRIN_VMLAL_LANEQ_S32:
- case ARM64_INTRIN_VMLAL_LANEQ_U16:
- case ARM64_INTRIN_VMLAL_LANEQ_U32:
- case ARM64_INTRIN_VMLSL_LANEQ_S16:
- case ARM64_INTRIN_VMLSL_LANEQ_S32:
- case ARM64_INTRIN_VMLSL_LANEQ_U16:
- case ARM64_INTRIN_VMLSL_LANEQ_U32:
- case ARM64_INTRIN_VQDMLAL_LANEQ_S16:
- case ARM64_INTRIN_VQDMLAL_LANEQ_S32:
- case ARM64_INTRIN_VQDMLSL_LANEQ_S16:
- case ARM64_INTRIN_VQDMLSL_LANEQ_S32:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(8, false)),
- NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VMLAL_N_S16:
- case ARM64_INTRIN_VMLAL_N_U16:
- case ARM64_INTRIN_VMLSL_N_S16:
- case ARM64_INTRIN_VMLSL_N_U16:
- case ARM64_INTRIN_VQDMLAL_N_S16:
- case ARM64_INTRIN_VQDMLSL_N_S16:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(8, false)),
- NameAndType(Type::IntegerType(2, false))};
- case ARM64_INTRIN_VMLAL_N_S32:
- case ARM64_INTRIN_VMLAL_N_U32:
- case ARM64_INTRIN_VMLSL_N_S32:
- case ARM64_INTRIN_VMLSL_N_U32:
- case ARM64_INTRIN_VMULL_HIGH_LANE_S16:
- case ARM64_INTRIN_VMULL_HIGH_LANE_S32:
- case ARM64_INTRIN_VMULL_HIGH_LANE_U16:
- case ARM64_INTRIN_VMULL_HIGH_LANE_U32:
- case ARM64_INTRIN_VMULQ_LANE_S16:
- case ARM64_INTRIN_VMULQ_LANE_S32:
- case ARM64_INTRIN_VMULQ_LANE_U16:
- case ARM64_INTRIN_VMULQ_LANE_U32:
- case ARM64_INTRIN_VQDMLAL_N_S32:
- case ARM64_INTRIN_VQDMLSL_N_S32:
- case ARM64_INTRIN_VQDMULHQ_LANE_S16:
- case ARM64_INTRIN_VQDMULHQ_LANE_S32:
- case ARM64_INTRIN_VQDMULL_HIGH_LANE_S16:
- case ARM64_INTRIN_VQDMULL_HIGH_LANE_S32:
- case ARM64_INTRIN_VQRDMULHQ_LANE_S16:
- case ARM64_INTRIN_VQRDMULHQ_LANE_S32:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(8, false)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VABAL_S16:
- case ARM64_INTRIN_VABAL_S32:
- case ARM64_INTRIN_VABAL_S8:
- case ARM64_INTRIN_VABAL_U16:
- case ARM64_INTRIN_VABAL_U32:
- case ARM64_INTRIN_VABAL_U8:
- case ARM64_INTRIN_VMLAL_S16:
- case ARM64_INTRIN_VMLAL_S32:
- case ARM64_INTRIN_VMLAL_S8:
- case ARM64_INTRIN_VMLAL_U16:
- case ARM64_INTRIN_VMLAL_U32:
- case ARM64_INTRIN_VMLAL_U8:
- case ARM64_INTRIN_VMLSL_S16:
- case ARM64_INTRIN_VMLSL_S32:
- case ARM64_INTRIN_VMLSL_S8:
- case ARM64_INTRIN_VMLSL_U16:
- case ARM64_INTRIN_VMLSL_U32:
- case ARM64_INTRIN_VMLSL_U8:
- case ARM64_INTRIN_VQDMLAL_S16:
- case ARM64_INTRIN_VQDMLAL_S32:
- case ARM64_INTRIN_VQDMLSL_S16:
- case ARM64_INTRIN_VQDMLSL_S32:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(8, false)),
- NameAndType(Type::IntegerType(8, false))};
- case ARM64_INTRIN_VMLAL_LANE_S16:
- case ARM64_INTRIN_VMLAL_LANE_S32:
- case ARM64_INTRIN_VMLAL_LANE_U16:
- case ARM64_INTRIN_VMLAL_LANE_U32:
- case ARM64_INTRIN_VMLSL_LANE_S16:
- case ARM64_INTRIN_VMLSL_LANE_S32:
- case ARM64_INTRIN_VMLSL_LANE_U16:
- case ARM64_INTRIN_VMLSL_LANE_U32:
- case ARM64_INTRIN_VQDMLAL_LANE_S16:
- case ARM64_INTRIN_VQDMLAL_LANE_S32:
- case ARM64_INTRIN_VQDMLSL_LANE_S16:
- case ARM64_INTRIN_VQDMLSL_LANE_S32:
- return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(8, false)),
- NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VCVTH_F16_S16:
- case ARM64_INTRIN_VCVTH_F16_U16:
- case ARM64_INTRIN_VDUP_N_P16:
- case ARM64_INTRIN_VDUP_N_S16:
- case ARM64_INTRIN_VDUP_N_U16:
- case ARM64_INTRIN_VDUPQ_N_P16:
- case ARM64_INTRIN_VDUPQ_N_S16:
- case ARM64_INTRIN_VDUPQ_N_U16:
- case ARM64_INTRIN_VMOV_N_P16:
- case ARM64_INTRIN_VMOV_N_S16:
- case ARM64_INTRIN_VMOV_N_U16:
- case ARM64_INTRIN_VMOVQ_N_P16:
- case ARM64_INTRIN_VMOVQ_N_S16:
- case ARM64_INTRIN_VMOVQ_N_U16:
- case ARM64_INTRIN_VQABSH_S16:
- case ARM64_INTRIN_VQMOVNH_S16:
- case ARM64_INTRIN_VQMOVNH_U16:
- case ARM64_INTRIN_VQMOVUNH_S16:
- case ARM64_INTRIN_VQNEGH_S16:
- return {NameAndType(Type::IntegerType(2, false))};
- case ARM64_INTRIN_VQDMULHH_LANEQ_S16:
- case ARM64_INTRIN_VQDMULLH_LANEQ_S16:
- case ARM64_INTRIN_VQRDMULHH_LANEQ_S16:
- case ARM64_INTRIN_VSETQ_LANE_P16:
- case ARM64_INTRIN_VSETQ_LANE_S16:
- case ARM64_INTRIN_VSETQ_LANE_U16:
- return {NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(16, false)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VQADDH_S16:
- case ARM64_INTRIN_VQADDH_U16:
- case ARM64_INTRIN_VQDMULHH_S16:
- case ARM64_INTRIN_VQDMULLH_S16:
- case ARM64_INTRIN_VQRDMULHH_S16:
- case ARM64_INTRIN_VQRSHLH_S16:
- case ARM64_INTRIN_VQRSHLH_U16:
- case ARM64_INTRIN_VQSHLH_S16:
- case ARM64_INTRIN_VQSHLH_U16:
- case ARM64_INTRIN_VQSUBH_S16:
- case ARM64_INTRIN_VQSUBH_U16:
- case ARM64_INTRIN_VSQADDH_U16:
- case ARM64_INTRIN_VUQADDH_S16:
- return {NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false))};
- case ARM64_INTRIN_VQRDMLAHH_LANEQ_S16:
- case ARM64_INTRIN_VQRDMLSHH_LANEQ_S16:
- return {NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)),
- NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VQRDMLAHH_S16:
- case ARM64_INTRIN_VQRDMLSHH_S16:
- return {NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)),
- NameAndType(Type::IntegerType(2, false))};
- case ARM64_INTRIN_VQRDMLAHH_LANE_S16:
- case ARM64_INTRIN_VQRDMLSHH_LANE_S16:
- return {NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)),
- NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VCVTH_N_F16_S16:
- case ARM64_INTRIN_VCVTH_N_F16_U16:
- case ARM64_INTRIN_VQRSHRNH_N_S16:
- case ARM64_INTRIN_VQRSHRNH_N_U16:
- case ARM64_INTRIN_VQRSHRUNH_N_S16:
- case ARM64_INTRIN_VQSHLH_N_S16:
- case ARM64_INTRIN_VQSHLH_N_U16:
- case ARM64_INTRIN_VQSHLUH_N_S16:
- case ARM64_INTRIN_VQSHRNH_N_S16:
- case ARM64_INTRIN_VQSHRNH_N_U16:
- case ARM64_INTRIN_VQSHRUNH_N_S16:
- return {NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VQDMULHH_LANE_S16:
- case ARM64_INTRIN_VQDMULLH_LANE_S16:
- case ARM64_INTRIN_VQRDMULHH_LANE_S16:
- case ARM64_INTRIN_VSET_LANE_P16:
- case ARM64_INTRIN_VSET_LANE_S16:
- case ARM64_INTRIN_VSET_LANE_U16:
- return {NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VCVTH_F16_S32:
- case ARM64_INTRIN_VCVTH_F16_U32:
- case ARM64_INTRIN_VCVTS_F32_S32:
- case ARM64_INTRIN_VCVTS_F32_U32:
- case ARM64_INTRIN_VDUP_N_S32:
- case ARM64_INTRIN_VDUP_N_U32:
- case ARM64_INTRIN_VDUPQ_N_S32:
- case ARM64_INTRIN_VDUPQ_N_U32:
- case ARM64_INTRIN_VMOV_N_S32:
- case ARM64_INTRIN_VMOV_N_U32:
- case ARM64_INTRIN_VMOVQ_N_S32:
- case ARM64_INTRIN_VMOVQ_N_U32:
- case ARM64_INTRIN_VQABSS_S32:
- case ARM64_INTRIN_VQMOVNS_S32:
- case ARM64_INTRIN_VQMOVNS_U32:
- case ARM64_INTRIN_VQMOVUNS_S32:
- case ARM64_INTRIN_VQNEGS_S32:
- case ARM64_INTRIN_VSHA1H_U32:
- case ARM64_INTRIN_VCVT_F64_U32:
- return {NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN___CRC32B:
- case ARM64_INTRIN___CRC32CB:
- case ARM64_INTRIN_VCVTH_N_F16_U32:
- case ARM64_INTRIN_VCVTS_N_F32_U32:
- case ARM64_INTRIN_VCVTD_N_F64_U32:
- return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(1, false))};
- case ARM64_INTRIN_VCVTH_N_F16_U64:
- case ARM64_INTRIN_VCVTD_N_F64_U64:
- case ARM64_INTRIN_VCVTS_N_F32_U64:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(1, false))};
- case ARM64_INTRIN_VQDMULHS_LANEQ_S32:
- case ARM64_INTRIN_VQDMULLS_LANEQ_S32:
- case ARM64_INTRIN_VQRDMULHS_LANEQ_S32:
- case ARM64_INTRIN_VSETQ_LANE_S32:
- case ARM64_INTRIN_VSETQ_LANE_U32:
- return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(16, false)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN___CRC32CH:
- case ARM64_INTRIN___CRC32H:
- return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(2, false))};
- case ARM64_INTRIN_VQDMLALH_LANEQ_S16:
- case ARM64_INTRIN_VQDMLSLH_LANEQ_S16:
- return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(2, false)),
- NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VQDMLALH_S16:
- case ARM64_INTRIN_VQDMLSLH_S16:
- return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(2, false)),
- NameAndType(Type::IntegerType(2, false))};
- case ARM64_INTRIN_VQDMLALH_LANE_S16:
- case ARM64_INTRIN_VQDMLSLH_LANE_S16:
- return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(2, false)),
- NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN___CRC32CW:
- case ARM64_INTRIN___CRC32W:
- case ARM64_INTRIN_VCVTH_N_F16_S32:
- case ARM64_INTRIN_VCVTS_N_F32_S32:
- case ARM64_INTRIN_VQADDS_S32:
- case ARM64_INTRIN_VQADDS_U32:
- case ARM64_INTRIN_VQDMULHS_S32:
- case ARM64_INTRIN_VQDMULLS_S32:
- case ARM64_INTRIN_VQRDMULHS_S32:
- case ARM64_INTRIN_VQRSHLS_S32:
- case ARM64_INTRIN_VQRSHLS_U32:
- case ARM64_INTRIN_VQRSHRNS_N_S32:
- case ARM64_INTRIN_VQRSHRNS_N_U32:
- case ARM64_INTRIN_VQRSHRUNS_N_S32:
- case ARM64_INTRIN_VQSHLS_N_S32:
- case ARM64_INTRIN_VQSHLS_N_U32:
- case ARM64_INTRIN_VQSHLS_S32:
- case ARM64_INTRIN_VQSHLS_U32:
- case ARM64_INTRIN_VQSHLUS_N_S32:
- case ARM64_INTRIN_VQSHRNS_N_S32:
- case ARM64_INTRIN_VQSHRNS_N_U32:
- case ARM64_INTRIN_VQSHRUNS_N_S32:
- case ARM64_INTRIN_VQSUBS_S32:
- case ARM64_INTRIN_VQSUBS_U32:
- case ARM64_INTRIN_VSQADDS_U32:
- case ARM64_INTRIN_VUQADDS_S32:
- return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VQRDMLAHS_LANEQ_S32:
- case ARM64_INTRIN_VQRDMLSHS_LANEQ_S32:
- return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)),
- NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VQRDMLAHS_S32:
- case ARM64_INTRIN_VQRDMLSHS_S32:
- return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VQRDMLAHS_LANE_S32:
- case ARM64_INTRIN_VQRDMLSHS_LANE_S32:
- return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)),
- NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN___CRC32CD:
- case ARM64_INTRIN___CRC32D:
- return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(8, false))};
- case ARM64_INTRIN_VQDMULHS_LANE_S32:
- case ARM64_INTRIN_VQDMULLS_LANE_S32:
- case ARM64_INTRIN_VQRDMULHS_LANE_S32:
- case ARM64_INTRIN_VSET_LANE_S32:
- case ARM64_INTRIN_VSET_LANE_U32:
- return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(8, false)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VABS_S16:
- case ARM64_INTRIN_VABS_S32:
- case ARM64_INTRIN_VABS_S64:
- case ARM64_INTRIN_VABS_S8:
- case ARM64_INTRIN_VABSD_S64:
- case ARM64_INTRIN_VADDLV_S16:
- case ARM64_INTRIN_VADDLV_S32:
- case ARM64_INTRIN_VADDLV_S8:
- case ARM64_INTRIN_VADDLV_U16:
- case ARM64_INTRIN_VADDLV_U32:
- case ARM64_INTRIN_VADDLV_U8:
- case ARM64_INTRIN_VADDV_S16:
- case ARM64_INTRIN_VADDV_S32:
- case ARM64_INTRIN_VADDV_S8:
- case ARM64_INTRIN_VADDV_U16:
- case ARM64_INTRIN_VADDV_U32:
- case ARM64_INTRIN_VADDV_U8:
- case ARM64_INTRIN_VCEQZ_P64:
- case ARM64_INTRIN_VCEQZ_P8:
- case ARM64_INTRIN_VCEQZ_S16:
- case ARM64_INTRIN_VCEQZ_S32:
- case ARM64_INTRIN_VCEQZ_S64:
- case ARM64_INTRIN_VCEQZ_S8:
- case ARM64_INTRIN_VCEQZ_U16:
- case ARM64_INTRIN_VCEQZ_U32:
- case ARM64_INTRIN_VCEQZ_U64:
- case ARM64_INTRIN_VCEQZ_U8:
- case ARM64_INTRIN_VCEQZD_S64:
- case ARM64_INTRIN_VCEQZD_U64:
- case ARM64_INTRIN_VCGEZ_S16:
- case ARM64_INTRIN_VCGEZ_S32:
- case ARM64_INTRIN_VCGEZ_S64:
- case ARM64_INTRIN_VCGEZ_S8:
- case ARM64_INTRIN_VCGEZD_S64:
- case ARM64_INTRIN_VCGTZ_S16:
- case ARM64_INTRIN_VCGTZ_S32:
- case ARM64_INTRIN_VCGTZ_S64:
- case ARM64_INTRIN_VCGTZ_S8:
- case ARM64_INTRIN_VCGTZD_S64:
- case ARM64_INTRIN_VCLEZ_S16:
- case ARM64_INTRIN_VCLEZ_S32:
- case ARM64_INTRIN_VCLEZ_S64:
- case ARM64_INTRIN_VCLEZ_S8:
- case ARM64_INTRIN_VCLEZD_S64:
- case ARM64_INTRIN_VCLS_S16:
- case ARM64_INTRIN_VCLS_S32:
- case ARM64_INTRIN_VCLS_S8:
- case ARM64_INTRIN_VCLS_U16:
- case ARM64_INTRIN_VCLS_U32:
- case ARM64_INTRIN_VCLS_U8:
- case ARM64_INTRIN_VCLTZ_S16:
- case ARM64_INTRIN_VCLTZ_S32:
- case ARM64_INTRIN_VCLTZ_S64:
- case ARM64_INTRIN_VCLTZ_S8:
- case ARM64_INTRIN_VCLTZD_S64:
- case ARM64_INTRIN_VCLZ_S16:
- case ARM64_INTRIN_VCLZ_S32:
- case ARM64_INTRIN_VCLZ_S8:
- case ARM64_INTRIN_VCLZ_U16:
- case ARM64_INTRIN_VCLZ_U32:
- case ARM64_INTRIN_VCLZ_U8:
- case ARM64_INTRIN_VCNT_P8:
- case ARM64_INTRIN_VCNT_S8:
- case ARM64_INTRIN_VCNT_U8:
- case ARM64_INTRIN_VCREATE_BF16:
- case ARM64_INTRIN_VCREATE_F16:
- case ARM64_INTRIN_VCREATE_F32:
- case ARM64_INTRIN_VCREATE_F64:
- case ARM64_INTRIN_VCREATE_P16:
- case ARM64_INTRIN_VCREATE_P64:
- case ARM64_INTRIN_VCREATE_P8:
- case ARM64_INTRIN_VCREATE_S16:
- case ARM64_INTRIN_VCREATE_S32:
- case ARM64_INTRIN_VCREATE_S64:
- case ARM64_INTRIN_VCREATE_S8:
- case ARM64_INTRIN_VCREATE_U16:
- case ARM64_INTRIN_VCREATE_U32:
- case ARM64_INTRIN_VCREATE_U64:
- case ARM64_INTRIN_VCREATE_U8:
- case ARM64_INTRIN_VCVT_F16_S16:
- case ARM64_INTRIN_VCVT_F16_U16:
- case ARM64_INTRIN_VCVT_F32_S32:
- case ARM64_INTRIN_VCVT_F32_U32:
- case ARM64_INTRIN_VCVT_F64_S64:
- case ARM64_INTRIN_VCVT_F64_U64:
- case ARM64_INTRIN_VCVT_F32_U64:
- case ARM64_INTRIN_VCVTD_F64_S64:
- case ARM64_INTRIN_VCVTD_F64_U64:
- case ARM64_INTRIN_VCVTH_F16_S64:
- case ARM64_INTRIN_VCVTH_F16_U64:
- case ARM64_INTRIN_VDUP_N_P64:
- case ARM64_INTRIN_VDUP_N_S64:
- case ARM64_INTRIN_VDUP_N_U64:
- case ARM64_INTRIN_VDUPQ_N_P64:
- case ARM64_INTRIN_VDUPQ_N_S64:
- case ARM64_INTRIN_VDUPQ_N_U64:
- case ARM64_INTRIN_VMAXV_S16:
- case ARM64_INTRIN_VMAXV_S32:
- case ARM64_INTRIN_VMAXV_S8:
- case ARM64_INTRIN_VMAXV_U16:
- case ARM64_INTRIN_VMAXV_U32:
- case ARM64_INTRIN_VMAXV_U8:
- case ARM64_INTRIN_VMINV_S16:
- case ARM64_INTRIN_VMINV_S32:
- case ARM64_INTRIN_VMINV_S8:
- case ARM64_INTRIN_VMINV_U16:
- case ARM64_INTRIN_VMINV_U32:
- case ARM64_INTRIN_VMINV_U8:
- case ARM64_INTRIN_VMOV_N_S64:
- case ARM64_INTRIN_VMOV_N_U64:
- case ARM64_INTRIN_VMOVL_S16:
- case ARM64_INTRIN_VMOVL_S32:
- case ARM64_INTRIN_VMOVL_S8:
- case ARM64_INTRIN_VMOVL_U16:
- case ARM64_INTRIN_VMOVL_U32:
- case ARM64_INTRIN_VMOVL_U8:
- case ARM64_INTRIN_VMOVQ_N_S64:
- case ARM64_INTRIN_VMOVQ_N_U64:
- case ARM64_INTRIN_VMVN_P8:
- case ARM64_INTRIN_VMVN_S16:
- case ARM64_INTRIN_VMVN_S32:
- case ARM64_INTRIN_VMVN_S8:
- case ARM64_INTRIN_VMVN_U16:
- case ARM64_INTRIN_VMVN_U32:
- case ARM64_INTRIN_VMVN_U8:
- case ARM64_INTRIN_VNEG_S16:
- case ARM64_INTRIN_VNEG_S32:
- case ARM64_INTRIN_VNEG_S64:
- case ARM64_INTRIN_VNEG_S8:
- case ARM64_INTRIN_VNEGD_S64:
- case ARM64_INTRIN_VPADDL_S16:
- case ARM64_INTRIN_VPADDL_S32:
- case ARM64_INTRIN_VPADDL_S8:
- case ARM64_INTRIN_VPADDL_U16:
- case ARM64_INTRIN_VPADDL_U32:
- case ARM64_INTRIN_VPADDL_U8:
- case ARM64_INTRIN_VQABS_S16:
- case ARM64_INTRIN_VQABS_S32:
- case ARM64_INTRIN_VQABS_S64:
- case ARM64_INTRIN_VQABS_S8:
- case ARM64_INTRIN_VQABSD_S64:
- case ARM64_INTRIN_VQMOVND_S64:
- case ARM64_INTRIN_VQMOVND_U64:
- case ARM64_INTRIN_VQMOVUND_S64:
- case ARM64_INTRIN_VQNEG_S16:
- case ARM64_INTRIN_VQNEG_S32:
- case ARM64_INTRIN_VQNEG_S64:
- case ARM64_INTRIN_VQNEG_S8:
- case ARM64_INTRIN_VQNEGD_S64:
- case ARM64_INTRIN_VRBIT_P8:
- case ARM64_INTRIN_VRBIT_S8:
- case ARM64_INTRIN_VRBIT_U8:
- case ARM64_INTRIN_VRECPE_U32:
- case ARM64_INTRIN_VREV16_P8:
- case ARM64_INTRIN_VREV16_S8:
- case ARM64_INTRIN_VREV16_U8:
- case ARM64_INTRIN_VREV32_P16:
- case ARM64_INTRIN_VREV32_P8:
- case ARM64_INTRIN_VREV32_S16:
- case ARM64_INTRIN_VREV32_S8:
- case ARM64_INTRIN_VREV32_U16:
- case ARM64_INTRIN_VREV32_U8:
- case ARM64_INTRIN_VREV64_P16:
- case ARM64_INTRIN_VREV64_P8:
- case ARM64_INTRIN_VREV64_S16:
- case ARM64_INTRIN_VREV64_S32:
- case ARM64_INTRIN_VREV64_S8:
- case ARM64_INTRIN_VREV64_U16:
- case ARM64_INTRIN_VREV64_U32:
- case ARM64_INTRIN_VREV64_U8:
- case ARM64_INTRIN_VRSQRTE_U32:
- return {NameAndType(Type::IntegerType(8, false))};
- case ARM64_INTRIN_VBSL_F16:
- case ARM64_INTRIN_VBSL_F32:
- case ARM64_INTRIN_VBSL_F64:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::FloatType(8)),
- NameAndType(Type::FloatType(8))};
- case ARM64_INTRIN_VMOVN_HIGH_S16:
- case ARM64_INTRIN_VMOVN_HIGH_S32:
- case ARM64_INTRIN_VMOVN_HIGH_S64:
- case ARM64_INTRIN_VMOVN_HIGH_U16:
- case ARM64_INTRIN_VMOVN_HIGH_U32:
- case ARM64_INTRIN_VMOVN_HIGH_U64:
- case ARM64_INTRIN_VQMOVN_HIGH_S16:
- case ARM64_INTRIN_VQMOVN_HIGH_S32:
- case ARM64_INTRIN_VQMOVN_HIGH_S64:
- case ARM64_INTRIN_VQMOVN_HIGH_U16:
- case ARM64_INTRIN_VQMOVN_HIGH_U32:
- case ARM64_INTRIN_VQMOVN_HIGH_U64:
- case ARM64_INTRIN_VQMOVUN_HIGH_S16:
- case ARM64_INTRIN_VQMOVUN_HIGH_S32:
- case ARM64_INTRIN_VQMOVUN_HIGH_S64:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(16, false))};
- case ARM64_INTRIN_VADDHN_HIGH_S16:
- case ARM64_INTRIN_VADDHN_HIGH_S32:
- case ARM64_INTRIN_VADDHN_HIGH_S64:
- case ARM64_INTRIN_VADDHN_HIGH_U16:
- case ARM64_INTRIN_VADDHN_HIGH_U32:
- case ARM64_INTRIN_VADDHN_HIGH_U64:
- case ARM64_INTRIN_VRADDHN_HIGH_S16:
- case ARM64_INTRIN_VRADDHN_HIGH_S32:
- case ARM64_INTRIN_VRADDHN_HIGH_S64:
- case ARM64_INTRIN_VRADDHN_HIGH_U16:
- case ARM64_INTRIN_VRADDHN_HIGH_U32:
- case ARM64_INTRIN_VRADDHN_HIGH_U64:
- case ARM64_INTRIN_VRSUBHN_HIGH_S16:
- case ARM64_INTRIN_VRSUBHN_HIGH_S32:
- case ARM64_INTRIN_VRSUBHN_HIGH_S64:
- case ARM64_INTRIN_VRSUBHN_HIGH_U16:
- case ARM64_INTRIN_VRSUBHN_HIGH_U32:
- case ARM64_INTRIN_VRSUBHN_HIGH_U64:
- case ARM64_INTRIN_VSUBHN_HIGH_S16:
- case ARM64_INTRIN_VSUBHN_HIGH_S32:
- case ARM64_INTRIN_VSUBHN_HIGH_S64:
- case ARM64_INTRIN_VSUBHN_HIGH_U16:
- case ARM64_INTRIN_VSUBHN_HIGH_U32:
- case ARM64_INTRIN_VSUBHN_HIGH_U64:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(16, false)),
- NameAndType(Type::IntegerType(16, false))};
- case ARM64_INTRIN_VMUL_LANEQ_S16:
- case ARM64_INTRIN_VMUL_LANEQ_S32:
- case ARM64_INTRIN_VMUL_LANEQ_U16:
- case ARM64_INTRIN_VMUL_LANEQ_U32:
- case ARM64_INTRIN_VMULL_LANEQ_S16:
- case ARM64_INTRIN_VMULL_LANEQ_S32:
- case ARM64_INTRIN_VMULL_LANEQ_U16:
- case ARM64_INTRIN_VMULL_LANEQ_U32:
- case ARM64_INTRIN_VQDMULH_LANEQ_S16:
- case ARM64_INTRIN_VQDMULH_LANEQ_S32:
- case ARM64_INTRIN_VQDMULL_LANEQ_S16:
- case ARM64_INTRIN_VQDMULL_LANEQ_S32:
- case ARM64_INTRIN_VQRDMULH_LANEQ_S16:
- case ARM64_INTRIN_VQRDMULH_LANEQ_S32:
- case ARM64_INTRIN_VQRSHRN_HIGH_N_S16:
- case ARM64_INTRIN_VQRSHRN_HIGH_N_S32:
- case ARM64_INTRIN_VQRSHRN_HIGH_N_S64:
- case ARM64_INTRIN_VQRSHRN_HIGH_N_U16:
- case ARM64_INTRIN_VQRSHRN_HIGH_N_U32:
- case ARM64_INTRIN_VQRSHRN_HIGH_N_U64:
- case ARM64_INTRIN_VQRSHRUN_HIGH_N_S16:
- case ARM64_INTRIN_VQRSHRUN_HIGH_N_S32:
- case ARM64_INTRIN_VQRSHRUN_HIGH_N_S64:
- case ARM64_INTRIN_VQSHRN_HIGH_N_S16:
- case ARM64_INTRIN_VQSHRN_HIGH_N_S32:
- case ARM64_INTRIN_VQSHRN_HIGH_N_S64:
- case ARM64_INTRIN_VQSHRN_HIGH_N_U16:
- case ARM64_INTRIN_VQSHRN_HIGH_N_U32:
- case ARM64_INTRIN_VQSHRN_HIGH_N_U64:
- case ARM64_INTRIN_VQSHRUN_HIGH_N_S16:
- case ARM64_INTRIN_VQSHRUN_HIGH_N_S32:
- case ARM64_INTRIN_VQSHRUN_HIGH_N_S64:
- case ARM64_INTRIN_VRSHRN_HIGH_N_S16:
- case ARM64_INTRIN_VRSHRN_HIGH_N_S32:
- case ARM64_INTRIN_VRSHRN_HIGH_N_S64:
- case ARM64_INTRIN_VRSHRN_HIGH_N_U16:
- case ARM64_INTRIN_VRSHRN_HIGH_N_U32:
- case ARM64_INTRIN_VRSHRN_HIGH_N_U64:
- case ARM64_INTRIN_VSETQ_LANE_P64:
- case ARM64_INTRIN_VSETQ_LANE_S64:
- case ARM64_INTRIN_VSETQ_LANE_U64:
- case ARM64_INTRIN_VSHRN_HIGH_N_S16:
- case ARM64_INTRIN_VSHRN_HIGH_N_S32:
- case ARM64_INTRIN_VSHRN_HIGH_N_S64:
- case ARM64_INTRIN_VSHRN_HIGH_N_U16:
- case ARM64_INTRIN_VSHRN_HIGH_N_U32:
- case ARM64_INTRIN_VSHRN_HIGH_N_U64:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(16, false)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VMUL_N_S16:
- case ARM64_INTRIN_VMUL_N_U16:
- case ARM64_INTRIN_VMULL_N_S16:
- case ARM64_INTRIN_VMULL_N_U16:
- case ARM64_INTRIN_VQDMULH_N_S16:
- case ARM64_INTRIN_VQDMULL_N_S16:
- case ARM64_INTRIN_VQRDMULH_N_S16:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(2, false))};
- case ARM64_INTRIN_VCVT_N_F16_S16:
- case ARM64_INTRIN_VCVT_N_F16_U16:
- case ARM64_INTRIN_VCVT_N_F32_S32:
- case ARM64_INTRIN_VCVT_N_F32_U32:
- case ARM64_INTRIN_VCVT_N_F64_S64:
- case ARM64_INTRIN_VCVT_N_F64_U64:
- case ARM64_INTRIN_VCVTD_N_F64_S64:
- case ARM64_INTRIN_VCVTH_N_F16_S64:
- case ARM64_INTRIN_VDUP_LANE_P16:
- case ARM64_INTRIN_VDUP_LANE_P64:
- case ARM64_INTRIN_VDUP_LANE_P8:
- case ARM64_INTRIN_VDUP_LANE_S16:
- case ARM64_INTRIN_VDUP_LANE_S32:
- case ARM64_INTRIN_VDUP_LANE_S64:
- case ARM64_INTRIN_VDUP_LANE_S8:
- case ARM64_INTRIN_VDUP_LANE_U16:
- case ARM64_INTRIN_VDUP_LANE_U32:
- case ARM64_INTRIN_VDUP_LANE_U64:
- case ARM64_INTRIN_VDUP_LANE_U8:
- case ARM64_INTRIN_VDUPB_LANE_P8:
- case ARM64_INTRIN_VDUPB_LANE_S8:
- case ARM64_INTRIN_VDUPB_LANE_U8:
- case ARM64_INTRIN_VDUPD_LANE_S64:
- case ARM64_INTRIN_VDUPD_LANE_U64:
- case ARM64_INTRIN_VDUPH_LANE_P16:
- case ARM64_INTRIN_VDUPH_LANE_S16:
- case ARM64_INTRIN_VDUPH_LANE_U16:
- case ARM64_INTRIN_VDUPQ_LANE_P16:
- case ARM64_INTRIN_VDUPQ_LANE_P64:
- case ARM64_INTRIN_VDUPQ_LANE_P8:
- case ARM64_INTRIN_VDUPQ_LANE_S16:
- case ARM64_INTRIN_VDUPQ_LANE_S32:
- case ARM64_INTRIN_VDUPQ_LANE_S64:
- case ARM64_INTRIN_VDUPQ_LANE_S8:
- case ARM64_INTRIN_VDUPQ_LANE_U16:
- case ARM64_INTRIN_VDUPQ_LANE_U32:
- case ARM64_INTRIN_VDUPQ_LANE_U64:
- case ARM64_INTRIN_VDUPQ_LANE_U8:
- case ARM64_INTRIN_VDUPS_LANE_S32:
- case ARM64_INTRIN_VDUPS_LANE_U32:
- case ARM64_INTRIN_VGET_LANE_P16:
- case ARM64_INTRIN_VGET_LANE_P64:
- case ARM64_INTRIN_VGET_LANE_P8:
- case ARM64_INTRIN_VGET_LANE_S16:
- case ARM64_INTRIN_VGET_LANE_S32:
- case ARM64_INTRIN_VGET_LANE_S64:
- case ARM64_INTRIN_VGET_LANE_S8:
- case ARM64_INTRIN_VGET_LANE_U16:
- case ARM64_INTRIN_VGET_LANE_U32:
- case ARM64_INTRIN_VGET_LANE_U64:
- case ARM64_INTRIN_VGET_LANE_U8:
- case ARM64_INTRIN_VMUL_N_S32:
- case ARM64_INTRIN_VMUL_N_U32:
- case ARM64_INTRIN_VMULL_N_S32:
- case ARM64_INTRIN_VMULL_N_U32:
- case ARM64_INTRIN_VQDMULH_N_S32:
- case ARM64_INTRIN_VQDMULL_N_S32:
- case ARM64_INTRIN_VQRDMULH_N_S32:
- case ARM64_INTRIN_VQRSHRND_N_S64:
- case ARM64_INTRIN_VQRSHRND_N_U64:
- case ARM64_INTRIN_VQRSHRUND_N_S64:
- case ARM64_INTRIN_VQSHL_N_S16:
- case ARM64_INTRIN_VQSHL_N_S32:
- case ARM64_INTRIN_VQSHL_N_S64:
- case ARM64_INTRIN_VQSHL_N_S8:
- case ARM64_INTRIN_VQSHL_N_U16:
- case ARM64_INTRIN_VQSHL_N_U32:
- case ARM64_INTRIN_VQSHL_N_U64:
- case ARM64_INTRIN_VQSHL_N_U8:
- case ARM64_INTRIN_VQSHLD_N_S64:
- case ARM64_INTRIN_VQSHLD_N_U64:
- case ARM64_INTRIN_VQSHLU_N_S16:
- case ARM64_INTRIN_VQSHLU_N_S32:
- case ARM64_INTRIN_VQSHLU_N_S64:
- case ARM64_INTRIN_VQSHLU_N_S8:
- case ARM64_INTRIN_VQSHLUD_N_S64:
- case ARM64_INTRIN_VQSHRND_N_S64:
- case ARM64_INTRIN_VQSHRND_N_U64:
- case ARM64_INTRIN_VQSHRUND_N_S64:
- case ARM64_INTRIN_VRSHR_N_S16:
- case ARM64_INTRIN_VRSHR_N_S32:
- case ARM64_INTRIN_VRSHR_N_S64:
- case ARM64_INTRIN_VRSHR_N_S8:
- case ARM64_INTRIN_VRSHR_N_U16:
- case ARM64_INTRIN_VRSHR_N_U32:
- case ARM64_INTRIN_VRSHR_N_U64:
- case ARM64_INTRIN_VRSHR_N_U8:
- case ARM64_INTRIN_VRSHRD_N_S64:
- case ARM64_INTRIN_VRSHRD_N_U64:
- case ARM64_INTRIN_VSHL_N_S16:
- case ARM64_INTRIN_VSHL_N_S32:
- case ARM64_INTRIN_VSHL_N_S64:
- case ARM64_INTRIN_VSHL_N_S8:
- case ARM64_INTRIN_VSHL_N_U16:
- case ARM64_INTRIN_VSHL_N_U32:
- case ARM64_INTRIN_VSHL_N_U64:
- case ARM64_INTRIN_VSHL_N_U8:
- case ARM64_INTRIN_VSHLD_N_S64:
- case ARM64_INTRIN_VSHLD_N_U64:
- case ARM64_INTRIN_VSHLL_N_S16:
- case ARM64_INTRIN_VSHLL_N_S32:
- case ARM64_INTRIN_VSHLL_N_S8:
- case ARM64_INTRIN_VSHLL_N_U16:
- case ARM64_INTRIN_VSHLL_N_U32:
- case ARM64_INTRIN_VSHLL_N_U8:
- case ARM64_INTRIN_VSHR_N_S16:
- case ARM64_INTRIN_VSHR_N_S32:
- case ARM64_INTRIN_VSHR_N_S64:
- case ARM64_INTRIN_VSHR_N_S8:
- case ARM64_INTRIN_VSHR_N_U16:
- case ARM64_INTRIN_VSHR_N_U32:
- case ARM64_INTRIN_VSHR_N_U64:
- case ARM64_INTRIN_VSHR_N_U8:
- case ARM64_INTRIN_VSHRD_N_S64:
- case ARM64_INTRIN_VSHRD_N_U64:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VQDMLALS_LANEQ_S32:
- case ARM64_INTRIN_VQDMLSLS_LANEQ_S32:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false)),
- NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VQDMLALS_S32:
- case ARM64_INTRIN_VQDMLSLS_S32:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VQDMLALS_LANE_S32:
- case ARM64_INTRIN_VQDMLSLS_LANE_S32:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false)),
- NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VABD_S16:
- case ARM64_INTRIN_VABD_S32:
- case ARM64_INTRIN_VABD_S8:
- case ARM64_INTRIN_VABD_U16:
- case ARM64_INTRIN_VABD_U32:
- case ARM64_INTRIN_VABD_U8:
- case ARM64_INTRIN_VABDL_S16:
- case ARM64_INTRIN_VABDL_S32:
- case ARM64_INTRIN_VABDL_S8:
- case ARM64_INTRIN_VABDL_U16:
- case ARM64_INTRIN_VABDL_U32:
- case ARM64_INTRIN_VABDL_U8:
- case ARM64_INTRIN_VADD_P16:
- case ARM64_INTRIN_VADD_P64:
- case ARM64_INTRIN_VADD_P8:
- case ARM64_INTRIN_VADD_S16:
- case ARM64_INTRIN_VADD_S32:
- case ARM64_INTRIN_VADD_S64:
- case ARM64_INTRIN_VADD_S8:
- case ARM64_INTRIN_VADD_U16:
- case ARM64_INTRIN_VADD_U32:
- case ARM64_INTRIN_VADD_U64:
- case ARM64_INTRIN_VADD_U8:
- case ARM64_INTRIN_VADDD_S64:
- case ARM64_INTRIN_VADDD_U64:
- case ARM64_INTRIN_VADDL_S16:
- case ARM64_INTRIN_VADDL_S32:
- case ARM64_INTRIN_VADDL_S8:
- case ARM64_INTRIN_VADDL_U16:
- case ARM64_INTRIN_VADDL_U32:
- case ARM64_INTRIN_VADDL_U8:
- case ARM64_INTRIN_VAND_S16:
- case ARM64_INTRIN_VAND_S32:
- case ARM64_INTRIN_VAND_S64:
- case ARM64_INTRIN_VAND_S8:
- case ARM64_INTRIN_VAND_U16:
- case ARM64_INTRIN_VAND_U32:
- case ARM64_INTRIN_VAND_U64:
- case ARM64_INTRIN_VAND_U8:
- case ARM64_INTRIN_VBIC_S16:
- case ARM64_INTRIN_VBIC_S32:
- case ARM64_INTRIN_VBIC_S64:
- case ARM64_INTRIN_VBIC_S8:
- case ARM64_INTRIN_VBIC_U16:
- case ARM64_INTRIN_VBIC_U32:
- case ARM64_INTRIN_VBIC_U64:
- case ARM64_INTRIN_VBIC_U8:
- case ARM64_INTRIN_VCEQ_P64:
- case ARM64_INTRIN_VCEQ_P8:
- case ARM64_INTRIN_VCEQ_S16:
- case ARM64_INTRIN_VCEQ_S32:
- case ARM64_INTRIN_VCEQ_S64:
- case ARM64_INTRIN_VCEQ_S8:
- case ARM64_INTRIN_VCEQ_U16:
- case ARM64_INTRIN_VCEQ_U32:
- case ARM64_INTRIN_VCEQ_U64:
- case ARM64_INTRIN_VCEQ_U8:
- case ARM64_INTRIN_VCEQD_S64:
- case ARM64_INTRIN_VCEQD_U64:
- case ARM64_INTRIN_VCGE_S16:
- case ARM64_INTRIN_VCGE_S32:
- case ARM64_INTRIN_VCGE_S64:
- case ARM64_INTRIN_VCGE_S8:
- case ARM64_INTRIN_VCGE_U16:
- case ARM64_INTRIN_VCGE_U32:
- case ARM64_INTRIN_VCGE_U64:
- case ARM64_INTRIN_VCGE_U8:
- case ARM64_INTRIN_VCGED_S64:
- case ARM64_INTRIN_VCGED_U64:
- case ARM64_INTRIN_VCGT_S16:
- case ARM64_INTRIN_VCGT_S32:
- case ARM64_INTRIN_VCGT_S64:
- case ARM64_INTRIN_VCGT_S8:
- case ARM64_INTRIN_VCGT_U16:
- case ARM64_INTRIN_VCGT_U32:
- case ARM64_INTRIN_VCGT_U64:
- case ARM64_INTRIN_VCGT_U8:
- case ARM64_INTRIN_VCGTD_S64:
- case ARM64_INTRIN_VCGTD_U64:
- case ARM64_INTRIN_VCLE_S16:
- case ARM64_INTRIN_VCLE_S32:
- case ARM64_INTRIN_VCLE_S64:
- case ARM64_INTRIN_VCLE_S8:
- case ARM64_INTRIN_VCLE_U16:
- case ARM64_INTRIN_VCLE_U32:
- case ARM64_INTRIN_VCLE_U64:
- case ARM64_INTRIN_VCLE_U8:
- case ARM64_INTRIN_VCLED_S64:
- case ARM64_INTRIN_VCLED_U64:
- case ARM64_INTRIN_VCLT_S16:
- case ARM64_INTRIN_VCLT_S32:
- case ARM64_INTRIN_VCLT_S64:
- case ARM64_INTRIN_VCLT_S8:
- case ARM64_INTRIN_VCLT_U16:
- case ARM64_INTRIN_VCLT_U32:
- case ARM64_INTRIN_VCLT_U64:
- case ARM64_INTRIN_VCLT_U8:
- case ARM64_INTRIN_VCLTD_S64:
- case ARM64_INTRIN_VCLTD_U64:
- case ARM64_INTRIN_VEOR_S16:
- case ARM64_INTRIN_VEOR_S32:
- case ARM64_INTRIN_VEOR_S64:
- case ARM64_INTRIN_VEOR_S8:
- case ARM64_INTRIN_VEOR_U16:
- case ARM64_INTRIN_VEOR_U32:
- case ARM64_INTRIN_VEOR_U64:
- case ARM64_INTRIN_VEOR_U8:
- case ARM64_INTRIN_VHADD_S16:
- case ARM64_INTRIN_VHADD_S32:
- case ARM64_INTRIN_VHADD_S8:
- case ARM64_INTRIN_VHADD_U16:
- case ARM64_INTRIN_VHADD_U32:
- case ARM64_INTRIN_VHADD_U8:
- case ARM64_INTRIN_VHSUB_S16:
- case ARM64_INTRIN_VHSUB_S32:
- case ARM64_INTRIN_VHSUB_S8:
- case ARM64_INTRIN_VHSUB_U16:
- case ARM64_INTRIN_VHSUB_U32:
- case ARM64_INTRIN_VHSUB_U8:
- case ARM64_INTRIN_VMAX_S16:
- case ARM64_INTRIN_VMAX_S32:
- case ARM64_INTRIN_VMAX_S8:
- case ARM64_INTRIN_VMAX_U16:
- case ARM64_INTRIN_VMAX_U32:
- case ARM64_INTRIN_VMAX_U8:
- case ARM64_INTRIN_VMIN_S16:
- case ARM64_INTRIN_VMIN_S32:
- case ARM64_INTRIN_VMIN_S8:
- case ARM64_INTRIN_VMIN_U16:
- case ARM64_INTRIN_VMIN_U32:
- case ARM64_INTRIN_VMIN_U8:
- case ARM64_INTRIN_VMUL_P8:
- case ARM64_INTRIN_VMUL_S16:
- case ARM64_INTRIN_VMUL_S32:
- case ARM64_INTRIN_VMUL_S8:
- case ARM64_INTRIN_VMUL_U16:
- case ARM64_INTRIN_VMUL_U32:
- case ARM64_INTRIN_VMUL_U8:
- case ARM64_INTRIN_VMULL_P64:
- case ARM64_INTRIN_VMULL_P8:
- case ARM64_INTRIN_VMULL_S16:
- case ARM64_INTRIN_VMULL_S32:
- case ARM64_INTRIN_VMULL_S8:
- case ARM64_INTRIN_VMULL_U16:
- case ARM64_INTRIN_VMULL_U32:
- case ARM64_INTRIN_VMULL_U8:
- case ARM64_INTRIN_VORN_S16:
- case ARM64_INTRIN_VORN_S32:
- case ARM64_INTRIN_VORN_S64:
- case ARM64_INTRIN_VORN_S8:
- case ARM64_INTRIN_VORN_U16:
- case ARM64_INTRIN_VORN_U32:
- case ARM64_INTRIN_VORN_U64:
- case ARM64_INTRIN_VORN_U8:
- case ARM64_INTRIN_VORR_S16:
- case ARM64_INTRIN_VORR_S32:
- case ARM64_INTRIN_VORR_S64:
- case ARM64_INTRIN_VORR_S8:
- case ARM64_INTRIN_VORR_U16:
- case ARM64_INTRIN_VORR_U32:
- case ARM64_INTRIN_VORR_U64:
- case ARM64_INTRIN_VORR_U8:
- case ARM64_INTRIN_VPADAL_S16:
- case ARM64_INTRIN_VPADAL_S32:
- case ARM64_INTRIN_VPADAL_S8:
- case ARM64_INTRIN_VPADAL_U16:
- case ARM64_INTRIN_VPADAL_U32:
- case ARM64_INTRIN_VPADAL_U8:
- case ARM64_INTRIN_VPADD_S16:
- case ARM64_INTRIN_VPADD_S32:
- case ARM64_INTRIN_VPADD_S8:
- case ARM64_INTRIN_VPADD_U16:
- case ARM64_INTRIN_VPADD_U32:
- case ARM64_INTRIN_VPADD_U8:
- case ARM64_INTRIN_VPMAX_S16:
- case ARM64_INTRIN_VPMAX_S32:
- case ARM64_INTRIN_VPMAX_S8:
- case ARM64_INTRIN_VPMAX_U16:
- case ARM64_INTRIN_VPMAX_U32:
- case ARM64_INTRIN_VPMAX_U8:
- case ARM64_INTRIN_VPMIN_S16:
- case ARM64_INTRIN_VPMIN_S32:
- case ARM64_INTRIN_VPMIN_S8:
- case ARM64_INTRIN_VPMIN_U16:
- case ARM64_INTRIN_VPMIN_U32:
- case ARM64_INTRIN_VPMIN_U8:
- case ARM64_INTRIN_VQADD_S16:
- case ARM64_INTRIN_VQADD_S32:
- case ARM64_INTRIN_VQADD_S64:
- case ARM64_INTRIN_VQADD_S8:
- case ARM64_INTRIN_VQADD_U16:
- case ARM64_INTRIN_VQADD_U32:
- case ARM64_INTRIN_VQADD_U64:
- case ARM64_INTRIN_VQADD_U8:
- case ARM64_INTRIN_VQADDD_S64:
- case ARM64_INTRIN_VQADDD_U64:
- case ARM64_INTRIN_VQDMULH_S16:
- case ARM64_INTRIN_VQDMULH_S32:
- case ARM64_INTRIN_VQDMULL_S16:
- case ARM64_INTRIN_VQDMULL_S32:
- case ARM64_INTRIN_VQRDMULH_S16:
- case ARM64_INTRIN_VQRDMULH_S32:
- case ARM64_INTRIN_VQRSHL_S16:
- case ARM64_INTRIN_VQRSHL_S32:
- case ARM64_INTRIN_VQRSHL_S64:
- case ARM64_INTRIN_VQRSHL_S8:
- case ARM64_INTRIN_VQRSHL_U16:
- case ARM64_INTRIN_VQRSHL_U32:
- case ARM64_INTRIN_VQRSHL_U64:
- case ARM64_INTRIN_VQRSHL_U8:
- case ARM64_INTRIN_VQRSHLD_S64:
- case ARM64_INTRIN_VQRSHLD_U64:
- case ARM64_INTRIN_VQSHL_S16:
- case ARM64_INTRIN_VQSHL_S32:
- case ARM64_INTRIN_VQSHL_S64:
- case ARM64_INTRIN_VQSHL_S8:
- case ARM64_INTRIN_VQSHL_U16:
- case ARM64_INTRIN_VQSHL_U32:
- case ARM64_INTRIN_VQSHL_U64:
- case ARM64_INTRIN_VQSHL_U8:
- case ARM64_INTRIN_VQSHLD_S64:
- case ARM64_INTRIN_VQSHLD_U64:
- case ARM64_INTRIN_VQSUB_S16:
- case ARM64_INTRIN_VQSUB_S32:
- case ARM64_INTRIN_VQSUB_S64:
- case ARM64_INTRIN_VQSUB_S8:
- case ARM64_INTRIN_VQSUB_U16:
- case ARM64_INTRIN_VQSUB_U32:
- case ARM64_INTRIN_VQSUB_U64:
- case ARM64_INTRIN_VQSUB_U8:
- case ARM64_INTRIN_VQSUBD_S64:
- case ARM64_INTRIN_VQSUBD_U64:
- case ARM64_INTRIN_VRHADD_S16:
- case ARM64_INTRIN_VRHADD_S32:
- case ARM64_INTRIN_VRHADD_S8:
- case ARM64_INTRIN_VRHADD_U16:
- case ARM64_INTRIN_VRHADD_U32:
- case ARM64_INTRIN_VRHADD_U8:
- case ARM64_INTRIN_VRSHL_S16:
- case ARM64_INTRIN_VRSHL_S32:
- case ARM64_INTRIN_VRSHL_S64:
- case ARM64_INTRIN_VRSHL_S8:
- case ARM64_INTRIN_VRSHL_U16:
- case ARM64_INTRIN_VRSHL_U32:
- case ARM64_INTRIN_VRSHL_U64:
- case ARM64_INTRIN_VRSHL_U8:
- case ARM64_INTRIN_VRSHLD_S64:
- case ARM64_INTRIN_VRSHLD_U64:
- case ARM64_INTRIN_VSHL_S16:
- case ARM64_INTRIN_VSHL_S32:
- case ARM64_INTRIN_VSHL_S64:
- case ARM64_INTRIN_VSHL_S8:
- case ARM64_INTRIN_VSHL_U16:
- case ARM64_INTRIN_VSHL_U32:
- case ARM64_INTRIN_VSHL_U64:
- case ARM64_INTRIN_VSHL_U8:
- case ARM64_INTRIN_VSHLD_S64:
- case ARM64_INTRIN_VSHLD_U64:
- case ARM64_INTRIN_VSQADD_U16:
- case ARM64_INTRIN_VSQADD_U32:
- case ARM64_INTRIN_VSQADD_U64:
- case ARM64_INTRIN_VSQADD_U8:
- case ARM64_INTRIN_VSQADDD_U64:
- case ARM64_INTRIN_VSUB_S16:
- case ARM64_INTRIN_VSUB_S32:
- case ARM64_INTRIN_VSUB_S64:
- case ARM64_INTRIN_VSUB_S8:
- case ARM64_INTRIN_VSUB_U16:
- case ARM64_INTRIN_VSUB_U32:
- case ARM64_INTRIN_VSUB_U64:
- case ARM64_INTRIN_VSUB_U8:
- case ARM64_INTRIN_VSUBD_S64:
- case ARM64_INTRIN_VSUBD_U64:
- case ARM64_INTRIN_VSUBL_S16:
- case ARM64_INTRIN_VSUBL_S32:
- case ARM64_INTRIN_VSUBL_S8:
- case ARM64_INTRIN_VSUBL_U16:
- case ARM64_INTRIN_VSUBL_U32:
- case ARM64_INTRIN_VSUBL_U8:
- case ARM64_INTRIN_VTRN1_P16:
- case ARM64_INTRIN_VTRN1_P8:
- case ARM64_INTRIN_VTRN1_S16:
- case ARM64_INTRIN_VTRN1_S32:
- case ARM64_INTRIN_VTRN1_S8:
- case ARM64_INTRIN_VTRN1_U16:
- case ARM64_INTRIN_VTRN1_U32:
- case ARM64_INTRIN_VTRN1_U8:
- case ARM64_INTRIN_VTRN2_P16:
- case ARM64_INTRIN_VTRN2_P8:
- case ARM64_INTRIN_VTRN2_S16:
- case ARM64_INTRIN_VTRN2_S32:
- case ARM64_INTRIN_VTRN2_S8:
- case ARM64_INTRIN_VTRN2_U16:
- case ARM64_INTRIN_VTRN2_U32:
- case ARM64_INTRIN_VTRN2_U8:
- case ARM64_INTRIN_VTST_P64:
- case ARM64_INTRIN_VTST_P8:
- case ARM64_INTRIN_VTST_S16:
- case ARM64_INTRIN_VTST_S32:
- case ARM64_INTRIN_VTST_S64:
- case ARM64_INTRIN_VTST_S8:
- case ARM64_INTRIN_VTST_U16:
- case ARM64_INTRIN_VTST_U32:
- case ARM64_INTRIN_VTST_U64:
- case ARM64_INTRIN_VTST_U8:
- case ARM64_INTRIN_VTSTD_S64:
- case ARM64_INTRIN_VTSTD_U64:
- case ARM64_INTRIN_VUQADD_S16:
- case ARM64_INTRIN_VUQADD_S32:
- case ARM64_INTRIN_VUQADD_S64:
- case ARM64_INTRIN_VUQADD_S8:
- case ARM64_INTRIN_VUQADDD_S64:
- case ARM64_INTRIN_VUZP1_P16:
- case ARM64_INTRIN_VUZP1_P8:
- case ARM64_INTRIN_VUZP1_S16:
- case ARM64_INTRIN_VUZP1_S32:
- case ARM64_INTRIN_VUZP1_S8:
- case ARM64_INTRIN_VUZP1_U16:
- case ARM64_INTRIN_VUZP1_U32:
- case ARM64_INTRIN_VUZP1_U8:
- case ARM64_INTRIN_VUZP2_P16:
- case ARM64_INTRIN_VUZP2_P8:
- case ARM64_INTRIN_VUZP2_S16:
- case ARM64_INTRIN_VUZP2_S32:
- case ARM64_INTRIN_VUZP2_S8:
- case ARM64_INTRIN_VUZP2_U16:
- case ARM64_INTRIN_VUZP2_U32:
- case ARM64_INTRIN_VUZP2_U8:
- case ARM64_INTRIN_VZIP1_P16:
- case ARM64_INTRIN_VZIP1_P8:
- case ARM64_INTRIN_VZIP1_S16:
- case ARM64_INTRIN_VZIP1_S32:
- case ARM64_INTRIN_VZIP1_S8:
- case ARM64_INTRIN_VZIP1_U16:
- case ARM64_INTRIN_VZIP1_U32:
- case ARM64_INTRIN_VZIP1_U8:
- case ARM64_INTRIN_VZIP2_P16:
- case ARM64_INTRIN_VZIP2_P8:
- case ARM64_INTRIN_VZIP2_S16:
- case ARM64_INTRIN_VZIP2_S32:
- case ARM64_INTRIN_VZIP2_S8:
- case ARM64_INTRIN_VZIP2_U16:
- case ARM64_INTRIN_VZIP2_U32:
- case ARM64_INTRIN_VZIP2_U8:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false))};
- case ARM64_INTRIN_VDOT_LANEQ_S32:
- case ARM64_INTRIN_VDOT_LANEQ_U32:
- case ARM64_INTRIN_VMLA_LANEQ_S16:
- case ARM64_INTRIN_VMLA_LANEQ_S32:
- case ARM64_INTRIN_VMLA_LANEQ_U16:
- case ARM64_INTRIN_VMLA_LANEQ_U32:
- case ARM64_INTRIN_VMLS_LANEQ_S16:
- case ARM64_INTRIN_VMLS_LANEQ_S32:
- case ARM64_INTRIN_VMLS_LANEQ_U16:
- case ARM64_INTRIN_VMLS_LANEQ_U32:
- case ARM64_INTRIN_VQRDMLAH_LANEQ_S16:
- case ARM64_INTRIN_VQRDMLAH_LANEQ_S32:
- case ARM64_INTRIN_VQRDMLSH_LANEQ_S16:
- case ARM64_INTRIN_VQRDMLSH_LANEQ_S32:
- case ARM64_INTRIN_VSUDOT_LANEQ_S32:
- case ARM64_INTRIN_VUSDOT_LANEQ_S32:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)),
- NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VMLA_N_S16:
- case ARM64_INTRIN_VMLA_N_U16:
- case ARM64_INTRIN_VMLS_N_S16:
- case ARM64_INTRIN_VMLS_N_U16:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)),
- NameAndType(Type::IntegerType(2, false))};
- case ARM64_INTRIN_VEXT_P16:
- case ARM64_INTRIN_VEXT_P64:
- case ARM64_INTRIN_VEXT_P8:
- case ARM64_INTRIN_VEXT_S16:
- case ARM64_INTRIN_VEXT_S32:
- case ARM64_INTRIN_VEXT_S64:
- case ARM64_INTRIN_VEXT_S8:
- case ARM64_INTRIN_VEXT_U16:
- case ARM64_INTRIN_VEXT_U32:
- case ARM64_INTRIN_VEXT_U64:
- case ARM64_INTRIN_VEXT_U8:
- case ARM64_INTRIN_VMLA_N_S32:
- case ARM64_INTRIN_VMLA_N_U32:
- case ARM64_INTRIN_VMLS_N_S32:
- case ARM64_INTRIN_VMLS_N_U32:
- case ARM64_INTRIN_VMUL_LANE_S16:
- case ARM64_INTRIN_VMUL_LANE_S32:
- case ARM64_INTRIN_VMUL_LANE_U16:
- case ARM64_INTRIN_VMUL_LANE_U32:
- case ARM64_INTRIN_VMULL_LANE_S16:
- case ARM64_INTRIN_VMULL_LANE_S32:
- case ARM64_INTRIN_VMULL_LANE_U16:
- case ARM64_INTRIN_VMULL_LANE_U32:
- case ARM64_INTRIN_VQDMULH_LANE_S16:
- case ARM64_INTRIN_VQDMULH_LANE_S32:
- case ARM64_INTRIN_VQDMULL_LANE_S16:
- case ARM64_INTRIN_VQDMULL_LANE_S32:
- case ARM64_INTRIN_VQRDMULH_LANE_S16:
- case ARM64_INTRIN_VQRDMULH_LANE_S32:
- case ARM64_INTRIN_VRSRA_N_S16:
- case ARM64_INTRIN_VRSRA_N_S32:
- case ARM64_INTRIN_VRSRA_N_S64:
- case ARM64_INTRIN_VRSRA_N_S8:
- case ARM64_INTRIN_VRSRA_N_U16:
- case ARM64_INTRIN_VRSRA_N_U32:
- case ARM64_INTRIN_VRSRA_N_U64:
- case ARM64_INTRIN_VRSRA_N_U8:
- case ARM64_INTRIN_VRSRAD_N_S64:
- case ARM64_INTRIN_VRSRAD_N_U64:
- case ARM64_INTRIN_VSET_LANE_P64:
- case ARM64_INTRIN_VSET_LANE_S64:
- case ARM64_INTRIN_VSET_LANE_U64:
- case ARM64_INTRIN_VSLI_N_P16:
- case ARM64_INTRIN_VSLI_N_P64:
- case ARM64_INTRIN_VSLI_N_P8:
- case ARM64_INTRIN_VSLI_N_S16:
- case ARM64_INTRIN_VSLI_N_S32:
- case ARM64_INTRIN_VSLI_N_S64:
- case ARM64_INTRIN_VSLI_N_S8:
- case ARM64_INTRIN_VSLI_N_U16:
- case ARM64_INTRIN_VSLI_N_U32:
- case ARM64_INTRIN_VSLI_N_U64:
- case ARM64_INTRIN_VSLI_N_U8:
- case ARM64_INTRIN_VSLID_N_S64:
- case ARM64_INTRIN_VSLID_N_U64:
- case ARM64_INTRIN_VSRA_N_S16:
- case ARM64_INTRIN_VSRA_N_S32:
- case ARM64_INTRIN_VSRA_N_S64:
- case ARM64_INTRIN_VSRA_N_S8:
- case ARM64_INTRIN_VSRA_N_U16:
- case ARM64_INTRIN_VSRA_N_U32:
- case ARM64_INTRIN_VSRA_N_U64:
- case ARM64_INTRIN_VSRA_N_U8:
- case ARM64_INTRIN_VSRAD_N_S64:
- case ARM64_INTRIN_VSRAD_N_U64:
- case ARM64_INTRIN_VSRI_N_P16:
- case ARM64_INTRIN_VSRI_N_P64:
- case ARM64_INTRIN_VSRI_N_P8:
- case ARM64_INTRIN_VSRI_N_S16:
- case ARM64_INTRIN_VSRI_N_S32:
- case ARM64_INTRIN_VSRI_N_S64:
- case ARM64_INTRIN_VSRI_N_S8:
- case ARM64_INTRIN_VSRI_N_U16:
- case ARM64_INTRIN_VSRI_N_U32:
- case ARM64_INTRIN_VSRI_N_U64:
- case ARM64_INTRIN_VSRI_N_U8:
- case ARM64_INTRIN_VSRID_N_S64:
- case ARM64_INTRIN_VSRID_N_U64:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)),
- NameAndType(Type::IntegerType(4, false))};
- case ARM64_INTRIN_VABA_S16:
- case ARM64_INTRIN_VABA_S32:
- case ARM64_INTRIN_VABA_S8:
- case ARM64_INTRIN_VABA_U16:
- case ARM64_INTRIN_VABA_U32:
- case ARM64_INTRIN_VABA_U8:
- case ARM64_INTRIN_VBSL_P16:
- case ARM64_INTRIN_VBSL_P64:
- case ARM64_INTRIN_VBSL_P8:
- case ARM64_INTRIN_VBSL_S16:
- case ARM64_INTRIN_VBSL_S32:
- case ARM64_INTRIN_VBSL_S64:
- case ARM64_INTRIN_VBSL_S8:
- case ARM64_INTRIN_VBSL_U16:
- case ARM64_INTRIN_VBSL_U32:
- case ARM64_INTRIN_VBSL_U64:
- case ARM64_INTRIN_VBSL_U8:
- case ARM64_INTRIN_VDOT_S32:
- case ARM64_INTRIN_VDOT_U32:
- case ARM64_INTRIN_VMLA_S16:
- case ARM64_INTRIN_VMLA_S32:
- case ARM64_INTRIN_VMLA_S8:
- case ARM64_INTRIN_VMLA_U16:
- case ARM64_INTRIN_VMLA_U32:
- case ARM64_INTRIN_VMLA_U8:
- case ARM64_INTRIN_VMLS_S16:
- case ARM64_INTRIN_VMLS_S32:
- case ARM64_INTRIN_VMLS_S8:
- case ARM64_INTRIN_VMLS_U16:
- case ARM64_INTRIN_VMLS_U32:
- case ARM64_INTRIN_VMLS_U8:
- case ARM64_INTRIN_VQRDMLAH_S16:
- case ARM64_INTRIN_VQRDMLAH_S32:
- case ARM64_INTRIN_VQRDMLSH_S16:
- case ARM64_INTRIN_VQRDMLSH_S32:
- case ARM64_INTRIN_VUSDOT_S32:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)),
- NameAndType(Type::IntegerType(8, false))};
- case ARM64_INTRIN_VDOT_LANE_S32:
- case ARM64_INTRIN_VDOT_LANE_U32:
- case ARM64_INTRIN_VMLA_LANE_S16:
- case ARM64_INTRIN_VMLA_LANE_S32:
- case ARM64_INTRIN_VMLA_LANE_U16:
- case ARM64_INTRIN_VMLA_LANE_U32:
- case ARM64_INTRIN_VMLS_LANE_S16:
- case ARM64_INTRIN_VMLS_LANE_S32:
- case ARM64_INTRIN_VMLS_LANE_U16:
- case ARM64_INTRIN_VMLS_LANE_U32:
- case ARM64_INTRIN_VQRDMLAH_LANE_S16:
- case ARM64_INTRIN_VQRDMLAH_LANE_S32:
- case ARM64_INTRIN_VQRDMLSH_LANE_S16:
- case ARM64_INTRIN_VQRDMLSH_LANE_S32:
- case ARM64_INTRIN_VSUDOT_LANE_S32:
- case ARM64_INTRIN_VUSDOT_LANE_S32:
- return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)),
- NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VABSQ_F16: // FABS Vd.8H,Vn.8H float16x8_t vabsq_f16(float16x8_t a)
+ case ARM64_INTRIN_VABSQ_F32: // FABS Vd.4S,Vn.4S float32x4_t vabsq_f32(float32x4_t a)
+ case ARM64_INTRIN_VABSQ_F64: // FABS Vd.2D,Vn.2D float64x2_t vabsq_f64(float64x2_t a)
+ case ARM64_INTRIN_VADDVQ_F32: // FADDP Vt.4S,Vn.4S,Vm.4S; FADDP Sd,Vt.2S float32_t vaddvq_f32(float32x4_t a)
+ case ARM64_INTRIN_VADDVQ_F64: // FADDP Dd,Vn.2D float64_t vaddvq_f64(float64x2_t a)
+ case ARM64_INTRIN_VCEQZQ_F16: // FCMEQ Vd.8H,Vn.8H,#0 uint16x8_t vceqzq_f16(float16x8_t a)
+ case ARM64_INTRIN_VCEQZQ_F32: // FCMEQ Vd.4S,Vn.4S,#0 uint32x4_t vceqzq_f32(float32x4_t a)
+ case ARM64_INTRIN_VCEQZQ_F64: // FCMEQ Vd.2D,Vn.2D,#0 uint64x2_t vceqzq_f64(float64x2_t a)
+ case ARM64_INTRIN_VCGEZQ_F16: // FCMGE Vd.8H,Vn.8H,#0 uint16x8_t vcgezq_f16(float16x8_t a)
+ case ARM64_INTRIN_VCGEZQ_F32: // FCMGE Vd.4S,Vn.4S,#0 uint32x4_t vcgezq_f32(float32x4_t a)
+ case ARM64_INTRIN_VCGEZQ_F64: // FCMGE Vd.2D,Vn.2D,#0 uint64x2_t vcgezq_f64(float64x2_t a)
+ case ARM64_INTRIN_VCGTZQ_F16: // FCMGT Vd.8H,Vn.8H,#0 uint16x8_t vcgtzq_f16(float16x8_t a)
+ case ARM64_INTRIN_VCGTZQ_F32: // FCMGT Vd.4S,Vn.4S,#0 uint32x4_t vcgtzq_f32(float32x4_t a)
+ case ARM64_INTRIN_VCGTZQ_F64: // FCMGT Vd.2D,Vn.2D,#0 uint64x2_t vcgtzq_f64(float64x2_t a)
+ case ARM64_INTRIN_VCLEZQ_F16: // FCMLE Vd.8H,Vn.8H,#0 uint16x8_t vclezq_f16(float16x8_t a)
+ case ARM64_INTRIN_VCLEZQ_F32: // FCMLE Vd.4S,Vn.4S,#0 uint32x4_t vclezq_f32(float32x4_t a)
+ case ARM64_INTRIN_VCLEZQ_F64: // FCMLE Vd.2D,Vn.2D,#0 uint64x2_t vclezq_f64(float64x2_t a)
+ case ARM64_INTRIN_VCLTZQ_F16: // FCMLT Vd.8H,Vn.8H,#0 uint16x8_t vcltzq_f16(float16x8_t a)
+ case ARM64_INTRIN_VCLTZQ_F32: // FCMLT Vd.4S,Vn.4S,#0 uint32x4_t vcltzq_f32(float32x4_t a)
+ case ARM64_INTRIN_VCLTZQ_F64: // FCMLT Vd.2D,Vn.2D,#0 uint64x2_t vcltzq_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVT_BF16_F32: // BFCVTN Vd.4H,Vn.4S bfloat16x4_t vcvt_bf16_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVT_F16_F32: // FCVTN Vd.4H,Vn.4S float16x4_t vcvt_f16_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVT_F32_F64: // FCVTN Vd.2S,Vn.2D float32x2_t vcvt_f32_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVT_HIGH_F32_F16: // FCVTL2 Vd.4S,Vn.8H float32x4_t vcvt_high_f32_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVT_HIGH_F64_F32: // FCVTL2 Vd.2D,Vn.4S float64x2_t vcvt_high_f64_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTAQ_S16_F16: // FCVTAS Vd.8H,Vn.8H int16x8_t vcvtaq_s16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTAQ_S32_F32: // FCVTAS Vd.4S,Vn.4S int32x4_t vcvtaq_s32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTAQ_S64_F64: // FCVTAS Vd.2D,Vn.2D int64x2_t vcvtaq_s64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTAQ_U16_F16: // FCVTAU Vd.8H,Vn.8H uint16x8_t vcvtaq_u16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTAQ_U32_F32: // FCVTAU Vd.4S,Vn.4S uint32x4_t vcvtaq_u32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTAQ_U64_F64: // FCVTAU Vd.2D,Vn.2D uint64x2_t vcvtaq_u64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTMQ_S16_F16: // FCVTMS Vd.8H,Vn.8H int16x8_t vcvtmq_s16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTMQ_S32_F32: // FCVTMS Vd.4S,Vn.4S int32x4_t vcvtmq_s32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTMQ_S64_F64: // FCVTMS Vd.2D,Vn.2D int64x2_t vcvtmq_s64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTMQ_U16_F16: // FCVTMU Vd.8H,Vn.8H uint16x8_t vcvtmq_u16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTMQ_U32_F32: // FCVTMU Vd.4S,Vn.4S uint32x4_t vcvtmq_u32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTMQ_U64_F64: // FCVTMU Vd.2D,Vn.2D uint64x2_t vcvtmq_u64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTNQ_S16_F16: // FCVTNS Vd.8H,Vn.8H int16x8_t vcvtnq_s16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTNQ_S32_F32: // FCVTNS Vd.4S,Vn.4S int32x4_t vcvtnq_s32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTNQ_S64_F64: // FCVTNS Vd.2D,Vn.2D int64x2_t vcvtnq_s64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTNQ_U16_F16: // FCVTNU Vd.8H,Vn.8H uint16x8_t vcvtnq_u16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTNQ_U32_F32: // FCVTNU Vd.4S,Vn.4S uint32x4_t vcvtnq_u32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTNQ_U64_F64: // FCVTNU Vd.2D,Vn.2D uint64x2_t vcvtnq_u64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTPQ_S16_F16: // FCVTPS Vd.8H,Vn.8H int16x8_t vcvtpq_s16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTPQ_S32_F32: // FCVTPS Vd.4S,Vn.4S int32x4_t vcvtpq_s32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTPQ_S64_F64: // FCVTPS Vd.2D,Vn.2D int64x2_t vcvtpq_s64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTPQ_U16_F16: // FCVTPU Vd.8H,Vn.8H uint16x8_t vcvtpq_u16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTPQ_U32_F32: // FCVTPU Vd.4S,Vn.4S uint32x4_t vcvtpq_u32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTPQ_U64_F64: // FCVTPU Vd.2D,Vn.2D uint64x2_t vcvtpq_u64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTQ_HIGH_F32_BF16: // SHLL2 Vd.4S,Vn.8H,#16 float32x4_t vcvtq_high_f32_bf16(bfloat16x8_t a)
+ case ARM64_INTRIN_VCVTQ_LOW_BF16_F32: // BFCVTN Vd.4H,Vn.4S bfloat16x8_t vcvtq_low_bf16_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTQ_LOW_F32_BF16: // SHLL Vd.4S,Vn.8H,#16 float32x4_t vcvtq_low_f32_bf16(bfloat16x8_t a)
+ case ARM64_INTRIN_VCVTQ_S16_F16: // FCVTZS Vd.8H,Vn.8H int16x8_t vcvtq_s16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTQ_S32_F32: // FCVTZS Vd.4S,Vn.4S int32x4_t vcvtq_s32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTQ_S64_F64: // FCVTZS Vd.2D,Vn.2D int64x2_t vcvtq_s64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTQ_U16_F16: // FCVTZS Vd.8H,Vn.8H uint16x8_t vcvtq_u16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTQ_U32_F32: // FCVTZU Vd.4S,Vn.4S uint32x4_t vcvtq_u32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTQ_U64_F64: // FCVTZU Vd.2D,Vn.2D uint64x2_t vcvtq_u64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTX_F32_F64: // FCVTXN Vd.2S,Vn.2D float32x2_t vcvtx_f32_f64(float64x2_t a)
+ case ARM64_INTRIN_VGET_HIGH_BF16: // DUP Vd.1D,Vn.D[1] bfloat16x4_t vget_high_bf16(bfloat16x8_t a)
+ case ARM64_INTRIN_VGET_HIGH_F16: // DUP Vd.1D,Vn.D[1] float16x4_t vget_high_f16(float16x8_t a)
+ case ARM64_INTRIN_VGET_HIGH_F32: // DUP Vd.1D,Vn.D[1] float32x2_t vget_high_f32(float32x4_t a)
+ case ARM64_INTRIN_VGET_HIGH_F64: // DUP Vd.1D,Vn.D[1] float64x1_t vget_high_f64(float64x2_t a)
+ case ARM64_INTRIN_VGET_LOW_BF16: // DUP Vd.1D,Vn.D[0] bfloat16x4_t vget_low_bf16(bfloat16x8_t a)
+ case ARM64_INTRIN_VGET_LOW_F16: // DUP Vd.1D,Vn.D[0] float16x4_t vget_low_f16(float16x8_t a)
+ case ARM64_INTRIN_VGET_LOW_F32: // DUP Vd.1D,Vn.D[0] float32x2_t vget_low_f32(float32x4_t a)
+ case ARM64_INTRIN_VGET_LOW_F64: // DUP Vd.1D,Vn.D[0] float64x1_t vget_low_f64(float64x2_t a)
+ case ARM64_INTRIN_VMAXNMVQ_F16: // FMAXNMP Hd,Vn.8H float16_t vmaxnmvq_f16(float16x8_t a)
+ // case ARM64_INTRIN_VMAXNMVQ_F16: // FMAXNMV Hd,Hn.8H float16_t vmaxnmvq_f16(float16x8_t a)
+ case ARM64_INTRIN_VMAXNMVQ_F32: // FMAXNMV Sd,Vn.4S float32_t vmaxnmvq_f32(float32x4_t a)
+ case ARM64_INTRIN_VMAXNMVQ_F64: // FMAXNMP Dd,Vn.2D float64_t vmaxnmvq_f64(float64x2_t a)
+ case ARM64_INTRIN_VMAXVQ_F16: // FMAXP Hd,Vn.8H float16_t vmaxvq_f16(float16x8_t a)
+ // case ARM64_INTRIN_VMAXVQ_F16: // FMAXV Hd,Hn.8H float16_t vmaxvq_f16(float16x8_t a)
+ case ARM64_INTRIN_VMAXVQ_F32: // FMAXV Sd,Vn.4S float32_t vmaxvq_f32(float32x4_t a)
+ case ARM64_INTRIN_VMAXVQ_F64: // FMAXP Dd,Vn.2D float64_t vmaxvq_f64(float64x2_t a)
+ case ARM64_INTRIN_VMINNMVQ_F16: // FMINNMP Hd,Vn.8H float16_t vminnmvq_f16(float16x8_t a)
+ // case ARM64_INTRIN_VMINNMVQ_F16: // FMINNMV Hd,Vn.8H float16_t vminnmvq_f16(float16x8_t a)
+ case ARM64_INTRIN_VMINNMVQ_F32: // FMINNMV Sd,Vn.4S float32_t vminnmvq_f32(float32x4_t a)
+ case ARM64_INTRIN_VMINNMVQ_F64: // FMINNMP Dd,Vn.2D float64_t vminnmvq_f64(float64x2_t a)
+ case ARM64_INTRIN_VMINVQ_F16: // FMINP Hd,Vn.8H float16_t vminvq_f16(float16x8_t a)
+ // case ARM64_INTRIN_VMINVQ_F16: // FMINV Hd,Vn.8H float16_t vminvq_f16(float16x8_t a)
+ case ARM64_INTRIN_VMINVQ_F32: // FMINV Sd,Vn.4S float32_t vminvq_f32(float32x4_t a)
+ case ARM64_INTRIN_VMINVQ_F64: // FMINP Dd,Vn.2D float64_t vminvq_f64(float64x2_t a)
+ // case ARM64_INTRIN_VMINVQ_F64: // FMINV Dd,Vn.2D float64_t vminvq_f64(float64x2_t a)
+ case ARM64_INTRIN_VNEGQ_F16: // FNEG Vd.8H,Vn.8H float16x8_t vnegq_f16(float16x8_t a)
+ case ARM64_INTRIN_VNEGQ_F32: // FNEG Vd.4S,Vn.4S float32x4_t vnegq_f32(float32x4_t a)
+ case ARM64_INTRIN_VNEGQ_F64: // FNEG Vd.2D,Vn.2D float64x2_t vnegq_f64(float64x2_t a)
+ case ARM64_INTRIN_VPADDD_F64: // FADDP Dd,Vn.2D float64_t vpaddd_f64(float64x2_t a)
+ case ARM64_INTRIN_VPMAXNMQD_F64: // FMAXNMP Dd,Vn.2D float64_t vpmaxnmqd_f64(float64x2_t a)
+ case ARM64_INTRIN_VPMAXQD_F64: // FMAXP Dd,Vn.2D float64_t vpmaxqd_f64(float64x2_t a)
+ case ARM64_INTRIN_VPMINNMQD_F64: // FMINNMP Dd,Vn.2D float64_t vpminnmqd_f64(float64x2_t a)
+ case ARM64_INTRIN_VPMINQD_F64: // FMINP Dd,Vn.2D float64_t vpminqd_f64(float64x2_t a)
+ case ARM64_INTRIN_VRECPEQ_F16: // FRECPE Vd.8H,Vn.8H float16x8_t vrecpeq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRECPEQ_F32: // FRECPE Vd.4S,Vn.4S float32x4_t vrecpeq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRECPEQ_F64: // FRECPE Vd.2D,Vn.2D float64x2_t vrecpeq_f64(float64x2_t a)
+ case ARM64_INTRIN_VREV64Q_F16: // REV64 Vd.8H,Vn.8H float16x8_t vrev64q_f16(float16x8_t vec)
+ case ARM64_INTRIN_VREV64Q_F32: // REV64 Vd.4S,Vn.4S float32x4_t vrev64q_f32(float32x4_t vec)
+ case ARM64_INTRIN_VRND32XQ_F32: // FRINT32X Vd.4S,Vn.4S float32x4_t vrnd32xq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRND32XQ_F64: // FRINT32X Vd.2D,Vn.2D float64x2_t vrnd32xq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRND32ZQ_F32: // FRINT32Z Vd.4S,Vn.4S float32x4_t vrnd32zq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRND32ZQ_F64: // FRINT32Z Vd.2D,Vn.2D float64x2_t vrnd32zq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRND64XQ_F32: // FRINT64X Vd.4S,Vn.4S float32x4_t vrnd64xq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRND64XQ_F64: // FRINT64X Vd.2D,Vn.2D float64x2_t vrnd64xq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRND64ZQ_F32: // FRINT64Z Vd.4S,Vn.4S float32x4_t vrnd64zq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRND64ZQ_F64: // FRINT64Z Vd.2D,Vn.2D float64x2_t vrnd64zq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRNDAQ_F16: // FRINTA Vd.8H,Vn.8H float16x8_t vrndaq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRNDAQ_F32: // FRINTA Vd.4S,Vn.4S float32x4_t vrndaq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRNDAQ_F64: // FRINTA Vd.2D,Vn.2D float64x2_t vrndaq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRNDIQ_F16: // FRINTI Vd.8H,Vn.8H float16x8_t vrndiq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRNDIQ_F32: // FRINTI Vd.4S,Vn.4S float32x4_t vrndiq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRNDIQ_F64: // FRINTI Vd.2D,Vn.2D float64x2_t vrndiq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRNDMQ_F16: // FRINTM Vd.8H,Vn.8H float16x8_t vrndmq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRNDMQ_F32: // FRINTM Vd.4S,Vn.4S float32x4_t vrndmq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRNDMQ_F64: // FRINTM Vd.2D,Vn.2D float64x2_t vrndmq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRNDNQ_F16: // FRINTN Vd.8H,Vn.8H float16x8_t vrndnq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRNDNQ_F32: // FRINTN Vd.4S,Vn.4S float32x4_t vrndnq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRNDNQ_F64: // FRINTN Vd.2D,Vn.2D float64x2_t vrndnq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRNDPQ_F16: // FRINTP Vd.8H,Vn.8H float16x8_t vrndpq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRNDPQ_F32: // FRINTP Vd.4S,Vn.4S float32x4_t vrndpq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRNDPQ_F64: // FRINTP Vd.2D,Vn.2D float64x2_t vrndpq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRNDQ_F16: // FRINTZ Vd.8H,Vn.8H float16x8_t vrndq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRNDQ_F32: // FRINTZ Vd.4S,Vn.4S float32x4_t vrndq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRNDQ_F64: // FRINTZ Vd.2D,Vn.2D float64x2_t vrndq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRNDXQ_F16: // FRINTX Vd.8H,Vn.8H float16x8_t vrndxq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRNDXQ_F32: // FRINTX Vd.4S,Vn.4S float32x4_t vrndxq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRNDXQ_F64: // FRINTX Vd.2D,Vn.2D float64x2_t vrndxq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRSQRTEQ_F16: // FRSQRTE Vd.8H,Vn.8H float16x8_t vrsqrteq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRSQRTEQ_F32: // FRSQRTE Vd.4S,Vn.4S float32x4_t vrsqrteq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRSQRTEQ_F64: // FRSQRTE Vd.2D,Vn.2D float64x2_t vrsqrteq_f64(float64x2_t a)
+ case ARM64_INTRIN_VSQRTQ_F16: // FSQRT Vd.8H,Vn.8H float16x8_t vsqrtq_f16(float16x8_t a)
+ case ARM64_INTRIN_VSQRTQ_F32: // FSQRT Vd.4S,Vn.4S float32x4_t vsqrtq_f32(float32x4_t a)
+ case ARM64_INTRIN_VSQRTQ_F64: // FSQRT Vd.2D,Vn.2D float64x2_t vsqrtq_f64(float64x2_t a)
+ return {NameAndType(Type::FloatType(16))};
+ case ARM64_INTRIN_VABDQ_F16: // FABD Vd.8H,Vn.8H,Vm.8H float16x8_t vabdq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VABDQ_F32: // FABD Vd.4S,Vn.4S,Vm.4S float32x4_t vabdq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VABDQ_F64: // FABD Vd.2D,Vn.2D,Vm.2D float64x2_t vabdq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VADDQ_F16: // FADD Vd.8H,Vn.8H,Vm.8H float16x8_t vaddq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VADDQ_F32: // FADD Vd.4S,Vn.4S,Vm.4S float32x4_t vaddq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VADDQ_F64: // FADD Vd.2D,Vn.2D,Vm.2D float64x2_t vaddq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCADDQ_ROT270_F16: // FCADD Vd.8H,Vn.8H,Vm.8H,#270 float16x8_t vcaddq_rot270_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCADDQ_ROT270_F32: // FCADD Vd.4S,Vn.4S,Vm.4S,#270 float32x4_t vcaddq_rot270_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCADDQ_ROT270_F64: // FCADD Vd.2D,Vn.2D,Vm.2D,#270 float64x2_t vcaddq_rot270_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCADDQ_ROT90_F16: // FCADD Vd.8H,Vn.8H,Vm.8H,#90 float16x8_t vcaddq_rot90_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCADDQ_ROT90_F32: // FCADD Vd.4S,Vn.4S,Vm.4S,#90 float32x4_t vcaddq_rot90_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCADDQ_ROT90_F64: // FCADD Vd.2D,Vn.2D,Vm.2D,#90 float64x2_t vcaddq_rot90_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCAGEQ_F16: // FACGE Vd.8H,Vn.8H,Vm.8H uint16x8_t vcageq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCAGEQ_F32: // FACGE Vd.4S,Vn.4S,Vm.4S uint32x4_t vcageq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCAGEQ_F64: // FACGE Vd.2D,Vn.2D,Vm.2D uint64x2_t vcageq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCAGTQ_F16: // FACGT Vd.8H,Vn.8H,Vm.8H uint16x8_t vcagtq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCAGTQ_F32: // FACGT Vd.4S,Vn.4S,Vm.4S uint32x4_t vcagtq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCAGTQ_F64: // FACGT Vd.2D,Vn.2D,Vm.2D uint64x2_t vcagtq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCALEQ_F16: // FACGE Vd.8H,Vn.8H,Vm.8H uint16x8_t vcaleq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCALEQ_F32: // FACGE Vd.4S,Vm.4S,Vn.4S uint32x4_t vcaleq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCALEQ_F64: // FACGE Vd.2D,Vm.2D,Vn.2D uint64x2_t vcaleq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCALTQ_F16: // FACGT Vd.8H,Vn.8H,Vm.8H uint16x8_t vcaltq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCALTQ_F32: // FACGT Vd.4S,Vm.4S,Vn.4S uint32x4_t vcaltq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCALTQ_F64: // FACGT Vd.2D,Vn.2D,Vm.2D uint64x2_t vcaltq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCEQQ_F16: // FCMEQ Vd.8H,Vn.8H,Vm.8H uint16x8_t vceqq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCEQQ_F32: // FCMEQ Vd.4S,Vn.4S,Vm.4S uint32x4_t vceqq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCEQQ_F64: // FCMEQ Vd.2D,Vn.2D,Vm.2D uint64x2_t vceqq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCGEQ_F16: // FCMGE Vd.8H,Vn.8H,Vm.8H uint16x8_t vcgeq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCGEQ_F32: // FCMGE Vd.4S,Vm.4S,Vn.4S uint32x4_t vcgeq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCGEQ_F64: // FCMGE Vd.2D,Vm.2D,Vn.2D uint64x2_t vcgeq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCGTQ_F16: // FCMGT Vd.8H,Vn.8H,Vm.8H uint16x8_t vcgtq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCGTQ_F32: // FCMGT Vd.4S,Vn.4S,Vm.4S uint32x4_t vcgtq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCGTQ_F64: // FCMGT Vd.2D,Vn.2D,Vm.2D uint64x2_t vcgtq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCLEQ_F16: // FCMGE Vd.8H,Vn.8H,Vm.8H uint16x8_t vcleq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCLEQ_F32: // FCMGE Vd.4S,Vm.4S,Vn.4S uint32x4_t vcleq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCLEQ_F64: // FCMGE Vd.2D,Vm.2D,Vn.2D uint64x2_t vcleq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCLTQ_F16: // FCMGT Vd.8H,Vn.8H,Vm.8H uint16x8_t vcltq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCLTQ_F32: // FCMGT Vd.4S,Vm.4S,Vn.4S uint32x4_t vcltq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCLTQ_F64: // FCMGT Vd.2D,Vm.2D,Vn.2D uint64x2_t vcltq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCVTQ_HIGH_BF16_F32: // BFCVTN2 Vd.8H,Vn.4S bfloat16x8_t vcvtq_high_bf16_f32(bfloat16x8_t inactive, float32x4_t a)
+ case ARM64_INTRIN_VDIVQ_F16: // FDIV Vd.8H,Vn.8H,Vm.8H float16x8_t vdivq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VDIVQ_F32: // FDIV Vd.4S,Vn.4S,Vm.4S float32x4_t vdivq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VDIVQ_F64: // FDIV Vd.2D,Vn.2D,Vm.2D float64x2_t vdivq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VMAXNMQ_F16: // FMAXNM Vd.8H,Vn.8H,Vm.8H float16x8_t vmaxnmq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VMAXNMQ_F32: // FMAXNM Vd.4S,Vn.4S,Vm.4S float32x4_t vmaxnmq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VMAXNMQ_F64: // FMAXNM Vd.2D,Vn.2D,Vm.2D float64x2_t vmaxnmq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VMAXQ_F16: // FMAX Vd.8H,Vn.8H,Vm.8H float16x8_t vmaxq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VMAXQ_F32: // FMAX Vd.4S,Vn.4S,Vm.4S float32x4_t vmaxq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VMAXQ_F64: // FMAX Vd.2D,Vn.2D,Vm.2D float64x2_t vmaxq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VMINNMQ_F16: // FMINNM Vd.8H,Vn.8H,Vm.8H float16x8_t vminnmq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VMINNMQ_F32: // FMINNM Vd.4S,Vn.4S,Vm.4S float32x4_t vminnmq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VMINNMQ_F64: // FMINNM Vd.2D,Vn.2D,Vm.2D float64x2_t vminnmq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VMINQ_F16: // FMIN Vd.8H,Vn.8H,Vm.8H float16x8_t vminq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VMINQ_F32: // FMIN Vd.4S,Vn.4S,Vm.4S float32x4_t vminq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VMINQ_F64: // FMIN Vd.2D,Vn.2D,Vm.2D float64x2_t vminq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VMULQ_F16: // FMUL Vd.8H,Vn.8H,Vm.8H float16x8_t vmulq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VMULQ_F32: // FMUL Vd.4S,Vn.4S,Vm.4S float32x4_t vmulq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VMULQ_F64: // FMUL Vd.2D,Vn.2D,Vm.2D float64x2_t vmulq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VMULXQ_F16: // FMULX Vd.8H,Vn.8H,Vm.8H float16x8_t vmulxq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VMULXQ_F32: // FMULX Vd.4S,Vn.4S,Vm.4S float32x4_t vmulxq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VMULXQ_F64: // FMULX Vd.2D,Vn.2D,Vm.2D float64x2_t vmulxq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VPADDQ_F16: // FADDP Vd.8H,Vn.8H,Vm.8H float16x8_t vpaddq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VPADDQ_F32: // FADDP Vd.4S,Vn.4S,Vm.4S float32x4_t vpaddq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VPADDQ_F64: // FADDP Vd.2D,Vn.2D,Vm.2D float64x2_t vpaddq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VPMAXNMQ_F16: // FMAXNMP Vd.8H,Vn.8H,Vm.8H float16x8_t vpmaxnmq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VPMAXNMQ_F32: // FMAXNMP Vd.4S,Vn.4S,Vm.4S float32x4_t vpmaxnmq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VPMAXNMQ_F64: // FMAXNMP Vd.2D,Vn.2D,Vm.2D float64x2_t vpmaxnmq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VPMAXQ_F16: // FMAXP Vd.8H,Vn.8H,Vm.8H float16x8_t vpmaxq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VPMAXQ_F32: // FMAXP Vd.4S,Vn.4S,Vm.4S float32x4_t vpmaxq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VPMAXQ_F64: // FMAXP Vd.2D,Vn.2D,Vm.2D float64x2_t vpmaxq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VPMINNMQ_F16: // FMINNMP Vd.8H,Vn.8H,Vm.8H float16x8_t vpminnmq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VPMINNMQ_F32: // FMINNMP Vd.4S,Vn.4S,Vm.4S float32x4_t vpminnmq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VPMINNMQ_F64: // FMINNMP Vd.2D,Vn.2D,Vm.2D float64x2_t vpminnmq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VPMINQ_F16: // FMINP Vd.8H,Vn.8H,Vm.8H float16x8_t vpminq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VPMINQ_F32: // FMINP Vd.4S,Vn.4S,Vm.4S float32x4_t vpminq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VPMINQ_F64: // FMINP Vd.2D,Vn.2D,Vm.2D float64x2_t vpminq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VRECPSQ_F16: // FRECPS Vd.8H,Vn.8H,Vm.8H float16x8_t vrecpsq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VRECPSQ_F32: // FRECPS Vd.4S,Vn.4S,Vm.4S float32x4_t vrecpsq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VRECPSQ_F64: // FRECPS Vd.2D,Vn.2D,Vm.2D float64x2_t vrecpsq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VRSQRTSQ_F16: // FRSQRTS Vd.8H,Vn.8H,Vm.8H float16x8_t vrsqrtsq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VRSQRTSQ_F32: // FRSQRTS Vd.4S,Vn.4S,Vm.4S float32x4_t vrsqrtsq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VRSQRTSQ_F64: // FRSQRTS Vd.2D,Vn.2D,Vm.2D float64x2_t vrsqrtsq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VSUBQ_F16: // FSUB Vd.8H,Vn.8H,Vm.8H float16x8_t vsubq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VSUBQ_F32: // FSUB Vd.4S,Vn.4S,Vm.4S float32x4_t vsubq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VSUBQ_F64: // FSUB Vd.2D,Vn.2D,Vm.2D float64x2_t vsubq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VTRN1Q_F16: // TRN1 Vd.8H,Vn.8H,Vm.8H float16x8_t vtrn1q_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VTRN1Q_F32: // TRN1 Vd.4S,Vn.4S,Vm.4S float32x4_t vtrn1q_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VTRN1Q_F64: // TRN1 Vd.2D,Vn.2D,Vm.2D float64x2_t vtrn1q_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VTRN2Q_F16: // TRN2 Vd.8H,Vn.8H,Vm.8H float16x8_t vtrn2q_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VTRN2Q_F32: // TRN2 Vd.4S,Vn.4S,Vm.4S float32x4_t vtrn2q_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VTRN2Q_F64: // TRN2 Vd.2D,Vn.2D,Vm.2D float64x2_t vtrn2q_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VTRNQ_F16: // TRN1 Vd1.8H,Vn.8H,Vm.8H float16x8x2_t vtrnq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VTRNQ_F32: // TRN1 Vd1.4S,Vn.4S,Vm.4S float32x4x2_t vtrnq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VUZP1Q_F16: // UZP1 Vd.8H,Vn.8H,Vm.8H float16x8_t vuzp1q_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VUZP1Q_F32: // UZP1 Vd.4S,Vn.4S,Vm.4S float32x4_t vuzp1q_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VUZP1Q_F64: // UZP1 Vd.2D,Vn.2D,Vm.2D float64x2_t vuzp1q_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VUZP2Q_F16: // UZP2 Vd.8H,Vn.8H,Vm.8H float16x8_t vuzp2q_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VUZP2Q_F32: // UZP2 Vd.4S,Vn.4S,Vm.4S float32x4_t vuzp2q_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VUZP2Q_F64: // UZP2 Vd.2D,Vn.2D,Vm.2D float64x2_t vuzp2q_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VUZPQ_F16: // UZP1 Vd1.8H,Vn.8H,Vm.8H float16x8x2_t vuzpq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VUZPQ_F32: // UZP1 Vd1.4S,Vn.4S,Vm.4S float32x4x2_t vuzpq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VZIP1Q_F16: // ZIP1 Vd.8H,Vn.8H,Vm.8H float16x8_t vzip1q_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VZIP1Q_F32: // ZIP1 Vd.4S,Vn.4S,Vm.4S float32x4_t vzip1q_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VZIP1Q_F64: // ZIP1 Vd.2D,Vn.2D,Vm.2D float64x2_t vzip1q_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VZIP2Q_F16: // ZIP2 Vd.8H,Vn.8H,Vm.8H float16x8_t vzip2q_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VZIP2Q_F32: // ZIP2 Vd.4S,Vn.4S,Vm.4S float32x4_t vzip2q_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VZIP2Q_F64: // ZIP2 Vd.2D,Vn.2D,Vm.2D float64x2_t vzip2q_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VZIPQ_F16: // ZIP1 Vd1.8H,Vn.8H,Vm.8H float16x8x2_t vzipq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VZIPQ_F32: // ZIP1 Vd1.4S,Vn.4S,Vm.4S float32x4x2_t vzipq_f32(float32x4_t a, float32x4_t b)
+ return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16))};
+ case ARM64_INTRIN_VBFDOTQ_F32: // BFDOT Vd.4S,Vn.8H,Vm.8H float32x4_t vbfdotq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b)
+ case ARM64_INTRIN_VBFMLALBQ_F32: // BFMLALB Vd.4S,Vn.8H,Vm.8H float32x4_t vbfmlalbq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b)
+ case ARM64_INTRIN_VBFMLALTQ_F32: // BFMLALT Vd.4S,Vn.8H,Vm.8H float32x4_t vbfmlaltq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b)
+ case ARM64_INTRIN_VBFMMLAQ_F32: // BFMMLA Vd.4S,Vn.8H,Vm.8H float32x4_t vbfmmlaq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b)
+ case ARM64_INTRIN_VCMLAQ_F16: // FCMLA Vd.8H,Vn.8H,Vm.8H,#0 float16x8_t vcmlaq_f16(float16x8_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCMLAQ_F32: // FCMLA Vd.4S,Vn.4S,Vm.4S,#0 float32x4_t vcmlaq_f32(float32x4_t r, float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCMLAQ_F64: // FCMLA Vd.2D,Vn.2D,Vm.2D,#0 float64x2_t vcmlaq_f64(float64x2_t r, float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT180_F16: // FCMLA Vd.8H,Vn.8H,Vm.8H,#180 float16x8_t vcmlaq_rot180_f16(float16x8_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT180_F32: // FCMLA Vd.4S,Vn.4S,Vm.4S,#180 float32x4_t vcmlaq_rot180_f32(float32x4_t r, float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT180_F64: // FCMLA Vd.2D,Vn.2D,Vm.2D,#180 float64x2_t vcmlaq_rot180_f64(float64x2_t r, float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT270_F16: // FCMLA Vd.8H,Vn.8H,Vm.8H,#270 float16x8_t vcmlaq_rot270_f16(float16x8_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT270_F32: // FCMLA Vd.4S,Vn.4S,Vm.4S,#270 float32x4_t vcmlaq_rot270_f32(float32x4_t r, float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT270_F64: // FCMLA Vd.2D,Vn.2D,Vm.2D,#270 float64x2_t vcmlaq_rot270_f64(float64x2_t r, float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT90_F16: // FCMLA Vd.8H,Vn.8H,Vm.8H,#90 float16x8_t vcmlaq_rot90_f16(float16x8_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT90_F32: // FCMLA Vd.4S,Vn.4S,Vm.4S,#90 float32x4_t vcmlaq_rot90_f32(float32x4_t r, float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT90_F64: // FCMLA Vd.2D,Vn.2D,Vm.2D,#90 float64x2_t vcmlaq_rot90_f64(float64x2_t r, float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VFMAQ_F16: // FMLA Vd.8H,Vn.8H,Vm.8H float16x8_t vfmaq_f16(float16x8_t a, float16x8_t b, float16x8_t c)
+ case ARM64_INTRIN_VFMAQ_F32: // FMLA Vd.4S,Vn.4S,Vm.4S float32x4_t vfmaq_f32(float32x4_t a, float32x4_t b, float32x4_t c)
+ case ARM64_INTRIN_VFMAQ_F64: // FMLA Vd.2D,Vn.2D,Vm.2D float64x2_t vfmaq_f64(float64x2_t a, float64x2_t b, float64x2_t c)
+ case ARM64_INTRIN_VFMLALQ_HIGH_F16: // FMLAL2 Vd.4S,Vn.4H,Vm.4H float32x4_t vfmlalq_high_f16(float32x4_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VFMLALQ_LOW_F16: // FMLAL Vd.4S,Vn.4H,Vm.4H float32x4_t vfmlalq_low_f16(float32x4_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VFMLSLQ_HIGH_F16: // FMLSL2 Vd.4S,Vn.4H,Vm.4H float32x4_t vfmlslq_high_f16(float32x4_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VFMLSLQ_LOW_F16: // FMLSL Vd.4S,Vn.4H,Vm.4H float32x4_t vfmlslq_low_f16(float32x4_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VFMSQ_F16: // FMLS Vd.8H,Vn.8H,Vm.8H float16x8_t vfmsq_f16(float16x8_t a, float16x8_t b, float16x8_t c)
+ case ARM64_INTRIN_VFMSQ_F32: // FMLS Vd.4S,Vn.4S,Vm.4S float32x4_t vfmsq_f32(float32x4_t a, float32x4_t b, float32x4_t c)
+ case ARM64_INTRIN_VFMSQ_F64: // FMLS Vd.2D,Vn.2D,Vm.2D float64x2_t vfmsq_f64(float64x2_t a, float64x2_t b, float64x2_t c)
+ return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16))};
+ case ARM64_INTRIN_VBFDOTQ_LANEQ_F32: // BFDOT Vd.4S,Vn.8H,Vm.2H[lane] float32x4_t vbfdotq_laneq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b, const int lane)
+ case ARM64_INTRIN_VBFMLALBQ_LANEQ_F32: // BFMLALB Vd.4S,Vn.8H,Vm.H[lane] float32x4_t vbfmlalbq_laneq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b, const int lane)
+ case ARM64_INTRIN_VBFMLALTQ_LANEQ_F32: // BFMLALT Vd.4S,Vn.8H,Vm.H[lane] float32x4_t vbfmlaltq_laneq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_LANEQ_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#0 float16x8_t vcmlaq_laneq_f16(float16x8_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_LANEQ_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#0 float32x4_t vcmlaq_laneq_f32(float32x4_t r, float32x4_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT180_LANEQ_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#180 float16x8_t vcmlaq_rot180_laneq_f16(float16x8_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT180_LANEQ_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#180 float32x4_t vcmlaq_rot180_laneq_f32(float32x4_t r, float32x4_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT270_LANEQ_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#270 float16x8_t vcmlaq_rot270_laneq_f16(float16x8_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT270_LANEQ_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#270 float32x4_t vcmlaq_rot270_laneq_f32(float32x4_t r, float32x4_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT90_LANEQ_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#90 float16x8_t vcmlaq_rot90_laneq_f16(float16x8_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT90_LANEQ_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#90 float32x4_t vcmlaq_rot90_laneq_f32(float32x4_t r, float32x4_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VFMAQ_LANEQ_F16: // FMLA Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vfmaq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VFMAQ_LANEQ_F32: // FMLA Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vfmaq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VFMAQ_LANEQ_F64: // FMLA Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vfmaq_laneq_f64(float64x2_t a, float64x2_t b, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VFMLALQ_LANEQ_HIGH_F16: // FMLAL2 Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlalq_laneq_high_f16(float32x4_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMLALQ_LANEQ_LOW_F16: // FMLAL Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlalq_laneq_low_f16(float32x4_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMLSLQ_LANEQ_HIGH_F16: // FMLSL2 Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlslq_laneq_high_f16(float32x4_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMLSLQ_LANEQ_LOW_F16: // FMLSL Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlslq_laneq_low_f16(float32x4_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMSQ_LANEQ_F16: // FMLS Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vfmsq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VFMSQ_LANEQ_F32: // FMLS Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vfmsq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VFMSQ_LANEQ_F64: // FMLS Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vfmsq_laneq_f64(float64x2_t a, float64x2_t b, float64x2_t v, const int lane)
+ return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VFMAQ_N_F16: // FMLA Vd.8H,Vn.8H,Vm.H[0] float16x8_t vfmaq_n_f16(float16x8_t a, float16x8_t b, float16_t n)
+ case ARM64_INTRIN_VFMSQ_N_F16: // FMLS Vd.8H,Vn.8H,Vm.H[0] float16x8_t vfmsq_n_f16(float16x8_t a, float16x8_t b, float16_t n)
+ return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(2))};
+ case ARM64_INTRIN_VFMAQ_N_F32: // FMLA Vd.4S,Vn.4S,Vm.S[0] float32x4_t vfmaq_n_f32(float32x4_t a, float32x4_t b, float32_t n)
+ case ARM64_INTRIN_VFMSQ_N_F32: // FMLS Vd.4S,Vn.4S,Vm.S[0] float32x4_t vfmsq_n_f32(float32x4_t a, float32x4_t b, float32_t n)
+ return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(4))};
+ case ARM64_INTRIN_VFMAQ_N_F64: // FMLA Vd.2D,Vn.2D,Vm.D[0] float64x2_t vfmaq_n_f64(float64x2_t a, float64x2_t b, float64_t n)
+ case ARM64_INTRIN_VFMSQ_N_F64: // FMLS Vd.2D,Vn.2D,Vm.D[0] float64x2_t vfmsq_n_f64(float64x2_t a, float64x2_t b, float64_t n)
+ return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(8))};
+ case ARM64_INTRIN_VBFDOTQ_LANE_F32: // BFDOT Vd.4S,Vn.8H,Vm.2H[lane] float32x4_t vbfdotq_lane_f32(float32x4_t r, bfloat16x8_t a, bfloat16x4_t b, const int lane)
+ case ARM64_INTRIN_VBFMLALBQ_LANE_F32: // BFMLALB Vd.4S,Vn.8H,Vm.H[lane] float32x4_t vbfmlalbq_lane_f32(float32x4_t r, bfloat16x8_t a, bfloat16x4_t b, const int lane)
+ case ARM64_INTRIN_VBFMLALTQ_LANE_F32: // BFMLALT Vd.4S,Vn.8H,Vm.H[lane] float32x4_t vbfmlaltq_lane_f32(float32x4_t r, bfloat16x8_t a, bfloat16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_LANE_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#0 float16x8_t vcmlaq_lane_f16(float16x8_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_LANE_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#0 float32x4_t vcmlaq_lane_f32(float32x4_t r, float32x4_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT180_LANE_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#180 float16x8_t vcmlaq_rot180_lane_f16(float16x8_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT180_LANE_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#180 float32x4_t vcmlaq_rot180_lane_f32(float32x4_t r, float32x4_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT270_LANE_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#270 float16x8_t vcmlaq_rot270_lane_f16(float16x8_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT270_LANE_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#270 float32x4_t vcmlaq_rot270_lane_f32(float32x4_t r, float32x4_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT90_LANE_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#90 float16x8_t vcmlaq_rot90_lane_f16(float16x8_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT90_LANE_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#90 float32x4_t vcmlaq_rot90_lane_f32(float32x4_t r, float32x4_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VFMAQ_LANE_F16: // FMLA Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vfmaq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VFMAQ_LANE_F32: // FMLA Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vfmaq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VFMAQ_LANE_F64: // FMLA Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vfmaq_lane_f64(float64x2_t a, float64x2_t b, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VFMLALQ_LANE_HIGH_F16: // FMLAL2 Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlalq_lane_high_f16(float32x4_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMLALQ_LANE_LOW_F16: // FMLAL Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlalq_lane_low_f16(float32x4_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMLSLQ_LANE_HIGH_F16: // FMLSL2 Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlslq_lane_high_f16(float32x4_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMLSLQ_LANE_LOW_F16: // FMLSL Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlslq_lane_low_f16(float32x4_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMSQ_LANE_F16: // FMLS Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vfmsq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VFMSQ_LANE_F32: // FMLS Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vfmsq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VFMSQ_LANE_F64: // FMLS Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vfmsq_lane_f64(float64x2_t a, float64x2_t b, float64x1_t v, const int lane)
+ return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VEXTQ_F16: // EXT Vd.16B,Vn.16B,Vm.16B,#n float16x8_t vextq_f16(float16x8_t a, float16x8_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_F32: // EXT Vd.16B,Vn.16B,Vm.16B,#n float32x4_t vextq_f32(float32x4_t a, float32x4_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_F64: // EXT Vd.16B,Vn.16B,Vm.16B,#n float64x2_t vextq_f64(float64x2_t a, float64x2_t b, const int n)
+ case ARM64_INTRIN_VMULQ_LANEQ_F16: // FMUL Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vmulq_laneq_f16(float16x8_t a, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANEQ_F32: // FMUL Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vmulq_laneq_f32(float32x4_t a, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANEQ_F64: // FMUL Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vmulq_laneq_f64(float64x2_t a, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VMULXQ_LANEQ_F16: // FMULX Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vmulxq_laneq_f16(float16x8_t a, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULXQ_LANEQ_F32: // FMULX Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vmulxq_laneq_f32(float32x4_t a, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULXQ_LANEQ_F64: // FMULX Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vmulxq_laneq_f64(float64x2_t a, float64x2_t v, const int lane)
+ return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VMULQ_N_F16: // FMUL Vd.8H,Vn.8H,Vm.H[0] float16x8_t vmulq_n_f16(float16x8_t a, float16_t n)
+ case ARM64_INTRIN_VMULXQ_N_F16: // FMULX Vd.8H,Vn.8H,Vm.H[0] float16x8_t vmulxq_n_f16(float16x8_t a, float16_t n)
+ return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(2))};
+ case ARM64_INTRIN_VMULQ_N_F32: // FMUL Vd.4S,Vn.4S,Vm.S[0] float32x4_t vmulq_n_f32(float32x4_t a, float32_t b)
+ return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(4))};
+ case ARM64_INTRIN_VMULQ_N_F64: // FMUL Vd.2D,Vn.2D,Vm.D[0] float64x2_t vmulq_n_f64(float64x2_t a, float64_t b)
+ return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(8))};
+ case ARM64_INTRIN_VMULQ_LANE_F16: // FMUL Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vmulq_lane_f16(float16x8_t a, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANE_F32: // FMUL Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vmulq_lane_f32(float32x4_t a, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANE_F64: // FMUL Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vmulq_lane_f64(float64x2_t a, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VMULXQ_LANE_F16: // FMULX Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vmulxq_lane_f16(float16x8_t a, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULXQ_LANE_F32: // FMULX Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vmulxq_lane_f32(float32x4_t a, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULXQ_LANE_F64: // FMULX Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vmulxq_lane_f64(float64x2_t a, float64x1_t v, const int lane)
+ return {NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VCVTQ_N_S16_F16: // FCVTZS Vd.8H,Vn.8H,#n int16x8_t vcvtq_n_s16_f16(float16x8_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_S32_F32: // FCVTZS Vd.4S,Vn.4S,#n int32x4_t vcvtq_n_s32_f32(float32x4_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_S64_F64: // FCVTZS Vd.2D,Vn.2D,#n int64x2_t vcvtq_n_s64_f64(float64x2_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_U16_F16: // FCVTZU Vd.8H,Vn.8H,#n uint16x8_t vcvtq_n_u16_f16(float16x8_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_U32_F32: // FCVTZU Vd.4S,Vn.4S,#n uint32x4_t vcvtq_n_u32_f32(float32x4_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_U64_F64: // FCVTZU Vd.2D,Vn.2D,#n uint64x2_t vcvtq_n_u64_f64(float64x2_t a, const int n)
+ case ARM64_INTRIN_VDUP_LANEQ_BF16: // DUP Vd.4H,Vn.H[lane] bfloat16x4_t vdup_laneq_bf16(bfloat16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_F16: // DUP Vd.4H,Vn.H[lane] float16x4_t vdup_laneq_f16(float16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_F32: // DUP Vd.2S,Vn.S[lane] float32x2_t vdup_laneq_f32(float32x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_F64: // DUP Dd,Vn.D[lane] float64x1_t vdup_laneq_f64(float64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPD_LANEQ_F64: // DUP Dd,Vn.D[lane] float64_t vdupd_laneq_f64(float64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANEQ_BF16: // DUP Hd,Vn.H[lane] bfloat16_t vduph_laneq_bf16(bfloat16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANEQ_F16: // DUP Hd,Vn.H[lane] float16_t vduph_laneq_f16(float16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_BF16: // DUP Vd.8H,Vn.H[lane] bfloat16x8_t vdupq_laneq_bf16(bfloat16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_F16: // DUP Vd.8H,Vn.H[lane] float16x8_t vdupq_laneq_f16(float16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_F32: // DUP Vd.4S,Vn.S[lane] float32x4_t vdupq_laneq_f32(float32x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_F64: // DUP Vd.2D,Vn.D[lane] float64x2_t vdupq_laneq_f64(float64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPS_LANEQ_F32: // DUP Sd,Vn.S[lane] float32_t vdups_laneq_f32(float32x4_t vec, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_BF16: // DUP Hd,Vn.H[lane] bfloat16_t vgetq_lane_bf16(bfloat16x8_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_F16: // DUP Hd,Vn.H[lane] float16_t vgetq_lane_f16(float16x8_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_F32: // DUP Sd,Vn.S[lane] float32_t vgetq_lane_f32(float32x4_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_F64: // DUP Dd,Vn.D[lane] float64_t vgetq_lane_f64(float64x2_t v, const int lane)
+ return {NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VCOPYQ_LANEQ_BF16: // INS Vd.H[lane1],Vn.H[lane2] bfloat16x8_t vcopyq_laneq_bf16(bfloat16x8_t a, const int lane1, bfloat16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_F32: // INS Vd.S[lane1],Vn.S[lane2] float32x4_t vcopyq_laneq_f32(float32x4_t a, const int lane1, float32x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_F64: // INS Vd.D[lane1],Vn.D[lane2] float64x2_t vcopyq_laneq_f64(float64x2_t a, const int lane1, float64x2_t b, const int lane2)
+ return {NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VCOPYQ_LANE_BF16: // INS Vd.H[lane1],Vn.H[lane2] bfloat16x8_t vcopyq_lane_bf16(bfloat16x8_t a, const int lane1, bfloat16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_F32: // INS Vd.S[lane1],Vn.S[lane2] float32x4_t vcopyq_lane_f32(float32x4_t a, const int lane1, float32x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_F64: // INS Vd.D[lane1],Vn.D[lane2] float64x2_t vcopyq_lane_f64(float64x2_t a, const int lane1, float64x1_t b, const int lane2)
+ return {NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VABSH_F16: // FABS Hd,Hn float16_t vabsh_f16(float16_t a)
+ case ARM64_INTRIN_VCEQZH_F16: // FCMEQ Hd,Hn,#0 uint16_t vceqzh_f16(float16_t a)
+ case ARM64_INTRIN_VCGEZH_F16: // FCMGE Hd,Hn,#0 uint16_t vcgezh_f16(float16_t a)
+ case ARM64_INTRIN_VCGTZH_F16: // FCMGT Hd,Hn,#0 uint16_t vcgtzh_f16(float16_t a)
+ case ARM64_INTRIN_VCLEZH_F16: // FCMLE Hd,Hn,#0 uint16_t vclezh_f16(float16_t a)
+ case ARM64_INTRIN_VCLTZH_F16: // FCMLT Hd,Hn,#0 uint16_t vcltzh_f16(float16_t a)
+ case ARM64_INTRIN_VCVTAH_F32_BF16: // SHL Dd,Dn,#16 float32_t vcvtah_f32_bf16(bfloat16_t a)
+ case ARM64_INTRIN_VCVTAH_S16_F16: // FCVTAS Hd,Hn int16_t vcvtah_s16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTAH_U16_F16: // FCVTAU Hd,Hn uint16_t vcvtah_u16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTH_S16_F16: // FCVTZS Hd,Hn int16_t vcvth_s16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTH_U16_F16: // FCVTZU Hd,Hn uint16_t vcvth_u16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTMH_S16_F16: // FCVTMS Hd,Hn int16_t vcvtmh_s16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTMH_U16_F16: // FCVTMU Hd,Hn uint16_t vcvtmh_u16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTNH_S16_F16: // FCVTNS Hd,Hn int16_t vcvtnh_s16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTNH_U16_F16: // FCVTNU Hd,Hn uint16_t vcvtnh_u16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTPH_S16_F16: // FCVTPS Hd,Hn int16_t vcvtph_s16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTPH_U16_F16: // FCVTPU Hd,Hn uint16_t vcvtph_u16_f16(float16_t a)
+ case ARM64_INTRIN_VDUP_N_BF16: // DUP Vd.4H,rn bfloat16x4_t vdup_n_bf16(bfloat16_t value)
+ case ARM64_INTRIN_VDUP_N_F16: // DUP Vd.4H,rn float16x4_t vdup_n_f16(float16_t value)
+ case ARM64_INTRIN_VDUPQ_N_BF16: // DUP Vd.8H,rn bfloat16x8_t vdupq_n_bf16(bfloat16_t value)
+ case ARM64_INTRIN_VDUPQ_N_F16: // DUP Vd.8H,rn float16x8_t vdupq_n_f16(float16_t value)
+ case ARM64_INTRIN_VMOV_N_F16: // DUP Vd.4H,rn float16x4_t vmov_n_f16(float16_t value)
+ case ARM64_INTRIN_VMOVQ_N_F16: // DUP Vd.8H,rn float16x8_t vmovq_n_f16(float16_t value)
+ case ARM64_INTRIN_VNEGH_F16: // FNEG Hd,Hn float16_t vnegh_f16(float16_t a)
+ case ARM64_INTRIN_VRECPEH_F16: // FRECPE Hd,Hn float16_t vrecpeh_f16(float16_t a)
+ case ARM64_INTRIN_VRECPXH_F16: // FRECPX Hd,Hn float16_t vrecpxh_f16(float16_t a)
+ case ARM64_INTRIN_VRNDAH_F16: // FRINTA Hd,Hn float16_t vrndah_f16(float16_t a)
+ case ARM64_INTRIN_VRNDH_F16: // FRINTZ Hd,Hn float16_t vrndh_f16(float16_t a)
+ case ARM64_INTRIN_VRNDIH_F16: // FRINTI Hd,Hn float16_t vrndih_f16(float16_t a)
+ case ARM64_INTRIN_VRNDMH_F16: // FRINTM Hd,Hn float16_t vrndmh_f16(float16_t a)
+ case ARM64_INTRIN_VRNDNH_F16: // FRINTN Hd,Hn float16_t vrndnh_f16(float16_t a)
+ case ARM64_INTRIN_VRNDPH_F16: // FRINTP Hd,Hn float16_t vrndph_f16(float16_t a)
+ case ARM64_INTRIN_VRNDXH_F16: // FRINTX Hd,Hn float16_t vrndxh_f16(float16_t a)
+ case ARM64_INTRIN_VRSQRTEH_F16: // FRSQRTE Hd,Hn float16_t vrsqrteh_f16(float16_t a)
+ case ARM64_INTRIN_VSQRTH_F16: // FSQRT Hd,Hn float16_t vsqrth_f16(float16_t a)
+ return {NameAndType(Type::FloatType(2))};
+ case ARM64_INTRIN_VMULH_LANEQ_F16: // FMUL Hd,Hn,Vm.H[lane] float16_t vmulh_laneq_f16(float16_t a, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULXH_LANEQ_F16: // FMULX Hd,Hn,Vm.H[lane] float16_t vmulxh_laneq_f16(float16_t a, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_BF16: // INS Vd.H[lane],Vn.H[0] bfloat16x8_t vsetq_lane_bf16(bfloat16_t a, bfloat16x8_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_F16: // MOV Vd.H[lane],Vn.H[0] float16x8_t vsetq_lane_f16(float16_t a, float16x8_t v, const int lane)
+ return {NameAndType(Type::FloatType(2)), NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VABDH_F16: // FABD Hd,Hn,Hm float16_t vabdh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VADDH_F16: // FADD Hd,Hn,Hm float16_t vaddh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCAGEH_F16: // FACGE Hd,Hn,Hm uint16_t vcageh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCAGTH_F16: // FACGT Hd,Hn,Hm uint16_t vcagth_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCALEH_F16: // FACGE Hd,Hn,Hm uint16_t vcaleh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCALTH_F16: // FACGT Hd,Hn,Hm uint16_t vcalth_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCEQH_F16: // FCMEQ Hd,Hn,Hm uint16_t vceqh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCGEH_F16: // FCMGE Hd,Hn,Hm uint16_t vcgeh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCGTH_F16: // FCMGT Hd,Hn,Hm uint16_t vcgth_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCLEH_F16: // FCMGE Hd,Hn,Hm uint16_t vcleh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCLTH_F16: // FCMGT Hd,Hn,Hm uint16_t vclth_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VDIVH_F16: // FDIV Hd,Hn,Hm float16_t vdivh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VMAXH_F16: // FMAX Hd,Hn,Hm float16_t vmaxh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VMAXNMH_F16: // FMAXNM Hd,Hn,Hm float16_t vmaxnmh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VMINH_F16: // FMIN Hd,Hn,Hm float16_t vminh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VMINNMH_F16: // FMINNM Hd,Hn,Hm float16_t vminnmh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VMULH_F16: // FMUL Hd,Hn,Hm float16_t vmulh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VMULXH_F16: // FMULX Hd,Hn,Hm float16_t vmulxh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VRECPSH_F16: // FRECPS Hd,Hn,Hm float16_t vrecpsh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VRSQRTSH_F16: // FRSQRTS Hd,Hn,Hm float16_t vrsqrtsh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VSUBH_F16: // FSUB Hd,Hn,Hm float16_t vsubh_f16(float16_t a, float16_t b)
+ return {NameAndType(Type::FloatType(2)), NameAndType(Type::FloatType(2))};
+ case ARM64_INTRIN_VFMAH_LANEQ_F16: // FMLA Hd,Hn,Vm.H[lane] float16_t vfmah_laneq_f16(float16_t a, float16_t b, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VFMSH_LANEQ_F16: // FMLS Hd,Hn,Vm.H[lane] float16_t vfmsh_laneq_f16(float16_t a, float16_t b, float16x8_t v, const int lane)
+ return {NameAndType(Type::FloatType(2)), NameAndType(Type::FloatType(2)), NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VFMAH_F16: // FMADD Hd,Hn,Hm,Ha float16_t vfmah_f16(float16_t a, float16_t b, float16_t c)
+ case ARM64_INTRIN_VFMSH_F16: // FMSUB Hd,Hn,Hm,Ha float16_t vfmsh_f16(float16_t a, float16_t b, float16_t c)
+ return {NameAndType(Type::FloatType(2)), NameAndType(Type::FloatType(2)), NameAndType(Type::FloatType(2))};
+ case ARM64_INTRIN_VFMAH_LANE_F16: // FMLA Hd,Hn,Vm.H[lane] float16_t vfmah_lane_f16(float16_t a, float16_t b, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VFMSH_LANE_F16: // FMLS Hd,Hn,Vm.H[lane] float16_t vfmsh_lane_f16(float16_t a, float16_t b, float16x4_t v, const int lane)
+ return {NameAndType(Type::FloatType(2)), NameAndType(Type::FloatType(2)), NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VMULH_LANE_F16: // FMUL Hd,Hn,Vm.H[lane] float16_t vmulh_lane_f16(float16_t a, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULXH_LANE_F16: // FMULX Hd,Hn,Vm.H[lane] float16_t vmulxh_lane_f16(float16_t a, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_BF16: // INS Vd.H[lane],Vn.H[0] bfloat16x4_t vset_lane_bf16(bfloat16_t a, bfloat16x4_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_F16: // MOV Vd.H[lane],Vn.H[0] float16x4_t vset_lane_f16(float16_t a, float16x4_t v, const int lane)
+ return {NameAndType(Type::FloatType(2)), NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VCVTH_N_S16_F16: // FCVTZS Hd,Hn,#n int16_t vcvth_n_s16_f16(float16_t a, const int n)
+ case ARM64_INTRIN_VCVTH_N_U16_F16: // FCVTZU Hd,Hn,#n uint16_t vcvth_n_u16_f16(float16_t a, const int n)
+ return {NameAndType(Type::FloatType(2)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VCEQZS_F32: // FCMEQ Sd,Sn,#0 uint32_t vceqzs_f32(float32_t a)
+ case ARM64_INTRIN_VCGEZS_F32: // FCMGE Sd,Sn,#0 uint32_t vcgezs_f32(float32_t a)
+ case ARM64_INTRIN_VCGTZS_F32: // FCMGT Sd,Sn,#0 uint32_t vcgtzs_f32(float32_t a)
+ case ARM64_INTRIN_VCLEZS_F32: // FCMLE Sd,Sn,#0 uint32_t vclezs_f32(float32_t a)
+ case ARM64_INTRIN_VCLTZS_F32: // FCMLT Sd,Sn,#0 uint32_t vcltzs_f32(float32_t a)
+ case ARM64_INTRIN_VCVT_U64_F32: // FCVTZU Xd,Sn uint64x1_t vcvt_u64_f32(float32x1_t a)
+ case ARM64_INTRIN_VCVTAS_S32_F32: // FCVTAS Sd,Sn int32_t vcvtas_s32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTAS_S32_F32: // FCVTAS Wd,Sn int32_t vcvtas_s32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTAS_U32_F32: // FCVTAU Sd,Sn uint32_t vcvtas_u32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTAS_U32_F32: // FCVTAU Wd,Sn uint32_t vcvtas_u32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTH_BF16_F32: // BFCVT Hd,Sn bfloat16_t vcvth_bf16_f32(float32_t a)
+ case ARM64_INTRIN_VCVTMS_S32_F32: // FCVTMS Sd,Sn int32_t vcvtms_s32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTMS_S32_F32: // FCVTMS Wd,Sn int32_t vcvtms_s32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTMS_U32_F32: // FCVTMU Sd,Sn uint32_t vcvtms_u32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTMS_U32_F32: // FCVTMU Wd,Sn uint32_t vcvtms_u32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTNS_S32_F32: // FCVTNS Sd,Sn int32_t vcvtns_s32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTNS_S32_F32: // FCVTNS Wd,Sn int32_t vcvtns_s32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTNS_U32_F32: // FCVTNU Sd,Sn uint32_t vcvtns_u32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTNS_U32_F32: // FCVTNU Wd,Sn uint32_t vcvtns_u32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTPS_S32_F32: // FCVTPS Sd,Sn int32_t vcvtps_s32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTPS_S32_F32: // FCVTPS Wd,Sn int32_t vcvtps_s32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTPS_U32_F32: // FCVTPU Sd,Sn uint32_t vcvtps_u32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTPS_U32_F32: // FCVTPU Wd,Sn uint32_t vcvtps_u32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTS_S32_F32: // FCVTZS Sd,Sn int32_t vcvts_s32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTS_S32_F32: // FCVTZS Wd,Sn int32_t vcvts_s32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTS_U32_F32: // FCVTZU Sd,Sn uint32_t vcvts_u32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTS_U32_F32: // FCVTZU Wd,Sn uint32_t vcvts_u32_f32(float32_t a)
+ case ARM64_INTRIN_VDUP_N_F32: // DUP Vd.2S,rn float32x2_t vdup_n_f32(float32_t value)
+ case ARM64_INTRIN_VDUPQ_N_F32: // DUP Vd.4S,rn float32x4_t vdupq_n_f32(float32_t value)
+ case ARM64_INTRIN_VMAXNMV_F16: // FMAXNMP Hd,Vn.2H float16_t vmaxnmv_f16(float16x2_t a)
+ case ARM64_INTRIN_VMINNMV_F16: // FMINNMP Hd,Vn.2H float16_t vminnmv_f16(float16x2_t a)
+ case ARM64_INTRIN_VMOV_N_F32: // DUP Vd.2S,rn float32x2_t vmov_n_f32(float32_t value)
+ case ARM64_INTRIN_VMOVQ_N_F32: // DUP Vd.4S,rn float32x4_t vmovq_n_f32(float32_t value)
+ case ARM64_INTRIN_VRECPES_F32: // FRECPE Sd,Sn float32_t vrecpes_f32(float32_t a)
+ case ARM64_INTRIN_VRECPXS_F32: // FRECPX Sd,Sn float32_t vrecpxs_f32(float32_t a)
+ case ARM64_INTRIN_VRND32X_F32: // FRINT32X Sd,Sn float32x1_t vrnd32x_f32(float32x1_t a)
+ case ARM64_INTRIN_VRND32Z_F32: // FRINT32Z Sd,Sn float32x1_t vrnd32z_f32(float32x1_t a)
+ case ARM64_INTRIN_VRND64X_F32: // FRINT64X Sd,Sn float32x1_t vrnd64x_f32(float32x1_t a)
+ case ARM64_INTRIN_VRND64Z_F32: // FRINT64Z Sd,Sn float64x1_t vrnd64z_f32(float32x1_t a)
+ case ARM64_INTRIN_VRNDA_F32: // FRINTA Sd,Sn float32x1_t vrnda_f32(float32x1_t a)
+ case ARM64_INTRIN_VRNDI_F32: // FRINTI Sd,Sn float32x1_t vrndi_f32(float32x1_t a)
+ case ARM64_INTRIN_VRNDM_F32: // FRINTM Sd,Sn float32x1_t vrndm_f32(float32x1_t a)
+ case ARM64_INTRIN_VRNDNS_F32: // FRINTN Sd,Sn float32_t vrndns_f32(float32_t a)
+ case ARM64_INTRIN_VRNDP_F32: // FRINTP Sd,Sn float32x1_t vrndp_f32(float32x1_t a)
+ case ARM64_INTRIN_VRNDX_F32: // FRINTX Sd,Sn float32x1_t vrndx_f32(float32x1_t a)
+ case ARM64_INTRIN_VRSQRTES_F32: // FRSQRTE Sd,Sn float32_t vrsqrtes_f32(float32_t a)
+ return {NameAndType(Type::FloatType(4))};
+ case ARM64_INTRIN_VMULS_LANEQ_F32: // FMUL Sd,Sn,Vm.S[lane] float32_t vmuls_laneq_f32(float32_t a, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULXS_LANEQ_F32: // FMULX Sd,Sn,Vm.S[lane] float32_t vmulxs_laneq_f32(float32_t a, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_F32: // MOV Vd.S[lane],Rn float32x4_t vsetq_lane_f32(float32_t a, float32x4_t v, const int lane)
+ return {NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VABDS_F32: // FABD Sd,Sn,Sm float32_t vabds_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCAGES_F32: // FACGE Sd,Sn,Sm uint32_t vcages_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCAGTS_F32: // FACGT Sd,Sn,Sm uint32_t vcagts_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCALES_F32: // FACGE Sd,Sm,Sn uint32_t vcales_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCALTS_F32: // FACGT Sd,Sm,Sn uint32_t vcalts_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCEQS_F32: // FCMEQ Sd,Sn,Sm uint32_t vceqs_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCGES_F32: // FCMGE Sd,Sn,Sm uint32_t vcges_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCGTS_F32: // FCMGT Sd,Sn,Sm uint32_t vcgts_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCLES_F32: // FCMGE Sd,Sm,Sn uint32_t vcles_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCLTS_F32: // FCMGT Sd,Sm,Sn uint32_t vclts_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VMAX_F32: // FMAX Sd,Sn,Sm float32x1_t vmax_f32(float32x1_t a, float32x1_t b)
+ case ARM64_INTRIN_VMAXNM_F32: // FMAXNM Sd,Sn,Sm float32x1_t vmaxnm_f32(float32x1_t a, float32x1_t b)
+ case ARM64_INTRIN_VMULXS_F32: // FMULX Sd,Sn,Sm float32_t vmulxs_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VRECPSS_F32: // FRECPS Sd,Sn,Sm float32_t vrecpss_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VRSQRTSS_F32: // FRSQRTS Sd,Sn,Sm float32_t vrsqrtss_f32(float32_t a, float32_t b)
+ return {NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(4))};
+ case ARM64_INTRIN_VFMAS_LANEQ_F32: // FMLA Sd,Sn,Vm.S[lane] float32_t vfmas_laneq_f32(float32_t a, float32_t b, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VFMSS_LANEQ_F32: // FMLS Sd,Sn,Vm.S[lane] float32_t vfmss_laneq_f32(float32_t a, float32_t b, float32x4_t v, const int lane)
+ return {NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VFMAS_LANE_F32: // FMLA Sd,Sn,Vm.S[lane] float32_t vfmas_lane_f32(float32_t a, float32_t b, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VFMSS_LANE_F32: // FMLS Sd,Sn,Vm.S[lane] float32_t vfmss_lane_f32(float32_t a, float32_t b, float32x2_t v, const int lane)
+ return {NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VMULS_LANE_F32: // FMUL Sd,Sn,Vm.S[lane] float32_t vmuls_lane_f32(float32_t a, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULXS_LANE_F32: // FMULX Sd,Sn,Vm.S[lane] float32_t vmulxs_lane_f32(float32_t a, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_F32: // MOV Vd.S[lane],Rn float32x2_t vset_lane_f32(float32_t a, float32x2_t v, const int lane)
+ return {NameAndType(Type::FloatType(4)), NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VCVTAS_N_S32_F32: // FCVTAS Wd,Sn,#n int32_t vcvtas_n_s32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTAS_N_U32_F32: // FCVTAU Wd,Sn,#n uint32_t vcvtas_n_u32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTMS_N_S32_F32: // FCVTMS Wd,Sn,#n int32_t vcvtms_n_s32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTMS_N_U32_F32: // FCVTMU Wd,Sn,#n uint32_t vcvtms_n_u32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTPS_N_S32_F32: // FCVTPS Wd,Sn,#n int32_t vcvtps_n_s32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTPS_N_U32_F32: // FCVTPU Wd,Sn,#n uint32_t vcvtps_n_u32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTS_N_S32_F32: // FCVTZS Sd,Sn,#n int32_t vcvts_n_s32_f32(float32_t a, const int n)
+ // case ARM64_INTRIN_VCVTS_N_S32_F32: // FCVTZS Wd,Sn,#n int32_t vcvts_n_s32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTS_N_U32_F32: // FCVTZU Sd,Sn,#n uint32_t vcvts_n_u32_f32(float32_t a, const int n)
+ // case ARM64_INTRIN_VCVTS_N_U32_F32: // FCVTZU Wd,Sn,#n uint32_t vcvts_n_u32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTS_N_U64_F32: // FCVTZU Xd,Sn,#n uint64_t vcvts_n_u64_f32(float32_t a, const int n)
+ return {NameAndType(Type::FloatType(4)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VABS_F16: // FABS Vd.4H,Vn.4H float16x4_t vabs_f16(float16x4_t a)
+ case ARM64_INTRIN_VABS_F32: // FABS Vd.2S,Vn.2S float32x2_t vabs_f32(float32x2_t a)
+ case ARM64_INTRIN_VABS_F64: // FABS Dd,Dn float64x1_t vabs_f64(float64x1_t a)
+ case ARM64_INTRIN_VADDV_F32: // FADDP Sd,Vn.2S float32_t vaddv_f32(float32x2_t a)
+ case ARM64_INTRIN_VCEQZ_F16: // FCMEQ Vd.4H,Vn.4H,#0 uint16x4_t vceqz_f16(float16x4_t a)
+ case ARM64_INTRIN_VCEQZ_F32: // FCMEQ Vd.2S,Vn.2S,#0 uint32x2_t vceqz_f32(float32x2_t a)
+ case ARM64_INTRIN_VCEQZ_F64: // FCMEQ Dd,Dn,#0 uint64x1_t vceqz_f64(float64x1_t a)
+ case ARM64_INTRIN_VCEQZD_F64: // FCMEQ Dd,Dn,#0 uint64_t vceqzd_f64(float64_t a)
+ case ARM64_INTRIN_VCGEZ_F16: // FCMGE Vd.4H,Vn.4H,#0 uint16x4_t vcgez_f16(float16x4_t a)
+ case ARM64_INTRIN_VCGEZ_F32: // FCMGE Vd.2S,Vn.2S,#0 uint32x2_t vcgez_f32(float32x2_t a)
+ case ARM64_INTRIN_VCGEZ_F64: // FCMGE Dd,Dn,#0 uint64x1_t vcgez_f64(float64x1_t a)
+ case ARM64_INTRIN_VCGEZD_F64: // FCMGE Dd,Dn,#0 uint64_t vcgezd_f64(float64_t a)
+ case ARM64_INTRIN_VCGTZ_F16: // FCMGT Vd.4H,Vn.4H,#0 uint16x4_t vcgtz_f16(float16x4_t a)
+ case ARM64_INTRIN_VCGTZ_F32: // FCMGT Vd.2S,Vn.2S,#0 uint32x2_t vcgtz_f32(float32x2_t a)
+ case ARM64_INTRIN_VCGTZ_F64: // FCMGT Dd,Dn,#0 uint64x1_t vcgtz_f64(float64x1_t a)
+ case ARM64_INTRIN_VCGTZD_F64: // FCMGT Dd,Dn,#0 uint64_t vcgtzd_f64(float64_t a)
+ case ARM64_INTRIN_VCLEZ_F16: // FCMLE Vd.4H,Vn.4H,#0 uint16x4_t vclez_f16(float16x4_t a)
+ case ARM64_INTRIN_VCLEZ_F32: // CMLE Vd.2S,Vn.2S,#0 uint32x2_t vclez_f32(float32x2_t a)
+ case ARM64_INTRIN_VCLEZ_F64: // FCMLE Dd,Dn,#0 uint64x1_t vclez_f64(float64x1_t a)
+ case ARM64_INTRIN_VCLEZD_F64: // FCMLE Dd,Dn,#0 uint64_t vclezd_f64(float64_t a)
+ case ARM64_INTRIN_VCLTZ_F16: // FCMLT Vd.4H,Vn.4H,#0 uint16x4_t vcltz_f16(float16x4_t a)
+ case ARM64_INTRIN_VCLTZ_F32: // FCMLT Vd.2S,Vn.2S,#0 uint32x2_t vcltz_f32(float32x2_t a)
+ case ARM64_INTRIN_VCLTZ_F64: // FCMLT Dd,Dn,#0 uint64x1_t vcltz_f64(float64x1_t a)
+ case ARM64_INTRIN_VCLTZD_F64: // FCMLT Dd,Dn,#0 uint64_t vcltzd_f64(float64_t a)
+ case ARM64_INTRIN_VCVT_F32_BF16: // SHLL Vd.4S,Vn.8H,#16 float32x4_t vcvt_f32_bf16(bfloat16x4_t a)
+ case ARM64_INTRIN_VCVT_F32_F16: // FCVTL Vd.4S,Vn.4H float32x4_t vcvt_f32_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVT_F64_F32: // FCVTL Vd.2D,Vn.2S float64x2_t vcvt_f64_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVT_S16_F16: // FCVTZS Vd.4H,Vn.4H int16x4_t vcvt_s16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVT_S32_F32: // FCVTZS Vd.2S,Vn.2S int32x2_t vcvt_s32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVT_S32_F64: // FCVTZS Wd,Dn int32x1_t vcvt_s32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVT_S32_F64: // FCVTZS Wd,Sn int32x1_t vcvt_s32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVT_S64_F64: // FCVTZS Dd,Dn int64x1_t vcvt_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVT_S64_F64: // FCVTZS Xd,Dn int64x1_t vcvt_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVT_S64_F64: // FCVTZS Xd,Sn int64x1_t vcvt_s64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVT_U16_F16: // FCVTZS Vd.4H,Vn.4H uint16x4_t vcvt_u16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVT_U32_F32: // FCVTZU Vd.2S,Vn.2S uint32x2_t vcvt_u32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVT_U32_F64: // FCVTZU Wd,Dn uint32x1_t vcvt_u32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVT_U32_F64: // FCVTZU Wd,Sn uint32x1_t vcvt_u32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVT_U64_F64: // FCVTZU Xd,Dn uint64x1_t vcvt_u64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVT_U64_F64: // FCVTZU Xd,Sn uint64x1_t vcvt_u64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTA_S16_F16: // FCVTAS Vd.4H,Vn.4H int16x4_t vcvta_s16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTA_S32_F32: // FCVTAS Vd.2S,Vn.2S int32x2_t vcvta_s32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTA_S32_F64: // FCVTAS Wd,Dn int32x1_t vcvta_s32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTA_S32_F64: // FCVTAS Wd,Sn int32x1_t vcvta_s32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTA_S64_F64: // FCVTAS Dd,Dn int64x1_t vcvta_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTA_S64_F64: // FCVTAS Xd,Dn int64x1_t vcvta_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTA_S64_F64: // FCVTAS Xd,Sn int64x1_t vcvta_s64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTA_U16_F16: // FCVTAU Vd.4H,Vn.4H uint16x4_t vcvta_u16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTA_U32_F32: // FCVTAU Vd.2S,Vn.2S uint32x2_t vcvta_u32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTA_U32_F64: // FCVTAU Wd,Dn uint32x1_t vcvta_u32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTA_U32_F64: // FCVTAU Wd,Sn uint32x1_t vcvta_u32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTA_U64_F64: // FCVTAU Dd,Dn uint64x1_t vcvta_u64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTA_U64_F64: // FCVTAU Xd,Dn uint64x1_t vcvta_u64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTA_U64_F64: // FCVTAU Xd,Sn uint64x1_t vcvta_u64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTAD_S32_F64: // FCVTAS Wd,Dn int32_t vcvtad_s32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTAD_S32_F64: // FCVTAS Wd,Sn int32_t vcvtad_s32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTAD_S64_F64: // FCVTAS Dd,Dn int64_t vcvtad_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTAD_S64_F64: // FCVTAS Xd,Dn int64_t vcvtad_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTAD_S64_F64: // FCVTAS Xd,Sn int64_t vcvtad_s64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTAD_U32_F64: // FCVTAU Wd,Dn uint32_t vcvtad_u32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTAD_U32_F64: // FCVTAU Wd,Sn uint32_t vcvtad_u32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTAD_U64_F64: // FCVTAU Dd,Dn uint64_t vcvtad_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTAD_U64_F64: // FCVTAU Xd,Dn uint64_t vcvtad_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTAD_U64_F64: // FCVTAU Xd,Sn uint64_t vcvtad_u64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTD_S32_F64: // FCVTZS Wd,Dn int32_t vcvtd_s32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTD_S32_F64: // FCVTZS Wd,Sn int32_t vcvtd_s32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTD_S64_F64: // FCVTZS Dd,Dn int64_t vcvtd_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTD_S64_F64: // FCVTZS Xd,Dn int64_t vcvtd_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTD_S64_F64: // FCVTZS Xd,Sn int64_t vcvtd_s64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTD_U32_F64: // FCVTZU Wd,Dn uint32_t vcvtd_u32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTD_U32_F64: // FCVTZU Wd,Sn uint32_t vcvtd_u32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTD_U64_F64: // FCVTZU Dd,Dn uint64_t vcvtd_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTD_U64_F64: // FCVTZU Xd,Dn uint64_t vcvtd_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTD_U64_F64: // FCVTZU Xd,Sn uint64_t vcvtd_u64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTM_S16_F16: // FCVTMS Vd.4H,Vn.4H int16x4_t vcvtm_s16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTM_S32_F32: // FCVTMS Vd.2S,Vn.2S int32x2_t vcvtm_s32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTM_S32_F64: // FCVTMS Wd,Dn int32x1_t vcvtm_s32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTM_S32_F64: // FCVTMS Wd,Sn int32x1_t vcvtm_s32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTM_S64_F64: // FCVTMS Dd,Dn int64x1_t vcvtm_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTM_S64_F64: // FCVTMS Xd,Dn int64x1_t vcvtm_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTM_S64_F64: // FCVTMS Xd,Sn int64x1_t vcvtm_s64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTM_U16_F16: // FCVTMU Vd.4H,Vn.4H uint16x4_t vcvtm_u16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTM_U32_F32: // FCVTMU Vd.2S,Vn.2S uint32x2_t vcvtm_u32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTM_U32_F64: // FCVTMU Wd,Dn uint32x1_t vcvtm_u32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTM_U32_F64: // FCVTMU Wd,Sn uint32x1_t vcvtm_u32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTM_U64_F64: // FCVTMU Dd,Dn uint64x1_t vcvtm_u64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTM_U64_F64: // FCVTMU Xd,Dn uint64x1_t vcvtm_u64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTM_U64_F64: // FCVTMU Xd,Sn uint64x1_t vcvtm_u64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTMD_S32_F64: // FCVTMS Wd,Dn int32_t vcvtmd_s32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTMD_S32_F64: // FCVTMS Wd,Sn int32_t vcvtmd_s32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTMD_S64_F64: // FCVTMS Dd,Dn int64_t vcvtmd_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTMD_S64_F64: // FCVTMS Xd,Dn int64_t vcvtmd_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTMD_S64_F64: // FCVTMS Xd,Sn int64_t vcvtmd_s64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTMD_U32_F64: // FCVTMU Wd,Dn uint32_t vcvtmd_u32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTMD_U32_F64: // FCVTMU Wd,Sn uint32_t vcvtmd_u32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTMD_U64_F64: // FCVTMU Dd,Dn uint64_t vcvtmd_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTMD_U64_F64: // FCVTMU Xd,Dn uint64_t vcvtmd_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTMD_U64_F64: // FCVTMU Xd,Sn uint64_t vcvtmd_u64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTN_S16_F16: // FCVTNS Vd.4H,Vn.4H int16x4_t vcvtn_s16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTN_S32_F32: // FCVTNS Vd.2S,Vn.2S int32x2_t vcvtn_s32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTN_S32_F64: // FCVTNS Wd,Dn int32x1_t vcvtn_s32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTN_S32_F64: // FCVTNS Wd,Sn int32x1_t vcvtn_s32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTN_S64_F64: // FCVTNS Dd,Dn int64x1_t vcvtn_s64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTN_U16_F16: // FCVTNU Vd.4H,Vn.4H uint16x4_t vcvtn_u16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTN_U32_F32: // FCVTNU Vd.2S,Vn.2S uint32x2_t vcvtn_u32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTN_U32_F64: // FCVTNU Wd,Dn uint32x1_t vcvtn_u32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTN_U32_F64: // FCVTNU Wd,Sn uint32x1_t vcvtn_u32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTN_U64_F64: // FCVTNU Dd,Dn uint64x1_t vcvtn_u64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTND_S32_F64: // FCVTNS Wd,Dn int32_t vcvtnd_s32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTND_S32_F64: // FCVTNS Wd,Sn int32_t vcvtnd_s32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTND_S64_F64: // FCVTNS Dd,Dn int64_t vcvtnd_s64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTND_U32_F64: // FCVTNU Wd,Dn uint32_t vcvtnd_u32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTND_U32_F64: // FCVTNU Wd,Sn uint32_t vcvtnd_u32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTND_U64_F64: // FCVTNU Dd,Dn uint64_t vcvtnd_u64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTP_S16_F16: // FCVTPS Vd.4H,Vn.4H int16x4_t vcvtp_s16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTP_S32_F32: // FCVTPS Vd.2S,Vn.2S int32x2_t vcvtp_s32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTP_S32_F64: // FCVTPS Wd,Dn int32x1_t vcvtp_s32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTP_S32_F64: // FCVTPS Wd,Sn int32x1_t vcvtp_s32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTP_S64_F64: // FCVTPS Dd,Dn int64x1_t vcvtp_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTP_S64_F64: // FCVTPS Xd,Dn int64x1_t vcvtp_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTP_S64_F64: // FCVTPS Xd,Sn int64x1_t vcvtp_s64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTP_U16_F16: // FCVTPU Vd.4H,Vn.4H uint16x4_t vcvtp_u16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTP_U32_F32: // FCVTPU Vd.2S,Vn.2S uint32x2_t vcvtp_u32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTP_U32_F64: // FCVTPU Wd,Dn uint32x1_t vcvtp_u32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTP_U32_F64: // FCVTPU Wd,Sn uint32x1_t vcvtp_u32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTP_U64_F64: // FCVTPU Xd,Dn uint64x1_t vcvtp_u64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTP_U64_F64: // FCVTPU Xd,Sn uint64x1_t vcvtp_u64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTPD_S32_F64: // FCVTPS Wd,Dn int32_t vcvtpd_s32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTPD_S32_F64: // FCVTPS Wd,Sn int32_t vcvtpd_s32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTPD_S64_F64: // FCVTPS Dd,Dn int64_t vcvtpd_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTPD_S64_F64: // FCVTPS Xd,Dn int64_t vcvtpd_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTPD_S64_F64: // FCVTPS Xd,Sn int64_t vcvtpd_s64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTPD_U32_F64: // FCVTPU Wd,Dn uint32_t vcvtpd_u32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTPD_U32_F64: // FCVTPU Wd,Sn uint32_t vcvtpd_u32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTPD_U64_F64: // FCVTPU Dd,Dn uint64_t vcvtpd_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTPD_U64_F64: // FCVTPU Xd,Dn uint64_t vcvtpd_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTPD_U64_F64: // FCVTPU Xd,Sn uint64_t vcvtpd_u64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTXD_F32_F64: // FCVTXN Sd,Dn float32_t vcvtxd_f32_f64(float64_t a)
+ case ARM64_INTRIN_VDUP_N_F64: // INS Vd.D[0],rn float64x1_t vdup_n_f64(float64_t value)
+ case ARM64_INTRIN_VDUPQ_N_F64: // DUP Vd.2D,rn float64x2_t vdupq_n_f64(float64_t value)
+ // case ARM64_INTRIN_VMAXNMV_F16: // FMAXNMP Hd,Vn.4H float16_t vmaxnmv_f16(float16x4_t a)
+ case ARM64_INTRIN_VMAXNMV_F32: // FMAXNMP Sd,Vn.2S float32_t vmaxnmv_f32(float32x2_t a)
+ // case ARM64_INTRIN_VMAXNMVQ_F16: // FMAXNMV Hd,Hn.4H float16_t vmaxnmvq_f16(float16x4_t a)
+ case ARM64_INTRIN_VMAXV_F16: // FMAXP Hd,Vn.4H float16_t vmaxv_f16(float16x4_t a)
+ case ARM64_INTRIN_VMAXV_F32: // FMAXP Sd,Vn.2S float32_t vmaxv_f32(float32x2_t a)
+ // case ARM64_INTRIN_VMAXVQ_F16: // FMAXV Hd,Hn.4H float16_t vmaxvq_f16(float16x4_t a)
+ // case ARM64_INTRIN_VMINNMV_F16: // FMINNMP Hd,Vn.4H float16_t vminnmv_f16(float16x4_t a)
+ // case ARM64_INTRIN_VMINNMV_F16: // FMINNMV Hd,Vn.4H float16_t vminnmv_f16(float16x4_t a)
+ case ARM64_INTRIN_VMINNMV_F32: // FMINNMP Sd,Vn.2S float32_t vminnmv_f32(float32x2_t a)
+ case ARM64_INTRIN_VMINV_F16: // FMINP Hd,Vn.4H float16_t vminv_f16(float16x4_t a)
+ // case ARM64_INTRIN_VMINV_F16: // FMINV Hd,Vn.4H float16_t vminv_f16(float16x4_t a)
+ case ARM64_INTRIN_VMINV_F32: // FMINP Sd,Vn.2S float32_t vminv_f32(float32x2_t a)
+ // case ARM64_INTRIN_VMINV_F32: // FMINV Sd,Vn.2S float32_t vminv_f32(float32x2_t a)
+ case ARM64_INTRIN_VMOV_N_F64: // DUP Vd.1D,rn float64x1_t vmov_n_f64(float64_t value)
+ case ARM64_INTRIN_VMOVQ_N_F64: // DUP Vd.2D,rn float64x2_t vmovq_n_f64(float64_t value)
+ case ARM64_INTRIN_VNEG_F16: // FNEG Vd.4H,Vn.4H float16x4_t vneg_f16(float16x4_t a)
+ case ARM64_INTRIN_VNEG_F32: // FNEG Vd.2S,Vn.2S float32x2_t vneg_f32(float32x2_t a)
+ case ARM64_INTRIN_VNEG_F64: // FNEG Dd,Dn float64x1_t vneg_f64(float64x1_t a)
+ case ARM64_INTRIN_VPADDS_F32: // FADDP Sd,Vn.2S float32_t vpadds_f32(float32x2_t a)
+ case ARM64_INTRIN_VPMAXNMS_F32: // FMAXNMP Sd,Vn.2S float32_t vpmaxnms_f32(float32x2_t a)
+ case ARM64_INTRIN_VPMAXS_F32: // FMAXP Sd,Vn.2S float32_t vpmaxs_f32(float32x2_t a)
+ case ARM64_INTRIN_VPMINNMS_F32: // FMINNMP Sd,Vn.2S float32_t vpminnms_f32(float32x2_t a)
+ case ARM64_INTRIN_VPMINS_F32: // FMINP Sd,Vn.2S float32_t vpmins_f32(float32x2_t a)
+ case ARM64_INTRIN_VRECPE_F16: // FRECPE Vd.4H,Vn.4H float16x4_t vrecpe_f16(float16x4_t a)
+ case ARM64_INTRIN_VRECPE_F32: // FRECPE Vd.2S,Vn.2S float32x2_t vrecpe_f32(float32x2_t a)
+ case ARM64_INTRIN_VRECPE_F64: // FRECPE Dd,Dn float64x1_t vrecpe_f64(float64x1_t a)
+ case ARM64_INTRIN_VRECPED_F64: // FRECPE Dd,Dn float64_t vrecped_f64(float64_t a)
+ case ARM64_INTRIN_VRECPXD_F64: // FRECPX Dd,Dn float64_t vrecpxd_f64(float64_t a)
+ case ARM64_INTRIN_VREV64_F16: // REV64 Vd.4H,Vn.4H float16x4_t vrev64_f16(float16x4_t vec)
+ case ARM64_INTRIN_VREV64_F32: // REV64 Vd.2S,Vn.2S float32x2_t vrev64_f32(float32x2_t vec)
+ // case ARM64_INTRIN_VRND32X_F32: // FRINT32X Vd.2S,Vn.2S float32x2_t vrnd32x_f32(float32x2_t a)
+ case ARM64_INTRIN_VRND32X_F64: // FRINT32X Dd,Dn float64x1_t vrnd32x_f64(float64x1_t a)
+ // case ARM64_INTRIN_VRND32Z_F32: // FRINT32Z Vd.2S,Vn.2S float32x2_t vrnd32z_f32(float32x2_t a)
+ case ARM64_INTRIN_VRND32Z_F64: // FRINT32Z Dd,Dn float64x1_t vrnd32z_f64(float64x1_t a)
+ // case ARM64_INTRIN_VRND64X_F32: // FRINT64X Vd.2S,Vn.2S float32x2_t vrnd64x_f32(float32x2_t a)
+ case ARM64_INTRIN_VRND64X_F64: // FRINT64X Dd,Dn float64x1_t vrnd64x_f64(float64x1_t a)
+ // case ARM64_INTRIN_VRND64Z_F32: // FRINT64Z Vd.2S,Vn.2S float32x2_t vrnd64z_f32(float32x2_t a)
+ case ARM64_INTRIN_VRND64Z_F64: // FRINT64Z Dd,Dn float64x1_t vrnd64z_f64(float64x1_t a)
+ case ARM64_INTRIN_VRND_F16: // FRINTZ Vd.4H,Vn.4H float16x4_t vrnd_f16(float16x4_t a)
+ case ARM64_INTRIN_VRND_F32: // FRINTZ Vd.2S,Vn.2S float32x2_t vrnd_f32(float32x2_t a)
+ case ARM64_INTRIN_VRND_F64: // FRINTZ Dd,Dn float64x1_t vrnd_f64(float64x1_t a)
+ case ARM64_INTRIN_VRNDA_F16: // FRINTA Vd.4H,Vn.4H float16x4_t vrnda_f16(float16x4_t a)
+ // case ARM64_INTRIN_VRNDA_F32: // FRINTA Vd.2S,Vn.2S float32x2_t vrnda_f32(float32x2_t a)
+ case ARM64_INTRIN_VRNDA_F64: // FRINTA Dd,Dn float64x1_t vrnda_f64(float64x1_t a)
+ case ARM64_INTRIN_VRNDI_F16: // FRINTI Vd.4H,Vn.4H float16x4_t vrndi_f16(float16x4_t a)
+ // case ARM64_INTRIN_VRNDI_F32: // FRINTI Vd.2S,Vn.2S float32x2_t vrndi_f32(float32x2_t a)
+ case ARM64_INTRIN_VRNDI_F64: // FRINTI Dd,Dn float64x1_t vrndi_f64(float64x1_t a)
+ case ARM64_INTRIN_VRNDM_F16: // FRINTM Vd.4H,Vn.4H float16x4_t vrndm_f16(float16x4_t a)
+ // case ARM64_INTRIN_VRNDM_F32: // FRINTM Vd.2S,Vn.2S float32x2_t vrndm_f32(float32x2_t a)
+ case ARM64_INTRIN_VRNDM_F64: // FRINTM Dd,Dn float64x1_t vrndm_f64(float64x1_t a)
+ case ARM64_INTRIN_VRNDN_F16: // FRINTN Vd.4H,Vn.4H float16x4_t vrndn_f16(float16x4_t a)
+ case ARM64_INTRIN_VRNDN_F32: // FRINTN Vd.2S,Vn.2S float32x2_t vrndn_f32(float32x2_t a)
+ case ARM64_INTRIN_VRNDN_F64: // FRINTN Dd,Dn float64x1_t vrndn_f64(float64x1_t a)
+ case ARM64_INTRIN_VRNDP_F16: // FRINTP Vd.4H,Vn.4H float16x4_t vrndp_f16(float16x4_t a)
+ // case ARM64_INTRIN_VRNDP_F32: // FRINTP Vd.2S,Vn.2S float32x2_t vrndp_f32(float32x2_t a)
+ case ARM64_INTRIN_VRNDP_F64: // FRINTP Dd,Dn float64x1_t vrndp_f64(float64x1_t a)
+ case ARM64_INTRIN_VRNDX_F16: // FRINTX Vd.4H,Vn.4H float16x4_t vrndx_f16(float16x4_t a)
+ // case ARM64_INTRIN_VRNDX_F32: // FRINTX Vd.2S,Vn.2S float32x2_t vrndx_f32(float32x2_t a)
+ case ARM64_INTRIN_VRNDX_F64: // FRINTX Dd,Dn float64x1_t vrndx_f64(float64x1_t a)
+ case ARM64_INTRIN_VRSQRTE_F16: // FRSQRTE Vd.4H,Vn.4H float16x4_t vrsqrte_f16(float16x4_t a)
+ case ARM64_INTRIN_VRSQRTE_F32: // FRSQRTE Vd.2S,Vn.2S float32x2_t vrsqrte_f32(float32x2_t a)
+ case ARM64_INTRIN_VRSQRTE_F64: // FRSQRTE Dd,Dn float64x1_t vrsqrte_f64(float64x1_t a)
+ case ARM64_INTRIN_VRSQRTED_F64: // FRSQRTE Dd,Dn float64_t vrsqrted_f64(float64_t a)
+ case ARM64_INTRIN_VSQRT_F16: // FSQRT Vd.4H,Vn.4H float16x4_t vsqrt_f16(float16x4_t a)
+ case ARM64_INTRIN_VSQRT_F32: // FSQRT Vd.2S,Vn.2S float32x2_t vsqrt_f32(float32x2_t a)
+ case ARM64_INTRIN_VSQRT_F64: // FSQRT Dd,Dn float64x1_t vsqrt_f64(float64x1_t a)
+ return {NameAndType(Type::FloatType(8))};
+ case ARM64_INTRIN_VCVT_HIGH_F16_F32: // FCVTN2 Vd.8H,Vn.4S float16x8_t vcvt_high_f16_f32(float16x4_t r, float32x4_t a)
+ case ARM64_INTRIN_VCVT_HIGH_F32_F64: // FCVTN2 Vd.4S,Vn.2D float32x4_t vcvt_high_f32_f64(float32x2_t r, float64x2_t a)
+ case ARM64_INTRIN_VCVTX_HIGH_F32_F64: // FCVTXN2 Vd.4S,Vn.2D float32x4_t vcvtx_high_f32_f64(float32x2_t r, float64x2_t a)
+ return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(16))};
+ case ARM64_INTRIN_VMUL_LANEQ_F16: // FMUL Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vmul_laneq_f16(float16x4_t a, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANEQ_F32: // FMUL Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vmul_laneq_f32(float32x2_t a, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANEQ_F64: // FMUL Dd,Dn,Vm.D[lane] float64x1_t vmul_laneq_f64(float64x1_t a, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VMULD_LANEQ_F64: // FMUL Dd,Dn,Vm.D[lane] float64_t vmuld_laneq_f64(float64_t a, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VMULX_LANEQ_F16: // FMULX Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vmulx_laneq_f16(float16x4_t a, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULX_LANEQ_F32: // FMULX Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vmulx_laneq_f32(float32x2_t a, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULX_LANEQ_F64: // FMULX Dd,Dn,Vm.D[lane] float64x1_t vmulx_laneq_f64(float64x1_t a, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VMULXD_LANEQ_F64: // FMULX Dd,Dn,Vm.D[lane] float64_t vmulxd_laneq_f64(float64_t a, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_F64: // MOV Vd.D[lane],Rn float64x2_t vsetq_lane_f64(float64_t a, float64x2_t v, const int lane)
+ return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VMUL_N_F16: // FMUL Vd.4H,Vn.4H,Vm.H[0] float16x4_t vmul_n_f16(float16x4_t a, float16_t n)
+ case ARM64_INTRIN_VMULX_N_F16: // FMULX Vd.4H,Vn.4H,Vm.H[0] float16x4_t vmulx_n_f16(float16x4_t a, float16_t n)
+ return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(2))};
+ case ARM64_INTRIN_VMUL_N_F32: // FMUL Vd.2S,Vn.2S,Vm.S[0] float32x2_t vmul_n_f32(float32x2_t a, float32_t b)
+ return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(4))};
+ case ARM64_INTRIN_VABD_F16: // FABD Vd.4H,Vn.4H,Vm.4H float16x4_t vabd_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VABD_F32: // FABD Vd.2S,Vn.2S,Vm.2S float32x2_t vabd_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VABD_F64: // FABD Dd,Dn,Dm float64x1_t vabd_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VABDD_F64: // FABD Dd,Dn,Dm float64_t vabdd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VADD_F16: // FADD Vd.4H,Vn.4H,Vm.4H float16x4_t vadd_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VADD_F32: // FADD Vd.2S,Vn.2S,Vm.2S float32x2_t vadd_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VADD_F64: // FADD Dd,Dn,Dm float64x1_t vadd_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCADD_ROT270_F16: // FCADD Vd.4H,Vn.4H,Vm.4H,#270 float16x4_t vcadd_rot270_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCADD_ROT270_F32: // FCADD Vd.2S,Vn.2S,Vm.2S,#270 float32x2_t vcadd_rot270_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCADD_ROT90_F16: // FCADD Vd.4H,Vn.4H,Vm.4H,#90 float16x4_t vcadd_rot90_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCADD_ROT90_F32: // FCADD Vd.2S,Vn.2S,Vm.2S,#90 float32x2_t vcadd_rot90_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCAGE_F16: // FACGE Vd.4H,Vn.4H,Vm.4H uint16x4_t vcage_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCAGE_F32: // FACGE Vd.2S,Vn.2S,Vm.2S uint32x2_t vcage_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCAGE_F64: // FACGE Dd,Dn,Dm uint64x1_t vcage_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCAGED_F64: // FACGE Dd,Dn,Dm uint64_t vcaged_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCAGT_F16: // FACGT Vd.4H,Vn.4H,Vm.4H uint16x4_t vcagt_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCAGT_F32: // FACGT Vd.2S,Vn.2S,Vm.2S uint32x2_t vcagt_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCAGT_F64: // FACGT Dd,Dn,Dm uint64x1_t vcagt_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCAGTD_F64: // FACGT Dd,Dn,Dm uint64_t vcagtd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCALE_F16: // FACGE Vd.4H,Vn.4H,Vm.4H uint16x4_t vcale_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCALE_F32: // FACGE Vd.2S,Vm.2S,Vn.2S uint32x2_t vcale_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCALE_F64: // FACGE Dd,Dm,Dn uint64x1_t vcale_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCALED_F64: // FACGE Dd,Dm,Dn uint64_t vcaled_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCALT_F16: // FACGT Vd.4H,Vn.4H,Vm.4H uint16x4_t vcalt_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCALT_F32: // FACGT Vd.2S,Vm.2S,Vn.2S uint32x2_t vcalt_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCALT_F64: // FACGT Dd,Dm,Dn uint64x1_t vcalt_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCALTD_F64: // FACGT Dd,Dm,Dn uint64_t vcaltd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCEQ_F16: // FCMEQ Vd.4H,Vn.4H,Vm.4H uint16x4_t vceq_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCEQ_F32: // FCMEQ Vd.2S,Vn.2S,Vm.2S uint32x2_t vceq_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCEQ_F64: // FCMEQ Dd,Dn,Dm uint64x1_t vceq_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCEQD_F64: // FCMEQ Dd,Dn,Dm uint64_t vceqd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCGE_F16: // FCMGE Vd.4H,Vn.4H,Vm.4H uint16x4_t vcge_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCGE_F32: // FCMGE Vd.2S,Vm.2S,Vn.2S uint32x2_t vcge_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCGE_F64: // FCMGE Dd,Dn,Dm uint64x1_t vcge_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCGED_F64: // FCMGE Dd,Dn,Dm uint64_t vcged_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCGT_F16: // FCMGT Vd.4H,Vn.4H,Vm.4H uint16x4_t vcgt_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCGT_F32: // FCMGT Vd.2S,Vn.2S,Vm.2S uint32x2_t vcgt_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCGT_F64: // FCMGT Dd,Dn,Dm uint64x1_t vcgt_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCGTD_F64: // FCMGT Dd,Dn,Dm uint64_t vcgtd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCLE_F16: // FCMGE Vd.4H,Vn.4H,Vm.4H uint16x4_t vcle_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCLE_F32: // FCMGE Vd.2S,Vm.2S,Vn.2S uint32x2_t vcle_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCLE_F64: // FCMGE Dd,Dm,Dn uint64x1_t vcle_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCLED_F64: // FCMGE Dd,Dm,Dn uint64_t vcled_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCLT_F16: // FCMGT Vd.4H,Vn.4H,Vm.4H uint16x4_t vclt_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCLT_F32: // FCMGT Vd.2S,Vm.2S,Vn.2S uint32x2_t vclt_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCLT_F64: // FCMGT Dd,Dm,Dn uint64x1_t vclt_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCLTD_F64: // FCMGT Dd,Dm,Dn uint64_t vcltd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCOMBINE_BF16: // INS Vd.D[1],Vm.D[0] bfloat16x8_t vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high)
+ case ARM64_INTRIN_VCOMBINE_F16: // INS Vd.D[1],Vm.D[0] float16x8_t vcombine_f16(float16x4_t low, float16x4_t high)
+ case ARM64_INTRIN_VCOMBINE_F32: // INS Vd.D[1],Vm.D[0] float32x4_t vcombine_f32(float32x2_t low, float32x2_t high)
+ case ARM64_INTRIN_VCOMBINE_F64: // INS Vd.D[1],Vm.D[0] float64x2_t vcombine_f64(float64x1_t low, float64x1_t high)
+ case ARM64_INTRIN_VDIV_F16: // FDIV Vd.4H,Vn.4H,Vm.4H float16x4_t vdiv_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VDIV_F32: // FDIV Vd.2S,Vn.2S,Vm.2S float32x2_t vdiv_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VDIV_F64: // FDIV Dd,Dn,Dm float64x1_t vdiv_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VMAX__F32: // FMAX Vd.2S,Vn.2S,Vm.2S float32x2_t vmax__f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VMAX_F16: // FMAX Vd.4H,Vn.4H,Vm.4H float16x4_t vmax_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VMAX_F64: // FMAX Dd,Dn,Dm float64x1_t vmax_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VMAXNM__F32: // FMAXNM Vd.2S,Vn.2S,Vm.2S float32x2_t vmaxnm__f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VMAXNM_F16: // FMAXNM Vd.4H,Vn.4H,Vm.4H float16x4_t vmaxnm_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VMAXNM_F64: // FMAXNM Dd,Dn,Dm float64x1_t vmaxnm_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VMIN_F16: // FMIN Vd.4H,Vn.4H,Vm.4H float16x4_t vmin_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VMIN_F32: // FMIN Vd.2S,Vn.2S,Vm.2S float32x2_t vmin_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VMIN_F64: // FMIN Dd,Dn,Dm float64x1_t vmin_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VMINNM_F16: // FMINNM Vd.4H,Vn.4H,Vm.4H float16x4_t vminnm_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VMINNM_F32: // FMINNM Vd.2S,Vn.2S,Vm.2S float32x2_t vminnm_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VMINNM_F64: // FMINNM Dd,Dn,Dm float64x1_t vminnm_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VMUL_F16: // FMUL Vd.4H,Vn.4H,Vm.4H float16x4_t vmul_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VMUL_F32: // FMUL Vd.2S,Vn.2S,Vm.2S float32x2_t vmul_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VMUL_F64: // FMUL Dd,Dn,Dm float64x1_t vmul_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VMUL_N_F64: // FMUL Dd,Dn,Vm.D[0] float64x1_t vmul_n_f64(float64x1_t a, float64_t b)
+ case ARM64_INTRIN_VMULX_F16: // FMULX Vd.4H,Vn.4H,Vm.4H float16x4_t vmulx_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VMULX_F32: // FMULX Vd.2S,Vn.2S,Vm.2S float32x2_t vmulx_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VMULX_F64: // FMULX Dd,Dn,Dm float64x1_t vmulx_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VMULXD_F64: // FMULX Dd,Dn,Dm float64_t vmulxd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VPADD_F16: // FADDP Vd.4H,Vn.4H,Vm.4H float16x4_t vpadd_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VPADD_F32: // FADDP Vd.2S,Vn.2S,Vm.2S float32x2_t vpadd_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VPMAX_F16: // FMAXP Vd.4H,Vn.4H,Vm.4H float16x4_t vpmax_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VPMAX_F32: // FMAXP Vd.2S,Vn.2S,Vm.2S float32x2_t vpmax_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VPMAXNM_F16: // FMAXNMP Vd.4H,Vn.4H,Vm.4H float16x4_t vpmaxnm_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VPMAXNM_F32: // FMAXNMP Vd.2S,Vn.2S,Vm.2S float32x2_t vpmaxnm_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VPMIN_F16: // FMINP Vd.4H,Vn.4H,Vm.4H float16x4_t vpmin_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VPMIN_F32: // FMINP Vd.2S,Vn.2S,Vm.2S float32x2_t vpmin_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VPMINNM_F16: // FMINNMP Vd.4H,Vn.4H,Vm.4H float16x4_t vpminnm_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VPMINNM_F32: // FMINNMP Vd.2S,Vn.2S,Vm.2S float32x2_t vpminnm_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VRECPS_F16: // FRECPS Vd.4H,Vn.4H,Vm.4H float16x4_t vrecps_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VRECPS_F32: // FRECPS Vd.2S,Vn.2S,Vm.2S float32x2_t vrecps_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VRECPS_F64: // FRECPS Dd,Dn,Dm float64x1_t vrecps_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VRECPSD_F64: // FRECPS Dd,Dn,Dm float64_t vrecpsd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VRSQRTS_F16: // FRSQRTS Vd.4H,Vn.4H,Vm.4H float16x4_t vrsqrts_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VRSQRTS_F32: // FRSQRTS Vd.2S,Vn.2S,Vm.2S float32x2_t vrsqrts_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VRSQRTS_F64: // FRSQRTS Dd,Dn,Dm float64x1_t vrsqrts_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VRSQRTSD_F64: // FRSQRTS Dd,Dn,Dm float64_t vrsqrtsd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VSUB_F16: // FSUB Vd.4H,Vn.4H,Vm.4H float16x4_t vsub_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VSUB_F32: // FSUB Vd.2S,Vn.2S,Vm.2S float32x2_t vsub_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VSUB_F64: // FSUB Dd,Dn,Dm float64x1_t vsub_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VTRN1_F16: // TRN1 Vd.4H,Vn.4H,Vm.4H float16x4_t vtrn1_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VTRN1_F32: // TRN1 Vd.2S,Vn.2S,Vm.2S float32x2_t vtrn1_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VTRN2_F16: // TRN2 Vd.4H,Vn.4H,Vm.4H float16x4_t vtrn2_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VTRN2_F32: // TRN2 Vd.2S,Vn.2S,Vm.2S float32x2_t vtrn2_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VTRN_F16: // TRN1 Vd1.4H,Vn.4H,Vm.4H float16x4x2_t vtrn_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VTRN_F32: // TRN1 Vd1.2S,Vn.2S,Vm.2S float32x2x2_t vtrn_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VUZP1_F16: // UZP1 Vd.4H,Vn.4H,Vm.4H float16x4_t vuzp1_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VUZP1_F32: // UZP1 Vd.2S,Vn.2S,Vm.2S float32x2_t vuzp1_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VUZP2_F16: // UZP2 Vd.4H,Vn.4H,Vm.4H float16x4_t vuzp2_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VUZP2_F32: // UZP2 Vd.2S,Vn.2S,Vm.2S float32x2_t vuzp2_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VUZP_F16: // UZP1 Vd1.4H,Vn.4H,Vm.4H float16x4x2_t vuzp_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VUZP_F32: // UZP1 Vd1.2S,Vn.2S,Vm.2S float32x2x2_t vuzp_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VZIP1_F16: // ZIP1 Vd.4H,Vn.4H,Vm.4H float16x4_t vzip1_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VZIP1_F32: // ZIP1 Vd.2S,Vn.2S,Vm.2S float32x2_t vzip1_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VZIP2_F16: // ZIP2 Vd.4H,Vn.4H,Vm.4H float16x4_t vzip2_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VZIP2_F32: // ZIP2 Vd.2S,Vn.2S,Vm.2S float32x2_t vzip2_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VZIP_F16: // ZIP1 Vd1.4H,Vn.4H,Vm.4H float16x4x2_t vzip_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VZIP_F32: // ZIP1 Vd1.2S,Vn.2S,Vm.2S float32x2x2_t vzip_f32(float32x2_t a, float32x2_t b)
+ return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8))};
+ case ARM64_INTRIN_VBFDOT_LANEQ_F32: // BFDOT Vd.2S,Vn.4H,Vm.2H[lane] float32x2_t vbfdot_laneq_f32(float32x2_t r, bfloat16x4_t a, bfloat16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_LANEQ_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#0 float16x4_t vcmla_laneq_f16(float16x4_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_LANEQ_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S,#0 float32x2_t vcmla_laneq_f32(float32x2_t r, float32x2_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT180_LANEQ_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#180 float16x4_t vcmla_rot180_laneq_f16(float16x4_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT180_LANEQ_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S,#180 float32x2_t vcmla_rot180_laneq_f32(float32x2_t r, float32x2_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT270_LANEQ_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#270 float16x4_t vcmla_rot270_laneq_f16(float16x4_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT270_LANEQ_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#270 float32x2_t vcmla_rot270_laneq_f32(float32x2_t r, float32x2_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT90_LANEQ_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#90 float16x4_t vcmla_rot90_laneq_f16(float16x4_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT90_LANEQ_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S,#90 float32x2_t vcmla_rot90_laneq_f32(float32x2_t r, float32x2_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VFMA_LANEQ_F16: // FMLA Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vfma_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VFMA_LANEQ_F32: // FMLA Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vfma_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VFMA_LANEQ_F64: // FMLA Dd,Dn,Vm.D[lane] float64x1_t vfma_laneq_f64(float64x1_t a, float64x1_t b, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VFMAD_LANEQ_F64: // FMLA Dd,Dn,Vm.D[lane] float64_t vfmad_laneq_f64(float64_t a, float64_t b, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VFMLAL_LANEQ_HIGH_F16: // FMLAL2 Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlal_laneq_high_f16(float32x2_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMLAL_LANEQ_LOW_F16: // FMLAL Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlal_laneq_low_f16(float32x2_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMLSL_LANEQ_HIGH_F16: // FMLSL2 Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlsl_laneq_high_f16(float32x2_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMLSL_LANEQ_LOW_F16: // FMLSL Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlsl_laneq_low_f16(float32x2_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMS_LANEQ_F16: // FMLS Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vfms_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VFMS_LANEQ_F32: // FMLS Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vfms_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VFMS_LANEQ_F64: // FMLS Dd,Dn,Vm.D[lane] float64x1_t vfms_laneq_f64(float64x1_t a, float64x1_t b, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VFMSD_LANEQ_F64: // FMLS Dd,Dn,Vm.D[lane] float64_t vfmsd_laneq_f64(float64_t a, float64_t b, float64x2_t v, const int lane)
+ return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VFMA_N_F16: // FMLA Vd.4H,Vn.4H,Vm.H[0] float16x4_t vfma_n_f16(float16x4_t a, float16x4_t b, float16_t n)
+ case ARM64_INTRIN_VFMS_N_F16: // FMLS Vd.4H,Vn.4H,Vm.H[0] float16x4_t vfms_n_f16(float16x4_t a, float16x4_t b, float16_t n)
+ return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(2))};
+ case ARM64_INTRIN_VFMA_N_F32: // FMLA Vd.2S,Vn.2S,Vm.S[0] float32x2_t vfma_n_f32(float32x2_t a, float32x2_t b, float32_t n)
+ case ARM64_INTRIN_VFMS_N_F32: // FMLS Vd.2S,Vn.2S,Vm.S[0] float32x2_t vfms_n_f32(float32x2_t a, float32x2_t b, float32_t n)
+ return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(4))};
+ case ARM64_INTRIN_VBFDOT_F32: // BFDOT Vd.2S,Vn.4H,Vm.4H float32x2_t vbfdot_f32(float32x2_t r, bfloat16x4_t a, bfloat16x4_t b)
+ case ARM64_INTRIN_VCMLA_F16: // FCMLA Vd.4H,Vn.4H,Vm.4H,#0 float16x4_t vcmla_f16(float16x4_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCMLA_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S,#0 float32x2_t vcmla_f32(float32x2_t r, float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCMLA_ROT180_F16: // FCMLA Vd.4H,Vn.4H,Vm.4H,#180 float16x4_t vcmla_rot180_f16(float16x4_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCMLA_ROT180_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S,#180 float32x2_t vcmla_rot180_f32(float32x2_t r, float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCMLA_ROT270_F16: // FCMLA Vd.4H,Vn.4H,Vm.4H,#270 float16x4_t vcmla_rot270_f16(float16x4_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCMLA_ROT270_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S,#270 float32x2_t vcmla_rot270_f32(float32x2_t r, float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCMLA_ROT90_F16: // FCMLA Vd.4H,Vn.4H,Vm.4H,#90 float16x4_t vcmla_rot90_f16(float16x4_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCMLA_ROT90_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S,#90 float32x2_t vcmla_rot90_f32(float32x2_t r, float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VFMA_F16: // FMLA Vd.4H,Vn.4H,Vm.4H float16x4_t vfma_f16(float16x4_t a, float16x4_t b, float16x4_t c)
+ case ARM64_INTRIN_VFMA_F32: // FMLA Vd.2S,Vn.2S,Vm.2S float32x2_t vfma_f32(float32x2_t a, float32x2_t b, float32x2_t c)
+ case ARM64_INTRIN_VFMA_F64: // FMADD Dd,Dn,Dm,Da float64x1_t vfma_f64(float64x1_t a, float64x1_t b, float64x1_t c)
+ case ARM64_INTRIN_VFMA_N_F64: // FMADD Dd,Dn,Dm,Da float64x1_t vfma_n_f64(float64x1_t a, float64x1_t b, float64_t n)
+ case ARM64_INTRIN_VFMLAL_HIGH_F16: // FMLAL2 Vd.2S,Vn.2H,Vm.2H float32x2_t vfmlal_high_f16(float32x2_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VFMLAL_LOW_F16: // FMLAL Vd.2S,Vn.2H,Vm.2H float32x2_t vfmlal_low_f16(float32x2_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VFMLSL_HIGH_F16: // FMLSL2 Vd.2S,Vn.2H,Vm.2H float32x2_t vfmlsl_high_f16(float32x2_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VFMLSL_LOW_F16: // FMLSL Vd.2S,Vn.2H,Vm.2H float32x2_t vfmlsl_low_f16(float32x2_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VFMS_F16: // FMLS Vd.4H,Vn.4H,Vm.4H float16x4_t vfms_f16(float16x4_t a, float16x4_t b, float16x4_t c)
+ case ARM64_INTRIN_VFMS_F32: // FMLS Vd.2S,Vn.2S,Vm.2S float32x2_t vfms_f32(float32x2_t a, float32x2_t b, float32x2_t c)
+ case ARM64_INTRIN_VFMS_F64: // FMSUB Dd,Dn,Dm,Da float64x1_t vfms_f64(float64x1_t a, float64x1_t b, float64x1_t c)
+ return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8))};
+ case ARM64_INTRIN_VBFDOT_LANE_F32: // BFDOT Vd.2S,Vn.4H,Vm.2H[lane] float32x2_t vbfdot_lane_f32(float32x2_t r, bfloat16x4_t a, bfloat16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_LANE_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#0 float16x4_t vcmla_lane_f16(float16x4_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_LANE_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#0 float32x2_t vcmla_lane_f32(float32x2_t r, float32x2_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT180_LANE_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#180 float16x4_t vcmla_rot180_lane_f16(float16x4_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT180_LANE_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#180 float32x2_t vcmla_rot180_lane_f32(float32x2_t r, float32x2_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT270_LANE_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#270 float16x4_t vcmla_rot270_lane_f16(float16x4_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT270_LANE_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#270 float32x2_t vcmla_rot270_lane_f32(float32x2_t r, float32x2_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT90_LANE_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#90 float16x4_t vcmla_rot90_lane_f16(float16x4_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT90_LANE_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#90 float32x2_t vcmla_rot90_lane_f32(float32x2_t r, float32x2_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VFMA_LANE_F16: // FMLA Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vfma_lane_f16(float16x4_t a, float16x4_t b, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VFMA_LANE_F32: // FMLA Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vfma_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VFMA_LANE_F64: // FMLA Dd,Dn,Vm.D[lane] float64x1_t vfma_lane_f64(float64x1_t a, float64x1_t b, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VFMAD_LANE_F64: // FMLA Dd,Dn,Vm.D[lane] float64_t vfmad_lane_f64(float64_t a, float64_t b, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VFMLAL_LANE_HIGH_F16: // FMLAL2 Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlal_lane_high_f16(float32x2_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMLAL_LANE_LOW_F16: // FMLAL Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlal_lane_low_f16(float32x2_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMLSL_LANE_HIGH_F16: // FMLSL2 Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlsl_lane_high_f16(float32x2_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMLSL_LANE_LOW_F16: // FMLSL Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlsl_lane_low_f16(float32x2_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMS_LANE_F16: // FMLS Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vfms_lane_f16(float16x4_t a, float16x4_t b, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VFMS_LANE_F32: // FMLS Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vfms_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VFMS_LANE_F64: // FMLS Dd,Dn,Vm.D[lane] float64x1_t vfms_lane_f64(float64x1_t a, float64x1_t b, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VFMSD_LANE_F64: // FMLS Dd,Dn,Vm.D[lane] float64_t vfmsd_lane_f64(float64_t a, float64_t b, float64x1_t v, const int lane)
+ return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VEXT_F16: // EXT Vd.8B,Vn.8B,Vm.8B,#n float16x4_t vext_f16(float16x4_t a, float16x4_t b, const int n)
+ case ARM64_INTRIN_VEXT_F32: // EXT Vd.8B,Vn.8B,Vm.8B,#n float32x2_t vext_f32(float32x2_t a, float32x2_t b, const int n)
+ case ARM64_INTRIN_VEXT_F64: // EXT Vd.8B,Vn.8B,Vm.8B,#n float64x1_t vext_f64(float64x1_t a, float64x1_t b, const int n)
+ case ARM64_INTRIN_VMUL_LANE_F16: // FMUL Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vmul_lane_f16(float16x4_t a, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANE_F32: // FMUL Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vmul_lane_f32(float32x2_t a, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANE_F64: // FMUL Dd,Dn,Vm.D[lane] float64x1_t vmul_lane_f64(float64x1_t a, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VMULX_LANE_F16: // FMULX Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vmulx_lane_f16(float16x4_t a, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULX_LANE_F32: // FMULX Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vmulx_lane_f32(float32x2_t a, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULX_LANE_F64: // FMULX Dd,Dn,Vm.D[lane] float64x1_t vmulx_lane_f64(float64x1_t a, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VMULXD_LANE_F64: // FMULX Dd,Dn,Vm.D[lane] float64_t vmulxd_lane_f64(float64_t a, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_F64: // MOV Vd.D[lane],Rn float64x1_t vset_lane_f64(float64_t a, float64x1_t v, const int lane)
+ return {NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VCVT_N_S16_F16: // FCVTZS Vd.4H,Vn.4H,#n int16x4_t vcvt_n_s16_f16(float16x4_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_S32_F32: // FCVTZS Vd.2S,Vn.2S,#n int32x2_t vcvt_n_s32_f32(float32x2_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_S64_F64: // FCVTZS Dd,Dn,#n int64x1_t vcvt_n_s64_f64(float64x1_t a, const int n)
+ // case ARM64_INTRIN_VCVT_N_S64_F64: // FCVTZS Xd,Dn,#n int64x1_t vcvt_n_s64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_U16_F16: // FCVTZU Vd.4H,Vn.4H,#n uint16x4_t vcvt_n_u16_f16(float16x4_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_U32_F32: // FCVTZU Vd.2S,Vn.2S,#n uint32x2_t vcvt_n_u32_f32(float32x2_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_U64_F64: // FCVTZU Dd,Dn,#n uint64x1_t vcvt_n_u64_f64(float64x1_t a, const int n)
+ // case ARM64_INTRIN_VCVT_N_U64_F64: // FCVTZU Xd,Dn,#n uint64x1_t vcvt_n_u64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVTA_N_S64_F64: // FCVTAS Xd,Dn,#n int64x1_t vcvta_n_s64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVTA_N_U64_F64: // FCVTAU Xd,Dn,#n uint64x1_t vcvta_n_u64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVTAD_N_S64_F64: // FCVTAS Xd,Dn,#n int64_t vcvtad_n_s64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTAD_N_U64_F64: // FCVTAU Xd,Dn,#n uint64_t vcvtad_n_u64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTD_N_S64_F64: // FCVTZS Dd,Dn,#n int64_t vcvtd_n_s64_f64(float64_t a, const int n)
+ // case ARM64_INTRIN_VCVTD_N_S64_F64: // FCVTZS Xd,Dn,#n int64_t vcvtd_n_s64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTD_N_U64_F64: // FCVTZU Dd,Dn,#n uint64_t vcvtd_n_u64_f64(float64_t a, const int n)
+ // case ARM64_INTRIN_VCVTD_N_U64_F64: // FCVTZU Xd,Dn,#n uint64_t vcvtd_n_u64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTM_N_S64_F64: // FCVTMS Xd,Dn,#n int64x1_t vcvtm_n_s64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVTM_N_U64_F64: // FCVTMU Xd,Dn,#n uint64x1_t vcvtm_n_u64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVTMD_N_S64_F64: // FCVTMS Xd,Dn,#n int64_t vcvtmd_n_s64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTMD_N_U64_F64: // FCVTMU Xd,Dn,#n uint64_t vcvtmd_n_u64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTP_N_S64_F64: // FCVTPS Xd,Dn,#n int64x1_t vcvtp_n_s64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVTP_N_U64_F64: // FCVTPU Xd,Dn,#n uint64x1_t vcvtp_n_u64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVTPD_N_S64_F64: // FCVTPS Xd,Dn,#n int64_t vcvtpd_n_s64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTPD_N_U64_F64: // FCVTPU Xd,Dn,#n uint64_t vcvtpd_n_u64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTS_N_U32_F64: // FCVTZU Wd,Dn,#n uint32_t vcvts_n_u32_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTS_N_U64_F64: // FCVTZU Xd,Dn,#n uint64_t vcvts_n_u64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VDUP_LANE_BF16: // DUP Vd.4H,Vn.H[lane] bfloat16x4_t vdup_lane_bf16(bfloat16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_F16: // DUP Vd.4H,Vn.H[lane] float16x4_t vdup_lane_f16(float16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_F32: // DUP Vd.2S,Vn.S[lane] float32x2_t vdup_lane_f32(float32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_F64: // DUP Dd,Vn.D[lane] float64x1_t vdup_lane_f64(float64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUPD_LANE_F64: // DUP Dd,Vn.D[lane] float64_t vdupd_lane_f64(float64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANE_BF16: // DUP Hd,Vn.H[lane] bfloat16_t vduph_lane_bf16(bfloat16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANE_F16: // DUP Hd,Vn.H[lane] float16_t vduph_lane_f16(float16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_BF16: // DUP Vd.8H,Vn.H[lane] bfloat16x8_t vdupq_lane_bf16(bfloat16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_F16: // DUP Vd.8H,Vn.H[lane] float16x8_t vdupq_lane_f16(float16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_F32: // DUP Vd.4S,Vn.S[lane] float32x4_t vdupq_lane_f32(float32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_F64: // DUP Vd.2D,Vn.D[lane] float64x2_t vdupq_lane_f64(float64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUPS_LANE_F32: // DUP Sd,Vn.S[lane] float32_t vdups_lane_f32(float32x2_t vec, const int lane)
+ case ARM64_INTRIN_VGET_LANE_BF16: // DUP Hd,Vn.H[lane] bfloat16_t vget_lane_bf16(bfloat16x4_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_F16: // DUP Hd,Vn.H[lane] float16_t vget_lane_f16(float16x4_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_F32: // DUP Sd,Vn.S[lane] float32_t vget_lane_f32(float32x2_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_F64: // DUP Dd,Vn.D[lane] float64_t vget_lane_f64(float64x1_t v, const int lane)
+ return {NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VCOPY_LANEQ_BF16: // INS Vd.H[lane1],Vn.H[lane2] bfloat16x4_t vcopy_laneq_bf16(bfloat16x4_t a, const int lane1, bfloat16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_F32: // INS Vd.S[lane1],Vn.S[lane2] float32x2_t vcopy_laneq_f32(float32x2_t a, const int lane1, float32x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_F64: // DUP Dd,Vn.D[lane2] float64x1_t vcopy_laneq_f64(float64x1_t a, const int lane1, float64x2_t b, const int lane2)
+ return {NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::FloatType(16)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VCOPY_LANE_BF16: // INS Vd.H[lane1],Vn.H[lane2] bfloat16x4_t vcopy_lane_bf16(bfloat16x4_t a, const int lane1, bfloat16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_F32: // INS Vd.S[lane1],Vn.S[lane2] float32x2_t vcopy_lane_f32(float32x2_t a, const int lane1, float32x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_F64: // DUP Dd,Vn.D[lane2] float64x1_t vcopy_lane_f64(float64x1_t a, const int lane1, float64x1_t b, const int lane2)
+ return {NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::FloatType(8)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VDUP_N_P8: // DUP Vd.8B,rn poly8x8_t vdup_n_p8(poly8_t value)
+ case ARM64_INTRIN_VDUP_N_S8: // DUP Vd.8B,rn int8x8_t vdup_n_s8(int8_t value)
+ case ARM64_INTRIN_VDUP_N_U8: // DUP Vd.8B,rn uint8x8_t vdup_n_u8(uint8_t value)
+ case ARM64_INTRIN_VDUPQ_N_P8: // DUP Vd.16B,rn poly8x16_t vdupq_n_p8(poly8_t value)
+ case ARM64_INTRIN_VDUPQ_N_S8: // DUP Vd.16B,rn int8x16_t vdupq_n_s8(int8_t value)
+ case ARM64_INTRIN_VDUPQ_N_U8: // DUP Vd.16B,rn uint8x16_t vdupq_n_u8(uint8_t value)
+ case ARM64_INTRIN_VMOV_N_P8: // DUP Vd.8B,rn poly8x8_t vmov_n_p8(poly8_t value)
+ case ARM64_INTRIN_VMOV_N_S8: // DUP Vd.8B,rn int8x8_t vmov_n_s8(int8_t value)
+ case ARM64_INTRIN_VMOV_N_U8: // DUP Vd.8B,rn uint8x8_t vmov_n_u8(uint8_t value)
+ case ARM64_INTRIN_VMOVQ_N_P8: // DUP Vd.16B,rn poly8x16_t vmovq_n_p8(poly8_t value)
+ case ARM64_INTRIN_VMOVQ_N_S8: // DUP Vd.16B,rn int8x16_t vmovq_n_s8(int8_t value)
+ case ARM64_INTRIN_VMOVQ_N_U8: // DUP Vd.16B,rn uint8x16_t vmovq_n_u8(uint8_t value)
+ case ARM64_INTRIN_VQABSB_S8: // SQABS Bd,Bn int8_t vqabsb_s8(int8_t a)
+ case ARM64_INTRIN_VQNEGB_S8: // SQNEG Bd,Bn int8_t vqnegb_s8(int8_t a)
+ return {NameAndType(Type::IntegerType(1, false))};
+ case ARM64_INTRIN_VQADDB_S8: // SQADD Bd,Bn,Bm int8_t vqaddb_s8(int8_t a, int8_t b)
+ case ARM64_INTRIN_VQADDB_U8: // UQADD Bd,Bn,Bm uint8_t vqaddb_u8(uint8_t a, uint8_t b)
+ case ARM64_INTRIN_VQRSHLB_S8: // SQRSHL Bd,Bn,Bm int8_t vqrshlb_s8(int8_t a, int8_t b)
+ case ARM64_INTRIN_VQRSHLB_U8: // UQRSHL Bd,Bn,Bm uint8_t vqrshlb_u8(uint8_t a, int8_t b)
+ case ARM64_INTRIN_VQSHLB_S8: // SQSHL Bd,Bn,Bm int8_t vqshlb_s8(int8_t a, int8_t b)
+ case ARM64_INTRIN_VQSHLB_U8: // UQSHL Bd,Bn,Bm uint8_t vqshlb_u8(uint8_t a, int8_t b)
+ case ARM64_INTRIN_VQSUBB_S8: // SQSUB Bd,Bn,Bm int8_t vqsubb_s8(int8_t a, int8_t b)
+ case ARM64_INTRIN_VQSUBB_U8: // UQSUB Bd,Bn,Bm uint8_t vqsubb_u8(uint8_t a, uint8_t b)
+ case ARM64_INTRIN_VSQADDB_U8: // USQADD Bd,Bn uint8_t vsqaddb_u8(uint8_t a, int8_t b)
+ case ARM64_INTRIN_VUQADDB_S8: // SUQADD Bd,Bn int8_t vuqaddb_s8(int8_t a, uint8_t b)
+ return {NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(1, false))};
+ case ARM64_INTRIN_VSETQ_LANE_P8: // MOV Vd.B[lane],Rn poly8x16_t vsetq_lane_p8(poly8_t a, poly8x16_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_S8: // MOV Vd.B[lane],Rn int8x16_t vsetq_lane_s8(int8_t a, int8x16_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_U8: // MOV Vd.B[lane],Rn uint8x16_t vsetq_lane_u8(uint8_t a, uint8x16_t v, const int lane)
+ return {NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VQSHLB_N_S8: // SQSHL Bd,Bn,#n int8_t vqshlb_n_s8(int8_t a, const int n)
+ case ARM64_INTRIN_VQSHLB_N_U8: // UQSHL Bd,Bn,#n uint8_t vqshlb_n_u8(uint8_t a, const int n)
+ case ARM64_INTRIN_VQSHLUB_N_S8: // SQSHLU Bd,Bn,#n uint8_t vqshlub_n_s8(int8_t a, const int n)
+ return {NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VSET_LANE_P8: // MOV Vd.B[lane],Rn poly8x8_t vset_lane_p8(poly8_t a, poly8x8_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_S8: // MOV Vd.B[lane],Rn int8x8_t vset_lane_s8(int8_t a, int8x8_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_U8: // MOV Vd.B[lane],Rn uint8x8_t vset_lane_u8(uint8_t a, uint8x8_t v, const int lane)
+ return {NameAndType(Type::IntegerType(1, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VABSQ_S16: // ABS Vd.8H,Vn.8H int16x8_t vabsq_s16(int16x8_t a)
+ case ARM64_INTRIN_VABSQ_S32: // ABS Vd.4S,Vn.4S int32x4_t vabsq_s32(int32x4_t a)
+ case ARM64_INTRIN_VABSQ_S64: // ABS Vd.2D,Vn.2D int64x2_t vabsq_s64(int64x2_t a)
+ case ARM64_INTRIN_VABSQ_S8: // ABS Vd.16B,Vn.16B int8x16_t vabsq_s8(int8x16_t a)
+ case ARM64_INTRIN_VADDLVQ_S16: // SADDLV Sd,Vn.8H int32_t vaddlvq_s16(int16x8_t a)
+ case ARM64_INTRIN_VADDLVQ_S32: // SADDLV Dd,Vn.4S int64_t vaddlvq_s32(int32x4_t a)
+ case ARM64_INTRIN_VADDLVQ_S8: // SADDLV Hd,Vn.16B int16_t vaddlvq_s8(int8x16_t a)
+ case ARM64_INTRIN_VADDLVQ_U16: // UADDLV Sd,Vn.8H uint32_t vaddlvq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VADDLVQ_U32: // UADDLV Dd,Vn.4S uint64_t vaddlvq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VADDLVQ_U8: // UADDLV Hd,Vn.16B uint16_t vaddlvq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VADDVQ_S16: // ADDV Hd,Vn.8H int16_t vaddvq_s16(int16x8_t a)
+ case ARM64_INTRIN_VADDVQ_S32: // ADDV Sd,Vn.4S int32_t vaddvq_s32(int32x4_t a)
+ case ARM64_INTRIN_VADDVQ_S64: // ADDP Dd,Vn.2D int64_t vaddvq_s64(int64x2_t a)
+ case ARM64_INTRIN_VADDVQ_S8: // ADDV Bd,Vn.16B int8_t vaddvq_s8(int8x16_t a)
+ case ARM64_INTRIN_VADDVQ_U16: // ADDV Hd,Vn.8H uint16_t vaddvq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VADDVQ_U32: // ADDV Sd,Vn.4S uint32_t vaddvq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VADDVQ_U64: // ADDP Dd,Vn.2D uint64_t vaddvq_u64(uint64x2_t a)
+ case ARM64_INTRIN_VADDVQ_U8: // ADDV Bd,Vn.16B uint8_t vaddvq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VAESIMCQ_U8: // AESIMC Vd.16B,Vn.16B uint8x16_t vaesimcq_u8(uint8x16_t data)
+ case ARM64_INTRIN_VAESMCQ_U8: // AESMC Vd.16B,Vn.16B uint8x16_t vaesmcq_u8(uint8x16_t data)
+ case ARM64_INTRIN_VCEQZQ_P64: // CMEQ Vd.2D,Vn.2D,#0 uint64x2_t vceqzq_p64(poly64x2_t a)
+ case ARM64_INTRIN_VCEQZQ_P8: // CMEQ Vd.16B,Vn.16B,#0 uint8x16_t vceqzq_p8(poly8x16_t a)
+ case ARM64_INTRIN_VCEQZQ_S16: // CMEQ Vd.8H,Vn.8H,#0 uint16x8_t vceqzq_s16(int16x8_t a)
+ case ARM64_INTRIN_VCEQZQ_S32: // CMEQ Vd.4S,Vn.4S,#0 uint32x4_t vceqzq_s32(int32x4_t a)
+ case ARM64_INTRIN_VCEQZQ_S64: // CMEQ Vd.2D,Vn.2D,#0 uint64x2_t vceqzq_s64(int64x2_t a)
+ case ARM64_INTRIN_VCEQZQ_S8: // CMEQ Vd.16B,Vn.16B,#0 uint8x16_t vceqzq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCEQZQ_U16: // CMEQ Vd.8H,Vn.8H,#0 uint16x8_t vceqzq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VCEQZQ_U32: // CMEQ Vd.4S,Vn.4S,#0 uint32x4_t vceqzq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VCEQZQ_U64: // CMEQ Vd.2D,Vn.2D,#0 uint64x2_t vceqzq_u64(uint64x2_t a)
+ case ARM64_INTRIN_VCEQZQ_U8: // CMEQ Vd.16B,Vn.16B,#0 uint8x16_t vceqzq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VCGEZQ_S16: // CMGE Vd.8H,Vn.8H,#0 uint16x8_t vcgezq_s16(int16x8_t a)
+ case ARM64_INTRIN_VCGEZQ_S32: // CMGE Vd.4S,Vn.4S,#0 uint32x4_t vcgezq_s32(int32x4_t a)
+ case ARM64_INTRIN_VCGEZQ_S64: // CMGE Vd.2D,Vn.2D,#0 uint64x2_t vcgezq_s64(int64x2_t a)
+ case ARM64_INTRIN_VCGEZQ_S8: // CMGE Vd.16B,Vn.16B,#0 uint8x16_t vcgezq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCGTZQ_S16: // CMGT Vd.8H,Vn.8H,#0 uint16x8_t vcgtzq_s16(int16x8_t a)
+ case ARM64_INTRIN_VCGTZQ_S32: // CMGT Vd.4S,Vn.4S,#0 uint32x4_t vcgtzq_s32(int32x4_t a)
+ case ARM64_INTRIN_VCGTZQ_S64: // CMGT Vd.2D,Vn.2D,#0 uint64x2_t vcgtzq_s64(int64x2_t a)
+ case ARM64_INTRIN_VCGTZQ_S8: // CMGT Vd.16B,Vn.16B,#0 uint8x16_t vcgtzq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCLEZQ_S16: // CMLE Vd.8H,Vn.8H,#0 uint16x8_t vclezq_s16(int16x8_t a)
+ case ARM64_INTRIN_VCLEZQ_S32: // CMLE Vd.4S,Vn.4S,#0 uint32x4_t vclezq_s32(int32x4_t a)
+ case ARM64_INTRIN_VCLEZQ_S64: // CMLE Vd.2D,Vn.2D,#0 uint64x2_t vclezq_s64(int64x2_t a)
+ case ARM64_INTRIN_VCLEZQ_S8: // CMLE Vd.16B,Vn.16B,#0 uint8x16_t vclezq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCLSQ_S16: // CLS Vd.8H,Vn.8H int16x8_t vclsq_s16(int16x8_t a)
+ case ARM64_INTRIN_VCLSQ_S32: // CLS Vd.4S,Vn.4S int32x4_t vclsq_s32(int32x4_t a)
+ case ARM64_INTRIN_VCLSQ_S8: // CLS Vd.16B,Vn.16B int8x16_t vclsq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCLSQ_U16: // CLS Vd.8H,Vn.8H int16x8_t vclsq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VCLSQ_U32: // CLS Vd.4S,Vn.4S int32x4_t vclsq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VCLSQ_U8: // CLS Vd.16B,Vn.16B int8x16_t vclsq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VCLTZQ_S16: // CMLT Vd.8H,Vn.8H,#0 uint16x8_t vcltzq_s16(int16x8_t a)
+ case ARM64_INTRIN_VCLTZQ_S32: // CMLT Vd.4S,Vn.4S,#0 uint32x4_t vcltzq_s32(int32x4_t a)
+ case ARM64_INTRIN_VCLTZQ_S64: // CMLT Vd.2D,Vn.2D,#0 uint64x2_t vcltzq_s64(int64x2_t a)
+ case ARM64_INTRIN_VCLTZQ_S8: // CMLT Vd.16B,Vn.16B,#0 uint8x16_t vcltzq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCLZQ_S16: // CLZ Vd.8H,Vn.8H int16x8_t vclzq_s16(int16x8_t a)
+ case ARM64_INTRIN_VCLZQ_S32: // CLZ Vd.4S,Vn.4S int32x4_t vclzq_s32(int32x4_t a)
+ case ARM64_INTRIN_VCLZQ_S8: // CLZ Vd.16B,Vn.16B int8x16_t vclzq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCLZQ_U16: // CLZ Vd.8H,Vn.8H uint16x8_t vclzq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VCLZQ_U32: // CLZ Vd.4S,Vn.4S uint32x4_t vclzq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VCLZQ_U8: // CLZ Vd.16B,Vn.16B uint8x16_t vclzq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VCNTQ_P8: // CNT Vd.16B,Vn.16B poly8x16_t vcntq_p8(poly8x16_t a)
+ case ARM64_INTRIN_VCNTQ_S8: // CNT Vd.16B,Vn.16B int8x16_t vcntq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCNTQ_U8: // CNT Vd.16B,Vn.16B uint8x16_t vcntq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VCVTQ_F16_S16: // SCVTF Vd.8H,Vn.8H float16x8_t vcvtq_f16_s16(int16x8_t a)
+ // case ARM64_INTRIN_VCVTQ_F16_S16: // SCVTF Vd.8H,Vn.8H,#0 float16x8_t vcvtq_f16_s16(int16x8_t a)
+ case ARM64_INTRIN_VCVTQ_F16_U16: // UCVTF Vd.8H,Vn.8H float16x8_t vcvtq_f16_u16(uint16x8_t a)
+ case ARM64_INTRIN_VCVTQ_F32_S32: // SCVTF Vd.4S,Vn.4S float32x4_t vcvtq_f32_s32(int32x4_t a)
+ case ARM64_INTRIN_VCVTQ_F32_U32: // UCVTF Vd.4S,Vn.4S float32x4_t vcvtq_f32_u32(uint32x4_t a)
+ case ARM64_INTRIN_VCVTQ_F64_S64: // SCVTF Vd.2D,Vn.2D float64x2_t vcvtq_f64_s64(int64x2_t a)
+ case ARM64_INTRIN_VCVTQ_F64_U64: // UCVTF Vd.2D,Vn.2D float64x2_t vcvtq_f64_u64(uint64x2_t a)
+ case ARM64_INTRIN_VGET_HIGH_P16: // DUP Vd.1D,Vn.D[1] poly16x4_t vget_high_p16(poly16x8_t a)
+ case ARM64_INTRIN_VGET_HIGH_P64: // DUP Vd.1D,Vn.D[1] poly64x1_t vget_high_p64(poly64x2_t a)
+ case ARM64_INTRIN_VGET_HIGH_P8: // DUP Vd.1D,Vn.D[1] poly8x8_t vget_high_p8(poly8x16_t a)
+ case ARM64_INTRIN_VGET_HIGH_S16: // DUP Vd.1D,Vn.D[1] int16x4_t vget_high_s16(int16x8_t a)
+ case ARM64_INTRIN_VGET_HIGH_S32: // DUP Vd.1D,Vn.D[1] int32x2_t vget_high_s32(int32x4_t a)
+ case ARM64_INTRIN_VGET_HIGH_S64: // DUP Vd.1D,Vn.D[1] int64x1_t vget_high_s64(int64x2_t a)
+ case ARM64_INTRIN_VGET_HIGH_S8: // DUP Vd.1D,Vn.D[1] int8x8_t vget_high_s8(int8x16_t a)
+ case ARM64_INTRIN_VGET_HIGH_U16: // DUP Vd.1D,Vn.D[1] uint16x4_t vget_high_u16(uint16x8_t a)
+ case ARM64_INTRIN_VGET_HIGH_U32: // DUP Vd.1D,Vn.D[1] uint32x2_t vget_high_u32(uint32x4_t a)
+ case ARM64_INTRIN_VGET_HIGH_U64: // DUP Vd.1D,Vn.D[1] uint64x1_t vget_high_u64(uint64x2_t a)
+ case ARM64_INTRIN_VGET_HIGH_U8: // DUP Vd.1D,Vn.D[1] uint8x8_t vget_high_u8(uint8x16_t a)
+ case ARM64_INTRIN_VGET_LOW_P16: // DUP Vd.1D,Vn.D[0] poly16x4_t vget_low_p16(poly16x8_t a)
+ case ARM64_INTRIN_VGET_LOW_P64: // DUP Vd.1D,Vn.D[0] poly64x1_t vget_low_p64(poly64x2_t a)
+ case ARM64_INTRIN_VGET_LOW_P8: // DUP Vd.1D,Vn.D[0] poly8x8_t vget_low_p8(poly8x16_t a)
+ case ARM64_INTRIN_VGET_LOW_S16: // DUP Vd.1D,Vn.D[0] int16x4_t vget_low_s16(int16x8_t a)
+ case ARM64_INTRIN_VGET_LOW_S32: // DUP Vd.1D,Vn.D[0] int32x2_t vget_low_s32(int32x4_t a)
+ case ARM64_INTRIN_VGET_LOW_S64: // DUP Vd.1D,Vn.D[0] int64x1_t vget_low_s64(int64x2_t a)
+ case ARM64_INTRIN_VGET_LOW_S8: // DUP Vd.1D,Vn.D[0] int8x8_t vget_low_s8(int8x16_t a)
+ case ARM64_INTRIN_VGET_LOW_U16: // DUP Vd.1D,Vn.D[0] uint16x4_t vget_low_u16(uint16x8_t a)
+ case ARM64_INTRIN_VGET_LOW_U32: // DUP Vd.1D,Vn.D[0] uint32x2_t vget_low_u32(uint32x4_t a)
+ case ARM64_INTRIN_VGET_LOW_U64: // DUP Vd.1D,Vn.D[0] uint64x1_t vget_low_u64(uint64x2_t a)
+ case ARM64_INTRIN_VGET_LOW_U8: // DUP Vd.1D,Vn.D[0] uint8x8_t vget_low_u8(uint8x16_t a)
+ case ARM64_INTRIN_VMAXVQ_S16: // SMAXV Hd,Vn.8H int16_t vmaxvq_s16(int16x8_t a)
+ case ARM64_INTRIN_VMAXVQ_S32: // SMAXV Sd,Vn.4S int32_t vmaxvq_s32(int32x4_t a)
+ case ARM64_INTRIN_VMAXVQ_S8: // SMAXV Bd,Vn.16B int8_t vmaxvq_s8(int8x16_t a)
+ case ARM64_INTRIN_VMAXVQ_U16: // UMAXV Hd,Vn.8H uint16_t vmaxvq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VMAXVQ_U32: // UMAXV Sd,Vn.4S uint32_t vmaxvq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VMAXVQ_U8: // UMAXV Bd,Vn.16B uint8_t vmaxvq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VMINVQ_S16: // SMINV Hd,Vn.8H int16_t vminvq_s16(int16x8_t a)
+ case ARM64_INTRIN_VMINVQ_S32: // SMINV Sd,Vn.4S int32_t vminvq_s32(int32x4_t a)
+ case ARM64_INTRIN_VMINVQ_S8: // SMINV Bd,Vn.16B int8_t vminvq_s8(int8x16_t a)
+ case ARM64_INTRIN_VMINVQ_U16: // UMINV Hd,Vn.8H uint16_t vminvq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VMINVQ_U32: // UMINV Sd,Vn.4S uint32_t vminvq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VMINVQ_U8: // UMINV Bd,Vn.16B uint8_t vminvq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VMOVL_HIGH_S16: // SSHLL2 Vd.4S,Vn.8H,#0 int32x4_t vmovl_high_s16(int16x8_t a)
+ case ARM64_INTRIN_VMOVL_HIGH_S32: // SSHLL2 Vd.2D,Vn.4S,#0 int64x2_t vmovl_high_s32(int32x4_t a)
+ case ARM64_INTRIN_VMOVL_HIGH_S8: // SSHLL2 Vd.8H,Vn.16B,#0 int16x8_t vmovl_high_s8(int8x16_t a)
+ case ARM64_INTRIN_VMOVL_HIGH_U16: // USHLL2 Vd.4S,Vn.8H,#0 uint32x4_t vmovl_high_u16(uint16x8_t a)
+ case ARM64_INTRIN_VMOVL_HIGH_U32: // USHLL2 Vd.2D,Vn.4S,#0 uint64x2_t vmovl_high_u32(uint32x4_t a)
+ case ARM64_INTRIN_VMOVL_HIGH_U8: // USHLL2 Vd.8H,Vn.16B,#0 uint16x8_t vmovl_high_u8(uint8x16_t a)
+ case ARM64_INTRIN_VMOVN_S16: // XTN Vd.8B,Vn.8H int8x8_t vmovn_s16(int16x8_t a)
+ case ARM64_INTRIN_VMOVN_S32: // XTN Vd.4H,Vn.4S int16x4_t vmovn_s32(int32x4_t a)
+ case ARM64_INTRIN_VMOVN_S64: // XTN Vd.2S,Vn.2D int32x2_t vmovn_s64(int64x2_t a)
+ case ARM64_INTRIN_VMOVN_U16: // XTN Vd.8B,Vn.8H uint8x8_t vmovn_u16(uint16x8_t a)
+ case ARM64_INTRIN_VMOVN_U32: // XTN Vd.4H,Vn.4S uint16x4_t vmovn_u32(uint32x4_t a)
+ case ARM64_INTRIN_VMOVN_U64: // XTN Vd.2S,Vn.2D uint32x2_t vmovn_u64(uint64x2_t a)
+ case ARM64_INTRIN_VMVNQ_P8: // MVN Vd.16B,Vn.16B poly8x16_t vmvnq_p8(poly8x16_t a)
+ case ARM64_INTRIN_VMVNQ_S16: // MVN Vd.16B,Vn.16B int16x8_t vmvnq_s16(int16x8_t a)
+ case ARM64_INTRIN_VMVNQ_S32: // MVN Vd.16B,Vn.16B int32x4_t vmvnq_s32(int32x4_t a)
+ case ARM64_INTRIN_VMVNQ_S8: // MVN Vd.16B,Vn.16B int8x16_t vmvnq_s8(int8x16_t a)
+ case ARM64_INTRIN_VMVNQ_U16: // MVN Vd.16B,Vn.16B uint16x8_t vmvnq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VMVNQ_U32: // MVN Vd.16B,Vn.16B uint32x4_t vmvnq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VMVNQ_U8: // MVN Vd.16B,Vn.16B uint8x16_t vmvnq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VNEGQ_S16: // NEG Vd.8H,Vn.8H int16x8_t vnegq_s16(int16x8_t a)
+ case ARM64_INTRIN_VNEGQ_S32: // NEG Vd.4S,Vn.4S int32x4_t vnegq_s32(int32x4_t a)
+ case ARM64_INTRIN_VNEGQ_S64: // NEG Vd.2D,Vn.2D int64x2_t vnegq_s64(int64x2_t a)
+ case ARM64_INTRIN_VNEGQ_S8: // NEG Vd.16B,Vn.16B int8x16_t vnegq_s8(int8x16_t a)
+ case ARM64_INTRIN_VPADDD_S64: // ADDP Dd,Vn.2D int64_t vpaddd_s64(int64x2_t a)
+ case ARM64_INTRIN_VPADDD_U64: // ADDP Dd,Vn.2D uint64_t vpaddd_u64(uint64x2_t a)
+ case ARM64_INTRIN_VPADDLQ_S16: // SADDLP Vd.4S,Vn.8H int32x4_t vpaddlq_s16(int16x8_t a)
+ case ARM64_INTRIN_VPADDLQ_S32: // SADDLP Vd.2D,Vn.4S int64x2_t vpaddlq_s32(int32x4_t a)
+ case ARM64_INTRIN_VPADDLQ_S8: // SADDLP Vd.8H,Vn.16B int16x8_t vpaddlq_s8(int8x16_t a)
+ case ARM64_INTRIN_VPADDLQ_U16: // UADDLP Vd.4S,Vn.8H uint32x4_t vpaddlq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VPADDLQ_U32: // UADDLP Vd.2D,Vn.4S uint64x2_t vpaddlq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VPADDLQ_U8: // UADDLP Vd.8H,Vn.16B uint16x8_t vpaddlq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VQABSQ_S16: // SQABS Vd.8H,Vn.8H int16x8_t vqabsq_s16(int16x8_t a)
+ case ARM64_INTRIN_VQABSQ_S32: // SQABS Vd.4S,Vn.4S int32x4_t vqabsq_s32(int32x4_t a)
+ case ARM64_INTRIN_VQABSQ_S64: // SQABS Vd.2D,Vn.2D int64x2_t vqabsq_s64(int64x2_t a)
+ case ARM64_INTRIN_VQABSQ_S8: // SQABS Vd.16B,Vn.16B int8x16_t vqabsq_s8(int8x16_t a)
+ case ARM64_INTRIN_VQMOVN_S16: // SQXTN Vd.8B,Vn.8H int8x8_t vqmovn_s16(int16x8_t a)
+ case ARM64_INTRIN_VQMOVN_S32: // SQXTN Vd.4H,Vn.4S int16x4_t vqmovn_s32(int32x4_t a)
+ case ARM64_INTRIN_VQMOVN_S64: // SQXTN Vd.2S,Vn.2D int32x2_t vqmovn_s64(int64x2_t a)
+ case ARM64_INTRIN_VQMOVN_U16: // UQXTN Vd.8B,Vn.8H uint8x8_t vqmovn_u16(uint16x8_t a)
+ case ARM64_INTRIN_VQMOVN_U32: // UQXTN Vd.4H,Vn.4S uint16x4_t vqmovn_u32(uint32x4_t a)
+ case ARM64_INTRIN_VQMOVN_U64: // UQXTN Vd.2S,Vn.2D uint32x2_t vqmovn_u64(uint64x2_t a)
+ case ARM64_INTRIN_VQMOVUN_S16: // SQXTUN Vd.8B,Vn.8H uint8x8_t vqmovun_s16(int16x8_t a)
+ case ARM64_INTRIN_VQMOVUN_S32: // SQXTUN Vd.4H,Vn.4S uint16x4_t vqmovun_s32(int32x4_t a)
+ case ARM64_INTRIN_VQMOVUN_S64: // SQXTUN Vd.2S,Vn.2D uint32x2_t vqmovun_s64(int64x2_t a)
+ case ARM64_INTRIN_VQNEGQ_S16: // SQNEG Vd.8H,Vn.8H int16x8_t vqnegq_s16(int16x8_t a)
+ case ARM64_INTRIN_VQNEGQ_S32: // SQNEG Vd.4S,Vn.4S int32x4_t vqnegq_s32(int32x4_t a)
+ case ARM64_INTRIN_VQNEGQ_S64: // SQNEG Vd.2D,Vn.2D int64x2_t vqnegq_s64(int64x2_t a)
+ case ARM64_INTRIN_VQNEGQ_S8: // SQNEG Vd.16B,Vn.16B int8x16_t vqnegq_s8(int8x16_t a)
+ case ARM64_INTRIN_VRBITQ_P8: // RBIT Vd.16B,Vn.16B poly8x16_t vrbitq_p8(poly8x16_t a)
+ case ARM64_INTRIN_VRBITQ_S8: // RBIT Vd.16B,Vn.16B int8x16_t vrbitq_s8(int8x16_t a)
+ case ARM64_INTRIN_VRBITQ_U8: // RBIT Vd.16B,Vn.16B uint8x16_t vrbitq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VRECPEQ_U32: // URECPE Vd.4S,Vn.4S uint32x4_t vrecpeq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VREV16Q_P8: // REV16 Vd.16B,Vn.16B poly8x16_t vrev16q_p8(poly8x16_t vec)
+ case ARM64_INTRIN_VREV16Q_S8: // REV16 Vd.16B,Vn.16B int8x16_t vrev16q_s8(int8x16_t vec)
+ case ARM64_INTRIN_VREV16Q_U8: // REV16 Vd.16B,Vn.16B uint8x16_t vrev16q_u8(uint8x16_t vec)
+ case ARM64_INTRIN_VREV32Q_P16: // REV32 Vd.8H,Vn.8H poly16x8_t vrev32q_p16(poly16x8_t vec)
+ case ARM64_INTRIN_VREV32Q_P8: // REV32 Vd.16B,Vn.16B poly8x16_t vrev32q_p8(poly8x16_t vec)
+ case ARM64_INTRIN_VREV32Q_S16: // REV32 Vd.8H,Vn.8H int16x8_t vrev32q_s16(int16x8_t vec)
+ case ARM64_INTRIN_VREV32Q_S8: // REV32 Vd.16B,Vn.16B int8x16_t vrev32q_s8(int8x16_t vec)
+ case ARM64_INTRIN_VREV32Q_U16: // REV32 Vd.8H,Vn.8H uint16x8_t vrev32q_u16(uint16x8_t vec)
+ case ARM64_INTRIN_VREV32Q_U8: // REV32 Vd.16B,Vn.16B uint8x16_t vrev32q_u8(uint8x16_t vec)
+ case ARM64_INTRIN_VREV64Q_P16: // REV64 Vd.8H,Vn.8H poly16x8_t vrev64q_p16(poly16x8_t vec)
+ case ARM64_INTRIN_VREV64Q_P8: // REV64 Vd.16B,Vn.16B poly8x16_t vrev64q_p8(poly8x16_t vec)
+ case ARM64_INTRIN_VREV64Q_S16: // REV64 Vd.8H,Vn.8H int16x8_t vrev64q_s16(int16x8_t vec)
+ case ARM64_INTRIN_VREV64Q_S32: // REV64 Vd.4S,Vn.4S int32x4_t vrev64q_s32(int32x4_t vec)
+ case ARM64_INTRIN_VREV64Q_S8: // REV64 Vd.16B,Vn.16B int8x16_t vrev64q_s8(int8x16_t vec)
+ case ARM64_INTRIN_VREV64Q_U16: // REV64 Vd.8H,Vn.8H uint16x8_t vrev64q_u16(uint16x8_t vec)
+ case ARM64_INTRIN_VREV64Q_U32: // REV64 Vd.4S,Vn.4S uint32x4_t vrev64q_u32(uint32x4_t vec)
+ case ARM64_INTRIN_VREV64Q_U8: // REV64 Vd.16B,Vn.16B uint8x16_t vrev64q_u8(uint8x16_t vec)
+ case ARM64_INTRIN_VRSQRTEQ_U32: // URSQRTE Vd.4S,Vn.4S uint32x4_t vrsqrteq_u32(uint32x4_t a)
+ return {NameAndType(Type::IntegerType(16, false))};
+ case ARM64_INTRIN_VBSLQ_F16: // BSL Vd.16B,Vn.16B,Vm.16B float16x8_t vbslq_f16(uint16x8_t a, float16x8_t b, float16x8_t c)
+ case ARM64_INTRIN_VBSLQ_F32: // BSL Vd.16B,Vn.16B,Vm.16B float32x4_t vbslq_f32(uint32x4_t a, float32x4_t b, float32x4_t c)
+ case ARM64_INTRIN_VBSLQ_F64: // BSL Vd.16B,Vn.16B,Vm.16B float64x2_t vbslq_f64(uint64x2_t a, float64x2_t b, float64x2_t c)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::FloatType(16)), NameAndType(Type::FloatType(16))};
+ case ARM64_INTRIN_VABDL_HIGH_S16: // SABDL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vabdl_high_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VABDL_HIGH_S32: // SABDL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vabdl_high_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VABDL_HIGH_S8: // SABDL2 Vd.8H,Vn.16B,Vm.16B int16x8_t vabdl_high_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VABDL_HIGH_U16: // UABDL2 Vd.4S,Vn.8H,Vm.8H uint32x4_t vabdl_high_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VABDL_HIGH_U32: // UABDL2 Vd.2D,Vn.4S,Vm.4S uint64x2_t vabdl_high_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VABDL_HIGH_U8: // UABDL2 Vd.8H,Vn.16B,Vm.16B uint16x8_t vabdl_high_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VABDQ_S16: // SABD Vd.8H,Vn.8H,Vm.8H int16x8_t vabdq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VABDQ_S32: // SABD Vd.4S,Vn.4S,Vm.4S int32x4_t vabdq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VABDQ_S8: // SABD Vd.16B,Vn.16B,Vm.16B int8x16_t vabdq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VABDQ_U16: // UABD Vd.8H,Vn.8H,Vm.8H uint16x8_t vabdq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VABDQ_U32: // UABD Vd.4S,Vn.4S,Vm.4S uint32x4_t vabdq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VABDQ_U8: // UABD Vd.16B,Vn.16B,Vm.16B uint8x16_t vabdq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VADDHN_S16: // ADDHN Vd.8B,Vn.8H,Vm.8H int8x8_t vaddhn_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VADDHN_S32: // ADDHN Vd.4H,Vn.4S,Vm.4S int16x4_t vaddhn_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VADDHN_S64: // ADDHN Vd.2S,Vn.2D,Vm.2D int32x2_t vaddhn_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VADDHN_U16: // ADDHN Vd.8B,Vn.8H,Vm.8H uint8x8_t vaddhn_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VADDHN_U32: // ADDHN Vd.4H,Vn.4S,Vm.4S uint16x4_t vaddhn_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VADDHN_U64: // ADDHN Vd.2S,Vn.2D,Vm.2D uint32x2_t vaddhn_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VADDL_HIGH_S16: // SADDL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vaddl_high_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VADDL_HIGH_S32: // SADDL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vaddl_high_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VADDL_HIGH_S8: // SADDL2 Vd.8H,Vn.16B,Vm.16B int16x8_t vaddl_high_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VADDL_HIGH_U16: // UADDL2 Vd.4S,Vn.8H,Vm.8H uint32x4_t vaddl_high_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VADDL_HIGH_U32: // UADDL2 Vd.2D,Vn.4S,Vm.4S uint64x2_t vaddl_high_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VADDL_HIGH_U8: // UADDL2 Vd.8H,Vn.16B,Vm.16B uint16x8_t vaddl_high_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VADDQ_P128: // EOR Vd.16B,Vn.16B,Vm.16B poly128_t vaddq_p128(poly128_t a, poly128_t b)
+ case ARM64_INTRIN_VADDQ_P16: // EOR Vd.16B,Vn.16B,Vm.16B poly16x8_t vaddq_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VADDQ_P64: // EOR Vd.16B,Vn.16B,Vm.16B poly64x2_t vaddq_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VADDQ_P8: // EOR Vd.16B,Vn.16B,Vm.16B poly8x16_t vaddq_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VADDQ_S16: // ADD Vd.8H,Vn.8H,Vm.8H int16x8_t vaddq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VADDQ_S32: // ADD Vd.4S,Vn.4S,Vm.4S int32x4_t vaddq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VADDQ_S64: // ADD Vd.2D,Vn.2D,Vm.2D int64x2_t vaddq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VADDQ_S8: // ADD Vd.16B,Vn.16B,Vm.16B int8x16_t vaddq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VADDQ_U16: // ADD Vd.8H,Vn.8H,Vm.8H uint16x8_t vaddq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VADDQ_U32: // ADD Vd.4S,Vn.4S,Vm.4S uint32x4_t vaddq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VADDQ_U64: // ADD Vd.2D,Vn.2D,Vm.2D uint64x2_t vaddq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VADDQ_U8: // ADD Vd.16B,Vn.16B,Vm.16B uint8x16_t vaddq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VADDW_HIGH_S16: // SADDW2 Vd.4S,Vn.4S,Vm.8H int32x4_t vaddw_high_s16(int32x4_t a, int16x8_t b)
+ case ARM64_INTRIN_VADDW_HIGH_S32: // SADDW2 Vd.2D,Vn.2D,Vm.4S int64x2_t vaddw_high_s32(int64x2_t a, int32x4_t b)
+ case ARM64_INTRIN_VADDW_HIGH_S8: // SADDW2 Vd.8H,Vn.8H,Vm.16B int16x8_t vaddw_high_s8(int16x8_t a, int8x16_t b)
+ case ARM64_INTRIN_VADDW_HIGH_U16: // UADDW2 Vd.4S,Vn.4S,Vm.8H uint32x4_t vaddw_high_u16(uint32x4_t a, uint16x8_t b)
+ case ARM64_INTRIN_VADDW_HIGH_U32: // UADDW2 Vd.2D,Vn.2D,Vm.4S uint64x2_t vaddw_high_u32(uint64x2_t a, uint32x4_t b)
+ case ARM64_INTRIN_VADDW_HIGH_U8: // UADDW2 Vd.8H,Vn.8H,Vm.16B uint16x8_t vaddw_high_u8(uint16x8_t a, uint8x16_t b)
+ case ARM64_INTRIN_VAESDQ_U8: // AESD Vd.16B,Vn.16B uint8x16_t vaesdq_u8(uint8x16_t data, uint8x16_t key)
+ case ARM64_INTRIN_VAESEQ_U8: // AESE Vd.16B,Vn.16B uint8x16_t vaeseq_u8(uint8x16_t data, uint8x16_t key)
+ case ARM64_INTRIN_VANDQ_S16: // AND Vd.16B,Vn.16B,Vm.16B int16x8_t vandq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VANDQ_S32: // AND Vd.16B,Vn.16B,Vm.16B int32x4_t vandq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VANDQ_S64: // AND Vd.16B,Vn.16B,Vm.16B int64x2_t vandq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VANDQ_S8: // AND Vd.16B,Vn.16B,Vm.16B int8x16_t vandq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VANDQ_U16: // AND Vd.16B,Vn.16B,Vm.16B uint16x8_t vandq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VANDQ_U32: // AND Vd.16B,Vn.16B,Vm.16B uint32x4_t vandq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VANDQ_U64: // AND Vd.16B,Vn.16B,Vm.16B uint64x2_t vandq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VANDQ_U8: // AND Vd.16B,Vn.16B,Vm.16B uint8x16_t vandq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VBICQ_S16: // BIC Vd.16B,Vn.16B,Vm.16B int16x8_t vbicq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VBICQ_S32: // BIC Vd.16B,Vn.16B,Vm.16B int32x4_t vbicq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VBICQ_S64: // BIC Vd.16B,Vn.16B,Vm.16B int64x2_t vbicq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VBICQ_S8: // BIC Vd.16B,Vn.16B,Vm.16B int8x16_t vbicq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VBICQ_U16: // BIC Vd.16B,Vn.16B,Vm.16B uint16x8_t vbicq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VBICQ_U32: // BIC Vd.16B,Vn.16B,Vm.16B uint32x4_t vbicq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VBICQ_U64: // BIC Vd.16B,Vn.16B,Vm.16B uint64x2_t vbicq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VBICQ_U8: // BIC Vd.16B,Vn.16B,Vm.16B uint8x16_t vbicq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VCEQQ_P64: // CMEQ Vd.2D,Vn.2D,Vm.2D uint64x2_t vceqq_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VCEQQ_P8: // CMEQ Vd.16B,Vn.16B,Vm.16B uint8x16_t vceqq_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VCEQQ_S16: // CMEQ Vd.8H,Vn.8H,Vm.8H uint16x8_t vceqq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VCEQQ_S32: // CMEQ Vd.4S,Vn.4S,Vm.4S uint32x4_t vceqq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VCEQQ_S64: // CMEQ Vd.2D,Vn.2D,Vm.2D uint64x2_t vceqq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VCEQQ_S8: // CMEQ Vd.16B,Vn.16B,Vm.16B uint8x16_t vceqq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VCEQQ_U16: // CMEQ Vd.8H,Vn.8H,Vm.8H uint16x8_t vceqq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VCEQQ_U32: // CMEQ Vd.4S,Vn.4S,Vm.4S uint32x4_t vceqq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VCEQQ_U64: // CMEQ Vd.2D,Vn.2D,Vm.2D uint64x2_t vceqq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VCEQQ_U8: // CMEQ Vd.16B,Vn.16B,Vm.16B uint8x16_t vceqq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VCGEQ_S16: // CMGE Vd.8H,Vm.8H,Vn.8H uint16x8_t vcgeq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VCGEQ_S32: // CMGE Vd.4S,Vm.4S,Vn.4S uint32x4_t vcgeq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VCGEQ_S64: // CMGE Vd.2D,Vm.2D,Vn.2D uint64x2_t vcgeq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VCGEQ_S8: // CMGE Vd.16B,Vm.16B,Vn.16B uint8x16_t vcgeq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VCGEQ_U16: // CMHS Vd.8H,Vm.8H,Vn.8H uint16x8_t vcgeq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VCGEQ_U32: // CMHS Vd.4S,Vm.4S,Vn.4S uint32x4_t vcgeq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VCGEQ_U64: // CMHS Vd.2D,Vm.2D,Vn.2D uint64x2_t vcgeq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VCGEQ_U8: // CMHS Vd.16B,Vm.16B,Vn.16B uint8x16_t vcgeq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VCGTQ_S16: // CMGT Vd.8H,Vn.8H,Vm.8H uint16x8_t vcgtq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VCGTQ_S32: // CMGT Vd.4S,Vn.4S,Vm.4S uint32x4_t vcgtq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VCGTQ_S64: // CMGT Vd.2D,Vn.2D,Vm.2D uint64x2_t vcgtq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VCGTQ_S8: // CMGT Vd.16B,Vn.16B,Vm.16B uint8x16_t vcgtq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VCGTQ_U16: // CMHI Vd.8H,Vn.8H,Vm.8H uint16x8_t vcgtq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VCGTQ_U32: // CMHI Vd.4S,Vn.4S,Vm.4S uint32x4_t vcgtq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VCGTQ_U64: // CMHI Vd.2D,Vn.2D,Vm.2D uint64x2_t vcgtq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VCGTQ_U8: // CMHI Vd.16B,Vn.16B,Vm.16B uint8x16_t vcgtq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VCLEQ_S16: // CMGE Vd.8H,Vm.8H,Vn.8H uint16x8_t vcleq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VCLEQ_S32: // CMGE Vd.4S,Vm.4S,Vn.4S uint32x4_t vcleq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VCLEQ_S64: // CMGE Vd.2D,Vm.2D,Vn.2D uint64x2_t vcleq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VCLEQ_S8: // CMGE Vd.16B,Vm.16B,Vn.16B uint8x16_t vcleq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VCLEQ_U16: // CMHS Vd.8H,Vm.8H,Vn.8H uint16x8_t vcleq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VCLEQ_U32: // CMHS Vd.4S,Vm.4S,Vn.4S uint32x4_t vcleq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VCLEQ_U64: // CMHS Vd.2D,Vm.2D,Vn.2D uint64x2_t vcleq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VCLEQ_U8: // CMHS Vd.16B,Vm.16B,Vn.16B uint8x16_t vcleq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VCLTQ_S16: // CMGT Vd.8H,Vm.8H,Vn.8H uint16x8_t vcltq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VCLTQ_S32: // CMGT Vd.4S,Vm.4S,Vn.4S uint32x4_t vcltq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VCLTQ_S64: // CMGT Vd.2D,Vm.2D,Vn.2D uint64x2_t vcltq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VCLTQ_S8: // CMGT Vd.16B,Vm.16B,Vn.16B uint8x16_t vcltq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VCLTQ_U16: // CMHI Vd.8H,Vm.8H,Vn.8H uint16x8_t vcltq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VCLTQ_U32: // CMHI Vd.4S,Vm.4S,Vn.4S uint32x4_t vcltq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VCLTQ_U64: // CMHI Vd.2D,Vm.2D,Vn.2D uint64x2_t vcltq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VCLTQ_U8: // CMHI Vd.16B,Vm.16B,Vn.16B uint8x16_t vcltq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VEORQ_S16: // EOR Vd.16B,Vn.16B,Vm.16B int16x8_t veorq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VEORQ_S32: // EOR Vd.16B,Vn.16B,Vm.16B int32x4_t veorq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VEORQ_S64: // EOR Vd.16B,Vn.16B,Vm.16B int64x2_t veorq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VEORQ_S8: // EOR Vd.16B,Vn.16B,Vm.16B int8x16_t veorq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VEORQ_U16: // EOR Vd.16B,Vn.16B,Vm.16B uint16x8_t veorq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VEORQ_U32: // EOR Vd.16B,Vn.16B,Vm.16B uint32x4_t veorq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VEORQ_U64: // EOR Vd.16B,Vn.16B,Vm.16B uint64x2_t veorq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VEORQ_U8: // EOR Vd.16B,Vn.16B,Vm.16B uint8x16_t veorq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VHADDQ_S16: // SHADD Vd.8H,Vn.8H,Vm.8H int16x8_t vhaddq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VHADDQ_S32: // SHADD Vd.4S,Vn.4S,Vm.4S int32x4_t vhaddq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VHADDQ_S8: // SHADD Vd.16B,Vn.16B,Vm.16B int8x16_t vhaddq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VHADDQ_U16: // UHADD Vd.8H,Vn.8H,Vm.8H uint16x8_t vhaddq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VHADDQ_U32: // UHADD Vd.4S,Vn.4S,Vm.4S uint32x4_t vhaddq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VHADDQ_U8: // UHADD Vd.16B,Vn.16B,Vm.16B uint8x16_t vhaddq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VHSUBQ_S16: // SHSUB Vd.8H,Vn.8H,Vm.8H int16x8_t vhsubq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VHSUBQ_S32: // SHSUB Vd.4S,Vn.4S,Vm.4S int32x4_t vhsubq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VHSUBQ_S8: // SHSUB Vd.16B,Vn.16B,Vm.16B int8x16_t vhsubq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VHSUBQ_U16: // UHSUB Vd.8H,Vn.8H,Vm.8H uint16x8_t vhsubq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VHSUBQ_U32: // UHSUB Vd.4S,Vn.4S,Vm.4S uint32x4_t vhsubq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VHSUBQ_U8: // UHSUB Vd.16B,Vn.16B,Vm.16B uint8x16_t vhsubq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VMAXQ_S16: // SMAX Vd.8H,Vn.8H,Vm.8H int16x8_t vmaxq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VMAXQ_S32: // SMAX Vd.4S,Vn.4S,Vm.4S int32x4_t vmaxq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VMAXQ_S8: // SMAX Vd.16B,Vn.16B,Vm.16B int8x16_t vmaxq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VMAXQ_U16: // UMAX Vd.8H,Vn.8H,Vm.8H uint16x8_t vmaxq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VMAXQ_U32: // UMAX Vd.4S,Vn.4S,Vm.4S uint32x4_t vmaxq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VMAXQ_U8: // UMAX Vd.16B,Vn.16B,Vm.16B uint8x16_t vmaxq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VMINQ_S16: // SMIN Vd.8H,Vn.8H,Vm.8H int16x8_t vminq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VMINQ_S32: // SMIN Vd.4S,Vn.4S,Vm.4S int32x4_t vminq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VMINQ_S8: // SMIN Vd.16B,Vn.16B,Vm.16B int8x16_t vminq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VMINQ_U16: // UMIN Vd.8H,Vn.8H,Vm.8H uint16x8_t vminq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VMINQ_U32: // UMIN Vd.4S,Vn.4S,Vm.4S uint32x4_t vminq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VMINQ_U8: // UMIN Vd.16B,Vn.16B,Vm.16B uint8x16_t vminq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VMULL_HIGH_P64: // PMULL2 Vd.1Q,Vn.2D,Vm.2D poly128_t vmull_high_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VMULL_HIGH_P8: // PMULL2 Vd.8H,Vn.16B,Vm.16B poly16x8_t vmull_high_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VMULL_HIGH_S16: // SMULL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vmull_high_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VMULL_HIGH_S32: // SMULL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vmull_high_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VMULL_HIGH_S8: // SMULL2 Vd.8H,Vn.16B,Vm.16B int16x8_t vmull_high_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VMULL_HIGH_U16: // UMULL2 Vd.4S,Vn.8H,Vm.8H uint32x4_t vmull_high_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VMULL_HIGH_U32: // UMULL2 Vd.2D,Vn.4S,Vm.4S uint64x2_t vmull_high_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VMULL_HIGH_U8: // UMULL2 Vd.8H,Vn.16B,Vm.16B uint16x8_t vmull_high_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VMULQ_P8: // PMUL Vd.16B,Vn.16B,Vm.16B poly8x16_t vmulq_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VMULQ_S16: // MUL Vd.8H,Vn.8H,Vm.8H int16x8_t vmulq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VMULQ_S32: // MUL Vd.4S,Vn.4S,Vm.4S int32x4_t vmulq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VMULQ_S8: // MUL Vd.16B,Vn.16B,Vm.16B int8x16_t vmulq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VMULQ_U16: // MUL Vd.8H,Vn.8H,Vm.8H uint16x8_t vmulq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VMULQ_U32: // MUL Vd.4S,Vn.4S,Vm.4S uint32x4_t vmulq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VMULQ_U8: // MUL Vd.16B,Vn.16B,Vm.16B uint8x16_t vmulq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VORNQ_S16: // ORN Vd.16B,Vn.16B,Vm.16B int16x8_t vornq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VORNQ_S32: // ORN Vd.16B,Vn.16B,Vm.16B int32x4_t vornq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VORNQ_S64: // ORN Vd.16B,Vn.16B,Vm.16B int64x2_t vornq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VORNQ_S8: // ORN Vd.16B,Vn.16B,Vm.16B int8x16_t vornq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VORNQ_U16: // ORN Vd.16B,Vn.16B,Vm.16B uint16x8_t vornq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VORNQ_U32: // ORN Vd.16B,Vn.16B,Vm.16B uint32x4_t vornq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VORNQ_U64: // ORN Vd.16B,Vn.16B,Vm.16B uint64x2_t vornq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VORNQ_U8: // ORN Vd.16B,Vn.16B,Vm.16B uint8x16_t vornq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VORRQ_S16: // ORR Vd.16B,Vn.16B,Vm.16B int16x8_t vorrq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VORRQ_S32: // ORR Vd.16B,Vn.16B,Vm.16B int32x4_t vorrq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VORRQ_S64: // ORR Vd.16B,Vn.16B,Vm.16B int64x2_t vorrq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VORRQ_S8: // ORR Vd.16B,Vn.16B,Vm.16B int8x16_t vorrq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VORRQ_U16: // ORR Vd.16B,Vn.16B,Vm.16B uint16x8_t vorrq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VORRQ_U32: // ORR Vd.16B,Vn.16B,Vm.16B uint32x4_t vorrq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VORRQ_U64: // ORR Vd.16B,Vn.16B,Vm.16B uint64x2_t vorrq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VORRQ_U8: // ORR Vd.16B,Vn.16B,Vm.16B uint8x16_t vorrq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VPADALQ_S16: // SADALP Vd.4S,Vn.8H int32x4_t vpadalq_s16(int32x4_t a, int16x8_t b)
+ case ARM64_INTRIN_VPADALQ_S32: // SADALP Vd.2D,Vn.4S int64x2_t vpadalq_s32(int64x2_t a, int32x4_t b)
+ case ARM64_INTRIN_VPADALQ_S8: // SADALP Vd.8H,Vn.16B int16x8_t vpadalq_s8(int16x8_t a, int8x16_t b)
+ case ARM64_INTRIN_VPADALQ_U16: // UADALP Vd.4S,Vn.8H uint32x4_t vpadalq_u16(uint32x4_t a, uint16x8_t b)
+ case ARM64_INTRIN_VPADALQ_U32: // UADALP Vd.2D,Vn.4S uint64x2_t vpadalq_u32(uint64x2_t a, uint32x4_t b)
+ case ARM64_INTRIN_VPADALQ_U8: // UADALP Vd.8H,Vn.16B uint16x8_t vpadalq_u8(uint16x8_t a, uint8x16_t b)
+ case ARM64_INTRIN_VPADDQ_S16: // ADDP Vd.8H,Vn.8H,Vm.8H int16x8_t vpaddq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VPADDQ_S32: // ADDP Vd.4S,Vn.4S,Vm.4S int32x4_t vpaddq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VPADDQ_S64: // ADDP Vd.2D,Vn.2D,Vm.2D int64x2_t vpaddq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VPADDQ_S8: // ADDP Vd.16B,Vn.16B,Vm.16B int8x16_t vpaddq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VPADDQ_U16: // ADDP Vd.8H,Vn.8H,Vm.8H uint16x8_t vpaddq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VPADDQ_U32: // ADDP Vd.4S,Vn.4S,Vm.4S uint32x4_t vpaddq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VPADDQ_U64: // ADDP Vd.2D,Vn.2D,Vm.2D uint64x2_t vpaddq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VPADDQ_U8: // ADDP Vd.16B,Vn.16B,Vm.16B uint8x16_t vpaddq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VPMAXQ_S16: // SMAXP Vd.8H,Vn.8H,Vm.8H int16x8_t vpmaxq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VPMAXQ_S32: // SMAXP Vd.4S,Vn.4S,Vm.4S int32x4_t vpmaxq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VPMAXQ_S8: // SMAXP Vd.16B,Vn.16B,Vm.16B int8x16_t vpmaxq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VPMAXQ_U16: // UMAXP Vd.8H,Vn.8H,Vm.8H uint16x8_t vpmaxq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VPMAXQ_U32: // UMAXP Vd.4S,Vn.4S,Vm.4S uint32x4_t vpmaxq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VPMAXQ_U8: // UMAXP Vd.16B,Vn.16B,Vm.16B uint8x16_t vpmaxq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VPMINQ_S16: // SMINP Vd.8H,Vn.8H,Vm.8H int16x8_t vpminq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VPMINQ_S32: // SMINP Vd.4S,Vn.4S,Vm.4S int32x4_t vpminq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VPMINQ_S8: // SMINP Vd.16B,Vn.16B,Vm.16B int8x16_t vpminq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VPMINQ_U16: // UMINP Vd.8H,Vn.8H,Vm.8H uint16x8_t vpminq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VPMINQ_U32: // UMINP Vd.4S,Vn.4S,Vm.4S uint32x4_t vpminq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VPMINQ_U8: // UMINP Vd.16B,Vn.16B,Vm.16B uint8x16_t vpminq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VQADDQ_S16: // SQADD Vd.8H,Vn.8H,Vm.8H int16x8_t vqaddq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQADDQ_S32: // SQADD Vd.4S,Vn.4S,Vm.4S int32x4_t vqaddq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQADDQ_S64: // SQADD Vd.2D,Vn.2D,Vm.2D int64x2_t vqaddq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VQADDQ_S8: // SQADD Vd.16B,Vn.16B,Vm.16B int8x16_t vqaddq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VQADDQ_U16: // UQADD Vd.8H,Vn.8H,Vm.8H uint16x8_t vqaddq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VQADDQ_U32: // UQADD Vd.4S,Vn.4S,Vm.4S uint32x4_t vqaddq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VQADDQ_U64: // UQADD Vd.2D,Vn.2D,Vm.2D uint64x2_t vqaddq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VQADDQ_U8: // UQADD Vd.16B,Vn.16B,Vm.16B uint8x16_t vqaddq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VQDMULHQ_S16: // SQDMULH Vd.8H,Vn.8H,Vm.8H int16x8_t vqdmulhq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQDMULHQ_S32: // SQDMULH Vd.4S,Vn.4S,Vm.4S int32x4_t vqdmulhq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQDMULL_HIGH_S16: // SQDMULL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vqdmull_high_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQDMULL_HIGH_S32: // SQDMULL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vqdmull_high_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQRDMULHQ_S16: // SQRDMULH Vd.8H,Vn.8H,Vm.8H int16x8_t vqrdmulhq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQRDMULHQ_S32: // SQRDMULH Vd.4S,Vn.4S,Vm.4S int32x4_t vqrdmulhq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQRSHLQ_S16: // SQRSHL Vd.8H,Vn.8H,Vm.8H int16x8_t vqrshlq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQRSHLQ_S32: // SQRSHL Vd.4S,Vn.4S,Vm.4S int32x4_t vqrshlq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQRSHLQ_S64: // SQRSHL Vd.2D,Vn.2D,Vm.2D int64x2_t vqrshlq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VQRSHLQ_S8: // SQRSHL Vd.16B,Vn.16B,Vm.16B int8x16_t vqrshlq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VQRSHLQ_U16: // UQRSHL Vd.8H,Vn.8H,Vm.8H uint16x8_t vqrshlq_u16(uint16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQRSHLQ_U32: // UQRSHL Vd.4S,Vn.4S,Vm.4S uint32x4_t vqrshlq_u32(uint32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQRSHLQ_U64: // UQRSHL Vd.2D,Vn.2D,Vm.2D uint64x2_t vqrshlq_u64(uint64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VQRSHLQ_U8: // UQRSHL Vd.16B,Vn.16B,Vm.16B uint8x16_t vqrshlq_u8(uint8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VQSHLQ_S16: // SQSHL Vd.8H,Vn.8H,Vm.8H int16x8_t vqshlq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQSHLQ_S32: // SQSHL Vd.4S,Vn.4S,Vm.4S int32x4_t vqshlq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQSHLQ_S64: // SQSHL Vd.2D,Vn.2D,Vm.2D int64x2_t vqshlq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VQSHLQ_S8: // SQSHL Vd.16B,Vn.16B,Vm.16B int8x16_t vqshlq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VQSHLQ_U16: // UQSHL Vd.8H,Vn.8H,Vm.8H uint16x8_t vqshlq_u16(uint16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQSHLQ_U32: // UQSHL Vd.4S,Vn.4S,Vm.4S uint32x4_t vqshlq_u32(uint32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQSHLQ_U64: // UQSHL Vd.2D,Vn.2D,Vm.2D uint64x2_t vqshlq_u64(uint64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VQSHLQ_U8: // UQSHL Vd.16B,Vn.16B,Vm.16B uint8x16_t vqshlq_u8(uint8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VQSUBQ_S16: // SQSUB Vd.8H,Vn.8H,Vm.8H int16x8_t vqsubq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQSUBQ_S32: // SQSUB Vd.4S,Vn.4S,Vm.4S int32x4_t vqsubq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQSUBQ_S64: // SQSUB Vd.2D,Vn.2D,Vm.2D int64x2_t vqsubq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VQSUBQ_S8: // SQSUB Vd.16B,Vn.16B,Vm.16B int8x16_t vqsubq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VQSUBQ_U16: // UQSUB Vd.8H,Vn.8H,Vm.8H uint16x8_t vqsubq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VQSUBQ_U32: // UQSUB Vd.4S,Vn.4S,Vm.4S uint32x4_t vqsubq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VQSUBQ_U64: // UQSUB Vd.2D,Vn.2D,Vm.2D uint64x2_t vqsubq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VQSUBQ_U8: // UQSUB Vd.16B,Vn.16B,Vm.16B uint8x16_t vqsubq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VRADDHN_S16: // RADDHN Vd.8B,Vn.8H,Vm.8H int8x8_t vraddhn_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VRADDHN_S32: // RADDHN Vd.4H,Vn.4S,Vm.4S int16x4_t vraddhn_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VRADDHN_S64: // RADDHN Vd.2S,Vn.2D,Vm.2D int32x2_t vraddhn_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VRADDHN_U16: // RADDHN Vd.8B,Vn.8H,Vm.8H uint8x8_t vraddhn_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VRADDHN_U32: // RADDHN Vd.4H,Vn.4S,Vm.4S uint16x4_t vraddhn_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VRADDHN_U64: // RADDHN Vd.2S,Vn.2D,Vm.2D uint32x2_t vraddhn_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VRAX1Q_U64: // RAX1 Vd.2D,Vn.2D,Vm.2D uint64x2_t vrax1q_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VRHADDQ_S16: // SRHADD Vd.8H,Vn.8H,Vm.8H int16x8_t vrhaddq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VRHADDQ_S32: // SRHADD Vd.4S,Vn.4S,Vm.4S int32x4_t vrhaddq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VRHADDQ_S8: // SRHADD Vd.16B,Vn.16B,Vm.16B int8x16_t vrhaddq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VRHADDQ_U16: // URHADD Vd.8H,Vn.8H,Vm.8H uint16x8_t vrhaddq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VRHADDQ_U32: // URHADD Vd.4S,Vn.4S,Vm.4S uint32x4_t vrhaddq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VRHADDQ_U8: // URHADD Vd.16B,Vn.16B,Vm.16B uint8x16_t vrhaddq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VRSHLQ_S16: // SRSHL Vd.8H,Vn.8H,Vm.8H int16x8_t vrshlq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VRSHLQ_S32: // SRSHL Vd.4S,Vn.4S,Vm.4S int32x4_t vrshlq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VRSHLQ_S64: // SRSHL Vd.2D,Vn.2D,Vm.2D int64x2_t vrshlq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VRSHLQ_S8: // SRSHL Vd.16B,Vn.16B,Vm.16B int8x16_t vrshlq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VRSHLQ_U16: // URSHL Vd.8H,Vn.8H,Vm.8H uint16x8_t vrshlq_u16(uint16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VRSHLQ_U32: // URSHL Vd.4S,Vn.4S,Vm.4S uint32x4_t vrshlq_u32(uint32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VRSHLQ_U64: // URSHL Vd.2D,Vn.2D,Vm.2D uint64x2_t vrshlq_u64(uint64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VRSHLQ_U8: // URSHL Vd.16B,Vn.16B,Vm.16B uint8x16_t vrshlq_u8(uint8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VRSUBHN_S16: // RSUBHN Vd.8B,Vn.8H,Vm.8H int8x8_t vrsubhn_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VRSUBHN_S32: // RSUBHN Vd.4H,Vn.4S,Vm.4S int16x4_t vrsubhn_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VRSUBHN_S64: // RSUBHN Vd.2S,Vn.2D,Vm.2D int32x2_t vrsubhn_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VRSUBHN_U16: // RSUBHN Vd.8B,Vn.8H,Vm.8H uint8x8_t vrsubhn_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VRSUBHN_U32: // RSUBHN Vd.4H,Vn.4S,Vm.4S uint16x4_t vrsubhn_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VRSUBHN_U64: // RSUBHN Vd.2S,Vn.2D,Vm.2D uint32x2_t vrsubhn_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VSHA1SU1Q_U32: // SHA1SU1 Vd.4S,Vn.4S uint32x4_t vsha1su1q_u32(uint32x4_t tw0_3, uint32x4_t w12_15)
+ case ARM64_INTRIN_VSHA256SU0Q_U32: // SHA256SU0 Vd.4S,Vn.4S uint32x4_t vsha256su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7)
+ case ARM64_INTRIN_VSHA512SU0Q_U64: // SHA512SU0 Vd.2D,Vn.2D uint64x2_t vsha512su0q_u64(uint64x2_t w0_1, uint64x2_t w2_)
+ case ARM64_INTRIN_VSHLQ_S16: // SSHL Vd.8H,Vn.8H,Vm.8H int16x8_t vshlq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VSHLQ_S32: // SSHL Vd.4S,Vn.4S,Vm.4S int32x4_t vshlq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VSHLQ_S64: // SSHL Vd.2D,Vn.2D,Vm.2D int64x2_t vshlq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VSHLQ_S8: // SSHL Vd.16B,Vn.16B,Vm.16B int8x16_t vshlq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VSHLQ_U16: // USHL Vd.8H,Vn.8H,Vm.8H uint16x8_t vshlq_u16(uint16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VSHLQ_U32: // USHL Vd.4S,Vn.4S,Vm.4S uint32x4_t vshlq_u32(uint32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VSHLQ_U64: // USHL Vd.2D,Vn.2D,Vm.2D uint64x2_t vshlq_u64(uint64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VSHLQ_U8: // USHL Vd.16B,Vn.16B,Vm.16B uint8x16_t vshlq_u8(uint8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VSM4EKEYQ_U32: // SM4EKEY Vd.4S,Vn.4S,Vm.4S uint32x4_t vsm4ekeyq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VSM4EQ_U32: // SM4E Vd.4S,Vn.4S uint32x4_t vsm4eq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VSQADDQ_U16: // USQADD Vd.8H,Vn.8H uint16x8_t vsqaddq_u16(uint16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VSQADDQ_U32: // USQADD Vd.4S,Vn.4S uint32x4_t vsqaddq_u32(uint32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VSQADDQ_U64: // USQADD Vd.2D,Vn.2D uint64x2_t vsqaddq_u64(uint64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VSQADDQ_U8: // USQADD Vd.16B,Vn.16B uint8x16_t vsqaddq_u8(uint8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VSUBHN_S16: // SUBHN Vd.8B,Vn.8H,Vm.8H int8x8_t vsubhn_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VSUBHN_S32: // SUBHN Vd.4H,Vn.4S,Vm.4S int16x4_t vsubhn_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VSUBHN_S64: // SUBHN Vd.2S,Vn.2D,Vm.2D int32x2_t vsubhn_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VSUBHN_U16: // SUBHN Vd.8B,Vn.8H,Vm.8H uint8x8_t vsubhn_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VSUBHN_U32: // SUBHN Vd.4H,Vn.4S,Vm.4S uint16x4_t vsubhn_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VSUBHN_U64: // SUBHN Vd.2S,Vn.2D,Vm.2D uint32x2_t vsubhn_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VSUBL_HIGH_S16: // SSUBL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vsubl_high_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VSUBL_HIGH_S32: // SSUBL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vsubl_high_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VSUBL_HIGH_S8: // SSUBL2 Vd.8H,Vn.16B,Vm.16B int16x8_t vsubl_high_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VSUBL_HIGH_U16: // USUBL2 Vd.4S,Vn.8H,Vm.8H uint32x4_t vsubl_high_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VSUBL_HIGH_U32: // USUBL2 Vd.2D,Vn.4S,Vm.4S uint64x2_t vsubl_high_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VSUBL_HIGH_U8: // USUBL2 Vd.8H,Vn.16B,Vm.16B uint16x8_t vsubl_high_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VSUBQ_S16: // SUB Vd.8H,Vn.8H,Vm.8H int16x8_t vsubq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VSUBQ_S32: // SUB Vd.4S,Vn.4S,Vm.4S int32x4_t vsubq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VSUBQ_S64: // SUB Vd.2D,Vn.2D,Vm.2D int64x2_t vsubq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VSUBQ_S8: // SUB Vd.16B,Vn.16B,Vm.16B int8x16_t vsubq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VSUBQ_U16: // SUB Vd.8H,Vn.8H,Vm.8H uint16x8_t vsubq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VSUBQ_U32: // SUB Vd.4S,Vn.4S,Vm.4S uint32x4_t vsubq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VSUBQ_U64: // SUB Vd.2D,Vn.2D,Vm.2D uint64x2_t vsubq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VSUBQ_U8: // SUB Vd.16B,Vn.16B,Vm.16B uint8x16_t vsubq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VSUBW_HIGH_S16: // SSUBW2 Vd.4S,Vn.4S,Vm.8H int32x4_t vsubw_high_s16(int32x4_t a, int16x8_t b)
+ case ARM64_INTRIN_VSUBW_HIGH_S32: // SSUBW2 Vd.2D,Vn.2D,Vm.4S int64x2_t vsubw_high_s32(int64x2_t a, int32x4_t b)
+ case ARM64_INTRIN_VSUBW_HIGH_S8: // SSUBW2 Vd.8H,Vn.8H,Vm.16B int16x8_t vsubw_high_s8(int16x8_t a, int8x16_t b)
+ case ARM64_INTRIN_VSUBW_HIGH_U16: // USUBW2 Vd.4S,Vn.4S,Vm.8H uint32x4_t vsubw_high_u16(uint32x4_t a, uint16x8_t b)
+ case ARM64_INTRIN_VSUBW_HIGH_U32: // USUBW2 Vd.2D,Vn.2D,Vm.4S uint64x2_t vsubw_high_u32(uint64x2_t a, uint32x4_t b)
+ case ARM64_INTRIN_VSUBW_HIGH_U8: // USUBW2 Vd.8H,Vn.8H,Vm.16B uint16x8_t vsubw_high_u8(uint16x8_t a, uint8x16_t b)
+ case ARM64_INTRIN_VTRN1Q_P16: // TRN1 Vd.8H,Vn.8H,Vm.8H poly16x8_t vtrn1q_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VTRN1Q_P64: // TRN1 Vd.2D,Vn.2D,Vm.2D poly64x2_t vtrn1q_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VTRN1Q_P8: // TRN1 Vd.16B,Vn.16B,Vm.16B poly8x16_t vtrn1q_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VTRN1Q_S16: // TRN1 Vd.8H,Vn.8H,Vm.8H int16x8_t vtrn1q_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VTRN1Q_S32: // TRN1 Vd.4S,Vn.4S,Vm.4S int32x4_t vtrn1q_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VTRN1Q_S64: // TRN1 Vd.2D,Vn.2D,Vm.2D int64x2_t vtrn1q_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VTRN1Q_S8: // TRN1 Vd.16B,Vn.16B,Vm.16B int8x16_t vtrn1q_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VTRN1Q_U16: // TRN1 Vd.8H,Vn.8H,Vm.8H uint16x8_t vtrn1q_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VTRN1Q_U32: // TRN1 Vd.4S,Vn.4S,Vm.4S uint32x4_t vtrn1q_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VTRN1Q_U64: // TRN1 Vd.2D,Vn.2D,Vm.2D uint64x2_t vtrn1q_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VTRN1Q_U8: // TRN1 Vd.16B,Vn.16B,Vm.16B uint8x16_t vtrn1q_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VTRN2Q_P16: // TRN2 Vd.8H,Vn.8H,Vm.8H poly16x8_t vtrn2q_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VTRN2Q_P64: // TRN2 Vd.2D,Vn.2D,Vm.2D poly64x2_t vtrn2q_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VTRN2Q_P8: // TRN2 Vd.16B,Vn.16B,Vm.16B poly8x16_t vtrn2q_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VTRN2Q_S16: // TRN2 Vd.8H,Vn.8H,Vm.8H int16x8_t vtrn2q_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VTRN2Q_S32: // TRN2 Vd.4S,Vn.4S,Vm.4S int32x4_t vtrn2q_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VTRN2Q_S64: // TRN2 Vd.2D,Vn.2D,Vm.2D int64x2_t vtrn2q_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VTRN2Q_S8: // TRN2 Vd.16B,Vn.16B,Vm.16B int8x16_t vtrn2q_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VTRN2Q_U16: // TRN2 Vd.8H,Vn.8H,Vm.8H uint16x8_t vtrn2q_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VTRN2Q_U32: // TRN2 Vd.4S,Vn.4S,Vm.4S uint32x4_t vtrn2q_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VTRN2Q_U64: // TRN2 Vd.2D,Vn.2D,Vm.2D uint64x2_t vtrn2q_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VTRN2Q_U8: // TRN2 Vd.16B,Vn.16B,Vm.16B uint8x16_t vtrn2q_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VTRNQ_P16: // TRN1 Vd1.8H,Vn.8H,Vm.8H poly16x8x2_t vtrnq_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VTRNQ_P8: // TRN1 Vd1.16B,Vn.16B,Vm.16B poly8x16x2_t vtrnq_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VTRNQ_S16: // TRN1 Vd1.8H,Vn.8H,Vm.8H int16x8x2_t vtrnq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VTRNQ_S32: // TRN1 Vd1.4S,Vn.4S,Vm.4S int32x4x2_t vtrnq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VTRNQ_S8: // TRN1 Vd1.16B,Vn.16B,Vm.16B int8x16x2_t vtrnq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VTRNQ_U16: // TRN1 Vd1.8H,Vn.8H,Vm.8H uint16x8x2_t vtrnq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VTRNQ_U32: // TRN1 Vd1.4S,Vn.4S,Vm.4S uint32x4x2_t vtrnq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VTRNQ_U8: // TRN1 Vd1.16B,Vn.16B,Vm.16B uint8x16x2_t vtrnq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VTSTQ_P64: // CMTST Vd.2D,Vn.2D,Vm.2D uint64x2_t vtstq_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VTSTQ_P8: // CMTST Vd.16B,Vn.16B,Vm.16B uint8x16_t vtstq_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VTSTQ_S16: // CMTST Vd.8H,Vn.8H,Vm.8H uint16x8_t vtstq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VTSTQ_S32: // CMTST Vd.4S,Vn.4S,Vm.4S uint32x4_t vtstq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VTSTQ_S64: // CMTST Vd.2D,Vn.2D,Vm.2D uint64x2_t vtstq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VTSTQ_S8: // CMTST Vd.16B,Vn.16B,Vm.16B uint8x16_t vtstq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VTSTQ_U16: // CMTST Vd.8H,Vn.8H,Vm.8H uint16x8_t vtstq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VTSTQ_U32: // CMTST Vd.4S,Vn.4S,Vm.4S uint32x4_t vtstq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VTSTQ_U64: // CMTST Vd.2D,Vn.2D,Vm.2D uint64x2_t vtstq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VTSTQ_U8: // CMTST Vd.16B,Vn.16B,Vm.16B uint8x16_t vtstq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VUQADDQ_S16: // SUQADD Vd.8H,Vn.8H int16x8_t vuqaddq_s16(int16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VUQADDQ_S32: // SUQADD Vd.4S,Vn.4S int32x4_t vuqaddq_s32(int32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VUQADDQ_S64: // SUQADD Vd.2D,Vn.2D int64x2_t vuqaddq_s64(int64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VUQADDQ_S8: // SUQADD Vd.16B,Vn.16B int8x16_t vuqaddq_s8(int8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VUZP1Q_P16: // UZP1 Vd.8H,Vn.8H,Vm.8H poly16x8_t vuzp1q_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VUZP1Q_P64: // UZP1 Vd.2D,Vn.2D,Vm.2D poly64x2_t vuzp1q_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VUZP1Q_P8: // UZP1 Vd.16B,Vn.16B,Vm.16B poly8x16_t vuzp1q_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VUZP1Q_S16: // UZP1 Vd.8H,Vn.8H,Vm.8H int16x8_t vuzp1q_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VUZP1Q_S32: // UZP1 Vd.4S,Vn.4S,Vm.4S int32x4_t vuzp1q_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VUZP1Q_S64: // UZP1 Vd.2D,Vn.2D,Vm.2D int64x2_t vuzp1q_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VUZP1Q_S8: // UZP1 Vd.16B,Vn.16B,Vm.16B int8x16_t vuzp1q_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VUZP1Q_U16: // UZP1 Vd.8H,Vn.8H,Vm.8H uint16x8_t vuzp1q_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VUZP1Q_U32: // UZP1 Vd.4S,Vn.4S,Vm.4S uint32x4_t vuzp1q_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VUZP1Q_U64: // UZP1 Vd.2D,Vn.2D,Vm.2D uint64x2_t vuzp1q_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VUZP1Q_U8: // UZP1 Vd.16B,Vn.16B,Vm.16B uint8x16_t vuzp1q_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VUZP2Q_P16: // UZP2 Vd.8H,Vn.8H,Vm.8H poly16x8_t vuzp2q_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VUZP2Q_P64: // UZP2 Vd.2D,Vn.2D,Vm.2D poly64x2_t vuzp2q_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VUZP2Q_P8: // UZP2 Vd.16B,Vn.16B,Vm.16B poly8x16_t vuzp2q_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VUZP2Q_S16: // UZP2 Vd.8H,Vn.8H,Vm.8H int16x8_t vuzp2q_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VUZP2Q_S32: // UZP2 Vd.4S,Vn.4S,Vm.4S int32x4_t vuzp2q_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VUZP2Q_S64: // UZP2 Vd.2D,Vn.2D,Vm.2D int64x2_t vuzp2q_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VUZP2Q_S8: // UZP2 Vd.16B,Vn.16B,Vm.16B int8x16_t vuzp2q_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VUZP2Q_U16: // UZP2 Vd.8H,Vn.8H,Vm.8H uint16x8_t vuzp2q_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VUZP2Q_U32: // UZP2 Vd.4S,Vn.4S,Vm.4S uint32x4_t vuzp2q_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VUZP2Q_U64: // UZP2 Vd.2D,Vn.2D,Vm.2D uint64x2_t vuzp2q_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VUZP2Q_U8: // UZP2 Vd.16B,Vn.16B,Vm.16B uint8x16_t vuzp2q_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VUZPQ_P16: // UZP1 Vd1.8H,Vn.8H,Vm.8H poly16x8x2_t vuzpq_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VUZPQ_P8: // UZP1 Vd1.16B,Vn.16B,Vm.16B poly8x16x2_t vuzpq_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VUZPQ_S16: // UZP1 Vd1.8H,Vn.8H,Vm.8H int16x8x2_t vuzpq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VUZPQ_S32: // UZP1 Vd1.4S,Vn.4S,Vm.4S int32x4x2_t vuzpq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VUZPQ_S8: // UZP1 Vd1.16B,Vn.16B,Vm.16B int8x16x2_t vuzpq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VUZPQ_U16: // UZP1 Vd1.8H,Vn.8H,Vm.8H uint16x8x2_t vuzpq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VUZPQ_U32: // UZP1 Vd1.4S,Vn.4S,Vm.4S uint32x4x2_t vuzpq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VUZPQ_U8: // UZP1 Vd1.16B,Vn.16B,Vm.16B uint8x16x2_t vuzpq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VZIP1Q_P16: // ZIP1 Vd.8H,Vn.8H,Vm.8H poly16x8_t vzip1q_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VZIP1Q_P64: // ZIP1 Vd.2D,Vn.2D,Vm.2D poly64x2_t vzip1q_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VZIP1Q_P8: // ZIP1 Vd.16B,Vn.16B,Vm.16B poly8x16_t vzip1q_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VZIP1Q_S16: // ZIP1 Vd.8H,Vn.8H,Vm.8H int16x8_t vzip1q_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VZIP1Q_S32: // ZIP1 Vd.4S,Vn.4S,Vm.4S int32x4_t vzip1q_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VZIP1Q_S64: // ZIP1 Vd.2D,Vn.2D,Vm.2D int64x2_t vzip1q_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VZIP1Q_S8: // ZIP1 Vd.16B,Vn.16B,Vm.16B int8x16_t vzip1q_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VZIP1Q_U16: // ZIP1 Vd.8H,Vn.8H,Vm.8H uint16x8_t vzip1q_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VZIP1Q_U32: // ZIP1 Vd.4S,Vn.4S,Vm.4S uint32x4_t vzip1q_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VZIP1Q_U64: // ZIP1 Vd.2D,Vn.2D,Vm.2D uint64x2_t vzip1q_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VZIP1Q_U8: // ZIP1 Vd.16B,Vn.16B,Vm.16B uint8x16_t vzip1q_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VZIP2Q_P16: // ZIP2 Vd.8H,Vn.8H,Vm.8H poly16x8_t vzip2q_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VZIP2Q_P64: // ZIP2 Vd.2D,Vn.2D,Vm.2D poly64x2_t vzip2q_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VZIP2Q_P8: // ZIP2 Vd.16B,Vn.16B,Vm.16B poly8x16_t vzip2q_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VZIP2Q_S16: // ZIP2 Vd.8H,Vn.8H,Vm.8H int16x8_t vzip2q_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VZIP2Q_S32: // ZIP2 Vd.4S,Vn.4S,Vm.4S int32x4_t vzip2q_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VZIP2Q_S64: // ZIP2 Vd.2D,Vn.2D,Vm.2D int64x2_t vzip2q_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VZIP2Q_S8: // ZIP2 Vd.16B,Vn.16B,Vm.16B int8x16_t vzip2q_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VZIP2Q_U16: // ZIP2 Vd.8H,Vn.8H,Vm.8H uint16x8_t vzip2q_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VZIP2Q_U32: // ZIP2 Vd.4S,Vn.4S,Vm.4S uint32x4_t vzip2q_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VZIP2Q_U64: // ZIP2 Vd.2D,Vn.2D,Vm.2D uint64x2_t vzip2q_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VZIP2Q_U8: // ZIP2 Vd.16B,Vn.16B,Vm.16B uint8x16_t vzip2q_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VZIPQ_P16: // ZIP1 Vd1.8H,Vn.8H,Vm.8H poly16x8x2_t vzipq_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VZIPQ_P8: // ZIP1 Vd1.16B,Vn.16B,Vm.16B poly8x16x2_t vzipq_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VZIPQ_S16: // ZIP1 Vd1.8H,Vn.8H,Vm.8H int16x8x2_t vzipq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VZIPQ_S32: // ZIP1 Vd1.4S,Vn.4S,Vm.4S int32x4x2_t vzipq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VZIPQ_S8: // ZIP1 Vd1.16B,Vn.16B,Vm.16B int8x16x2_t vzipq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VZIPQ_U16: // ZIP1 Vd1.8H,Vn.8H,Vm.8H uint16x8x2_t vzipq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VZIPQ_U32: // ZIP1 Vd1.4S,Vn.4S,Vm.4S uint32x4x2_t vzipq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VZIPQ_U8: // ZIP1 Vd1.16B,Vn.16B,Vm.16B uint8x16x2_t vzipq_u8(uint8x16_t a, uint8x16_t b)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false))};
+ case ARM64_INTRIN_VABAL_HIGH_S16: // SABAL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vabal_high_s16(int32x4_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VABAL_HIGH_S32: // SABAL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vabal_high_s32(int64x2_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VABAL_HIGH_S8: // SABAL2 Vd.8H,Vn.16B,Vm.16B int16x8_t vabal_high_s8(int16x8_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VABAL_HIGH_U16: // UABAL2 Vd.4S,Vn.8H,Vm.8H uint32x4_t vabal_high_u16(uint32x4_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VABAL_HIGH_U32: // UABAL2 Vd.2D,Vn.4S,Vm.4S uint64x2_t vabal_high_u32(uint64x2_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VABAL_HIGH_U8: // UABAL2 Vd.8H,Vn.16B,Vm.16B uint16x8_t vabal_high_u8(uint16x8_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VABAQ_S16: // SABA Vd.8H,Vn.8H,Vm.8H int16x8_t vabaq_s16(int16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VABAQ_S32: // SABA Vd.4S,Vn.4S,Vm.4S int32x4_t vabaq_s32(int32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VABAQ_S8: // SABA Vd.16B,Vn.16B,Vm.16B int8x16_t vabaq_s8(int8x16_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VABAQ_U16: // UABA Vd.8H,Vn.8H,Vm.8H uint16x8_t vabaq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VABAQ_U32: // UABA Vd.4S,Vn.4S,Vm.4S uint32x4_t vabaq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VABAQ_U8: // UABA Vd.16B,Vn.16B,Vm.16B uint8x16_t vabaq_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VBCAXQ_S16: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B int16x8_t vbcaxq_s16(int16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VBCAXQ_S32: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B int32x4_t vbcaxq_s32(int32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VBCAXQ_S64: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B int64x2_t vbcaxq_s64(int64x2_t a, int64x2_t b, int64x2_t c)
+ case ARM64_INTRIN_VBCAXQ_S8: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B int8x16_t vbcaxq_s8(int8x16_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VBCAXQ_U16: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B uint16x8_t vbcaxq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VBCAXQ_U32: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B uint32x4_t vbcaxq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VBCAXQ_U64: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B uint64x2_t vbcaxq_u64(uint64x2_t a, uint64x2_t b, uint64x2_t c)
+ case ARM64_INTRIN_VBCAXQ_U8: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B uint8x16_t vbcaxq_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VBSLQ_P16: // BSL Vd.16B,Vn.16B,Vm.16B poly16x8_t vbslq_p16(uint16x8_t a, poly16x8_t b, poly16x8_t c)
+ case ARM64_INTRIN_VBSLQ_P64: // BSL Vd.16B,Vn.16B,Vm.16B poly64x2_t vbslq_p64(poly64x2_t a, poly64x2_t b, poly64x2_t c)
+ case ARM64_INTRIN_VBSLQ_P8: // BSL Vd.16B,Vn.16B,Vm.16B poly8x16_t vbslq_p8(uint8x16_t a, poly8x16_t b, poly8x16_t c)
+ case ARM64_INTRIN_VBSLQ_S16: // BSL Vd.16B,Vn.16B,Vm.16B int16x8_t vbslq_s16(uint16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VBSLQ_S32: // BSL Vd.16B,Vn.16B,Vm.16B int32x4_t vbslq_s32(uint32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VBSLQ_S64: // BSL Vd.16B,Vn.16B,Vm.16B int64x2_t vbslq_s64(uint64x2_t a, int64x2_t b, int64x2_t c)
+ case ARM64_INTRIN_VBSLQ_S8: // BSL Vd.16B,Vn.16B,Vm.16B int8x16_t vbslq_s8(uint8x16_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VBSLQ_U16: // BSL Vd.16B,Vn.16B,Vm.16B uint16x8_t vbslq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VBSLQ_U32: // BSL Vd.16B,Vn.16B,Vm.16B uint32x4_t vbslq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VBSLQ_U64: // BSL Vd.16B,Vn.16B,Vm.16B uint64x2_t vbslq_u64(uint64x2_t a, uint64x2_t b, uint64x2_t c)
+ case ARM64_INTRIN_VBSLQ_U8: // BSL Vd.16B,Vn.16B,Vm.16B uint8x16_t vbslq_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VDOTQ_S32: // SDOT Vd.4S,Vn.16B,Vm.16B int32x4_t vdotq_s32(int32x4_t r, int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VDOTQ_U32: // UDOT Vd.4S,Vn.16B,Vm.16B uint32x4_t vdotq_u32(uint32x4_t r, uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VEOR3Q_S16: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B int16x8_t veor3q_s16(int16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VEOR3Q_S32: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B int32x4_t veor3q_s32(int32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VEOR3Q_S64: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B int64x2_t veor3q_s64(int64x2_t a, int64x2_t b, int64x2_t c)
+ case ARM64_INTRIN_VEOR3Q_S8: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B int8x16_t veor3q_s8(int8x16_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VEOR3Q_U16: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B uint16x8_t veor3q_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VEOR3Q_U32: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B uint32x4_t veor3q_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VEOR3Q_U64: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B uint64x2_t veor3q_u64(uint64x2_t a, uint64x2_t b, uint64x2_t c)
+ case ARM64_INTRIN_VEOR3Q_U8: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B uint8x16_t veor3q_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_S16: // SMLAL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vmlal_high_s16(int32x4_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_S32: // SMLAL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vmlal_high_s32(int64x2_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_S8: // SMLAL2 Vd.8H,Vn.16B,Vm.16B int16x8_t vmlal_high_s8(int16x8_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_U16: // UMLAL2 Vd.4S,Vn.8H,Vm.8H uint32x4_t vmlal_high_u16(uint32x4_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_U32: // UMLAL2 Vd.2D,Vn.4S,Vm.4S uint64x2_t vmlal_high_u32(uint64x2_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_U8: // UMLAL2 Vd.8H,Vn.16B,Vm.16B uint16x8_t vmlal_high_u8(uint16x8_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VMLAQ_S16: // MLA Vd.8H,Vn.8H,Vm.8H int16x8_t vmlaq_s16(int16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VMLAQ_S32: // MLA Vd.4S,Vn.4S,Vm.4S int32x4_t vmlaq_s32(int32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VMLAQ_S8: // MLA Vd.16B,Vn.16B,Vm.16B int8x16_t vmlaq_s8(int8x16_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VMLAQ_U16: // MLA Vd.8H,Vn.8H,Vm.8H uint16x8_t vmlaq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VMLAQ_U32: // MLA Vd.4S,Vn.4S,Vm.4S uint32x4_t vmlaq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VMLAQ_U8: // MLA Vd.16B,Vn.16B,Vm.16B uint8x16_t vmlaq_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_S16: // SMLSL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vmlsl_high_s16(int32x4_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_S32: // SMLSL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vmlsl_high_s32(int64x2_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_S8: // SMLSL2 Vd.8H,Vn.16B,Vm.16B int16x8_t vmlsl_high_s8(int16x8_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_U16: // UMLSL2 Vd.4S,Vn.8H,Vm.8H uint32x4_t vmlsl_high_u16(uint32x4_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_U32: // UMLSL2 Vd.2D,Vn.4S,Vm.4S uint64x2_t vmlsl_high_u32(uint64x2_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_U8: // UMLSL2 Vd.8H,Vn.16B,Vm.16B uint16x8_t vmlsl_high_u8(uint16x8_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VMLSQ_S16: // MLS Vd.8H,Vn.8H,Vm.8H int16x8_t vmlsq_s16(int16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VMLSQ_S32: // MLS Vd.4S,Vn.4S,Vm.4S int32x4_t vmlsq_s32(int32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VMLSQ_S8: // MLS Vd.16B,Vn.16B,Vm.16B int8x16_t vmlsq_s8(int8x16_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VMLSQ_U16: // MLS Vd.8H,Vn.8H,Vm.8H uint16x8_t vmlsq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VMLSQ_U32: // MLS Vd.4S,Vn.4S,Vm.4S uint32x4_t vmlsq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VMLSQ_U8: // MLS Vd.16B,Vn.16B,Vm.16B uint8x16_t vmlsq_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VMMLAQ_S32: // SMMLA Vd.4S,Vn.16B,Vm.16B int32x4_t vmmlaq_s32(int32x4_t r, int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VMMLAQ_U32: // UMMLA Vd.4S,Vn.16B,Vm.16B uint32x4_t vmmlaq_u32(uint32x4_t r, uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VQDMLAL_HIGH_S16: // SQDMLAL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vqdmlal_high_s16(int32x4_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VQDMLAL_HIGH_S32: // SQDMLAL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vqdmlal_high_s32(int64x2_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VQDMLSL_HIGH_S16: // SQDMLSL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vqdmlsl_high_s16(int32x4_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VQDMLSL_HIGH_S32: // SQDMLSL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vqdmlsl_high_s32(int64x2_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VQRDMLAHQ_S16: // SQRDMLAH Vd.8H,Vn.8H,Vm.8H int16x8_t vqrdmlahq_s16(int16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VQRDMLAHQ_S32: // SQRDMLAH Vd.4S,Vn.4S,Vm.4S int32x4_t vqrdmlahq_s32(int32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VQRDMLSHQ_S16: // SQRDMLSH Vd.8H,Vn.8H,Vm.8H int16x8_t vqrdmlshq_s16(int16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VQRDMLSHQ_S32: // SQRDMLSH Vd.4S,Vn.4S,Vm.4S int32x4_t vqrdmlshq_s32(int32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VSHA1SU0Q_U32: // SHA1SU0 Vd.4S,Vn.4S,Vm.4S uint32x4_t vsha1su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11)
+ case ARM64_INTRIN_VSHA256H2Q_U32: // SHA256H2 Qd,Qn,Vm.4S uint32x4_t vsha256h2q_u32(uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk)
+ case ARM64_INTRIN_VSHA256HQ_U32: // SHA256H Qd,Qn,Vm.4S uint32x4_t vsha256hq_u32(uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk)
+ case ARM64_INTRIN_VSHA256SU1Q_U32: // SHA256SU1 Vd.4S,Vn.4S,Vm.4S uint32x4_t vsha256su1q_u32(uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15)
+ case ARM64_INTRIN_VSHA512H2Q_U64: // SHA512H2 Qd,Qn,Vm.2D uint64x2_t vsha512h2q_u64(uint64x2_t sum_ab, uint64x2_t hash_c_, uint64x2_t hash_ab)
+ case ARM64_INTRIN_VSHA512HQ_U64: // SHA512H Qd,Qn,Vm.2D uint64x2_t vsha512hq_u64(uint64x2_t hash_ed, uint64x2_t hash_gf, uint64x2_t kwh_kwh2)
+ case ARM64_INTRIN_VSHA512SU1Q_U64: // SHA512SU1 Vd.2D,Vn.2D,Vm.2D uint64x2_t vsha512su1q_u64(uint64x2_t s01_s02, uint64x2_t w14_15, uint64x2_t w9_10)
+ case ARM64_INTRIN_VSM3PARTW1Q_U32: // SM3PARTW1 Vd.4S,Vn.4S,Vm.4S uint32x4_t vsm3partw1q_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VSM3PARTW2Q_U32: // SM3PARTW2 Vd.4S,Vn.4S,Vm.4S uint32x4_t vsm3partw2q_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VSM3SS1Q_U32: // SM3SS1 Vd.4S,Vn.4S,Vm.4S,Va.4S uint32x4_t vsm3ss1q_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VUSDOTQ_S32: // USDOT Vd.4S,Vn.16B,Vm.16B int32x4_t vusdotq_s32(int32x4_t r, uint8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VUSMMLAQ_S32: // USMMLA Vd.4S,Vn.16B,Vm.16B int32x4_t vusmmlaq_s32(int32x4_t r, uint8x16_t a, int8x16_t b)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false))};
+ case ARM64_INTRIN_VDOTQ_LANEQ_S32: // SDOT Vd.4S,Vn.16B,Vm.4B[lane] int32x4_t vdotq_laneq_s32(int32x4_t r, int8x16_t a, int8x16_t b, const int lane)
+ case ARM64_INTRIN_VDOTQ_LANEQ_U32: // UDOT Vd.4S,Vn.16B,Vm.4B[lane] uint32x4_t vdotq_laneq_u32(uint32x4_t r, uint8x16_t a, uint8x16_t b, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_LANEQ_S16: // SMLAL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vmlal_high_laneq_s16(int32x4_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_LANEQ_S32: // SMLAL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vmlal_high_laneq_s32(int64x2_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_LANEQ_U16: // UMLAL2 Vd.4S,Vn.8H,Vm.H[lane] uint32x4_t vmlal_high_laneq_u16(uint32x4_t a, uint16x8_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_LANEQ_U32: // UMLAL2 Vd.2D,Vn.4S,Vm.S[lane] uint64x2_t vmlal_high_laneq_u32(uint64x2_t a, uint32x4_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_LANEQ_S16: // MLA Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vmlaq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_LANEQ_S32: // MLA Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vmlaq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_LANEQ_U16: // MLA Vd.8H,Vn.8H,Vm.H[lane] uint16x8_t vmlaq_laneq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_LANEQ_U32: // MLA Vd.4S,Vn.4S,Vm.S[lane] uint32x4_t vmlaq_laneq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_LANEQ_S16: // SMLSL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vmlsl_high_laneq_s16(int32x4_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_LANEQ_S32: // SMLSL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vmlsl_high_laneq_s32(int64x2_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_LANEQ_U16: // UMLSL2 Vd.4S,Vn.8H,Vm.H[lane] uint32x4_t vmlsl_high_laneq_u16(uint32x4_t a, uint16x8_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_LANEQ_U32: // UMLSL2 Vd.2D,Vn.4S,Vm.S[lane] uint64x2_t vmlsl_high_laneq_u32(uint64x2_t a, uint32x4_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_LANEQ_S16: // MLS Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vmlsq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_LANEQ_S32: // MLS Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vmlsq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_LANEQ_U16: // MLS Vd.8H,Vn.8H,Vm.H[lane] uint16x8_t vmlsq_laneq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_LANEQ_U32: // MLS Vd.4S,Vn.4S,Vm.S[lane] uint32x4_t vmlsq_laneq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_HIGH_LANEQ_S16: // SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vqdmlal_high_laneq_s16(int32x4_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_HIGH_LANEQ_S32: // SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vqdmlal_high_laneq_s32(int64x2_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_HIGH_LANEQ_S16: // SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vqdmlsl_high_laneq_s16(int32x4_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_HIGH_LANEQ_S32: // SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vqdmlsl_high_laneq_s32(int64x2_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAHQ_LANEQ_S16: // SQRDMLAH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqrdmlahq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAHQ_LANEQ_S32: // SQRDMLAH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqrdmlahq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHQ_LANEQ_S16: // SQRDMLSH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqrdmlshq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHQ_LANEQ_S32: // SQRDMLSH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqrdmlshq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VSM3TT1AQ_U32: // SM3TT1A Vd.4S,Vn.4S,Vm.4S[imm2] uint32x4_t vsm3tt1aq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c, const int imm2)
+ case ARM64_INTRIN_VSM3TT1BQ_U32: // SM3TT1B Vd.4S,Vn.4S,Vm.4S[imm2] uint32x4_t vsm3tt1bq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c, const int imm2)
+ case ARM64_INTRIN_VSM3TT2AQ_U32: // SM3TT2A Vd.4S,Vn.4S,Vm.4S[imm2] uint32x4_t vsm3tt2aq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c, const int imm2)
+ case ARM64_INTRIN_VSM3TT2BQ_U32: // SM3TT2B Vd.4S,Vn.4S,Vm.4S[imm2] uint32x4_t vsm3tt2bq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c, const int imm2)
+ case ARM64_INTRIN_VSUDOTQ_LANEQ_S32: // SUDOT Vd.4S,Vn.16B,Vm.4B[lane] int32x4_t vsudotq_laneq_s32(int32x4_t r, int8x16_t a, uint8x16_t b, const int lane)
+ case ARM64_INTRIN_VUSDOTQ_LANEQ_S32: // USDOT Vd.4S,Vn.16B,Vm.4B[lane] int32x4_t vusdotq_laneq_s32(int32x4_t r, uint8x16_t a, int8x16_t b, const int lane)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VMLAL_HIGH_N_S16: // SMLAL2 Vd.4S,Vn.8H,Vm.H[0] int32x4_t vmlal_high_n_s16(int32x4_t a, int16x8_t b, int16_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_N_U16: // UMLAL2 Vd.4S,Vn.8H,Vm.H[0] uint32x4_t vmlal_high_n_u16(uint32x4_t a, uint16x8_t b, uint16_t c)
+ case ARM64_INTRIN_VMLAQ_N_S16: // MLA Vd.8H,Vn.8H,Vm.H[0] int16x8_t vmlaq_n_s16(int16x8_t a, int16x8_t b, int16_t c)
+ case ARM64_INTRIN_VMLAQ_N_U16: // MLA Vd.8H,Vn.8H,Vm.H[0] uint16x8_t vmlaq_n_u16(uint16x8_t a, uint16x8_t b, uint16_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_N_S16: // SMLSL2 Vd.4S,Vn.8H,Vm.H[0] int32x4_t vmlsl_high_n_s16(int32x4_t a, int16x8_t b, int16_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_N_U16: // UMLSL2 Vd.4S,Vn.8H,Vm.H[0] uint32x4_t vmlsl_high_n_u16(uint32x4_t a, uint16x8_t b, uint16_t c)
+ case ARM64_INTRIN_VMLSQ_N_S16: // MLS Vd.8H,Vn.8H,Vm.H[0] int16x8_t vmlsq_n_s16(int16x8_t a, int16x8_t b, int16_t c)
+ case ARM64_INTRIN_VMLSQ_N_U16: // MLS Vd.8H,Vn.8H,Vm.H[0] uint16x8_t vmlsq_n_u16(uint16x8_t a, uint16x8_t b, uint16_t c)
+ case ARM64_INTRIN_VQDMLAL_HIGH_N_S16: // SQDMLAL2 Vd.4S,Vn.8H,Vm.H[0] int32x4_t vqdmlal_high_n_s16(int32x4_t a, int16x8_t b, int16_t c)
+ case ARM64_INTRIN_VQDMLSL_HIGH_N_S16: // SQDMLSL2 Vd.4S,Vn.8H,Vm.H[0] int32x4_t vqdmlsl_high_n_s16(int32x4_t a, int16x8_t b, int16_t c)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(2, false))};
+ case ARM64_INTRIN_VEXTQ_P16: // EXT Vd.16B,Vn.16B,Vm.16B,#n poly16x8_t vextq_p16(poly16x8_t a, poly16x8_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_P64: // EXT Vd.16B,Vn.16B,Vm.16B,#n poly64x2_t vextq_p64(poly64x2_t a, poly64x2_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_P8: // EXT Vd.16B,Vn.16B,Vm.16B,#n poly8x16_t vextq_p8(poly8x16_t a, poly8x16_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_S16: // EXT Vd.16B,Vn.16B,Vm.16B,#n int16x8_t vextq_s16(int16x8_t a, int16x8_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_S32: // EXT Vd.16B,Vn.16B,Vm.16B,#n int32x4_t vextq_s32(int32x4_t a, int32x4_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_S64: // EXT Vd.16B,Vn.16B,Vm.16B,#n int64x2_t vextq_s64(int64x2_t a, int64x2_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_S8: // EXT Vd.16B,Vn.16B,Vm.16B,#n int8x16_t vextq_s8(int8x16_t a, int8x16_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_U16: // EXT Vd.16B,Vn.16B,Vm.16B,#n uint16x8_t vextq_u16(uint16x8_t a, uint16x8_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_U32: // EXT Vd.16B,Vn.16B,Vm.16B,#n uint32x4_t vextq_u32(uint32x4_t a, uint32x4_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_U64: // EXT Vd.16B,Vn.16B,Vm.16B,#n uint64x2_t vextq_u64(uint64x2_t a, uint64x2_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_U8: // EXT Vd.16B,Vn.16B,Vm.16B,#n uint8x16_t vextq_u8(uint8x16_t a, uint8x16_t b, const int n)
+ case ARM64_INTRIN_VMLAL_HIGH_N_S32: // SMLAL2 Vd.2D,Vn.4S,Vm.S[0] int64x2_t vmlal_high_n_s32(int64x2_t a, int32x4_t b, int32_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_N_U32: // UMLAL2 Vd.2D,Vn.4S,Vm.S[0] uint64x2_t vmlal_high_n_u32(uint64x2_t a, uint32x4_t b, uint32_t c)
+ case ARM64_INTRIN_VMLAQ_N_S32: // MLA Vd.4S,Vn.4S,Vm.S[0] int32x4_t vmlaq_n_s32(int32x4_t a, int32x4_t b, int32_t c)
+ case ARM64_INTRIN_VMLAQ_N_U32: // MLA Vd.4S,Vn.4S,Vm.S[0] uint32x4_t vmlaq_n_u32(uint32x4_t a, uint32x4_t b, uint32_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_N_S32: // SMLSL2 Vd.2D,Vn.4S,Vm.S[0] int64x2_t vmlsl_high_n_s32(int64x2_t a, int32x4_t b, int32_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_N_U32: // UMLSL2 Vd.2D,Vn.4S,Vm.S[0] uint64x2_t vmlsl_high_n_u32(uint64x2_t a, uint32x4_t b, uint32_t c)
+ case ARM64_INTRIN_VMLSQ_N_S32: // MLS Vd.4S,Vn.4S,Vm.S[0] int32x4_t vmlsq_n_s32(int32x4_t a, int32x4_t b, int32_t c)
+ case ARM64_INTRIN_VMLSQ_N_U32: // MLS Vd.4S,Vn.4S,Vm.S[0] uint32x4_t vmlsq_n_u32(uint32x4_t a, uint32x4_t b, uint32_t c)
+ case ARM64_INTRIN_VMULL_HIGH_LANEQ_S16: // SMULL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vmull_high_laneq_s16(int16x8_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULL_HIGH_LANEQ_S32: // SMULL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vmull_high_laneq_s32(int32x4_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULL_HIGH_LANEQ_U16: // UMULL2 Vd.4S,Vn.8H,Vm.H[lane] uint32x4_t vmull_high_laneq_u16(uint16x8_t a, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULL_HIGH_LANEQ_U32: // UMULL2 Vd.2D,Vn.4S,Vm.S[lane] uint64x2_t vmull_high_laneq_u32(uint32x4_t a, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANEQ_S16: // MUL Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vmulq_laneq_s16(int16x8_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANEQ_S32: // MUL Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vmulq_laneq_s32(int32x4_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANEQ_U16: // MUL Vd.8H,Vn.8H,Vm.H[lane] uint16x8_t vmulq_laneq_u16(uint16x8_t a, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANEQ_U32: // MUL Vd.4S,Vn.4S,Vm.S[lane] uint32x4_t vmulq_laneq_u32(uint32x4_t a, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_HIGH_N_S32: // SQDMLAL2 Vd.2D,Vn.4S,Vm.S[0] int64x2_t vqdmlal_high_n_s32(int64x2_t a, int32x4_t b, int32_t c)
+ case ARM64_INTRIN_VQDMLSL_HIGH_N_S32: // SQDMLSL2 Vd.2D,Vn.4S,Vm.S[0] int64x2_t vqdmlsl_high_n_s32(int64x2_t a, int32x4_t b, int32_t c)
+ case ARM64_INTRIN_VQDMULHQ_LANEQ_S16: // SQDMULH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqdmulhq_laneq_s16(int16x8_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMULHQ_LANEQ_S32: // SQDMULH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqdmulhq_laneq_s32(int32x4_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_HIGH_LANEQ_S16: // SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vqdmull_high_laneq_s16(int16x8_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_HIGH_LANEQ_S32: // SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vqdmull_high_laneq_s32(int32x4_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHQ_LANEQ_S16: // SQRDMULH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqrdmulhq_laneq_s16(int16x8_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHQ_LANEQ_S32: // SQRDMULH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqrdmulhq_laneq_s32(int32x4_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VRSRAQ_N_S16: // SRSRA Vd.8H,Vn.8H,#n int16x8_t vrsraq_n_s16(int16x8_t a, int16x8_t b, const int n)
+ case ARM64_INTRIN_VRSRAQ_N_S32: // SRSRA Vd.4S,Vn.4S,#n int32x4_t vrsraq_n_s32(int32x4_t a, int32x4_t b, const int n)
+ case ARM64_INTRIN_VRSRAQ_N_S64: // SRSRA Vd.2D,Vn.2D,#n int64x2_t vrsraq_n_s64(int64x2_t a, int64x2_t b, const int n)
+ case ARM64_INTRIN_VRSRAQ_N_S8: // SRSRA Vd.16B,Vn.16B,#n int8x16_t vrsraq_n_s8(int8x16_t a, int8x16_t b, const int n)
+ case ARM64_INTRIN_VRSRAQ_N_U16: // URSRA Vd.8H,Vn.8H,#n uint16x8_t vrsraq_n_u16(uint16x8_t a, uint16x8_t b, const int n)
+ case ARM64_INTRIN_VRSRAQ_N_U32: // URSRA Vd.4S,Vn.4S,#n uint32x4_t vrsraq_n_u32(uint32x4_t a, uint32x4_t b, const int n)
+ case ARM64_INTRIN_VRSRAQ_N_U64: // URSRA Vd.2D,Vn.2D,#n uint64x2_t vrsraq_n_u64(uint64x2_t a, uint64x2_t b, const int n)
+ case ARM64_INTRIN_VRSRAQ_N_U8: // URSRA Vd.16B,Vn.16B,#n uint8x16_t vrsraq_n_u8(uint8x16_t a, uint8x16_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_P16: // SLI Vd.8H,Vn.8H,#n poly16x8_t vsliq_n_p16(poly16x8_t a, poly16x8_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_P64: // SLI Vd.2D,Vn.2D,#n poly64x2_t vsliq_n_p64(poly64x2_t a, poly64x2_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_P8: // SLI Vd.16B,Vn.16B,#n poly8x16_t vsliq_n_p8(poly8x16_t a, poly8x16_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_S16: // SLI Vd.8H,Vn.8H,#n int16x8_t vsliq_n_s16(int16x8_t a, int16x8_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_S32: // SLI Vd.4S,Vn.4S,#n int32x4_t vsliq_n_s32(int32x4_t a, int32x4_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_S64: // SLI Vd.2D,Vn.2D,#n int64x2_t vsliq_n_s64(int64x2_t a, int64x2_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_S8: // SLI Vd.16B,Vn.16B,#n int8x16_t vsliq_n_s8(int8x16_t a, int8x16_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_U16: // SLI Vd.8H,Vn.8H,#n uint16x8_t vsliq_n_u16(uint16x8_t a, uint16x8_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_U32: // SLI Vd.4S,Vn.4S,#n uint32x4_t vsliq_n_u32(uint32x4_t a, uint32x4_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_U64: // SLI Vd.2D,Vn.2D,#n uint64x2_t vsliq_n_u64(uint64x2_t a, uint64x2_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_U8: // SLI Vd.16B,Vn.16B,#n uint8x16_t vsliq_n_u8(uint8x16_t a, uint8x16_t b, const int n)
+ case ARM64_INTRIN_VSRAQ_N_S16: // SSRA Vd.8H,Vn.8H,#n int16x8_t vsraq_n_s16(int16x8_t a, int16x8_t b, const int n)
+ case ARM64_INTRIN_VSRAQ_N_S32: // SSRA Vd.4S,Vn.4S,#n int32x4_t vsraq_n_s32(int32x4_t a, int32x4_t b, const int n)
+ case ARM64_INTRIN_VSRAQ_N_S64: // SSRA Vd.2D,Vn.2D,#n int64x2_t vsraq_n_s64(int64x2_t a, int64x2_t b, const int n)
+ case ARM64_INTRIN_VSRAQ_N_S8: // SSRA Vd.16B,Vn.16B,#n int8x16_t vsraq_n_s8(int8x16_t a, int8x16_t b, const int n)
+ case ARM64_INTRIN_VSRAQ_N_U16: // USRA Vd.8H,Vn.8H,#n uint16x8_t vsraq_n_u16(uint16x8_t a, uint16x8_t b, const int n)
+ case ARM64_INTRIN_VSRAQ_N_U32: // USRA Vd.4S,Vn.4S,#n uint32x4_t vsraq_n_u32(uint32x4_t a, uint32x4_t b, const int n)
+ case ARM64_INTRIN_VSRAQ_N_U64: // USRA Vd.2D,Vn.2D,#n uint64x2_t vsraq_n_u64(uint64x2_t a, uint64x2_t b, const int n)
+ case ARM64_INTRIN_VSRAQ_N_U8: // USRA Vd.16B,Vn.16B,#n uint8x16_t vsraq_n_u8(uint8x16_t a, uint8x16_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_P16: // SRI Vd.8H,Vn.8H,#n poly16x8_t vsriq_n_p16(poly16x8_t a, poly16x8_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_P64: // SRI Vd.2D,Vn.2D,#n poly64x2_t vsriq_n_p64(poly64x2_t a, poly64x2_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_P8: // SRI Vd.16B,Vn.16B,#n poly8x16_t vsriq_n_p8(poly8x16_t a, poly8x16_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_S16: // SRI Vd.8H,Vn.8H,#n int16x8_t vsriq_n_s16(int16x8_t a, int16x8_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_S32: // SRI Vd.4S,Vn.4S,#n int32x4_t vsriq_n_s32(int32x4_t a, int32x4_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_S64: // SRI Vd.2D,Vn.2D,#n int64x2_t vsriq_n_s64(int64x2_t a, int64x2_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_S8: // SRI Vd.16B,Vn.16B,#n int8x16_t vsriq_n_s8(int8x16_t a, int8x16_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_U16: // SRI Vd.8H,Vn.8H,#n uint16x8_t vsriq_n_u16(uint16x8_t a, uint16x8_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_U32: // SRI Vd.4S,Vn.4S,#n uint32x4_t vsriq_n_u32(uint32x4_t a, uint32x4_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_U64: // SRI Vd.2D,Vn.2D,#n uint64x2_t vsriq_n_u64(uint64x2_t a, uint64x2_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_U8: // SRI Vd.16B,Vn.16B,#n uint8x16_t vsriq_n_u8(uint8x16_t a, uint8x16_t b, const int n)
+ case ARM64_INTRIN_VXARQ_U64: // XAR Vd.2D,Vn.2D,Vm.2D,imm6 uint64x2_t vxarq_u64(uint64x2_t a, uint64x2_t b, const int imm6)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VDOTQ_LANE_S32: // SDOT Vd.4S,Vn.16B,Vm.4B[lane] int32x4_t vdotq_lane_s32(int32x4_t r, int8x16_t a, int8x8_t b, const int lane)
+ case ARM64_INTRIN_VDOTQ_LANE_U32: // UDOT Vd.4S,Vn.16B,Vm.4B[lane] uint32x4_t vdotq_lane_u32(uint32x4_t r, uint8x16_t a, uint8x8_t b, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_LANE_S16: // SMLAL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vmlal_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_LANE_S32: // SMLAL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vmlal_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_LANE_U16: // UMLAL2 Vd.4S,Vn.8H,Vm.H[lane] uint32x4_t vmlal_high_lane_u16(uint32x4_t a, uint16x8_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_LANE_U32: // UMLAL2 Vd.2D,Vn.4S,Vm.S[lane] uint64x2_t vmlal_high_lane_u32(uint64x2_t a, uint32x4_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_LANE_S16: // MLA Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vmlaq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_LANE_S32: // MLA Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vmlaq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_LANE_U16: // MLA Vd.8H,Vn.8H,Vm.H[lane] uint16x8_t vmlaq_lane_u16(uint16x8_t a, uint16x8_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_LANE_U32: // MLA Vd.4S,Vn.4S,Vm.S[lane] uint32x4_t vmlaq_lane_u32(uint32x4_t a, uint32x4_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_LANE_S16: // SMLSL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vmlsl_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_LANE_S32: // SMLSL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vmlsl_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_LANE_U16: // UMLSL2 Vd.4S,Vn.8H,Vm.H[lane] uint32x4_t vmlsl_high_lane_u16(uint32x4_t a, uint16x8_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_LANE_U32: // UMLSL2 Vd.2D,Vn.4S,Vm.S[lane] uint64x2_t vmlsl_high_lane_u32(uint64x2_t a, uint32x4_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_LANE_S16: // MLS Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vmlsq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_LANE_S32: // MLS Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vmlsq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_LANE_U16: // MLS Vd.8H,Vn.8H,Vm.H[lane] uint16x8_t vmlsq_lane_u16(uint16x8_t a, uint16x8_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_LANE_U32: // MLS Vd.4S,Vn.4S,Vm.S[lane] uint32x4_t vmlsq_lane_u32(uint32x4_t a, uint32x4_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_HIGH_LANE_S16: // SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vqdmlal_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_HIGH_LANE_S32: // SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vqdmlal_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_HIGH_LANE_S16: // SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vqdmlsl_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_HIGH_LANE_S32: // SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vqdmlsl_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAHQ_LANE_S16: // SQRDMLAH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqrdmlahq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAHQ_LANE_S32: // SQRDMLAH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqrdmlahq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHQ_LANE_S16: // SQRDMLSH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqrdmlshq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHQ_LANE_S32: // SQRDMLSH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqrdmlshq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VSUDOTQ_LANE_S32: // SUDOT Vd.4S,Vn.16B,Vm.4B[lane] int32x4_t vsudotq_lane_s32(int32x4_t r, int8x16_t a, uint8x8_t b, const int lane)
+ case ARM64_INTRIN_VUSDOTQ_LANE_S32: // USDOT Vd.4S,Vn.16B,Vm.4B[lane] int32x4_t vusdotq_lane_s32(int32x4_t r, uint8x16_t a, int8x8_t b, const int lane)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VMULL_HIGH_N_S16: // SMULL2 Vd.4S,Vn.8H,Vm.H[0] int32x4_t vmull_high_n_s16(int16x8_t a, int16_t b)
+ case ARM64_INTRIN_VMULL_HIGH_N_U16: // UMULL2 Vd.4S,Vn.8H,Vm.H[0] uint32x4_t vmull_high_n_u16(uint16x8_t a, uint16_t b)
+ case ARM64_INTRIN_VMULQ_N_S16: // MUL Vd.8H,Vn.8H,Vm.H[0] int16x8_t vmulq_n_s16(int16x8_t a, int16_t b)
+ case ARM64_INTRIN_VMULQ_N_U16: // MUL Vd.8H,Vn.8H,Vm.H[0] uint16x8_t vmulq_n_u16(uint16x8_t a, uint16_t b)
+ case ARM64_INTRIN_VQDMULHQ_N_S16: // SQDMULH Vd.8H,Vn.8H,Vm.H[0] int16x8_t vqdmulhq_n_s16(int16x8_t a, int16_t b)
+ case ARM64_INTRIN_VQDMULL_HIGH_N_S16: // SQDMULL2 Vd.4S,Vn.8H,Vm.H[0] int32x4_t vqdmull_high_n_s16(int16x8_t a, int16_t b)
+ case ARM64_INTRIN_VQRDMULHQ_N_S16: // SQRDMULH Vd.8H,Vn.8H,Vm.H[0] int16x8_t vqrdmulhq_n_s16(int16x8_t a, int16_t b)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(2, false))};
+ case ARM64_INTRIN_VCVTQ_N_F16_S16: // SCVTF Vd.8H,Vn.8H,#n float16x8_t vcvtq_n_f16_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_F16_U16: // UCVTF Vd.8H,Vn.8H,#n float16x8_t vcvtq_n_f16_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_F32_S32: // SCVTF Vd.4S,Vn.4S,#n float32x4_t vcvtq_n_f32_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_F32_U32: // UCVTF Vd.4S,Vn.4S,#n float32x4_t vcvtq_n_f32_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_F64_S64: // SCVTF Vd.2D,Vn.2D,#n float64x2_t vcvtq_n_f64_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_F64_U64: // UCVTF Vd.2D,Vn.2D,#n float64x2_t vcvtq_n_f64_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VDUP_LANEQ_P16: // DUP Vd.4H,Vn.H[lane] poly16x4_t vdup_laneq_p16(poly16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_P64: // DUP Dd,Vn.D[lane] poly64x1_t vdup_laneq_p64(poly64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_P8: // DUP Vd.8B,Vn.B[lane] poly8x8_t vdup_laneq_p8(poly8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_S16: // DUP Vd.4H,Vn.H[lane] int16x4_t vdup_laneq_s16(int16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_S32: // DUP Vd.2S,Vn.S[lane] int32x2_t vdup_laneq_s32(int32x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_S64: // DUP Dd,Vn.D[lane] int64x1_t vdup_laneq_s64(int64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_S8: // DUP Vd.8B,Vn.B[lane] int8x8_t vdup_laneq_s8(int8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_U16: // DUP Vd.4H,Vn.H[lane] uint16x4_t vdup_laneq_u16(uint16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_U32: // DUP Vd.2S,Vn.S[lane] uint32x2_t vdup_laneq_u32(uint32x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_U64: // DUP Dd,Vn.D[lane] uint64x1_t vdup_laneq_u64(uint64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_U8: // DUP Vd.8B,Vn.B[lane] uint8x8_t vdup_laneq_u8(uint8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUPB_LANEQ_P8: // DUP Bd,Vn.B[lane] poly8_t vdupb_laneq_p8(poly8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUPB_LANEQ_S8: // DUP Bd,Vn.B[lane] int8_t vdupb_laneq_s8(int8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUPB_LANEQ_U8: // DUP Bd,Vn.B[lane] uint8_t vdupb_laneq_u8(uint8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUPD_LANEQ_S64: // DUP Dd,Vn.D[lane] int64_t vdupd_laneq_s64(int64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPD_LANEQ_U64: // DUP Dd,Vn.D[lane] uint64_t vdupd_laneq_u64(uint64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANEQ_P16: // DUP Hd,Vn.H[lane] poly16_t vduph_laneq_p16(poly16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANEQ_S16: // DUP Hd,Vn.H[lane] int16_t vduph_laneq_s16(int16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANEQ_U16: // DUP Hd,Vn.H[lane] uint16_t vduph_laneq_u16(uint16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_P16: // DUP Vd.8H,Vn.H[lane] poly16x8_t vdupq_laneq_p16(poly16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_P64: // DUP Vd.2D,Vn.D[lane] poly64x2_t vdupq_laneq_p64(poly64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_P8: // DUP Vd.16B,Vn.B[lane] poly8x16_t vdupq_laneq_p8(poly8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_S16: // DUP Vd.8H,Vn.H[lane] int16x8_t vdupq_laneq_s16(int16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_S32: // DUP Vd.4S,Vn.S[lane] int32x4_t vdupq_laneq_s32(int32x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_S64: // DUP Vd.2D,Vn.D[lane] int64x2_t vdupq_laneq_s64(int64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_S8: // DUP Vd.16B,Vn.B[lane] int8x16_t vdupq_laneq_s8(int8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_U16: // DUP Vd.8H,Vn.H[lane] uint16x8_t vdupq_laneq_u16(uint16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_U32: // DUP Vd.4S,Vn.S[lane] uint32x4_t vdupq_laneq_u32(uint32x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_U64: // DUP Vd.2D,Vn.D[lane] uint64x2_t vdupq_laneq_u64(uint64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_U8: // DUP Vd.16B,Vn.B[lane] uint8x16_t vdupq_laneq_u8(uint8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUPS_LANEQ_S32: // DUP Sd,Vn.S[lane] int32_t vdups_laneq_s32(int32x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPS_LANEQ_U32: // DUP Sd,Vn.S[lane] uint32_t vdups_laneq_u32(uint32x4_t vec, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_P16: // UMOV Rd,Vn.H[lane] poly16_t vgetq_lane_p16(poly16x8_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_P64: // UMOV Rd,Vn.D[lane] poly64_t vgetq_lane_p64(poly64x2_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_P8: // UMOV Rd,Vn.B[lane] poly8_t vgetq_lane_p8(poly8x16_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_S16: // SMOV Rd,Vn.H[lane] int16_t vgetq_lane_s16(int16x8_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_S32: // SMOV Rd,Vn.S[lane] int32_t vgetq_lane_s32(int32x4_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_S64: // UMOV Rd,Vn.D[lane] int64_t vgetq_lane_s64(int64x2_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_S8: // SMOV Rd,Vn.B[lane] int8_t vgetq_lane_s8(int8x16_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_U16: // UMOV Rd,Vn.H[lane] uint16_t vgetq_lane_u16(uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_U32: // UMOV Rd,Vn.S[lane] uint32_t vgetq_lane_u32(uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_U64: // UMOV Rd,Vn.D[lane] uint64_t vgetq_lane_u64(uint64x2_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_U8: // UMOV Rd,Vn.B[lane] uint8_t vgetq_lane_u8(uint8x16_t v, const int lane)
+ case ARM64_INTRIN_VMULL_HIGH_N_S32: // SMULL2 Vd.2D,Vn.4S,Vm.S[0] int64x2_t vmull_high_n_s32(int32x4_t a, int32_t b)
+ case ARM64_INTRIN_VMULL_HIGH_N_U32: // UMULL2 Vd.2D,Vn.4S,Vm.S[0] uint64x2_t vmull_high_n_u32(uint32x4_t a, uint32_t b)
+ case ARM64_INTRIN_VMULQ_N_S32: // MUL Vd.4S,Vn.4S,Vm.S[0] int32x4_t vmulq_n_s32(int32x4_t a, int32_t b)
+ case ARM64_INTRIN_VMULQ_N_U32: // MUL Vd.4S,Vn.4S,Vm.S[0] uint32x4_t vmulq_n_u32(uint32x4_t a, uint32_t b)
+ case ARM64_INTRIN_VQDMULHQ_N_S32: // SQDMULH Vd.4S,Vn.4S,Vm.S[0] int32x4_t vqdmulhq_n_s32(int32x4_t a, int32_t b)
+ case ARM64_INTRIN_VQDMULL_HIGH_N_S32: // SQDMULL2 Vd.2D,Vn.4S,Vm.S[0] int64x2_t vqdmull_high_n_s32(int32x4_t a, int32_t b)
+ case ARM64_INTRIN_VQRDMULHQ_N_S32: // SQRDMULH Vd.4S,Vn.4S,Vm.S[0] int32x4_t vqrdmulhq_n_s32(int32x4_t a, int32_t b)
+ case ARM64_INTRIN_VQRSHRN_N_S16: // SQRSHRN Vd.8B,Vn.8H,#n int8x8_t vqrshrn_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_N_S32: // SQRSHRN Vd.4H,Vn.4S,#n int16x4_t vqrshrn_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_N_S64: // SQRSHRN Vd.2S,Vn.2D,#n int32x2_t vqrshrn_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_N_U16: // UQRSHRN Vd.8B,Vn.8H,#n uint8x8_t vqrshrn_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_N_U32: // UQRSHRN Vd.4H,Vn.4S,#n uint16x4_t vqrshrn_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_N_U64: // UQRSHRN Vd.2S,Vn.2D,#n uint32x2_t vqrshrn_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUN_N_S16: // SQRSHRUN Vd.8B,Vn.8H,#n uint8x8_t vqrshrun_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUN_N_S32: // SQRSHRUN Vd.4H,Vn.4S,#n uint16x4_t vqrshrun_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUN_N_S64: // SQRSHRUN Vd.2S,Vn.2D,#n uint32x2_t vqrshrun_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_S16: // SQSHL Vd.8H,Vn.8H,#n int16x8_t vqshlq_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_S32: // SQSHL Vd.4S,Vn.4S,#n int32x4_t vqshlq_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_S64: // SQSHL Vd.2D,Vn.2D,#n int64x2_t vqshlq_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_S8: // SQSHL Vd.16B,Vn.16B,#n int8x16_t vqshlq_n_s8(int8x16_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_U16: // UQSHL Vd.8H,Vn.8H,#n uint16x8_t vqshlq_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_U32: // UQSHL Vd.4S,Vn.4S,#n uint32x4_t vqshlq_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_U64: // UQSHL Vd.2D,Vn.2D,#n uint64x2_t vqshlq_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_U8: // UQSHL Vd.16B,Vn.16B,#n uint8x16_t vqshlq_n_u8(uint8x16_t a, const int n)
+ case ARM64_INTRIN_VQSHLUQ_N_S16: // SQSHLU Vd.8H,Vn.8H,#n uint16x8_t vqshluq_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHLUQ_N_S32: // SQSHLU Vd.4S,Vn.4S,#n uint32x4_t vqshluq_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHLUQ_N_S64: // SQSHLU Vd.2D,Vn.2D,#n uint64x2_t vqshluq_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHLUQ_N_S8: // SQSHLU Vd.16B,Vn.16B,#n uint8x16_t vqshluq_n_s8(int8x16_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_N_S16: // SQSHRN Vd.8B,Vn.8H,#n int8x8_t vqshrn_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_N_S32: // SQSHRN Vd.4H,Vn.4S,#n int16x4_t vqshrn_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_N_S64: // SQSHRN Vd.2S,Vn.2D,#n int32x2_t vqshrn_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_N_U16: // UQSHRN Vd.8B,Vn.8H,#n uint8x8_t vqshrn_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_N_U32: // UQSHRN Vd.4H,Vn.4S,#n uint16x4_t vqshrn_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_N_U64: // UQSHRN Vd.2S,Vn.2D,#n uint32x2_t vqshrn_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHRUN_N_S16: // SQSHRUN Vd.8B,Vn.8H,#n uint8x8_t vqshrun_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHRUN_N_S32: // SQSHRUN Vd.4H,Vn.4S,#n uint16x4_t vqshrun_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHRUN_N_S64: // SQSHRUN Vd.2S,Vn.2D,#n uint32x2_t vqshrun_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_N_S16: // RSHRN Vd.8B,Vn.8H,#n int8x8_t vrshrn_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_N_S32: // RSHRN Vd.4H,Vn.4S,#n int16x4_t vrshrn_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_N_S64: // RSHRN Vd.2S,Vn.2D,#n int32x2_t vrshrn_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_N_U16: // RSHRN Vd.8B,Vn.8H,#n uint8x8_t vrshrn_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_N_U32: // RSHRN Vd.4H,Vn.4S,#n uint16x4_t vrshrn_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_N_U64: // RSHRN Vd.2S,Vn.2D,#n uint32x2_t vrshrn_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_S16: // SRSHR Vd.8H,Vn.8H,#n int16x8_t vrshrq_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_S32: // SRSHR Vd.4S,Vn.4S,#n int32x4_t vrshrq_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_S64: // SRSHR Vd.2D,Vn.2D,#n int64x2_t vrshrq_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_S8: // SRSHR Vd.16B,Vn.16B,#n int8x16_t vrshrq_n_s8(int8x16_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_U16: // URSHR Vd.8H,Vn.8H,#n uint16x8_t vrshrq_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_U32: // URSHR Vd.4S,Vn.4S,#n uint32x4_t vrshrq_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_U64: // URSHR Vd.2D,Vn.2D,#n uint64x2_t vrshrq_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_U8: // URSHR Vd.16B,Vn.16B,#n uint8x16_t vrshrq_n_u8(uint8x16_t a, const int n)
+ case ARM64_INTRIN_VSHLL_HIGH_N_S16: // SHLL2 Vd.4S,Vn.8H,#n int32x4_t vshll_high_n_s16(int16x8_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_HIGH_N_S16: // SSHLL2 Vd.4S,Vn.8H,#n int32x4_t vshll_high_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VSHLL_HIGH_N_S32: // SHLL2 Vd.2D,Vn.4S,#n int64x2_t vshll_high_n_s32(int32x4_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_HIGH_N_S32: // SSHLL2 Vd.2D,Vn.4S,#n int64x2_t vshll_high_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VSHLL_HIGH_N_S8: // SHLL2 Vd.8H,Vn.16B,#n int16x8_t vshll_high_n_s8(int8x16_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_HIGH_N_S8: // SSHLL2 Vd.8H,Vn.16B,#n int16x8_t vshll_high_n_s8(int8x16_t a, const int n)
+ case ARM64_INTRIN_VSHLL_HIGH_N_U16: // SHLL2 Vd.4S,Vn.8H,#n uint32x4_t vshll_high_n_u16(uint16x8_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_HIGH_N_U16: // USHLL2 Vd.4S,Vn.8H,#n uint32x4_t vshll_high_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VSHLL_HIGH_N_U32: // SHLL2 Vd.2D,Vn.4S,#n uint64x2_t vshll_high_n_u32(uint32x4_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_HIGH_N_U32: // USHLL2 Vd.2D,Vn.4S,#n uint64x2_t vshll_high_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VSHLL_HIGH_N_U8: // SHLL2 Vd.8H,Vn.16B,#n uint16x8_t vshll_high_n_u8(uint8x16_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_HIGH_N_U8: // USHLL2 Vd.8H,Vn.16B,#n uint16x8_t vshll_high_n_u8(uint8x16_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_S16: // SHL Vd.8H,Vn.8H,#n int16x8_t vshlq_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_S32: // SHL Vd.4S,Vn.4S,#n int32x4_t vshlq_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_S64: // SHL Vd.2D,Vn.2D,#n int64x2_t vshlq_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_S8: // SHL Vd.16B,Vn.16B,#n int8x16_t vshlq_n_s8(int8x16_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_U16: // SHL Vd.8H,Vn.8H,#n uint16x8_t vshlq_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_U32: // SHL Vd.4S,Vn.4S,#n uint32x4_t vshlq_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_U64: // SHL Vd.2D,Vn.2D,#n uint64x2_t vshlq_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_U8: // SHL Vd.16B,Vn.16B,#n uint8x16_t vshlq_n_u8(uint8x16_t a, const int n)
+ case ARM64_INTRIN_VSHRN_N_S16: // SHRN Vd.8B,Vn.8H,#n int8x8_t vshrn_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VSHRN_N_S32: // SHRN Vd.4H,Vn.4S,#n int16x4_t vshrn_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VSHRN_N_S64: // SHRN Vd.2S,Vn.2D,#n int32x2_t vshrn_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VSHRN_N_U16: // SHRN Vd.8B,Vn.8H,#n uint8x8_t vshrn_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VSHRN_N_U32: // SHRN Vd.4H,Vn.4S,#n uint16x4_t vshrn_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VSHRN_N_U64: // SHRN Vd.2S,Vn.2D,#n uint32x2_t vshrn_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_S16: // SSHR Vd.8H,Vn.8H,#n int16x8_t vshrq_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_S32: // SSHR Vd.4S,Vn.4S,#n int32x4_t vshrq_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_S64: // SSHR Vd.2D,Vn.2D,#n int64x2_t vshrq_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_S8: // SSHR Vd.16B,Vn.16B,#n int8x16_t vshrq_n_s8(int8x16_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_U16: // USHR Vd.8H,Vn.8H,#n uint16x8_t vshrq_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_U32: // USHR Vd.4S,Vn.4S,#n uint32x4_t vshrq_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_U64: // USHR Vd.2D,Vn.2D,#n uint64x2_t vshrq_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_U8: // USHR Vd.16B,Vn.16B,#n uint8x16_t vshrq_n_u8(uint8x16_t a, const int n)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VSHA1CQ_U32: // SHA1C Qd,Sn,Vm.4S uint32x4_t vsha1cq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+ case ARM64_INTRIN_VSHA1MQ_U32: // SHA1M Qd,Sn,Vm.4S uint32x4_t vsha1mq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+ case ARM64_INTRIN_VSHA1PQ_U32: // SHA1P Qd,Sn,Vm.4S uint32x4_t vsha1pq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(16, false))};
+ case ARM64_INTRIN_VCOPYQ_LANEQ_P16: // INS Vd.H[lane1],Vn.H[lane2] poly16x8_t vcopyq_laneq_p16(poly16x8_t a, const int lane1, poly16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_P64: // INS Vd.D[lane1],Vn.D[lane2] poly64x2_t vcopyq_laneq_p64(poly64x2_t a, const int lane1, poly64x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_P8: // INS Vd.B[lane1],Vn.B[lane2] poly8x16_t vcopyq_laneq_p8(poly8x16_t a, const int lane1, poly8x16_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_S16: // INS Vd.H[lane1],Vn.H[lane2] int16x8_t vcopyq_laneq_s16(int16x8_t a, const int lane1, int16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_S32: // INS Vd.S[lane1],Vn.S[lane2] int32x4_t vcopyq_laneq_s32(int32x4_t a, const int lane1, int32x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_S64: // INS Vd.D[lane1],Vn.D[lane2] int64x2_t vcopyq_laneq_s64(int64x2_t a, const int lane1, int64x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_S8: // INS Vd.B[lane1],Vn.B[lane2] int8x16_t vcopyq_laneq_s8(int8x16_t a, const int lane1, int8x16_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_U16: // INS Vd.H[lane1],Vn.H[lane2] uint16x8_t vcopyq_laneq_u16(uint16x8_t a, const int lane1, uint16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_U32: // INS Vd.S[lane1],Vn.S[lane2] uint32x4_t vcopyq_laneq_u32(uint32x4_t a, const int lane1, uint32x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_U64: // INS Vd.D[lane1],Vn.D[lane2] uint64x2_t vcopyq_laneq_u64(uint64x2_t a, const int lane1, uint64x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_U8: // INS Vd.B[lane1],Vn.B[lane2] uint8x16_t vcopyq_laneq_u8(uint8x16_t a, const int lane1, uint8x16_t b, const int lane2)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VCOPYQ_LANE_P16: // INS Vd.H[lane1],Vn.H[lane2] poly16x8_t vcopyq_lane_p16(poly16x8_t a, const int lane1, poly16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_P64: // INS Vd.D[lane1],Vn.D[lane2] poly64x2_t vcopyq_lane_p64(poly64x2_t a, const int lane1, poly64x1_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_P8: // INS Vd.B[lane1],Vn.B[lane2] poly8x16_t vcopyq_lane_p8(poly8x16_t a, const int lane1, poly8x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_S16: // INS Vd.H[lane1],Vn.H[lane2] int16x8_t vcopyq_lane_s16(int16x8_t a, const int lane1, int16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_S32: // INS Vd.S[lane1],Vn.S[lane2] int32x4_t vcopyq_lane_s32(int32x4_t a, const int lane1, int32x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_S64: // INS Vd.D[lane1],Vn.D[lane2] int64x2_t vcopyq_lane_s64(int64x2_t a, const int lane1, int64x1_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_S8: // INS Vd.B[lane1],Vn.B[lane2] int8x16_t vcopyq_lane_s8(int8x16_t a, const int lane1, int8x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_U16: // INS Vd.H[lane1],Vn.H[lane2] uint16x8_t vcopyq_lane_u16(uint16x8_t a, const int lane1, uint16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_U32: // INS Vd.S[lane1],Vn.S[lane2] uint32x4_t vcopyq_lane_u32(uint32x4_t a, const int lane1, uint32x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_U64: // INS Vd.D[lane1],Vn.D[lane2] uint64x2_t vcopyq_lane_u64(uint64x2_t a, const int lane1, uint64x1_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_U8: // INS Vd.B[lane1],Vn.B[lane2] uint8x16_t vcopyq_lane_u8(uint8x16_t a, const int lane1, uint8x8_t b, const int lane2)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VADDW_S16: // SADDW Vd.4S,Vn.4S,Vm.4H int32x4_t vaddw_s16(int32x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VADDW_S32: // SADDW Vd.2D,Vn.2D,Vm.2S int64x2_t vaddw_s32(int64x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VADDW_S8: // SADDW Vd.8H,Vn.8H,Vm.8B int16x8_t vaddw_s8(int16x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VADDW_U16: // UADDW Vd.4S,Vn.4S,Vm.4H uint32x4_t vaddw_u16(uint32x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VADDW_U32: // UADDW Vd.2D,Vn.2D,Vm.2S uint64x2_t vaddw_u32(uint64x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VADDW_U8: // UADDW Vd.8H,Vn.8H,Vm.8B uint16x8_t vaddw_u8(uint16x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VSUBW_S16: // SSUBW Vd.4S,Vn.4S,Vm.4H int32x4_t vsubw_s16(int32x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VSUBW_S32: // SSUBW Vd.2D,Vn.2D,Vm.2S int64x2_t vsubw_s32(int64x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VSUBW_S8: // SSUBW Vd.8H,Vn.8H,Vm.8B int16x8_t vsubw_s8(int16x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VSUBW_U16: // USUBW Vd.4S,Vn.4S,Vm.4H uint32x4_t vsubw_u16(uint32x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VSUBW_U32: // USUBW Vd.2D,Vn.2D,Vm.2S uint64x2_t vsubw_u32(uint64x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VSUBW_U8: // USUBW Vd.8H,Vn.8H,Vm.8B uint16x8_t vsubw_u8(uint16x8_t a, uint8x8_t b)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(8, false))};
+ case ARM64_INTRIN_VMLAL_LANEQ_S16: // SMLAL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vmlal_laneq_s16(int32x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_LANEQ_S32: // SMLAL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vmlal_laneq_s32(int64x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_LANEQ_U16: // UMLAL Vd.4S,Vn.4H,Vm.H[lane] uint32x4_t vmlal_laneq_u16(uint32x4_t a, uint16x4_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_LANEQ_U32: // UMLAL Vd.2D,Vn.2S,Vm.S[lane] uint64x2_t vmlal_laneq_u32(uint64x2_t a, uint32x2_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_LANEQ_S16: // SMLSL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vmlsl_laneq_s16(int32x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_LANEQ_S32: // SMLSL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vmlsl_laneq_s32(int64x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_LANEQ_U16: // UMLSL Vd.4S,Vn.4H,Vm.H[lane] uint32x4_t vmlsl_laneq_u16(uint32x4_t a, uint16x4_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_LANEQ_U32: // UMLSL Vd.2D,Vn.2S,Vm.S[lane] uint64x2_t vmlsl_laneq_u32(uint64x2_t a, uint32x2_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_LANEQ_S16: // SQDMLAL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vqdmlal_laneq_s16(int32x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_LANEQ_S32: // SQDMLAL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vqdmlal_laneq_s32(int64x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_LANEQ_S16: // SQDMLSL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vqdmlsl_laneq_s16(int32x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_LANEQ_S32: // SQDMLSL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vqdmlsl_laneq_s32(int64x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VMLAL_N_S16: // SMLAL Vd.4S,Vn.4H,Vm.H[0] int32x4_t vmlal_n_s16(int32x4_t a, int16x4_t b, int16_t c)
+ case ARM64_INTRIN_VMLAL_N_U16: // UMLAL Vd.4S,Vn.4H,Vm.H[0] uint32x4_t vmlal_n_u16(uint32x4_t a, uint16x4_t b, uint16_t c)
+ case ARM64_INTRIN_VMLSL_N_S16: // SMLSL Vd.4S,Vn.4H,Vm.H[0] int32x4_t vmlsl_n_s16(int32x4_t a, int16x4_t b, int16_t c)
+ case ARM64_INTRIN_VMLSL_N_U16: // UMLSL Vd.4S,Vn.4H,Vm.H[0] uint32x4_t vmlsl_n_u16(uint32x4_t a, uint16x4_t b, uint16_t c)
+ case ARM64_INTRIN_VQDMLAL_N_S16: // SQDMLAL Vd.4S,Vn.4H,Vm.H[0] int32x4_t vqdmlal_n_s16(int32x4_t a, int16x4_t b, int16_t c)
+ case ARM64_INTRIN_VQDMLSL_N_S16: // SQDMLSL Vd.4S,Vn.4H,Vm.H[0] int32x4_t vqdmlsl_n_s16(int32x4_t a, int16x4_t b, int16_t c)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(2, false))};
+ case ARM64_INTRIN_VMLAL_N_S32: // SMLAL Vd.2D,Vn.2S,Vm.S[0] int64x2_t vmlal_n_s32(int64x2_t a, int32x2_t b, int32_t c)
+ case ARM64_INTRIN_VMLAL_N_U32: // UMLAL Vd.2D,Vn.2S,Vm.S[0] uint64x2_t vmlal_n_u32(uint64x2_t a, uint32x2_t b, uint32_t c)
+ case ARM64_INTRIN_VMLSL_N_S32: // SMLSL Vd.2D,Vn.2S,Vm.S[0] int64x2_t vmlsl_n_s32(int64x2_t a, int32x2_t b, int32_t c)
+ case ARM64_INTRIN_VMLSL_N_U32: // UMLSL Vd.2D,Vn.2S,Vm.S[0] uint64x2_t vmlsl_n_u32(uint64x2_t a, uint32x2_t b, uint32_t c)
+ case ARM64_INTRIN_VMULL_HIGH_LANE_S16: // SMULL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vmull_high_lane_s16(int16x8_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULL_HIGH_LANE_S32: // SMULL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vmull_high_lane_s32(int32x4_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULL_HIGH_LANE_U16: // UMULL2 Vd.4S,Vn.8H,Vm.H[lane] uint32x4_t vmull_high_lane_u16(uint16x8_t a, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULL_HIGH_LANE_U32: // UMULL2 Vd.2D,Vn.4S,Vm.S[lane] uint64x2_t vmull_high_lane_u32(uint32x4_t a, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANE_S16: // MUL Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vmulq_lane_s16(int16x8_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANE_S32: // MUL Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vmulq_lane_s32(int32x4_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANE_U16: // MUL Vd.8H,Vn.8H,Vm.H[lane] uint16x8_t vmulq_lane_u16(uint16x8_t a, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANE_U32: // MUL Vd.4S,Vn.4S,Vm.S[lane] uint32x4_t vmulq_lane_u32(uint32x4_t a, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_N_S32: // SQDMLAL Vd.2D,Vn.2S,Vm.S[0] int64x2_t vqdmlal_n_s32(int64x2_t a, int32x2_t b, int32_t c)
+ case ARM64_INTRIN_VQDMLSL_N_S32: // SQDMLSL Vd.2D,Vn.2S,Vm.S[0] int64x2_t vqdmlsl_n_s32(int64x2_t a, int32x2_t b, int32_t c)
+ case ARM64_INTRIN_VQDMULHQ_LANE_S16: // SQDMULH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqdmulhq_lane_s16(int16x8_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULHQ_LANE_S32: // SQDMULH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqdmulhq_lane_s32(int32x4_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_HIGH_LANE_S16: // SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vqdmull_high_lane_s16(int16x8_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_HIGH_LANE_S32: // SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vqdmull_high_lane_s32(int32x4_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHQ_LANE_S16: // SQRDMULH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqrdmulhq_lane_s16(int16x8_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHQ_LANE_S32: // SQRDMULH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqrdmulhq_lane_s32(int32x4_t a, int32x2_t v, const int lane)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VABAL_S16: // SABAL Vd.4S,Vn.4H,Vm.4H int32x4_t vabal_s16(int32x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VABAL_S32: // SABAL Vd.2D,Vn.2S,Vm.2S int64x2_t vabal_s32(int64x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VABAL_S8: // SABAL Vd.8H,Vn.8B,Vm.8B int16x8_t vabal_s8(int16x8_t a, int8x8_t b, int8x8_t c)
+ case ARM64_INTRIN_VABAL_U16: // UABAL Vd.4S,Vn.4H,Vm.4H uint32x4_t vabal_u16(uint32x4_t a, uint16x4_t b, uint16x4_t c)
+ case ARM64_INTRIN_VABAL_U32: // UABAL Vd.2D,Vn.2S,Vm.2S uint64x2_t vabal_u32(uint64x2_t a, uint32x2_t b, uint32x2_t c)
+ case ARM64_INTRIN_VABAL_U8: // UABAL Vd.8H,Vn.8B,Vm.8B uint16x8_t vabal_u8(uint16x8_t a, uint8x8_t b, uint8x8_t c)
+ case ARM64_INTRIN_VMLAL_S16: // SMLAL Vd.4S,Vn.4H,Vm.4H int32x4_t vmlal_s16(int32x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VMLAL_S32: // SMLAL Vd.2D,Vn.2S,Vm.2S int64x2_t vmlal_s32(int64x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VMLAL_S8: // SMLAL Vd.8H,Vn.8B,Vm.8B int16x8_t vmlal_s8(int16x8_t a, int8x8_t b, int8x8_t c)
+ case ARM64_INTRIN_VMLAL_U16: // UMLAL Vd.4S,Vn.4H,Vm.4H uint32x4_t vmlal_u16(uint32x4_t a, uint16x4_t b, uint16x4_t c)
+ case ARM64_INTRIN_VMLAL_U32: // UMLAL Vd.2D,Vn.2S,Vm.2S uint64x2_t vmlal_u32(uint64x2_t a, uint32x2_t b, uint32x2_t c)
+ case ARM64_INTRIN_VMLAL_U8: // UMLAL Vd.8H,Vn.8B,Vm.8B uint16x8_t vmlal_u8(uint16x8_t a, uint8x8_t b, uint8x8_t c)
+ case ARM64_INTRIN_VMLSL_S16: // SMLSL Vd.4S,Vn.4H,Vm.4H int32x4_t vmlsl_s16(int32x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VMLSL_S32: // SMLSL Vd.2D,Vn.2S,Vm.2S int64x2_t vmlsl_s32(int64x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VMLSL_S8: // SMLSL Vd.8H,Vn.8B,Vm.8B int16x8_t vmlsl_s8(int16x8_t a, int8x8_t b, int8x8_t c)
+ case ARM64_INTRIN_VMLSL_U16: // UMLSL Vd.4S,Vn.4H,Vm.4H uint32x4_t vmlsl_u16(uint32x4_t a, uint16x4_t b, uint16x4_t c)
+ case ARM64_INTRIN_VMLSL_U32: // UMLSL Vd.2D,Vn.2S,Vm.2S uint64x2_t vmlsl_u32(uint64x2_t a, uint32x2_t b, uint32x2_t c)
+ case ARM64_INTRIN_VMLSL_U8: // UMLSL Vd.8H,Vn.8B,Vm.8B uint16x8_t vmlsl_u8(uint16x8_t a, uint8x8_t b, uint8x8_t c)
+ case ARM64_INTRIN_VQDMLAL_S16: // SQDMLAL Vd.4S,Vn.4H,Vm.4H int32x4_t vqdmlal_s16(int32x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VQDMLAL_S32: // SQDMLAL Vd.2D,Vn.2S,Vm.2S int64x2_t vqdmlal_s32(int64x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VQDMLSL_S16: // SQDMLSL Vd.4S,Vn.4H,Vm.4H int32x4_t vqdmlsl_s16(int32x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VQDMLSL_S32: // SQDMLSL Vd.2D,Vn.2S,Vm.2S int64x2_t vqdmlsl_s32(int64x2_t a, int32x2_t b, int32x2_t c)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false))};
+ case ARM64_INTRIN_VMLAL_LANE_S16: // SMLAL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vmlal_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_LANE_S32: // SMLAL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vmlal_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_LANE_U16: // UMLAL Vd.4S,Vn.4H,Vm.H[lane] uint32x4_t vmlal_lane_u16(uint32x4_t a, uint16x4_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_LANE_U32: // UMLAL Vd.2D,Vn.2S,Vm.S[lane] uint64x2_t vmlal_lane_u32(uint64x2_t a, uint32x2_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_LANE_S16: // SMLSL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vmlsl_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_LANE_S32: // SMLSL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vmlsl_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_LANE_U16: // UMLSL Vd.4S,Vn.4H,Vm.H[lane] uint32x4_t vmlsl_lane_u16(uint32x4_t a, uint16x4_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_LANE_U32: // UMLSL Vd.2D,Vn.2S,Vm.S[lane] uint64x2_t vmlsl_lane_u32(uint64x2_t a, uint32x2_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_LANE_S16: // SQDMLAL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vqdmlal_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_LANE_S32: // SQDMLAL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vqdmlal_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_LANE_S16: // SQDMLSL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vqdmlsl_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_LANE_S32: // SQDMLSL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vqdmlsl_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ return {NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VCVTH_F16_S16: // SCVTF Hd,Hn float16_t vcvth_f16_s16(int16_t a)
+ case ARM64_INTRIN_VCVTH_F16_U16: // UCVTF Hd,Hn float16_t vcvth_f16_u16(uint16_t a)
+ case ARM64_INTRIN_VDUP_N_P16: // DUP Vd.4H,rn poly16x4_t vdup_n_p16(poly16_t value)
+ case ARM64_INTRIN_VDUP_N_S16: // DUP Vd.4H,rn int16x4_t vdup_n_s16(int16_t value)
+ case ARM64_INTRIN_VDUP_N_U16: // DUP Vd.4H,rn uint16x4_t vdup_n_u16(uint16_t value)
+ case ARM64_INTRIN_VDUPQ_N_P16: // DUP Vd.8H,rn poly16x8_t vdupq_n_p16(poly16_t value)
+ case ARM64_INTRIN_VDUPQ_N_S16: // DUP Vd.8H,rn int16x8_t vdupq_n_s16(int16_t value)
+ case ARM64_INTRIN_VDUPQ_N_U16: // DUP Vd.8H,rn uint16x8_t vdupq_n_u16(uint16_t value)
+ case ARM64_INTRIN_VMOV_N_P16: // DUP Vd.4H,rn poly16x4_t vmov_n_p16(poly16_t value)
+ case ARM64_INTRIN_VMOV_N_S16: // DUP Vd.4H,rn int16x4_t vmov_n_s16(int16_t value)
+ case ARM64_INTRIN_VMOV_N_U16: // DUP Vd.4H,rn uint16x4_t vmov_n_u16(uint16_t value)
+ case ARM64_INTRIN_VMOVQ_N_P16: // DUP Vd.8H,rn poly16x8_t vmovq_n_p16(poly16_t value)
+ case ARM64_INTRIN_VMOVQ_N_S16: // DUP Vd.8H,rn int16x8_t vmovq_n_s16(int16_t value)
+ case ARM64_INTRIN_VMOVQ_N_U16: // DUP Vd.8H,rn uint16x8_t vmovq_n_u16(uint16_t value)
+ case ARM64_INTRIN_VQABSH_S16: // SQABS Hd,Hn int16_t vqabsh_s16(int16_t a)
+ case ARM64_INTRIN_VQMOVNH_S16: // SQXTN Bd,Hn int8_t vqmovnh_s16(int16_t a)
+ case ARM64_INTRIN_VQMOVNH_U16: // UQXTN Bd,Hn uint8_t vqmovnh_u16(uint16_t a)
+ case ARM64_INTRIN_VQMOVUNH_S16: // SQXTUN Bd,Hn uint8_t vqmovunh_s16(int16_t a)
+ case ARM64_INTRIN_VQNEGH_S16: // SQNEG Hd,Hn int16_t vqnegh_s16(int16_t a)
+ return {NameAndType(Type::IntegerType(2, false))};
+ case ARM64_INTRIN_VQDMULHH_LANEQ_S16: // SQDMULH Hd,Hn,Vm.H[lane] int16_t vqdmulhh_laneq_s16(int16_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMULLH_LANEQ_S16: // SQDMULL Sd,Hn,Vm.H[lane] int32_t vqdmullh_laneq_s16(int16_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHH_LANEQ_S16: // SQRDMULH Hd,Hn,Vm.H[lane] int16_t vqrdmulhh_laneq_s16(int16_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_P16: // MOV Vd.H[lane],Rn poly16x8_t vsetq_lane_p16(poly16_t a, poly16x8_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_S16: // MOV Vd.H[lane],Rn int16x8_t vsetq_lane_s16(int16_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_U16: // MOV Vd.H[lane],Rn uint16x8_t vsetq_lane_u16(uint16_t a, uint16x8_t v, const int lane)
+ return {NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VQADDH_S16: // SQADD Hd,Hn,Hm int16_t vqaddh_s16(int16_t a, int16_t b)
+ case ARM64_INTRIN_VQADDH_U16: // UQADD Hd,Hn,Hm uint16_t vqaddh_u16(uint16_t a, uint16_t b)
+ case ARM64_INTRIN_VQDMULHH_S16: // SQDMULH Hd,Hn,Hm int16_t vqdmulhh_s16(int16_t a, int16_t b)
+ case ARM64_INTRIN_VQDMULLH_S16: // SQDMULL Sd,Hn,Hm int32_t vqdmullh_s16(int16_t a, int16_t b)
+ case ARM64_INTRIN_VQRDMULHH_S16: // SQRDMULH Hd,Hn,Hm int16_t vqrdmulhh_s16(int16_t a, int16_t b)
+ case ARM64_INTRIN_VQRSHLH_S16: // SQRSHL Hd,Hn,Hm int16_t vqrshlh_s16(int16_t a, int16_t b)
+ case ARM64_INTRIN_VQRSHLH_U16: // UQRSHL Hd,Hn,Hm uint16_t vqrshlh_u16(uint16_t a, int16_t b)
+ case ARM64_INTRIN_VQSHLH_S16: // SQSHL Hd,Hn,Hm int16_t vqshlh_s16(int16_t a, int16_t b)
+ case ARM64_INTRIN_VQSHLH_U16: // UQSHL Hd,Hn,Hm uint16_t vqshlh_u16(uint16_t a, int16_t b)
+ case ARM64_INTRIN_VQSUBH_S16: // SQSUB Hd,Hn,Hm int16_t vqsubh_s16(int16_t a, int16_t b)
+ case ARM64_INTRIN_VQSUBH_U16: // UQSUB Hd,Hn,Hm uint16_t vqsubh_u16(uint16_t a, uint16_t b)
+ case ARM64_INTRIN_VSQADDH_U16: // USQADD Hd,Hn uint16_t vsqaddh_u16(uint16_t a, int16_t b)
+ case ARM64_INTRIN_VUQADDH_S16: // SUQADD Hd,Hn int16_t vuqaddh_s16(int16_t a, uint16_t b)
+ return {NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false))};
+ case ARM64_INTRIN_VQRDMLAHH_LANEQ_S16: // SQRDMLAH Hd,Hn,Vm.H[lane] int16_t vqrdmlahh_laneq_s16(int16_t a, int16_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHH_LANEQ_S16: // SQRDMLSH Hd,Hn,Vm.H[lane] int16_t vqrdmlshh_laneq_s16(int16_t a, int16_t b, int16x8_t v, const int lane)
+ return {NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VQRDMLAHH_S16: // SQRDMLSH Hd,Hn,Hm int16_t vqrdmlahh_s16(int16_t a, int16_t b, int16_t c)
+ case ARM64_INTRIN_VQRDMLSHH_S16: // SQRDMLSH Hd,Hn,Hm int16_t vqrdmlshh_s16(int16_t a, int16_t b, int16_t c)
+ return {NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false))};
+ case ARM64_INTRIN_VQRDMLAHH_LANE_S16: // SQRDMLAH Hd,Hn,Vm.H[lane] int16_t vqrdmlahh_lane_s16(int16_t a, int16_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHH_LANE_S16: // SQRDMLSH Hd,Hn,Vm.H[lane] int16_t vqrdmlshh_lane_s16(int16_t a, int16_t b, int16x4_t v, const int lane)
+ return {NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VCVTH_N_F16_S16: // SCVTF Hd,Hn,#n float16_t vcvth_n_f16_s16(int16_t a, const int n)
+ case ARM64_INTRIN_VCVTH_N_F16_U16: // UCVTF Hd,Hn,#n float16_t vcvth_n_f16_u16(uint16_t a, const int n)
+ case ARM64_INTRIN_VQRSHRNH_N_S16: // SQRSHRN Bd,Hn,#n int8_t vqrshrnh_n_s16(int16_t a, const int n)
+ case ARM64_INTRIN_VQRSHRNH_N_U16: // UQRSHRN Bd,Hn,#n uint8_t vqrshrnh_n_u16(uint16_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUNH_N_S16: // SQRSHRUN Bd,Hn,#n uint8_t vqrshrunh_n_s16(int16_t a, const int n)
+ case ARM64_INTRIN_VQSHLH_N_S16: // SQSHL Hd,Hn,#n int16_t vqshlh_n_s16(int16_t a, const int n)
+ case ARM64_INTRIN_VQSHLH_N_U16: // UQSHL Hd,Hn,#n uint16_t vqshlh_n_u16(uint16_t a, const int n)
+ case ARM64_INTRIN_VQSHLUH_N_S16: // SQSHLU Hd,Hn,#n uint16_t vqshluh_n_s16(int16_t a, const int n)
+ case ARM64_INTRIN_VQSHRNH_N_S16: // SQSHRN Bd,Hn,#n int8_t vqshrnh_n_s16(int16_t a, const int n)
+ case ARM64_INTRIN_VQSHRNH_N_U16: // UQSHRN Bd,Hn,#n uint8_t vqshrnh_n_u16(uint16_t a, const int n)
+ case ARM64_INTRIN_VQSHRUNH_N_S16: // SQSHRUN Bd,Hn,#n uint8_t vqshrunh_n_s16(int16_t a, const int n)
+ return {NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VQDMULHH_LANE_S16: // SQDMULH Hd,Hn,Vm.H[lane] int16_t vqdmulhh_lane_s16(int16_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULLH_LANE_S16: // SQDMULL Sd,Hn,Vm.H[lane] int32_t vqdmullh_lane_s16(int16_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHH_LANE_S16: // SQRDMULH Hd,Hn,Vm.H[lane] int16_t vqrdmulhh_lane_s16(int16_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_P16: // MOV Vd.H[lane],Rn poly16x4_t vset_lane_p16(poly16_t a, poly16x4_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_S16: // MOV Vd.H[lane],Rn int16x4_t vset_lane_s16(int16_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_U16: // MOV Vd.H[lane],Rn uint16x4_t vset_lane_u16(uint16_t a, uint16x4_t v, const int lane)
+ return {NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VCVTH_F16_S32: // SCVTF Hd,Hn float16_t vcvth_f16_s32(int32_t a)
+ case ARM64_INTRIN_VCVTH_F16_U32: // UCVTF Hd,Hn float16_t vcvth_f16_u32(uint32_t a)
+ case ARM64_INTRIN_VCVTS_F32_S32: // SCVTF Wd,Sn float32_t vcvts_f32_s32(int32_t a)
+ case ARM64_INTRIN_VCVTS_F32_U32: // UCVTF Wd,Sn float32_t vcvts_f32_u32(uint32_t a)
+ case ARM64_INTRIN_VDUP_N_S32: // DUP Vd.2S,rn int32x2_t vdup_n_s32(int32_t value)
+ case ARM64_INTRIN_VDUP_N_U32: // DUP Vd.2S,rn uint32x2_t vdup_n_u32(uint32_t value)
+ case ARM64_INTRIN_VDUPQ_N_S32: // DUP Vd.4S,rn int32x4_t vdupq_n_s32(int32_t value)
+ case ARM64_INTRIN_VDUPQ_N_U32: // DUP Vd.4S,rn uint32x4_t vdupq_n_u32(uint32_t value)
+ case ARM64_INTRIN_VMOV_N_S32: // DUP Vd.2S,rn int32x2_t vmov_n_s32(int32_t value)
+ case ARM64_INTRIN_VMOV_N_U32: // DUP Vd.2S,rn uint32x2_t vmov_n_u32(uint32_t value)
+ case ARM64_INTRIN_VMOVQ_N_S32: // DUP Vd.4S,rn int32x4_t vmovq_n_s32(int32_t value)
+ case ARM64_INTRIN_VMOVQ_N_U32: // DUP Vd.4S,rn uint32x4_t vmovq_n_u32(uint32_t value)
+ case ARM64_INTRIN_VQABSS_S32: // SQABS Sd,Sn int32_t vqabss_s32(int32_t a)
+ case ARM64_INTRIN_VQMOVNS_S32: // SQXTN Hd,Sn int16_t vqmovns_s32(int32_t a)
+ case ARM64_INTRIN_VQMOVNS_U32: // UQXTN Hd,Sn uint16_t vqmovns_u32(uint32_t a)
+ case ARM64_INTRIN_VQMOVUNS_S32: // SQXTUN Hd,Sn uint16_t vqmovuns_s32(int32_t a)
+ case ARM64_INTRIN_VQNEGS_S32: // SQNEG Sd,Sn int32_t vqnegs_s32(int32_t a)
+ case ARM64_INTRIN_VSHA1H_U32: // SHA1H Sd,Sn uint32_t vsha1h_u32(uint32_t hash_e)
+ return {NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN___CRC32B: // CRC32B Wd,Wn,Wm uint32_t __crc32b(uint32_t a, uint8_t b)
+ case ARM64_INTRIN___CRC32CB: // CRC32CB Wd,Wn,Wm uint32_t __crc32cb(uint32_t a, uint8_t b)
+ return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(1, false))};
+ case ARM64_INTRIN_VQDMULHS_LANEQ_S32: // SQDMULH Sd,Sn,Vm.H[lane] int32_t vqdmulhs_laneq_s32(int32_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULLS_LANEQ_S32: // SQDMULL Dd,Sn,Vm.S[lane] int64_t vqdmulls_laneq_s32(int32_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHS_LANEQ_S32: // SQRDMULH Sd,Sn,Vm.S[lane] int32_t vqrdmulhs_laneq_s32(int32_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_S32: // MOV Vd.S[lane],Rn int32x4_t vsetq_lane_s32(int32_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_U32: // MOV Vd.S[lane],Rn uint32x4_t vsetq_lane_u32(uint32_t a, uint32x4_t v, const int lane)
+ return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN___CRC32CH: // CRC32CH Wd,Wn,Wm uint32_t __crc32ch(uint32_t a, uint16_t b)
+ case ARM64_INTRIN___CRC32H: // CRC32H Wd,Wn,Wm uint32_t __crc32h(uint32_t a, uint16_t b)
+ return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(2, false))};
+ case ARM64_INTRIN_VQDMLALH_LANEQ_S16: // SQDMLAL Sd,Hn,Vm.H[lane] int32_t vqdmlalh_laneq_s16(int32_t a, int16_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSLH_LANEQ_S16: // SQDMLSL Sd,Hn,Vm.H[lane] int32_t vqdmlslh_laneq_s16(int32_t a, int16_t b, int16x8_t v, const int lane)
+ return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VQDMLALH_S16: // SQDMLAL Sd,Hn,Hm int32_t vqdmlalh_s16(int32_t a, int16_t b, int16_t c)
+ case ARM64_INTRIN_VQDMLSLH_S16: // SQDMLSL Sd,Hn,Hm int32_t vqdmlslh_s16(int32_t a, int16_t b, int16_t c)
+ return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(2, false))};
+ case ARM64_INTRIN_VQDMLALH_LANE_S16: // SQDMLAL Sd,Hn,Vm.H[lane] int32_t vqdmlalh_lane_s16(int32_t a, int16_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSLH_LANE_S16: // SQDMLSL Sd,Hn,Vm.H[lane] int32_t vqdmlslh_lane_s16(int32_t a, int16_t b, int16x4_t v, const int lane)
+ return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(2, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN___CRC32CW: // CRC32CW Wd,Wn,Wm uint32_t __crc32cw(uint32_t a, uint32_t b)
+ case ARM64_INTRIN___CRC32W: // CRC32W Wd,Wn,Wm uint32_t __crc32w(uint32_t a, uint32_t b)
+ case ARM64_INTRIN_VCVTH_N_F16_S32: // SCVTF Hd,Hn,#n float16_t vcvth_n_f16_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VCVTH_N_F16_U32: // UCVTF Hd,Hn,#n float16_t vcvth_n_f16_u32(uint32_t a, const int n)
+ case ARM64_INTRIN_VCVTS_N_F32_S32: // SCVTF Sd,Sn,#n float32_t vcvts_n_f32_s32(int32_t a, const int n)
+ // case ARM64_INTRIN_VCVTS_N_F32_S32: // SCVTF Wd,Sn,#n float32_t vcvts_n_f32_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VCVTS_N_F32_U32: // UCVTF Sd,Sn,#n float32_t vcvts_n_f32_u32(uint32_t a, const int n)
+ // case ARM64_INTRIN_VCVTS_N_F32_U32: // UCVTF Wd,Sn,#n float32_t vcvts_n_f32_u32(uint32_t a, const int n)
+ case ARM64_INTRIN_VQADDS_S32: // SQADD Sd,Sn,Sm int32_t vqadds_s32(int32_t a, int32_t b)
+ case ARM64_INTRIN_VQADDS_U32: // UQADD Sd,Sn,Sm uint32_t vqadds_u32(uint32_t a, uint32_t b)
+ case ARM64_INTRIN_VQDMULHS_S32: // SQDMULH Sd,Sn,Sm int32_t vqdmulhs_s32(int32_t a, int32_t b)
+ case ARM64_INTRIN_VQDMULLS_S32: // SQDMULL Dd,Sn,Sm int64_t vqdmulls_s32(int32_t a, int32_t b)
+ case ARM64_INTRIN_VQRDMULHS_S32: // SQRDMULH Sd,Sn,Sm int32_t vqrdmulhs_s32(int32_t a, int32_t b)
+ case ARM64_INTRIN_VQRSHLS_S32: // SQRSHL Sd,Sn,Sm int32_t vqrshls_s32(int32_t a, int32_t b)
+ case ARM64_INTRIN_VQRSHLS_U32: // UQRSHL Sd,Sn,Sm uint32_t vqrshls_u32(uint32_t a, int32_t b)
+ case ARM64_INTRIN_VQRSHRNS_N_S32: // SQRSHRN Hd,Sn,#n int16_t vqrshrns_n_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VQRSHRNS_N_U32: // UQRSHRN Hd,Sn,#n uint16_t vqrshrns_n_u32(uint32_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUNS_N_S32: // SQRSHRUN Hd,Sn,#n uint16_t vqrshruns_n_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VQSHLS_N_S32: // SQSHL Sd,Sn,#n int32_t vqshls_n_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VQSHLS_N_U32: // UQSHL Sd,Sn,#n uint32_t vqshls_n_u32(uint32_t a, const int n)
+ case ARM64_INTRIN_VQSHLS_S32: // SQSHL Sd,Sn,Sm int32_t vqshls_s32(int32_t a, int32_t b)
+ case ARM64_INTRIN_VQSHLS_U32: // UQSHL Sd,Sn,Sm uint32_t vqshls_u32(uint32_t a, int32_t b)
+ case ARM64_INTRIN_VQSHLUS_N_S32: // SQSHLU Sd,Sn,#n uint32_t vqshlus_n_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VQSHRNS_N_S32: // SQSHRN Hd,Sn,#n int16_t vqshrns_n_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VQSHRNS_N_U32: // UQSHRN Hd,Sn,#n uint16_t vqshrns_n_u32(uint32_t a, const int n)
+ case ARM64_INTRIN_VQSHRUNS_N_S32: // SQSHRUN Hd,Sn,#n uint16_t vqshruns_n_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VQSUBS_S32: // SQSUB Sd,Sn,Sm int32_t vqsubs_s32(int32_t a, int32_t b)
+ case ARM64_INTRIN_VQSUBS_U32: // UQSUB Sd,Sn,Sm uint32_t vqsubs_u32(uint32_t a, uint32_t b)
+ case ARM64_INTRIN_VSQADDS_U32: // USQADD Sd,Sn uint32_t vsqadds_u32(uint32_t a, int32_t b)
+ case ARM64_INTRIN_VUQADDS_S32: // SUQADD Sd,Sn int32_t vuqadds_s32(int32_t a, uint32_t b)
+ return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VQRDMLAHS_LANEQ_S32: // SQRDMLAH Sd,Sn,Vm.S[lane] int32_t vqrdmlahs_laneq_s32(int32_t a, int32_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHS_LANEQ_S32: // SQRDMLSH Sd,Sn,Vm.S[lane] int32_t vqrdmlshs_laneq_s32(int32_t a, int32_t b, int32x4_t v, const int lane)
+ return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VQRDMLAHS_S32: // SQRDMLSH Sd,Sn,Sm int32_t vqrdmlahs_s32(int32_t a, int32_t b, int32_t c)
+ case ARM64_INTRIN_VQRDMLSHS_S32: // SQRDMLSH Sd,Sn,Sm int32_t vqrdmlshs_s32(int32_t a, int32_t b, int32_t c)
+ return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VQRDMLAHS_LANE_S32: // SQRDMLAH Sd,Sn,Vm.S[lane] int32_t vqrdmlahs_lane_s32(int32_t a, int32_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHS_LANE_S32: // SQRDMLSH Sd,Sn,Vm.S[lane] int32_t vqrdmlshs_lane_s32(int32_t a, int32_t b, int32x2_t v, const int lane)
+ return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN___CRC32CD: // CRC32CX Wd,Wn,Xm uint32_t __crc32cd(uint32_t a, uint64_t b)
+ case ARM64_INTRIN___CRC32D: // CRC32X Wd,Wn,Xm uint32_t __crc32d(uint32_t a, uint64_t b)
+ return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(8, false))};
+ case ARM64_INTRIN_VQDMULHS_LANE_S32: // SQDMULH Sd,Sn,Vm.H[lane] int32_t vqdmulhs_lane_s32(int32_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMULLS_LANE_S32: // SQDMULL Dd,Sn,Vm.S[lane] int64_t vqdmulls_lane_s32(int32_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHS_LANE_S32: // SQRDMULH Sd,Sn,Vm.S[lane] int32_t vqrdmulhs_lane_s32(int32_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_S32: // MOV Vd.S[lane],Rn int32x2_t vset_lane_s32(int32_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_U32: // MOV Vd.S[lane],Rn uint32x2_t vset_lane_u32(uint32_t a, uint32x2_t v, const int lane)
+ return {NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VABS_S16: // ABS Vd.4H,Vn.4H int16x4_t vabs_s16(int16x4_t a)
+ case ARM64_INTRIN_VABS_S32: // ABS Vd.2S,Vn.2S int32x2_t vabs_s32(int32x2_t a)
+ case ARM64_INTRIN_VABS_S64: // ABS Dd,Dn int64x1_t vabs_s64(int64x1_t a)
+ case ARM64_INTRIN_VABS_S8: // ABS Vd.8B,Vn.8B int8x8_t vabs_s8(int8x8_t a)
+ case ARM64_INTRIN_VABSD_S64: // ABS Dd,Dn int64_t vabsd_s64(int64_t a)
+ case ARM64_INTRIN_VADDLV_S16: // SADDLV Sd,Vn.4H int32_t vaddlv_s16(int16x4_t a)
+ case ARM64_INTRIN_VADDLV_S32: // SADDLP Vd.1D,Vn.2S int64_t vaddlv_s32(int32x2_t a)
+ case ARM64_INTRIN_VADDLV_S8: // SADDLV Hd,Vn.8B int16_t vaddlv_s8(int8x8_t a)
+ case ARM64_INTRIN_VADDLV_U16: // UADDLV Sd,Vn.4H uint32_t vaddlv_u16(uint16x4_t a)
+ case ARM64_INTRIN_VADDLV_U32: // UADDLP Vd.1D,Vn.2S uint64_t vaddlv_u32(uint32x2_t a)
+ case ARM64_INTRIN_VADDLV_U8: // UADDLV Hd,Vn.8B uint16_t vaddlv_u8(uint8x8_t a)
+ case ARM64_INTRIN_VADDV_S16: // ADDV Hd,Vn.4H int16_t vaddv_s16(int16x4_t a)
+ case ARM64_INTRIN_VADDV_S32: // ADDP Vd.2S,Vn.2S,Vm.2S int32_t vaddv_s32(int32x2_t a)
+ case ARM64_INTRIN_VADDV_S8: // ADDV Bd,Vn.8B int8_t vaddv_s8(int8x8_t a)
+ case ARM64_INTRIN_VADDV_U16: // ADDV Hd,Vn.4H uint16_t vaddv_u16(uint16x4_t a)
+ case ARM64_INTRIN_VADDV_U32: // ADDP Vd.2S,Vn.2S,Vm.2S uint32_t vaddv_u32(uint32x2_t a)
+ case ARM64_INTRIN_VADDV_U8: // ADDV Bd,Vn.8B uint8_t vaddv_u8(uint8x8_t a)
+ case ARM64_INTRIN_VCEQZ_P64: // CMEQ Dd,Dn,#0 uint64x1_t vceqz_p64(poly64x1_t a)
+ case ARM64_INTRIN_VCEQZ_P8: // CMEQ Vd.8B,Vn.8B,#0 uint8x8_t vceqz_p8(poly8x8_t a)
+ case ARM64_INTRIN_VCEQZ_S16: // CMEQ Vd.4H,Vn.4H,#0 uint16x4_t vceqz_s16(int16x4_t a)
+ case ARM64_INTRIN_VCEQZ_S32: // CMEQ Vd.2S,Vn.2S,#0 uint32x2_t vceqz_s32(int32x2_t a)
+ case ARM64_INTRIN_VCEQZ_S64: // CMEQ Dd,Dn,#0 uint64x1_t vceqz_s64(int64x1_t a)
+ case ARM64_INTRIN_VCEQZ_S8: // CMEQ Vd.8B,Vn.8B,#0 uint8x8_t vceqz_s8(int8x8_t a)
+ case ARM64_INTRIN_VCEQZ_U16: // CMEQ Vd.4H,Vn.4H,#0 uint16x4_t vceqz_u16(uint16x4_t a)
+ case ARM64_INTRIN_VCEQZ_U32: // CMEQ Vd.2S,Vn.2S,#0 uint32x2_t vceqz_u32(uint32x2_t a)
+ case ARM64_INTRIN_VCEQZ_U64: // CMEQ Dd,Dn,#0 uint64x1_t vceqz_u64(uint64x1_t a)
+ case ARM64_INTRIN_VCEQZ_U8: // CMEQ Vd.8B,Vn.8B,#0 uint8x8_t vceqz_u8(uint8x8_t a)
+ case ARM64_INTRIN_VCEQZD_S64: // CMEQ Dd,Dn,#0 uint64_t vceqzd_s64(int64_t a)
+ case ARM64_INTRIN_VCEQZD_U64: // CMEQ Dd,Dn,#0 uint64_t vceqzd_u64(uint64_t a)
+ case ARM64_INTRIN_VCGEZ_S16: // CMGE Vd.4H,Vn.4H,#0 uint16x4_t vcgez_s16(int16x4_t a)
+ case ARM64_INTRIN_VCGEZ_S32: // CMGE Vd.2S,Vn.2S,#0 uint32x2_t vcgez_s32(int32x2_t a)
+ case ARM64_INTRIN_VCGEZ_S64: // CMGE Dd,Dn,#0 uint64x1_t vcgez_s64(int64x1_t a)
+ case ARM64_INTRIN_VCGEZ_S8: // CMGE Vd.8B,Vn.8B,#0 uint8x8_t vcgez_s8(int8x8_t a)
+ case ARM64_INTRIN_VCGEZD_S64: // CMGE Dd,Dn,#0 uint64_t vcgezd_s64(int64_t a)
+ case ARM64_INTRIN_VCGTZ_S16: // CMGT Vd.4H,Vn.4H,#0 uint16x4_t vcgtz_s16(int16x4_t a)
+ case ARM64_INTRIN_VCGTZ_S32: // CMGT Vd.2S,Vn.2S,#0 uint32x2_t vcgtz_s32(int32x2_t a)
+ case ARM64_INTRIN_VCGTZ_S64: // CMGT Dd,Dn,#0 uint64x1_t vcgtz_s64(int64x1_t a)
+ case ARM64_INTRIN_VCGTZ_S8: // CMGT Vd.8B,Vn.8B,#0 uint8x8_t vcgtz_s8(int8x8_t a)
+ case ARM64_INTRIN_VCGTZD_S64: // CMGT Dd,Dn,#0 uint64_t vcgtzd_s64(int64_t a)
+ case ARM64_INTRIN_VCLEZ_S16: // CMLE Vd.4H,Vn.4H,#0 uint16x4_t vclez_s16(int16x4_t a)
+ case ARM64_INTRIN_VCLEZ_S32: // CMLE Vd.2S,Vn.2S,#0 uint32x2_t vclez_s32(int32x2_t a)
+ case ARM64_INTRIN_VCLEZ_S64: // CMLE Dd,Dn,#0 uint64x1_t vclez_s64(int64x1_t a)
+ case ARM64_INTRIN_VCLEZ_S8: // CMLE Vd.8B,Vn.8B,#0 uint8x8_t vclez_s8(int8x8_t a)
+ case ARM64_INTRIN_VCLEZD_S64: // CMLE Dd,Dn,#0 uint64_t vclezd_s64(int64_t a)
+ case ARM64_INTRIN_VCLS_S16: // CLS Vd.4H,Vn.4H int16x4_t vcls_s16(int16x4_t a)
+ case ARM64_INTRIN_VCLS_S32: // CLS Vd.2S,Vn.2S int32x2_t vcls_s32(int32x2_t a)
+ case ARM64_INTRIN_VCLS_S8: // CLS Vd.8B,Vn.8B int8x8_t vcls_s8(int8x8_t a)
+ case ARM64_INTRIN_VCLS_U16: // CLS Vd.4H,Vn.4H int16x4_t vcls_u16(uint16x4_t a)
+ case ARM64_INTRIN_VCLS_U32: // CLS Vd.2S,Vn.2S int32x2_t vcls_u32(uint32x2_t a)
+ case ARM64_INTRIN_VCLS_U8: // CLS Vd.8B,Vn.8B int8x8_t vcls_u8(uint8x8_t a)
+ case ARM64_INTRIN_VCLTZ_S16: // CMLT Vd.4H,Vn.4H,#0 uint16x4_t vcltz_s16(int16x4_t a)
+ case ARM64_INTRIN_VCLTZ_S32: // CMLT Vd.2S,Vn.2S,#0 uint32x2_t vcltz_s32(int32x2_t a)
+ case ARM64_INTRIN_VCLTZ_S64: // CMLT Dd,Dn,#0 uint64x1_t vcltz_s64(int64x1_t a)
+ case ARM64_INTRIN_VCLTZ_S8: // CMLT Vd.8B,Vn.8B,#0 uint8x8_t vcltz_s8(int8x8_t a)
+ case ARM64_INTRIN_VCLTZD_S64: // CMLT Dd,Dn,#0 uint64_t vcltzd_s64(int64_t a)
+ case ARM64_INTRIN_VCLZ_S16: // CLZ Vd.4H,Vn.4H int16x4_t vclz_s16(int16x4_t a)
+ case ARM64_INTRIN_VCLZ_S32: // CLZ Vd.2S,Vn.2S int32x2_t vclz_s32(int32x2_t a)
+ case ARM64_INTRIN_VCLZ_S8: // CLZ Vd.8B,Vn.8B int8x8_t vclz_s8(int8x8_t a)
+ case ARM64_INTRIN_VCLZ_U16: // CLZ Vd.4H,Vn.4H uint16x4_t vclz_u16(uint16x4_t a)
+ case ARM64_INTRIN_VCLZ_U32: // CLZ Vd.2S,Vn.2S uint32x2_t vclz_u32(uint32x2_t a)
+ case ARM64_INTRIN_VCLZ_U8: // CLZ Vd.8B,Vn.8B uint8x8_t vclz_u8(uint8x8_t a)
+ case ARM64_INTRIN_VCNT_P8: // CNT Vd.8B,Vn.8B poly8x8_t vcnt_p8(poly8x8_t a)
+ case ARM64_INTRIN_VCNT_S8: // CNT Vd.8B,Vn.8B int8x8_t vcnt_s8(int8x8_t a)
+ case ARM64_INTRIN_VCNT_U8: // CNT Vd.8B,Vn.8B uint8x8_t vcnt_u8(uint8x8_t a)
+ case ARM64_INTRIN_VCREATE_BF16: // INS Vd.D[0],Xn bfloat16x4_t vcreate_bf16(uint64_t a)
+ case ARM64_INTRIN_VCREATE_F16: // INS Vd.D[0],Xn float16x4_t vcreate_f16(uint64_t a)
+ case ARM64_INTRIN_VCREATE_F32: // INS Vd.D[0],Xn float32x2_t vcreate_f32(uint64_t a)
+ case ARM64_INTRIN_VCREATE_F64: // INS Vd.D[0],Xn float64x1_t vcreate_f64(uint64_t a)
+ case ARM64_INTRIN_VCREATE_P16: // INS Vd.D[0],Xn poly16x4_t vcreate_p16(uint64_t a)
+ case ARM64_INTRIN_VCREATE_P64: // INS Vd.D[0],Xn poly64x1_t vcreate_p64(uint64_t a)
+ case ARM64_INTRIN_VCREATE_P8: // INS Vd.D[0],Xn poly8x8_t vcreate_p8(uint64_t a)
+ case ARM64_INTRIN_VCREATE_S16: // INS Vd.D[0],Xn int16x4_t vcreate_s16(uint64_t a)
+ case ARM64_INTRIN_VCREATE_S32: // INS Vd.D[0],Xn int32x2_t vcreate_s32(uint64_t a)
+ case ARM64_INTRIN_VCREATE_S64: // INS Vd.D[0],Xn int64x1_t vcreate_s64(uint64_t a)
+ case ARM64_INTRIN_VCREATE_S8: // INS Vd.D[0],Xn int8x8_t vcreate_s8(uint64_t a)
+ case ARM64_INTRIN_VCREATE_U16: // INS Vd.D[0],Xn uint16x4_t vcreate_u16(uint64_t a)
+ case ARM64_INTRIN_VCREATE_U32: // INS Vd.D[0],Xn uint32x2_t vcreate_u32(uint64_t a)
+ case ARM64_INTRIN_VCREATE_U64: // INS Vd.D[0],Xn uint64x1_t vcreate_u64(uint64_t a)
+ case ARM64_INTRIN_VCREATE_U8: // INS Vd.D[0],Xn uint8x8_t vcreate_u8(uint64_t a)
+ case ARM64_INTRIN_VCVT_F16_S16: // SCVTF Vd.4H,Vn.4H,#0 float16x4_t vcvt_f16_s16(int16x4_t a)
+ case ARM64_INTRIN_VCVT_F16_U16: // UCVTF Vd.4H,Vn.4H,#0 float16x4_t vcvt_f16_u16(uint16x4_t a)
+ case ARM64_INTRIN_VCVT_F32_S32: // SCVTF Vd.2S,Vn.2S float32x2_t vcvt_f32_s32(int32x2_t a)
+ case ARM64_INTRIN_VCVT_F32_U32: // UCVTF Vd.2S,Vn.2S float32x2_t vcvt_f32_u32(uint32x2_t a)
+ case ARM64_INTRIN_VCVT_F64_S64: // SCVTF Xd,Dn float64x1_t vcvt_f64_s64(int64x1_t a)
+ case ARM64_INTRIN_VCVT_F64_U64: // UCVTF Xd,Dn float64x1_t vcvt_f64_u64(uint64x1_t a)
+ case ARM64_INTRIN_VCVTD_F64_S64: // SCVTF Xd,Dn float64_t vcvtd_f64_s64(int64_t a)
+ case ARM64_INTRIN_VCVTD_F64_U64: // UCVTF Xd,Dn float64_t vcvtd_f64_u64(uint64_t a)
+ case ARM64_INTRIN_VCVTH_F16_S64: // SCVTF Hd,Hn float16_t vcvth_f16_s64(int64_t a)
+ case ARM64_INTRIN_VCVTH_F16_U64: // UCVTF Hd,Hn float16_t vcvth_f16_u64(uint64_t a)
+ case ARM64_INTRIN_VDUP_N_P64: // INS Vd.D[0],rn poly64x1_t vdup_n_p64(poly64_t value)
+ case ARM64_INTRIN_VDUP_N_S64: // INS Vd.D[0],rn int64x1_t vdup_n_s64(int64_t value)
+ case ARM64_INTRIN_VDUP_N_U64: // INS Vd.D[0],rn uint64x1_t vdup_n_u64(uint64_t value)
+ case ARM64_INTRIN_VDUPQ_N_P64: // DUP Vd.2D,rn poly64x2_t vdupq_n_p64(poly64_t value)
+ case ARM64_INTRIN_VDUPQ_N_S64: // DUP Vd.2D,rn int64x2_t vdupq_n_s64(int64_t value)
+ case ARM64_INTRIN_VDUPQ_N_U64: // DUP Vd.2D,rn uint64x2_t vdupq_n_u64(uint64_t value)
+ case ARM64_INTRIN_VMAXV_S16: // SMAXV Hd,Vn.4H int16_t vmaxv_s16(int16x4_t a)
+ case ARM64_INTRIN_VMAXV_S32: // SMAXP Vd.2S,Vn.2S,Vm.2S int32_t vmaxv_s32(int32x2_t a)
+ case ARM64_INTRIN_VMAXV_S8: // SMAXV Bd,Vn.8B int8_t vmaxv_s8(int8x8_t a)
+ case ARM64_INTRIN_VMAXV_U16: // UMAXV Hd,Vn.4H uint16_t vmaxv_u16(uint16x4_t a)
+ case ARM64_INTRIN_VMAXV_U32: // UMAXP Vd.2S,Vn.2S,Vm.2S uint32_t vmaxv_u32(uint32x2_t a)
+ case ARM64_INTRIN_VMAXV_U8: // UMAXV Bd,Vn.8B uint8_t vmaxv_u8(uint8x8_t a)
+ case ARM64_INTRIN_VMINV_S16: // SMINV Hd,Vn.4H int16_t vminv_s16(int16x4_t a)
+ case ARM64_INTRIN_VMINV_S32: // SMINP Vd.2S,Vn.2S,Vm.2S int32_t vminv_s32(int32x2_t a)
+ case ARM64_INTRIN_VMINV_S8: // SMINV Bd,Vn.8B int8_t vminv_s8(int8x8_t a)
+ case ARM64_INTRIN_VMINV_U16: // UMINV Hd,Vn.4H uint16_t vminv_u16(uint16x4_t a)
+ case ARM64_INTRIN_VMINV_U32: // UMINP Vd.2S,Vn.2S,Vm.2S uint32_t vminv_u32(uint32x2_t a)
+ case ARM64_INTRIN_VMINV_U8: // UMINV Bd,Vn.8B uint8_t vminv_u8(uint8x8_t a)
+ case ARM64_INTRIN_VMOV_N_S64: // DUP Vd.1D,rn int64x1_t vmov_n_s64(int64_t value)
+ case ARM64_INTRIN_VMOV_N_U64: // DUP Vd.1D,rn uint64x1_t vmov_n_u64(uint64_t value)
+ case ARM64_INTRIN_VMOVL_S16: // SSHLL Vd.4S,Vn.4H,#0 int32x4_t vmovl_s16(int16x4_t a)
+ case ARM64_INTRIN_VMOVL_S32: // SSHLL Vd.2D,Vn.2S,#0 int64x2_t vmovl_s32(int32x2_t a)
+ case ARM64_INTRIN_VMOVL_S8: // SSHLL Vd.8H,Vn.8B,#0 int16x8_t vmovl_s8(int8x8_t a)
+ case ARM64_INTRIN_VMOVL_U16: // USHLL Vd.4S,Vn.4H,#0 uint32x4_t vmovl_u16(uint16x4_t a)
+ case ARM64_INTRIN_VMOVL_U32: // USHLL Vd.2D,Vn.2S,#0 uint64x2_t vmovl_u32(uint32x2_t a)
+ case ARM64_INTRIN_VMOVL_U8: // USHLL Vd.8H,Vn.8B,#0 uint16x8_t vmovl_u8(uint8x8_t a)
+ case ARM64_INTRIN_VMOVQ_N_S64: // DUP Vd.2D,rn int64x2_t vmovq_n_s64(int64_t value)
+ case ARM64_INTRIN_VMOVQ_N_U64: // DUP Vd.2D,rn uint64x2_t vmovq_n_u64(uint64_t value)
+ case ARM64_INTRIN_VMVN_P8: // MVN Vd.8B,Vn.8B poly8x8_t vmvn_p8(poly8x8_t a)
+ case ARM64_INTRIN_VMVN_S16: // MVN Vd.8B,Vn.8B int16x4_t vmvn_s16(int16x4_t a)
+ case ARM64_INTRIN_VMVN_S32: // MVN Vd.8B,Vn.8B int32x2_t vmvn_s32(int32x2_t a)
+ case ARM64_INTRIN_VMVN_S8: // MVN Vd.8B,Vn.8B int8x8_t vmvn_s8(int8x8_t a)
+ case ARM64_INTRIN_VMVN_U16: // MVN Vd.8B,Vn.8B uint16x4_t vmvn_u16(uint16x4_t a)
+ case ARM64_INTRIN_VMVN_U32: // MVN Vd.8B,Vn.8B uint32x2_t vmvn_u32(uint32x2_t a)
+ case ARM64_INTRIN_VMVN_U8: // MVN Vd.8B,Vn.8B uint8x8_t vmvn_u8(uint8x8_t a)
+ case ARM64_INTRIN_VNEG_S16: // NEG Vd.4H,Vn.4H int16x4_t vneg_s16(int16x4_t a)
+ case ARM64_INTRIN_VNEG_S32: // NEG Vd.2S,Vn.2S int32x2_t vneg_s32(int32x2_t a)
+ case ARM64_INTRIN_VNEG_S64: // NEG Dd,Dn int64x1_t vneg_s64(int64x1_t a)
+ case ARM64_INTRIN_VNEG_S8: // NEG Vd.8B,Vn.8B int8x8_t vneg_s8(int8x8_t a)
+ case ARM64_INTRIN_VNEGD_S64: // NEG Dd,Dn int64_t vnegd_s64(int64_t a)
+ case ARM64_INTRIN_VPADDL_S16: // SADDLP Vd.2S,Vn.4H int32x2_t vpaddl_s16(int16x4_t a)
+ case ARM64_INTRIN_VPADDL_S32: // SADDLP Vd.1D,Vn.2S int64x1_t vpaddl_s32(int32x2_t a)
+ case ARM64_INTRIN_VPADDL_S8: // SADDLP Vd.4H,Vn.8B int16x4_t vpaddl_s8(int8x8_t a)
+ case ARM64_INTRIN_VPADDL_U16: // UADDLP Vd.2S,Vn.4H uint32x2_t vpaddl_u16(uint16x4_t a)
+ case ARM64_INTRIN_VPADDL_U32: // UADDLP Vd.1D,Vn.2S uint64x1_t vpaddl_u32(uint32x2_t a)
+ case ARM64_INTRIN_VPADDL_U8: // UADDLP Vd.4H,Vn.8B uint16x4_t vpaddl_u8(uint8x8_t a)
+ case ARM64_INTRIN_VQABS_S16: // SQABS Vd.4H,Vn.4H int16x4_t vqabs_s16(int16x4_t a)
+ case ARM64_INTRIN_VQABS_S32: // SQABS Vd.2S,Vn.2S int32x2_t vqabs_s32(int32x2_t a)
+ case ARM64_INTRIN_VQABS_S64: // SQABS Dd,Dn int64x1_t vqabs_s64(int64x1_t a)
+ case ARM64_INTRIN_VQABS_S8: // SQABS Vd.8B,Vn.8B int8x8_t vqabs_s8(int8x8_t a)
+ case ARM64_INTRIN_VQABSD_S64: // SQABS Dd,Dn int64_t vqabsd_s64(int64_t a)
+ case ARM64_INTRIN_VQMOVND_S64: // SQXTN Sd,Dn int32_t vqmovnd_s64(int64_t a)
+ case ARM64_INTRIN_VQMOVND_U64: // UQXTN Sd,Dn uint32_t vqmovnd_u64(uint64_t a)
+ case ARM64_INTRIN_VQMOVUND_S64: // SQXTUN Sd,Dn uint32_t vqmovund_s64(int64_t a)
+ case ARM64_INTRIN_VQNEG_S16: // SQNEG Vd.4H,Vn.4H int16x4_t vqneg_s16(int16x4_t a)
+ case ARM64_INTRIN_VQNEG_S32: // SQNEG Vd.2S,Vn.2S int32x2_t vqneg_s32(int32x2_t a)
+ case ARM64_INTRIN_VQNEG_S64: // SQNEG Dd,Dn int64x1_t vqneg_s64(int64x1_t a)
+ case ARM64_INTRIN_VQNEG_S8: // SQNEG Vd.8B,Vn.8B int8x8_t vqneg_s8(int8x8_t a)
+ case ARM64_INTRIN_VQNEGD_S64: // SQNEG Dd,Dn int64_t vqnegd_s64(int64_t a)
+ case ARM64_INTRIN_VRBIT_P8: // RBIT Vd.8B,Vn.8B poly8x8_t vrbit_p8(poly8x8_t a)
+ case ARM64_INTRIN_VRBIT_S8: // RBIT Vd.8B,Vn.8B int8x8_t vrbit_s8(int8x8_t a)
+ case ARM64_INTRIN_VRBIT_U8: // RBIT Vd.8B,Vn.8B uint8x8_t vrbit_u8(uint8x8_t a)
+ case ARM64_INTRIN_VRECPE_U32: // URECPE Vd.2S,Vn.2S uint32x2_t vrecpe_u32(uint32x2_t a)
+ case ARM64_INTRIN_VREV16_P8: // REV16 Vd.8B,Vn.8B poly8x8_t vrev16_p8(poly8x8_t vec)
+ case ARM64_INTRIN_VREV16_S8: // REV16 Vd.8B,Vn.8B int8x8_t vrev16_s8(int8x8_t vec)
+ case ARM64_INTRIN_VREV16_U8: // REV16 Vd.8B,Vn.8B uint8x8_t vrev16_u8(uint8x8_t vec)
+ case ARM64_INTRIN_VREV32_P16: // REV32 Vd.4H,Vn.4H poly16x4_t vrev32_p16(poly16x4_t vec)
+ case ARM64_INTRIN_VREV32_P8: // REV32 Vd.8B,Vn.8B poly8x8_t vrev32_p8(poly8x8_t vec)
+ case ARM64_INTRIN_VREV32_S16: // REV32 Vd.4H,Vn.4H int16x4_t vrev32_s16(int16x4_t vec)
+ case ARM64_INTRIN_VREV32_S8: // REV32 Vd.8B,Vn.8B int8x8_t vrev32_s8(int8x8_t vec)
+ case ARM64_INTRIN_VREV32_U16: // REV32 Vd.4H,Vn.4H uint16x4_t vrev32_u16(uint16x4_t vec)
+ case ARM64_INTRIN_VREV32_U8: // REV32 Vd.8B,Vn.8B uint8x8_t vrev32_u8(uint8x8_t vec)
+ case ARM64_INTRIN_VREV64_P16: // REV64 Vd.4H,Vn.4H poly16x4_t vrev64_p16(poly16x4_t vec)
+ case ARM64_INTRIN_VREV64_P8: // REV64 Vd.8B,Vn.8B poly8x8_t vrev64_p8(poly8x8_t vec)
+ case ARM64_INTRIN_VREV64_S16: // REV64 Vd.4H,Vn.4H int16x4_t vrev64_s16(int16x4_t vec)
+ case ARM64_INTRIN_VREV64_S32: // REV64 Vd.2S,Vn.2S int32x2_t vrev64_s32(int32x2_t vec)
+ case ARM64_INTRIN_VREV64_S8: // REV64 Vd.8B,Vn.8B int8x8_t vrev64_s8(int8x8_t vec)
+ case ARM64_INTRIN_VREV64_U16: // REV64 Vd.4H,Vn.4H uint16x4_t vrev64_u16(uint16x4_t vec)
+ case ARM64_INTRIN_VREV64_U32: // REV64 Vd.2S,Vn.2S uint32x2_t vrev64_u32(uint32x2_t vec)
+ case ARM64_INTRIN_VREV64_U8: // REV64 Vd.8B,Vn.8B uint8x8_t vrev64_u8(uint8x8_t vec)
+ case ARM64_INTRIN_VRSQRTE_U32: // URSQRTE Vd.2S,Vn.2S uint32x2_t vrsqrte_u32(uint32x2_t a)
+ return {NameAndType(Type::IntegerType(8, false))};
+ case ARM64_INTRIN_VBSL_F16: // BSL Vd.8B,Vn.8B,Vm.8B float16x4_t vbsl_f16(uint16x4_t a, float16x4_t b, float16x4_t c)
+ case ARM64_INTRIN_VBSL_F32: // BSL Vd.8B,Vn.8B,Vm.8B float32x2_t vbsl_f32(uint32x2_t a, float32x2_t b, float32x2_t c)
+ case ARM64_INTRIN_VBSL_F64: // BSL Vd.8B,Vn.8B,Vm.8B float64x1_t vbsl_f64(uint64x1_t a, float64x1_t b, float64x1_t c)
+ return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::FloatType(8)), NameAndType(Type::FloatType(8))};
+ case ARM64_INTRIN_VMOVN_HIGH_S16: // XTN2 Vd.16B,Vn.8H int8x16_t vmovn_high_s16(int8x8_t r, int16x8_t a)
+ case ARM64_INTRIN_VMOVN_HIGH_S32: // XTN2 Vd.8H,Vn.4S int16x8_t vmovn_high_s32(int16x4_t r, int32x4_t a)
+ case ARM64_INTRIN_VMOVN_HIGH_S64: // XTN2 Vd.4S,Vn.2D int32x4_t vmovn_high_s64(int32x2_t r, int64x2_t a)
+ case ARM64_INTRIN_VMOVN_HIGH_U16: // XTN2 Vd.16B,Vn.8H uint8x16_t vmovn_high_u16(uint8x8_t r, uint16x8_t a)
+ case ARM64_INTRIN_VMOVN_HIGH_U32: // XTN2 Vd.8H,Vn.4S uint16x8_t vmovn_high_u32(uint16x4_t r, uint32x4_t a)
+ case ARM64_INTRIN_VMOVN_HIGH_U64: // XTN2 Vd.4S,Vn.2D uint32x4_t vmovn_high_u64(uint32x2_t r, uint64x2_t a)
+ case ARM64_INTRIN_VQMOVN_HIGH_S16: // SQXTN2 Vd.16B,Vn.8H int8x16_t vqmovn_high_s16(int8x8_t r, int16x8_t a)
+ case ARM64_INTRIN_VQMOVN_HIGH_S32: // SQXTN2 Vd.8H,Vn.4S int16x8_t vqmovn_high_s32(int16x4_t r, int32x4_t a)
+ case ARM64_INTRIN_VQMOVN_HIGH_S64: // SQXTN2 Vd.4S,Vn.2D int32x4_t vqmovn_high_s64(int32x2_t r, int64x2_t a)
+ case ARM64_INTRIN_VQMOVN_HIGH_U16: // UQXTN2 Vd.16B,Vn.8H uint8x16_t vqmovn_high_u16(uint8x8_t r, uint16x8_t a)
+ case ARM64_INTRIN_VQMOVN_HIGH_U32: // UQXTN2 Vd.8H,Vn.4S uint16x8_t vqmovn_high_u32(uint16x4_t r, uint32x4_t a)
+ case ARM64_INTRIN_VQMOVN_HIGH_U64: // UQXTN2 Vd.4S,Vn.2D uint32x4_t vqmovn_high_u64(uint32x2_t r, uint64x2_t a)
+ case ARM64_INTRIN_VQMOVUN_HIGH_S16: // SQXTUN2 Vd.16B,Vn.8H uint8x16_t vqmovun_high_s16(uint8x8_t r, int16x8_t a)
+ case ARM64_INTRIN_VQMOVUN_HIGH_S32: // SQXTUN2 Vd.8H,Vn.4S uint16x8_t vqmovun_high_s32(uint16x4_t r, int32x4_t a)
+ case ARM64_INTRIN_VQMOVUN_HIGH_S64: // SQXTUN2 Vd.4S,Vn.2D uint32x4_t vqmovun_high_s64(uint32x2_t r, int64x2_t a)
+ return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(16, false))};
+ case ARM64_INTRIN_VADDHN_HIGH_S16: // ADDHN2 Vd.16B,Vn.8H,Vm.8H int8x16_t vaddhn_high_s16(int8x8_t r, int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VADDHN_HIGH_S32: // ADDHN2 Vd.8H,Vn.4S,Vm.4S int16x8_t vaddhn_high_s32(int16x4_t r, int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VADDHN_HIGH_S64: // ADDHN2 Vd.4S,Vn.2D,Vm.2D int32x4_t vaddhn_high_s64(int32x2_t r, int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VADDHN_HIGH_U16: // ADDHN2 Vd.16B,Vn.8H,Vm.8H uint8x16_t vaddhn_high_u16(uint8x8_t r, uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VADDHN_HIGH_U32: // ADDHN2 Vd.8H,Vn.4S,Vm.4S uint16x8_t vaddhn_high_u32(uint16x4_t r, uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VADDHN_HIGH_U64: // ADDHN2 Vd.4S,Vn.2D,Vm.2D uint32x4_t vaddhn_high_u64(uint32x2_t r, uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VRADDHN_HIGH_S16: // RADDHN2 Vd.16B,Vn.8H,Vm.8H int8x16_t vraddhn_high_s16(int8x8_t r, int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VRADDHN_HIGH_S32: // RADDHN2 Vd.8H,Vn.4S,Vm.4S int16x8_t vraddhn_high_s32(int16x4_t r, int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VRADDHN_HIGH_S64: // RADDHN2 Vd.4S,Vn.2D,Vm.2D int32x4_t vraddhn_high_s64(int32x2_t r, int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VRADDHN_HIGH_U16: // RADDHN2 Vd.16B,Vn.8H,Vm.8H uint8x16_t vraddhn_high_u16(uint8x8_t r, uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VRADDHN_HIGH_U32: // RADDHN2 Vd.8H,Vn.4S,Vm.4S uint16x8_t vraddhn_high_u32(uint16x4_t r, uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VRADDHN_HIGH_U64: // RADDHN2 Vd.4S,Vn.2D,Vm.2D uint32x4_t vraddhn_high_u64(uint32x2_t r, uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VRSUBHN_HIGH_S16: // RSUBHN2 Vd.16B,Vn.8H,Vm.8H int8x16_t vrsubhn_high_s16(int8x8_t r, int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VRSUBHN_HIGH_S32: // RSUBHN2 Vd.8H,Vn.4S,Vm.4S int16x8_t vrsubhn_high_s32(int16x4_t r, int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VRSUBHN_HIGH_S64: // RSUBHN2 Vd.4S,Vn.2D,Vm.2D int32x4_t vrsubhn_high_s64(int32x2_t r, int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VRSUBHN_HIGH_U16: // RSUBHN2 Vd.16B,Vn.8H,Vm.8H uint8x16_t vrsubhn_high_u16(uint8x8_t r, uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VRSUBHN_HIGH_U32: // RSUBHN2 Vd.8H,Vn.4S,Vm.4S uint16x8_t vrsubhn_high_u32(uint16x4_t r, uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VRSUBHN_HIGH_U64: // RSUBHN2 Vd.4S,Vn.2D,Vm.2D uint32x4_t vrsubhn_high_u64(uint32x2_t r, uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VSUBHN_HIGH_S16: // SUBHN2 Vd.16B,Vn.8H,Vm.8H int8x16_t vsubhn_high_s16(int8x8_t r, int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VSUBHN_HIGH_S32: // SUBHN2 Vd.8H,Vn.4S,Vm.4S int16x8_t vsubhn_high_s32(int16x4_t r, int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VSUBHN_HIGH_S64: // SUBHN2 Vd.4S,Vn.2D,Vm.2D int32x4_t vsubhn_high_s64(int32x2_t r, int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VSUBHN_HIGH_U16: // SUBHN2 Vd.16B,Vn.8H,Vm.8H uint8x16_t vsubhn_high_u16(uint8x8_t r, uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VSUBHN_HIGH_U32: // SUBHN2 Vd.8H,Vn.4S,Vm.4S uint16x8_t vsubhn_high_u32(uint16x4_t r, uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VSUBHN_HIGH_U64: // SUBHN2 Vd.4S,Vn.2D,Vm.2D uint32x4_t vsubhn_high_u64(uint32x2_t r, uint64x2_t a, uint64x2_t b)
+ return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(16, false))};
+ case ARM64_INTRIN_VMUL_LANEQ_S16: // MUL Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vmul_laneq_s16(int16x4_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANEQ_S32: // MUL Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vmul_laneq_s32(int32x2_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANEQ_U16: // MUL Vd.4H,Vn.4H,Vm.H[lane] uint16x4_t vmul_laneq_u16(uint16x4_t a, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANEQ_U32: // MUL Vd.2S,Vn.2S,Vm.S[lane] uint32x2_t vmul_laneq_u32(uint32x2_t a, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULL_LANEQ_S16: // SMULL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vmull_laneq_s16(int16x4_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULL_LANEQ_S32: // SMULL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vmull_laneq_s32(int32x2_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULL_LANEQ_U16: // UMULL Vd.4S,Vn.4H,Vm.H[lane] uint32x4_t vmull_laneq_u16(uint16x4_t a, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULL_LANEQ_U32: // UMULL Vd.2D,Vn.2S,Vm.S[lane] uint64x2_t vmull_laneq_u32(uint32x2_t a, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULH_LANEQ_S16: // SQDMULH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqdmulh_laneq_s16(int16x4_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMULH_LANEQ_S32: // SQDMULH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqdmulh_laneq_s32(int32x2_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_LANEQ_S16: // SQDMULL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vqdmull_laneq_s16(int16x4_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_LANEQ_S32: // SQDMULL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vqdmull_laneq_s32(int32x2_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULH_LANEQ_S16: // SQRDMULH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqrdmulh_laneq_s16(int16x4_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULH_LANEQ_S32: // SQRDMULH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqrdmulh_laneq_s32(int32x2_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRSHRN_HIGH_N_S16: // SQRSHRN2 Vd.16B,Vn.8H,#n int8x16_t vqrshrn_high_n_s16(int8x8_t r, int16x8_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_HIGH_N_S32: // SQRSHRN2 Vd.8H,Vn.4S,#n int16x8_t vqrshrn_high_n_s32(int16x4_t r, int32x4_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_HIGH_N_S64: // SQRSHRN2 Vd.4S,Vn.2D,#n int32x4_t vqrshrn_high_n_s64(int32x2_t r, int64x2_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_HIGH_N_U16: // UQRSHRN2 Vd.16B,Vn.8H,#n uint8x16_t vqrshrn_high_n_u16(uint8x8_t r, uint16x8_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_HIGH_N_U32: // UQRSHRN2 Vd.8H,Vn.4S,#n uint16x8_t vqrshrn_high_n_u32(uint16x4_t r, uint32x4_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_HIGH_N_U64: // UQRSHRN2 Vd.4S,Vn.2D,#n uint32x4_t vqrshrn_high_n_u64(uint32x2_t r, uint64x2_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUN_HIGH_N_S16: // SQRSHRUN2 Vd.16B,Vn.8H,#n uint8x16_t vqrshrun_high_n_s16(uint8x8_t r, int16x8_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUN_HIGH_N_S32: // SQRSHRUN2 Vd.8H,Vn.4S,#n uint16x8_t vqrshrun_high_n_s32(uint16x4_t r, int32x4_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUN_HIGH_N_S64: // SQRSHRUN2 Vd.4S,Vn.2D,#n uint32x4_t vqrshrun_high_n_s64(uint32x2_t r, int64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_HIGH_N_S16: // SQSHRN2 Vd.16B,Vn.8H,#n int8x16_t vqshrn_high_n_s16(int8x8_t r, int16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_HIGH_N_S32: // SQSHRN2 Vd.8H,Vn.4S,#n int16x8_t vqshrn_high_n_s32(int16x4_t r, int32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_HIGH_N_S64: // SQSHRN2 Vd.4S,Vn.2D,#n int32x4_t vqshrn_high_n_s64(int32x2_t r, int64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_HIGH_N_U16: // UQSHRN2 Vd.16B,Vn.8H,#n uint8x16_t vqshrn_high_n_u16(uint8x8_t r, uint16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_HIGH_N_U32: // UQSHRN2 Vd.8H,Vn.4S,#n uint16x8_t vqshrn_high_n_u32(uint16x4_t r, uint32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_HIGH_N_U64: // UQSHRN2 Vd.4S,Vn.2D,#n uint32x4_t vqshrn_high_n_u64(uint32x2_t r, uint64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHRUN_HIGH_N_S16: // SQSHRUN2 Vd.16B,Vn.8H,#n uint8x16_t vqshrun_high_n_s16(uint8x8_t r, int16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHRUN_HIGH_N_S32: // SQSHRUN2 Vd.8H,Vn.4S,#n uint16x8_t vqshrun_high_n_s32(uint16x4_t r, int32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHRUN_HIGH_N_S64: // SQSHRUN2 Vd.4S,Vn.2D,#n uint32x4_t vqshrun_high_n_s64(uint32x2_t r, int64x2_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_HIGH_N_S16: // RSHRN2 Vd.16B,Vn.8H,#n int8x16_t vrshrn_high_n_s16(int8x8_t r, int16x8_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_HIGH_N_S32: // RSHRN2 Vd.8H,Vn.4S,#n int16x8_t vrshrn_high_n_s32(int16x4_t r, int32x4_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_HIGH_N_S64: // RSHRN2 Vd.4S,Vn.2D,#n int32x4_t vrshrn_high_n_s64(int32x2_t r, int64x2_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_HIGH_N_U16: // RSHRN2 Vd.16B,Vn.8H,#n uint8x16_t vrshrn_high_n_u16(uint8x8_t r, uint16x8_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_HIGH_N_U32: // RSHRN2 Vd.8H,Vn.4S,#n uint16x8_t vrshrn_high_n_u32(uint16x4_t r, uint32x4_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_HIGH_N_U64: // RSHRN2 Vd.4S,Vn.2D,#n uint32x4_t vrshrn_high_n_u64(uint32x2_t r, uint64x2_t a, const int n)
+ case ARM64_INTRIN_VSETQ_LANE_P64: // MOV Vd.D[lane],Rn poly64x2_t vsetq_lane_p64(poly64_t a, poly64x2_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_S64: // MOV Vd.D[lane],Rn int64x2_t vsetq_lane_s64(int64_t a, int64x2_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_U64: // MOV Vd.D[lane],Rn uint64x2_t vsetq_lane_u64(uint64_t a, uint64x2_t v, const int lane)
+ case ARM64_INTRIN_VSHRN_HIGH_N_S16: // SHRN2 Vd.16B,Vn.8H,#n int8x16_t vshrn_high_n_s16(int8x8_t r, int16x8_t a, const int n)
+ case ARM64_INTRIN_VSHRN_HIGH_N_S32: // SHRN2 Vd.8H,Vn.4S,#n int16x8_t vshrn_high_n_s32(int16x4_t r, int32x4_t a, const int n)
+ case ARM64_INTRIN_VSHRN_HIGH_N_S64: // SHRN2 Vd.4S,Vn.2D,#n int32x4_t vshrn_high_n_s64(int32x2_t r, int64x2_t a, const int n)
+ case ARM64_INTRIN_VSHRN_HIGH_N_U16: // SHRN2 Vd.16B,Vn.8H,#n uint8x16_t vshrn_high_n_u16(uint8x8_t r, uint16x8_t a, const int n)
+ case ARM64_INTRIN_VSHRN_HIGH_N_U32: // SHRN2 Vd.8H,Vn.4S,#n uint16x8_t vshrn_high_n_u32(uint16x4_t r, uint32x4_t a, const int n)
+ case ARM64_INTRIN_VSHRN_HIGH_N_U64: // SHRN2 Vd.4S,Vn.2D,#n uint32x4_t vshrn_high_n_u64(uint32x2_t r, uint64x2_t a, const int n)
+ return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VMUL_N_S16: // MUL Vd.4H,Vn.4H,Vm.H[0] int16x4_t vmul_n_s16(int16x4_t a, int16_t b)
+ case ARM64_INTRIN_VMUL_N_U16: // MUL Vd.4H,Vn.4H,Vm.H[0] uint16x4_t vmul_n_u16(uint16x4_t a, uint16_t b)
+ case ARM64_INTRIN_VMULL_N_S16: // SMULL Vd.4S,Vn.4H,Vm.H[0] int32x4_t vmull_n_s16(int16x4_t a, int16_t b)
+ case ARM64_INTRIN_VMULL_N_U16: // UMULL Vd.4S,Vn.4H,Vm.H[0] uint32x4_t vmull_n_u16(uint16x4_t a, uint16_t b)
+ case ARM64_INTRIN_VQDMULH_N_S16: // SQDMULH Vd.4H,Vn.4H,Vm.H[0] int16x4_t vqdmulh_n_s16(int16x4_t a, int16_t b)
+ case ARM64_INTRIN_VQDMULL_N_S16: // SQDMULL Vd.4S,Vn.4H,Vm.H[0] int32x4_t vqdmull_n_s16(int16x4_t a, int16_t b)
+ case ARM64_INTRIN_VQRDMULH_N_S16: // SQRDMULH Vd.4H,Vn.4H,Vm.H[0] int16x4_t vqrdmulh_n_s16(int16x4_t a, int16_t b)
+ return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(2, false))};
+ case ARM64_INTRIN_VCVT_N_F16_S16: // SCVTF Vd.4H,Vn.4H,#n float16x4_t vcvt_n_f16_s16(int16x4_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_F16_U16: // UCVTF Vd.4H,Vn.4H,#n float16x4_t vcvt_n_f16_u16(uint16x4_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_F32_S32: // SCVTF Vd.2S,Vn.2S,#n float32x2_t vcvt_n_f32_s32(int32x2_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_F32_U32: // UCVTF Vd.2S,Vn.2S,#n float32x2_t vcvt_n_f32_u32(uint32x2_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_F64_S64: // SCVTF Dd,Dn,#n float64x1_t vcvt_n_f64_s64(int64x1_t a, const int n)
+ // case ARM64_INTRIN_VCVT_N_F64_S64: // SCVTF Xd,Dn,#n float64x1_t vcvt_n_f64_s64(int64x1_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_F64_U64: // UCVTF Dd,Dn,#n float64x1_t vcvt_n_f64_u64(uint64x1_t a, const int n)
+ // case ARM64_INTRIN_VCVT_N_F64_U64: // UCVTF Xd,Dn,#n float64x1_t vcvt_n_f64_u64(uint64x1_t a, const int n)
+ case ARM64_INTRIN_VCVTD_N_F64_S64: // SCVTF Dd,Dn,#n float64_t vcvtd_n_f64_s64(int64_t a, const int n)
+ // case ARM64_INTRIN_VCVTD_N_F64_S64: // SCVTF Xd,Dn,#n float64_t vcvtd_n_f64_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VCVTD_N_F64_U64: // UCVTF Dd,Dn,#n float64_t vcvtd_n_f64_u64(uint64_t a, const int n)
+ // case ARM64_INTRIN_VCVTD_N_F64_U64: // UCVTF Xd,Dn,#n float64_t vcvtd_n_f64_u64(uint64_t a, const int n)
+ case ARM64_INTRIN_VCVTH_N_F16_S64: // SCVTF Hd,Hn,#n float16_t vcvth_n_f16_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VCVTH_N_F16_U64: // UCVTF Hd,Hn,#n float16_t vcvth_n_f16_u64(uint64_t a, const int n)
+ case ARM64_INTRIN_VDUP_LANE_P16: // DUP Vd.4H,Vn.H[lane] poly16x4_t vdup_lane_p16(poly16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_P64: // DUP Dd,Vn.D[lane] poly64x1_t vdup_lane_p64(poly64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_P8: // DUP Vd.8B,Vn.B[lane] poly8x8_t vdup_lane_p8(poly8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_S16: // DUP Vd.4H,Vn.H[lane] int16x4_t vdup_lane_s16(int16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_S32: // DUP Vd.2S,Vn.S[lane] int32x2_t vdup_lane_s32(int32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_S64: // DUP Dd,Vn.D[lane] int64x1_t vdup_lane_s64(int64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_S8: // DUP Vd.8B,Vn.B[lane] int8x8_t vdup_lane_s8(int8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_U16: // DUP Vd.4H,Vn.H[lane] uint16x4_t vdup_lane_u16(uint16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_U32: // DUP Vd.2S,Vn.S[lane] uint32x2_t vdup_lane_u32(uint32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_U64: // DUP Dd,Vn.D[lane] uint64x1_t vdup_lane_u64(uint64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_U8: // DUP Vd.8B,Vn.B[lane] uint8x8_t vdup_lane_u8(uint8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPB_LANE_P8: // DUP Bd,Vn.B[lane] poly8_t vdupb_lane_p8(poly8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPB_LANE_S8: // DUP Bd,Vn.B[lane] int8_t vdupb_lane_s8(int8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPB_LANE_U8: // DUP Bd,Vn.B[lane] uint8_t vdupb_lane_u8(uint8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPD_LANE_S64: // DUP Dd,Vn.D[lane] int64_t vdupd_lane_s64(int64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUPD_LANE_U64: // DUP Dd,Vn.D[lane] uint64_t vdupd_lane_u64(uint64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANE_P16: // DUP Hd,Vn.H[lane] poly16_t vduph_lane_p16(poly16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANE_S16: // DUP Hd,Vn.H[lane] int16_t vduph_lane_s16(int16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANE_U16: // DUP Hd,Vn.H[lane] uint16_t vduph_lane_u16(uint16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_P16: // DUP Vd.8H,Vn.H[lane] poly16x8_t vdupq_lane_p16(poly16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_P64: // DUP Vd.2D,Vn.D[lane] poly64x2_t vdupq_lane_p64(poly64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_P8: // DUP Vd.16B,Vn.B[lane] poly8x16_t vdupq_lane_p8(poly8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_S16: // DUP Vd.8H,Vn.H[lane] int16x8_t vdupq_lane_s16(int16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_S32: // DUP Vd.4S,Vn.S[lane] int32x4_t vdupq_lane_s32(int32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_S64: // DUP Vd.2D,Vn.D[lane] int64x2_t vdupq_lane_s64(int64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_S8: // DUP Vd.16B,Vn.B[lane] int8x16_t vdupq_lane_s8(int8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_U16: // DUP Vd.8H,Vn.H[lane] uint16x8_t vdupq_lane_u16(uint16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_U32: // DUP Vd.4S,Vn.S[lane] uint32x4_t vdupq_lane_u32(uint32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_U64: // DUP Vd.2D,Vn.D[lane] uint64x2_t vdupq_lane_u64(uint64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_U8: // DUP Vd.16B,Vn.B[lane] uint8x16_t vdupq_lane_u8(uint8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPS_LANE_S32: // DUP Sd,Vn.S[lane] int32_t vdups_lane_s32(int32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPS_LANE_U32: // DUP Sd,Vn.S[lane] uint32_t vdups_lane_u32(uint32x2_t vec, const int lane)
+ case ARM64_INTRIN_VGET_LANE_P16: // UMOV Rd,Vn.H[lane] poly16_t vget_lane_p16(poly16x4_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_P64: // UMOV Rd,Vn.D[lane] poly64_t vget_lane_p64(poly64x1_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_P8: // UMOV Rd,Vn.B[lane] poly8_t vget_lane_p8(poly8x8_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_S16: // SMOV Rd,Vn.H[lane] int16_t vget_lane_s16(int16x4_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_S32: // SMOV Rd,Vn.S[lane] int32_t vget_lane_s32(int32x2_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_S64: // UMOV Rd,Vn.D[lane] int64_t vget_lane_s64(int64x1_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_S8: // SMOV Rd,Vn.B[lane] int8_t vget_lane_s8(int8x8_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_U16: // UMOV Rd,Vn.H[lane] uint16_t vget_lane_u16(uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_U32: // UMOV Rd,Vn.S[lane] uint32_t vget_lane_u32(uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_U64: // UMOV Rd,Vn.D[lane] uint64_t vget_lane_u64(uint64x1_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_U8: // UMOV Rd,Vn.B[lane] uint8_t vget_lane_u8(uint8x8_t v, const int lane)
+ case ARM64_INTRIN_VMUL_N_S32: // MUL Vd.2S,Vn.2S,Vm.S[0] int32x2_t vmul_n_s32(int32x2_t a, int32_t b)
+ case ARM64_INTRIN_VMUL_N_U32: // MUL Vd.2S,Vn.2S,Vm.S[0] uint32x2_t vmul_n_u32(uint32x2_t a, uint32_t b)
+ case ARM64_INTRIN_VMULL_N_S32: // SMULL Vd.2D,Vn.2S,Vm.S[0] int64x2_t vmull_n_s32(int32x2_t a, int32_t b)
+ case ARM64_INTRIN_VMULL_N_U32: // UMULL Vd.2D,Vn.2S,Vm.S[0] uint64x2_t vmull_n_u32(uint32x2_t a, uint32_t b)
+ case ARM64_INTRIN_VQDMULH_N_S32: // SQDMULH Vd.2S,Vn.2S,Vm.S[0] int32x2_t vqdmulh_n_s32(int32x2_t a, int32_t b)
+ case ARM64_INTRIN_VQDMULL_N_S32: // SQDMULL Vd.2D,Vn.2S,Vm.S[0] int64x2_t vqdmull_n_s32(int32x2_t a, int32_t b)
+ case ARM64_INTRIN_VQRDMULH_N_S32: // SQRDMULH Vd.2S,Vn.2S,Vm.S[0] int32x2_t vqrdmulh_n_s32(int32x2_t a, int32_t b)
+ case ARM64_INTRIN_VQRSHRND_N_S64: // SQRSHRN Sd,Dn,#n int32_t vqrshrnd_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VQRSHRND_N_U64: // UQRSHRN Sd,Dn,#n uint32_t vqrshrnd_n_u64(uint64_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUND_N_S64: // SQRSHRUN Sd,Dn,#n uint32_t vqrshrund_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_S16: // SQSHL Vd.4H,Vn.4H,#n int16x4_t vqshl_n_s16(int16x4_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_S32: // SQSHL Vd.2S,Vn.2S,#n int32x2_t vqshl_n_s32(int32x2_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_S64: // SQSHL Dd,Dn,#n int64x1_t vqshl_n_s64(int64x1_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_S8: // SQSHL Vd.8B,Vn.8B,#n int8x8_t vqshl_n_s8(int8x8_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_U16: // UQSHL Vd.4H,Vn.4H,#n uint16x4_t vqshl_n_u16(uint16x4_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_U32: // UQSHL Vd.2S,Vn.2S,#n uint32x2_t vqshl_n_u32(uint32x2_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_U64: // UQSHL Dd,Dn,#n uint64x1_t vqshl_n_u64(uint64x1_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_U8: // UQSHL Vd.8B,Vn.8B,#n uint8x8_t vqshl_n_u8(uint8x8_t a, const int n)
+ case ARM64_INTRIN_VQSHLD_N_S64: // SQSHL Dd,Dn,#n int64_t vqshld_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VQSHLD_N_U64: // UQSHL Dd,Dn,#n uint64_t vqshld_n_u64(uint64_t a, const int n)
+ case ARM64_INTRIN_VQSHLU_N_S16: // SQSHLU Vd.4H,Vn.4H,#n uint16x4_t vqshlu_n_s16(int16x4_t a, const int n)
+ case ARM64_INTRIN_VQSHLU_N_S32: // SQSHLU Vd.2S,Vn.2S,#n uint32x2_t vqshlu_n_s32(int32x2_t a, const int n)
+ case ARM64_INTRIN_VQSHLU_N_S64: // SQSHLU Dd,Dn,#n uint64x1_t vqshlu_n_s64(int64x1_t a, const int n)
+ case ARM64_INTRIN_VQSHLU_N_S8: // SQSHLU Vd.8B,Vn.8B,#n uint8x8_t vqshlu_n_s8(int8x8_t a, const int n)
+ case ARM64_INTRIN_VQSHLUD_N_S64: // SQSHLU Dd,Dn,#n uint64_t vqshlud_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VQSHRND_N_S64: // SQSHRN Sd,Dn,#n int32_t vqshrnd_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VQSHRND_N_U64: // UQSHRN Sd,Dn,#n uint32_t vqshrnd_n_u64(uint64_t a, const int n)
+ case ARM64_INTRIN_VQSHRUND_N_S64: // SQSHRUN Sd,Dn,#n uint32_t vqshrund_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VRSHR_N_S16: // SRSHR Vd.4H,Vn.4H,#n int16x4_t vrshr_n_s16(int16x4_t a, const int n)
+ case ARM64_INTRIN_VRSHR_N_S32: // SRSHR Vd.2S,Vn.2S,#n int32x2_t vrshr_n_s32(int32x2_t a, const int n)
+ case ARM64_INTRIN_VRSHR_N_S64: // SRSHR Dd,Dn,#n int64x1_t vrshr_n_s64(int64x1_t a, const int n)
+ case ARM64_INTRIN_VRSHR_N_S8: // SRSHR Vd.8B,Vn.8B,#n int8x8_t vrshr_n_s8(int8x8_t a, const int n)
+ case ARM64_INTRIN_VRSHR_N_U16: // URSHR Vd.4H,Vn.4H,#n uint16x4_t vrshr_n_u16(uint16x4_t a, const int n)
+ case ARM64_INTRIN_VRSHR_N_U32: // URSHR Vd.2S,Vn.2S,#n uint32x2_t vrshr_n_u32(uint32x2_t a, const int n)
+ case ARM64_INTRIN_VRSHR_N_U64: // URSHR Dd,Dn,#n uint64x1_t vrshr_n_u64(uint64x1_t a, const int n)
+ case ARM64_INTRIN_VRSHR_N_U8: // URSHR Vd.8B,Vn.8B,#n uint8x8_t vrshr_n_u8(uint8x8_t a, const int n)
+ case ARM64_INTRIN_VRSHRD_N_S64: // SRSHR Dd,Dn,#n int64_t vrshrd_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VRSHRD_N_U64: // URSHR Dd,Dn,#n uint64_t vrshrd_n_u64(uint64_t a, const int n)
+ case ARM64_INTRIN_VSHL_N_S16: // SHL Vd.4H,Vn.4H,#n int16x4_t vshl_n_s16(int16x4_t a, const int n)
+ case ARM64_INTRIN_VSHL_N_S32: // SHL Vd.2S,Vn.2S,#n int32x2_t vshl_n_s32(int32x2_t a, const int n)
+ case ARM64_INTRIN_VSHL_N_S64: // SHL Dd,Dn,#n int64x1_t vshl_n_s64(int64x1_t a, const int n)
+ case ARM64_INTRIN_VSHL_N_S8: // SHL Vd.8B,Vn.8B,#n int8x8_t vshl_n_s8(int8x8_t a, const int n)
+ case ARM64_INTRIN_VSHL_N_U16: // SHL Vd.4H,Vn.4H,#n uint16x4_t vshl_n_u16(uint16x4_t a, const int n)
+ case ARM64_INTRIN_VSHL_N_U32: // SHL Vd.2S,Vn.2S,#n uint32x2_t vshl_n_u32(uint32x2_t a, const int n)
+ case ARM64_INTRIN_VSHL_N_U64: // SHL Dd,Dn,#n uint64x1_t vshl_n_u64(uint64x1_t a, const int n)
+ case ARM64_INTRIN_VSHL_N_U8: // SHL Vd.8B,Vn.8B,#n uint8x8_t vshl_n_u8(uint8x8_t a, const int n)
+ case ARM64_INTRIN_VSHLD_N_S64: // SHL Dd,Dn,#n int64_t vshld_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VSHLD_N_U64: // SHL Dd,Dn,#n uint64_t vshld_n_u64(uint64_t a, const int n)
+ case ARM64_INTRIN_VSHLL_N_S16: // SHLL Vd.4S,Vn.4H,#n int32x4_t vshll_n_s16(int16x4_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_N_S16: // SSHLL Vd.4S,Vn.4H,#n int32x4_t vshll_n_s16(int16x4_t a, const int n)
+ case ARM64_INTRIN_VSHLL_N_S32: // SHLL Vd.2D,Vn.2S,#n int64x2_t vshll_n_s32(int32x2_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_N_S32: // SSHLL Vd.2D,Vn.2S,#n int64x2_t vshll_n_s32(int32x2_t a, const int n)
+ case ARM64_INTRIN_VSHLL_N_S8: // SHLL Vd.8H,Vn.8B,#n int16x8_t vshll_n_s8(int8x8_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_N_S8: // SSHLL Vd.8H,Vn.8B,#n int16x8_t vshll_n_s8(int8x8_t a, const int n)
+ case ARM64_INTRIN_VSHLL_N_U16: // SHLL Vd.4S,Vn.4H,#n uint32x4_t vshll_n_u16(uint16x4_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_N_U16: // USHLL Vd.4S,Vn.4H,#n uint32x4_t vshll_n_u16(uint16x4_t a, const int n)
+ case ARM64_INTRIN_VSHLL_N_U32: // SHLL Vd.2D,Vn.2S,#n uint64x2_t vshll_n_u32(uint32x2_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_N_U32: // USHLL Vd.2D,Vn.2S,#n uint64x2_t vshll_n_u32(uint32x2_t a, const int n)
+ case ARM64_INTRIN_VSHLL_N_U8: // SHLL Vd.8H,Vn.8B,#n uint16x8_t vshll_n_u8(uint8x8_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_N_U8: // USHLL Vd.8H,Vn.8B,#n uint16x8_t vshll_n_u8(uint8x8_t a, const int n)
+ case ARM64_INTRIN_VSHR_N_S16: // SSHR Vd.4H,Vn.4H,#n int16x4_t vshr_n_s16(int16x4_t a, const int n)
+ case ARM64_INTRIN_VSHR_N_S32: // SSHR Vd.2S,Vn.2S,#n int32x2_t vshr_n_s32(int32x2_t a, const int n)
+ case ARM64_INTRIN_VSHR_N_S64: // SSHR Dd,Dn,#n int64x1_t vshr_n_s64(int64x1_t a, const int n)
+ case ARM64_INTRIN_VSHR_N_S8: // SSHR Vd.8B,Vn.8B,#n int8x8_t vshr_n_s8(int8x8_t a, const int n)
+ case ARM64_INTRIN_VSHR_N_U16: // USHR Vd.4H,Vn.4H,#n uint16x4_t vshr_n_u16(uint16x4_t a, const int n)
+ case ARM64_INTRIN_VSHR_N_U32: // USHR Vd.2S,Vn.2S,#n uint32x2_t vshr_n_u32(uint32x2_t a, const int n)
+ case ARM64_INTRIN_VSHR_N_U64: // USHR Dd,Dn,#n uint64x1_t vshr_n_u64(uint64x1_t a, const int n)
+ case ARM64_INTRIN_VSHR_N_U8: // USHR Vd.8B,Vn.8B,#n uint8x8_t vshr_n_u8(uint8x8_t a, const int n)
+ case ARM64_INTRIN_VSHRD_N_S64: // SSHR Dd,Dn,#n int64_t vshrd_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VSHRD_N_U64: // USHR Dd,Dn,#n uint64_t vshrd_n_u64(uint64_t a, const int n)
+ return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VCOPY_LANEQ_P16: // INS Vd.H[lane1],Vn.H[lane2] poly16x4_t vcopy_laneq_p16(poly16x4_t a, const int lane1, poly16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_P64: // DUP Dd,Vn.D[lane2] poly64x1_t vcopy_laneq_p64(poly64x1_t a, const int lane1, poly64x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_P8: // INS Vd.B[lane1],Vn.B[lane2] poly8x8_t vcopy_laneq_p8(poly8x8_t a, const int lane1, poly8x16_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_S16: // INS Vd.H[lane1],Vn.H[lane2] int16x4_t vcopy_laneq_s16(int16x4_t a, const int lane1, int16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_S32: // INS Vd.S[lane1],Vn.S[lane2] int32x2_t vcopy_laneq_s32(int32x2_t a, const int lane1, int32x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_S64: // DUP Dd,Vn.D[lane2] int64x1_t vcopy_laneq_s64(int64x1_t a, const int lane1, int64x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_S8: // INS Vd.B[lane1],Vn.B[lane2] int8x8_t vcopy_laneq_s8(int8x8_t a, const int lane1, int8x16_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_U16: // INS Vd.H[lane1],Vn.H[lane2] uint16x4_t vcopy_laneq_u16(uint16x4_t a, const int lane1, uint16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_U32: // INS Vd.S[lane1],Vn.S[lane2] uint32x2_t vcopy_laneq_u32(uint32x2_t a, const int lane1, uint32x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_U64: // DUP Dd,Vn.D[lane2] uint64x1_t vcopy_laneq_u64(uint64x1_t a, const int lane1, uint64x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_U8: // INS Vd.B[lane1],Vn.B[lane2] uint8x8_t vcopy_laneq_u8(uint8x8_t a, const int lane1, uint8x16_t b, const int lane2)
+ case ARM64_INTRIN_VQDMLALS_LANEQ_S32: // SQDMLAL Dd,Sn,Vm.S[lane] int64_t vqdmlals_laneq_s32(int64_t a, int32_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSLS_LANEQ_S32: // SQDMLSL Dd,Sn,Vm.S[lane] int64_t vqdmlsls_laneq_s32(int64_t a, int32_t b, int32x4_t v, const int lane)
+ return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VQDMLALS_S32: // SQDMLAL Dd,Sn,Sm int64_t vqdmlals_s32(int64_t a, int32_t b, int32_t c)
+ case ARM64_INTRIN_VQDMLSLS_S32: // SQDMLSL Dd,Sn,Sm int64_t vqdmlsls_s32(int64_t a, int32_t b, int32_t c)
+ return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VCOPY_LANE_P16: // INS Vd.H[lane1],Vn.H[lane2] poly16x4_t vcopy_lane_p16(poly16x4_t a, const int lane1, poly16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_P64: // DUP Dd,Vn.D[lane2] poly64x1_t vcopy_lane_p64(poly64x1_t a, const int lane1, poly64x1_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_P8: // INS Vd.B[lane1],Vn.B[lane2] poly8x8_t vcopy_lane_p8(poly8x8_t a, const int lane1, poly8x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_S16: // INS Vd.H[lane1],Vn.H[lane2] int16x4_t vcopy_lane_s16(int16x4_t a, const int lane1, int16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_S32: // INS Vd.S[lane1],Vn.S[lane2] int32x2_t vcopy_lane_s32(int32x2_t a, const int lane1, int32x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_S64: // DUP Dd,Vn.D[lane2] int64x1_t vcopy_lane_s64(int64x1_t a, const int lane1, int64x1_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_S8: // INS Vd.B[lane1],Vn.B[lane2] int8x8_t vcopy_lane_s8(int8x8_t a, const int lane1, int8x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_U16: // INS Vd.H[lane1],Vn.H[lane2] uint16x4_t vcopy_lane_u16(uint16x4_t a, const int lane1, uint16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_U32: // INS Vd.S[lane1],Vn.S[lane2] uint32x2_t vcopy_lane_u32(uint32x2_t a, const int lane1, uint32x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_U64: // DUP Dd,Vn.D[lane2] uint64x1_t vcopy_lane_u64(uint64x1_t a, const int lane1, uint64x1_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_U8: // INS Vd.B[lane1],Vn.B[lane2] uint8x8_t vcopy_lane_u8(uint8x8_t a, const int lane1, uint8x8_t b, const int lane2)
+ case ARM64_INTRIN_VQDMLALS_LANE_S32: // SQDMLAL Dd,Sn,Vm.S[lane] int64_t vqdmlals_lane_s32(int64_t a, int32_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSLS_LANE_S32: // SQDMLSL Dd,Sn,Vm.S[lane] int64_t vqdmlsls_lane_s32(int64_t a, int32_t b, int32x2_t v, const int lane)
+ return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VABD_S16: // SABD Vd.4H,Vn.4H,Vm.4H int16x4_t vabd_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VABD_S32: // SABD Vd.2S,Vn.2S,Vm.2S int32x2_t vabd_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VABD_S8: // SABD Vd.8B,Vn.8B,Vm.8B int8x8_t vabd_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VABD_U16: // UABD Vd.4H,Vn.4H,Vm.4H uint16x4_t vabd_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VABD_U32: // UABD Vd.2S,Vn.2S,Vm.2S uint32x2_t vabd_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VABD_U8: // UABD Vd.8B,Vn.8B,Vm.8B uint8x8_t vabd_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VABDL_S16: // SABDL Vd.4S,Vn.4H,Vm.4H int32x4_t vabdl_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VABDL_S32: // SABDL Vd.2D,Vn.2S,Vm.2S int64x2_t vabdl_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VABDL_S8: // SABDL Vd.8H,Vn.8B,Vm.8B int16x8_t vabdl_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VABDL_U16: // UABDL Vd.4S,Vn.4H,Vm.4H uint32x4_t vabdl_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VABDL_U32: // UABDL Vd.2D,Vn.2S,Vm.2S uint64x2_t vabdl_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VABDL_U8: // UABDL Vd.8H,Vn.8B,Vm.8B uint16x8_t vabdl_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VADD_P16: // EOR Vd.8B,Vn.8B,Vm.8B poly16x4_t vadd_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VADD_P64: // EOR Vd.8B,Vn.8B,Vm.8B poly64x1_t vadd_p64(poly64x1_t a, poly64x1_t b)
+ case ARM64_INTRIN_VADD_P8: // EOR Vd.8B,Vn.8B,Vm.8B poly8x8_t vadd_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VADD_S16: // ADD Vd.4H,Vn.4H,Vm.4H int16x4_t vadd_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VADD_S32: // ADD Vd.2S,Vn.2S,Vm.2S int32x2_t vadd_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VADD_S64: // ADD Dd,Dn,Dm int64x1_t vadd_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VADD_S8: // ADD Vd.8B,Vn.8B,Vm.8B int8x8_t vadd_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VADD_U16: // ADD Vd.4H,Vn.4H,Vm.4H uint16x4_t vadd_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VADD_U32: // ADD Vd.2S,Vn.2S,Vm.2S uint32x2_t vadd_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VADD_U64: // ADD Dd,Dn,Dm uint64x1_t vadd_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VADD_U8: // ADD Vd.8B,Vn.8B,Vm.8B uint8x8_t vadd_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VADDD_S64: // ADD Dd,Dn,Dm int64_t vaddd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VADDD_U64: // ADD Dd,Dn,Dm uint64_t vaddd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VADDL_S16: // SADDL Vd.4S,Vn.4H,Vm.4H int32x4_t vaddl_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VADDL_S32: // SADDL Vd.2D,Vn.2S,Vm.2S int64x2_t vaddl_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VADDL_S8: // SADDL Vd.8H,Vn.8B,Vm.8B int16x8_t vaddl_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VADDL_U16: // UADDL Vd.4S,Vn.4H,Vm.4H uint32x4_t vaddl_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VADDL_U32: // UADDL Vd.2D,Vn.2S,Vm.2S uint64x2_t vaddl_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VADDL_U8: // UADDL Vd.8H,Vn.8B,Vm.8B uint16x8_t vaddl_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VAND_S16: // AND Vd.8B,Vn.8B,Vm.8B int16x4_t vand_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VAND_S32: // AND Vd.8B,Vn.8B,Vm.8B int32x2_t vand_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VAND_S8: // AND Vd.8B,Vn.8B,Vm.8B int8x8_t vand_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VAND_U16: // AND Vd.8B,Vn.8B,Vm.8B uint16x4_t vand_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VAND_U32: // AND Vd.8B,Vn.8B,Vm.8B uint32x2_t vand_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VAND_U64: // AND Vd.8B,Vn.8B,Vm.8B uint64x1_t vand_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VAND_U8: // AND Vd.8B,Vn.8B,Vm.8B uint8x8_t vand_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VBIC_S16: // BIC Vd.8B,Vn.8B,Vm.8B int16x4_t vbic_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VBIC_S32: // BIC Vd.8B,Vn.8B,Vm.8B int32x2_t vbic_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VBIC_S64: // BIC Vd.8B,Vn.8B,Vm.8B int64x1_t vbic_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VBIC_S8: // BIC Vd.8B,Vn.8B,Vm.8B int8x8_t vbic_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VBIC_U16: // BIC Vd.8B,Vn.8B,Vm.8B uint16x4_t vbic_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VBIC_U32: // BIC Vd.8B,Vn.8B,Vm.8B uint32x2_t vbic_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VBIC_U64: // BIC Vd.8B,Vn.8B,Vm.8B uint64x1_t vbic_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VBIC_U8: // BIC Vd.8B,Vn.8B,Vm.8B uint8x8_t vbic_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VCEQ_P64: // CMEQ Dd,Dn,Dm uint64x1_t vceq_p64(poly64x1_t a, poly64x1_t b)
+ case ARM64_INTRIN_VCEQ_P8: // CMEQ Vd.8B,Vn.8B,Vm.8B uint8x8_t vceq_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VCEQ_S16: // CMEQ Vd.4H,Vn.4H,Vm.4H uint16x4_t vceq_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VCEQ_S32: // CMEQ Vd.2S,Vn.2S,Vm.2S uint32x2_t vceq_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VCEQ_S64: // CMEQ Dd,Dn,Dm uint64x1_t vceq_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VCEQ_S8: // CMEQ Vd.8B,Vn.8B,Vm.8B uint8x8_t vceq_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VCEQ_U16: // CMEQ Vd.4H,Vn.4H,Vm.4H uint16x4_t vceq_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VCEQ_U32: // CMEQ Vd.2S,Vn.2S,Vm.2S uint32x2_t vceq_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VCEQ_U64: // CMEQ Dd,Dn,Dm uint64x1_t vceq_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VCEQ_U8: // CMEQ Vd.8B,Vn.8B,Vm.8B uint8x8_t vceq_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VCEQD_S64: // CMEQ Dd,Dn,Dm uint64_t vceqd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VCEQD_U64: // CMEQ Dd,Dn,Dm uint64_t vceqd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VCGE_S16: // CMGE Vd.4H,Vm.4H,Vn.4H uint16x4_t vcge_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VCGE_S32: // CMGE Vd.2S,Vm.2S,Vn.2S uint32x2_t vcge_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VCGE_S64: // CMGE Dd,Dn,Dm uint64x1_t vcge_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VCGE_S8: // CMGE Vd.8B,Vm.8B,Vn.8B uint8x8_t vcge_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VCGE_U16: // CMHS Vd.4H,Vm.4H,Vn.4H uint16x4_t vcge_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VCGE_U32: // CMHS Vd.2S,Vm.2S,Vn.2S uint32x2_t vcge_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VCGE_U64: // CMHS Dd,Dn,Dm uint64x1_t vcge_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VCGE_U8: // CMHS Vd.8B,Vm.8B,Vn.8B uint8x8_t vcge_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VCGED_S64: // CMGE Dd,Dn,Dm uint64_t vcged_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VCGED_U64: // CMHS Dd,Dn,Dm uint64_t vcged_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VCGT_S16: // CMGT Vd.4H,Vn.4H,Vm.4H uint16x4_t vcgt_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VCGT_S32: // CMGT Vd.2S,Vn.2S,Vm.2S uint32x2_t vcgt_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VCGT_S64: // CMGT Dd,Dn,Dm uint64x1_t vcgt_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VCGT_S8: // CMGT Vd.8B,Vn.8B,Vm.8B uint8x8_t vcgt_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VCGT_U16: // CMHI Vd.4H,Vn.4H,Vm.4H uint16x4_t vcgt_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VCGT_U32: // CMHI Vd.2S,Vn.2S,Vm.2S uint32x2_t vcgt_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VCGT_U64: // CMHI Dd,Dn,Dm uint64x1_t vcgt_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VCGT_U8: // CMHI Vd.8B,Vn.8B,Vm.8B uint8x8_t vcgt_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VCGTD_S64: // CMGT Dd,Dn,Dm uint64_t vcgtd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VCGTD_U64: // CMHI Dd,Dn,Dm uint64_t vcgtd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VCLE_S16: // CMGE Vd.4H,Vm.4H,Vn.4H uint16x4_t vcle_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VCLE_S32: // CMGE Vd.2S,Vm.2S,Vn.2S uint32x2_t vcle_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VCLE_S64: // CMGE Dd,Dm,Dn uint64x1_t vcle_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VCLE_S8: // CMGE Vd.8B,Vm.8B,Vn.8B uint8x8_t vcle_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VCLE_U16: // CMHS Vd.4H,Vm.4H,Vn.4H uint16x4_t vcle_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VCLE_U32: // CMHS Vd.2S,Vm.2S,Vn.2S uint32x2_t vcle_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VCLE_U64: // CMHS Dd,Dm,Dn uint64x1_t vcle_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VCLE_U8: // CMHS Vd.8B,Vm.8B,Vn.8B uint8x8_t vcle_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VCLED_S64: // CMGE Dd,Dm,Dn uint64_t vcled_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VCLED_U64: // CMHS Dd,Dm,Dn uint64_t vcled_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VCLT_S16: // CMGT Vd.4H,Vm.4H,Vn.4H uint16x4_t vclt_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VCLT_S32: // CMGT Vd.2S,Vm.2S,Vn.2S uint32x2_t vclt_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VCLT_S64: // CMGT Dd,Dm,Dn uint64x1_t vclt_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VCLT_S8: // CMGT Vd.8B,Vm.8B,Vn.8B uint8x8_t vclt_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VCLT_U16: // CMHI Vd.4H,Vm.4H,Vn.4H uint16x4_t vclt_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VCLT_U32: // CMHI Vd.2S,Vm.2S,Vn.2S uint32x2_t vclt_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VCLT_U64: // CMHI Dd,Dm,Dn uint64x1_t vclt_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VCLT_U8: // CMHI Vd.8B,Vm.8B,Vn.8B uint8x8_t vclt_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VCLTD_S64: // CMGT Dd,Dm,Dn uint64_t vcltd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VCLTD_U64: // CMHI Dd,Dm,Dn uint64_t vcltd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VCOMBINE_P16: // INS Vd.D[1],Vm.D[0] poly16x8_t vcombine_p16(poly16x4_t low, poly16x4_t high)
+ case ARM64_INTRIN_VCOMBINE_P64: // INS Vd.D[1],Vm.D[0] poly64x2_t vcombine_p64(poly64x1_t low, poly64x1_t high)
+ case ARM64_INTRIN_VCOMBINE_P8: // INS Vd.D[1],Vm.D[0] poly8x16_t vcombine_p8(poly8x8_t low, poly8x8_t high)
+ case ARM64_INTRIN_VCOMBINE_S16: // INS Vd.D[1],Vm.D[0] int16x8_t vcombine_s16(int16x4_t low, int16x4_t high)
+ case ARM64_INTRIN_VCOMBINE_S32: // INS Vd.D[1],Vm.D[0] int32x4_t vcombine_s32(int32x2_t low, int32x2_t high)
+ case ARM64_INTRIN_VCOMBINE_S64: // INS Vd.D[1],Vm.D[0] int64x2_t vcombine_s64(int64x1_t low, int64x1_t high)
+ case ARM64_INTRIN_VCOMBINE_S8: // INS Vd.D[1],Vm.D[0] int8x16_t vcombine_s8(int8x8_t low, int8x8_t high)
+ case ARM64_INTRIN_VCOMBINE_U16: // INS Vd.D[1],Vm.D[0] uint16x8_t vcombine_u16(uint16x4_t low, uint16x4_t high)
+ case ARM64_INTRIN_VCOMBINE_U32: // INS Vd.D[1],Vm.D[0] uint32x4_t vcombine_u32(uint32x2_t low, uint32x2_t high)
+ case ARM64_INTRIN_VCOMBINE_U64: // INS Vd.D[1],Vm.D[0] uint64x2_t vcombine_u64(uint64x1_t low, uint64x1_t high)
+ case ARM64_INTRIN_VCOMBINE_U8: // INS Vd.D[1],Vm.D[0] uint8x16_t vcombine_u8(uint8x8_t low, uint8x8_t high)
+ case ARM64_INTRIN_VEOR_S16: // EOR Vd.8B,Vn.8B,Vm.8B int16x4_t veor_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VEOR_S32: // EOR Vd.8B,Vn.8B,Vm.8B int32x2_t veor_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VEOR_S64: // EOR Vd.8B,Vn.8B,Vm.8B int64x1_t veor_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VEOR_S8: // EOR Vd.8B,Vn.8B,Vm.8B int8x8_t veor_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VEOR_U16: // EOR Vd.8B,Vn.8B,Vm.8B uint16x4_t veor_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VEOR_U32: // EOR Vd.8B,Vn.8B,Vm.8B uint32x2_t veor_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VEOR_U64: // EOR Vd.8B,Vn.8B,Vm.8B uint64x1_t veor_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VEOR_U8: // EOR Vd.8B,Vn.8B,Vm.8B uint8x8_t veor_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VHADD_S16: // SHADD Vd.4H,Vn.4H,Vm.4H int16x4_t vhadd_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VHADD_S32: // SHADD Vd.2S,Vn.2S,Vm.2S int32x2_t vhadd_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VHADD_S8: // SHADD Vd.8B,Vn.8B,Vm.8B int8x8_t vhadd_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VHADD_U16: // UHADD Vd.4H,Vn.4H,Vm.4H uint16x4_t vhadd_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VHADD_U32: // UHADD Vd.2S,Vn.2S,Vm.2S uint32x2_t vhadd_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VHADD_U8: // UHADD Vd.8B,Vn.8B,Vm.8B uint8x8_t vhadd_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VHSUB_S16: // SHSUB Vd.4H,Vn.4H,Vm.4H int16x4_t vhsub_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VHSUB_S32: // SHSUB Vd.2S,Vn.2S,Vm.2S int32x2_t vhsub_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VHSUB_S8: // SHSUB Vd.8B,Vn.8B,Vm.8B int8x8_t vhsub_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VHSUB_U16: // UHSUB Vd.4H,Vn.4H,Vm.4H uint16x4_t vhsub_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VHSUB_U32: // UHSUB Vd.2S,Vn.2S,Vm.2S uint32x2_t vhsub_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VHSUB_U8: // UHSUB Vd.8B,Vn.8B,Vm.8B uint8x8_t vhsub_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VMAX_S16: // SMAX Vd.4H,Vn.4H,Vm.4H int16x4_t vmax_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VMAX_S32: // SMAX Vd.2S,Vn.2S,Vm.2S int32x2_t vmax_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VMAX_S8: // SMAX Vd.8B,Vn.8B,Vm.8B int8x8_t vmax_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VMAX_U16: // UMAX Vd.4H,Vn.4H,Vm.4H uint16x4_t vmax_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VMAX_U32: // UMAX Vd.2S,Vn.2S,Vm.2S uint32x2_t vmax_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VMAX_U8: // UMAX Vd.8B,Vn.8B,Vm.8B uint8x8_t vmax_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VMIN_S16: // SMIN Vd.4H,Vn.4H,Vm.4H int16x4_t vmin_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VMIN_S32: // SMIN Vd.2S,Vn.2S,Vm.2S int32x2_t vmin_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VMIN_S8: // SMIN Vd.8B,Vn.8B,Vm.8B int8x8_t vmin_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VMIN_U16: // UMIN Vd.4H,Vn.4H,Vm.4H uint16x4_t vmin_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VMIN_U32: // UMIN Vd.2S,Vn.2S,Vm.2S uint32x2_t vmin_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VMIN_U8: // UMIN Vd.8B,Vn.8B,Vm.8B uint8x8_t vmin_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VMUL_P8: // PMUL Vd.8B,Vn.8B,Vm.8B poly8x8_t vmul_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VMUL_S16: // MUL Vd.4H,Vn.4H,Vm.4H int16x4_t vmul_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VMUL_S32: // MUL Vd.2S,Vn.2S,Vm.2S int32x2_t vmul_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VMUL_S8: // MUL Vd.8B,Vn.8B,Vm.8B int8x8_t vmul_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VMUL_U16: // MUL Vd.4H,Vn.4H,Vm.4H uint16x4_t vmul_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VMUL_U32: // MUL Vd.2S,Vn.2S,Vm.2S uint32x2_t vmul_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VMUL_U8: // MUL Vd.8B,Vn.8B,Vm.8B uint8x8_t vmul_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VMULL_P64: // PMULL Vd.1Q,Vn.1D,Vm.1D poly128_t vmull_p64(poly64_t a, poly64_t b)
+ case ARM64_INTRIN_VMULL_P8: // PMULL Vd.8H,Vn.8B,Vm.8B poly16x8_t vmull_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VMULL_S16: // SMULL Vd.4S,Vn.4H,Vm.4H int32x4_t vmull_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VMULL_S32: // SMULL Vd.2D,Vn.2S,Vm.2S int64x2_t vmull_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VMULL_S8: // SMULL Vd.8H,Vn.8B,Vm.8B int16x8_t vmull_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VMULL_U16: // UMULL Vd.4S,Vn.4H,Vm.4H uint32x4_t vmull_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VMULL_U32: // UMULL Vd.2D,Vn.2S,Vm.2S uint64x2_t vmull_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VMULL_U8: // UMULL Vd.8H,Vn.8B,Vm.8B uint16x8_t vmull_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VORN_S16: // ORN Vd.8B,Vn.8B,Vm.8B int16x4_t vorn_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VORN_S32: // ORN Vd.8B,Vn.8B,Vm.8B int32x2_t vorn_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VORN_S64: // ORN Vd.8B,Vn.8B,Vm.8B int64x1_t vorn_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VORN_S8: // ORN Vd.8B,Vn.8B,Vm.8B int8x8_t vorn_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VORN_U16: // ORN Vd.8B,Vn.8B,Vm.8B uint16x4_t vorn_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VORN_U32: // ORN Vd.8B,Vn.8B,Vm.8B uint32x2_t vorn_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VORN_U64: // ORN Vd.8B,Vn.8B,Vm.8B uint64x1_t vorn_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VORN_U8: // ORN Vd.8B,Vn.8B,Vm.8B uint8x8_t vorn_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VORR_S16: // ORR Vd.8B,Vn.8B,Vm.8B int16x4_t vorr_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VORR_S32: // ORR Vd.8B,Vn.8B,Vm.8B int32x2_t vorr_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VORR_S64: // ORR Vd.8B,Vn.8B,Vm.8B int64x1_t vorr_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VORR_S8: // ORR Vd.8B,Vn.8B,Vm.8B int8x8_t vorr_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VORR_U16: // ORR Vd.8B,Vn.8B,Vm.8B uint16x4_t vorr_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VORR_U32: // ORR Vd.8B,Vn.8B,Vm.8B uint32x2_t vorr_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VORR_U64: // ORR Vd.8B,Vn.8B,Vm.8B uint64x1_t vorr_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VORR_U8: // ORR Vd.8B,Vn.8B,Vm.8B uint8x8_t vorr_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VPADAL_S16: // SADALP Vd.2S,Vn.4H int32x2_t vpadal_s16(int32x2_t a, int16x4_t b)
+ case ARM64_INTRIN_VPADAL_S32: // SADALP Vd.1D,Vn.2S int64x1_t vpadal_s32(int64x1_t a, int32x2_t b)
+ case ARM64_INTRIN_VPADAL_S8: // SADALP Vd.4H,Vn.8B int16x4_t vpadal_s8(int16x4_t a, int8x8_t b)
+ case ARM64_INTRIN_VPADAL_U16: // UADALP Vd.2S,Vn.4H uint32x2_t vpadal_u16(uint32x2_t a, uint16x4_t b)
+ case ARM64_INTRIN_VPADAL_U32: // UADALP Vd.1D,Vn.2S uint64x1_t vpadal_u32(uint64x1_t a, uint32x2_t b)
+ case ARM64_INTRIN_VPADAL_U8: // UADALP Vd.4H,Vn.8B uint16x4_t vpadal_u8(uint16x4_t a, uint8x8_t b)
+ case ARM64_INTRIN_VPADD_S16: // ADDP Vd.4H,Vn.4H,Vm.4H int16x4_t vpadd_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VPADD_S32: // ADDP Vd.2S,Vn.2S,Vm.2S int32x2_t vpadd_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VPADD_S8: // ADDP Vd.8B,Vn.8B,Vm.8B int8x8_t vpadd_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VPADD_U16: // ADDP Vd.4H,Vn.4H,Vm.4H uint16x4_t vpadd_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VPADD_U32: // ADDP Vd.2S,Vn.2S,Vm.2S uint32x2_t vpadd_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VPADD_U8: // ADDP Vd.8B,Vn.8B,Vm.8B uint8x8_t vpadd_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VPMAX_S16: // SMAXP Vd.4H,Vn.4H,Vm.4H int16x4_t vpmax_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VPMAX_S32: // SMAXP Vd.2S,Vn.2S,Vm.2S int32x2_t vpmax_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VPMAX_S8: // SMAXP Vd.8B,Vn.8B,Vm.8B int8x8_t vpmax_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VPMAX_U16: // UMAXP Vd.4H,Vn.4H,Vm.4H uint16x4_t vpmax_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VPMAX_U32: // UMAXP Vd.2S,Vn.2S,Vm.2S uint32x2_t vpmax_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VPMAX_U8: // UMAXP Vd.8B,Vn.8B,Vm.8B uint8x8_t vpmax_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VPMIN_S16: // SMINP Vd.4H,Vn.4H,Vm.4H int16x4_t vpmin_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VPMIN_S32: // SMINP Vd.2S,Vn.2S,Vm.2S int32x2_t vpmin_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VPMIN_S8: // SMINP Vd.8B,Vn.8B,Vm.8B int8x8_t vpmin_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VPMIN_U16: // UMINP Vd.4H,Vn.4H,Vm.4H uint16x4_t vpmin_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VPMIN_U32: // UMINP Vd.2S,Vn.2S,Vm.2S uint32x2_t vpmin_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VPMIN_U8: // UMINP Vd.8B,Vn.8B,Vm.8B uint8x8_t vpmin_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VQADD_S16: // SQADD Vd.4H,Vn.4H,Vm.4H int16x4_t vqadd_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQADD_S32: // SQADD Vd.2S,Vn.2S,Vm.2S int32x2_t vqadd_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQADD_S64: // SQADD Dd,Dn,Dm int64x1_t vqadd_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VQADD_S8: // SQADD Vd.8B,Vn.8B,Vm.8B int8x8_t vqadd_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VQADD_U16: // UQADD Vd.4H,Vn.4H,Vm.4H uint16x4_t vqadd_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VQADD_U32: // UQADD Vd.2S,Vn.2S,Vm.2S uint32x2_t vqadd_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VQADD_U64: // UQADD Dd,Dn,Dm uint64x1_t vqadd_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VQADD_U8: // UQADD Vd.8B,Vn.8B,Vm.8B uint8x8_t vqadd_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VQADDD_S64: // SQADD Dd,Dn,Dm int64_t vqaddd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VQADDD_U64: // UQADD Dd,Dn,Dm uint64_t vqaddd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VQDMULH_S16: // SQDMULH Vd.4H,Vn.4H,Vm.4H int16x4_t vqdmulh_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQDMULH_S32: // SQDMULH Vd.2S,Vn.2S,Vm.2S int32x2_t vqdmulh_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQDMULL_S16: // SQDMULL Vd.4S,Vn.4H,Vm.4H int32x4_t vqdmull_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQDMULL_S32: // SQDMULL Vd.2D,Vn.2S,Vm.2S int64x2_t vqdmull_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQRDMULH_S16: // SQRDMULH Vd.4H,Vn.4H,Vm.4H int16x4_t vqrdmulh_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQRDMULH_S32: // SQRDMULH Vd.2S,Vn.2S,Vm.2S int32x2_t vqrdmulh_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQRSHL_S16: // SQRSHL Vd.4H,Vn.4H,Vm.4H int16x4_t vqrshl_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQRSHL_S32: // SQRSHL Vd.2S,Vn.2S,Vm.2S int32x2_t vqrshl_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQRSHL_S64: // SQRSHL Dd,Dn,Dm int64x1_t vqrshl_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VQRSHL_S8: // SQRSHL Vd.8B,Vn.8B,Vm.8B int8x8_t vqrshl_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VQRSHL_U16: // UQRSHL Vd.4H,Vn.4H,Vm.4H uint16x4_t vqrshl_u16(uint16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQRSHL_U32: // UQRSHL Vd.2S,Vn.2S,Vm.2S uint32x2_t vqrshl_u32(uint32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQRSHL_U64: // UQRSHL Dd,Dn,Dm uint64x1_t vqrshl_u64(uint64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VQRSHL_U8: // UQRSHL Vd.8B,Vn.8B,Vm.8B uint8x8_t vqrshl_u8(uint8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VQRSHLD_S64: // SQRSHL Dd,Dn,Dm int64_t vqrshld_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VQRSHLD_U64: // UQRSHL Dd,Dn,Dm uint64_t vqrshld_u64(uint64_t a, int64_t b)
+ case ARM64_INTRIN_VQSHL_S16: // SQSHL Vd.4H,Vn.4H,Vm.4H int16x4_t vqshl_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQSHL_S32: // SQSHL Vd.2S,Vn.2S,Vm.2S int32x2_t vqshl_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQSHL_S64: // SQSHL Dd,Dn,Dm int64x1_t vqshl_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VQSHL_S8: // SQSHL Vd.8B,Vn.8B,Vm.8B int8x8_t vqshl_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VQSHL_U16: // UQSHL Vd.4H,Vn.4H,Vm.4H uint16x4_t vqshl_u16(uint16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQSHL_U32: // UQSHL Vd.2S,Vn.2S,Vm.2S uint32x2_t vqshl_u32(uint32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQSHL_U64: // UQSHL Dd,Dn,Dm uint64x1_t vqshl_u64(uint64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VQSHL_U8: // UQSHL Vd.8B,Vn.8B,Vm.8B uint8x8_t vqshl_u8(uint8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VQSHLD_S64: // SQSHL Dd,Dn,Dm int64_t vqshld_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VQSHLD_U64: // UQSHL Dd,Dn,Dm uint64_t vqshld_u64(uint64_t a, int64_t b)
+ case ARM64_INTRIN_VQSUB_S16: // SQSUB Vd.4H,Vn.4H,Vm.4H int16x4_t vqsub_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQSUB_S32: // SQSUB Vd.2S,Vn.2S,Vm.2S int32x2_t vqsub_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQSUB_S64: // SQSUB Dd,Dn,Dm int64x1_t vqsub_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VQSUB_S8: // SQSUB Vd.8B,Vn.8B,Vm.8B int8x8_t vqsub_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VQSUB_U16: // UQSUB Vd.4H,Vn.4H,Vm.4H uint16x4_t vqsub_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VQSUB_U32: // UQSUB Vd.2S,Vn.2S,Vm.2S uint32x2_t vqsub_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VQSUB_U64: // UQSUB Dd,Dn,Dm uint64x1_t vqsub_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VQSUB_U8: // UQSUB Vd.8B,Vn.8B,Vm.8B uint8x8_t vqsub_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VQSUBD_S64: // SQSUB Dd,Dn,Dm int64_t vqsubd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VQSUBD_U64: // UQSUB Dd,Dn,Dm uint64_t vqsubd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VRHADD_S16: // SRHADD Vd.4H,Vn.4H,Vm.4H int16x4_t vrhadd_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VRHADD_S32: // SRHADD Vd.2S,Vn.2S,Vm.2S int32x2_t vrhadd_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VRHADD_S8: // SRHADD Vd.8B,Vn.8B,Vm.8B int8x8_t vrhadd_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VRHADD_U16: // URHADD Vd.4H,Vn.4H,Vm.4H uint16x4_t vrhadd_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VRHADD_U32: // URHADD Vd.2S,Vn.2S,Vm.2S uint32x2_t vrhadd_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VRHADD_U8: // URHADD Vd.8B,Vn.8B,Vm.8B uint8x8_t vrhadd_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VRSHL_S16: // SRSHL Vd.4H,Vn.4H,Vm.4H int16x4_t vrshl_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VRSHL_S32: // SRSHL Vd.2S,Vn.2S,Vm.2S int32x2_t vrshl_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VRSHL_S64: // SRSHL Dd,Dn,Dm int64x1_t vrshl_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VRSHL_S8: // SRSHL Vd.8B,Vn.8B,Vm.8B int8x8_t vrshl_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VRSHL_U16: // URSHL Vd.4H,Vn.4H,Vm.4H uint16x4_t vrshl_u16(uint16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VRSHL_U32: // URSHL Vd.2S,Vn.2S,Vm.2S uint32x2_t vrshl_u32(uint32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VRSHL_U64: // URSHL Dd,Dn,Dm uint64x1_t vrshl_u64(uint64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VRSHL_U8: // URSHL Vd.8B,Vn.8B,Vm.8B uint8x8_t vrshl_u8(uint8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VRSHLD_S64: // SRSHL Dd,Dn,Dm int64_t vrshld_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VRSHLD_U64: // URSHL Dd,Dn,Dm uint64_t vrshld_u64(uint64_t a, int64_t b)
+ case ARM64_INTRIN_VSHL_S16: // SSHL Vd.4H,Vn.4H,Vm.4H int16x4_t vshl_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VSHL_S32: // SSHL Vd.2S,Vn.2S,Vm.2S int32x2_t vshl_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VSHL_S64: // SSHL Dd,Dn,Dm int64x1_t vshl_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VSHL_S8: // SSHL Vd.8B,Vn.8B,Vm.8B int8x8_t vshl_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VSHL_U16: // USHL Vd.4H,Vn.4H,Vm.4H uint16x4_t vshl_u16(uint16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VSHL_U32: // USHL Vd.2S,Vn.2S,Vm.2S uint32x2_t vshl_u32(uint32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VSHL_U64: // USHL Dd,Dn,Dm uint64x1_t vshl_u64(uint64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VSHL_U8: // USHL Vd.8B,Vn.8B,Vm.8B uint8x8_t vshl_u8(uint8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VSHLD_S64: // SSHL Dd,Dn,Dm int64_t vshld_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VSHLD_U64: // USHL Dd,Dn,Dm uint64_t vshld_u64(uint64_t a, int64_t b)
+ case ARM64_INTRIN_VSQADD_U16: // USQADD Vd.4H,Vn.4H uint16x4_t vsqadd_u16(uint16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VSQADD_U32: // USQADD Vd.2S,Vn.2S uint32x2_t vsqadd_u32(uint32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VSQADD_U64: // USQADD Dd,Dn uint64x1_t vsqadd_u64(uint64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VSQADD_U8: // USQADD Vd.8B,Vn.8B uint8x8_t vsqadd_u8(uint8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VSQADDD_U64: // USQADD Dd,Dn uint64_t vsqaddd_u64(uint64_t a, int64_t b)
+ case ARM64_INTRIN_VSUB_S16: // SUB Vd.4H,Vn.4H,Vm.4H int16x4_t vsub_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VSUB_S32: // SUB Vd.2S,Vn.2S,Vm.2S int32x2_t vsub_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VSUB_S64: // SUB Dd,Dn,Dm int64x1_t vsub_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VSUB_S8: // SUB Vd.8B,Vn.8B,Vm.8B int8x8_t vsub_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VSUB_U16: // SUB Vd.4H,Vn.4H,Vm.4H uint16x4_t vsub_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VSUB_U32: // SUB Vd.2S,Vn.2S,Vm.2S uint32x2_t vsub_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VSUB_U64: // SUB Dd,Dn,Dm uint64x1_t vsub_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VSUB_U8: // SUB Vd.8B,Vn.8B,Vm.8B uint8x8_t vsub_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VSUBD_S64: // SUB Dd,Dn,Dm int64_t vsubd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VSUBD_U64: // SUB Dd,Dn,Dm uint64_t vsubd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VSUBL_S16: // SSUBL Vd.4S,Vn.4H,Vm.4H int32x4_t vsubl_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VSUBL_S32: // SSUBL Vd.2D,Vn.2S,Vm.2S int64x2_t vsubl_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VSUBL_S8: // SSUBL Vd.8H,Vn.8B,Vm.8B int16x8_t vsubl_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VSUBL_U16: // USUBL Vd.4S,Vn.4H,Vm.4H uint32x4_t vsubl_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VSUBL_U32: // USUBL Vd.2D,Vn.2S,Vm.2S uint64x2_t vsubl_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VSUBL_U8: // USUBL Vd.8H,Vn.8B,Vm.8B uint16x8_t vsubl_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VTRN1_P16: // TRN1 Vd.4H,Vn.4H,Vm.4H poly16x4_t vtrn1_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VTRN1_P8: // TRN1 Vd.8B,Vn.8B,Vm.8B poly8x8_t vtrn1_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VTRN1_S16: // TRN1 Vd.4H,Vn.4H,Vm.4H int16x4_t vtrn1_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VTRN1_S32: // TRN1 Vd.2S,Vn.2S,Vm.2S int32x2_t vtrn1_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VTRN1_S8: // TRN1 Vd.8B,Vn.8B,Vm.8B int8x8_t vtrn1_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VTRN1_U16: // TRN1 Vd.4H,Vn.4H,Vm.4H uint16x4_t vtrn1_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VTRN1_U32: // TRN1 Vd.2S,Vn.2S,Vm.2S uint32x2_t vtrn1_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VTRN1_U8: // TRN1 Vd.8B,Vn.8B,Vm.8B uint8x8_t vtrn1_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VTRN2_P16: // TRN2 Vd.4H,Vn.4H,Vm.4H poly16x4_t vtrn2_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VTRN2_P8: // TRN2 Vd.8B,Vn.8B,Vm.8B poly8x8_t vtrn2_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VTRN2_S16: // TRN2 Vd.4H,Vn.4H,Vm.4H int16x4_t vtrn2_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VTRN2_S32: // TRN2 Vd.2S,Vn.2S,Vm.2S int32x2_t vtrn2_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VTRN2_S8: // TRN2 Vd.8B,Vn.8B,Vm.8B int8x8_t vtrn2_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VTRN2_U16: // TRN2 Vd.4H,Vn.4H,Vm.4H uint16x4_t vtrn2_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VTRN2_U32: // TRN2 Vd.2S,Vn.2S,Vm.2S uint32x2_t vtrn2_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VTRN2_U8: // TRN2 Vd.8B,Vn.8B,Vm.8B uint8x8_t vtrn2_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VTRN_P16: // TRN1 Vd1.4H,Vn.4H,Vm.4H poly16x4x2_t vtrn_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VTRN_P8: // TRN1 Vd1.8B,Vn.8B,Vm.8B poly8x8x2_t vtrn_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VTRN_S16: // TRN1 Vd1.4H,Vn.4H,Vm.4H int16x4x2_t vtrn_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VTRN_S32: // TRN1 Vd1.2S,Vn.2S,Vm.2S int32x2x2_t vtrn_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VTRN_S8: // TRN1 Vd1.8B,Vn.8B,Vm.8B int8x8x2_t vtrn_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VTRN_U16: // TRN1 Vd1.4H,Vn.4H,Vm.4H uint16x4x2_t vtrn_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VTRN_U32: // TRN1 Vd1.2S,Vn.2S,Vm.2S uint32x2x2_t vtrn_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VTRN_U8: // TRN1 Vd1.8B,Vn.8B,Vm.8B uint8x8x2_t vtrn_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VTST_P64: // CMTST Dd,Dn,Dm uint64x1_t vtst_p64(poly64x1_t a, poly64x1_t b)
+ case ARM64_INTRIN_VTST_P8: // CMTST Vd.8B,Vn.8B,Vm.8B uint8x8_t vtst_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VTST_S16: // CMTST Vd.4H,Vn.4H,Vm.4H uint16x4_t vtst_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VTST_S32: // CMTST Vd.2S,Vn.2S,Vm.2S uint32x2_t vtst_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VTST_S64: // CMTST Dd,Dn,Dm uint64x1_t vtst_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VTST_S8: // CMTST Vd.8B,Vn.8B,Vm.8B uint8x8_t vtst_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VTST_U16: // CMTST Vd.4H,Vn.4H,Vm.4H uint16x4_t vtst_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VTST_U32: // CMTST Vd.2S,Vn.2S,Vm.2S uint32x2_t vtst_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VTST_U64: // CMTST Dd,Dn,Dm uint64x1_t vtst_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VTST_U8: // CMTST Vd.8B,Vn.8B,Vm.8B uint8x8_t vtst_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VTSTD_S64: // CMTST Dd,Dn,Dm uint64_t vtstd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VTSTD_U64: // CMTST Dd,Dn,Dm uint64_t vtstd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VUQADD_S16: // SUQADD Vd.4H,Vn.4H int16x4_t vuqadd_s16(int16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VUQADD_S32: // SUQADD Vd.2S,Vn.2S int32x2_t vuqadd_s32(int32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VUQADD_S64: // SUQADD Dd,Dn int64x1_t vuqadd_s64(int64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VUQADD_S8: // SUQADD Vd.8B,Vn.8B int8x8_t vuqadd_s8(int8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VUQADDD_S64: // SUQADD Dd,Dn int64_t vuqaddd_s64(int64_t a, uint64_t b)
+ case ARM64_INTRIN_VUZP1_P16: // UZP1 Vd.4H,Vn.4H,Vm.4H poly16x4_t vuzp1_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VUZP1_P8: // UZP1 Vd.8B,Vn.8B,Vm.8B poly8x8_t vuzp1_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VUZP1_S16: // UZP1 Vd.4H,Vn.4H,Vm.4H int16x4_t vuzp1_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VUZP1_S32: // UZP1 Vd.2S,Vn.2S,Vm.2S int32x2_t vuzp1_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VUZP1_S8: // UZP1 Vd.8B,Vn.8B,Vm.8B int8x8_t vuzp1_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VUZP1_U16: // UZP1 Vd.4H,Vn.4H,Vm.4H uint16x4_t vuzp1_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VUZP1_U32: // UZP1 Vd.2S,Vn.2S,Vm.2S uint32x2_t vuzp1_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VUZP1_U8: // UZP1 Vd.8B,Vn.8B,Vm.8B uint8x8_t vuzp1_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VUZP2_P16: // UZP2 Vd.4H,Vn.4H,Vm.4H poly16x4_t vuzp2_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VUZP2_P8: // UZP2 Vd.8B,Vn.8B,Vm.8B poly8x8_t vuzp2_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VUZP2_S16: // UZP2 Vd.4H,Vn.4H,Vm.4H int16x4_t vuzp2_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VUZP2_S32: // UZP2 Vd.2S,Vn.2S,Vm.2S int32x2_t vuzp2_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VUZP2_S8: // UZP2 Vd.8B,Vn.8B,Vm.8B int8x8_t vuzp2_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VUZP2_U16: // UZP2 Vd.4H,Vn.4H,Vm.4H uint16x4_t vuzp2_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VUZP2_U32: // UZP2 Vd.2S,Vn.2S,Vm.2S uint32x2_t vuzp2_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VUZP2_U8: // UZP2 Vd.8B,Vn.8B,Vm.8B uint8x8_t vuzp2_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VUZP_P16: // UZP1 Vd1.4H,Vn.4H,Vm.4H poly16x4x2_t vuzp_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VUZP_P8: // UZP1 Vd1.8B,Vn.8B,Vm.8B poly8x8x2_t vuzp_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VUZP_S16: // UZP1 Vd1.4H,Vn.4H,Vm.4H int16x4x2_t vuzp_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VUZP_S32: // UZP1 Vd1.2S,Vn.2S,Vm.2S int32x2x2_t vuzp_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VUZP_S8: // UZP1 Vd1.8B,Vn.8B,Vm.8B int8x8x2_t vuzp_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VUZP_U16: // UZP1 Vd1.4H,Vn.4H,Vm.4H uint16x4x2_t vuzp_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VUZP_U32: // UZP1 Vd1.2S,Vn.2S,Vm.2S uint32x2x2_t vuzp_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VUZP_U8: // UZP1 Vd1.8B,Vn.8B,Vm.8B uint8x8x2_t vuzp_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VZIP1_P16: // ZIP1 Vd.4H,Vn.4H,Vm.4H poly16x4_t vzip1_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VZIP1_P8: // ZIP1 Vd.8B,Vn.8B,Vm.8B poly8x8_t vzip1_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VZIP1_S16: // ZIP1 Vd.4H,Vn.4H,Vm.4H int16x4_t vzip1_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VZIP1_S32: // ZIP1 Vd.2S,Vn.2S,Vm.2S int32x2_t vzip1_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VZIP1_S8: // ZIP1 Vd.8B,Vn.8B,Vm.8B int8x8_t vzip1_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VZIP1_U16: // ZIP1 Vd.4H,Vn.4H,Vm.4H uint16x4_t vzip1_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VZIP1_U32: // ZIP1 Vd.2S,Vn.2S,Vm.2S uint32x2_t vzip1_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VZIP1_U8: // ZIP1 Vd.8B,Vn.8B,Vm.8B uint8x8_t vzip1_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VZIP2_P16: // ZIP2 Vd.4H,Vn.4H,Vm.4H poly16x4_t vzip2_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VZIP2_P8: // ZIP2 Vd.8B,Vn.8B,Vm.8B poly8x8_t vzip2_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VZIP2_S16: // ZIP2 Vd.4H,Vn.4H,Vm.4H int16x4_t vzip2_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VZIP2_S32: // ZIP2 Vd.2S,Vn.2S,Vm.2S int32x2_t vzip2_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VZIP2_S8: // ZIP2 Vd.8B,Vn.8B,Vm.8B int8x8_t vzip2_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VZIP2_U16: // ZIP2 Vd.4H,Vn.4H,Vm.4H uint16x4_t vzip2_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VZIP2_U32: // ZIP2 Vd.2S,Vn.2S,Vm.2S uint32x2_t vzip2_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VZIP2_U8: // ZIP2 Vd.8B,Vn.8B,Vm.8B uint8x8_t vzip2_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VZIP_P16: // ZIP1 Vd1.4H,Vn.4H,Vm.4H poly16x4x2_t vzip_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VZIP_P8: // ZIP1 Vd1.8B,Vn.8B,Vm.8B poly8x8x2_t vzip_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VZIP_S16: // ZIP1 Vd1.4H,Vn.4H,Vm.4H int16x4x2_t vzip_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VZIP_S32: // ZIP1 Vd1.2S,Vn.2S,Vm.2S int32x2x2_t vzip_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VZIP_S8: // ZIP1 Vd1.8B,Vn.8B,Vm.8B int8x8x2_t vzip_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VZIP_U16: // ZIP1 Vd1.4H,Vn.4H,Vm.4H uint16x4x2_t vzip_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VZIP_U32: // ZIP1 Vd1.2S,Vn.2S,Vm.2S uint32x2x2_t vzip_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VZIP_U8: // ZIP1 Vd1.8B,Vn.8B,Vm.8B uint8x8x2_t vzip_u8(uint8x8_t a, uint8x8_t b)
+ return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false))};
+ case ARM64_INTRIN_VDOT_LANEQ_S32: // SDOT Vd.2S,Vn.8B,Vm.4B[lane] int32x2_t vdot_laneq_s32(int32x2_t r, int8x8_t a, int8x16_t b, const int lane)
+ case ARM64_INTRIN_VDOT_LANEQ_U32: // UDOT Vd.2S,Vn.8B,Vm.4B[lane] uint32x2_t vdot_laneq_u32(uint32x2_t r, uint8x8_t a, uint8x16_t b, const int lane)
+ case ARM64_INTRIN_VMLA_LANEQ_S16: // MLA Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vmla_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLA_LANEQ_S32: // MLA Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vmla_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLA_LANEQ_U16: // MLA Vd.4H,Vn.4H,Vm.H[lane] uint16x4_t vmla_laneq_u16(uint16x4_t a, uint16x4_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLA_LANEQ_U32: // MLA Vd.2S,Vn.2S,Vm.S[lane] uint32x2_t vmla_laneq_u32(uint32x2_t a, uint32x2_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLS_LANEQ_S16: // MLS Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vmls_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLS_LANEQ_S32: // MLS Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vmls_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLS_LANEQ_U16: // MLS Vd.4H,Vn.4H,Vm.H[lane] uint16x4_t vmls_laneq_u16(uint16x4_t a, uint16x4_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLS_LANEQ_U32: // MLS Vd.2S,Vn.2S,Vm.S[lane] uint32x2_t vmls_laneq_u32(uint32x2_t a, uint32x2_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAH_LANEQ_S16: // SQRDMLAH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqrdmlah_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAH_LANEQ_S32: // SQRDMLAH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqrdmlah_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSH_LANEQ_S16: // SQRDMLSH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqrdmlsh_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSH_LANEQ_S32: // SQRDMLSH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqrdmlsh_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VSUDOT_LANEQ_S32: // SUDOT Vd.2S,Vn.8B,Vm.4B[lane] int32x2_t vsudot_laneq_s32(int32x2_t r, int8x8_t a, uint8x16_t b, const int lane)
+ case ARM64_INTRIN_VUSDOT_LANEQ_S32: // USDOT Vd.2S,Vn.8B,Vm.4B[lane] int32x2_t vusdot_laneq_s32(int32x2_t r, uint8x8_t a, int8x16_t b, const int lane)
+ return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(16, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VMLA_N_S16: // MLA Vd.4H,Vn.4H,Vm.H[0] int16x4_t vmla_n_s16(int16x4_t a, int16x4_t b, int16_t c)
+ case ARM64_INTRIN_VMLA_N_U16: // MLA Vd.4H,Vn.4H,Vm.H[0] uint16x4_t vmla_n_u16(uint16x4_t a, uint16x4_t b, uint16_t c)
+ case ARM64_INTRIN_VMLS_N_S16: // MLS Vd.4H,Vn.4H,Vm.H[0] int16x4_t vmls_n_s16(int16x4_t a, int16x4_t b, int16_t c)
+ case ARM64_INTRIN_VMLS_N_U16: // MLS Vd.4H,Vn.4H,Vm.H[0] uint16x4_t vmls_n_u16(uint16x4_t a, uint16x4_t b, uint16_t c)
+ return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(2, false))};
+ case ARM64_INTRIN_VEXT_P16: // EXT Vd.8B,Vn.8B,Vm.8B,#n poly16x4_t vext_p16(poly16x4_t a, poly16x4_t b, const int n)
+ case ARM64_INTRIN_VEXT_P64: // EXT Vd.8B,Vn.8B,Vm.8B,#n poly64x1_t vext_p64(poly64x1_t a, poly64x1_t b, const int n)
+ case ARM64_INTRIN_VEXT_P8: // EXT Vd.8B,Vn.8B,Vm.8B,#n poly8x8_t vext_p8(poly8x8_t a, poly8x8_t b, const int n)
+ case ARM64_INTRIN_VEXT_S16: // EXT Vd.8B,Vn.8B,Vm.8B,#n int16x4_t vext_s16(int16x4_t a, int16x4_t b, const int n)
+ case ARM64_INTRIN_VEXT_S32: // EXT Vd.8B,Vn.8B,Vm.8B,#n int32x2_t vext_s32(int32x2_t a, int32x2_t b, const int n)
+ case ARM64_INTRIN_VEXT_S64: // EXT Vd.8B,Vn.8B,Vm.8B,#n int64x1_t vext_s64(int64x1_t a, int64x1_t b, const int n)
+ case ARM64_INTRIN_VEXT_S8: // EXT Vd.8B,Vn.8B,Vm.8B,#n int8x8_t vext_s8(int8x8_t a, int8x8_t b, const int n)
+ case ARM64_INTRIN_VEXT_U16: // EXT Vd.8B,Vn.8B,Vm.8B,#n uint16x4_t vext_u16(uint16x4_t a, uint16x4_t b, const int n)
+ case ARM64_INTRIN_VEXT_U32: // EXT Vd.8B,Vn.8B,Vm.8B,#n uint32x2_t vext_u32(uint32x2_t a, uint32x2_t b, const int n)
+ case ARM64_INTRIN_VEXT_U64: // EXT Vd.8B,Vn.8B,Vm.8B,#n uint64x1_t vext_u64(uint64x1_t a, uint64x1_t b, const int n)
+ case ARM64_INTRIN_VEXT_U8: // EXT Vd.8B,Vn.8B,Vm.8B,#n uint8x8_t vext_u8(uint8x8_t a, uint8x8_t b, const int n)
+ case ARM64_INTRIN_VMLA_N_S32: // MLA Vd.2S,Vn.2S,Vm.S[0] int32x2_t vmla_n_s32(int32x2_t a, int32x2_t b, int32_t c)
+ case ARM64_INTRIN_VMLA_N_U32: // MLA Vd.2S,Vn.2S,Vm.S[0] uint32x2_t vmla_n_u32(uint32x2_t a, uint32x2_t b, uint32_t c)
+ case ARM64_INTRIN_VMLS_N_S32: // MLS Vd.2S,Vn.2S,Vm.S[0] int32x2_t vmls_n_s32(int32x2_t a, int32x2_t b, int32_t c)
+ case ARM64_INTRIN_VMLS_N_U32: // MLS Vd.2S,Vn.2S,Vm.S[0] uint32x2_t vmls_n_u32(uint32x2_t a, uint32x2_t b, uint32_t c)
+ case ARM64_INTRIN_VMUL_LANE_S16: // MUL Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vmul_lane_s16(int16x4_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANE_S32: // MUL Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vmul_lane_s32(int32x2_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANE_U16: // MUL Vd.4H,Vn.4H,Vm.H[lane] uint16x4_t vmul_lane_u16(uint16x4_t a, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANE_U32: // MUL Vd.2S,Vn.2S,Vm.S[lane] uint32x2_t vmul_lane_u32(uint32x2_t a, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULL_LANE_S16: // SMULL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vmull_lane_s16(int16x4_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULL_LANE_S32: // SMULL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vmull_lane_s32(int32x2_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULL_LANE_U16: // UMULL Vd.4S,Vn.4H,Vm.H[lane] uint32x4_t vmull_lane_u16(uint16x4_t a, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULL_LANE_U32: // UMULL Vd.2D,Vn.2S,Vm.S[lane] uint64x2_t vmull_lane_u32(uint32x2_t a, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMULH_LANE_S16: // SQDMULH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqdmulh_lane_s16(int16x4_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULH_LANE_S32: // SQDMULH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqdmulh_lane_s32(int32x2_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_LANE_S16: // SQDMULL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vqdmull_lane_s16(int16x4_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_LANE_S32: // SQDMULL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vqdmull_lane_s32(int32x2_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULH_LANE_S16: // SQRDMULH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqrdmulh_lane_s16(int16x4_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULH_LANE_S32: // SQRDMULH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqrdmulh_lane_s32(int32x2_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VRSRA_N_S16: // SRSRA Vd.4H,Vn.4H,#n int16x4_t vrsra_n_s16(int16x4_t a, int16x4_t b, const int n)
+ case ARM64_INTRIN_VRSRA_N_S32: // SRSRA Vd.2S,Vn.2S,#n int32x2_t vrsra_n_s32(int32x2_t a, int32x2_t b, const int n)
+ case ARM64_INTRIN_VRSRA_N_S64: // SRSRA Dd,Dn,#n int64x1_t vrsra_n_s64(int64x1_t a, int64x1_t b, const int n)
+ case ARM64_INTRIN_VRSRA_N_S8: // SRSRA Vd.8B,Vn.8B,#n int8x8_t vrsra_n_s8(int8x8_t a, int8x8_t b, const int n)
+ case ARM64_INTRIN_VRSRA_N_U16: // URSRA Vd.4H,Vn.4H,#n uint16x4_t vrsra_n_u16(uint16x4_t a, uint16x4_t b, const int n)
+ case ARM64_INTRIN_VRSRA_N_U32: // URSRA Vd.2S,Vn.2S,#n uint32x2_t vrsra_n_u32(uint32x2_t a, uint32x2_t b, const int n)
+ case ARM64_INTRIN_VRSRA_N_U64: // URSRA Dd,Dn,#n uint64x1_t vrsra_n_u64(uint64x1_t a, uint64x1_t b, const int n)
+ case ARM64_INTRIN_VRSRA_N_U8: // URSRA Vd.8B,Vn.8B,#n uint8x8_t vrsra_n_u8(uint8x8_t a, uint8x8_t b, const int n)
+ case ARM64_INTRIN_VRSRAD_N_S64: // SRSRA Dd,Dn,#n int64_t vrsrad_n_s64(int64_t a, int64_t b, const int n)
+ case ARM64_INTRIN_VRSRAD_N_U64: // URSRA Dd,Dn,#n uint64_t vrsrad_n_u64(uint64_t a, uint64_t b, const int n)
+ case ARM64_INTRIN_VSET_LANE_P64: // MOV Vd.D[lane],Rn poly64x1_t vset_lane_p64(poly64_t a, poly64x1_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_S64: // MOV Vd.D[lane],Rn int64x1_t vset_lane_s64(int64_t a, int64x1_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_U64: // MOV Vd.D[lane],Rn uint64x1_t vset_lane_u64(uint64_t a, uint64x1_t v, const int lane)
+ case ARM64_INTRIN_VSLI_N_P16: // SLI Vd.4H,Vn.4H,#n poly16x4_t vsli_n_p16(poly16x4_t a, poly16x4_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_P64: // SLI Dd,Dn,#n poly64x1_t vsli_n_p64(poly64x1_t a, poly64x1_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_P8: // SLI Vd.8B,Vn.8B,#n poly8x8_t vsli_n_p8(poly8x8_t a, poly8x8_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_S16: // SLI Vd.4H,Vn.4H,#n int16x4_t vsli_n_s16(int16x4_t a, int16x4_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_S32: // SLI Vd.2S,Vn.2S,#n int32x2_t vsli_n_s32(int32x2_t a, int32x2_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_S64: // SLI Dd,Dn,#n int64x1_t vsli_n_s64(int64x1_t a, int64x1_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_S8: // SLI Vd.8B,Vn.8B,#n int8x8_t vsli_n_s8(int8x8_t a, int8x8_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_U16: // SLI Vd.4H,Vn.4H,#n uint16x4_t vsli_n_u16(uint16x4_t a, uint16x4_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_U32: // SLI Vd.2S,Vn.2S,#n uint32x2_t vsli_n_u32(uint32x2_t a, uint32x2_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_U64: // SLI Dd,Dn,#n uint64x1_t vsli_n_u64(uint64x1_t a, uint64x1_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_U8: // SLI Vd.8B,Vn.8B,#n uint8x8_t vsli_n_u8(uint8x8_t a, uint8x8_t b, const int n)
+ case ARM64_INTRIN_VSLID_N_S64: // SLI Dd,Dn,#n int64_t vslid_n_s64(int64_t a, int64_t b, const int n)
+ case ARM64_INTRIN_VSLID_N_U64: // SLI Dd,Dn,#n uint64_t vslid_n_u64(uint64_t a, uint64_t b, const int n)
+ case ARM64_INTRIN_VSRA_N_S16: // SSRA Vd.4H,Vn.4H,#n int16x4_t vsra_n_s16(int16x4_t a, int16x4_t b, const int n)
+ case ARM64_INTRIN_VSRA_N_S32: // SSRA Vd.2S,Vn.2S,#n int32x2_t vsra_n_s32(int32x2_t a, int32x2_t b, const int n)
+ case ARM64_INTRIN_VSRA_N_S64: // SSRA Dd,Dn,#n int64x1_t vsra_n_s64(int64x1_t a, int64x1_t b, const int n)
+ case ARM64_INTRIN_VSRA_N_S8: // SSRA Vd.8B,Vn.8B,#n int8x8_t vsra_n_s8(int8x8_t a, int8x8_t b, const int n)
+ case ARM64_INTRIN_VSRA_N_U16: // USRA Vd.4H,Vn.4H,#n uint16x4_t vsra_n_u16(uint16x4_t a, uint16x4_t b, const int n)
+ case ARM64_INTRIN_VSRA_N_U32: // USRA Vd.2S,Vn.2S,#n uint32x2_t vsra_n_u32(uint32x2_t a, uint32x2_t b, const int n)
+ case ARM64_INTRIN_VSRA_N_U64: // USRA Dd,Dn,#n uint64x1_t vsra_n_u64(uint64x1_t a, uint64x1_t b, const int n)
+ case ARM64_INTRIN_VSRA_N_U8: // USRA Vd.8B,Vn.8B,#n uint8x8_t vsra_n_u8(uint8x8_t a, uint8x8_t b, const int n)
+ case ARM64_INTRIN_VSRAD_N_S64: // SSRA Dd,Dn,#n int64_t vsrad_n_s64(int64_t a, int64_t b, const int n)
+ case ARM64_INTRIN_VSRAD_N_U64: // USRA Dd,Dn,#n uint64_t vsrad_n_u64(uint64_t a, uint64_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_P16: // SRI Vd.4H,Vn.4H,#n poly16x4_t vsri_n_p16(poly16x4_t a, poly16x4_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_P64: // SRI Dd,Dn,#n poly64x1_t vsri_n_p64(poly64x1_t a, poly64x1_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_P8: // SRI Vd.8B,Vn.8B,#n poly8x8_t vsri_n_p8(poly8x8_t a, poly8x8_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_S16: // SRI Vd.4H,Vn.4H,#n int16x4_t vsri_n_s16(int16x4_t a, int16x4_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_S32: // SRI Vd.2S,Vn.2S,#n int32x2_t vsri_n_s32(int32x2_t a, int32x2_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_S64: // SRI Dd,Dn,#n int64x1_t vsri_n_s64(int64x1_t a, int64x1_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_S8: // SRI Vd.8B,Vn.8B,#n int8x8_t vsri_n_s8(int8x8_t a, int8x8_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_U16: // SRI Vd.4H,Vn.4H,#n uint16x4_t vsri_n_u16(uint16x4_t a, uint16x4_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_U32: // SRI Vd.2S,Vn.2S,#n uint32x2_t vsri_n_u32(uint32x2_t a, uint32x2_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_U64: // SRI Dd,Dn,#n uint64x1_t vsri_n_u64(uint64x1_t a, uint64x1_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_U8: // SRI Vd.8B,Vn.8B,#n uint8x8_t vsri_n_u8(uint8x8_t a, uint8x8_t b, const int n)
+ case ARM64_INTRIN_VSRID_N_S64: // SRI Dd,Dn,#n int64_t vsrid_n_s64(int64_t a, int64_t b, const int n)
+ case ARM64_INTRIN_VSRID_N_U64: // SRI Dd,Dn,#n uint64_t vsrid_n_u64(uint64_t a, uint64_t b, const int n)
+ return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
+ case ARM64_INTRIN_VABA_S16: // SABA Vd.4H,Vn.4H,Vm.4H int16x4_t vaba_s16(int16x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VABA_S32: // SABA Vd.2S,Vn.2S,Vm.2S int32x2_t vaba_s32(int32x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VABA_S8: // SABA Vd.8B,Vn.8B,Vm.8B int8x8_t vaba_s8(int8x8_t a, int8x8_t b, int8x8_t c)
+ case ARM64_INTRIN_VABA_U16: // UABA Vd.4H,Vn.4H,Vm.4H uint16x4_t vaba_u16(uint16x4_t a, uint16x4_t b, uint16x4_t c)
+ case ARM64_INTRIN_VABA_U32: // UABA Vd.2S,Vn.2S,Vm.2S uint32x2_t vaba_u32(uint32x2_t a, uint32x2_t b, uint32x2_t c)
+ case ARM64_INTRIN_VABA_U8: // UABA Vd.8B,Vn.8B,Vm.8B uint8x8_t vaba_u8(uint8x8_t a, uint8x8_t b, uint8x8_t c)
+ case ARM64_INTRIN_VBSL_P16: // BSL Vd.8B,Vn.8B,Vm.8B poly16x4_t vbsl_p16(uint16x4_t a, poly16x4_t b, poly16x4_t c)
+ case ARM64_INTRIN_VBSL_P64: // BSL Vd.8B,Vn.8B,Vm.8B poly64x1_t vbsl_p64(poly64x1_t a, poly64x1_t b, poly64x1_t c)
+ case ARM64_INTRIN_VBSL_P8: // BSL Vd.8B,Vn.8B,Vm.8B poly8x8_t vbsl_p8(uint8x8_t a, poly8x8_t b, poly8x8_t c)
+ case ARM64_INTRIN_VBSL_S16: // BSL Vd.8B,Vn.8B,Vm.8B int16x4_t vbsl_s16(uint16x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VBSL_S32: // BSL Vd.8B,Vn.8B,Vm.8B int32x2_t vbsl_s32(uint32x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VBSL_S64: // BSL Vd.8B,Vn.8B,Vm.8B int64x1_t vbsl_s64(uint64x1_t a, int64x1_t b, int64x1_t c)
+ case ARM64_INTRIN_VBSL_S8: // BSL Vd.8B,Vn.8B,Vm.8B int8x8_t vbsl_s8(uint8x8_t a, int8x8_t b, int8x8_t c)
+ case ARM64_INTRIN_VBSL_U16: // BSL Vd.8B,Vn.8B,Vm.8B uint16x4_t vbsl_u16(uint16x4_t a, uint16x4_t b, uint16x4_t c)
+ case ARM64_INTRIN_VBSL_U32: // BSL Vd.8B,Vn.8B,Vm.8B uint32x2_t vbsl_u32(uint32x2_t a, uint32x2_t b, uint32x2_t c)
+ case ARM64_INTRIN_VBSL_U64: // BSL Vd.8B,Vn.8B,Vm.8B uint64x1_t vbsl_u64(uint64x1_t a, uint64x1_t b, uint64x1_t c)
+ case ARM64_INTRIN_VBSL_U8: // BSL Vd.8B,Vn.8B,Vm.8B uint8x8_t vbsl_u8(uint8x8_t a, uint8x8_t b, uint8x8_t c)
+ case ARM64_INTRIN_VDOT_S32: // SDOT Vd.2S,Vn.8B,Vm.8B int32x2_t vdot_s32(int32x2_t r, int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VDOT_U32: // UDOT Vd.2S,Vn.8B,Vm.8B uint32x2_t vdot_u32(uint32x2_t r, uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VMLA_S16: // MLA Vd.4H,Vn.4H,Vm.4H int16x4_t vmla_s16(int16x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VMLA_S32: // MLA Vd.2S,Vn.2S,Vm.2S int32x2_t vmla_s32(int32x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VMLA_S8: // MLA Vd.8B,Vn.8B,Vm.8B int8x8_t vmla_s8(int8x8_t a, int8x8_t b, int8x8_t c)
+ case ARM64_INTRIN_VMLA_U16: // MLA Vd.4H,Vn.4H,Vm.4H uint16x4_t vmla_u16(uint16x4_t a, uint16x4_t b, uint16x4_t c)
+ case ARM64_INTRIN_VMLA_U32: // MLA Vd.2S,Vn.2S,Vm.2S uint32x2_t vmla_u32(uint32x2_t a, uint32x2_t b, uint32x2_t c)
+ case ARM64_INTRIN_VMLA_U8: // MLA Vd.8B,Vn.8B,Vm.8B uint8x8_t vmla_u8(uint8x8_t a, uint8x8_t b, uint8x8_t c)
+ case ARM64_INTRIN_VMLS_S16: // MLS Vd.4H,Vn.4H,Vm.4H int16x4_t vmls_s16(int16x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VMLS_S32: // MLS Vd.2S,Vn.2S,Vm.2S int32x2_t vmls_s32(int32x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VMLS_S8: // MLS Vd.8B,Vn.8B,Vm.8B int8x8_t vmls_s8(int8x8_t a, int8x8_t b, int8x8_t c)
+ case ARM64_INTRIN_VMLS_U16: // MLS Vd.4H,Vn.4H,Vm.4H uint16x4_t vmls_u16(uint16x4_t a, uint16x4_t b, uint16x4_t c)
+ case ARM64_INTRIN_VMLS_U32: // MLS Vd.2S,Vn.2S,Vm.2S uint32x2_t vmls_u32(uint32x2_t a, uint32x2_t b, uint32x2_t c)
+ case ARM64_INTRIN_VMLS_U8: // MLS Vd.8B,Vn.8B,Vm.8B uint8x8_t vmls_u8(uint8x8_t a, uint8x8_t b, uint8x8_t c)
+ case ARM64_INTRIN_VQRDMLAH_S16: // SQRDMLAH Vd.4H,Vn.4H,Vm.4H int16x4_t vqrdmlah_s16(int16x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VQRDMLAH_S32: // SQRDMLAH Vd.2S,Vn.2S,Vm.2S int32x2_t vqrdmlah_s32(int32x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VQRDMLSH_S16: // SQRDMLSH Vd.4H,Vn.4H,Vm.4H int16x4_t vqrdmlsh_s16(int16x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VQRDMLSH_S32: // SQRDMLSH Vd.2S,Vn.2S,Vm.2S int32x2_t vqrdmlsh_s32(int32x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VUSDOT_S32: // USDOT Vd.2S,Vn.8B,Vm.8B int32x2_t vusdot_s32(int32x2_t r, uint8x8_t a, int8x8_t b)
+ return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false))};
+ case ARM64_INTRIN_VDOT_LANE_S32: // SDOT Vd.2S,Vn.8B,Vm.4B[lane] int32x2_t vdot_lane_s32(int32x2_t r, int8x8_t a, int8x8_t b, const int lane)
+ case ARM64_INTRIN_VDOT_LANE_U32: // UDOT Vd.2S,Vn.8B,Vm.4B[lane] uint32x2_t vdot_lane_u32(uint32x2_t r, uint8x8_t a, uint8x8_t b, const int lane)
+ case ARM64_INTRIN_VMLA_LANE_S16: // MLA Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vmla_lane_s16(int16x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLA_LANE_S32: // MLA Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vmla_lane_s32(int32x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLA_LANE_U16: // MLA Vd.4H,Vn.4H,Vm.H[lane] uint16x4_t vmla_lane_u16(uint16x4_t a, uint16x4_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLA_LANE_U32: // MLA Vd.2S,Vn.2S,Vm.S[lane] uint32x2_t vmla_lane_u32(uint32x2_t a, uint32x2_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLS_LANE_S16: // MLS Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vmls_lane_s16(int16x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLS_LANE_S32: // MLS Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vmls_lane_s32(int32x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLS_LANE_U16: // MLS Vd.4H,Vn.4H,Vm.H[lane] uint16x4_t vmls_lane_u16(uint16x4_t a, uint16x4_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLS_LANE_U32: // MLS Vd.2S,Vn.2S,Vm.S[lane] uint32x2_t vmls_lane_u32(uint32x2_t a, uint32x2_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAH_LANE_S16: // SQRDMLAH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqrdmlah_lane_s16(int16x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAH_LANE_S32: // SQRDMLAH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqrdmlah_lane_s32(int32x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSH_LANE_S16: // SQRDMLSH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqrdmlsh_lane_s16(int16x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSH_LANE_S32: // SQRDMLSH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqrdmlsh_lane_s32(int32x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VSUDOT_LANE_S32: // SUDOT Vd.2S,Vn.8B,Vm.4B[lane] int32x2_t vsudot_lane_s32(int32x2_t r, int8x8_t a, uint8x8_t b, const int lane)
+ case ARM64_INTRIN_VUSDOT_LANE_S32: // USDOT Vd.2S,Vn.8B,Vm.4B[lane] int32x2_t vusdot_lane_s32(int32x2_t r, uint8x8_t a, int8x8_t b, const int lane)
+ return {NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(8, false)), NameAndType(Type::IntegerType(4, false))};
default:
return vector<NameAndType>();
@@ -10903,2914 +11209,3174 @@ vector<Confidence<Ref<Type>>> NeonGetIntrinsicOutputs(uint32_t intrinsic)
{
switch (intrinsic)
{
- case ARM64_INTRIN_VABDQ_F16:
- case ARM64_INTRIN_VABDQ_F32:
- case ARM64_INTRIN_VABDQ_F64:
- case ARM64_INTRIN_VABSQ_F16:
- case ARM64_INTRIN_VABSQ_F32:
- case ARM64_INTRIN_VABSQ_F64:
- case ARM64_INTRIN_VADDQ_F16:
- case ARM64_INTRIN_VADDQ_F32:
- case ARM64_INTRIN_VADDQ_F64:
- case ARM64_INTRIN_VBFDOTQ_F32:
- case ARM64_INTRIN_VBFDOTQ_LANE_F32:
- case ARM64_INTRIN_VBFDOTQ_LANEQ_F32:
- case ARM64_INTRIN_VBFMLALBQ_F32:
- case ARM64_INTRIN_VBFMLALBQ_LANE_F32:
- case ARM64_INTRIN_VBFMLALBQ_LANEQ_F32:
- case ARM64_INTRIN_VBFMLALTQ_F32:
- case ARM64_INTRIN_VBFMLALTQ_LANE_F32:
- case ARM64_INTRIN_VBFMLALTQ_LANEQ_F32:
- case ARM64_INTRIN_VBFMMLAQ_F32:
- case ARM64_INTRIN_VBSLQ_F16:
- case ARM64_INTRIN_VBSLQ_F32:
- case ARM64_INTRIN_VBSLQ_F64:
- case ARM64_INTRIN_VCADDQ_ROT270_F16:
- case ARM64_INTRIN_VCADDQ_ROT270_F32:
- case ARM64_INTRIN_VCADDQ_ROT270_F64:
- case ARM64_INTRIN_VCADDQ_ROT90_F16:
- case ARM64_INTRIN_VCADDQ_ROT90_F32:
- case ARM64_INTRIN_VCADDQ_ROT90_F64:
- case ARM64_INTRIN_VCMLAQ_F16:
- case ARM64_INTRIN_VCMLAQ_F32:
- case ARM64_INTRIN_VCMLAQ_F64:
- case ARM64_INTRIN_VCMLAQ_LANE_F16:
- case ARM64_INTRIN_VCMLAQ_LANE_F32:
- case ARM64_INTRIN_VCMLAQ_LANEQ_F16:
- case ARM64_INTRIN_VCMLAQ_LANEQ_F32:
- case ARM64_INTRIN_VCMLAQ_ROT180_F16:
- case ARM64_INTRIN_VCMLAQ_ROT180_F32:
- case ARM64_INTRIN_VCMLAQ_ROT180_F64:
- case ARM64_INTRIN_VCMLAQ_ROT180_LANE_F16:
- case ARM64_INTRIN_VCMLAQ_ROT180_LANE_F32:
- case ARM64_INTRIN_VCMLAQ_ROT180_LANEQ_F16:
- case ARM64_INTRIN_VCMLAQ_ROT180_LANEQ_F32:
- case ARM64_INTRIN_VCMLAQ_ROT270_F16:
- case ARM64_INTRIN_VCMLAQ_ROT270_F32:
- case ARM64_INTRIN_VCMLAQ_ROT270_F64:
- case ARM64_INTRIN_VCMLAQ_ROT270_LANE_F16:
- case ARM64_INTRIN_VCMLAQ_ROT270_LANE_F32:
- case ARM64_INTRIN_VCMLAQ_ROT270_LANEQ_F16:
- case ARM64_INTRIN_VCMLAQ_ROT270_LANEQ_F32:
- case ARM64_INTRIN_VCMLAQ_ROT90_F16:
- case ARM64_INTRIN_VCMLAQ_ROT90_F32:
- case ARM64_INTRIN_VCMLAQ_ROT90_F64:
- case ARM64_INTRIN_VCMLAQ_ROT90_LANE_F16:
- case ARM64_INTRIN_VCMLAQ_ROT90_LANE_F32:
- case ARM64_INTRIN_VCMLAQ_ROT90_LANEQ_F16:
- case ARM64_INTRIN_VCMLAQ_ROT90_LANEQ_F32:
- case ARM64_INTRIN_VCVT_F32_BF16:
- case ARM64_INTRIN_VCVT_F32_F16:
- case ARM64_INTRIN_VCVT_F64_F32:
- case ARM64_INTRIN_VCVT_HIGH_F16_F32:
- case ARM64_INTRIN_VCVT_HIGH_F32_F16:
- case ARM64_INTRIN_VCVT_HIGH_F32_F64:
- case ARM64_INTRIN_VCVT_HIGH_F64_F32:
- case ARM64_INTRIN_VCVTQ_F16_S16:
- case ARM64_INTRIN_VCVTQ_F16_U16:
- case ARM64_INTRIN_VCVTQ_F32_S32:
- case ARM64_INTRIN_VCVTQ_F32_U32:
- case ARM64_INTRIN_VCVTQ_F64_S64:
- case ARM64_INTRIN_VCVTQ_F64_U64:
- case ARM64_INTRIN_VCVTQ_HIGH_BF16_F32:
- case ARM64_INTRIN_VCVTQ_HIGH_F32_BF16:
- case ARM64_INTRIN_VCVTQ_LOW_BF16_F32:
- case ARM64_INTRIN_VCVTQ_LOW_F32_BF16:
- case ARM64_INTRIN_VCVTQ_N_F16_S16:
- case ARM64_INTRIN_VCVTQ_N_F16_U16:
- case ARM64_INTRIN_VCVTQ_N_F32_S32:
- case ARM64_INTRIN_VCVTQ_N_F32_U32:
- case ARM64_INTRIN_VCVTQ_N_F64_S64:
- case ARM64_INTRIN_VCVTQ_N_F64_U64:
- case ARM64_INTRIN_VCVTX_HIGH_F32_F64:
- case ARM64_INTRIN_VDIVQ_F16:
- case ARM64_INTRIN_VDIVQ_F32:
- case ARM64_INTRIN_VDIVQ_F64:
- case ARM64_INTRIN_VDUPQ_LANE_BF16:
- case ARM64_INTRIN_VDUPQ_LANE_F16:
- case ARM64_INTRIN_VDUPQ_LANE_F32:
- case ARM64_INTRIN_VDUPQ_LANE_F64:
- case ARM64_INTRIN_VDUPQ_LANEQ_BF16:
- case ARM64_INTRIN_VDUPQ_LANEQ_F16:
- case ARM64_INTRIN_VDUPQ_LANEQ_F32:
- case ARM64_INTRIN_VDUPQ_LANEQ_F64:
- case ARM64_INTRIN_VDUPQ_N_BF16:
- case ARM64_INTRIN_VDUPQ_N_F16:
- case ARM64_INTRIN_VDUPQ_N_F32:
- case ARM64_INTRIN_VDUPQ_N_F64:
- case ARM64_INTRIN_VEXTQ_F16:
- case ARM64_INTRIN_VEXTQ_F32:
- case ARM64_INTRIN_VEXTQ_F64:
- case ARM64_INTRIN_VFMAQ_F16:
- case ARM64_INTRIN_VFMAQ_F32:
- case ARM64_INTRIN_VFMAQ_F64:
- case ARM64_INTRIN_VFMAQ_LANE_F16:
- case ARM64_INTRIN_VFMAQ_LANE_F32:
- case ARM64_INTRIN_VFMAQ_LANE_F64:
- case ARM64_INTRIN_VFMAQ_LANEQ_F16:
- case ARM64_INTRIN_VFMAQ_LANEQ_F32:
- case ARM64_INTRIN_VFMAQ_LANEQ_F64:
- case ARM64_INTRIN_VFMAQ_N_F16:
- case ARM64_INTRIN_VFMAQ_N_F32:
- case ARM64_INTRIN_VFMAQ_N_F64:
- case ARM64_INTRIN_VFMLALQ_HIGH_F16:
- case ARM64_INTRIN_VFMLALQ_LANE_HIGH_F16:
- case ARM64_INTRIN_VFMLALQ_LANE_LOW_F16:
- case ARM64_INTRIN_VFMLALQ_LANEQ_HIGH_F16:
- case ARM64_INTRIN_VFMLALQ_LANEQ_LOW_F16:
- case ARM64_INTRIN_VFMLALQ_LOW_F16:
- case ARM64_INTRIN_VFMLSLQ_HIGH_F16:
- case ARM64_INTRIN_VFMLSLQ_LANE_HIGH_F16:
- case ARM64_INTRIN_VFMLSLQ_LANE_LOW_F16:
- case ARM64_INTRIN_VFMLSLQ_LANEQ_HIGH_F16:
- case ARM64_INTRIN_VFMLSLQ_LANEQ_LOW_F16:
- case ARM64_INTRIN_VFMLSLQ_LOW_F16:
- case ARM64_INTRIN_VFMSQ_F16:
- case ARM64_INTRIN_VFMSQ_F32:
- case ARM64_INTRIN_VFMSQ_F64:
- case ARM64_INTRIN_VFMSQ_LANE_F16:
- case ARM64_INTRIN_VFMSQ_LANE_F32:
- case ARM64_INTRIN_VFMSQ_LANE_F64:
- case ARM64_INTRIN_VFMSQ_LANEQ_F16:
- case ARM64_INTRIN_VFMSQ_LANEQ_F32:
- case ARM64_INTRIN_VFMSQ_LANEQ_F64:
- case ARM64_INTRIN_VFMSQ_N_F16:
- case ARM64_INTRIN_VFMSQ_N_F32:
- case ARM64_INTRIN_VFMSQ_N_F64:
- case ARM64_INTRIN_VMAXNMQ_F16:
- case ARM64_INTRIN_VMAXNMQ_F32:
- case ARM64_INTRIN_VMAXNMQ_F64:
- case ARM64_INTRIN_VMAXQ_F16:
- case ARM64_INTRIN_VMAXQ_F32:
- case ARM64_INTRIN_VMAXQ_F64:
- case ARM64_INTRIN_VMINNMQ_F16:
- case ARM64_INTRIN_VMINNMQ_F32:
- case ARM64_INTRIN_VMINNMQ_F64:
- case ARM64_INTRIN_VMINQ_F16:
- case ARM64_INTRIN_VMINQ_F32:
- case ARM64_INTRIN_VMINQ_F64:
- case ARM64_INTRIN_VMOVQ_N_F16:
- case ARM64_INTRIN_VMOVQ_N_F32:
- case ARM64_INTRIN_VMOVQ_N_F64:
- case ARM64_INTRIN_VMULQ_F16:
- case ARM64_INTRIN_VMULQ_F32:
- case ARM64_INTRIN_VMULQ_F64:
- case ARM64_INTRIN_VMULQ_LANE_F16:
- case ARM64_INTRIN_VMULQ_LANE_F32:
- case ARM64_INTRIN_VMULQ_LANE_F64:
- case ARM64_INTRIN_VMULQ_LANEQ_F16:
- case ARM64_INTRIN_VMULQ_LANEQ_F32:
- case ARM64_INTRIN_VMULQ_LANEQ_F64:
- case ARM64_INTRIN_VMULQ_N_F16:
- case ARM64_INTRIN_VMULQ_N_F32:
- case ARM64_INTRIN_VMULQ_N_F64:
- case ARM64_INTRIN_VMULXQ_F16:
- case ARM64_INTRIN_VMULXQ_F32:
- case ARM64_INTRIN_VMULXQ_F64:
- case ARM64_INTRIN_VMULXQ_LANE_F16:
- case ARM64_INTRIN_VMULXQ_LANE_F32:
- case ARM64_INTRIN_VMULXQ_LANE_F64:
- case ARM64_INTRIN_VMULXQ_LANEQ_F16:
- case ARM64_INTRIN_VMULXQ_LANEQ_F32:
- case ARM64_INTRIN_VMULXQ_LANEQ_F64:
- case ARM64_INTRIN_VMULXQ_N_F16:
- case ARM64_INTRIN_VNEGQ_F16:
- case ARM64_INTRIN_VNEGQ_F32:
- case ARM64_INTRIN_VNEGQ_F64:
- case ARM64_INTRIN_VPADDQ_F16:
- case ARM64_INTRIN_VPADDQ_F32:
- case ARM64_INTRIN_VPADDQ_F64:
- case ARM64_INTRIN_VPMAXNMQ_F16:
- case ARM64_INTRIN_VPMAXNMQ_F32:
- case ARM64_INTRIN_VPMAXNMQ_F64:
- case ARM64_INTRIN_VPMAXQ_F16:
- case ARM64_INTRIN_VPMAXQ_F32:
- case ARM64_INTRIN_VPMAXQ_F64:
- case ARM64_INTRIN_VPMINNMQ_F16:
- case ARM64_INTRIN_VPMINNMQ_F32:
- case ARM64_INTRIN_VPMINNMQ_F64:
- case ARM64_INTRIN_VPMINQ_F16:
- case ARM64_INTRIN_VPMINQ_F32:
- case ARM64_INTRIN_VPMINQ_F64:
- case ARM64_INTRIN_VRECPEQ_F16:
- case ARM64_INTRIN_VRECPEQ_F32:
- case ARM64_INTRIN_VRECPEQ_F64:
- case ARM64_INTRIN_VRECPSQ_F16:
- case ARM64_INTRIN_VRECPSQ_F32:
- case ARM64_INTRIN_VRECPSQ_F64:
- case ARM64_INTRIN_VREV64Q_F16:
- case ARM64_INTRIN_VREV64Q_F32:
- case ARM64_INTRIN_VRND32XQ_F32:
- case ARM64_INTRIN_VRND32XQ_F64:
- case ARM64_INTRIN_VRND32ZQ_F32:
- case ARM64_INTRIN_VRND32ZQ_F64:
- case ARM64_INTRIN_VRND64XQ_F32:
- case ARM64_INTRIN_VRND64XQ_F64:
- case ARM64_INTRIN_VRND64ZQ_F32:
- case ARM64_INTRIN_VRND64ZQ_F64:
- case ARM64_INTRIN_VRNDAQ_F16:
- case ARM64_INTRIN_VRNDAQ_F32:
- case ARM64_INTRIN_VRNDAQ_F64:
- case ARM64_INTRIN_VRNDIQ_F16:
- case ARM64_INTRIN_VRNDIQ_F32:
- case ARM64_INTRIN_VRNDIQ_F64:
- case ARM64_INTRIN_VRNDMQ_F16:
- case ARM64_INTRIN_VRNDMQ_F32:
- case ARM64_INTRIN_VRNDMQ_F64:
- case ARM64_INTRIN_VRNDNQ_F16:
- case ARM64_INTRIN_VRNDNQ_F32:
- case ARM64_INTRIN_VRNDNQ_F64:
- case ARM64_INTRIN_VRNDPQ_F16:
- case ARM64_INTRIN_VRNDPQ_F32:
- case ARM64_INTRIN_VRNDPQ_F64:
- case ARM64_INTRIN_VRNDQ_F16:
- case ARM64_INTRIN_VRNDQ_F32:
- case ARM64_INTRIN_VRNDQ_F64:
- case ARM64_INTRIN_VRNDXQ_F16:
- case ARM64_INTRIN_VRNDXQ_F32:
- case ARM64_INTRIN_VRNDXQ_F64:
- case ARM64_INTRIN_VRSQRTEQ_F16:
- case ARM64_INTRIN_VRSQRTEQ_F32:
- case ARM64_INTRIN_VRSQRTEQ_F64:
- case ARM64_INTRIN_VRSQRTSQ_F16:
- case ARM64_INTRIN_VRSQRTSQ_F32:
- case ARM64_INTRIN_VRSQRTSQ_F64:
- case ARM64_INTRIN_VSETQ_LANE_BF16:
- case ARM64_INTRIN_VSETQ_LANE_F16:
- case ARM64_INTRIN_VSETQ_LANE_F32:
- case ARM64_INTRIN_VSETQ_LANE_F64:
- case ARM64_INTRIN_VSQRTQ_F16:
- case ARM64_INTRIN_VSQRTQ_F32:
- case ARM64_INTRIN_VSQRTQ_F64:
- case ARM64_INTRIN_VSUBQ_F16:
- case ARM64_INTRIN_VSUBQ_F32:
- case ARM64_INTRIN_VSUBQ_F64:
- case ARM64_INTRIN_VTRN1Q_F16:
- case ARM64_INTRIN_VTRN1Q_F32:
- case ARM64_INTRIN_VTRN1Q_F64:
- case ARM64_INTRIN_VTRN2Q_F16:
- case ARM64_INTRIN_VTRN2Q_F32:
- case ARM64_INTRIN_VTRN2Q_F64:
- case ARM64_INTRIN_VUZP1Q_F16:
- case ARM64_INTRIN_VUZP1Q_F32:
- case ARM64_INTRIN_VUZP1Q_F64:
- case ARM64_INTRIN_VUZP2Q_F16:
- case ARM64_INTRIN_VUZP2Q_F32:
- case ARM64_INTRIN_VUZP2Q_F64:
- case ARM64_INTRIN_VZIP1Q_F16:
- case ARM64_INTRIN_VZIP1Q_F32:
- case ARM64_INTRIN_VZIP1Q_F64:
- case ARM64_INTRIN_VZIP2Q_F16:
- case ARM64_INTRIN_VZIP2Q_F32:
- case ARM64_INTRIN_VZIP2Q_F64:
- case ARM64_INTRIN_VCVTH_N_F16_U32:
- return {Type::FloatType(16)};
- case ARM64_INTRIN_VABDH_F16:
- case ARM64_INTRIN_VABSH_F16:
- case ARM64_INTRIN_VADDH_F16:
- case ARM64_INTRIN_VCVTH_BF16_F32:
- case ARM64_INTRIN_VCVTH_F16_S16:
- case ARM64_INTRIN_VCVTH_F16_S32:
- case ARM64_INTRIN_VCVTH_F16_S64:
- case ARM64_INTRIN_VCVTH_F16_U16:
- case ARM64_INTRIN_VCVTH_F16_U32:
- case ARM64_INTRIN_VCVTH_F16_U64:
- case ARM64_INTRIN_VCVTH_N_F16_S16:
- case ARM64_INTRIN_VCVTH_N_F16_S32:
- case ARM64_INTRIN_VCVTH_N_F16_S64:
- case ARM64_INTRIN_VCVTH_N_F16_U16:
- case ARM64_INTRIN_VDIVH_F16:
- case ARM64_INTRIN_VDUPH_LANE_BF16:
- case ARM64_INTRIN_VDUPH_LANE_F16:
- case ARM64_INTRIN_VDUPH_LANEQ_BF16:
- case ARM64_INTRIN_VDUPH_LANEQ_F16:
- case ARM64_INTRIN_VFMAH_F16:
- case ARM64_INTRIN_VFMAH_LANE_F16:
- case ARM64_INTRIN_VFMAH_LANEQ_F16:
- case ARM64_INTRIN_VFMSH_F16:
- case ARM64_INTRIN_VFMSH_LANE_F16:
- case ARM64_INTRIN_VFMSH_LANEQ_F16:
- case ARM64_INTRIN_VGET_LANE_BF16:
- case ARM64_INTRIN_VGET_LANE_F16:
- case ARM64_INTRIN_VGETQ_LANE_BF16:
- case ARM64_INTRIN_VGETQ_LANE_F16:
- case ARM64_INTRIN_VMAXH_F16:
- case ARM64_INTRIN_VMAXNMH_F16:
- case ARM64_INTRIN_VMAXNMV_F16:
- case ARM64_INTRIN_VMAXNMVQ_F16:
- case ARM64_INTRIN_VMAXV_F16:
- case ARM64_INTRIN_VMAXVQ_F16:
- case ARM64_INTRIN_VMINH_F16:
- case ARM64_INTRIN_VMINNMH_F16:
- case ARM64_INTRIN_VMINNMV_F16:
- case ARM64_INTRIN_VMINNMVQ_F16:
- case ARM64_INTRIN_VMINV_F16:
- case ARM64_INTRIN_VMINVQ_F16:
- case ARM64_INTRIN_VMULH_F16:
- case ARM64_INTRIN_VMULH_LANE_F16:
- case ARM64_INTRIN_VMULH_LANEQ_F16:
- case ARM64_INTRIN_VMULXH_F16:
- case ARM64_INTRIN_VMULXH_LANE_F16:
- case ARM64_INTRIN_VMULXH_LANEQ_F16:
- case ARM64_INTRIN_VNEGH_F16:
- case ARM64_INTRIN_VRECPEH_F16:
- case ARM64_INTRIN_VRECPSH_F16:
- case ARM64_INTRIN_VRECPXH_F16:
- case ARM64_INTRIN_VRNDAH_F16:
- case ARM64_INTRIN_VRNDH_F16:
- case ARM64_INTRIN_VRNDIH_F16:
- case ARM64_INTRIN_VRNDMH_F16:
- case ARM64_INTRIN_VRNDNH_F16:
- case ARM64_INTRIN_VRNDPH_F16:
- case ARM64_INTRIN_VRNDXH_F16:
- case ARM64_INTRIN_VRSQRTEH_F16:
- case ARM64_INTRIN_VRSQRTSH_F16:
- case ARM64_INTRIN_VSQRTH_F16:
- case ARM64_INTRIN_VSUBH_F16:
- case ARM64_INTRIN_VCVTH_N_F16_U64:
- return {Type::FloatType(2)};
- case ARM64_INTRIN_VABDS_F32:
- case ARM64_INTRIN_VADDV_F32:
- case ARM64_INTRIN_VCVTAH_F32_BF16:
- case ARM64_INTRIN_VCVTS_F32_S32:
- case ARM64_INTRIN_VCVTS_F32_U32:
- case ARM64_INTRIN_VCVTS_N_F32_S32:
- case ARM64_INTRIN_VCVTS_N_F32_U32:
- case ARM64_INTRIN_VCVTS_N_F32_U64:
- case ARM64_INTRIN_VCVTXD_F32_F64:
- case ARM64_INTRIN_VDUPS_LANE_F32:
- case ARM64_INTRIN_VDUPS_LANEQ_F32:
- case ARM64_INTRIN_VFMAS_LANE_F32:
- case ARM64_INTRIN_VFMAS_LANEQ_F32:
- case ARM64_INTRIN_VFMSS_LANE_F32:
- case ARM64_INTRIN_VFMSS_LANEQ_F32:
- case ARM64_INTRIN_VGET_LANE_F32:
- case ARM64_INTRIN_VGETQ_LANE_F32:
- case ARM64_INTRIN_VMAXNMV_F32:
- case ARM64_INTRIN_VMAXNMVQ_F32:
- case ARM64_INTRIN_VMAXV_F32:
- case ARM64_INTRIN_VMAXVQ_F32:
- case ARM64_INTRIN_VMINNMV_F32:
- case ARM64_INTRIN_VMINNMVQ_F32:
- case ARM64_INTRIN_VMINV_F32:
- case ARM64_INTRIN_VMINVQ_F32:
- case ARM64_INTRIN_VMULS_LANE_F32:
- case ARM64_INTRIN_VMULS_LANEQ_F32:
- case ARM64_INTRIN_VMULXS_F32:
- case ARM64_INTRIN_VMULXS_LANE_F32:
- case ARM64_INTRIN_VMULXS_LANEQ_F32:
- case ARM64_INTRIN_VPADDS_F32:
- case ARM64_INTRIN_VPMAXNMS_F32:
- case ARM64_INTRIN_VPMAXS_F32:
- case ARM64_INTRIN_VPMINNMS_F32:
- case ARM64_INTRIN_VPMINS_F32:
- case ARM64_INTRIN_VRECPES_F32:
- case ARM64_INTRIN_VRECPSS_F32:
- case ARM64_INTRIN_VRECPXS_F32:
- case ARM64_INTRIN_VRNDNS_F32:
- case ARM64_INTRIN_VRSQRTES_F32:
- case ARM64_INTRIN_VRSQRTSS_F32:
- case ARM64_INTRIN_VCVT_F32_U64:
- return {Type::FloatType(4)};
- case ARM64_INTRIN_VABD_F16:
- case ARM64_INTRIN_VABD_F32:
- case ARM64_INTRIN_VABD_F64:
- case ARM64_INTRIN_VABDD_F64:
- case ARM64_INTRIN_VABS_F16:
- case ARM64_INTRIN_VABS_F32:
- case ARM64_INTRIN_VABS_F64:
- case ARM64_INTRIN_VADD_F16:
- case ARM64_INTRIN_VADD_F32:
- case ARM64_INTRIN_VADD_F64:
- case ARM64_INTRIN_VADDVQ_F64:
- case ARM64_INTRIN_VBFDOT_F32:
- case ARM64_INTRIN_VBFDOT_LANE_F32:
- case ARM64_INTRIN_VBFDOT_LANEQ_F32:
- case ARM64_INTRIN_VBSL_F16:
- case ARM64_INTRIN_VBSL_F32:
- case ARM64_INTRIN_VBSL_F64:
- case ARM64_INTRIN_VCADD_ROT270_F16:
- case ARM64_INTRIN_VCADD_ROT270_F32:
- case ARM64_INTRIN_VCADD_ROT90_F16:
- case ARM64_INTRIN_VCADD_ROT90_F32:
- case ARM64_INTRIN_VCMLA_F16:
- case ARM64_INTRIN_VCMLA_F32:
- case ARM64_INTRIN_VCMLA_LANE_F16:
- case ARM64_INTRIN_VCMLA_LANE_F32:
- case ARM64_INTRIN_VCMLA_LANEQ_F16:
- case ARM64_INTRIN_VCMLA_ROT180_F16:
- case ARM64_INTRIN_VCMLA_ROT180_F32:
- case ARM64_INTRIN_VCMLA_ROT180_LANE_F16:
- case ARM64_INTRIN_VCMLA_ROT180_LANE_F32:
- case ARM64_INTRIN_VCMLA_ROT180_LANEQ_F16:
- case ARM64_INTRIN_VCMLA_ROT270_F16:
- case ARM64_INTRIN_VCMLA_ROT270_F32:
- case ARM64_INTRIN_VCMLA_ROT270_LANE_F16:
- case ARM64_INTRIN_VCMLA_ROT270_LANE_F32:
- case ARM64_INTRIN_VCMLA_ROT270_LANEQ_F16:
- case ARM64_INTRIN_VCMLA_ROT90_F16:
- case ARM64_INTRIN_VCMLA_ROT90_F32:
- case ARM64_INTRIN_VCMLA_ROT90_LANE_F16:
- case ARM64_INTRIN_VCMLA_ROT90_LANE_F32:
- case ARM64_INTRIN_VCMLA_ROT90_LANEQ_F16:
- case ARM64_INTRIN_VCREATE_BF16:
- case ARM64_INTRIN_VCREATE_F16:
- case ARM64_INTRIN_VCREATE_F32:
- case ARM64_INTRIN_VCREATE_F64:
- case ARM64_INTRIN_VCVT_BF16_F32:
- case ARM64_INTRIN_VCVT_F16_F32:
- case ARM64_INTRIN_VCVT_F16_S16:
- case ARM64_INTRIN_VCVT_F16_U16:
- case ARM64_INTRIN_VCVT_F32_F64:
- case ARM64_INTRIN_VCVT_F32_S32:
- case ARM64_INTRIN_VCVT_F32_U32:
- case ARM64_INTRIN_VCVT_F64_S64:
- case ARM64_INTRIN_VCVT_F64_U64:
- case ARM64_INTRIN_VCVT_F64_U32:
- case ARM64_INTRIN_VCVT_N_F16_S16:
- case ARM64_INTRIN_VCVT_N_F16_U16:
- case ARM64_INTRIN_VCVT_N_F32_S32:
- case ARM64_INTRIN_VCVT_N_F32_U32:
- case ARM64_INTRIN_VCVT_N_F64_S64:
- case ARM64_INTRIN_VCVT_N_F64_U64:
- case ARM64_INTRIN_VCVTD_F64_S64:
- case ARM64_INTRIN_VCVTD_F64_U64:
- case ARM64_INTRIN_VCVTD_N_F64_U32:
- case ARM64_INTRIN_VCVTD_N_F64_S64:
- case ARM64_INTRIN_VCVTD_N_F64_U64:
- case ARM64_INTRIN_VCVTX_F32_F64:
- case ARM64_INTRIN_VDIV_F16:
- case ARM64_INTRIN_VDIV_F32:
- case ARM64_INTRIN_VDIV_F64:
- case ARM64_INTRIN_VDUP_LANE_BF16:
- case ARM64_INTRIN_VDUP_LANE_F16:
- case ARM64_INTRIN_VDUP_LANE_F32:
- case ARM64_INTRIN_VDUP_LANE_F64:
- case ARM64_INTRIN_VDUP_LANEQ_BF16:
- case ARM64_INTRIN_VDUP_LANEQ_F16:
- case ARM64_INTRIN_VDUP_LANEQ_F32:
- case ARM64_INTRIN_VDUP_LANEQ_F64:
- case ARM64_INTRIN_VDUP_N_BF16:
- case ARM64_INTRIN_VDUP_N_F16:
- case ARM64_INTRIN_VDUP_N_F32:
- case ARM64_INTRIN_VDUP_N_F64:
- case ARM64_INTRIN_VDUPD_LANE_F64:
- case ARM64_INTRIN_VDUPD_LANEQ_F64:
- case ARM64_INTRIN_VEXT_F16:
- case ARM64_INTRIN_VEXT_F32:
- case ARM64_INTRIN_VEXT_F64:
- case ARM64_INTRIN_VFMA_F16:
- case ARM64_INTRIN_VFMA_F32:
- case ARM64_INTRIN_VFMA_F64:
- case ARM64_INTRIN_VFMA_LANE_F16:
- case ARM64_INTRIN_VFMA_LANE_F32:
- case ARM64_INTRIN_VFMA_LANE_F64:
- case ARM64_INTRIN_VFMA_LANEQ_F16:
- case ARM64_INTRIN_VFMA_LANEQ_F32:
- case ARM64_INTRIN_VFMA_LANEQ_F64:
- case ARM64_INTRIN_VFMA_N_F16:
- case ARM64_INTRIN_VFMA_N_F32:
- case ARM64_INTRIN_VFMA_N_F64:
- case ARM64_INTRIN_VFMAD_LANE_F64:
- case ARM64_INTRIN_VFMAD_LANEQ_F64:
- case ARM64_INTRIN_VFMLAL_HIGH_F16:
- case ARM64_INTRIN_VFMLAL_LANE_HIGH_F16:
- case ARM64_INTRIN_VFMLAL_LANE_LOW_F16:
- case ARM64_INTRIN_VFMLAL_LANEQ_HIGH_F16:
- case ARM64_INTRIN_VFMLAL_LANEQ_LOW_F16:
- case ARM64_INTRIN_VFMLAL_LOW_F16:
- case ARM64_INTRIN_VFMLSL_HIGH_F16:
- case ARM64_INTRIN_VFMLSL_LANE_HIGH_F16:
- case ARM64_INTRIN_VFMLSL_LANE_LOW_F16:
- case ARM64_INTRIN_VFMLSL_LANEQ_HIGH_F16:
- case ARM64_INTRIN_VFMLSL_LANEQ_LOW_F16:
- case ARM64_INTRIN_VFMLSL_LOW_F16:
- case ARM64_INTRIN_VFMS_F16:
- case ARM64_INTRIN_VFMS_F32:
- case ARM64_INTRIN_VFMS_F64:
- case ARM64_INTRIN_VFMS_LANE_F16:
- case ARM64_INTRIN_VFMS_LANE_F32:
- case ARM64_INTRIN_VFMS_LANE_F64:
- case ARM64_INTRIN_VFMS_LANEQ_F16:
- case ARM64_INTRIN_VFMS_LANEQ_F32:
- case ARM64_INTRIN_VFMS_LANEQ_F64:
- case ARM64_INTRIN_VFMS_N_F16:
- case ARM64_INTRIN_VFMS_N_F32:
- case ARM64_INTRIN_VFMS_N_F64:
- case ARM64_INTRIN_VFMSD_LANE_F64:
- case ARM64_INTRIN_VFMSD_LANEQ_F64:
- case ARM64_INTRIN_VGET_HIGH_BF16:
- case ARM64_INTRIN_VGET_HIGH_F16:
- case ARM64_INTRIN_VGET_HIGH_F32:
- case ARM64_INTRIN_VGET_HIGH_F64:
- case ARM64_INTRIN_VGET_LANE_F64:
- case ARM64_INTRIN_VGET_LOW_BF16:
- case ARM64_INTRIN_VGET_LOW_F16:
- case ARM64_INTRIN_VGET_LOW_F32:
- case ARM64_INTRIN_VGET_LOW_F64:
- case ARM64_INTRIN_VGETQ_LANE_F64:
- case ARM64_INTRIN_VMAX_F16:
- case ARM64_INTRIN_VMAX_F32:
- case ARM64_INTRIN_VMAX_F64:
- case ARM64_INTRIN_VMAXNM_F16:
- case ARM64_INTRIN_VMAXNM_F32:
- case ARM64_INTRIN_VMAXNM_F64:
- case ARM64_INTRIN_VMAXNMVQ_F64:
- case ARM64_INTRIN_VMAXVQ_F64:
- case ARM64_INTRIN_VMIN_F16:
- case ARM64_INTRIN_VMIN_F32:
- case ARM64_INTRIN_VMIN_F64:
- case ARM64_INTRIN_VMINNM_F16:
- case ARM64_INTRIN_VMINNM_F32:
- case ARM64_INTRIN_VMINNM_F64:
- case ARM64_INTRIN_VMINNMVQ_F64:
- case ARM64_INTRIN_VMINVQ_F64:
- case ARM64_INTRIN_VMOV_N_F16:
- case ARM64_INTRIN_VMOV_N_F32:
- case ARM64_INTRIN_VMOV_N_F64:
- case ARM64_INTRIN_VMUL_F16:
- case ARM64_INTRIN_VMUL_F32:
- case ARM64_INTRIN_VMUL_F64:
- case ARM64_INTRIN_VMUL_LANE_F16:
- case ARM64_INTRIN_VMUL_LANE_F32:
- case ARM64_INTRIN_VMUL_LANE_F64:
- case ARM64_INTRIN_VMUL_LANEQ_F16:
- case ARM64_INTRIN_VMUL_LANEQ_F32:
- case ARM64_INTRIN_VMUL_LANEQ_F64:
- case ARM64_INTRIN_VMUL_N_F16:
- case ARM64_INTRIN_VMUL_N_F32:
- case ARM64_INTRIN_VMUL_N_F64:
- case ARM64_INTRIN_VMULD_LANE_F64:
- case ARM64_INTRIN_VMULD_LANEQ_F64:
- case ARM64_INTRIN_VMULX_F16:
- case ARM64_INTRIN_VMULX_F32:
- case ARM64_INTRIN_VMULX_F64:
- case ARM64_INTRIN_VMULX_LANE_F16:
- case ARM64_INTRIN_VMULX_LANE_F32:
- case ARM64_INTRIN_VMULX_LANE_F64:
- case ARM64_INTRIN_VMULX_LANEQ_F16:
- case ARM64_INTRIN_VMULX_LANEQ_F32:
- case ARM64_INTRIN_VMULX_LANEQ_F64:
- case ARM64_INTRIN_VMULX_N_F16:
- case ARM64_INTRIN_VMULXD_F64:
- case ARM64_INTRIN_VMULXD_LANE_F64:
- case ARM64_INTRIN_VMULXD_LANEQ_F64:
- case ARM64_INTRIN_VNEG_F16:
- case ARM64_INTRIN_VNEG_F32:
- case ARM64_INTRIN_VNEG_F64:
- case ARM64_INTRIN_VPADD_F16:
- case ARM64_INTRIN_VPADD_F32:
- case ARM64_INTRIN_VPADDD_F64:
- case ARM64_INTRIN_VPMAX_F16:
- case ARM64_INTRIN_VPMAX_F32:
- case ARM64_INTRIN_VPMAXNM_F16:
- case ARM64_INTRIN_VPMAXNM_F32:
- case ARM64_INTRIN_VPMAXNMQD_F64:
- case ARM64_INTRIN_VPMAXQD_F64:
- case ARM64_INTRIN_VPMIN_F16:
- case ARM64_INTRIN_VPMIN_F32:
- case ARM64_INTRIN_VPMINNM_F16:
- case ARM64_INTRIN_VPMINNM_F32:
- case ARM64_INTRIN_VPMINNMQD_F64:
- case ARM64_INTRIN_VPMINQD_F64:
- case ARM64_INTRIN_VRECPE_F16:
- case ARM64_INTRIN_VRECPE_F32:
- case ARM64_INTRIN_VRECPE_F64:
- case ARM64_INTRIN_VRECPED_F64:
- case ARM64_INTRIN_VRECPS_F16:
- case ARM64_INTRIN_VRECPS_F32:
- case ARM64_INTRIN_VRECPS_F64:
- case ARM64_INTRIN_VRECPSD_F64:
- case ARM64_INTRIN_VRECPXD_F64:
- case ARM64_INTRIN_VREV64_F16:
- case ARM64_INTRIN_VREV64_F32:
- case ARM64_INTRIN_VRND32X_F32:
- case ARM64_INTRIN_VRND32X_F64:
- case ARM64_INTRIN_VRND32Z_F32:
- case ARM64_INTRIN_VRND32Z_F64:
- case ARM64_INTRIN_VRND64X_F32:
- case ARM64_INTRIN_VRND64X_F64:
- case ARM64_INTRIN_VRND64Z_F32:
- case ARM64_INTRIN_VRND64Z_F64:
- case ARM64_INTRIN_VRND_F16:
- case ARM64_INTRIN_VRND_F32:
- case ARM64_INTRIN_VRND_F64:
- case ARM64_INTRIN_VRNDA_F16:
- case ARM64_INTRIN_VRNDA_F32:
- case ARM64_INTRIN_VRNDA_F64:
- case ARM64_INTRIN_VRNDI_F16:
- case ARM64_INTRIN_VRNDI_F32:
- case ARM64_INTRIN_VRNDI_F64:
- case ARM64_INTRIN_VRNDM_F16:
- case ARM64_INTRIN_VRNDM_F32:
- case ARM64_INTRIN_VRNDM_F64:
- case ARM64_INTRIN_VRNDN_F16:
- case ARM64_INTRIN_VRNDN_F32:
- case ARM64_INTRIN_VRNDN_F64:
- case ARM64_INTRIN_VRNDP_F16:
- case ARM64_INTRIN_VRNDP_F32:
- case ARM64_INTRIN_VRNDP_F64:
- case ARM64_INTRIN_VRNDX_F16:
- case ARM64_INTRIN_VRNDX_F32:
- case ARM64_INTRIN_VRNDX_F64:
- case ARM64_INTRIN_VRSQRTE_F16:
- case ARM64_INTRIN_VRSQRTE_F32:
- case ARM64_INTRIN_VRSQRTE_F64:
- case ARM64_INTRIN_VRSQRTED_F64:
- case ARM64_INTRIN_VRSQRTS_F16:
- case ARM64_INTRIN_VRSQRTS_F32:
- case ARM64_INTRIN_VRSQRTS_F64:
- case ARM64_INTRIN_VRSQRTSD_F64:
- case ARM64_INTRIN_VSET_LANE_BF16:
- case ARM64_INTRIN_VSET_LANE_F16:
- case ARM64_INTRIN_VSET_LANE_F32:
- case ARM64_INTRIN_VSET_LANE_F64:
- case ARM64_INTRIN_VSQRT_F16:
- case ARM64_INTRIN_VSQRT_F32:
- case ARM64_INTRIN_VSQRT_F64:
- case ARM64_INTRIN_VSUB_F16:
- case ARM64_INTRIN_VSUB_F32:
- case ARM64_INTRIN_VSUB_F64:
- case ARM64_INTRIN_VTRN1_F16:
- case ARM64_INTRIN_VTRN1_F32:
- case ARM64_INTRIN_VTRN2_F16:
- case ARM64_INTRIN_VTRN2_F32:
- case ARM64_INTRIN_VUZP1_F16:
- case ARM64_INTRIN_VUZP1_F32:
- case ARM64_INTRIN_VUZP2_F16:
- case ARM64_INTRIN_VUZP2_F32:
- case ARM64_INTRIN_VZIP1_F16:
- case ARM64_INTRIN_VZIP1_F32:
- case ARM64_INTRIN_VZIP2_F16:
- case ARM64_INTRIN_VZIP2_F32:
- return {Type::FloatType(8)};
- case ARM64_INTRIN_VADDV_S8:
- case ARM64_INTRIN_VADDV_U8:
- case ARM64_INTRIN_VADDVQ_S8:
- case ARM64_INTRIN_VADDVQ_U8:
- case ARM64_INTRIN_VDUPB_LANE_P8:
- case ARM64_INTRIN_VDUPB_LANE_S8:
- case ARM64_INTRIN_VDUPB_LANE_U8:
- case ARM64_INTRIN_VDUPB_LANEQ_P8:
- case ARM64_INTRIN_VDUPB_LANEQ_S8:
- case ARM64_INTRIN_VDUPB_LANEQ_U8:
- case ARM64_INTRIN_VGET_LANE_P8:
- case ARM64_INTRIN_VGET_LANE_S8:
- case ARM64_INTRIN_VGET_LANE_U8:
- case ARM64_INTRIN_VGETQ_LANE_P8:
- case ARM64_INTRIN_VGETQ_LANE_S8:
- case ARM64_INTRIN_VGETQ_LANE_U8:
- case ARM64_INTRIN_VMAXV_S8:
- case ARM64_INTRIN_VMAXV_U8:
- case ARM64_INTRIN_VMAXVQ_S8:
- case ARM64_INTRIN_VMAXVQ_U8:
- case ARM64_INTRIN_VMINV_S8:
- case ARM64_INTRIN_VMINV_U8:
- case ARM64_INTRIN_VMINVQ_S8:
- case ARM64_INTRIN_VMINVQ_U8:
- case ARM64_INTRIN_VQABSB_S8:
- case ARM64_INTRIN_VQADDB_S8:
- case ARM64_INTRIN_VQADDB_U8:
- case ARM64_INTRIN_VQMOVNH_S16:
- case ARM64_INTRIN_VQMOVNH_U16:
- case ARM64_INTRIN_VQMOVUNH_S16:
- case ARM64_INTRIN_VQNEGB_S8:
- case ARM64_INTRIN_VQRSHLB_S8:
- case ARM64_INTRIN_VQRSHLB_U8:
- case ARM64_INTRIN_VQRSHRNH_N_S16:
- case ARM64_INTRIN_VQRSHRNH_N_U16:
- case ARM64_INTRIN_VQRSHRUNH_N_S16:
- case ARM64_INTRIN_VQSHLB_N_S8:
- case ARM64_INTRIN_VQSHLB_N_U8:
- case ARM64_INTRIN_VQSHLB_S8:
- case ARM64_INTRIN_VQSHLB_U8:
- case ARM64_INTRIN_VQSHLUB_N_S8:
- case ARM64_INTRIN_VQSHRNH_N_S16:
- case ARM64_INTRIN_VQSHRNH_N_U16:
- case ARM64_INTRIN_VQSHRUNH_N_S16:
- case ARM64_INTRIN_VQSUBB_S8:
- case ARM64_INTRIN_VQSUBB_U8:
- case ARM64_INTRIN_VSQADDB_U8:
- case ARM64_INTRIN_VUQADDB_S8:
- return {Type::IntegerType(1, false)};
- case ARM64_INTRIN_VABAL_HIGH_S16:
- case ARM64_INTRIN_VABAL_HIGH_S32:
- case ARM64_INTRIN_VABAL_HIGH_S8:
- case ARM64_INTRIN_VABAL_HIGH_U16:
- case ARM64_INTRIN_VABAL_HIGH_U32:
- case ARM64_INTRIN_VABAL_HIGH_U8:
- case ARM64_INTRIN_VABAL_S16:
- case ARM64_INTRIN_VABAL_S32:
- case ARM64_INTRIN_VABAL_S8:
- case ARM64_INTRIN_VABAL_U16:
- case ARM64_INTRIN_VABAL_U32:
- case ARM64_INTRIN_VABAL_U8:
- case ARM64_INTRIN_VABAQ_S16:
- case ARM64_INTRIN_VABAQ_S32:
- case ARM64_INTRIN_VABAQ_S8:
- case ARM64_INTRIN_VABAQ_U16:
- case ARM64_INTRIN_VABAQ_U32:
- case ARM64_INTRIN_VABAQ_U8:
- case ARM64_INTRIN_VABDL_HIGH_S16:
- case ARM64_INTRIN_VABDL_HIGH_S32:
- case ARM64_INTRIN_VABDL_HIGH_S8:
- case ARM64_INTRIN_VABDL_HIGH_U16:
- case ARM64_INTRIN_VABDL_HIGH_U32:
- case ARM64_INTRIN_VABDL_HIGH_U8:
- case ARM64_INTRIN_VABDL_S16:
- case ARM64_INTRIN_VABDL_S32:
- case ARM64_INTRIN_VABDL_S8:
- case ARM64_INTRIN_VABDL_U16:
- case ARM64_INTRIN_VABDL_U32:
- case ARM64_INTRIN_VABDL_U8:
- case ARM64_INTRIN_VABDQ_S16:
- case ARM64_INTRIN_VABDQ_S32:
- case ARM64_INTRIN_VABDQ_S8:
- case ARM64_INTRIN_VABDQ_U16:
- case ARM64_INTRIN_VABDQ_U32:
- case ARM64_INTRIN_VABDQ_U8:
- case ARM64_INTRIN_VABSQ_S16:
- case ARM64_INTRIN_VABSQ_S32:
- case ARM64_INTRIN_VABSQ_S64:
- case ARM64_INTRIN_VABSQ_S8:
- case ARM64_INTRIN_VADDHN_HIGH_S16:
- case ARM64_INTRIN_VADDHN_HIGH_S32:
- case ARM64_INTRIN_VADDHN_HIGH_S64:
- case ARM64_INTRIN_VADDHN_HIGH_U16:
- case ARM64_INTRIN_VADDHN_HIGH_U32:
- case ARM64_INTRIN_VADDHN_HIGH_U64:
- case ARM64_INTRIN_VADDL_HIGH_S16:
- case ARM64_INTRIN_VADDL_HIGH_S32:
- case ARM64_INTRIN_VADDL_HIGH_S8:
- case ARM64_INTRIN_VADDL_HIGH_U16:
- case ARM64_INTRIN_VADDL_HIGH_U32:
- case ARM64_INTRIN_VADDL_HIGH_U8:
- case ARM64_INTRIN_VADDL_S16:
- case ARM64_INTRIN_VADDL_S32:
- case ARM64_INTRIN_VADDL_S8:
- case ARM64_INTRIN_VADDL_U16:
- case ARM64_INTRIN_VADDL_U32:
- case ARM64_INTRIN_VADDL_U8:
- case ARM64_INTRIN_VADDQ_P128:
- case ARM64_INTRIN_VADDQ_P16:
- case ARM64_INTRIN_VADDQ_P64:
- case ARM64_INTRIN_VADDQ_P8:
- case ARM64_INTRIN_VADDQ_S16:
- case ARM64_INTRIN_VADDQ_S32:
- case ARM64_INTRIN_VADDQ_S64:
- case ARM64_INTRIN_VADDQ_S8:
- case ARM64_INTRIN_VADDQ_U16:
- case ARM64_INTRIN_VADDQ_U32:
- case ARM64_INTRIN_VADDQ_U64:
- case ARM64_INTRIN_VADDQ_U8:
- case ARM64_INTRIN_VADDW_HIGH_S16:
- case ARM64_INTRIN_VADDW_HIGH_S32:
- case ARM64_INTRIN_VADDW_HIGH_S8:
- case ARM64_INTRIN_VADDW_HIGH_U16:
- case ARM64_INTRIN_VADDW_HIGH_U32:
- case ARM64_INTRIN_VADDW_HIGH_U8:
- case ARM64_INTRIN_VADDW_S16:
- case ARM64_INTRIN_VADDW_S32:
- case ARM64_INTRIN_VADDW_S8:
- case ARM64_INTRIN_VADDW_U16:
- case ARM64_INTRIN_VADDW_U32:
- case ARM64_INTRIN_VADDW_U8:
- case ARM64_INTRIN_VAESDQ_U8:
- case ARM64_INTRIN_VAESEQ_U8:
- case ARM64_INTRIN_VAESIMCQ_U8:
- case ARM64_INTRIN_VAESMCQ_U8:
- case ARM64_INTRIN_VANDQ_S16:
- case ARM64_INTRIN_VANDQ_S32:
- case ARM64_INTRIN_VANDQ_S64:
- case ARM64_INTRIN_VANDQ_S8:
- case ARM64_INTRIN_VANDQ_U16:
- case ARM64_INTRIN_VANDQ_U32:
- case ARM64_INTRIN_VANDQ_U64:
- case ARM64_INTRIN_VANDQ_U8:
- case ARM64_INTRIN_VBCAXQ_S16:
- case ARM64_INTRIN_VBCAXQ_S32:
- case ARM64_INTRIN_VBCAXQ_S64:
- case ARM64_INTRIN_VBCAXQ_S8:
- case ARM64_INTRIN_VBCAXQ_U16:
- case ARM64_INTRIN_VBCAXQ_U32:
- case ARM64_INTRIN_VBCAXQ_U64:
- case ARM64_INTRIN_VBCAXQ_U8:
- case ARM64_INTRIN_VBICQ_S16:
- case ARM64_INTRIN_VBICQ_S32:
- case ARM64_INTRIN_VBICQ_S64:
- case ARM64_INTRIN_VBICQ_S8:
- case ARM64_INTRIN_VBICQ_U16:
- case ARM64_INTRIN_VBICQ_U32:
- case ARM64_INTRIN_VBICQ_U64:
- case ARM64_INTRIN_VBICQ_U8:
- case ARM64_INTRIN_VBSLQ_P16:
- case ARM64_INTRIN_VBSLQ_P64:
- case ARM64_INTRIN_VBSLQ_P8:
- case ARM64_INTRIN_VBSLQ_S16:
- case ARM64_INTRIN_VBSLQ_S32:
- case ARM64_INTRIN_VBSLQ_S64:
- case ARM64_INTRIN_VBSLQ_S8:
- case ARM64_INTRIN_VBSLQ_U16:
- case ARM64_INTRIN_VBSLQ_U32:
- case ARM64_INTRIN_VBSLQ_U64:
- case ARM64_INTRIN_VBSLQ_U8:
- case ARM64_INTRIN_VCAGEQ_F16:
- case ARM64_INTRIN_VCAGEQ_F32:
- case ARM64_INTRIN_VCAGEQ_F64:
- case ARM64_INTRIN_VCAGTQ_F16:
- case ARM64_INTRIN_VCAGTQ_F32:
- case ARM64_INTRIN_VCAGTQ_F64:
- case ARM64_INTRIN_VCALEQ_F16:
- case ARM64_INTRIN_VCALEQ_F32:
- case ARM64_INTRIN_VCALEQ_F64:
- case ARM64_INTRIN_VCALTQ_F16:
- case ARM64_INTRIN_VCALTQ_F32:
- case ARM64_INTRIN_VCALTQ_F64:
- case ARM64_INTRIN_VCEQQ_F16:
- case ARM64_INTRIN_VCEQQ_F32:
- case ARM64_INTRIN_VCEQQ_F64:
- case ARM64_INTRIN_VCEQQ_P64:
- case ARM64_INTRIN_VCEQQ_P8:
- case ARM64_INTRIN_VCEQQ_S16:
- case ARM64_INTRIN_VCEQQ_S32:
- case ARM64_INTRIN_VCEQQ_S64:
- case ARM64_INTRIN_VCEQQ_S8:
- case ARM64_INTRIN_VCEQQ_U16:
- case ARM64_INTRIN_VCEQQ_U32:
- case ARM64_INTRIN_VCEQQ_U64:
- case ARM64_INTRIN_VCEQQ_U8:
- case ARM64_INTRIN_VCEQZQ_F16:
- case ARM64_INTRIN_VCEQZQ_F32:
- case ARM64_INTRIN_VCEQZQ_F64:
- case ARM64_INTRIN_VCEQZQ_P64:
- case ARM64_INTRIN_VCEQZQ_P8:
- case ARM64_INTRIN_VCEQZQ_S16:
- case ARM64_INTRIN_VCEQZQ_S32:
- case ARM64_INTRIN_VCEQZQ_S64:
- case ARM64_INTRIN_VCEQZQ_S8:
- case ARM64_INTRIN_VCEQZQ_U16:
- case ARM64_INTRIN_VCEQZQ_U32:
- case ARM64_INTRIN_VCEQZQ_U64:
- case ARM64_INTRIN_VCEQZQ_U8:
- case ARM64_INTRIN_VCGEQ_F16:
- case ARM64_INTRIN_VCGEQ_F32:
- case ARM64_INTRIN_VCGEQ_F64:
- case ARM64_INTRIN_VCGEQ_S16:
- case ARM64_INTRIN_VCGEQ_S32:
- case ARM64_INTRIN_VCGEQ_S64:
- case ARM64_INTRIN_VCGEQ_S8:
- case ARM64_INTRIN_VCGEQ_U16:
- case ARM64_INTRIN_VCGEQ_U32:
- case ARM64_INTRIN_VCGEQ_U64:
- case ARM64_INTRIN_VCGEQ_U8:
- case ARM64_INTRIN_VCGEZQ_F16:
- case ARM64_INTRIN_VCGEZQ_F32:
- case ARM64_INTRIN_VCGEZQ_F64:
- case ARM64_INTRIN_VCGEZQ_S16:
- case ARM64_INTRIN_VCGEZQ_S32:
- case ARM64_INTRIN_VCGEZQ_S64:
- case ARM64_INTRIN_VCGEZQ_S8:
- case ARM64_INTRIN_VCGTQ_F16:
- case ARM64_INTRIN_VCGTQ_F32:
- case ARM64_INTRIN_VCGTQ_F64:
- case ARM64_INTRIN_VCGTQ_S16:
- case ARM64_INTRIN_VCGTQ_S32:
- case ARM64_INTRIN_VCGTQ_S64:
- case ARM64_INTRIN_VCGTQ_S8:
- case ARM64_INTRIN_VCGTQ_U16:
- case ARM64_INTRIN_VCGTQ_U32:
- case ARM64_INTRIN_VCGTQ_U64:
- case ARM64_INTRIN_VCGTQ_U8:
- case ARM64_INTRIN_VCGTZQ_F16:
- case ARM64_INTRIN_VCGTZQ_F32:
- case ARM64_INTRIN_VCGTZQ_F64:
- case ARM64_INTRIN_VCGTZQ_S16:
- case ARM64_INTRIN_VCGTZQ_S32:
- case ARM64_INTRIN_VCGTZQ_S64:
- case ARM64_INTRIN_VCGTZQ_S8:
- case ARM64_INTRIN_VCLEQ_F16:
- case ARM64_INTRIN_VCLEQ_F32:
- case ARM64_INTRIN_VCLEQ_F64:
- case ARM64_INTRIN_VCLEQ_S16:
- case ARM64_INTRIN_VCLEQ_S32:
- case ARM64_INTRIN_VCLEQ_S64:
- case ARM64_INTRIN_VCLEQ_S8:
- case ARM64_INTRIN_VCLEQ_U16:
- case ARM64_INTRIN_VCLEQ_U32:
- case ARM64_INTRIN_VCLEQ_U64:
- case ARM64_INTRIN_VCLEQ_U8:
- case ARM64_INTRIN_VCLEZQ_F16:
- case ARM64_INTRIN_VCLEZQ_F32:
- case ARM64_INTRIN_VCLEZQ_F64:
- case ARM64_INTRIN_VCLEZQ_S16:
- case ARM64_INTRIN_VCLEZQ_S32:
- case ARM64_INTRIN_VCLEZQ_S64:
- case ARM64_INTRIN_VCLEZQ_S8:
- case ARM64_INTRIN_VCLSQ_S16:
- case ARM64_INTRIN_VCLSQ_S32:
- case ARM64_INTRIN_VCLSQ_S8:
- case ARM64_INTRIN_VCLSQ_U16:
- case ARM64_INTRIN_VCLSQ_U32:
- case ARM64_INTRIN_VCLSQ_U8:
- case ARM64_INTRIN_VCLTQ_F16:
- case ARM64_INTRIN_VCLTQ_F32:
- case ARM64_INTRIN_VCLTQ_F64:
- case ARM64_INTRIN_VCLTQ_S16:
- case ARM64_INTRIN_VCLTQ_S32:
- case ARM64_INTRIN_VCLTQ_S64:
- case ARM64_INTRIN_VCLTQ_S8:
- case ARM64_INTRIN_VCLTQ_U16:
- case ARM64_INTRIN_VCLTQ_U32:
- case ARM64_INTRIN_VCLTQ_U64:
- case ARM64_INTRIN_VCLTQ_U8:
- case ARM64_INTRIN_VCLTZQ_F16:
- case ARM64_INTRIN_VCLTZQ_F32:
- case ARM64_INTRIN_VCLTZQ_F64:
- case ARM64_INTRIN_VCLTZQ_S16:
- case ARM64_INTRIN_VCLTZQ_S32:
- case ARM64_INTRIN_VCLTZQ_S64:
- case ARM64_INTRIN_VCLTZQ_S8:
- case ARM64_INTRIN_VCLZQ_S16:
- case ARM64_INTRIN_VCLZQ_S32:
- case ARM64_INTRIN_VCLZQ_S8:
- case ARM64_INTRIN_VCLZQ_U16:
- case ARM64_INTRIN_VCLZQ_U32:
- case ARM64_INTRIN_VCLZQ_U8:
- case ARM64_INTRIN_VCNTQ_P8:
- case ARM64_INTRIN_VCNTQ_S8:
- case ARM64_INTRIN_VCNTQ_U8:
- case ARM64_INTRIN_VCVTAQ_S16_F16:
- case ARM64_INTRIN_VCVTAQ_S32_F32:
- case ARM64_INTRIN_VCVTAQ_S64_F64:
- case ARM64_INTRIN_VCVTAQ_U16_F16:
- case ARM64_INTRIN_VCVTAQ_U32_F32:
- case ARM64_INTRIN_VCVTAQ_U64_F64:
- case ARM64_INTRIN_VCVTMQ_S16_F16:
- case ARM64_INTRIN_VCVTMQ_S32_F32:
- case ARM64_INTRIN_VCVTMQ_S64_F64:
- case ARM64_INTRIN_VCVTMQ_U16_F16:
- case ARM64_INTRIN_VCVTMQ_U32_F32:
- case ARM64_INTRIN_VCVTMQ_U64_F64:
- case ARM64_INTRIN_VCVTNQ_S16_F16:
- case ARM64_INTRIN_VCVTNQ_S32_F32:
- case ARM64_INTRIN_VCVTNQ_S64_F64:
- case ARM64_INTRIN_VCVTNQ_U16_F16:
- case ARM64_INTRIN_VCVTNQ_U32_F32:
- case ARM64_INTRIN_VCVTNQ_U64_F64:
- case ARM64_INTRIN_VCVTPQ_S16_F16:
- case ARM64_INTRIN_VCVTPQ_S32_F32:
- case ARM64_INTRIN_VCVTPQ_S64_F64:
- case ARM64_INTRIN_VCVTPQ_U16_F16:
- case ARM64_INTRIN_VCVTPQ_U32_F32:
- case ARM64_INTRIN_VCVTPQ_U64_F64:
- case ARM64_INTRIN_VCVTQ_N_S16_F16:
- case ARM64_INTRIN_VCVTQ_N_S32_F32:
- case ARM64_INTRIN_VCVTQ_N_S64_F64:
- case ARM64_INTRIN_VCVTQ_N_U16_F16:
- case ARM64_INTRIN_VCVTQ_N_U32_F32:
- case ARM64_INTRIN_VCVTQ_N_U64_F64:
- case ARM64_INTRIN_VCVTQ_S16_F16:
- case ARM64_INTRIN_VCVTQ_S32_F32:
- case ARM64_INTRIN_VCVTQ_S64_F64:
- case ARM64_INTRIN_VCVTQ_U16_F16:
- case ARM64_INTRIN_VCVTQ_U32_F32:
- case ARM64_INTRIN_VCVTQ_U64_F64:
- case ARM64_INTRIN_VDOTQ_LANEQ_S32:
- case ARM64_INTRIN_VDOTQ_LANEQ_U32:
- case ARM64_INTRIN_VDOTQ_LANE_S32:
- case ARM64_INTRIN_VDOTQ_LANE_U32:
- case ARM64_INTRIN_VDOTQ_S32:
- case ARM64_INTRIN_VDOTQ_U32:
- case ARM64_INTRIN_VDUPQ_LANEQ_P16:
- case ARM64_INTRIN_VDUPQ_LANEQ_P64:
- case ARM64_INTRIN_VDUPQ_LANEQ_P8:
- case ARM64_INTRIN_VDUPQ_LANEQ_S16:
- case ARM64_INTRIN_VDUPQ_LANEQ_S32:
- case ARM64_INTRIN_VDUPQ_LANEQ_S64:
- case ARM64_INTRIN_VDUPQ_LANEQ_S8:
- case ARM64_INTRIN_VDUPQ_LANEQ_U16:
- case ARM64_INTRIN_VDUPQ_LANEQ_U32:
- case ARM64_INTRIN_VDUPQ_LANEQ_U64:
- case ARM64_INTRIN_VDUPQ_LANEQ_U8:
- case ARM64_INTRIN_VDUPQ_LANE_P16:
- case ARM64_INTRIN_VDUPQ_LANE_P64:
- case ARM64_INTRIN_VDUPQ_LANE_P8:
- case ARM64_INTRIN_VDUPQ_LANE_S16:
- case ARM64_INTRIN_VDUPQ_LANE_S32:
- case ARM64_INTRIN_VDUPQ_LANE_S64:
- case ARM64_INTRIN_VDUPQ_LANE_S8:
- case ARM64_INTRIN_VDUPQ_LANE_U16:
- case ARM64_INTRIN_VDUPQ_LANE_U32:
- case ARM64_INTRIN_VDUPQ_LANE_U64:
- case ARM64_INTRIN_VDUPQ_LANE_U8:
- case ARM64_INTRIN_VDUPQ_N_P16:
- case ARM64_INTRIN_VDUPQ_N_P64:
- case ARM64_INTRIN_VDUPQ_N_P8:
- case ARM64_INTRIN_VDUPQ_N_S16:
- case ARM64_INTRIN_VDUPQ_N_S32:
- case ARM64_INTRIN_VDUPQ_N_S64:
- case ARM64_INTRIN_VDUPQ_N_S8:
- case ARM64_INTRIN_VDUPQ_N_U16:
- case ARM64_INTRIN_VDUPQ_N_U32:
- case ARM64_INTRIN_VDUPQ_N_U64:
- case ARM64_INTRIN_VDUPQ_N_U8:
- case ARM64_INTRIN_VEOR3Q_S16:
- case ARM64_INTRIN_VEOR3Q_S32:
- case ARM64_INTRIN_VEOR3Q_S64:
- case ARM64_INTRIN_VEOR3Q_S8:
- case ARM64_INTRIN_VEOR3Q_U16:
- case ARM64_INTRIN_VEOR3Q_U32:
- case ARM64_INTRIN_VEOR3Q_U64:
- case ARM64_INTRIN_VEOR3Q_U8:
- case ARM64_INTRIN_VEORQ_S16:
- case ARM64_INTRIN_VEORQ_S32:
- case ARM64_INTRIN_VEORQ_S64:
- case ARM64_INTRIN_VEORQ_S8:
- case ARM64_INTRIN_VEORQ_U16:
- case ARM64_INTRIN_VEORQ_U32:
- case ARM64_INTRIN_VEORQ_U64:
- case ARM64_INTRIN_VEORQ_U8:
- case ARM64_INTRIN_VEXTQ_P16:
- case ARM64_INTRIN_VEXTQ_P64:
- case ARM64_INTRIN_VEXTQ_P8:
- case ARM64_INTRIN_VEXTQ_S16:
- case ARM64_INTRIN_VEXTQ_S32:
- case ARM64_INTRIN_VEXTQ_S64:
- case ARM64_INTRIN_VEXTQ_S8:
- case ARM64_INTRIN_VEXTQ_U16:
- case ARM64_INTRIN_VEXTQ_U32:
- case ARM64_INTRIN_VEXTQ_U64:
- case ARM64_INTRIN_VEXTQ_U8:
- case ARM64_INTRIN_VHADDQ_S16:
- case ARM64_INTRIN_VHADDQ_S32:
- case ARM64_INTRIN_VHADDQ_S8:
- case ARM64_INTRIN_VHADDQ_U16:
- case ARM64_INTRIN_VHADDQ_U32:
- case ARM64_INTRIN_VHADDQ_U8:
- case ARM64_INTRIN_VHSUBQ_S16:
- case ARM64_INTRIN_VHSUBQ_S32:
- case ARM64_INTRIN_VHSUBQ_S8:
- case ARM64_INTRIN_VHSUBQ_U16:
- case ARM64_INTRIN_VHSUBQ_U32:
- case ARM64_INTRIN_VHSUBQ_U8:
- case ARM64_INTRIN_VLDRQ_P128:
- case ARM64_INTRIN_VMAXQ_S16:
- case ARM64_INTRIN_VMAXQ_S32:
- case ARM64_INTRIN_VMAXQ_S8:
- case ARM64_INTRIN_VMAXQ_U16:
- case ARM64_INTRIN_VMAXQ_U32:
- case ARM64_INTRIN_VMAXQ_U8:
- case ARM64_INTRIN_VMINQ_S16:
- case ARM64_INTRIN_VMINQ_S32:
- case ARM64_INTRIN_VMINQ_S8:
- case ARM64_INTRIN_VMINQ_U16:
- case ARM64_INTRIN_VMINQ_U32:
- case ARM64_INTRIN_VMINQ_U8:
- case ARM64_INTRIN_VMLAL_HIGH_LANEQ_S16:
- case ARM64_INTRIN_VMLAL_HIGH_LANEQ_S32:
- case ARM64_INTRIN_VMLAL_HIGH_LANEQ_U16:
- case ARM64_INTRIN_VMLAL_HIGH_LANEQ_U32:
- case ARM64_INTRIN_VMLAL_HIGH_LANE_S16:
- case ARM64_INTRIN_VMLAL_HIGH_LANE_S32:
- case ARM64_INTRIN_VMLAL_HIGH_LANE_U16:
- case ARM64_INTRIN_VMLAL_HIGH_LANE_U32:
- case ARM64_INTRIN_VMLAL_HIGH_N_S16:
- case ARM64_INTRIN_VMLAL_HIGH_N_S32:
- case ARM64_INTRIN_VMLAL_HIGH_N_U16:
- case ARM64_INTRIN_VMLAL_HIGH_N_U32:
- case ARM64_INTRIN_VMLAL_HIGH_S16:
- case ARM64_INTRIN_VMLAL_HIGH_S32:
- case ARM64_INTRIN_VMLAL_HIGH_S8:
- case ARM64_INTRIN_VMLAL_HIGH_U16:
- case ARM64_INTRIN_VMLAL_HIGH_U32:
- case ARM64_INTRIN_VMLAL_HIGH_U8:
- case ARM64_INTRIN_VMLAL_LANEQ_S16:
- case ARM64_INTRIN_VMLAL_LANEQ_S32:
- case ARM64_INTRIN_VMLAL_LANEQ_U16:
- case ARM64_INTRIN_VMLAL_LANEQ_U32:
- case ARM64_INTRIN_VMLAL_LANE_S16:
- case ARM64_INTRIN_VMLAL_LANE_S32:
- case ARM64_INTRIN_VMLAL_LANE_U16:
- case ARM64_INTRIN_VMLAL_LANE_U32:
- case ARM64_INTRIN_VMLAL_N_S16:
- case ARM64_INTRIN_VMLAL_N_S32:
- case ARM64_INTRIN_VMLAL_N_U16:
- case ARM64_INTRIN_VMLAL_N_U32:
- case ARM64_INTRIN_VMLAL_S16:
- case ARM64_INTRIN_VMLAL_S32:
- case ARM64_INTRIN_VMLAL_S8:
- case ARM64_INTRIN_VMLAL_U16:
- case ARM64_INTRIN_VMLAL_U32:
- case ARM64_INTRIN_VMLAL_U8:
- case ARM64_INTRIN_VMLAQ_LANEQ_S16:
- case ARM64_INTRIN_VMLAQ_LANEQ_S32:
- case ARM64_INTRIN_VMLAQ_LANEQ_U16:
- case ARM64_INTRIN_VMLAQ_LANEQ_U32:
- case ARM64_INTRIN_VMLAQ_LANE_S16:
- case ARM64_INTRIN_VMLAQ_LANE_S32:
- case ARM64_INTRIN_VMLAQ_LANE_U16:
- case ARM64_INTRIN_VMLAQ_LANE_U32:
- case ARM64_INTRIN_VMLAQ_N_S16:
- case ARM64_INTRIN_VMLAQ_N_S32:
- case ARM64_INTRIN_VMLAQ_N_U16:
- case ARM64_INTRIN_VMLAQ_N_U32:
- case ARM64_INTRIN_VMLAQ_S16:
- case ARM64_INTRIN_VMLAQ_S32:
- case ARM64_INTRIN_VMLAQ_S8:
- case ARM64_INTRIN_VMLAQ_U16:
- case ARM64_INTRIN_VMLAQ_U32:
- case ARM64_INTRIN_VMLAQ_U8:
- case ARM64_INTRIN_VMLSL_HIGH_LANEQ_S16:
- case ARM64_INTRIN_VMLSL_HIGH_LANEQ_S32:
- case ARM64_INTRIN_VMLSL_HIGH_LANEQ_U16:
- case ARM64_INTRIN_VMLSL_HIGH_LANEQ_U32:
- case ARM64_INTRIN_VMLSL_HIGH_LANE_S16:
- case ARM64_INTRIN_VMLSL_HIGH_LANE_S32:
- case ARM64_INTRIN_VMLSL_HIGH_LANE_U16:
- case ARM64_INTRIN_VMLSL_HIGH_LANE_U32:
- case ARM64_INTRIN_VMLSL_HIGH_N_S16:
- case ARM64_INTRIN_VMLSL_HIGH_N_S32:
- case ARM64_INTRIN_VMLSL_HIGH_N_U16:
- case ARM64_INTRIN_VMLSL_HIGH_N_U32:
- case ARM64_INTRIN_VMLSL_HIGH_S16:
- case ARM64_INTRIN_VMLSL_HIGH_S32:
- case ARM64_INTRIN_VMLSL_HIGH_S8:
- case ARM64_INTRIN_VMLSL_HIGH_U16:
- case ARM64_INTRIN_VMLSL_HIGH_U32:
- case ARM64_INTRIN_VMLSL_HIGH_U8:
- case ARM64_INTRIN_VMLSL_LANEQ_S16:
- case ARM64_INTRIN_VMLSL_LANEQ_S32:
- case ARM64_INTRIN_VMLSL_LANEQ_U16:
- case ARM64_INTRIN_VMLSL_LANEQ_U32:
- case ARM64_INTRIN_VMLSL_LANE_S16:
- case ARM64_INTRIN_VMLSL_LANE_S32:
- case ARM64_INTRIN_VMLSL_LANE_U16:
- case ARM64_INTRIN_VMLSL_LANE_U32:
- case ARM64_INTRIN_VMLSL_N_S16:
- case ARM64_INTRIN_VMLSL_N_S32:
- case ARM64_INTRIN_VMLSL_N_U16:
- case ARM64_INTRIN_VMLSL_N_U32:
- case ARM64_INTRIN_VMLSL_S16:
- case ARM64_INTRIN_VMLSL_S32:
- case ARM64_INTRIN_VMLSL_S8:
- case ARM64_INTRIN_VMLSL_U16:
- case ARM64_INTRIN_VMLSL_U32:
- case ARM64_INTRIN_VMLSL_U8:
- case ARM64_INTRIN_VMLSQ_LANEQ_S16:
- case ARM64_INTRIN_VMLSQ_LANEQ_S32:
- case ARM64_INTRIN_VMLSQ_LANEQ_U16:
- case ARM64_INTRIN_VMLSQ_LANEQ_U32:
- case ARM64_INTRIN_VMLSQ_LANE_S16:
- case ARM64_INTRIN_VMLSQ_LANE_S32:
- case ARM64_INTRIN_VMLSQ_LANE_U16:
- case ARM64_INTRIN_VMLSQ_LANE_U32:
- case ARM64_INTRIN_VMLSQ_N_S16:
- case ARM64_INTRIN_VMLSQ_N_S32:
- case ARM64_INTRIN_VMLSQ_N_U16:
- case ARM64_INTRIN_VMLSQ_N_U32:
- case ARM64_INTRIN_VMLSQ_S16:
- case ARM64_INTRIN_VMLSQ_S32:
- case ARM64_INTRIN_VMLSQ_S8:
- case ARM64_INTRIN_VMLSQ_U16:
- case ARM64_INTRIN_VMLSQ_U32:
- case ARM64_INTRIN_VMLSQ_U8:
- case ARM64_INTRIN_VMMLAQ_S32:
- case ARM64_INTRIN_VMMLAQ_U32:
- case ARM64_INTRIN_VMOVL_HIGH_S16:
- case ARM64_INTRIN_VMOVL_HIGH_S32:
- case ARM64_INTRIN_VMOVL_HIGH_S8:
- case ARM64_INTRIN_VMOVL_HIGH_U16:
- case ARM64_INTRIN_VMOVL_HIGH_U32:
- case ARM64_INTRIN_VMOVL_HIGH_U8:
- case ARM64_INTRIN_VMOVL_S16:
- case ARM64_INTRIN_VMOVL_S32:
- case ARM64_INTRIN_VMOVL_S8:
- case ARM64_INTRIN_VMOVL_U16:
- case ARM64_INTRIN_VMOVL_U32:
- case ARM64_INTRIN_VMOVL_U8:
- case ARM64_INTRIN_VMOVN_HIGH_S16:
- case ARM64_INTRIN_VMOVN_HIGH_S32:
- case ARM64_INTRIN_VMOVN_HIGH_S64:
- case ARM64_INTRIN_VMOVN_HIGH_U16:
- case ARM64_INTRIN_VMOVN_HIGH_U32:
- case ARM64_INTRIN_VMOVN_HIGH_U64:
- case ARM64_INTRIN_VMOVQ_N_P16:
- case ARM64_INTRIN_VMOVQ_N_P8:
- case ARM64_INTRIN_VMOVQ_N_S16:
- case ARM64_INTRIN_VMOVQ_N_S32:
- case ARM64_INTRIN_VMOVQ_N_S64:
- case ARM64_INTRIN_VMOVQ_N_S8:
- case ARM64_INTRIN_VMOVQ_N_U16:
- case ARM64_INTRIN_VMOVQ_N_U32:
- case ARM64_INTRIN_VMOVQ_N_U64:
- case ARM64_INTRIN_VMOVQ_N_U8:
- case ARM64_INTRIN_VMULL_HIGH_LANEQ_S16:
- case ARM64_INTRIN_VMULL_HIGH_LANEQ_S32:
- case ARM64_INTRIN_VMULL_HIGH_LANEQ_U16:
- case ARM64_INTRIN_VMULL_HIGH_LANEQ_U32:
- case ARM64_INTRIN_VMULL_HIGH_LANE_S16:
- case ARM64_INTRIN_VMULL_HIGH_LANE_S32:
- case ARM64_INTRIN_VMULL_HIGH_LANE_U16:
- case ARM64_INTRIN_VMULL_HIGH_LANE_U32:
- case ARM64_INTRIN_VMULL_HIGH_N_S16:
- case ARM64_INTRIN_VMULL_HIGH_N_S32:
- case ARM64_INTRIN_VMULL_HIGH_N_U16:
- case ARM64_INTRIN_VMULL_HIGH_N_U32:
- case ARM64_INTRIN_VMULL_HIGH_P64:
- case ARM64_INTRIN_VMULL_HIGH_P8:
- case ARM64_INTRIN_VMULL_HIGH_S16:
- case ARM64_INTRIN_VMULL_HIGH_S32:
- case ARM64_INTRIN_VMULL_HIGH_S8:
- case ARM64_INTRIN_VMULL_HIGH_U16:
- case ARM64_INTRIN_VMULL_HIGH_U32:
- case ARM64_INTRIN_VMULL_HIGH_U8:
- case ARM64_INTRIN_VMULL_LANEQ_S16:
- case ARM64_INTRIN_VMULL_LANEQ_S32:
- case ARM64_INTRIN_VMULL_LANEQ_U16:
- case ARM64_INTRIN_VMULL_LANEQ_U32:
- case ARM64_INTRIN_VMULL_LANE_S16:
- case ARM64_INTRIN_VMULL_LANE_S32:
- case ARM64_INTRIN_VMULL_LANE_U16:
- case ARM64_INTRIN_VMULL_LANE_U32:
- case ARM64_INTRIN_VMULL_N_S16:
- case ARM64_INTRIN_VMULL_N_S32:
- case ARM64_INTRIN_VMULL_N_U16:
- case ARM64_INTRIN_VMULL_N_U32:
- case ARM64_INTRIN_VMULL_P64:
- case ARM64_INTRIN_VMULL_P8:
- case ARM64_INTRIN_VMULL_S16:
- case ARM64_INTRIN_VMULL_S32:
- case ARM64_INTRIN_VMULL_S8:
- case ARM64_INTRIN_VMULL_U16:
- case ARM64_INTRIN_VMULL_U32:
- case ARM64_INTRIN_VMULL_U8:
- case ARM64_INTRIN_VMULQ_LANEQ_S16:
- case ARM64_INTRIN_VMULQ_LANEQ_S32:
- case ARM64_INTRIN_VMULQ_LANEQ_U16:
- case ARM64_INTRIN_VMULQ_LANEQ_U32:
- case ARM64_INTRIN_VMULQ_LANE_S16:
- case ARM64_INTRIN_VMULQ_LANE_S32:
- case ARM64_INTRIN_VMULQ_LANE_U16:
- case ARM64_INTRIN_VMULQ_LANE_U32:
- case ARM64_INTRIN_VMULQ_N_S16:
- case ARM64_INTRIN_VMULQ_N_S32:
- case ARM64_INTRIN_VMULQ_N_U16:
- case ARM64_INTRIN_VMULQ_N_U32:
- case ARM64_INTRIN_VMULQ_P8:
- case ARM64_INTRIN_VMULQ_S16:
- case ARM64_INTRIN_VMULQ_S32:
- case ARM64_INTRIN_VMULQ_S8:
- case ARM64_INTRIN_VMULQ_U16:
- case ARM64_INTRIN_VMULQ_U32:
- case ARM64_INTRIN_VMULQ_U8:
- case ARM64_INTRIN_VMVNQ_P8:
- case ARM64_INTRIN_VMVNQ_S16:
- case ARM64_INTRIN_VMVNQ_S32:
- case ARM64_INTRIN_VMVNQ_S8:
- case ARM64_INTRIN_VMVNQ_U16:
- case ARM64_INTRIN_VMVNQ_U32:
- case ARM64_INTRIN_VMVNQ_U8:
- case ARM64_INTRIN_VNEGQ_S16:
- case ARM64_INTRIN_VNEGQ_S32:
- case ARM64_INTRIN_VNEGQ_S64:
- case ARM64_INTRIN_VNEGQ_S8:
- case ARM64_INTRIN_VORNQ_S16:
- case ARM64_INTRIN_VORNQ_S32:
- case ARM64_INTRIN_VORNQ_S64:
- case ARM64_INTRIN_VORNQ_S8:
- case ARM64_INTRIN_VORNQ_U16:
- case ARM64_INTRIN_VORNQ_U32:
- case ARM64_INTRIN_VORNQ_U64:
- case ARM64_INTRIN_VORNQ_U8:
- case ARM64_INTRIN_VORRQ_S16:
- case ARM64_INTRIN_VORRQ_S32:
- case ARM64_INTRIN_VORRQ_S64:
- case ARM64_INTRIN_VORRQ_S8:
- case ARM64_INTRIN_VORRQ_U16:
- case ARM64_INTRIN_VORRQ_U32:
- case ARM64_INTRIN_VORRQ_U64:
- case ARM64_INTRIN_VORRQ_U8:
- case ARM64_INTRIN_VPADALQ_S16:
- case ARM64_INTRIN_VPADALQ_S32:
- case ARM64_INTRIN_VPADALQ_S8:
- case ARM64_INTRIN_VPADALQ_U16:
- case ARM64_INTRIN_VPADALQ_U32:
- case ARM64_INTRIN_VPADALQ_U8:
- case ARM64_INTRIN_VPADDLQ_S16:
- case ARM64_INTRIN_VPADDLQ_S32:
- case ARM64_INTRIN_VPADDLQ_S8:
- case ARM64_INTRIN_VPADDLQ_U16:
- case ARM64_INTRIN_VPADDLQ_U32:
- case ARM64_INTRIN_VPADDLQ_U8:
- case ARM64_INTRIN_VPADDQ_S16:
- case ARM64_INTRIN_VPADDQ_S32:
- case ARM64_INTRIN_VPADDQ_S64:
- case ARM64_INTRIN_VPADDQ_S8:
- case ARM64_INTRIN_VPADDQ_U16:
- case ARM64_INTRIN_VPADDQ_U32:
- case ARM64_INTRIN_VPADDQ_U64:
- case ARM64_INTRIN_VPADDQ_U8:
- case ARM64_INTRIN_VPMAXQ_S16:
- case ARM64_INTRIN_VPMAXQ_S32:
- case ARM64_INTRIN_VPMAXQ_S8:
- case ARM64_INTRIN_VPMAXQ_U16:
- case ARM64_INTRIN_VPMAXQ_U32:
- case ARM64_INTRIN_VPMAXQ_U8:
- case ARM64_INTRIN_VPMINQ_S16:
- case ARM64_INTRIN_VPMINQ_S32:
- case ARM64_INTRIN_VPMINQ_S8:
- case ARM64_INTRIN_VPMINQ_U16:
- case ARM64_INTRIN_VPMINQ_U32:
- case ARM64_INTRIN_VPMINQ_U8:
- case ARM64_INTRIN_VQABSQ_S16:
- case ARM64_INTRIN_VQABSQ_S32:
- case ARM64_INTRIN_VQABSQ_S64:
- case ARM64_INTRIN_VQABSQ_S8:
- case ARM64_INTRIN_VQADDQ_S16:
- case ARM64_INTRIN_VQADDQ_S32:
- case ARM64_INTRIN_VQADDQ_S64:
- case ARM64_INTRIN_VQADDQ_S8:
- case ARM64_INTRIN_VQADDQ_U16:
- case ARM64_INTRIN_VQADDQ_U32:
- case ARM64_INTRIN_VQADDQ_U64:
- case ARM64_INTRIN_VQADDQ_U8:
- case ARM64_INTRIN_VQDMLAL_HIGH_LANEQ_S16:
- case ARM64_INTRIN_VQDMLAL_HIGH_LANEQ_S32:
- case ARM64_INTRIN_VQDMLAL_HIGH_LANE_S16:
- case ARM64_INTRIN_VQDMLAL_HIGH_LANE_S32:
- case ARM64_INTRIN_VQDMLAL_HIGH_N_S16:
- case ARM64_INTRIN_VQDMLAL_HIGH_N_S32:
- case ARM64_INTRIN_VQDMLAL_HIGH_S16:
- case ARM64_INTRIN_VQDMLAL_HIGH_S32:
- case ARM64_INTRIN_VQDMLAL_LANEQ_S16:
- case ARM64_INTRIN_VQDMLAL_LANEQ_S32:
- case ARM64_INTRIN_VQDMLAL_LANE_S16:
- case ARM64_INTRIN_VQDMLAL_LANE_S32:
- case ARM64_INTRIN_VQDMLAL_N_S16:
- case ARM64_INTRIN_VQDMLAL_N_S32:
- case ARM64_INTRIN_VQDMLAL_S16:
- case ARM64_INTRIN_VQDMLAL_S32:
- case ARM64_INTRIN_VQDMLSL_HIGH_LANEQ_S16:
- case ARM64_INTRIN_VQDMLSL_HIGH_LANEQ_S32:
- case ARM64_INTRIN_VQDMLSL_HIGH_LANE_S16:
- case ARM64_INTRIN_VQDMLSL_HIGH_LANE_S32:
- case ARM64_INTRIN_VQDMLSL_HIGH_N_S16:
- case ARM64_INTRIN_VQDMLSL_HIGH_N_S32:
- case ARM64_INTRIN_VQDMLSL_HIGH_S16:
- case ARM64_INTRIN_VQDMLSL_HIGH_S32:
- case ARM64_INTRIN_VQDMLSL_LANEQ_S16:
- case ARM64_INTRIN_VQDMLSL_LANEQ_S32:
- case ARM64_INTRIN_VQDMLSL_LANE_S16:
- case ARM64_INTRIN_VQDMLSL_LANE_S32:
- case ARM64_INTRIN_VQDMLSL_N_S16:
- case ARM64_INTRIN_VQDMLSL_N_S32:
- case ARM64_INTRIN_VQDMLSL_S16:
- case ARM64_INTRIN_VQDMLSL_S32:
- case ARM64_INTRIN_VQDMULHQ_LANEQ_S16:
- case ARM64_INTRIN_VQDMULHQ_LANEQ_S32:
- case ARM64_INTRIN_VQDMULHQ_LANE_S16:
- case ARM64_INTRIN_VQDMULHQ_LANE_S32:
- case ARM64_INTRIN_VQDMULHQ_N_S16:
- case ARM64_INTRIN_VQDMULHQ_N_S32:
- case ARM64_INTRIN_VQDMULHQ_S16:
- case ARM64_INTRIN_VQDMULHQ_S32:
- case ARM64_INTRIN_VQDMULL_HIGH_LANEQ_S16:
- case ARM64_INTRIN_VQDMULL_HIGH_LANEQ_S32:
- case ARM64_INTRIN_VQDMULL_HIGH_LANE_S16:
- case ARM64_INTRIN_VQDMULL_HIGH_LANE_S32:
- case ARM64_INTRIN_VQDMULL_HIGH_N_S16:
- case ARM64_INTRIN_VQDMULL_HIGH_N_S32:
- case ARM64_INTRIN_VQDMULL_HIGH_S16:
- case ARM64_INTRIN_VQDMULL_HIGH_S32:
- case ARM64_INTRIN_VQDMULL_LANEQ_S16:
- case ARM64_INTRIN_VQDMULL_LANEQ_S32:
- case ARM64_INTRIN_VQDMULL_LANE_S16:
- case ARM64_INTRIN_VQDMULL_LANE_S32:
- case ARM64_INTRIN_VQDMULL_N_S16:
- case ARM64_INTRIN_VQDMULL_N_S32:
- case ARM64_INTRIN_VQDMULL_S16:
- case ARM64_INTRIN_VQDMULL_S32:
- case ARM64_INTRIN_VQMOVN_HIGH_S16:
- case ARM64_INTRIN_VQMOVN_HIGH_S32:
- case ARM64_INTRIN_VQMOVN_HIGH_S64:
- case ARM64_INTRIN_VQMOVN_HIGH_U16:
- case ARM64_INTRIN_VQMOVN_HIGH_U32:
- case ARM64_INTRIN_VQMOVN_HIGH_U64:
- case ARM64_INTRIN_VQMOVUN_HIGH_S16:
- case ARM64_INTRIN_VQMOVUN_HIGH_S32:
- case ARM64_INTRIN_VQMOVUN_HIGH_S64:
- case ARM64_INTRIN_VQNEGQ_S16:
- case ARM64_INTRIN_VQNEGQ_S32:
- case ARM64_INTRIN_VQNEGQ_S64:
- case ARM64_INTRIN_VQNEGQ_S8:
- case ARM64_INTRIN_VQRDMLAHQ_LANEQ_S16:
- case ARM64_INTRIN_VQRDMLAHQ_LANEQ_S32:
- case ARM64_INTRIN_VQRDMLAHQ_LANE_S16:
- case ARM64_INTRIN_VQRDMLAHQ_LANE_S32:
- case ARM64_INTRIN_VQRDMLAHQ_S16:
- case ARM64_INTRIN_VQRDMLAHQ_S32:
- case ARM64_INTRIN_VQRDMLSHQ_LANEQ_S16:
- case ARM64_INTRIN_VQRDMLSHQ_LANEQ_S32:
- case ARM64_INTRIN_VQRDMLSHQ_LANE_S16:
- case ARM64_INTRIN_VQRDMLSHQ_LANE_S32:
- case ARM64_INTRIN_VQRDMLSHQ_S16:
- case ARM64_INTRIN_VQRDMLSHQ_S32:
- case ARM64_INTRIN_VQRDMULHQ_LANEQ_S16:
- case ARM64_INTRIN_VQRDMULHQ_LANEQ_S32:
- case ARM64_INTRIN_VQRDMULHQ_LANE_S16:
- case ARM64_INTRIN_VQRDMULHQ_LANE_S32:
- case ARM64_INTRIN_VQRDMULHQ_N_S16:
- case ARM64_INTRIN_VQRDMULHQ_N_S32:
- case ARM64_INTRIN_VQRDMULHQ_S16:
- case ARM64_INTRIN_VQRDMULHQ_S32:
- case ARM64_INTRIN_VQRSHLQ_S16:
- case ARM64_INTRIN_VQRSHLQ_S32:
- case ARM64_INTRIN_VQRSHLQ_S64:
- case ARM64_INTRIN_VQRSHLQ_S8:
- case ARM64_INTRIN_VQRSHLQ_U16:
- case ARM64_INTRIN_VQRSHLQ_U32:
- case ARM64_INTRIN_VQRSHLQ_U64:
- case ARM64_INTRIN_VQRSHLQ_U8:
- case ARM64_INTRIN_VQRSHRN_HIGH_N_S16:
- case ARM64_INTRIN_VQRSHRN_HIGH_N_S32:
- case ARM64_INTRIN_VQRSHRN_HIGH_N_S64:
- case ARM64_INTRIN_VQRSHRN_HIGH_N_U16:
- case ARM64_INTRIN_VQRSHRN_HIGH_N_U32:
- case ARM64_INTRIN_VQRSHRN_HIGH_N_U64:
- case ARM64_INTRIN_VQRSHRUN_HIGH_N_S16:
- case ARM64_INTRIN_VQRSHRUN_HIGH_N_S32:
- case ARM64_INTRIN_VQRSHRUN_HIGH_N_S64:
- case ARM64_INTRIN_VQSHLQ_N_S16:
- case ARM64_INTRIN_VQSHLQ_N_S32:
- case ARM64_INTRIN_VQSHLQ_N_S64:
- case ARM64_INTRIN_VQSHLQ_N_S8:
- case ARM64_INTRIN_VQSHLQ_N_U16:
- case ARM64_INTRIN_VQSHLQ_N_U32:
- case ARM64_INTRIN_VQSHLQ_N_U64:
- case ARM64_INTRIN_VQSHLQ_N_U8:
- case ARM64_INTRIN_VQSHLQ_S16:
- case ARM64_INTRIN_VQSHLQ_S32:
- case ARM64_INTRIN_VQSHLQ_S64:
- case ARM64_INTRIN_VQSHLQ_S8:
- case ARM64_INTRIN_VQSHLQ_U16:
- case ARM64_INTRIN_VQSHLQ_U32:
- case ARM64_INTRIN_VQSHLQ_U64:
- case ARM64_INTRIN_VQSHLQ_U8:
- case ARM64_INTRIN_VQSHLUQ_N_S16:
- case ARM64_INTRIN_VQSHLUQ_N_S32:
- case ARM64_INTRIN_VQSHLUQ_N_S64:
- case ARM64_INTRIN_VQSHLUQ_N_S8:
- case ARM64_INTRIN_VQSHRN_HIGH_N_S16:
- case ARM64_INTRIN_VQSHRN_HIGH_N_S32:
- case ARM64_INTRIN_VQSHRN_HIGH_N_S64:
- case ARM64_INTRIN_VQSHRN_HIGH_N_U16:
- case ARM64_INTRIN_VQSHRN_HIGH_N_U32:
- case ARM64_INTRIN_VQSHRN_HIGH_N_U64:
- case ARM64_INTRIN_VQSHRUN_HIGH_N_S16:
- case ARM64_INTRIN_VQSHRUN_HIGH_N_S32:
- case ARM64_INTRIN_VQSHRUN_HIGH_N_S64:
- case ARM64_INTRIN_VQSUBQ_S16:
- case ARM64_INTRIN_VQSUBQ_S32:
- case ARM64_INTRIN_VQSUBQ_S64:
- case ARM64_INTRIN_VQSUBQ_S8:
- case ARM64_INTRIN_VQSUBQ_U16:
- case ARM64_INTRIN_VQSUBQ_U32:
- case ARM64_INTRIN_VQSUBQ_U64:
- case ARM64_INTRIN_VQSUBQ_U8:
- case ARM64_INTRIN_VRADDHN_HIGH_S16:
- case ARM64_INTRIN_VRADDHN_HIGH_S32:
- case ARM64_INTRIN_VRADDHN_HIGH_S64:
- case ARM64_INTRIN_VRADDHN_HIGH_U16:
- case ARM64_INTRIN_VRADDHN_HIGH_U32:
- case ARM64_INTRIN_VRADDHN_HIGH_U64:
- case ARM64_INTRIN_VRAX1Q_U64:
- case ARM64_INTRIN_VRBITQ_P8:
- case ARM64_INTRIN_VRBITQ_S8:
- case ARM64_INTRIN_VRBITQ_U8:
- case ARM64_INTRIN_VRECPEQ_U32:
- case ARM64_INTRIN_VREV16Q_P8:
- case ARM64_INTRIN_VREV16Q_S8:
- case ARM64_INTRIN_VREV16Q_U8:
- case ARM64_INTRIN_VREV32Q_P16:
- case ARM64_INTRIN_VREV32Q_P8:
- case ARM64_INTRIN_VREV32Q_S16:
- case ARM64_INTRIN_VREV32Q_S8:
- case ARM64_INTRIN_VREV32Q_U16:
- case ARM64_INTRIN_VREV32Q_U8:
- case ARM64_INTRIN_VREV64Q_P16:
- case ARM64_INTRIN_VREV64Q_P8:
- case ARM64_INTRIN_VREV64Q_S16:
- case ARM64_INTRIN_VREV64Q_S32:
- case ARM64_INTRIN_VREV64Q_S8:
- case ARM64_INTRIN_VREV64Q_U16:
- case ARM64_INTRIN_VREV64Q_U32:
- case ARM64_INTRIN_VREV64Q_U8:
- case ARM64_INTRIN_VRHADDQ_S16:
- case ARM64_INTRIN_VRHADDQ_S32:
- case ARM64_INTRIN_VRHADDQ_S8:
- case ARM64_INTRIN_VRHADDQ_U16:
- case ARM64_INTRIN_VRHADDQ_U32:
- case ARM64_INTRIN_VRHADDQ_U8:
- case ARM64_INTRIN_VRSHLQ_S16:
- case ARM64_INTRIN_VRSHLQ_S32:
- case ARM64_INTRIN_VRSHLQ_S64:
- case ARM64_INTRIN_VRSHLQ_S8:
- case ARM64_INTRIN_VRSHLQ_U16:
- case ARM64_INTRIN_VRSHLQ_U32:
- case ARM64_INTRIN_VRSHLQ_U64:
- case ARM64_INTRIN_VRSHLQ_U8:
- case ARM64_INTRIN_VRSHRN_HIGH_N_S16:
- case ARM64_INTRIN_VRSHRN_HIGH_N_S32:
- case ARM64_INTRIN_VRSHRN_HIGH_N_S64:
- case ARM64_INTRIN_VRSHRN_HIGH_N_U16:
- case ARM64_INTRIN_VRSHRN_HIGH_N_U32:
- case ARM64_INTRIN_VRSHRN_HIGH_N_U64:
- case ARM64_INTRIN_VRSHRQ_N_S16:
- case ARM64_INTRIN_VRSHRQ_N_S32:
- case ARM64_INTRIN_VRSHRQ_N_S64:
- case ARM64_INTRIN_VRSHRQ_N_S8:
- case ARM64_INTRIN_VRSHRQ_N_U16:
- case ARM64_INTRIN_VRSHRQ_N_U32:
- case ARM64_INTRIN_VRSHRQ_N_U64:
- case ARM64_INTRIN_VRSHRQ_N_U8:
- case ARM64_INTRIN_VRSQRTEQ_U32:
- case ARM64_INTRIN_VRSRAQ_N_S16:
- case ARM64_INTRIN_VRSRAQ_N_S32:
- case ARM64_INTRIN_VRSRAQ_N_S64:
- case ARM64_INTRIN_VRSRAQ_N_S8:
- case ARM64_INTRIN_VRSRAQ_N_U16:
- case ARM64_INTRIN_VRSRAQ_N_U32:
- case ARM64_INTRIN_VRSRAQ_N_U64:
- case ARM64_INTRIN_VRSRAQ_N_U8:
- case ARM64_INTRIN_VRSUBHN_HIGH_S16:
- case ARM64_INTRIN_VRSUBHN_HIGH_S32:
- case ARM64_INTRIN_VRSUBHN_HIGH_S64:
- case ARM64_INTRIN_VRSUBHN_HIGH_U16:
- case ARM64_INTRIN_VRSUBHN_HIGH_U32:
- case ARM64_INTRIN_VRSUBHN_HIGH_U64:
- case ARM64_INTRIN_VSETQ_LANE_P16:
- case ARM64_INTRIN_VSETQ_LANE_P64:
- case ARM64_INTRIN_VSETQ_LANE_P8:
- case ARM64_INTRIN_VSETQ_LANE_S16:
- case ARM64_INTRIN_VSETQ_LANE_S32:
- case ARM64_INTRIN_VSETQ_LANE_S64:
- case ARM64_INTRIN_VSETQ_LANE_S8:
- case ARM64_INTRIN_VSETQ_LANE_U16:
- case ARM64_INTRIN_VSETQ_LANE_U32:
- case ARM64_INTRIN_VSETQ_LANE_U64:
- case ARM64_INTRIN_VSETQ_LANE_U8:
- case ARM64_INTRIN_VSHA1CQ_U32:
- case ARM64_INTRIN_VSHA1MQ_U32:
- case ARM64_INTRIN_VSHA1PQ_U32:
- case ARM64_INTRIN_VSHA1SU0Q_U32:
- case ARM64_INTRIN_VSHA1SU1Q_U32:
- case ARM64_INTRIN_VSHA256H2Q_U32:
- case ARM64_INTRIN_VSHA256HQ_U32:
- case ARM64_INTRIN_VSHA256SU0Q_U32:
- case ARM64_INTRIN_VSHA256SU1Q_U32:
- case ARM64_INTRIN_VSHA512H2Q_U64:
- case ARM64_INTRIN_VSHA512HQ_U64:
- case ARM64_INTRIN_VSHA512SU0Q_U64:
- case ARM64_INTRIN_VSHA512SU1Q_U64:
- case ARM64_INTRIN_VSHLL_HIGH_N_S16:
- case ARM64_INTRIN_VSHLL_HIGH_N_S32:
- case ARM64_INTRIN_VSHLL_HIGH_N_S8:
- case ARM64_INTRIN_VSHLL_HIGH_N_U16:
- case ARM64_INTRIN_VSHLL_HIGH_N_U32:
- case ARM64_INTRIN_VSHLL_HIGH_N_U8:
- case ARM64_INTRIN_VSHLL_N_S16:
- case ARM64_INTRIN_VSHLL_N_S32:
- case ARM64_INTRIN_VSHLL_N_S8:
- case ARM64_INTRIN_VSHLL_N_U16:
- case ARM64_INTRIN_VSHLL_N_U32:
- case ARM64_INTRIN_VSHLL_N_U8:
- case ARM64_INTRIN_VSHLQ_N_S16:
- case ARM64_INTRIN_VSHLQ_N_S32:
- case ARM64_INTRIN_VSHLQ_N_S64:
- case ARM64_INTRIN_VSHLQ_N_S8:
- case ARM64_INTRIN_VSHLQ_N_U16:
- case ARM64_INTRIN_VSHLQ_N_U32:
- case ARM64_INTRIN_VSHLQ_N_U64:
- case ARM64_INTRIN_VSHLQ_N_U8:
- case ARM64_INTRIN_VSHLQ_S16:
- case ARM64_INTRIN_VSHLQ_S32:
- case ARM64_INTRIN_VSHLQ_S64:
- case ARM64_INTRIN_VSHLQ_S8:
- case ARM64_INTRIN_VSHLQ_U16:
- case ARM64_INTRIN_VSHLQ_U32:
- case ARM64_INTRIN_VSHLQ_U64:
- case ARM64_INTRIN_VSHLQ_U8:
- case ARM64_INTRIN_VSHRN_HIGH_N_S16:
- case ARM64_INTRIN_VSHRN_HIGH_N_S32:
- case ARM64_INTRIN_VSHRN_HIGH_N_S64:
- case ARM64_INTRIN_VSHRN_HIGH_N_U16:
- case ARM64_INTRIN_VSHRN_HIGH_N_U32:
- case ARM64_INTRIN_VSHRN_HIGH_N_U64:
- case ARM64_INTRIN_VSHRQ_N_S16:
- case ARM64_INTRIN_VSHRQ_N_S32:
- case ARM64_INTRIN_VSHRQ_N_S64:
- case ARM64_INTRIN_VSHRQ_N_S8:
- case ARM64_INTRIN_VSHRQ_N_U16:
- case ARM64_INTRIN_VSHRQ_N_U32:
- case ARM64_INTRIN_VSHRQ_N_U64:
- case ARM64_INTRIN_VSHRQ_N_U8:
- case ARM64_INTRIN_VSLIQ_N_P16:
- case ARM64_INTRIN_VSLIQ_N_P64:
- case ARM64_INTRIN_VSLIQ_N_P8:
- case ARM64_INTRIN_VSLIQ_N_S16:
- case ARM64_INTRIN_VSLIQ_N_S32:
- case ARM64_INTRIN_VSLIQ_N_S64:
- case ARM64_INTRIN_VSLIQ_N_S8:
- case ARM64_INTRIN_VSLIQ_N_U16:
- case ARM64_INTRIN_VSLIQ_N_U32:
- case ARM64_INTRIN_VSLIQ_N_U64:
- case ARM64_INTRIN_VSLIQ_N_U8:
- case ARM64_INTRIN_VSM3PARTW1Q_U32:
- case ARM64_INTRIN_VSM3PARTW2Q_U32:
- case ARM64_INTRIN_VSM3SS1Q_U32:
- case ARM64_INTRIN_VSM3TT1AQ_U32:
- case ARM64_INTRIN_VSM3TT1BQ_U32:
- case ARM64_INTRIN_VSM3TT2AQ_U32:
- case ARM64_INTRIN_VSM3TT2BQ_U32:
- case ARM64_INTRIN_VSM4EKEYQ_U32:
- case ARM64_INTRIN_VSM4EQ_U32:
- case ARM64_INTRIN_VSQADDQ_U16:
- case ARM64_INTRIN_VSQADDQ_U32:
- case ARM64_INTRIN_VSQADDQ_U64:
- case ARM64_INTRIN_VSQADDQ_U8:
- case ARM64_INTRIN_VSRAQ_N_S16:
- case ARM64_INTRIN_VSRAQ_N_S32:
- case ARM64_INTRIN_VSRAQ_N_S64:
- case ARM64_INTRIN_VSRAQ_N_S8:
- case ARM64_INTRIN_VSRAQ_N_U16:
- case ARM64_INTRIN_VSRAQ_N_U32:
- case ARM64_INTRIN_VSRAQ_N_U64:
- case ARM64_INTRIN_VSRAQ_N_U8:
- case ARM64_INTRIN_VSRIQ_N_P16:
- case ARM64_INTRIN_VSRIQ_N_P64:
- case ARM64_INTRIN_VSRIQ_N_P8:
- case ARM64_INTRIN_VSRIQ_N_S16:
- case ARM64_INTRIN_VSRIQ_N_S32:
- case ARM64_INTRIN_VSRIQ_N_S64:
- case ARM64_INTRIN_VSRIQ_N_S8:
- case ARM64_INTRIN_VSRIQ_N_U16:
- case ARM64_INTRIN_VSRIQ_N_U32:
- case ARM64_INTRIN_VSRIQ_N_U64:
- case ARM64_INTRIN_VSRIQ_N_U8:
- case ARM64_INTRIN_VSUBHN_HIGH_S16:
- case ARM64_INTRIN_VSUBHN_HIGH_S32:
- case ARM64_INTRIN_VSUBHN_HIGH_S64:
- case ARM64_INTRIN_VSUBHN_HIGH_U16:
- case ARM64_INTRIN_VSUBHN_HIGH_U32:
- case ARM64_INTRIN_VSUBHN_HIGH_U64:
- case ARM64_INTRIN_VSUBL_HIGH_S16:
- case ARM64_INTRIN_VSUBL_HIGH_S32:
- case ARM64_INTRIN_VSUBL_HIGH_S8:
- case ARM64_INTRIN_VSUBL_HIGH_U16:
- case ARM64_INTRIN_VSUBL_HIGH_U32:
- case ARM64_INTRIN_VSUBL_HIGH_U8:
- case ARM64_INTRIN_VSUBL_S16:
- case ARM64_INTRIN_VSUBL_S32:
- case ARM64_INTRIN_VSUBL_S8:
- case ARM64_INTRIN_VSUBL_U16:
- case ARM64_INTRIN_VSUBL_U32:
- case ARM64_INTRIN_VSUBL_U8:
- case ARM64_INTRIN_VSUBQ_S16:
- case ARM64_INTRIN_VSUBQ_S32:
- case ARM64_INTRIN_VSUBQ_S64:
- case ARM64_INTRIN_VSUBQ_S8:
- case ARM64_INTRIN_VSUBQ_U16:
- case ARM64_INTRIN_VSUBQ_U32:
- case ARM64_INTRIN_VSUBQ_U64:
- case ARM64_INTRIN_VSUBQ_U8:
- case ARM64_INTRIN_VSUBW_HIGH_S16:
- case ARM64_INTRIN_VSUBW_HIGH_S32:
- case ARM64_INTRIN_VSUBW_HIGH_S8:
- case ARM64_INTRIN_VSUBW_HIGH_U16:
- case ARM64_INTRIN_VSUBW_HIGH_U32:
- case ARM64_INTRIN_VSUBW_HIGH_U8:
- case ARM64_INTRIN_VSUBW_S16:
- case ARM64_INTRIN_VSUBW_S32:
- case ARM64_INTRIN_VSUBW_S8:
- case ARM64_INTRIN_VSUBW_U16:
- case ARM64_INTRIN_VSUBW_U32:
- case ARM64_INTRIN_VSUBW_U8:
- case ARM64_INTRIN_VSUDOTQ_LANEQ_S32:
- case ARM64_INTRIN_VSUDOTQ_LANE_S32:
- case ARM64_INTRIN_VTRN1Q_P16:
- case ARM64_INTRIN_VTRN1Q_P64:
- case ARM64_INTRIN_VTRN1Q_P8:
- case ARM64_INTRIN_VTRN1Q_S16:
- case ARM64_INTRIN_VTRN1Q_S32:
- case ARM64_INTRIN_VTRN1Q_S64:
- case ARM64_INTRIN_VTRN1Q_S8:
- case ARM64_INTRIN_VTRN1Q_U16:
- case ARM64_INTRIN_VTRN1Q_U32:
- case ARM64_INTRIN_VTRN1Q_U64:
- case ARM64_INTRIN_VTRN1Q_U8:
- case ARM64_INTRIN_VTRN2Q_P16:
- case ARM64_INTRIN_VTRN2Q_P64:
- case ARM64_INTRIN_VTRN2Q_P8:
- case ARM64_INTRIN_VTRN2Q_S16:
- case ARM64_INTRIN_VTRN2Q_S32:
- case ARM64_INTRIN_VTRN2Q_S64:
- case ARM64_INTRIN_VTRN2Q_S8:
- case ARM64_INTRIN_VTRN2Q_U16:
- case ARM64_INTRIN_VTRN2Q_U32:
- case ARM64_INTRIN_VTRN2Q_U64:
- case ARM64_INTRIN_VTRN2Q_U8:
- case ARM64_INTRIN_VTSTQ_P64:
- case ARM64_INTRIN_VTSTQ_P8:
- case ARM64_INTRIN_VTSTQ_S16:
- case ARM64_INTRIN_VTSTQ_S32:
- case ARM64_INTRIN_VTSTQ_S64:
- case ARM64_INTRIN_VTSTQ_S8:
- case ARM64_INTRIN_VTSTQ_U16:
- case ARM64_INTRIN_VTSTQ_U32:
- case ARM64_INTRIN_VTSTQ_U64:
- case ARM64_INTRIN_VTSTQ_U8:
- case ARM64_INTRIN_VUQADDQ_S16:
- case ARM64_INTRIN_VUQADDQ_S32:
- case ARM64_INTRIN_VUQADDQ_S64:
- case ARM64_INTRIN_VUQADDQ_S8:
- case ARM64_INTRIN_VUSDOTQ_LANEQ_S32:
- case ARM64_INTRIN_VUSDOTQ_LANE_S32:
- case ARM64_INTRIN_VUSDOTQ_S32:
- case ARM64_INTRIN_VUSMMLAQ_S32:
- case ARM64_INTRIN_VUZP1Q_P16:
- case ARM64_INTRIN_VUZP1Q_P64:
- case ARM64_INTRIN_VUZP1Q_P8:
- case ARM64_INTRIN_VUZP1Q_S16:
- case ARM64_INTRIN_VUZP1Q_S32:
- case ARM64_INTRIN_VUZP1Q_S64:
- case ARM64_INTRIN_VUZP1Q_S8:
- case ARM64_INTRIN_VUZP1Q_U16:
- case ARM64_INTRIN_VUZP1Q_U32:
- case ARM64_INTRIN_VUZP1Q_U64:
- case ARM64_INTRIN_VUZP1Q_U8:
- case ARM64_INTRIN_VUZP2Q_P16:
- case ARM64_INTRIN_VUZP2Q_P64:
- case ARM64_INTRIN_VUZP2Q_P8:
- case ARM64_INTRIN_VUZP2Q_S16:
- case ARM64_INTRIN_VUZP2Q_S32:
- case ARM64_INTRIN_VUZP2Q_S64:
- case ARM64_INTRIN_VUZP2Q_S8:
- case ARM64_INTRIN_VUZP2Q_U16:
- case ARM64_INTRIN_VUZP2Q_U32:
- case ARM64_INTRIN_VUZP2Q_U64:
- case ARM64_INTRIN_VUZP2Q_U8:
- case ARM64_INTRIN_VXARQ_U64:
- case ARM64_INTRIN_VZIP1Q_P16:
- case ARM64_INTRIN_VZIP1Q_P64:
- case ARM64_INTRIN_VZIP1Q_P8:
- case ARM64_INTRIN_VZIP1Q_S16:
- case ARM64_INTRIN_VZIP1Q_S32:
- case ARM64_INTRIN_VZIP1Q_S64:
- case ARM64_INTRIN_VZIP1Q_S8:
- case ARM64_INTRIN_VZIP1Q_U16:
- case ARM64_INTRIN_VZIP1Q_U32:
- case ARM64_INTRIN_VZIP1Q_U64:
- case ARM64_INTRIN_VZIP1Q_U8:
- case ARM64_INTRIN_VZIP2Q_P16:
- case ARM64_INTRIN_VZIP2Q_P64:
- case ARM64_INTRIN_VZIP2Q_P8:
- case ARM64_INTRIN_VZIP2Q_S16:
- case ARM64_INTRIN_VZIP2Q_S32:
- case ARM64_INTRIN_VZIP2Q_S64:
- case ARM64_INTRIN_VZIP2Q_S8:
- case ARM64_INTRIN_VZIP2Q_U16:
- case ARM64_INTRIN_VZIP2Q_U32:
- case ARM64_INTRIN_VZIP2Q_U64:
- case ARM64_INTRIN_VZIP2Q_U8:
- return {Type::IntegerType(16, false)};
- case ARM64_INTRIN_VADDLV_S8:
- case ARM64_INTRIN_VADDLV_U8:
- case ARM64_INTRIN_VADDLVQ_S8:
- case ARM64_INTRIN_VADDLVQ_U8:
- case ARM64_INTRIN_VADDV_S16:
- case ARM64_INTRIN_VADDV_U16:
- case ARM64_INTRIN_VADDVQ_S16:
- case ARM64_INTRIN_VADDVQ_U16:
- case ARM64_INTRIN_VCAGEH_F16:
- case ARM64_INTRIN_VCAGTH_F16:
- case ARM64_INTRIN_VCALEH_F16:
- case ARM64_INTRIN_VCALTH_F16:
- case ARM64_INTRIN_VCEQH_F16:
- case ARM64_INTRIN_VCEQZH_F16:
- case ARM64_INTRIN_VCGEH_F16:
- case ARM64_INTRIN_VCGEZH_F16:
- case ARM64_INTRIN_VCGTH_F16:
- case ARM64_INTRIN_VCGTZH_F16:
- case ARM64_INTRIN_VCLEH_F16:
- case ARM64_INTRIN_VCLEZH_F16:
- case ARM64_INTRIN_VCLTH_F16:
- case ARM64_INTRIN_VCLTZH_F16:
- case ARM64_INTRIN_VCVTAH_S16_F16:
- case ARM64_INTRIN_VCVTAH_U16_F16:
- case ARM64_INTRIN_VCVTH_N_S16_F16:
- case ARM64_INTRIN_VCVTH_N_U16_F16:
- case ARM64_INTRIN_VCVTH_S16_F16:
- case ARM64_INTRIN_VCVTH_U16_F16:
- case ARM64_INTRIN_VCVTMH_S16_F16:
- case ARM64_INTRIN_VCVTMH_U16_F16:
- case ARM64_INTRIN_VCVTNH_S16_F16:
- case ARM64_INTRIN_VCVTNH_U16_F16:
- case ARM64_INTRIN_VCVTPH_S16_F16:
- case ARM64_INTRIN_VCVTPH_U16_F16:
- case ARM64_INTRIN_VDUPH_LANE_P16:
- case ARM64_INTRIN_VDUPH_LANE_S16:
- case ARM64_INTRIN_VDUPH_LANE_U16:
- case ARM64_INTRIN_VDUPH_LANEQ_P16:
- case ARM64_INTRIN_VDUPH_LANEQ_S16:
- case ARM64_INTRIN_VDUPH_LANEQ_U16:
- case ARM64_INTRIN_VGET_LANE_P16:
- case ARM64_INTRIN_VGET_LANE_S16:
- case ARM64_INTRIN_VGET_LANE_U16:
- case ARM64_INTRIN_VGETQ_LANE_P16:
- case ARM64_INTRIN_VGETQ_LANE_S16:
- case ARM64_INTRIN_VGETQ_LANE_U16:
- case ARM64_INTRIN_VMAXV_S16:
- case ARM64_INTRIN_VMAXV_U16:
- case ARM64_INTRIN_VMAXVQ_S16:
- case ARM64_INTRIN_VMAXVQ_U16:
- case ARM64_INTRIN_VMINV_S16:
- case ARM64_INTRIN_VMINV_U16:
- case ARM64_INTRIN_VMINVQ_S16:
- case ARM64_INTRIN_VMINVQ_U16:
- case ARM64_INTRIN_VQABSH_S16:
- case ARM64_INTRIN_VQADDH_S16:
- case ARM64_INTRIN_VQADDH_U16:
- case ARM64_INTRIN_VQDMULHH_LANE_S16:
- case ARM64_INTRIN_VQDMULHH_LANEQ_S16:
- case ARM64_INTRIN_VQDMULHH_S16:
- case ARM64_INTRIN_VQMOVNS_S32:
- case ARM64_INTRIN_VQMOVNS_U32:
- case ARM64_INTRIN_VQMOVUNS_S32:
- case ARM64_INTRIN_VQNEGH_S16:
- case ARM64_INTRIN_VQRDMLAHH_LANE_S16:
- case ARM64_INTRIN_VQRDMLAHH_LANEQ_S16:
- case ARM64_INTRIN_VQRDMLAHH_S16:
- case ARM64_INTRIN_VQRDMLSHH_LANE_S16:
- case ARM64_INTRIN_VQRDMLSHH_LANEQ_S16:
- case ARM64_INTRIN_VQRDMLSHH_S16:
- case ARM64_INTRIN_VQRDMULHH_LANE_S16:
- case ARM64_INTRIN_VQRDMULHH_LANEQ_S16:
- case ARM64_INTRIN_VQRDMULHH_S16:
- case ARM64_INTRIN_VQRSHLH_S16:
- case ARM64_INTRIN_VQRSHLH_U16:
- case ARM64_INTRIN_VQRSHRNS_N_S32:
- case ARM64_INTRIN_VQRSHRNS_N_U32:
- case ARM64_INTRIN_VQRSHRUNS_N_S32:
- case ARM64_INTRIN_VQSHLH_N_S16:
- case ARM64_INTRIN_VQSHLH_N_U16:
- case ARM64_INTRIN_VQSHLH_S16:
- case ARM64_INTRIN_VQSHLH_U16:
- case ARM64_INTRIN_VQSHLUH_N_S16:
- case ARM64_INTRIN_VQSHRNS_N_S32:
- case ARM64_INTRIN_VQSHRNS_N_U32:
- case ARM64_INTRIN_VQSHRUNS_N_S32:
- case ARM64_INTRIN_VQSUBH_S16:
- case ARM64_INTRIN_VQSUBH_U16:
- case ARM64_INTRIN_VSQADDH_U16:
- case ARM64_INTRIN_VUQADDH_S16:
- return {Type::IntegerType(2, false)};
- case ARM64_INTRIN___CRC32B:
- case ARM64_INTRIN___CRC32CB:
- case ARM64_INTRIN___CRC32CD:
- case ARM64_INTRIN___CRC32CH:
- case ARM64_INTRIN___CRC32CW:
- case ARM64_INTRIN___CRC32D:
- case ARM64_INTRIN___CRC32H:
- case ARM64_INTRIN___CRC32W:
- case ARM64_INTRIN_VADDLV_S16:
- case ARM64_INTRIN_VADDLV_U16:
- case ARM64_INTRIN_VADDLVQ_S16:
- case ARM64_INTRIN_VADDLVQ_U16:
- case ARM64_INTRIN_VADDV_S32:
- case ARM64_INTRIN_VADDV_U32:
- case ARM64_INTRIN_VADDVQ_S32:
- case ARM64_INTRIN_VADDVQ_U32:
- case ARM64_INTRIN_VCAGES_F32:
- case ARM64_INTRIN_VCAGTS_F32:
- case ARM64_INTRIN_VCALES_F32:
- case ARM64_INTRIN_VCALTS_F32:
- case ARM64_INTRIN_VCEQS_F32:
- case ARM64_INTRIN_VCEQZS_F32:
- case ARM64_INTRIN_VCGES_F32:
- case ARM64_INTRIN_VCGEZS_F32:
- case ARM64_INTRIN_VCGTS_F32:
- case ARM64_INTRIN_VCGTZS_F32:
- case ARM64_INTRIN_VCLES_F32:
- case ARM64_INTRIN_VCLEZS_F32:
- case ARM64_INTRIN_VCLTS_F32:
- case ARM64_INTRIN_VCLTZS_F32:
- case ARM64_INTRIN_VCVTAH_S32_F16:
- case ARM64_INTRIN_VCVTAH_U32_F16:
- case ARM64_INTRIN_VCVTAS_S32_F32:
- case ARM64_INTRIN_VCVTAS_U32_F32:
- case ARM64_INTRIN_VCVTH_N_S32_F16:
- case ARM64_INTRIN_VCVTH_N_U32_F16:
- case ARM64_INTRIN_VCVTH_S32_F16:
- case ARM64_INTRIN_VCVTH_U32_F16:
- case ARM64_INTRIN_VCVTMH_S32_F16:
- case ARM64_INTRIN_VCVTMH_U32_F16:
- case ARM64_INTRIN_VCVTMS_S32_F32:
- case ARM64_INTRIN_VCVTMS_U32_F32:
- case ARM64_INTRIN_VCVTNH_S32_F16:
- case ARM64_INTRIN_VCVTNH_U32_F16:
- case ARM64_INTRIN_VCVTNS_S32_F32:
- case ARM64_INTRIN_VCVTNS_U32_F32:
- case ARM64_INTRIN_VCVTPH_S32_F16:
- case ARM64_INTRIN_VCVTPH_U32_F16:
- case ARM64_INTRIN_VCVTPS_S32_F32:
- case ARM64_INTRIN_VCVTPS_U32_F32:
- case ARM64_INTRIN_VCVTS_N_S32_F32:
- case ARM64_INTRIN_VCVTS_N_U32_F32:
- case ARM64_INTRIN_VCVTS_S32_F32:
- case ARM64_INTRIN_VCVTS_U32_F32:
- case ARM64_INTRIN_VDUPS_LANE_S32:
- case ARM64_INTRIN_VDUPS_LANE_U32:
- case ARM64_INTRIN_VDUPS_LANEQ_S32:
- case ARM64_INTRIN_VDUPS_LANEQ_U32:
- case ARM64_INTRIN_VGET_LANE_S32:
- case ARM64_INTRIN_VGET_LANE_U32:
- case ARM64_INTRIN_VGETQ_LANE_S32:
- case ARM64_INTRIN_VGETQ_LANE_U32:
- case ARM64_INTRIN_VMAXV_S32:
- case ARM64_INTRIN_VMAXV_U32:
- case ARM64_INTRIN_VMAXVQ_S32:
- case ARM64_INTRIN_VMAXVQ_U32:
- case ARM64_INTRIN_VMINV_S32:
- case ARM64_INTRIN_VMINV_U32:
- case ARM64_INTRIN_VMINVQ_S32:
- case ARM64_INTRIN_VMINVQ_U32:
- case ARM64_INTRIN_VQABSS_S32:
- case ARM64_INTRIN_VQADDS_S32:
- case ARM64_INTRIN_VQADDS_U32:
- case ARM64_INTRIN_VQDMLALH_LANE_S16:
- case ARM64_INTRIN_VQDMLALH_LANEQ_S16:
- case ARM64_INTRIN_VQDMLALH_S16:
- case ARM64_INTRIN_VQDMLSLH_LANE_S16:
- case ARM64_INTRIN_VQDMLSLH_LANEQ_S16:
- case ARM64_INTRIN_VQDMLSLH_S16:
- case ARM64_INTRIN_VQDMULHS_LANE_S32:
- case ARM64_INTRIN_VQDMULHS_LANEQ_S32:
- case ARM64_INTRIN_VQDMULHS_S32:
- case ARM64_INTRIN_VQDMULLH_LANE_S16:
- case ARM64_INTRIN_VQDMULLH_LANEQ_S16:
- case ARM64_INTRIN_VQDMULLH_S16:
- case ARM64_INTRIN_VQMOVND_S64:
- case ARM64_INTRIN_VQMOVND_U64:
- case ARM64_INTRIN_VQMOVUND_S64:
- case ARM64_INTRIN_VQNEGS_S32:
- case ARM64_INTRIN_VQRDMLAHS_LANE_S32:
- case ARM64_INTRIN_VQRDMLAHS_LANEQ_S32:
- case ARM64_INTRIN_VQRDMLAHS_S32:
- case ARM64_INTRIN_VQRDMLSHS_LANE_S32:
- case ARM64_INTRIN_VQRDMLSHS_LANEQ_S32:
- case ARM64_INTRIN_VQRDMLSHS_S32:
- case ARM64_INTRIN_VQRDMULHS_LANE_S32:
- case ARM64_INTRIN_VQRDMULHS_LANEQ_S32:
- case ARM64_INTRIN_VQRDMULHS_S32:
- case ARM64_INTRIN_VQRSHLS_S32:
- case ARM64_INTRIN_VQRSHLS_U32:
- case ARM64_INTRIN_VQRSHRND_N_S64:
- case ARM64_INTRIN_VQRSHRND_N_U64:
- case ARM64_INTRIN_VQRSHRUND_N_S64:
- case ARM64_INTRIN_VQSHLS_N_S32:
- case ARM64_INTRIN_VQSHLS_N_U32:
- case ARM64_INTRIN_VQSHLS_S32:
- case ARM64_INTRIN_VQSHLS_U32:
- case ARM64_INTRIN_VQSHLUS_N_S32:
- case ARM64_INTRIN_VQSHRND_N_S64:
- case ARM64_INTRIN_VQSHRND_N_U64:
- case ARM64_INTRIN_VQSHRUND_N_S64:
- case ARM64_INTRIN_VQSUBS_S32:
- case ARM64_INTRIN_VQSUBS_U32:
- case ARM64_INTRIN_VSHA1H_U32:
- case ARM64_INTRIN_VSQADDS_U32:
- case ARM64_INTRIN_VUQADDS_S32:
- return {Type::IntegerType(4, false)};
- case ARM64_INTRIN_VABA_S16:
- case ARM64_INTRIN_VABA_S32:
- case ARM64_INTRIN_VABA_S8:
- case ARM64_INTRIN_VABA_U16:
- case ARM64_INTRIN_VABA_U32:
- case ARM64_INTRIN_VABA_U8:
- case ARM64_INTRIN_VABD_S16:
- case ARM64_INTRIN_VABD_S32:
- case ARM64_INTRIN_VABD_S8:
- case ARM64_INTRIN_VABD_U16:
- case ARM64_INTRIN_VABD_U32:
- case ARM64_INTRIN_VABD_U8:
- case ARM64_INTRIN_VABS_S16:
- case ARM64_INTRIN_VABS_S32:
- case ARM64_INTRIN_VABS_S64:
- case ARM64_INTRIN_VABS_S8:
- case ARM64_INTRIN_VABSD_S64:
- case ARM64_INTRIN_VADD_P16:
- case ARM64_INTRIN_VADD_P64:
- case ARM64_INTRIN_VADD_P8:
- case ARM64_INTRIN_VADD_S16:
- case ARM64_INTRIN_VADD_S32:
- case ARM64_INTRIN_VADD_S64:
- case ARM64_INTRIN_VADD_S8:
- case ARM64_INTRIN_VADD_U16:
- case ARM64_INTRIN_VADD_U32:
- case ARM64_INTRIN_VADD_U64:
- case ARM64_INTRIN_VADD_U8:
- case ARM64_INTRIN_VADDD_S64:
- case ARM64_INTRIN_VADDD_U64:
- case ARM64_INTRIN_VADDHN_S16:
- case ARM64_INTRIN_VADDHN_S32:
- case ARM64_INTRIN_VADDHN_S64:
- case ARM64_INTRIN_VADDHN_U16:
- case ARM64_INTRIN_VADDHN_U32:
- case ARM64_INTRIN_VADDHN_U64:
- case ARM64_INTRIN_VADDLV_S32:
- case ARM64_INTRIN_VADDLV_U32:
- case ARM64_INTRIN_VADDLVQ_S32:
- case ARM64_INTRIN_VADDLVQ_U32:
- case ARM64_INTRIN_VADDVQ_S64:
- case ARM64_INTRIN_VADDVQ_U64:
- case ARM64_INTRIN_VAND_S16:
- case ARM64_INTRIN_VAND_S32:
- case ARM64_INTRIN_VAND_S64:
- case ARM64_INTRIN_VAND_S8:
- case ARM64_INTRIN_VAND_U16:
- case ARM64_INTRIN_VAND_U32:
- case ARM64_INTRIN_VAND_U64:
- case ARM64_INTRIN_VAND_U8:
- case ARM64_INTRIN_VBIC_S16:
- case ARM64_INTRIN_VBIC_S32:
- case ARM64_INTRIN_VBIC_S64:
- case ARM64_INTRIN_VBIC_S8:
- case ARM64_INTRIN_VBIC_U16:
- case ARM64_INTRIN_VBIC_U32:
- case ARM64_INTRIN_VBIC_U64:
- case ARM64_INTRIN_VBIC_U8:
- case ARM64_INTRIN_VBSL_P16:
- case ARM64_INTRIN_VBSL_P64:
- case ARM64_INTRIN_VBSL_P8:
- case ARM64_INTRIN_VBSL_S16:
- case ARM64_INTRIN_VBSL_S32:
- case ARM64_INTRIN_VBSL_S64:
- case ARM64_INTRIN_VBSL_S8:
- case ARM64_INTRIN_VBSL_U16:
- case ARM64_INTRIN_VBSL_U32:
- case ARM64_INTRIN_VBSL_U64:
- case ARM64_INTRIN_VBSL_U8:
- case ARM64_INTRIN_VCAGE_F16:
- case ARM64_INTRIN_VCAGE_F32:
- case ARM64_INTRIN_VCAGE_F64:
- case ARM64_INTRIN_VCAGED_F64:
- case ARM64_INTRIN_VCAGT_F16:
- case ARM64_INTRIN_VCAGT_F32:
- case ARM64_INTRIN_VCAGT_F64:
- case ARM64_INTRIN_VCAGTD_F64:
- case ARM64_INTRIN_VCALE_F16:
- case ARM64_INTRIN_VCALE_F32:
- case ARM64_INTRIN_VCALE_F64:
- case ARM64_INTRIN_VCALED_F64:
- case ARM64_INTRIN_VCALT_F16:
- case ARM64_INTRIN_VCALT_F32:
- case ARM64_INTRIN_VCALT_F64:
- case ARM64_INTRIN_VCALTD_F64:
- case ARM64_INTRIN_VCEQ_F16:
- case ARM64_INTRIN_VCEQ_F32:
- case ARM64_INTRIN_VCEQ_F64:
- case ARM64_INTRIN_VCEQ_P64:
- case ARM64_INTRIN_VCEQ_P8:
- case ARM64_INTRIN_VCEQ_S16:
- case ARM64_INTRIN_VCEQ_S32:
- case ARM64_INTRIN_VCEQ_S64:
- case ARM64_INTRIN_VCEQ_S8:
- case ARM64_INTRIN_VCEQ_U16:
- case ARM64_INTRIN_VCEQ_U32:
- case ARM64_INTRIN_VCEQ_U64:
- case ARM64_INTRIN_VCEQ_U8:
- case ARM64_INTRIN_VCEQD_F64:
- case ARM64_INTRIN_VCEQD_S64:
- case ARM64_INTRIN_VCEQD_U64:
- case ARM64_INTRIN_VCEQZ_F16:
- case ARM64_INTRIN_VCEQZ_F32:
- case ARM64_INTRIN_VCEQZ_F64:
- case ARM64_INTRIN_VCEQZ_P64:
- case ARM64_INTRIN_VCEQZ_P8:
- case ARM64_INTRIN_VCEQZ_S16:
- case ARM64_INTRIN_VCEQZ_S32:
- case ARM64_INTRIN_VCEQZ_S64:
- case ARM64_INTRIN_VCEQZ_S8:
- case ARM64_INTRIN_VCEQZ_U16:
- case ARM64_INTRIN_VCEQZ_U32:
- case ARM64_INTRIN_VCEQZ_U64:
- case ARM64_INTRIN_VCEQZ_U8:
- case ARM64_INTRIN_VCEQZD_F64:
- case ARM64_INTRIN_VCEQZD_S64:
- case ARM64_INTRIN_VCEQZD_U64:
- case ARM64_INTRIN_VCGE_F16:
- case ARM64_INTRIN_VCGE_F32:
- case ARM64_INTRIN_VCGE_F64:
- case ARM64_INTRIN_VCGE_S16:
- case ARM64_INTRIN_VCGE_S32:
- case ARM64_INTRIN_VCGE_S64:
- case ARM64_INTRIN_VCGE_S8:
- case ARM64_INTRIN_VCGE_U16:
- case ARM64_INTRIN_VCGE_U32:
- case ARM64_INTRIN_VCGE_U64:
- case ARM64_INTRIN_VCGE_U8:
- case ARM64_INTRIN_VCGED_F64:
- case ARM64_INTRIN_VCGED_S64:
- case ARM64_INTRIN_VCGED_U64:
- case ARM64_INTRIN_VCGEZ_F16:
- case ARM64_INTRIN_VCGEZ_F32:
- case ARM64_INTRIN_VCGEZ_F64:
- case ARM64_INTRIN_VCGEZ_S16:
- case ARM64_INTRIN_VCGEZ_S32:
- case ARM64_INTRIN_VCGEZ_S64:
- case ARM64_INTRIN_VCGEZ_S8:
- case ARM64_INTRIN_VCGEZD_F64:
- case ARM64_INTRIN_VCGEZD_S64:
- case ARM64_INTRIN_VCGT_F16:
- case ARM64_INTRIN_VCGT_F32:
- case ARM64_INTRIN_VCGT_F64:
- case ARM64_INTRIN_VCGT_S16:
- case ARM64_INTRIN_VCGT_S32:
- case ARM64_INTRIN_VCGT_S64:
- case ARM64_INTRIN_VCGT_S8:
- case ARM64_INTRIN_VCGT_U16:
- case ARM64_INTRIN_VCGT_U32:
- case ARM64_INTRIN_VCGT_U64:
- case ARM64_INTRIN_VCGT_U8:
- case ARM64_INTRIN_VCGTD_F64:
- case ARM64_INTRIN_VCGTD_S64:
- case ARM64_INTRIN_VCGTD_U64:
- case ARM64_INTRIN_VCGTZ_F16:
- case ARM64_INTRIN_VCGTZ_F32:
- case ARM64_INTRIN_VCGTZ_F64:
- case ARM64_INTRIN_VCGTZ_S16:
- case ARM64_INTRIN_VCGTZ_S32:
- case ARM64_INTRIN_VCGTZ_S64:
- case ARM64_INTRIN_VCGTZ_S8:
- case ARM64_INTRIN_VCGTZD_F64:
- case ARM64_INTRIN_VCGTZD_S64:
- case ARM64_INTRIN_VCLE_F16:
- case ARM64_INTRIN_VCLE_F32:
- case ARM64_INTRIN_VCLE_F64:
- case ARM64_INTRIN_VCLE_S16:
- case ARM64_INTRIN_VCLE_S32:
- case ARM64_INTRIN_VCLE_S64:
- case ARM64_INTRIN_VCLE_S8:
- case ARM64_INTRIN_VCLE_U16:
- case ARM64_INTRIN_VCLE_U32:
- case ARM64_INTRIN_VCLE_U64:
- case ARM64_INTRIN_VCLE_U8:
- case ARM64_INTRIN_VCLED_F64:
- case ARM64_INTRIN_VCLED_S64:
- case ARM64_INTRIN_VCLED_U64:
- case ARM64_INTRIN_VCLEZ_F16:
- case ARM64_INTRIN_VCLEZ_F32:
- case ARM64_INTRIN_VCLEZ_F64:
- case ARM64_INTRIN_VCLEZ_S16:
- case ARM64_INTRIN_VCLEZ_S32:
- case ARM64_INTRIN_VCLEZ_S64:
- case ARM64_INTRIN_VCLEZ_S8:
- case ARM64_INTRIN_VCLEZD_F64:
- case ARM64_INTRIN_VCLEZD_S64:
- case ARM64_INTRIN_VCLS_S16:
- case ARM64_INTRIN_VCLS_S32:
- case ARM64_INTRIN_VCLS_S8:
- case ARM64_INTRIN_VCLS_U16:
- case ARM64_INTRIN_VCLS_U32:
- case ARM64_INTRIN_VCLS_U8:
- case ARM64_INTRIN_VCLT_F16:
- case ARM64_INTRIN_VCLT_F32:
- case ARM64_INTRIN_VCLT_F64:
- case ARM64_INTRIN_VCLT_S16:
- case ARM64_INTRIN_VCLT_S32:
- case ARM64_INTRIN_VCLT_S64:
- case ARM64_INTRIN_VCLT_S8:
- case ARM64_INTRIN_VCLT_U16:
- case ARM64_INTRIN_VCLT_U32:
- case ARM64_INTRIN_VCLT_U64:
- case ARM64_INTRIN_VCLT_U8:
- case ARM64_INTRIN_VCLTD_F64:
- case ARM64_INTRIN_VCLTD_S64:
- case ARM64_INTRIN_VCLTD_U64:
- case ARM64_INTRIN_VCLTZ_F16:
- case ARM64_INTRIN_VCLTZ_F32:
- case ARM64_INTRIN_VCLTZ_F64:
- case ARM64_INTRIN_VCLTZ_S16:
- case ARM64_INTRIN_VCLTZ_S32:
- case ARM64_INTRIN_VCLTZ_S64:
- case ARM64_INTRIN_VCLTZ_S8:
- case ARM64_INTRIN_VCLTZD_F64:
- case ARM64_INTRIN_VCLTZD_S64:
- case ARM64_INTRIN_VCLZ_S16:
- case ARM64_INTRIN_VCLZ_S32:
- case ARM64_INTRIN_VCLZ_S8:
- case ARM64_INTRIN_VCLZ_U16:
- case ARM64_INTRIN_VCLZ_U32:
- case ARM64_INTRIN_VCLZ_U8:
- case ARM64_INTRIN_VCNT_P8:
- case ARM64_INTRIN_VCNT_S8:
- case ARM64_INTRIN_VCNT_U8:
- case ARM64_INTRIN_VCREATE_P16:
- case ARM64_INTRIN_VCREATE_P64:
- case ARM64_INTRIN_VCREATE_P8:
- case ARM64_INTRIN_VCREATE_S16:
- case ARM64_INTRIN_VCREATE_S32:
- case ARM64_INTRIN_VCREATE_S64:
- case ARM64_INTRIN_VCREATE_S8:
- case ARM64_INTRIN_VCREATE_U16:
- case ARM64_INTRIN_VCREATE_U32:
- case ARM64_INTRIN_VCREATE_U64:
- case ARM64_INTRIN_VCREATE_U8:
- case ARM64_INTRIN_VCVT_N_S16_F16:
- case ARM64_INTRIN_VCVT_N_S32_F32:
- case ARM64_INTRIN_VCVT_N_S64_F64:
- case ARM64_INTRIN_VCVT_N_U16_F16:
- case ARM64_INTRIN_VCVT_N_U32_F32:
- case ARM64_INTRIN_VCVT_N_U64_F64:
- case ARM64_INTRIN_VCVT_S16_F16:
- case ARM64_INTRIN_VCVT_S32_F32:
- case ARM64_INTRIN_VCVT_S64_F64:
- case ARM64_INTRIN_VCVT_U16_F16:
- case ARM64_INTRIN_VCVT_U32_F32:
- case ARM64_INTRIN_VCVT_U64_F64:
- case ARM64_INTRIN_VCVTA_S16_F16:
- case ARM64_INTRIN_VCVTA_S32_F32:
- case ARM64_INTRIN_VCVTA_S64_F64:
- case ARM64_INTRIN_VCVTA_U16_F16:
- case ARM64_INTRIN_VCVTA_U32_F32:
- case ARM64_INTRIN_VCVTA_U64_F64:
- case ARM64_INTRIN_VCVTAD_S64_F64:
- case ARM64_INTRIN_VCVTAD_U64_F64:
- case ARM64_INTRIN_VCVTAH_S64_F16:
- case ARM64_INTRIN_VCVTAH_U64_F16:
- case ARM64_INTRIN_VCVTD_N_S64_F64:
- case ARM64_INTRIN_VCVTD_N_U64_F64:
- case ARM64_INTRIN_VCVTD_S64_F64:
- case ARM64_INTRIN_VCVTD_U64_F64:
- case ARM64_INTRIN_VCVTH_N_S64_F16:
- case ARM64_INTRIN_VCVTH_N_U64_F16:
- case ARM64_INTRIN_VCVTH_S64_F16:
- case ARM64_INTRIN_VCVTH_U64_F16:
- case ARM64_INTRIN_VCVTM_S16_F16:
- case ARM64_INTRIN_VCVTM_S32_F32:
- case ARM64_INTRIN_VCVTM_S64_F64:
- case ARM64_INTRIN_VCVTM_U16_F16:
- case ARM64_INTRIN_VCVTM_U32_F32:
- case ARM64_INTRIN_VCVTM_U64_F64:
- case ARM64_INTRIN_VCVTMD_S64_F64:
- case ARM64_INTRIN_VCVTMD_U64_F64:
- case ARM64_INTRIN_VCVTMH_S64_F16:
- case ARM64_INTRIN_VCVTMH_U64_F16:
- case ARM64_INTRIN_VCVTN_S16_F16:
- case ARM64_INTRIN_VCVTN_S32_F32:
- case ARM64_INTRIN_VCVTN_S64_F64:
- case ARM64_INTRIN_VCVTN_U16_F16:
- case ARM64_INTRIN_VCVTN_U32_F32:
- case ARM64_INTRIN_VCVTN_U64_F64:
- case ARM64_INTRIN_VCVTND_S64_F64:
- case ARM64_INTRIN_VCVTND_U64_F64:
- case ARM64_INTRIN_VCVTNH_S64_F16:
- case ARM64_INTRIN_VCVTNH_U64_F16:
- case ARM64_INTRIN_VCVTP_S16_F16:
- case ARM64_INTRIN_VCVTP_S32_F32:
- case ARM64_INTRIN_VCVTP_S64_F64:
- case ARM64_INTRIN_VCVTP_U16_F16:
- case ARM64_INTRIN_VCVTP_U32_F32:
- case ARM64_INTRIN_VCVTP_U64_F64:
- case ARM64_INTRIN_VCVTPD_S64_F64:
- case ARM64_INTRIN_VCVTPD_U64_F64:
- case ARM64_INTRIN_VCVTPH_S64_F16:
- case ARM64_INTRIN_VCVTPH_U64_F16:
- case ARM64_INTRIN_VDOT_LANE_S32:
- case ARM64_INTRIN_VDOT_LANE_U32:
- case ARM64_INTRIN_VDOT_LANEQ_S32:
- case ARM64_INTRIN_VDOT_LANEQ_U32:
- case ARM64_INTRIN_VDOT_S32:
- case ARM64_INTRIN_VDOT_U32:
- case ARM64_INTRIN_VDUP_LANE_P16:
- case ARM64_INTRIN_VDUP_LANE_P64:
- case ARM64_INTRIN_VDUP_LANE_P8:
- case ARM64_INTRIN_VDUP_LANE_S16:
- case ARM64_INTRIN_VDUP_LANE_S32:
- case ARM64_INTRIN_VDUP_LANE_S64:
- case ARM64_INTRIN_VDUP_LANE_S8:
- case ARM64_INTRIN_VDUP_LANE_U16:
- case ARM64_INTRIN_VDUP_LANE_U32:
- case ARM64_INTRIN_VDUP_LANE_U64:
- case ARM64_INTRIN_VDUP_LANE_U8:
- case ARM64_INTRIN_VDUP_LANEQ_P16:
- case ARM64_INTRIN_VDUP_LANEQ_P64:
- case ARM64_INTRIN_VDUP_LANEQ_P8:
- case ARM64_INTRIN_VDUP_LANEQ_S16:
- case ARM64_INTRIN_VDUP_LANEQ_S32:
- case ARM64_INTRIN_VDUP_LANEQ_S64:
- case ARM64_INTRIN_VDUP_LANEQ_S8:
- case ARM64_INTRIN_VDUP_LANEQ_U16:
- case ARM64_INTRIN_VDUP_LANEQ_U32:
- case ARM64_INTRIN_VDUP_LANEQ_U64:
- case ARM64_INTRIN_VDUP_LANEQ_U8:
- case ARM64_INTRIN_VDUP_N_P16:
- case ARM64_INTRIN_VDUP_N_P64:
- case ARM64_INTRIN_VDUP_N_P8:
- case ARM64_INTRIN_VDUP_N_S16:
- case ARM64_INTRIN_VDUP_N_S32:
- case ARM64_INTRIN_VDUP_N_S64:
- case ARM64_INTRIN_VDUP_N_S8:
- case ARM64_INTRIN_VDUP_N_U16:
- case ARM64_INTRIN_VDUP_N_U32:
- case ARM64_INTRIN_VDUP_N_U64:
- case ARM64_INTRIN_VDUP_N_U8:
- case ARM64_INTRIN_VDUPD_LANE_S64:
- case ARM64_INTRIN_VDUPD_LANE_U64:
- case ARM64_INTRIN_VDUPD_LANEQ_S64:
- case ARM64_INTRIN_VDUPD_LANEQ_U64:
- case ARM64_INTRIN_VEOR_S16:
- case ARM64_INTRIN_VEOR_S32:
- case ARM64_INTRIN_VEOR_S64:
- case ARM64_INTRIN_VEOR_S8:
- case ARM64_INTRIN_VEOR_U16:
- case ARM64_INTRIN_VEOR_U32:
- case ARM64_INTRIN_VEOR_U64:
- case ARM64_INTRIN_VEOR_U8:
- case ARM64_INTRIN_VEXT_P16:
- case ARM64_INTRIN_VEXT_P64:
- case ARM64_INTRIN_VEXT_P8:
- case ARM64_INTRIN_VEXT_S16:
- case ARM64_INTRIN_VEXT_S32:
- case ARM64_INTRIN_VEXT_S64:
- case ARM64_INTRIN_VEXT_S8:
- case ARM64_INTRIN_VEXT_U16:
- case ARM64_INTRIN_VEXT_U32:
- case ARM64_INTRIN_VEXT_U64:
- case ARM64_INTRIN_VEXT_U8:
- case ARM64_INTRIN_VGET_HIGH_P16:
- case ARM64_INTRIN_VGET_HIGH_P64:
- case ARM64_INTRIN_VGET_HIGH_P8:
- case ARM64_INTRIN_VGET_HIGH_S16:
- case ARM64_INTRIN_VGET_HIGH_S32:
- case ARM64_INTRIN_VGET_HIGH_S64:
- case ARM64_INTRIN_VGET_HIGH_S8:
- case ARM64_INTRIN_VGET_HIGH_U16:
- case ARM64_INTRIN_VGET_HIGH_U32:
- case ARM64_INTRIN_VGET_HIGH_U64:
- case ARM64_INTRIN_VGET_HIGH_U8:
- case ARM64_INTRIN_VGET_LANE_P64:
- case ARM64_INTRIN_VGET_LANE_S64:
- case ARM64_INTRIN_VGET_LANE_U64:
- case ARM64_INTRIN_VGET_LOW_P16:
- case ARM64_INTRIN_VGET_LOW_P64:
- case ARM64_INTRIN_VGET_LOW_P8:
- case ARM64_INTRIN_VGET_LOW_S16:
- case ARM64_INTRIN_VGET_LOW_S32:
- case ARM64_INTRIN_VGET_LOW_S64:
- case ARM64_INTRIN_VGET_LOW_S8:
- case ARM64_INTRIN_VGET_LOW_U16:
- case ARM64_INTRIN_VGET_LOW_U32:
- case ARM64_INTRIN_VGET_LOW_U64:
- case ARM64_INTRIN_VGET_LOW_U8:
- case ARM64_INTRIN_VGETQ_LANE_P64:
- case ARM64_INTRIN_VGETQ_LANE_S64:
- case ARM64_INTRIN_VGETQ_LANE_U64:
- case ARM64_INTRIN_VHADD_S16:
- case ARM64_INTRIN_VHADD_S32:
- case ARM64_INTRIN_VHADD_S8:
- case ARM64_INTRIN_VHADD_U16:
- case ARM64_INTRIN_VHADD_U32:
- case ARM64_INTRIN_VHADD_U8:
- case ARM64_INTRIN_VHSUB_S16:
- case ARM64_INTRIN_VHSUB_S32:
- case ARM64_INTRIN_VHSUB_S8:
- case ARM64_INTRIN_VHSUB_U16:
- case ARM64_INTRIN_VHSUB_U32:
- case ARM64_INTRIN_VHSUB_U8:
- case ARM64_INTRIN_VMAX_S16:
- case ARM64_INTRIN_VMAX_S32:
- case ARM64_INTRIN_VMAX_S8:
- case ARM64_INTRIN_VMAX_U16:
- case ARM64_INTRIN_VMAX_U32:
- case ARM64_INTRIN_VMAX_U8:
- case ARM64_INTRIN_VMIN_S16:
- case ARM64_INTRIN_VMIN_S32:
- case ARM64_INTRIN_VMIN_S8:
- case ARM64_INTRIN_VMIN_U16:
- case ARM64_INTRIN_VMIN_U32:
- case ARM64_INTRIN_VMIN_U8:
- case ARM64_INTRIN_VMLA_LANE_S16:
- case ARM64_INTRIN_VMLA_LANE_S32:
- case ARM64_INTRIN_VMLA_LANE_U16:
- case ARM64_INTRIN_VMLA_LANE_U32:
- case ARM64_INTRIN_VMLA_LANEQ_S16:
- case ARM64_INTRIN_VMLA_LANEQ_S32:
- case ARM64_INTRIN_VMLA_LANEQ_U16:
- case ARM64_INTRIN_VMLA_LANEQ_U32:
- case ARM64_INTRIN_VMLA_N_S16:
- case ARM64_INTRIN_VMLA_N_S32:
- case ARM64_INTRIN_VMLA_N_U16:
- case ARM64_INTRIN_VMLA_N_U32:
- case ARM64_INTRIN_VMLA_S16:
- case ARM64_INTRIN_VMLA_S32:
- case ARM64_INTRIN_VMLA_S8:
- case ARM64_INTRIN_VMLA_U16:
- case ARM64_INTRIN_VMLA_U32:
- case ARM64_INTRIN_VMLA_U8:
- case ARM64_INTRIN_VMLS_LANE_S16:
- case ARM64_INTRIN_VMLS_LANE_S32:
- case ARM64_INTRIN_VMLS_LANE_U16:
- case ARM64_INTRIN_VMLS_LANE_U32:
- case ARM64_INTRIN_VMLS_LANEQ_S16:
- case ARM64_INTRIN_VMLS_LANEQ_S32:
- case ARM64_INTRIN_VMLS_LANEQ_U16:
- case ARM64_INTRIN_VMLS_LANEQ_U32:
- case ARM64_INTRIN_VMLS_N_S16:
- case ARM64_INTRIN_VMLS_N_S32:
- case ARM64_INTRIN_VMLS_N_U16:
- case ARM64_INTRIN_VMLS_N_U32:
- case ARM64_INTRIN_VMLS_S16:
- case ARM64_INTRIN_VMLS_S32:
- case ARM64_INTRIN_VMLS_S8:
- case ARM64_INTRIN_VMLS_U16:
- case ARM64_INTRIN_VMLS_U32:
- case ARM64_INTRIN_VMLS_U8:
- case ARM64_INTRIN_VMOV_N_P16:
- case ARM64_INTRIN_VMOV_N_P8:
- case ARM64_INTRIN_VMOV_N_S16:
- case ARM64_INTRIN_VMOV_N_S32:
- case ARM64_INTRIN_VMOV_N_S64:
- case ARM64_INTRIN_VMOV_N_S8:
- case ARM64_INTRIN_VMOV_N_U16:
- case ARM64_INTRIN_VMOV_N_U32:
- case ARM64_INTRIN_VMOV_N_U64:
- case ARM64_INTRIN_VMOV_N_U8:
- case ARM64_INTRIN_VMOVN_S16:
- case ARM64_INTRIN_VMOVN_S32:
- case ARM64_INTRIN_VMOVN_S64:
- case ARM64_INTRIN_VMOVN_U16:
- case ARM64_INTRIN_VMOVN_U32:
- case ARM64_INTRIN_VMOVN_U64:
- case ARM64_INTRIN_VMUL_LANE_S16:
- case ARM64_INTRIN_VMUL_LANE_S32:
- case ARM64_INTRIN_VMUL_LANE_U16:
- case ARM64_INTRIN_VMUL_LANE_U32:
- case ARM64_INTRIN_VMUL_LANEQ_S16:
- case ARM64_INTRIN_VMUL_LANEQ_S32:
- case ARM64_INTRIN_VMUL_LANEQ_U16:
- case ARM64_INTRIN_VMUL_LANEQ_U32:
- case ARM64_INTRIN_VMUL_N_S16:
- case ARM64_INTRIN_VMUL_N_S32:
- case ARM64_INTRIN_VMUL_N_U16:
- case ARM64_INTRIN_VMUL_N_U32:
- case ARM64_INTRIN_VMUL_P8:
- case ARM64_INTRIN_VMUL_S16:
- case ARM64_INTRIN_VMUL_S32:
- case ARM64_INTRIN_VMUL_S8:
- case ARM64_INTRIN_VMUL_U16:
- case ARM64_INTRIN_VMUL_U32:
- case ARM64_INTRIN_VMUL_U8:
- case ARM64_INTRIN_VMVN_P8:
- case ARM64_INTRIN_VMVN_S16:
- case ARM64_INTRIN_VMVN_S32:
- case ARM64_INTRIN_VMVN_S8:
- case ARM64_INTRIN_VMVN_U16:
- case ARM64_INTRIN_VMVN_U32:
- case ARM64_INTRIN_VMVN_U8:
- case ARM64_INTRIN_VNEG_S16:
- case ARM64_INTRIN_VNEG_S32:
- case ARM64_INTRIN_VNEG_S64:
- case ARM64_INTRIN_VNEG_S8:
- case ARM64_INTRIN_VNEGD_S64:
- case ARM64_INTRIN_VORN_S16:
- case ARM64_INTRIN_VORN_S32:
- case ARM64_INTRIN_VORN_S64:
- case ARM64_INTRIN_VORN_S8:
- case ARM64_INTRIN_VORN_U16:
- case ARM64_INTRIN_VORN_U32:
- case ARM64_INTRIN_VORN_U64:
- case ARM64_INTRIN_VORN_U8:
- case ARM64_INTRIN_VORR_S16:
- case ARM64_INTRIN_VORR_S32:
- case ARM64_INTRIN_VORR_S64:
- case ARM64_INTRIN_VORR_S8:
- case ARM64_INTRIN_VORR_U16:
- case ARM64_INTRIN_VORR_U32:
- case ARM64_INTRIN_VORR_U64:
- case ARM64_INTRIN_VORR_U8:
- case ARM64_INTRIN_VPADAL_S16:
- case ARM64_INTRIN_VPADAL_S32:
- case ARM64_INTRIN_VPADAL_S8:
- case ARM64_INTRIN_VPADAL_U16:
- case ARM64_INTRIN_VPADAL_U32:
- case ARM64_INTRIN_VPADAL_U8:
- case ARM64_INTRIN_VPADD_S16:
- case ARM64_INTRIN_VPADD_S32:
- case ARM64_INTRIN_VPADD_S8:
- case ARM64_INTRIN_VPADD_U16:
- case ARM64_INTRIN_VPADD_U32:
- case ARM64_INTRIN_VPADD_U8:
- case ARM64_INTRIN_VPADDD_S64:
- case ARM64_INTRIN_VPADDD_U64:
- case ARM64_INTRIN_VPADDL_S16:
- case ARM64_INTRIN_VPADDL_S32:
- case ARM64_INTRIN_VPADDL_S8:
- case ARM64_INTRIN_VPADDL_U16:
- case ARM64_INTRIN_VPADDL_U32:
- case ARM64_INTRIN_VPADDL_U8:
- case ARM64_INTRIN_VPMAX_S16:
- case ARM64_INTRIN_VPMAX_S32:
- case ARM64_INTRIN_VPMAX_S8:
- case ARM64_INTRIN_VPMAX_U16:
- case ARM64_INTRIN_VPMAX_U32:
- case ARM64_INTRIN_VPMAX_U8:
- case ARM64_INTRIN_VPMIN_S16:
- case ARM64_INTRIN_VPMIN_S32:
- case ARM64_INTRIN_VPMIN_S8:
- case ARM64_INTRIN_VPMIN_U16:
- case ARM64_INTRIN_VPMIN_U32:
- case ARM64_INTRIN_VPMIN_U8:
- case ARM64_INTRIN_VQABS_S16:
- case ARM64_INTRIN_VQABS_S32:
- case ARM64_INTRIN_VQABS_S64:
- case ARM64_INTRIN_VQABS_S8:
- case ARM64_INTRIN_VQABSD_S64:
- case ARM64_INTRIN_VQADD_S16:
- case ARM64_INTRIN_VQADD_S32:
- case ARM64_INTRIN_VQADD_S64:
- case ARM64_INTRIN_VQADD_S8:
- case ARM64_INTRIN_VQADD_U16:
- case ARM64_INTRIN_VQADD_U32:
- case ARM64_INTRIN_VQADD_U64:
- case ARM64_INTRIN_VQADD_U8:
- case ARM64_INTRIN_VQADDD_S64:
- case ARM64_INTRIN_VQADDD_U64:
- case ARM64_INTRIN_VQDMLALS_LANE_S32:
- case ARM64_INTRIN_VQDMLALS_LANEQ_S32:
- case ARM64_INTRIN_VQDMLALS_S32:
- case ARM64_INTRIN_VQDMLSLS_LANE_S32:
- case ARM64_INTRIN_VQDMLSLS_LANEQ_S32:
- case ARM64_INTRIN_VQDMLSLS_S32:
- case ARM64_INTRIN_VQDMULH_LANE_S16:
- case ARM64_INTRIN_VQDMULH_LANE_S32:
- case ARM64_INTRIN_VQDMULH_LANEQ_S16:
- case ARM64_INTRIN_VQDMULH_LANEQ_S32:
- case ARM64_INTRIN_VQDMULH_N_S16:
- case ARM64_INTRIN_VQDMULH_N_S32:
- case ARM64_INTRIN_VQDMULH_S16:
- case ARM64_INTRIN_VQDMULH_S32:
- case ARM64_INTRIN_VQDMULLS_LANE_S32:
- case ARM64_INTRIN_VQDMULLS_LANEQ_S32:
- case ARM64_INTRIN_VQDMULLS_S32:
- case ARM64_INTRIN_VQMOVN_S16:
- case ARM64_INTRIN_VQMOVN_S32:
- case ARM64_INTRIN_VQMOVN_S64:
- case ARM64_INTRIN_VQMOVN_U16:
- case ARM64_INTRIN_VQMOVN_U32:
- case ARM64_INTRIN_VQMOVN_U64:
- case ARM64_INTRIN_VQMOVUN_S16:
- case ARM64_INTRIN_VQMOVUN_S32:
- case ARM64_INTRIN_VQMOVUN_S64:
- case ARM64_INTRIN_VQNEG_S16:
- case ARM64_INTRIN_VQNEG_S32:
- case ARM64_INTRIN_VQNEG_S64:
- case ARM64_INTRIN_VQNEG_S8:
- case ARM64_INTRIN_VQNEGD_S64:
- case ARM64_INTRIN_VQRDMLAH_LANE_S16:
- case ARM64_INTRIN_VQRDMLAH_LANE_S32:
- case ARM64_INTRIN_VQRDMLAH_LANEQ_S16:
- case ARM64_INTRIN_VQRDMLAH_LANEQ_S32:
- case ARM64_INTRIN_VQRDMLAH_S16:
- case ARM64_INTRIN_VQRDMLAH_S32:
- case ARM64_INTRIN_VQRDMLSH_LANE_S16:
- case ARM64_INTRIN_VQRDMLSH_LANE_S32:
- case ARM64_INTRIN_VQRDMLSH_LANEQ_S16:
- case ARM64_INTRIN_VQRDMLSH_LANEQ_S32:
- case ARM64_INTRIN_VQRDMLSH_S16:
- case ARM64_INTRIN_VQRDMLSH_S32:
- case ARM64_INTRIN_VQRDMULH_LANE_S16:
- case ARM64_INTRIN_VQRDMULH_LANE_S32:
- case ARM64_INTRIN_VQRDMULH_LANEQ_S16:
- case ARM64_INTRIN_VQRDMULH_LANEQ_S32:
- case ARM64_INTRIN_VQRDMULH_N_S16:
- case ARM64_INTRIN_VQRDMULH_N_S32:
- case ARM64_INTRIN_VQRDMULH_S16:
- case ARM64_INTRIN_VQRDMULH_S32:
- case ARM64_INTRIN_VQRSHL_S16:
- case ARM64_INTRIN_VQRSHL_S32:
- case ARM64_INTRIN_VQRSHL_S64:
- case ARM64_INTRIN_VQRSHL_S8:
- case ARM64_INTRIN_VQRSHL_U16:
- case ARM64_INTRIN_VQRSHL_U32:
- case ARM64_INTRIN_VQRSHL_U64:
- case ARM64_INTRIN_VQRSHL_U8:
- case ARM64_INTRIN_VQRSHLD_S64:
- case ARM64_INTRIN_VQRSHLD_U64:
- case ARM64_INTRIN_VQRSHRN_N_S16:
- case ARM64_INTRIN_VQRSHRN_N_S32:
- case ARM64_INTRIN_VQRSHRN_N_S64:
- case ARM64_INTRIN_VQRSHRN_N_U16:
- case ARM64_INTRIN_VQRSHRN_N_U32:
- case ARM64_INTRIN_VQRSHRN_N_U64:
- case ARM64_INTRIN_VQRSHRUN_N_S16:
- case ARM64_INTRIN_VQRSHRUN_N_S32:
- case ARM64_INTRIN_VQRSHRUN_N_S64:
- case ARM64_INTRIN_VQSHL_N_S16:
- case ARM64_INTRIN_VQSHL_N_S32:
- case ARM64_INTRIN_VQSHL_N_S64:
- case ARM64_INTRIN_VQSHL_N_S8:
- case ARM64_INTRIN_VQSHL_N_U16:
- case ARM64_INTRIN_VQSHL_N_U32:
- case ARM64_INTRIN_VQSHL_N_U64:
- case ARM64_INTRIN_VQSHL_N_U8:
- case ARM64_INTRIN_VQSHL_S16:
- case ARM64_INTRIN_VQSHL_S32:
- case ARM64_INTRIN_VQSHL_S64:
- case ARM64_INTRIN_VQSHL_S8:
- case ARM64_INTRIN_VQSHL_U16:
- case ARM64_INTRIN_VQSHL_U32:
- case ARM64_INTRIN_VQSHL_U64:
- case ARM64_INTRIN_VQSHL_U8:
- case ARM64_INTRIN_VQSHLD_N_S64:
- case ARM64_INTRIN_VQSHLD_N_U64:
- case ARM64_INTRIN_VQSHLD_S64:
- case ARM64_INTRIN_VQSHLD_U64:
- case ARM64_INTRIN_VQSHLU_N_S16:
- case ARM64_INTRIN_VQSHLU_N_S32:
- case ARM64_INTRIN_VQSHLU_N_S64:
- case ARM64_INTRIN_VQSHLU_N_S8:
- case ARM64_INTRIN_VQSHLUD_N_S64:
- case ARM64_INTRIN_VQSHRN_N_S16:
- case ARM64_INTRIN_VQSHRN_N_S32:
- case ARM64_INTRIN_VQSHRN_N_S64:
- case ARM64_INTRIN_VQSHRN_N_U16:
- case ARM64_INTRIN_VQSHRN_N_U32:
- case ARM64_INTRIN_VQSHRN_N_U64:
- case ARM64_INTRIN_VQSHRUN_N_S16:
- case ARM64_INTRIN_VQSHRUN_N_S32:
- case ARM64_INTRIN_VQSHRUN_N_S64:
- case ARM64_INTRIN_VQSUB_S16:
- case ARM64_INTRIN_VQSUB_S32:
- case ARM64_INTRIN_VQSUB_S64:
- case ARM64_INTRIN_VQSUB_S8:
- case ARM64_INTRIN_VQSUB_U16:
- case ARM64_INTRIN_VQSUB_U32:
- case ARM64_INTRIN_VQSUB_U64:
- case ARM64_INTRIN_VQSUB_U8:
- case ARM64_INTRIN_VQSUBD_S64:
- case ARM64_INTRIN_VQSUBD_U64:
- case ARM64_INTRIN_VRADDHN_S16:
- case ARM64_INTRIN_VRADDHN_S32:
- case ARM64_INTRIN_VRADDHN_S64:
- case ARM64_INTRIN_VRADDHN_U16:
- case ARM64_INTRIN_VRADDHN_U32:
- case ARM64_INTRIN_VRADDHN_U64:
- case ARM64_INTRIN_VRBIT_P8:
- case ARM64_INTRIN_VRBIT_S8:
- case ARM64_INTRIN_VRBIT_U8:
- case ARM64_INTRIN_VRECPE_U32:
- case ARM64_INTRIN_VREV16_P8:
- case ARM64_INTRIN_VREV16_S8:
- case ARM64_INTRIN_VREV16_U8:
- case ARM64_INTRIN_VREV32_P16:
- case ARM64_INTRIN_VREV32_P8:
- case ARM64_INTRIN_VREV32_S16:
- case ARM64_INTRIN_VREV32_S8:
- case ARM64_INTRIN_VREV32_U16:
- case ARM64_INTRIN_VREV32_U8:
- case ARM64_INTRIN_VREV64_P16:
- case ARM64_INTRIN_VREV64_P8:
- case ARM64_INTRIN_VREV64_S16:
- case ARM64_INTRIN_VREV64_S32:
- case ARM64_INTRIN_VREV64_S8:
- case ARM64_INTRIN_VREV64_U16:
- case ARM64_INTRIN_VREV64_U32:
- case ARM64_INTRIN_VREV64_U8:
- case ARM64_INTRIN_VRHADD_S16:
- case ARM64_INTRIN_VRHADD_S32:
- case ARM64_INTRIN_VRHADD_S8:
- case ARM64_INTRIN_VRHADD_U16:
- case ARM64_INTRIN_VRHADD_U32:
- case ARM64_INTRIN_VRHADD_U8:
- case ARM64_INTRIN_VRSHL_S16:
- case ARM64_INTRIN_VRSHL_S32:
- case ARM64_INTRIN_VRSHL_S64:
- case ARM64_INTRIN_VRSHL_S8:
- case ARM64_INTRIN_VRSHL_U16:
- case ARM64_INTRIN_VRSHL_U32:
- case ARM64_INTRIN_VRSHL_U64:
- case ARM64_INTRIN_VRSHL_U8:
- case ARM64_INTRIN_VRSHLD_S64:
- case ARM64_INTRIN_VRSHLD_U64:
- case ARM64_INTRIN_VRSHR_N_S16:
- case ARM64_INTRIN_VRSHR_N_S32:
- case ARM64_INTRIN_VRSHR_N_S64:
- case ARM64_INTRIN_VRSHR_N_S8:
- case ARM64_INTRIN_VRSHR_N_U16:
- case ARM64_INTRIN_VRSHR_N_U32:
- case ARM64_INTRIN_VRSHR_N_U64:
- case ARM64_INTRIN_VRSHR_N_U8:
- case ARM64_INTRIN_VRSHRD_N_S64:
- case ARM64_INTRIN_VRSHRD_N_U64:
- case ARM64_INTRIN_VRSHRN_N_S16:
- case ARM64_INTRIN_VRSHRN_N_S32:
- case ARM64_INTRIN_VRSHRN_N_S64:
- case ARM64_INTRIN_VRSHRN_N_U16:
- case ARM64_INTRIN_VRSHRN_N_U32:
- case ARM64_INTRIN_VRSHRN_N_U64:
- case ARM64_INTRIN_VRSQRTE_U32:
- case ARM64_INTRIN_VRSRA_N_S16:
- case ARM64_INTRIN_VRSRA_N_S32:
- case ARM64_INTRIN_VRSRA_N_S64:
- case ARM64_INTRIN_VRSRA_N_S8:
- case ARM64_INTRIN_VRSRA_N_U16:
- case ARM64_INTRIN_VRSRA_N_U32:
- case ARM64_INTRIN_VRSRA_N_U64:
- case ARM64_INTRIN_VRSRA_N_U8:
- case ARM64_INTRIN_VRSRAD_N_S64:
- case ARM64_INTRIN_VRSRAD_N_U64:
- case ARM64_INTRIN_VRSUBHN_S16:
- case ARM64_INTRIN_VRSUBHN_S32:
- case ARM64_INTRIN_VRSUBHN_S64:
- case ARM64_INTRIN_VRSUBHN_U16:
- case ARM64_INTRIN_VRSUBHN_U32:
- case ARM64_INTRIN_VRSUBHN_U64:
- case ARM64_INTRIN_VSET_LANE_P16:
- case ARM64_INTRIN_VSET_LANE_P64:
- case ARM64_INTRIN_VSET_LANE_P8:
- case ARM64_INTRIN_VSET_LANE_S16:
- case ARM64_INTRIN_VSET_LANE_S32:
- case ARM64_INTRIN_VSET_LANE_S64:
- case ARM64_INTRIN_VSET_LANE_S8:
- case ARM64_INTRIN_VSET_LANE_U16:
- case ARM64_INTRIN_VSET_LANE_U32:
- case ARM64_INTRIN_VSET_LANE_U64:
- case ARM64_INTRIN_VSET_LANE_U8:
- case ARM64_INTRIN_VSHL_N_S16:
- case ARM64_INTRIN_VSHL_N_S32:
- case ARM64_INTRIN_VSHL_N_S64:
- case ARM64_INTRIN_VSHL_N_S8:
- case ARM64_INTRIN_VSHL_N_U16:
- case ARM64_INTRIN_VSHL_N_U32:
- case ARM64_INTRIN_VSHL_N_U64:
- case ARM64_INTRIN_VSHL_N_U8:
- case ARM64_INTRIN_VSHL_S16:
- case ARM64_INTRIN_VSHL_S32:
- case ARM64_INTRIN_VSHL_S64:
- case ARM64_INTRIN_VSHL_S8:
- case ARM64_INTRIN_VSHL_U16:
- case ARM64_INTRIN_VSHL_U32:
- case ARM64_INTRIN_VSHL_U64:
- case ARM64_INTRIN_VSHL_U8:
- case ARM64_INTRIN_VSHLD_N_S64:
- case ARM64_INTRIN_VSHLD_N_U64:
- case ARM64_INTRIN_VSHLD_S64:
- case ARM64_INTRIN_VSHLD_U64:
- case ARM64_INTRIN_VSHR_N_S16:
- case ARM64_INTRIN_VSHR_N_S32:
- case ARM64_INTRIN_VSHR_N_S64:
- case ARM64_INTRIN_VSHR_N_S8:
- case ARM64_INTRIN_VSHR_N_U16:
- case ARM64_INTRIN_VSHR_N_U32:
- case ARM64_INTRIN_VSHR_N_U64:
- case ARM64_INTRIN_VSHR_N_U8:
- case ARM64_INTRIN_VSHRD_N_S64:
- case ARM64_INTRIN_VSHRD_N_U64:
- case ARM64_INTRIN_VSHRN_N_S16:
- case ARM64_INTRIN_VSHRN_N_S32:
- case ARM64_INTRIN_VSHRN_N_S64:
- case ARM64_INTRIN_VSHRN_N_U16:
- case ARM64_INTRIN_VSHRN_N_U32:
- case ARM64_INTRIN_VSHRN_N_U64:
- case ARM64_INTRIN_VSLI_N_P16:
- case ARM64_INTRIN_VSLI_N_P64:
- case ARM64_INTRIN_VSLI_N_P8:
- case ARM64_INTRIN_VSLI_N_S16:
- case ARM64_INTRIN_VSLI_N_S32:
- case ARM64_INTRIN_VSLI_N_S64:
- case ARM64_INTRIN_VSLI_N_S8:
- case ARM64_INTRIN_VSLI_N_U16:
- case ARM64_INTRIN_VSLI_N_U32:
- case ARM64_INTRIN_VSLI_N_U64:
- case ARM64_INTRIN_VSLI_N_U8:
- case ARM64_INTRIN_VSLID_N_S64:
- case ARM64_INTRIN_VSLID_N_U64:
- case ARM64_INTRIN_VSQADD_U16:
- case ARM64_INTRIN_VSQADD_U32:
- case ARM64_INTRIN_VSQADD_U64:
- case ARM64_INTRIN_VSQADD_U8:
- case ARM64_INTRIN_VSQADDD_U64:
- case ARM64_INTRIN_VSRA_N_S16:
- case ARM64_INTRIN_VSRA_N_S32:
- case ARM64_INTRIN_VSRA_N_S64:
- case ARM64_INTRIN_VSRA_N_S8:
- case ARM64_INTRIN_VSRA_N_U16:
- case ARM64_INTRIN_VSRA_N_U32:
- case ARM64_INTRIN_VSRA_N_U64:
- case ARM64_INTRIN_VSRA_N_U8:
- case ARM64_INTRIN_VSRAD_N_S64:
- case ARM64_INTRIN_VSRAD_N_U64:
- case ARM64_INTRIN_VSRI_N_P16:
- case ARM64_INTRIN_VSRI_N_P64:
- case ARM64_INTRIN_VSRI_N_P8:
- case ARM64_INTRIN_VSRI_N_S16:
- case ARM64_INTRIN_VSRI_N_S32:
- case ARM64_INTRIN_VSRI_N_S64:
- case ARM64_INTRIN_VSRI_N_S8:
- case ARM64_INTRIN_VSRI_N_U16:
- case ARM64_INTRIN_VSRI_N_U32:
- case ARM64_INTRIN_VSRI_N_U64:
- case ARM64_INTRIN_VSRI_N_U8:
- case ARM64_INTRIN_VSRID_N_S64:
- case ARM64_INTRIN_VSRID_N_U64:
- case ARM64_INTRIN_VSUB_S16:
- case ARM64_INTRIN_VSUB_S32:
- case ARM64_INTRIN_VSUB_S64:
- case ARM64_INTRIN_VSUB_S8:
- case ARM64_INTRIN_VSUB_U16:
- case ARM64_INTRIN_VSUB_U32:
- case ARM64_INTRIN_VSUB_U64:
- case ARM64_INTRIN_VSUB_U8:
- case ARM64_INTRIN_VSUBD_S64:
- case ARM64_INTRIN_VSUBD_U64:
- case ARM64_INTRIN_VSUBHN_S16:
- case ARM64_INTRIN_VSUBHN_S32:
- case ARM64_INTRIN_VSUBHN_S64:
- case ARM64_INTRIN_VSUBHN_U16:
- case ARM64_INTRIN_VSUBHN_U32:
- case ARM64_INTRIN_VSUBHN_U64:
- case ARM64_INTRIN_VSUDOT_LANE_S32:
- case ARM64_INTRIN_VSUDOT_LANEQ_S32:
- case ARM64_INTRIN_VTRN1_P16:
- case ARM64_INTRIN_VTRN1_P8:
- case ARM64_INTRIN_VTRN1_S16:
- case ARM64_INTRIN_VTRN1_S32:
- case ARM64_INTRIN_VTRN1_S8:
- case ARM64_INTRIN_VTRN1_U16:
- case ARM64_INTRIN_VTRN1_U32:
- case ARM64_INTRIN_VTRN1_U8:
- case ARM64_INTRIN_VTRN2_P16:
- case ARM64_INTRIN_VTRN2_P8:
- case ARM64_INTRIN_VTRN2_S16:
- case ARM64_INTRIN_VTRN2_S32:
- case ARM64_INTRIN_VTRN2_S8:
- case ARM64_INTRIN_VTRN2_U16:
- case ARM64_INTRIN_VTRN2_U32:
- case ARM64_INTRIN_VTRN2_U8:
- case ARM64_INTRIN_VTST_P64:
- case ARM64_INTRIN_VTST_P8:
- case ARM64_INTRIN_VTST_S16:
- case ARM64_INTRIN_VTST_S32:
- case ARM64_INTRIN_VTST_S64:
- case ARM64_INTRIN_VTST_S8:
- case ARM64_INTRIN_VTST_U16:
- case ARM64_INTRIN_VTST_U32:
- case ARM64_INTRIN_VTST_U64:
- case ARM64_INTRIN_VTST_U8:
- case ARM64_INTRIN_VTSTD_S64:
- case ARM64_INTRIN_VTSTD_U64:
- case ARM64_INTRIN_VUQADD_S16:
- case ARM64_INTRIN_VUQADD_S32:
- case ARM64_INTRIN_VUQADD_S64:
- case ARM64_INTRIN_VUQADD_S8:
- case ARM64_INTRIN_VUQADDD_S64:
- case ARM64_INTRIN_VUSDOT_LANE_S32:
- case ARM64_INTRIN_VUSDOT_LANEQ_S32:
- case ARM64_INTRIN_VUSDOT_S32:
- case ARM64_INTRIN_VUZP1_P16:
- case ARM64_INTRIN_VUZP1_P8:
- case ARM64_INTRIN_VUZP1_S16:
- case ARM64_INTRIN_VUZP1_S32:
- case ARM64_INTRIN_VUZP1_S8:
- case ARM64_INTRIN_VUZP1_U16:
- case ARM64_INTRIN_VUZP1_U32:
- case ARM64_INTRIN_VUZP1_U8:
- case ARM64_INTRIN_VUZP2_P16:
- case ARM64_INTRIN_VUZP2_P8:
- case ARM64_INTRIN_VUZP2_S16:
- case ARM64_INTRIN_VUZP2_S32:
- case ARM64_INTRIN_VUZP2_S8:
- case ARM64_INTRIN_VUZP2_U16:
- case ARM64_INTRIN_VUZP2_U32:
- case ARM64_INTRIN_VUZP2_U8:
- case ARM64_INTRIN_VZIP1_P16:
- case ARM64_INTRIN_VZIP1_P8:
- case ARM64_INTRIN_VZIP1_S16:
- case ARM64_INTRIN_VZIP1_S32:
- case ARM64_INTRIN_VZIP1_S8:
- case ARM64_INTRIN_VZIP1_U16:
- case ARM64_INTRIN_VZIP1_U32:
- case ARM64_INTRIN_VZIP1_U8:
- case ARM64_INTRIN_VZIP2_P16:
- case ARM64_INTRIN_VZIP2_P8:
- case ARM64_INTRIN_VZIP2_S16:
- case ARM64_INTRIN_VZIP2_S32:
- case ARM64_INTRIN_VZIP2_S8:
- case ARM64_INTRIN_VZIP2_U16:
- case ARM64_INTRIN_VZIP2_U32:
- case ARM64_INTRIN_VZIP2_U8:
- return {Type::IntegerType(8, false)};
+ case ARM64_INTRIN_VABDQ_F16: // FABD Vd.8H,Vn.8H,Vm.8H float16x8_t vabdq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VABDQ_F32: // FABD Vd.4S,Vn.4S,Vm.4S float32x4_t vabdq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VABDQ_F64: // FABD Vd.2D,Vn.2D,Vm.2D float64x2_t vabdq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VABSQ_F16: // FABS Vd.8H,Vn.8H float16x8_t vabsq_f16(float16x8_t a)
+ case ARM64_INTRIN_VABSQ_F32: // FABS Vd.4S,Vn.4S float32x4_t vabsq_f32(float32x4_t a)
+ case ARM64_INTRIN_VABSQ_F64: // FABS Vd.2D,Vn.2D float64x2_t vabsq_f64(float64x2_t a)
+ case ARM64_INTRIN_VADDQ_F16: // FADD Vd.8H,Vn.8H,Vm.8H float16x8_t vaddq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VADDQ_F32: // FADD Vd.4S,Vn.4S,Vm.4S float32x4_t vaddq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VADDQ_F64: // FADD Vd.2D,Vn.2D,Vm.2D float64x2_t vaddq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VBFDOTQ_F32: // BFDOT Vd.4S,Vn.8H,Vm.8H float32x4_t vbfdotq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b)
+ case ARM64_INTRIN_VBFDOTQ_LANE_F32: // BFDOT Vd.4S,Vn.8H,Vm.2H[lane] float32x4_t vbfdotq_lane_f32(float32x4_t r, bfloat16x8_t a, bfloat16x4_t b, const int lane)
+ case ARM64_INTRIN_VBFDOTQ_LANEQ_F32: // BFDOT Vd.4S,Vn.8H,Vm.2H[lane] float32x4_t vbfdotq_laneq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b, const int lane)
+ case ARM64_INTRIN_VBFMLALBQ_F32: // BFMLALB Vd.4S,Vn.8H,Vm.8H float32x4_t vbfmlalbq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b)
+ case ARM64_INTRIN_VBFMLALBQ_LANE_F32: // BFMLALB Vd.4S,Vn.8H,Vm.H[lane] float32x4_t vbfmlalbq_lane_f32(float32x4_t r, bfloat16x8_t a, bfloat16x4_t b, const int lane)
+ case ARM64_INTRIN_VBFMLALBQ_LANEQ_F32: // BFMLALB Vd.4S,Vn.8H,Vm.H[lane] float32x4_t vbfmlalbq_laneq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b, const int lane)
+ case ARM64_INTRIN_VBFMLALTQ_F32: // BFMLALT Vd.4S,Vn.8H,Vm.8H float32x4_t vbfmlaltq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b)
+ case ARM64_INTRIN_VBFMLALTQ_LANE_F32: // BFMLALT Vd.4S,Vn.8H,Vm.H[lane] float32x4_t vbfmlaltq_lane_f32(float32x4_t r, bfloat16x8_t a, bfloat16x4_t b, const int lane)
+ case ARM64_INTRIN_VBFMLALTQ_LANEQ_F32: // BFMLALT Vd.4S,Vn.8H,Vm.H[lane] float32x4_t vbfmlaltq_laneq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b, const int lane)
+ case ARM64_INTRIN_VBFMMLAQ_F32: // BFMMLA Vd.4S,Vn.8H,Vm.8H float32x4_t vbfmmlaq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b)
+ case ARM64_INTRIN_VBSLQ_F16: // BSL Vd.16B,Vn.16B,Vm.16B float16x8_t vbslq_f16(uint16x8_t a, float16x8_t b, float16x8_t c)
+ case ARM64_INTRIN_VBSLQ_F32: // BSL Vd.16B,Vn.16B,Vm.16B float32x4_t vbslq_f32(uint32x4_t a, float32x4_t b, float32x4_t c)
+ case ARM64_INTRIN_VBSLQ_F64: // BSL Vd.16B,Vn.16B,Vm.16B float64x2_t vbslq_f64(uint64x2_t a, float64x2_t b, float64x2_t c)
+ case ARM64_INTRIN_VCADDQ_ROT270_F16: // FCADD Vd.8H,Vn.8H,Vm.8H,#270 float16x8_t vcaddq_rot270_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCADDQ_ROT270_F32: // FCADD Vd.4S,Vn.4S,Vm.4S,#270 float32x4_t vcaddq_rot270_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCADDQ_ROT270_F64: // FCADD Vd.2D,Vn.2D,Vm.2D,#270 float64x2_t vcaddq_rot270_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCADDQ_ROT90_F16: // FCADD Vd.8H,Vn.8H,Vm.8H,#90 float16x8_t vcaddq_rot90_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCADDQ_ROT90_F32: // FCADD Vd.4S,Vn.4S,Vm.4S,#90 float32x4_t vcaddq_rot90_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCADDQ_ROT90_F64: // FCADD Vd.2D,Vn.2D,Vm.2D,#90 float64x2_t vcaddq_rot90_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCMLAQ_F16: // FCMLA Vd.8H,Vn.8H,Vm.8H,#0 float16x8_t vcmlaq_f16(float16x8_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCMLAQ_F32: // FCMLA Vd.4S,Vn.4S,Vm.4S,#0 float32x4_t vcmlaq_f32(float32x4_t r, float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCMLAQ_F64: // FCMLA Vd.2D,Vn.2D,Vm.2D,#0 float64x2_t vcmlaq_f64(float64x2_t r, float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCMLAQ_LANE_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#0 float16x8_t vcmlaq_lane_f16(float16x8_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_LANE_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#0 float32x4_t vcmlaq_lane_f32(float32x4_t r, float32x4_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_LANEQ_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#0 float16x8_t vcmlaq_laneq_f16(float16x8_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_LANEQ_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#0 float32x4_t vcmlaq_laneq_f32(float32x4_t r, float32x4_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT180_F16: // FCMLA Vd.8H,Vn.8H,Vm.8H,#180 float16x8_t vcmlaq_rot180_f16(float16x8_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT180_F32: // FCMLA Vd.4S,Vn.4S,Vm.4S,#180 float32x4_t vcmlaq_rot180_f32(float32x4_t r, float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT180_F64: // FCMLA Vd.2D,Vn.2D,Vm.2D,#180 float64x2_t vcmlaq_rot180_f64(float64x2_t r, float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT180_LANE_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#180 float16x8_t vcmlaq_rot180_lane_f16(float16x8_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT180_LANE_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#180 float32x4_t vcmlaq_rot180_lane_f32(float32x4_t r, float32x4_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT180_LANEQ_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#180 float16x8_t vcmlaq_rot180_laneq_f16(float16x8_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT180_LANEQ_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#180 float32x4_t vcmlaq_rot180_laneq_f32(float32x4_t r, float32x4_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT270_F16: // FCMLA Vd.8H,Vn.8H,Vm.8H,#270 float16x8_t vcmlaq_rot270_f16(float16x8_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT270_F32: // FCMLA Vd.4S,Vn.4S,Vm.4S,#270 float32x4_t vcmlaq_rot270_f32(float32x4_t r, float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT270_F64: // FCMLA Vd.2D,Vn.2D,Vm.2D,#270 float64x2_t vcmlaq_rot270_f64(float64x2_t r, float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT270_LANE_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#270 float16x8_t vcmlaq_rot270_lane_f16(float16x8_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT270_LANE_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#270 float32x4_t vcmlaq_rot270_lane_f32(float32x4_t r, float32x4_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT270_LANEQ_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#270 float16x8_t vcmlaq_rot270_laneq_f16(float16x8_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT270_LANEQ_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#270 float32x4_t vcmlaq_rot270_laneq_f32(float32x4_t r, float32x4_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT90_F16: // FCMLA Vd.8H,Vn.8H,Vm.8H,#90 float16x8_t vcmlaq_rot90_f16(float16x8_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT90_F32: // FCMLA Vd.4S,Vn.4S,Vm.4S,#90 float32x4_t vcmlaq_rot90_f32(float32x4_t r, float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT90_F64: // FCMLA Vd.2D,Vn.2D,Vm.2D,#90 float64x2_t vcmlaq_rot90_f64(float64x2_t r, float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCMLAQ_ROT90_LANE_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#90 float16x8_t vcmlaq_rot90_lane_f16(float16x8_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT90_LANE_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#90 float32x4_t vcmlaq_rot90_lane_f32(float32x4_t r, float32x4_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT90_LANEQ_F16: // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#90 float16x8_t vcmlaq_rot90_laneq_f16(float16x8_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLAQ_ROT90_LANEQ_F32: // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#90 float32x4_t vcmlaq_rot90_laneq_f32(float32x4_t r, float32x4_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VCOMBINE_BF16: // INS Vd.D[1],Vm.D[0] bfloat16x8_t vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high)
+ case ARM64_INTRIN_VCOMBINE_F16: // INS Vd.D[1],Vm.D[0] float16x8_t vcombine_f16(float16x4_t low, float16x4_t high)
+ case ARM64_INTRIN_VCOMBINE_F32: // INS Vd.D[1],Vm.D[0] float32x4_t vcombine_f32(float32x2_t low, float32x2_t high)
+ case ARM64_INTRIN_VCOMBINE_F64: // INS Vd.D[1],Vm.D[0] float64x2_t vcombine_f64(float64x1_t low, float64x1_t high)
+ case ARM64_INTRIN_VCOPYQ_LANE_BF16: // INS Vd.H[lane1],Vn.H[lane2] bfloat16x8_t vcopyq_lane_bf16(bfloat16x8_t a, const int lane1, bfloat16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_F32: // INS Vd.S[lane1],Vn.S[lane2] float32x4_t vcopyq_lane_f32(float32x4_t a, const int lane1, float32x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_F64: // INS Vd.D[lane1],Vn.D[lane2] float64x2_t vcopyq_lane_f64(float64x2_t a, const int lane1, float64x1_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_BF16: // INS Vd.H[lane1],Vn.H[lane2] bfloat16x8_t vcopyq_laneq_bf16(bfloat16x8_t a, const int lane1, bfloat16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_F32: // INS Vd.S[lane1],Vn.S[lane2] float32x4_t vcopyq_laneq_f32(float32x4_t a, const int lane1, float32x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_F64: // INS Vd.D[lane1],Vn.D[lane2] float64x2_t vcopyq_laneq_f64(float64x2_t a, const int lane1, float64x2_t b, const int lane2)
+ case ARM64_INTRIN_VCVT_F32_BF16: // SHLL Vd.4S,Vn.8H,#16 float32x4_t vcvt_f32_bf16(bfloat16x4_t a)
+ case ARM64_INTRIN_VCVT_F32_F16: // FCVTL Vd.4S,Vn.4H float32x4_t vcvt_f32_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVT_F64_F32: // FCVTL Vd.2D,Vn.2S float64x2_t vcvt_f64_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVT_HIGH_F16_F32: // FCVTN2 Vd.8H,Vn.4S float16x8_t vcvt_high_f16_f32(float16x4_t r, float32x4_t a)
+ case ARM64_INTRIN_VCVT_HIGH_F32_F16: // FCVTL2 Vd.4S,Vn.8H float32x4_t vcvt_high_f32_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVT_HIGH_F32_F64: // FCVTN2 Vd.4S,Vn.2D float32x4_t vcvt_high_f32_f64(float32x2_t r, float64x2_t a)
+ case ARM64_INTRIN_VCVT_HIGH_F64_F32: // FCVTL2 Vd.2D,Vn.4S float64x2_t vcvt_high_f64_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTQ_F16_S16: // SCVTF Vd.8H,Vn.8H float16x8_t vcvtq_f16_s16(int16x8_t a)
+ // case ARM64_INTRIN_VCVTQ_F16_S16: // SCVTF Vd.8H,Vn.8H,#0 float16x8_t vcvtq_f16_s16(int16x8_t a)
+ case ARM64_INTRIN_VCVTQ_F16_U16: // UCVTF Vd.8H,Vn.8H float16x8_t vcvtq_f16_u16(uint16x8_t a)
+ case ARM64_INTRIN_VCVTQ_F32_S32: // SCVTF Vd.4S,Vn.4S float32x4_t vcvtq_f32_s32(int32x4_t a)
+ case ARM64_INTRIN_VCVTQ_F32_U32: // UCVTF Vd.4S,Vn.4S float32x4_t vcvtq_f32_u32(uint32x4_t a)
+ case ARM64_INTRIN_VCVTQ_F64_S64: // SCVTF Vd.2D,Vn.2D float64x2_t vcvtq_f64_s64(int64x2_t a)
+ case ARM64_INTRIN_VCVTQ_F64_U64: // UCVTF Vd.2D,Vn.2D float64x2_t vcvtq_f64_u64(uint64x2_t a)
+ case ARM64_INTRIN_VCVTQ_HIGH_BF16_F32: // BFCVTN2 Vd.8H,Vn.4S bfloat16x8_t vcvtq_high_bf16_f32(bfloat16x8_t inactive, float32x4_t a)
+ case ARM64_INTRIN_VCVTQ_HIGH_F32_BF16: // SHLL2 Vd.4S,Vn.8H,#16 float32x4_t vcvtq_high_f32_bf16(bfloat16x8_t a)
+ case ARM64_INTRIN_VCVTQ_LOW_BF16_F32: // BFCVTN Vd.4H,Vn.4S bfloat16x8_t vcvtq_low_bf16_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTQ_LOW_F32_BF16: // SHLL Vd.4S,Vn.8H,#16 float32x4_t vcvtq_low_f32_bf16(bfloat16x8_t a)
+ case ARM64_INTRIN_VCVTQ_N_F16_S16: // SCVTF Vd.8H,Vn.8H,#n float16x8_t vcvtq_n_f16_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_F16_U16: // UCVTF Vd.8H,Vn.8H,#n float16x8_t vcvtq_n_f16_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_F32_S32: // SCVTF Vd.4S,Vn.4S,#n float32x4_t vcvtq_n_f32_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_F32_U32: // UCVTF Vd.4S,Vn.4S,#n float32x4_t vcvtq_n_f32_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_F64_S64: // SCVTF Vd.2D,Vn.2D,#n float64x2_t vcvtq_n_f64_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_F64_U64: // UCVTF Vd.2D,Vn.2D,#n float64x2_t vcvtq_n_f64_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VCVTX_HIGH_F32_F64: // FCVTXN2 Vd.4S,Vn.2D float32x4_t vcvtx_high_f32_f64(float32x2_t r, float64x2_t a)
+ case ARM64_INTRIN_VDIVQ_F16: // FDIV Vd.8H,Vn.8H,Vm.8H float16x8_t vdivq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VDIVQ_F32: // FDIV Vd.4S,Vn.4S,Vm.4S float32x4_t vdivq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VDIVQ_F64: // FDIV Vd.2D,Vn.2D,Vm.2D float64x2_t vdivq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VDUPQ_LANE_BF16: // DUP Vd.8H,Vn.H[lane] bfloat16x8_t vdupq_lane_bf16(bfloat16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_F16: // DUP Vd.8H,Vn.H[lane] float16x8_t vdupq_lane_f16(float16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_F32: // DUP Vd.4S,Vn.S[lane] float32x4_t vdupq_lane_f32(float32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_F64: // DUP Vd.2D,Vn.D[lane] float64x2_t vdupq_lane_f64(float64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_BF16: // DUP Vd.8H,Vn.H[lane] bfloat16x8_t vdupq_laneq_bf16(bfloat16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_F16: // DUP Vd.8H,Vn.H[lane] float16x8_t vdupq_laneq_f16(float16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_F32: // DUP Vd.4S,Vn.S[lane] float32x4_t vdupq_laneq_f32(float32x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_F64: // DUP Vd.2D,Vn.D[lane] float64x2_t vdupq_laneq_f64(float64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_N_BF16: // DUP Vd.8H,rn bfloat16x8_t vdupq_n_bf16(bfloat16_t value)
+ case ARM64_INTRIN_VDUPQ_N_F16: // DUP Vd.8H,rn float16x8_t vdupq_n_f16(float16_t value)
+ case ARM64_INTRIN_VDUPQ_N_F32: // DUP Vd.4S,rn float32x4_t vdupq_n_f32(float32_t value)
+ case ARM64_INTRIN_VDUPQ_N_F64: // DUP Vd.2D,rn float64x2_t vdupq_n_f64(float64_t value)
+ case ARM64_INTRIN_VEXTQ_F16: // EXT Vd.16B,Vn.16B,Vm.16B,#n float16x8_t vextq_f16(float16x8_t a, float16x8_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_F32: // EXT Vd.16B,Vn.16B,Vm.16B,#n float32x4_t vextq_f32(float32x4_t a, float32x4_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_F64: // EXT Vd.16B,Vn.16B,Vm.16B,#n float64x2_t vextq_f64(float64x2_t a, float64x2_t b, const int n)
+ case ARM64_INTRIN_VFMAQ_F16: // FMLA Vd.8H,Vn.8H,Vm.8H float16x8_t vfmaq_f16(float16x8_t a, float16x8_t b, float16x8_t c)
+ case ARM64_INTRIN_VFMAQ_F32: // FMLA Vd.4S,Vn.4S,Vm.4S float32x4_t vfmaq_f32(float32x4_t a, float32x4_t b, float32x4_t c)
+ case ARM64_INTRIN_VFMAQ_F64: // FMLA Vd.2D,Vn.2D,Vm.2D float64x2_t vfmaq_f64(float64x2_t a, float64x2_t b, float64x2_t c)
+ case ARM64_INTRIN_VFMAQ_LANE_F16: // FMLA Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vfmaq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VFMAQ_LANE_F32: // FMLA Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vfmaq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VFMAQ_LANE_F64: // FMLA Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vfmaq_lane_f64(float64x2_t a, float64x2_t b, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VFMAQ_LANEQ_F16: // FMLA Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vfmaq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VFMAQ_LANEQ_F32: // FMLA Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vfmaq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VFMAQ_LANEQ_F64: // FMLA Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vfmaq_laneq_f64(float64x2_t a, float64x2_t b, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VFMAQ_N_F16: // FMLA Vd.8H,Vn.8H,Vm.H[0] float16x8_t vfmaq_n_f16(float16x8_t a, float16x8_t b, float16_t n)
+ case ARM64_INTRIN_VFMAQ_N_F32: // FMLA Vd.4S,Vn.4S,Vm.S[0] float32x4_t vfmaq_n_f32(float32x4_t a, float32x4_t b, float32_t n)
+ case ARM64_INTRIN_VFMAQ_N_F64: // FMLA Vd.2D,Vn.2D,Vm.D[0] float64x2_t vfmaq_n_f64(float64x2_t a, float64x2_t b, float64_t n)
+ case ARM64_INTRIN_VFMLALQ_HIGH_F16: // FMLAL2 Vd.4S,Vn.4H,Vm.4H float32x4_t vfmlalq_high_f16(float32x4_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VFMLALQ_LANE_HIGH_F16: // FMLAL2 Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlalq_lane_high_f16(float32x4_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMLALQ_LANE_LOW_F16: // FMLAL Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlalq_lane_low_f16(float32x4_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMLALQ_LANEQ_HIGH_F16: // FMLAL2 Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlalq_laneq_high_f16(float32x4_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMLALQ_LANEQ_LOW_F16: // FMLAL Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlalq_laneq_low_f16(float32x4_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMLALQ_LOW_F16: // FMLAL Vd.4S,Vn.4H,Vm.4H float32x4_t vfmlalq_low_f16(float32x4_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VFMLSLQ_HIGH_F16: // FMLSL2 Vd.4S,Vn.4H,Vm.4H float32x4_t vfmlslq_high_f16(float32x4_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VFMLSLQ_LANE_HIGH_F16: // FMLSL2 Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlslq_lane_high_f16(float32x4_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMLSLQ_LANE_LOW_F16: // FMLSL Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlslq_lane_low_f16(float32x4_t r, float16x8_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMLSLQ_LANEQ_HIGH_F16: // FMLSL2 Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlslq_laneq_high_f16(float32x4_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMLSLQ_LANEQ_LOW_F16: // FMLSL Vd.4S,Vn.4H,Vm.H[lane] float32x4_t vfmlslq_laneq_low_f16(float32x4_t r, float16x8_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMLSLQ_LOW_F16: // FMLSL Vd.4S,Vn.4H,Vm.4H float32x4_t vfmlslq_low_f16(float32x4_t r, float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VFMSQ_F16: // FMLS Vd.8H,Vn.8H,Vm.8H float16x8_t vfmsq_f16(float16x8_t a, float16x8_t b, float16x8_t c)
+ case ARM64_INTRIN_VFMSQ_F32: // FMLS Vd.4S,Vn.4S,Vm.4S float32x4_t vfmsq_f32(float32x4_t a, float32x4_t b, float32x4_t c)
+ case ARM64_INTRIN_VFMSQ_F64: // FMLS Vd.2D,Vn.2D,Vm.2D float64x2_t vfmsq_f64(float64x2_t a, float64x2_t b, float64x2_t c)
+ case ARM64_INTRIN_VFMSQ_LANE_F16: // FMLS Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vfmsq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VFMSQ_LANE_F32: // FMLS Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vfmsq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VFMSQ_LANE_F64: // FMLS Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vfmsq_lane_f64(float64x2_t a, float64x2_t b, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VFMSQ_LANEQ_F16: // FMLS Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vfmsq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VFMSQ_LANEQ_F32: // FMLS Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vfmsq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VFMSQ_LANEQ_F64: // FMLS Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vfmsq_laneq_f64(float64x2_t a, float64x2_t b, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VFMSQ_N_F16: // FMLS Vd.8H,Vn.8H,Vm.H[0] float16x8_t vfmsq_n_f16(float16x8_t a, float16x8_t b, float16_t n)
+ case ARM64_INTRIN_VFMSQ_N_F32: // FMLS Vd.4S,Vn.4S,Vm.S[0] float32x4_t vfmsq_n_f32(float32x4_t a, float32x4_t b, float32_t n)
+ case ARM64_INTRIN_VFMSQ_N_F64: // FMLS Vd.2D,Vn.2D,Vm.D[0] float64x2_t vfmsq_n_f64(float64x2_t a, float64x2_t b, float64_t n)
+ case ARM64_INTRIN_VMAXNMQ_F16: // FMAXNM Vd.8H,Vn.8H,Vm.8H float16x8_t vmaxnmq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VMAXNMQ_F32: // FMAXNM Vd.4S,Vn.4S,Vm.4S float32x4_t vmaxnmq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VMAXNMQ_F64: // FMAXNM Vd.2D,Vn.2D,Vm.2D float64x2_t vmaxnmq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VMAXQ_F16: // FMAX Vd.8H,Vn.8H,Vm.8H float16x8_t vmaxq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VMAXQ_F32: // FMAX Vd.4S,Vn.4S,Vm.4S float32x4_t vmaxq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VMAXQ_F64: // FMAX Vd.2D,Vn.2D,Vm.2D float64x2_t vmaxq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VMINNMQ_F16: // FMINNM Vd.8H,Vn.8H,Vm.8H float16x8_t vminnmq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VMINNMQ_F32: // FMINNM Vd.4S,Vn.4S,Vm.4S float32x4_t vminnmq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VMINNMQ_F64: // FMINNM Vd.2D,Vn.2D,Vm.2D float64x2_t vminnmq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VMINQ_F16: // FMIN Vd.8H,Vn.8H,Vm.8H float16x8_t vminq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VMINQ_F32: // FMIN Vd.4S,Vn.4S,Vm.4S float32x4_t vminq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VMINQ_F64: // FMIN Vd.2D,Vn.2D,Vm.2D float64x2_t vminq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VMOVQ_N_F16: // DUP Vd.8H,rn float16x8_t vmovq_n_f16(float16_t value)
+ case ARM64_INTRIN_VMOVQ_N_F32: // DUP Vd.4S,rn float32x4_t vmovq_n_f32(float32_t value)
+ case ARM64_INTRIN_VMOVQ_N_F64: // DUP Vd.2D,rn float64x2_t vmovq_n_f64(float64_t value)
+ case ARM64_INTRIN_VMULQ_F16: // FMUL Vd.8H,Vn.8H,Vm.8H float16x8_t vmulq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VMULQ_F32: // FMUL Vd.4S,Vn.4S,Vm.4S float32x4_t vmulq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VMULQ_F64: // FMUL Vd.2D,Vn.2D,Vm.2D float64x2_t vmulq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VMULQ_LANE_F16: // FMUL Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vmulq_lane_f16(float16x8_t a, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANE_F32: // FMUL Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vmulq_lane_f32(float32x4_t a, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANE_F64: // FMUL Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vmulq_lane_f64(float64x2_t a, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANEQ_F16: // FMUL Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vmulq_laneq_f16(float16x8_t a, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANEQ_F32: // FMUL Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vmulq_laneq_f32(float32x4_t a, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANEQ_F64: // FMUL Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vmulq_laneq_f64(float64x2_t a, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_N_F16: // FMUL Vd.8H,Vn.8H,Vm.H[0] float16x8_t vmulq_n_f16(float16x8_t a, float16_t n)
+ case ARM64_INTRIN_VMULQ_N_F32: // FMUL Vd.4S,Vn.4S,Vm.S[0] float32x4_t vmulq_n_f32(float32x4_t a, float32_t b)
+ case ARM64_INTRIN_VMULQ_N_F64: // FMUL Vd.2D,Vn.2D,Vm.D[0] float64x2_t vmulq_n_f64(float64x2_t a, float64_t b)
+ case ARM64_INTRIN_VMULXQ_F16: // FMULX Vd.8H,Vn.8H,Vm.8H float16x8_t vmulxq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VMULXQ_F32: // FMULX Vd.4S,Vn.4S,Vm.4S float32x4_t vmulxq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VMULXQ_F64: // FMULX Vd.2D,Vn.2D,Vm.2D float64x2_t vmulxq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VMULXQ_LANE_F16: // FMULX Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vmulxq_lane_f16(float16x8_t a, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULXQ_LANE_F32: // FMULX Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vmulxq_lane_f32(float32x4_t a, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULXQ_LANE_F64: // FMULX Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vmulxq_lane_f64(float64x2_t a, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VMULXQ_LANEQ_F16: // FMULX Vd.8H,Vn.8H,Vm.H[lane] float16x8_t vmulxq_laneq_f16(float16x8_t a, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULXQ_LANEQ_F32: // FMULX Vd.4S,Vn.4S,Vm.S[lane] float32x4_t vmulxq_laneq_f32(float32x4_t a, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULXQ_LANEQ_F64: // FMULX Vd.2D,Vn.2D,Vm.D[lane] float64x2_t vmulxq_laneq_f64(float64x2_t a, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VMULXQ_N_F16: // FMULX Vd.8H,Vn.8H,Vm.H[0] float16x8_t vmulxq_n_f16(float16x8_t a, float16_t n)
+ case ARM64_INTRIN_VNEGQ_F16: // FNEG Vd.8H,Vn.8H float16x8_t vnegq_f16(float16x8_t a)
+ case ARM64_INTRIN_VNEGQ_F32: // FNEG Vd.4S,Vn.4S float32x4_t vnegq_f32(float32x4_t a)
+ case ARM64_INTRIN_VNEGQ_F64: // FNEG Vd.2D,Vn.2D float64x2_t vnegq_f64(float64x2_t a)
+ case ARM64_INTRIN_VPADDQ_F16: // FADDP Vd.8H,Vn.8H,Vm.8H float16x8_t vpaddq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VPADDQ_F32: // FADDP Vd.4S,Vn.4S,Vm.4S float32x4_t vpaddq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VPADDQ_F64: // FADDP Vd.2D,Vn.2D,Vm.2D float64x2_t vpaddq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VPMAXNMQ_F16: // FMAXNMP Vd.8H,Vn.8H,Vm.8H float16x8_t vpmaxnmq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VPMAXNMQ_F32: // FMAXNMP Vd.4S,Vn.4S,Vm.4S float32x4_t vpmaxnmq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VPMAXNMQ_F64: // FMAXNMP Vd.2D,Vn.2D,Vm.2D float64x2_t vpmaxnmq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VPMAXQ_F16: // FMAXP Vd.8H,Vn.8H,Vm.8H float16x8_t vpmaxq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VPMAXQ_F32: // FMAXP Vd.4S,Vn.4S,Vm.4S float32x4_t vpmaxq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VPMAXQ_F64: // FMAXP Vd.2D,Vn.2D,Vm.2D float64x2_t vpmaxq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VPMINNMQ_F16: // FMINNMP Vd.8H,Vn.8H,Vm.8H float16x8_t vpminnmq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VPMINNMQ_F32: // FMINNMP Vd.4S,Vn.4S,Vm.4S float32x4_t vpminnmq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VPMINNMQ_F64: // FMINNMP Vd.2D,Vn.2D,Vm.2D float64x2_t vpminnmq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VPMINQ_F16: // FMINP Vd.8H,Vn.8H,Vm.8H float16x8_t vpminq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VPMINQ_F32: // FMINP Vd.4S,Vn.4S,Vm.4S float32x4_t vpminq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VPMINQ_F64: // FMINP Vd.2D,Vn.2D,Vm.2D float64x2_t vpminq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VRECPEQ_F16: // FRECPE Vd.8H,Vn.8H float16x8_t vrecpeq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRECPEQ_F32: // FRECPE Vd.4S,Vn.4S float32x4_t vrecpeq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRECPEQ_F64: // FRECPE Vd.2D,Vn.2D float64x2_t vrecpeq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRECPSQ_F16: // FRECPS Vd.8H,Vn.8H,Vm.8H float16x8_t vrecpsq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VRECPSQ_F32: // FRECPS Vd.4S,Vn.4S,Vm.4S float32x4_t vrecpsq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VRECPSQ_F64: // FRECPS Vd.2D,Vn.2D,Vm.2D float64x2_t vrecpsq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VREV64Q_F16: // REV64 Vd.8H,Vn.8H float16x8_t vrev64q_f16(float16x8_t vec)
+ case ARM64_INTRIN_VREV64Q_F32: // REV64 Vd.4S,Vn.4S float32x4_t vrev64q_f32(float32x4_t vec)
+ case ARM64_INTRIN_VRND32XQ_F32: // FRINT32X Vd.4S,Vn.4S float32x4_t vrnd32xq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRND32XQ_F64: // FRINT32X Vd.2D,Vn.2D float64x2_t vrnd32xq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRND32ZQ_F32: // FRINT32Z Vd.4S,Vn.4S float32x4_t vrnd32zq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRND32ZQ_F64: // FRINT32Z Vd.2D,Vn.2D float64x2_t vrnd32zq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRND64XQ_F32: // FRINT64X Vd.4S,Vn.4S float32x4_t vrnd64xq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRND64XQ_F64: // FRINT64X Vd.2D,Vn.2D float64x2_t vrnd64xq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRND64ZQ_F32: // FRINT64Z Vd.4S,Vn.4S float32x4_t vrnd64zq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRND64ZQ_F64: // FRINT64Z Vd.2D,Vn.2D float64x2_t vrnd64zq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRNDAQ_F16: // FRINTA Vd.8H,Vn.8H float16x8_t vrndaq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRNDAQ_F32: // FRINTA Vd.4S,Vn.4S float32x4_t vrndaq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRNDAQ_F64: // FRINTA Vd.2D,Vn.2D float64x2_t vrndaq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRNDIQ_F16: // FRINTI Vd.8H,Vn.8H float16x8_t vrndiq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRNDIQ_F32: // FRINTI Vd.4S,Vn.4S float32x4_t vrndiq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRNDIQ_F64: // FRINTI Vd.2D,Vn.2D float64x2_t vrndiq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRNDMQ_F16: // FRINTM Vd.8H,Vn.8H float16x8_t vrndmq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRNDMQ_F32: // FRINTM Vd.4S,Vn.4S float32x4_t vrndmq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRNDMQ_F64: // FRINTM Vd.2D,Vn.2D float64x2_t vrndmq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRNDNQ_F16: // FRINTN Vd.8H,Vn.8H float16x8_t vrndnq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRNDNQ_F32: // FRINTN Vd.4S,Vn.4S float32x4_t vrndnq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRNDNQ_F64: // FRINTN Vd.2D,Vn.2D float64x2_t vrndnq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRNDPQ_F16: // FRINTP Vd.8H,Vn.8H float16x8_t vrndpq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRNDPQ_F32: // FRINTP Vd.4S,Vn.4S float32x4_t vrndpq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRNDPQ_F64: // FRINTP Vd.2D,Vn.2D float64x2_t vrndpq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRNDQ_F16: // FRINTZ Vd.8H,Vn.8H float16x8_t vrndq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRNDQ_F32: // FRINTZ Vd.4S,Vn.4S float32x4_t vrndq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRNDQ_F64: // FRINTZ Vd.2D,Vn.2D float64x2_t vrndq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRNDXQ_F16: // FRINTX Vd.8H,Vn.8H float16x8_t vrndxq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRNDXQ_F32: // FRINTX Vd.4S,Vn.4S float32x4_t vrndxq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRNDXQ_F64: // FRINTX Vd.2D,Vn.2D float64x2_t vrndxq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRSQRTEQ_F16: // FRSQRTE Vd.8H,Vn.8H float16x8_t vrsqrteq_f16(float16x8_t a)
+ case ARM64_INTRIN_VRSQRTEQ_F32: // FRSQRTE Vd.4S,Vn.4S float32x4_t vrsqrteq_f32(float32x4_t a)
+ case ARM64_INTRIN_VRSQRTEQ_F64: // FRSQRTE Vd.2D,Vn.2D float64x2_t vrsqrteq_f64(float64x2_t a)
+ case ARM64_INTRIN_VRSQRTSQ_F16: // FRSQRTS Vd.8H,Vn.8H,Vm.8H float16x8_t vrsqrtsq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VRSQRTSQ_F32: // FRSQRTS Vd.4S,Vn.4S,Vm.4S float32x4_t vrsqrtsq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VRSQRTSQ_F64: // FRSQRTS Vd.2D,Vn.2D,Vm.2D float64x2_t vrsqrtsq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VSETQ_LANE_BF16: // INS Vd.H[lane],Vn.H[0] bfloat16x8_t vsetq_lane_bf16(bfloat16_t a, bfloat16x8_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_F16: // MOV Vd.H[lane],Vn.H[0] float16x8_t vsetq_lane_f16(float16_t a, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_F32: // MOV Vd.S[lane],Rn float32x4_t vsetq_lane_f32(float32_t a, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_F64: // MOV Vd.D[lane],Rn float64x2_t vsetq_lane_f64(float64_t a, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VSQRTQ_F16: // FSQRT Vd.8H,Vn.8H float16x8_t vsqrtq_f16(float16x8_t a)
+ case ARM64_INTRIN_VSQRTQ_F32: // FSQRT Vd.4S,Vn.4S float32x4_t vsqrtq_f32(float32x4_t a)
+ case ARM64_INTRIN_VSQRTQ_F64: // FSQRT Vd.2D,Vn.2D float64x2_t vsqrtq_f64(float64x2_t a)
+ case ARM64_INTRIN_VSUBQ_F16: // FSUB Vd.8H,Vn.8H,Vm.8H float16x8_t vsubq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VSUBQ_F32: // FSUB Vd.4S,Vn.4S,Vm.4S float32x4_t vsubq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VSUBQ_F64: // FSUB Vd.2D,Vn.2D,Vm.2D float64x2_t vsubq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VTRN1Q_F16: // TRN1 Vd.8H,Vn.8H,Vm.8H float16x8_t vtrn1q_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VTRN1Q_F32: // TRN1 Vd.4S,Vn.4S,Vm.4S float32x4_t vtrn1q_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VTRN1Q_F64: // TRN1 Vd.2D,Vn.2D,Vm.2D float64x2_t vtrn1q_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VTRN2Q_F16: // TRN2 Vd.8H,Vn.8H,Vm.8H float16x8_t vtrn2q_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VTRN2Q_F32: // TRN2 Vd.4S,Vn.4S,Vm.4S float32x4_t vtrn2q_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VTRN2Q_F64: // TRN2 Vd.2D,Vn.2D,Vm.2D float64x2_t vtrn2q_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VUZP1Q_F16: // UZP1 Vd.8H,Vn.8H,Vm.8H float16x8_t vuzp1q_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VUZP1Q_F32: // UZP1 Vd.4S,Vn.4S,Vm.4S float32x4_t vuzp1q_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VUZP1Q_F64: // UZP1 Vd.2D,Vn.2D,Vm.2D float64x2_t vuzp1q_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VUZP2Q_F16: // UZP2 Vd.8H,Vn.8H,Vm.8H float16x8_t vuzp2q_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VUZP2Q_F32: // UZP2 Vd.4S,Vn.4S,Vm.4S float32x4_t vuzp2q_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VUZP2Q_F64: // UZP2 Vd.2D,Vn.2D,Vm.2D float64x2_t vuzp2q_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VZIP1Q_F16: // ZIP1 Vd.8H,Vn.8H,Vm.8H float16x8_t vzip1q_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VZIP1Q_F32: // ZIP1 Vd.4S,Vn.4S,Vm.4S float32x4_t vzip1q_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VZIP1Q_F64: // ZIP1 Vd.2D,Vn.2D,Vm.2D float64x2_t vzip1q_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VZIP2Q_F16: // ZIP2 Vd.8H,Vn.8H,Vm.8H float16x8_t vzip2q_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VZIP2Q_F32: // ZIP2 Vd.4S,Vn.4S,Vm.4S float32x4_t vzip2q_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VZIP2Q_F64: // ZIP2 Vd.2D,Vn.2D,Vm.2D float64x2_t vzip2q_f64(float64x2_t a, float64x2_t b)
+ return {Type::FloatType(16)};
+ case ARM64_INTRIN_VTRNQ_F16: // TRN1 Vd1.8H,Vn.8H,Vm.8H float16x8x2_t vtrnq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VTRNQ_F32: // TRN1 Vd1.4S,Vn.4S,Vm.4S float32x4x2_t vtrnq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VUZPQ_F16: // UZP1 Vd1.8H,Vn.8H,Vm.8H float16x8x2_t vuzpq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VUZPQ_F32: // UZP1 Vd1.4S,Vn.4S,Vm.4S float32x4x2_t vuzpq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VZIPQ_F16: // ZIP1 Vd1.8H,Vn.8H,Vm.8H float16x8x2_t vzipq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VZIPQ_F32: // ZIP1 Vd1.4S,Vn.4S,Vm.4S float32x4x2_t vzipq_f32(float32x4_t a, float32x4_t b)
+ return {Type::FloatType(16), Type::FloatType(16)};
+ case ARM64_INTRIN_VABDH_F16: // FABD Hd,Hn,Hm float16_t vabdh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VABSH_F16: // FABS Hd,Hn float16_t vabsh_f16(float16_t a)
+ case ARM64_INTRIN_VADDH_F16: // FADD Hd,Hn,Hm float16_t vaddh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCVTH_BF16_F32: // BFCVT Hd,Sn bfloat16_t vcvth_bf16_f32(float32_t a)
+ case ARM64_INTRIN_VCVTH_F16_S16: // SCVTF Hd,Hn float16_t vcvth_f16_s16(int16_t a)
+ case ARM64_INTRIN_VCVTH_F16_S32: // SCVTF Hd,Hn float16_t vcvth_f16_s32(int32_t a)
+ case ARM64_INTRIN_VCVTH_F16_S64: // SCVTF Hd,Hn float16_t vcvth_f16_s64(int64_t a)
+ case ARM64_INTRIN_VCVTH_F16_U16: // UCVTF Hd,Hn float16_t vcvth_f16_u16(uint16_t a)
+ case ARM64_INTRIN_VCVTH_F16_U32: // UCVTF Hd,Hn float16_t vcvth_f16_u32(uint32_t a)
+ case ARM64_INTRIN_VCVTH_F16_U64: // UCVTF Hd,Hn float16_t vcvth_f16_u64(uint64_t a)
+ case ARM64_INTRIN_VCVTH_N_F16_S16: // SCVTF Hd,Hn,#n float16_t vcvth_n_f16_s16(int16_t a, const int n)
+ case ARM64_INTRIN_VCVTH_N_F16_S32: // SCVTF Hd,Hn,#n float16_t vcvth_n_f16_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VCVTH_N_F16_S64: // SCVTF Hd,Hn,#n float16_t vcvth_n_f16_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VCVTH_N_F16_U16: // UCVTF Hd,Hn,#n float16_t vcvth_n_f16_u16(uint16_t a, const int n)
+ case ARM64_INTRIN_VCVTH_N_F16_U32: // UCVTF Hd,Hn,#n float16_t vcvth_n_f16_u32(uint32_t a, const int n)
+ case ARM64_INTRIN_VCVTH_N_F16_U64: // UCVTF Hd,Hn,#n float16_t vcvth_n_f16_u64(uint64_t a, const int n)
+ case ARM64_INTRIN_VDIVH_F16: // FDIV Hd,Hn,Hm float16_t vdivh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VDUPH_LANE_BF16: // DUP Hd,Vn.H[lane] bfloat16_t vduph_lane_bf16(bfloat16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANE_F16: // DUP Hd,Vn.H[lane] float16_t vduph_lane_f16(float16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANEQ_BF16: // DUP Hd,Vn.H[lane] bfloat16_t vduph_laneq_bf16(bfloat16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANEQ_F16: // DUP Hd,Vn.H[lane] float16_t vduph_laneq_f16(float16x8_t vec, const int lane)
+ case ARM64_INTRIN_VFMAH_F16: // FMADD Hd,Hn,Hm,Ha float16_t vfmah_f16(float16_t a, float16_t b, float16_t c)
+ case ARM64_INTRIN_VFMAH_LANE_F16: // FMLA Hd,Hn,Vm.H[lane] float16_t vfmah_lane_f16(float16_t a, float16_t b, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VFMAH_LANEQ_F16: // FMLA Hd,Hn,Vm.H[lane] float16_t vfmah_laneq_f16(float16_t a, float16_t b, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VFMSH_F16: // FMSUB Hd,Hn,Hm,Ha float16_t vfmsh_f16(float16_t a, float16_t b, float16_t c)
+ case ARM64_INTRIN_VFMSH_LANE_F16: // FMLS Hd,Hn,Vm.H[lane] float16_t vfmsh_lane_f16(float16_t a, float16_t b, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VFMSH_LANEQ_F16: // FMLS Hd,Hn,Vm.H[lane] float16_t vfmsh_laneq_f16(float16_t a, float16_t b, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_BF16: // DUP Hd,Vn.H[lane] bfloat16_t vget_lane_bf16(bfloat16x4_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_F16: // DUP Hd,Vn.H[lane] float16_t vget_lane_f16(float16x4_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_BF16: // DUP Hd,Vn.H[lane] bfloat16_t vgetq_lane_bf16(bfloat16x8_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_F16: // DUP Hd,Vn.H[lane] float16_t vgetq_lane_f16(float16x8_t v, const int lane)
+ case ARM64_INTRIN_VMAXH_F16: // FMAX Hd,Hn,Hm float16_t vmaxh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VMAXNMH_F16: // FMAXNM Hd,Hn,Hm float16_t vmaxnmh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VMAXNMV_F16: // FMAXNMP Hd,Vn.2H float16_t vmaxnmv_f16(float16x2_t a)
+ // case ARM64_INTRIN_VMAXNMV_F16: // FMAXNMP Hd,Vn.4H float16_t vmaxnmv_f16(float16x4_t a)
+ case ARM64_INTRIN_VMAXNMVQ_F16: // FMAXNMP Hd,Vn.8H float16_t vmaxnmvq_f16(float16x8_t a)
+ // case ARM64_INTRIN_VMAXNMVQ_F16: // FMAXNMV Hd,Hn.4H float16_t vmaxnmvq_f16(float16x4_t a)
+ // case ARM64_INTRIN_VMAXNMVQ_F16: // FMAXNMV Hd,Hn.8H float16_t vmaxnmvq_f16(float16x8_t a)
+ case ARM64_INTRIN_VMAXV_F16: // FMAXP Hd,Vn.4H float16_t vmaxv_f16(float16x4_t a)
+ case ARM64_INTRIN_VMAXVQ_F16: // FMAXP Hd,Vn.8H float16_t vmaxvq_f16(float16x8_t a)
+ // case ARM64_INTRIN_VMAXVQ_F16: // FMAXV Hd,Hn.4H float16_t vmaxvq_f16(float16x4_t a)
+ // case ARM64_INTRIN_VMAXVQ_F16: // FMAXV Hd,Hn.8H float16_t vmaxvq_f16(float16x8_t a)
+ case ARM64_INTRIN_VMINH_F16: // FMIN Hd,Hn,Hm float16_t vminh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VMINNMH_F16: // FMINNM Hd,Hn,Hm float16_t vminnmh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VMINNMV_F16: // FMINNMP Hd,Vn.2H float16_t vminnmv_f16(float16x2_t a)
+ // case ARM64_INTRIN_VMINNMV_F16: // FMINNMP Hd,Vn.4H float16_t vminnmv_f16(float16x4_t a)
+ // case ARM64_INTRIN_VMINNMV_F16: // FMINNMV Hd,Vn.4H float16_t vminnmv_f16(float16x4_t a)
+ case ARM64_INTRIN_VMINNMVQ_F16: // FMINNMP Hd,Vn.8H float16_t vminnmvq_f16(float16x8_t a)
+ // case ARM64_INTRIN_VMINNMVQ_F16: // FMINNMV Hd,Vn.8H float16_t vminnmvq_f16(float16x8_t a)
+ case ARM64_INTRIN_VMINV_F16: // FMINP Hd,Vn.4H float16_t vminv_f16(float16x4_t a)
+ // case ARM64_INTRIN_VMINV_F16: // FMINV Hd,Vn.4H float16_t vminv_f16(float16x4_t a)
+ case ARM64_INTRIN_VMINVQ_F16: // FMINP Hd,Vn.8H float16_t vminvq_f16(float16x8_t a)
+ // case ARM64_INTRIN_VMINVQ_F16: // FMINV Hd,Vn.8H float16_t vminvq_f16(float16x8_t a)
+ case ARM64_INTRIN_VMULH_F16: // FMUL Hd,Hn,Hm float16_t vmulh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VMULH_LANE_F16: // FMUL Hd,Hn,Vm.H[lane] float16_t vmulh_lane_f16(float16_t a, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULH_LANEQ_F16: // FMUL Hd,Hn,Vm.H[lane] float16_t vmulh_laneq_f16(float16_t a, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULXH_F16: // FMULX Hd,Hn,Hm float16_t vmulxh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VMULXH_LANE_F16: // FMULX Hd,Hn,Vm.H[lane] float16_t vmulxh_lane_f16(float16_t a, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULXH_LANEQ_F16: // FMULX Hd,Hn,Vm.H[lane] float16_t vmulxh_laneq_f16(float16_t a, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VNEGH_F16: // FNEG Hd,Hn float16_t vnegh_f16(float16_t a)
+ case ARM64_INTRIN_VRECPEH_F16: // FRECPE Hd,Hn float16_t vrecpeh_f16(float16_t a)
+ case ARM64_INTRIN_VRECPSH_F16: // FRECPS Hd,Hn,Hm float16_t vrecpsh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VRECPXH_F16: // FRECPX Hd,Hn float16_t vrecpxh_f16(float16_t a)
+ case ARM64_INTRIN_VRNDAH_F16: // FRINTA Hd,Hn float16_t vrndah_f16(float16_t a)
+ case ARM64_INTRIN_VRNDH_F16: // FRINTZ Hd,Hn float16_t vrndh_f16(float16_t a)
+ case ARM64_INTRIN_VRNDIH_F16: // FRINTI Hd,Hn float16_t vrndih_f16(float16_t a)
+ case ARM64_INTRIN_VRNDMH_F16: // FRINTM Hd,Hn float16_t vrndmh_f16(float16_t a)
+ case ARM64_INTRIN_VRNDNH_F16: // FRINTN Hd,Hn float16_t vrndnh_f16(float16_t a)
+ case ARM64_INTRIN_VRNDPH_F16: // FRINTP Hd,Hn float16_t vrndph_f16(float16_t a)
+ case ARM64_INTRIN_VRNDXH_F16: // FRINTX Hd,Hn float16_t vrndxh_f16(float16_t a)
+ case ARM64_INTRIN_VRSQRTEH_F16: // FRSQRTE Hd,Hn float16_t vrsqrteh_f16(float16_t a)
+ case ARM64_INTRIN_VRSQRTSH_F16: // FRSQRTS Hd,Hn,Hm float16_t vrsqrtsh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VSQRTH_F16: // FSQRT Hd,Hn float16_t vsqrth_f16(float16_t a)
+ case ARM64_INTRIN_VSUBH_F16: // FSUB Hd,Hn,Hm float16_t vsubh_f16(float16_t a, float16_t b)
+ return {Type::FloatType(2)};
+ case ARM64_INTRIN_VABDS_F32: // FABD Sd,Sn,Sm float32_t vabds_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VADDV_F32: // FADDP Sd,Vn.2S float32_t vaddv_f32(float32x2_t a)
+ case ARM64_INTRIN_VADDVQ_F32: // FADDP Vt.4S,Vn.4S,Vm.4S; FADDP Sd,Vt.2S float32_t vaddvq_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTAH_F32_BF16: // SHL Dd,Dn,#16 float32_t vcvtah_f32_bf16(bfloat16_t a)
+ case ARM64_INTRIN_VCVTS_F32_S32: // SCVTF Wd,Sn float32_t vcvts_f32_s32(int32_t a)
+ case ARM64_INTRIN_VCVTS_F32_U32: // UCVTF Wd,Sn float32_t vcvts_f32_u32(uint32_t a)
+ case ARM64_INTRIN_VCVTS_N_F32_S32: // SCVTF Sd,Sn,#n float32_t vcvts_n_f32_s32(int32_t a, const int n)
+ // case ARM64_INTRIN_VCVTS_N_F32_S32: // SCVTF Wd,Sn,#n float32_t vcvts_n_f32_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VCVTS_N_F32_U32: // UCVTF Sd,Sn,#n float32_t vcvts_n_f32_u32(uint32_t a, const int n)
+ // case ARM64_INTRIN_VCVTS_N_F32_U32: // UCVTF Wd,Sn,#n float32_t vcvts_n_f32_u32(uint32_t a, const int n)
+ case ARM64_INTRIN_VCVTXD_F32_F64: // FCVTXN Sd,Dn float32_t vcvtxd_f32_f64(float64_t a)
+ case ARM64_INTRIN_VDUPS_LANE_F32: // DUP Sd,Vn.S[lane] float32_t vdups_lane_f32(float32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPS_LANEQ_F32: // DUP Sd,Vn.S[lane] float32_t vdups_laneq_f32(float32x4_t vec, const int lane)
+ case ARM64_INTRIN_VFMAS_LANE_F32: // FMLA Sd,Sn,Vm.S[lane] float32_t vfmas_lane_f32(float32_t a, float32_t b, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VFMAS_LANEQ_F32: // FMLA Sd,Sn,Vm.S[lane] float32_t vfmas_laneq_f32(float32_t a, float32_t b, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VFMSS_LANE_F32: // FMLS Sd,Sn,Vm.S[lane] float32_t vfmss_lane_f32(float32_t a, float32_t b, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VFMSS_LANEQ_F32: // FMLS Sd,Sn,Vm.S[lane] float32_t vfmss_laneq_f32(float32_t a, float32_t b, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_F32: // DUP Sd,Vn.S[lane] float32_t vget_lane_f32(float32x2_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_F32: // DUP Sd,Vn.S[lane] float32_t vgetq_lane_f32(float32x4_t v, const int lane)
+ case ARM64_INTRIN_VMAX_F32: // FMAX Sd,Sn,Sm float32x1_t vmax_f32(float32x1_t a, float32x1_t b)
+ case ARM64_INTRIN_VMAXNM_F32: // FMAXNM Sd,Sn,Sm float32x1_t vmaxnm_f32(float32x1_t a, float32x1_t b)
+ case ARM64_INTRIN_VMAXNMV_F32: // FMAXNMP Sd,Vn.2S float32_t vmaxnmv_f32(float32x2_t a)
+ case ARM64_INTRIN_VMAXNMVQ_F32: // FMAXNMV Sd,Vn.4S float32_t vmaxnmvq_f32(float32x4_t a)
+ case ARM64_INTRIN_VMAXV_F32: // FMAXP Sd,Vn.2S float32_t vmaxv_f32(float32x2_t a)
+ case ARM64_INTRIN_VMAXVQ_F32: // FMAXV Sd,Vn.4S float32_t vmaxvq_f32(float32x4_t a)
+ case ARM64_INTRIN_VMINNMV_F32: // FMINNMP Sd,Vn.2S float32_t vminnmv_f32(float32x2_t a)
+ case ARM64_INTRIN_VMINNMVQ_F32: // FMINNMV Sd,Vn.4S float32_t vminnmvq_f32(float32x4_t a)
+ case ARM64_INTRIN_VMINV_F32: // FMINP Sd,Vn.2S float32_t vminv_f32(float32x2_t a)
+ // case ARM64_INTRIN_VMINV_F32: // FMINV Sd,Vn.2S float32_t vminv_f32(float32x2_t a)
+ case ARM64_INTRIN_VMINVQ_F32: // FMINV Sd,Vn.4S float32_t vminvq_f32(float32x4_t a)
+ case ARM64_INTRIN_VMULS_LANE_F32: // FMUL Sd,Sn,Vm.S[lane] float32_t vmuls_lane_f32(float32_t a, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULS_LANEQ_F32: // FMUL Sd,Sn,Vm.S[lane] float32_t vmuls_laneq_f32(float32_t a, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULXS_F32: // FMULX Sd,Sn,Sm float32_t vmulxs_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VMULXS_LANE_F32: // FMULX Sd,Sn,Vm.S[lane] float32_t vmulxs_lane_f32(float32_t a, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULXS_LANEQ_F32: // FMULX Sd,Sn,Vm.S[lane] float32_t vmulxs_laneq_f32(float32_t a, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VPADDS_F32: // FADDP Sd,Vn.2S float32_t vpadds_f32(float32x2_t a)
+ case ARM64_INTRIN_VPMAXNMS_F32: // FMAXNMP Sd,Vn.2S float32_t vpmaxnms_f32(float32x2_t a)
+ case ARM64_INTRIN_VPMAXS_F32: // FMAXP Sd,Vn.2S float32_t vpmaxs_f32(float32x2_t a)
+ case ARM64_INTRIN_VPMINNMS_F32: // FMINNMP Sd,Vn.2S float32_t vpminnms_f32(float32x2_t a)
+ case ARM64_INTRIN_VPMINS_F32: // FMINP Sd,Vn.2S float32_t vpmins_f32(float32x2_t a)
+ case ARM64_INTRIN_VRECPES_F32: // FRECPE Sd,Sn float32_t vrecpes_f32(float32_t a)
+ case ARM64_INTRIN_VRECPSS_F32: // FRECPS Sd,Sn,Sm float32_t vrecpss_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VRECPXS_F32: // FRECPX Sd,Sn float32_t vrecpxs_f32(float32_t a)
+ case ARM64_INTRIN_VRND32X_F32: // FRINT32X Sd,Sn float32x1_t vrnd32x_f32(float32x1_t a)
+ case ARM64_INTRIN_VRND32Z_F32: // FRINT32Z Sd,Sn float32x1_t vrnd32z_f32(float32x1_t a)
+ case ARM64_INTRIN_VRND64X_F32: // FRINT64X Sd,Sn float32x1_t vrnd64x_f32(float32x1_t a)
+ case ARM64_INTRIN_VRNDA_F32: // FRINTA Sd,Sn float32x1_t vrnda_f32(float32x1_t a)
+ case ARM64_INTRIN_VRNDI_F32: // FRINTI Sd,Sn float32x1_t vrndi_f32(float32x1_t a)
+ case ARM64_INTRIN_VRNDM_F32: // FRINTM Sd,Sn float32x1_t vrndm_f32(float32x1_t a)
+ case ARM64_INTRIN_VRNDNS_F32: // FRINTN Sd,Sn float32_t vrndns_f32(float32_t a)
+ case ARM64_INTRIN_VRNDP_F32: // FRINTP Sd,Sn float32x1_t vrndp_f32(float32x1_t a)
+ case ARM64_INTRIN_VRNDX_F32: // FRINTX Sd,Sn float32x1_t vrndx_f32(float32x1_t a)
+ case ARM64_INTRIN_VRSQRTES_F32: // FRSQRTE Sd,Sn float32_t vrsqrtes_f32(float32_t a)
+ case ARM64_INTRIN_VRSQRTSS_F32: // FRSQRTS Sd,Sn,Sm float32_t vrsqrtss_f32(float32_t a, float32_t b)
+ return {Type::FloatType(4)};
+ case ARM64_INTRIN_VABD_F16: // FABD Vd.4H,Vn.4H,Vm.4H float16x4_t vabd_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VABD_F32: // FABD Vd.2S,Vn.2S,Vm.2S float32x2_t vabd_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VABD_F64: // FABD Dd,Dn,Dm float64x1_t vabd_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VABDD_F64: // FABD Dd,Dn,Dm float64_t vabdd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VABS_F16: // FABS Vd.4H,Vn.4H float16x4_t vabs_f16(float16x4_t a)
+ case ARM64_INTRIN_VABS_F32: // FABS Vd.2S,Vn.2S float32x2_t vabs_f32(float32x2_t a)
+ case ARM64_INTRIN_VABS_F64: // FABS Dd,Dn float64x1_t vabs_f64(float64x1_t a)
+ case ARM64_INTRIN_VADD_F16: // FADD Vd.4H,Vn.4H,Vm.4H float16x4_t vadd_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VADD_F32: // FADD Vd.2S,Vn.2S,Vm.2S float32x2_t vadd_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VADD_F64: // FADD Dd,Dn,Dm float64x1_t vadd_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VADDVQ_F64: // FADDP Dd,Vn.2D float64_t vaddvq_f64(float64x2_t a)
+ case ARM64_INTRIN_VBFDOT_F32: // BFDOT Vd.2S,Vn.4H,Vm.4H float32x2_t vbfdot_f32(float32x2_t r, bfloat16x4_t a, bfloat16x4_t b)
+ case ARM64_INTRIN_VBFDOT_LANE_F32: // BFDOT Vd.2S,Vn.4H,Vm.2H[lane] float32x2_t vbfdot_lane_f32(float32x2_t r, bfloat16x4_t a, bfloat16x4_t b, const int lane)
+ case ARM64_INTRIN_VBFDOT_LANEQ_F32: // BFDOT Vd.2S,Vn.4H,Vm.2H[lane] float32x2_t vbfdot_laneq_f32(float32x2_t r, bfloat16x4_t a, bfloat16x8_t b, const int lane)
+ case ARM64_INTRIN_VBSL_F16: // BSL Vd.8B,Vn.8B,Vm.8B float16x4_t vbsl_f16(uint16x4_t a, float16x4_t b, float16x4_t c)
+ case ARM64_INTRIN_VBSL_F32: // BSL Vd.8B,Vn.8B,Vm.8B float32x2_t vbsl_f32(uint32x2_t a, float32x2_t b, float32x2_t c)
+ case ARM64_INTRIN_VBSL_F64: // BSL Vd.8B,Vn.8B,Vm.8B float64x1_t vbsl_f64(uint64x1_t a, float64x1_t b, float64x1_t c)
+ case ARM64_INTRIN_VCADD_ROT270_F16: // FCADD Vd.4H,Vn.4H,Vm.4H,#270 float16x4_t vcadd_rot270_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCADD_ROT270_F32: // FCADD Vd.2S,Vn.2S,Vm.2S,#270 float32x2_t vcadd_rot270_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCADD_ROT90_F16: // FCADD Vd.4H,Vn.4H,Vm.4H,#90 float16x4_t vcadd_rot90_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCADD_ROT90_F32: // FCADD Vd.2S,Vn.2S,Vm.2S,#90 float32x2_t vcadd_rot90_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCMLA_F16: // FCMLA Vd.4H,Vn.4H,Vm.4H,#0 float16x4_t vcmla_f16(float16x4_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCMLA_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S,#0 float32x2_t vcmla_f32(float32x2_t r, float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCMLA_LANE_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#0 float16x4_t vcmla_lane_f16(float16x4_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_LANE_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#0 float32x2_t vcmla_lane_f32(float32x2_t r, float32x2_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_LANEQ_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#0 float16x4_t vcmla_laneq_f16(float16x4_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_LANEQ_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S,#0 float32x2_t vcmla_laneq_f32(float32x2_t r, float32x2_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT180_F16: // FCMLA Vd.4H,Vn.4H,Vm.4H,#180 float16x4_t vcmla_rot180_f16(float16x4_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCMLA_ROT180_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S,#180 float32x2_t vcmla_rot180_f32(float32x2_t r, float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCMLA_ROT180_LANE_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#180 float16x4_t vcmla_rot180_lane_f16(float16x4_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT180_LANE_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#180 float32x2_t vcmla_rot180_lane_f32(float32x2_t r, float32x2_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT180_LANEQ_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#180 float16x4_t vcmla_rot180_laneq_f16(float16x4_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT180_LANEQ_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S,#180 float32x2_t vcmla_rot180_laneq_f32(float32x2_t r, float32x2_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT270_F16: // FCMLA Vd.4H,Vn.4H,Vm.4H,#270 float16x4_t vcmla_rot270_f16(float16x4_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCMLA_ROT270_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S,#270 float32x2_t vcmla_rot270_f32(float32x2_t r, float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCMLA_ROT270_LANE_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#270 float16x4_t vcmla_rot270_lane_f16(float16x4_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT270_LANE_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#270 float32x2_t vcmla_rot270_lane_f32(float32x2_t r, float32x2_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT270_LANEQ_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#270 float16x4_t vcmla_rot270_laneq_f16(float16x4_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT270_LANEQ_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#270 float32x2_t vcmla_rot270_laneq_f32(float32x2_t r, float32x2_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT90_F16: // FCMLA Vd.4H,Vn.4H,Vm.4H,#90 float16x4_t vcmla_rot90_f16(float16x4_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCMLA_ROT90_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S,#90 float32x2_t vcmla_rot90_f32(float32x2_t r, float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCMLA_ROT90_LANE_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#90 float16x4_t vcmla_rot90_lane_f16(float16x4_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT90_LANE_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#90 float32x2_t vcmla_rot90_lane_f32(float32x2_t r, float32x2_t a, float32x2_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT90_LANEQ_F16: // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#90 float16x4_t vcmla_rot90_laneq_f16(float16x4_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VCMLA_ROT90_LANEQ_F32: // FCMLA Vd.2S,Vn.2S,Vm.2S,#90 float32x2_t vcmla_rot90_laneq_f32(float32x2_t r, float32x2_t a, float32x4_t b, const int lane)
+ case ARM64_INTRIN_VCOPY_LANE_BF16: // INS Vd.H[lane1],Vn.H[lane2] bfloat16x4_t vcopy_lane_bf16(bfloat16x4_t a, const int lane1, bfloat16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_F32: // INS Vd.S[lane1],Vn.S[lane2] float32x2_t vcopy_lane_f32(float32x2_t a, const int lane1, float32x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_F64: // DUP Dd,Vn.D[lane2] float64x1_t vcopy_lane_f64(float64x1_t a, const int lane1, float64x1_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_BF16: // INS Vd.H[lane1],Vn.H[lane2] bfloat16x4_t vcopy_laneq_bf16(bfloat16x4_t a, const int lane1, bfloat16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_F32: // INS Vd.S[lane1],Vn.S[lane2] float32x2_t vcopy_laneq_f32(float32x2_t a, const int lane1, float32x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_F64: // DUP Dd,Vn.D[lane2] float64x1_t vcopy_laneq_f64(float64x1_t a, const int lane1, float64x2_t b, const int lane2)
+ case ARM64_INTRIN_VCREATE_BF16: // INS Vd.D[0],Xn bfloat16x4_t vcreate_bf16(uint64_t a)
+ case ARM64_INTRIN_VCREATE_F16: // INS Vd.D[0],Xn float16x4_t vcreate_f16(uint64_t a)
+ case ARM64_INTRIN_VCREATE_F32: // INS Vd.D[0],Xn float32x2_t vcreate_f32(uint64_t a)
+ case ARM64_INTRIN_VCREATE_F64: // INS Vd.D[0],Xn float64x1_t vcreate_f64(uint64_t a)
+ case ARM64_INTRIN_VCVT_BF16_F32: // BFCVTN Vd.4H,Vn.4S bfloat16x4_t vcvt_bf16_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVT_F16_F32: // FCVTN Vd.4H,Vn.4S float16x4_t vcvt_f16_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVT_F16_S16: // SCVTF Vd.4H,Vn.4H,#0 float16x4_t vcvt_f16_s16(int16x4_t a)
+ case ARM64_INTRIN_VCVT_F16_U16: // UCVTF Vd.4H,Vn.4H,#0 float16x4_t vcvt_f16_u16(uint16x4_t a)
+ case ARM64_INTRIN_VCVT_F32_F64: // FCVTN Vd.2S,Vn.2D float32x2_t vcvt_f32_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVT_F32_S32: // SCVTF Vd.2S,Vn.2S float32x2_t vcvt_f32_s32(int32x2_t a)
+ case ARM64_INTRIN_VCVT_F32_U32: // UCVTF Vd.2S,Vn.2S float32x2_t vcvt_f32_u32(uint32x2_t a)
+ case ARM64_INTRIN_VCVT_F64_S64: // SCVTF Xd,Dn float64x1_t vcvt_f64_s64(int64x1_t a)
+ case ARM64_INTRIN_VCVT_F64_U64: // UCVTF Xd,Dn float64x1_t vcvt_f64_u64(uint64x1_t a)
+ case ARM64_INTRIN_VCVT_N_F16_S16: // SCVTF Vd.4H,Vn.4H,#n float16x4_t vcvt_n_f16_s16(int16x4_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_F16_U16: // UCVTF Vd.4H,Vn.4H,#n float16x4_t vcvt_n_f16_u16(uint16x4_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_F32_S32: // SCVTF Vd.2S,Vn.2S,#n float32x2_t vcvt_n_f32_s32(int32x2_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_F32_U32: // UCVTF Vd.2S,Vn.2S,#n float32x2_t vcvt_n_f32_u32(uint32x2_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_F64_S64: // SCVTF Dd,Dn,#n float64x1_t vcvt_n_f64_s64(int64x1_t a, const int n)
+ // case ARM64_INTRIN_VCVT_N_F64_S64: // SCVTF Xd,Dn,#n float64x1_t vcvt_n_f64_s64(int64x1_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_F64_U64: // UCVTF Dd,Dn,#n float64x1_t vcvt_n_f64_u64(uint64x1_t a, const int n)
+ // case ARM64_INTRIN_VCVT_N_F64_U64: // UCVTF Xd,Dn,#n float64x1_t vcvt_n_f64_u64(uint64x1_t a, const int n)
+ case ARM64_INTRIN_VCVTD_F64_S64: // SCVTF Xd,Dn float64_t vcvtd_f64_s64(int64_t a)
+ case ARM64_INTRIN_VCVTD_F64_U64: // UCVTF Xd,Dn float64_t vcvtd_f64_u64(uint64_t a)
+ case ARM64_INTRIN_VCVTD_N_F64_S64: // SCVTF Dd,Dn,#n float64_t vcvtd_n_f64_s64(int64_t a, const int n)
+ // case ARM64_INTRIN_VCVTD_N_F64_S64: // SCVTF Xd,Dn,#n float64_t vcvtd_n_f64_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VCVTD_N_F64_U64: // UCVTF Dd,Dn,#n float64_t vcvtd_n_f64_u64(uint64_t a, const int n)
+ // case ARM64_INTRIN_VCVTD_N_F64_U64: // UCVTF Xd,Dn,#n float64_t vcvtd_n_f64_u64(uint64_t a, const int n)
+ case ARM64_INTRIN_VCVTX_F32_F64: // FCVTXN Vd.2S,Vn.2D float32x2_t vcvtx_f32_f64(float64x2_t a)
+ case ARM64_INTRIN_VDIV_F16: // FDIV Vd.4H,Vn.4H,Vm.4H float16x4_t vdiv_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VDIV_F32: // FDIV Vd.2S,Vn.2S,Vm.2S float32x2_t vdiv_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VDIV_F64: // FDIV Dd,Dn,Dm float64x1_t vdiv_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VDUP_LANE_BF16: // DUP Vd.4H,Vn.H[lane] bfloat16x4_t vdup_lane_bf16(bfloat16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_F16: // DUP Vd.4H,Vn.H[lane] float16x4_t vdup_lane_f16(float16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_F32: // DUP Vd.2S,Vn.S[lane] float32x2_t vdup_lane_f32(float32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_F64: // DUP Dd,Vn.D[lane] float64x1_t vdup_lane_f64(float64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_BF16: // DUP Vd.4H,Vn.H[lane] bfloat16x4_t vdup_laneq_bf16(bfloat16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_F16: // DUP Vd.4H,Vn.H[lane] float16x4_t vdup_laneq_f16(float16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_F32: // DUP Vd.2S,Vn.S[lane] float32x2_t vdup_laneq_f32(float32x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_F64: // DUP Dd,Vn.D[lane] float64x1_t vdup_laneq_f64(float64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_N_BF16: // DUP Vd.4H,rn bfloat16x4_t vdup_n_bf16(bfloat16_t value)
+ case ARM64_INTRIN_VDUP_N_F16: // DUP Vd.4H,rn float16x4_t vdup_n_f16(float16_t value)
+ case ARM64_INTRIN_VDUP_N_F32: // DUP Vd.2S,rn float32x2_t vdup_n_f32(float32_t value)
+ case ARM64_INTRIN_VDUP_N_F64: // INS Vd.D[0],rn float64x1_t vdup_n_f64(float64_t value)
+ case ARM64_INTRIN_VDUPD_LANE_F64: // DUP Dd,Vn.D[lane] float64_t vdupd_lane_f64(float64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUPD_LANEQ_F64: // DUP Dd,Vn.D[lane] float64_t vdupd_laneq_f64(float64x2_t vec, const int lane)
+ case ARM64_INTRIN_VEXT_F16: // EXT Vd.8B,Vn.8B,Vm.8B,#n float16x4_t vext_f16(float16x4_t a, float16x4_t b, const int n)
+ case ARM64_INTRIN_VEXT_F32: // EXT Vd.8B,Vn.8B,Vm.8B,#n float32x2_t vext_f32(float32x2_t a, float32x2_t b, const int n)
+ case ARM64_INTRIN_VEXT_F64: // EXT Vd.8B,Vn.8B,Vm.8B,#n float64x1_t vext_f64(float64x1_t a, float64x1_t b, const int n)
+ case ARM64_INTRIN_VFMA_F16: // FMLA Vd.4H,Vn.4H,Vm.4H float16x4_t vfma_f16(float16x4_t a, float16x4_t b, float16x4_t c)
+ case ARM64_INTRIN_VFMA_F32: // FMLA Vd.2S,Vn.2S,Vm.2S float32x2_t vfma_f32(float32x2_t a, float32x2_t b, float32x2_t c)
+ case ARM64_INTRIN_VFMA_F64: // FMADD Dd,Dn,Dm,Da float64x1_t vfma_f64(float64x1_t a, float64x1_t b, float64x1_t c)
+ case ARM64_INTRIN_VFMA_LANE_F16: // FMLA Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vfma_lane_f16(float16x4_t a, float16x4_t b, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VFMA_LANE_F32: // FMLA Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vfma_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VFMA_LANE_F64: // FMLA Dd,Dn,Vm.D[lane] float64x1_t vfma_lane_f64(float64x1_t a, float64x1_t b, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VFMA_LANEQ_F16: // FMLA Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vfma_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VFMA_LANEQ_F32: // FMLA Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vfma_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VFMA_LANEQ_F64: // FMLA Dd,Dn,Vm.D[lane] float64x1_t vfma_laneq_f64(float64x1_t a, float64x1_t b, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VFMA_N_F16: // FMLA Vd.4H,Vn.4H,Vm.H[0] float16x4_t vfma_n_f16(float16x4_t a, float16x4_t b, float16_t n)
+ case ARM64_INTRIN_VFMA_N_F32: // FMLA Vd.2S,Vn.2S,Vm.S[0] float32x2_t vfma_n_f32(float32x2_t a, float32x2_t b, float32_t n)
+ case ARM64_INTRIN_VFMA_N_F64: // FMADD Dd,Dn,Dm,Da float64x1_t vfma_n_f64(float64x1_t a, float64x1_t b, float64_t n)
+ case ARM64_INTRIN_VFMAD_LANE_F64: // FMLA Dd,Dn,Vm.D[lane] float64_t vfmad_lane_f64(float64_t a, float64_t b, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VFMAD_LANEQ_F64: // FMLA Dd,Dn,Vm.D[lane] float64_t vfmad_laneq_f64(float64_t a, float64_t b, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VFMLAL_HIGH_F16: // FMLAL2 Vd.2S,Vn.2H,Vm.2H float32x2_t vfmlal_high_f16(float32x2_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VFMLAL_LANE_HIGH_F16: // FMLAL2 Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlal_lane_high_f16(float32x2_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMLAL_LANE_LOW_F16: // FMLAL Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlal_lane_low_f16(float32x2_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMLAL_LANEQ_HIGH_F16: // FMLAL2 Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlal_laneq_high_f16(float32x2_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMLAL_LANEQ_LOW_F16: // FMLAL Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlal_laneq_low_f16(float32x2_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMLAL_LOW_F16: // FMLAL Vd.2S,Vn.2H,Vm.2H float32x2_t vfmlal_low_f16(float32x2_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VFMLSL_HIGH_F16: // FMLSL2 Vd.2S,Vn.2H,Vm.2H float32x2_t vfmlsl_high_f16(float32x2_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VFMLSL_LANE_HIGH_F16: // FMLSL2 Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlsl_lane_high_f16(float32x2_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMLSL_LANE_LOW_F16: // FMLSL Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlsl_lane_low_f16(float32x2_t r, float16x4_t a, float16x4_t b, const int lane)
+ case ARM64_INTRIN_VFMLSL_LANEQ_HIGH_F16: // FMLSL2 Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlsl_laneq_high_f16(float32x2_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMLSL_LANEQ_LOW_F16: // FMLSL Vd.2S,Vn.2H,Vm.H[lane] float32x2_t vfmlsl_laneq_low_f16(float32x2_t r, float16x4_t a, float16x8_t b, const int lane)
+ case ARM64_INTRIN_VFMLSL_LOW_F16: // FMLSL Vd.2S,Vn.2H,Vm.2H float32x2_t vfmlsl_low_f16(float32x2_t r, float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VFMS_F16: // FMLS Vd.4H,Vn.4H,Vm.4H float16x4_t vfms_f16(float16x4_t a, float16x4_t b, float16x4_t c)
+ case ARM64_INTRIN_VFMS_F32: // FMLS Vd.2S,Vn.2S,Vm.2S float32x2_t vfms_f32(float32x2_t a, float32x2_t b, float32x2_t c)
+ case ARM64_INTRIN_VFMS_F64: // FMSUB Dd,Dn,Dm,Da float64x1_t vfms_f64(float64x1_t a, float64x1_t b, float64x1_t c)
+ case ARM64_INTRIN_VFMS_LANE_F16: // FMLS Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vfms_lane_f16(float16x4_t a, float16x4_t b, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VFMS_LANE_F32: // FMLS Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vfms_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VFMS_LANE_F64: // FMLS Dd,Dn,Vm.D[lane] float64x1_t vfms_lane_f64(float64x1_t a, float64x1_t b, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VFMS_LANEQ_F16: // FMLS Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vfms_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VFMS_LANEQ_F32: // FMLS Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vfms_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VFMS_LANEQ_F64: // FMLS Dd,Dn,Vm.D[lane] float64x1_t vfms_laneq_f64(float64x1_t a, float64x1_t b, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VFMS_N_F16: // FMLS Vd.4H,Vn.4H,Vm.H[0] float16x4_t vfms_n_f16(float16x4_t a, float16x4_t b, float16_t n)
+ case ARM64_INTRIN_VFMS_N_F32: // FMLS Vd.2S,Vn.2S,Vm.S[0] float32x2_t vfms_n_f32(float32x2_t a, float32x2_t b, float32_t n)
+ case ARM64_INTRIN_VFMSD_LANE_F64: // FMLS Dd,Dn,Vm.D[lane] float64_t vfmsd_lane_f64(float64_t a, float64_t b, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VFMSD_LANEQ_F64: // FMLS Dd,Dn,Vm.D[lane] float64_t vfmsd_laneq_f64(float64_t a, float64_t b, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VGET_HIGH_BF16: // DUP Vd.1D,Vn.D[1] bfloat16x4_t vget_high_bf16(bfloat16x8_t a)
+ case ARM64_INTRIN_VGET_HIGH_F16: // DUP Vd.1D,Vn.D[1] float16x4_t vget_high_f16(float16x8_t a)
+ case ARM64_INTRIN_VGET_HIGH_F32: // DUP Vd.1D,Vn.D[1] float32x2_t vget_high_f32(float32x4_t a)
+ case ARM64_INTRIN_VGET_HIGH_F64: // DUP Vd.1D,Vn.D[1] float64x1_t vget_high_f64(float64x2_t a)
+ case ARM64_INTRIN_VGET_LANE_F64: // DUP Dd,Vn.D[lane] float64_t vget_lane_f64(float64x1_t v, const int lane)
+ case ARM64_INTRIN_VGET_LOW_BF16: // DUP Vd.1D,Vn.D[0] bfloat16x4_t vget_low_bf16(bfloat16x8_t a)
+ case ARM64_INTRIN_VGET_LOW_F16: // DUP Vd.1D,Vn.D[0] float16x4_t vget_low_f16(float16x8_t a)
+ case ARM64_INTRIN_VGET_LOW_F32: // DUP Vd.1D,Vn.D[0] float32x2_t vget_low_f32(float32x4_t a)
+ case ARM64_INTRIN_VGET_LOW_F64: // DUP Vd.1D,Vn.D[0] float64x1_t vget_low_f64(float64x2_t a)
+ case ARM64_INTRIN_VGETQ_LANE_F64: // DUP Dd,Vn.D[lane] float64_t vgetq_lane_f64(float64x2_t v, const int lane)
+ case ARM64_INTRIN_VMAX__F32: // FMAX Vd.2S,Vn.2S,Vm.2S float32x2_t vmax__f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VMAX_F16: // FMAX Vd.4H,Vn.4H,Vm.4H float16x4_t vmax_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VMAX_F64: // FMAX Dd,Dn,Dm float64x1_t vmax_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VMAXNM__F32: // FMAXNM Vd.2S,Vn.2S,Vm.2S float32x2_t vmaxnm__f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VMAXNM_F16: // FMAXNM Vd.4H,Vn.4H,Vm.4H float16x4_t vmaxnm_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VMAXNM_F64: // FMAXNM Dd,Dn,Dm float64x1_t vmaxnm_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VMAXNMVQ_F64: // FMAXNMP Dd,Vn.2D float64_t vmaxnmvq_f64(float64x2_t a)
+ case ARM64_INTRIN_VMAXVQ_F64: // FMAXP Dd,Vn.2D float64_t vmaxvq_f64(float64x2_t a)
+ case ARM64_INTRIN_VMIN_F16: // FMIN Vd.4H,Vn.4H,Vm.4H float16x4_t vmin_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VMIN_F32: // FMIN Vd.2S,Vn.2S,Vm.2S float32x2_t vmin_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VMIN_F64: // FMIN Dd,Dn,Dm float64x1_t vmin_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VMINNM_F16: // FMINNM Vd.4H,Vn.4H,Vm.4H float16x4_t vminnm_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VMINNM_F32: // FMINNM Vd.2S,Vn.2S,Vm.2S float32x2_t vminnm_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VMINNM_F64: // FMINNM Dd,Dn,Dm float64x1_t vminnm_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VMINNMVQ_F64: // FMINNMP Dd,Vn.2D float64_t vminnmvq_f64(float64x2_t a)
+ case ARM64_INTRIN_VMINVQ_F64: // FMINP Dd,Vn.2D float64_t vminvq_f64(float64x2_t a)
+ // case ARM64_INTRIN_VMINVQ_F64: // FMINV Dd,Vn.2D float64_t vminvq_f64(float64x2_t a)
+ case ARM64_INTRIN_VMOV_N_F16: // DUP Vd.4H,rn float16x4_t vmov_n_f16(float16_t value)
+ case ARM64_INTRIN_VMOV_N_F32: // DUP Vd.2S,rn float32x2_t vmov_n_f32(float32_t value)
+ case ARM64_INTRIN_VMOV_N_F64: // DUP Vd.1D,rn float64x1_t vmov_n_f64(float64_t value)
+ case ARM64_INTRIN_VMUL_F16: // FMUL Vd.4H,Vn.4H,Vm.4H float16x4_t vmul_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VMUL_F32: // FMUL Vd.2S,Vn.2S,Vm.2S float32x2_t vmul_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VMUL_F64: // FMUL Dd,Dn,Dm float64x1_t vmul_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VMUL_LANE_F16: // FMUL Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vmul_lane_f16(float16x4_t a, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANE_F32: // FMUL Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vmul_lane_f32(float32x2_t a, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANE_F64: // FMUL Dd,Dn,Vm.D[lane] float64x1_t vmul_lane_f64(float64x1_t a, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANEQ_F16: // FMUL Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vmul_laneq_f16(float16x4_t a, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANEQ_F32: // FMUL Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vmul_laneq_f32(float32x2_t a, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANEQ_F64: // FMUL Dd,Dn,Vm.D[lane] float64x1_t vmul_laneq_f64(float64x1_t a, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VMUL_N_F16: // FMUL Vd.4H,Vn.4H,Vm.H[0] float16x4_t vmul_n_f16(float16x4_t a, float16_t n)
+ case ARM64_INTRIN_VMUL_N_F32: // FMUL Vd.2S,Vn.2S,Vm.S[0] float32x2_t vmul_n_f32(float32x2_t a, float32_t b)
+ case ARM64_INTRIN_VMUL_N_F64: // FMUL Dd,Dn,Vm.D[0] float64x1_t vmul_n_f64(float64x1_t a, float64_t b)
+ case ARM64_INTRIN_VMULD_LANEQ_F64: // FMUL Dd,Dn,Vm.D[lane] float64_t vmuld_laneq_f64(float64_t a, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VMULX_F16: // FMULX Vd.4H,Vn.4H,Vm.4H float16x4_t vmulx_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VMULX_F32: // FMULX Vd.2S,Vn.2S,Vm.2S float32x2_t vmulx_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VMULX_F64: // FMULX Dd,Dn,Dm float64x1_t vmulx_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VMULX_LANE_F16: // FMULX Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vmulx_lane_f16(float16x4_t a, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULX_LANE_F32: // FMULX Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vmulx_lane_f32(float32x2_t a, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULX_LANE_F64: // FMULX Dd,Dn,Vm.D[lane] float64x1_t vmulx_lane_f64(float64x1_t a, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VMULX_LANEQ_F16: // FMULX Vd.4H,Vn.4H,Vm.H[lane] float16x4_t vmulx_laneq_f16(float16x4_t a, float16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULX_LANEQ_F32: // FMULX Vd.2S,Vn.2S,Vm.S[lane] float32x2_t vmulx_laneq_f32(float32x2_t a, float32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULX_LANEQ_F64: // FMULX Dd,Dn,Vm.D[lane] float64x1_t vmulx_laneq_f64(float64x1_t a, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VMULX_N_F16: // FMULX Vd.4H,Vn.4H,Vm.H[0] float16x4_t vmulx_n_f16(float16x4_t a, float16_t n)
+ case ARM64_INTRIN_VMULXD_F64: // FMULX Dd,Dn,Dm float64_t vmulxd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VMULXD_LANE_F64: // FMULX Dd,Dn,Vm.D[lane] float64_t vmulxd_lane_f64(float64_t a, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VMULXD_LANEQ_F64: // FMULX Dd,Dn,Vm.D[lane] float64_t vmulxd_laneq_f64(float64_t a, float64x2_t v, const int lane)
+ case ARM64_INTRIN_VNEG_F16: // FNEG Vd.4H,Vn.4H float16x4_t vneg_f16(float16x4_t a)
+ case ARM64_INTRIN_VNEG_F32: // FNEG Vd.2S,Vn.2S float32x2_t vneg_f32(float32x2_t a)
+ case ARM64_INTRIN_VNEG_F64: // FNEG Dd,Dn float64x1_t vneg_f64(float64x1_t a)
+ case ARM64_INTRIN_VPADD_F16: // FADDP Vd.4H,Vn.4H,Vm.4H float16x4_t vpadd_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VPADD_F32: // FADDP Vd.2S,Vn.2S,Vm.2S float32x2_t vpadd_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VPADDD_F64: // FADDP Dd,Vn.2D float64_t vpaddd_f64(float64x2_t a)
+ case ARM64_INTRIN_VPMAX_F16: // FMAXP Vd.4H,Vn.4H,Vm.4H float16x4_t vpmax_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VPMAX_F32: // FMAXP Vd.2S,Vn.2S,Vm.2S float32x2_t vpmax_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VPMAXNM_F16: // FMAXNMP Vd.4H,Vn.4H,Vm.4H float16x4_t vpmaxnm_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VPMAXNM_F32: // FMAXNMP Vd.2S,Vn.2S,Vm.2S float32x2_t vpmaxnm_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VPMAXNMQD_F64: // FMAXNMP Dd,Vn.2D float64_t vpmaxnmqd_f64(float64x2_t a)
+ case ARM64_INTRIN_VPMAXQD_F64: // FMAXP Dd,Vn.2D float64_t vpmaxqd_f64(float64x2_t a)
+ case ARM64_INTRIN_VPMIN_F16: // FMINP Vd.4H,Vn.4H,Vm.4H float16x4_t vpmin_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VPMIN_F32: // FMINP Vd.2S,Vn.2S,Vm.2S float32x2_t vpmin_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VPMINNM_F16: // FMINNMP Vd.4H,Vn.4H,Vm.4H float16x4_t vpminnm_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VPMINNM_F32: // FMINNMP Vd.2S,Vn.2S,Vm.2S float32x2_t vpminnm_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VPMINNMQD_F64: // FMINNMP Dd,Vn.2D float64_t vpminnmqd_f64(float64x2_t a)
+ case ARM64_INTRIN_VPMINQD_F64: // FMINP Dd,Vn.2D float64_t vpminqd_f64(float64x2_t a)
+ case ARM64_INTRIN_VRECPE_F16: // FRECPE Vd.4H,Vn.4H float16x4_t vrecpe_f16(float16x4_t a)
+ case ARM64_INTRIN_VRECPE_F32: // FRECPE Vd.2S,Vn.2S float32x2_t vrecpe_f32(float32x2_t a)
+ case ARM64_INTRIN_VRECPE_F64: // FRECPE Dd,Dn float64x1_t vrecpe_f64(float64x1_t a)
+ case ARM64_INTRIN_VRECPED_F64: // FRECPE Dd,Dn float64_t vrecped_f64(float64_t a)
+ case ARM64_INTRIN_VRECPS_F16: // FRECPS Vd.4H,Vn.4H,Vm.4H float16x4_t vrecps_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VRECPS_F32: // FRECPS Vd.2S,Vn.2S,Vm.2S float32x2_t vrecps_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VRECPS_F64: // FRECPS Dd,Dn,Dm float64x1_t vrecps_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VRECPSD_F64: // FRECPS Dd,Dn,Dm float64_t vrecpsd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VRECPXD_F64: // FRECPX Dd,Dn float64_t vrecpxd_f64(float64_t a)
+ case ARM64_INTRIN_VREV64_F16: // REV64 Vd.4H,Vn.4H float16x4_t vrev64_f16(float16x4_t vec)
+ case ARM64_INTRIN_VREV64_F32: // REV64 Vd.2S,Vn.2S float32x2_t vrev64_f32(float32x2_t vec)
+ // case ARM64_INTRIN_VRND32X_F32: // FRINT32X Vd.2S,Vn.2S float32x2_t vrnd32x_f32(float32x2_t a)
+ case ARM64_INTRIN_VRND32X_F64: // FRINT32X Dd,Dn float64x1_t vrnd32x_f64(float64x1_t a)
+ // case ARM64_INTRIN_VRND32Z_F32: // FRINT32Z Vd.2S,Vn.2S float32x2_t vrnd32z_f32(float32x2_t a)
+ case ARM64_INTRIN_VRND32Z_F64: // FRINT32Z Dd,Dn float64x1_t vrnd32z_f64(float64x1_t a)
+ // case ARM64_INTRIN_VRND64X_F32: // FRINT64X Vd.2S,Vn.2S float32x2_t vrnd64x_f32(float32x2_t a)
+ case ARM64_INTRIN_VRND64X_F64: // FRINT64X Dd,Dn float64x1_t vrnd64x_f64(float64x1_t a)
+ case ARM64_INTRIN_VRND64Z_F32: // FRINT64Z Sd,Sn float64x1_t vrnd64z_f32(float32x1_t a)
+ // case ARM64_INTRIN_VRND64Z_F32: // FRINT64Z Vd.2S,Vn.2S float32x2_t vrnd64z_f32(float32x2_t a)
+ case ARM64_INTRIN_VRND64Z_F64: // FRINT64Z Dd,Dn float64x1_t vrnd64z_f64(float64x1_t a)
+ case ARM64_INTRIN_VRND_F16: // FRINTZ Vd.4H,Vn.4H float16x4_t vrnd_f16(float16x4_t a)
+ case ARM64_INTRIN_VRND_F32: // FRINTZ Vd.2S,Vn.2S float32x2_t vrnd_f32(float32x2_t a)
+ case ARM64_INTRIN_VRND_F64: // FRINTZ Dd,Dn float64x1_t vrnd_f64(float64x1_t a)
+ case ARM64_INTRIN_VRNDA_F16: // FRINTA Vd.4H,Vn.4H float16x4_t vrnda_f16(float16x4_t a)
+ // case ARM64_INTRIN_VRNDA_F32: // FRINTA Vd.2S,Vn.2S float32x2_t vrnda_f32(float32x2_t a)
+ case ARM64_INTRIN_VRNDA_F64: // FRINTA Dd,Dn float64x1_t vrnda_f64(float64x1_t a)
+ case ARM64_INTRIN_VRNDI_F16: // FRINTI Vd.4H,Vn.4H float16x4_t vrndi_f16(float16x4_t a)
+ // case ARM64_INTRIN_VRNDI_F32: // FRINTI Vd.2S,Vn.2S float32x2_t vrndi_f32(float32x2_t a)
+ case ARM64_INTRIN_VRNDI_F64: // FRINTI Dd,Dn float64x1_t vrndi_f64(float64x1_t a)
+ case ARM64_INTRIN_VRNDM_F16: // FRINTM Vd.4H,Vn.4H float16x4_t vrndm_f16(float16x4_t a)
+ // case ARM64_INTRIN_VRNDM_F32: // FRINTM Vd.2S,Vn.2S float32x2_t vrndm_f32(float32x2_t a)
+ case ARM64_INTRIN_VRNDM_F64: // FRINTM Dd,Dn float64x1_t vrndm_f64(float64x1_t a)
+ case ARM64_INTRIN_VRNDN_F16: // FRINTN Vd.4H,Vn.4H float16x4_t vrndn_f16(float16x4_t a)
+ case ARM64_INTRIN_VRNDN_F32: // FRINTN Vd.2S,Vn.2S float32x2_t vrndn_f32(float32x2_t a)
+ case ARM64_INTRIN_VRNDN_F64: // FRINTN Dd,Dn float64x1_t vrndn_f64(float64x1_t a)
+ case ARM64_INTRIN_VRNDP_F16: // FRINTP Vd.4H,Vn.4H float16x4_t vrndp_f16(float16x4_t a)
+ // case ARM64_INTRIN_VRNDP_F32: // FRINTP Vd.2S,Vn.2S float32x2_t vrndp_f32(float32x2_t a)
+ case ARM64_INTRIN_VRNDP_F64: // FRINTP Dd,Dn float64x1_t vrndp_f64(float64x1_t a)
+ case ARM64_INTRIN_VRNDX_F16: // FRINTX Vd.4H,Vn.4H float16x4_t vrndx_f16(float16x4_t a)
+ // case ARM64_INTRIN_VRNDX_F32: // FRINTX Vd.2S,Vn.2S float32x2_t vrndx_f32(float32x2_t a)
+ case ARM64_INTRIN_VRNDX_F64: // FRINTX Dd,Dn float64x1_t vrndx_f64(float64x1_t a)
+ case ARM64_INTRIN_VRSQRTE_F16: // FRSQRTE Vd.4H,Vn.4H float16x4_t vrsqrte_f16(float16x4_t a)
+ case ARM64_INTRIN_VRSQRTE_F32: // FRSQRTE Vd.2S,Vn.2S float32x2_t vrsqrte_f32(float32x2_t a)
+ case ARM64_INTRIN_VRSQRTE_F64: // FRSQRTE Dd,Dn float64x1_t vrsqrte_f64(float64x1_t a)
+ case ARM64_INTRIN_VRSQRTED_F64: // FRSQRTE Dd,Dn float64_t vrsqrted_f64(float64_t a)
+ case ARM64_INTRIN_VRSQRTS_F16: // FRSQRTS Vd.4H,Vn.4H,Vm.4H float16x4_t vrsqrts_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VRSQRTS_F32: // FRSQRTS Vd.2S,Vn.2S,Vm.2S float32x2_t vrsqrts_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VRSQRTS_F64: // FRSQRTS Dd,Dn,Dm float64x1_t vrsqrts_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VRSQRTSD_F64: // FRSQRTS Dd,Dn,Dm float64_t vrsqrtsd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VSET_LANE_BF16: // INS Vd.H[lane],Vn.H[0] bfloat16x4_t vset_lane_bf16(bfloat16_t a, bfloat16x4_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_F16: // MOV Vd.H[lane],Vn.H[0] float16x4_t vset_lane_f16(float16_t a, float16x4_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_F32: // MOV Vd.S[lane],Rn float32x2_t vset_lane_f32(float32_t a, float32x2_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_F64: // MOV Vd.D[lane],Rn float64x1_t vset_lane_f64(float64_t a, float64x1_t v, const int lane)
+ case ARM64_INTRIN_VSQRT_F16: // FSQRT Vd.4H,Vn.4H float16x4_t vsqrt_f16(float16x4_t a)
+ case ARM64_INTRIN_VSQRT_F32: // FSQRT Vd.2S,Vn.2S float32x2_t vsqrt_f32(float32x2_t a)
+ case ARM64_INTRIN_VSQRT_F64: // FSQRT Dd,Dn float64x1_t vsqrt_f64(float64x1_t a)
+ case ARM64_INTRIN_VSUB_F16: // FSUB Vd.4H,Vn.4H,Vm.4H float16x4_t vsub_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VSUB_F32: // FSUB Vd.2S,Vn.2S,Vm.2S float32x2_t vsub_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VSUB_F64: // FSUB Dd,Dn,Dm float64x1_t vsub_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VTRN1_F16: // TRN1 Vd.4H,Vn.4H,Vm.4H float16x4_t vtrn1_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VTRN1_F32: // TRN1 Vd.2S,Vn.2S,Vm.2S float32x2_t vtrn1_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VTRN2_F16: // TRN2 Vd.4H,Vn.4H,Vm.4H float16x4_t vtrn2_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VTRN2_F32: // TRN2 Vd.2S,Vn.2S,Vm.2S float32x2_t vtrn2_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VUZP1_F16: // UZP1 Vd.4H,Vn.4H,Vm.4H float16x4_t vuzp1_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VUZP1_F32: // UZP1 Vd.2S,Vn.2S,Vm.2S float32x2_t vuzp1_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VUZP2_F16: // UZP2 Vd.4H,Vn.4H,Vm.4H float16x4_t vuzp2_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VUZP2_F32: // UZP2 Vd.2S,Vn.2S,Vm.2S float32x2_t vuzp2_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VZIP1_F16: // ZIP1 Vd.4H,Vn.4H,Vm.4H float16x4_t vzip1_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VZIP1_F32: // ZIP1 Vd.2S,Vn.2S,Vm.2S float32x2_t vzip1_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VZIP2_F16: // ZIP2 Vd.4H,Vn.4H,Vm.4H float16x4_t vzip2_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VZIP2_F32: // ZIP2 Vd.2S,Vn.2S,Vm.2S float32x2_t vzip2_f32(float32x2_t a, float32x2_t b)
+ return {Type::FloatType(8)};
+ case ARM64_INTRIN_VTRN_F16: // TRN1 Vd1.4H,Vn.4H,Vm.4H float16x4x2_t vtrn_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VTRN_F32: // TRN1 Vd1.2S,Vn.2S,Vm.2S float32x2x2_t vtrn_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VUZP_F16: // UZP1 Vd1.4H,Vn.4H,Vm.4H float16x4x2_t vuzp_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VUZP_F32: // UZP1 Vd1.2S,Vn.2S,Vm.2S float32x2x2_t vuzp_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VZIP_F16: // ZIP1 Vd1.4H,Vn.4H,Vm.4H float16x4x2_t vzip_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VZIP_F32: // ZIP1 Vd1.2S,Vn.2S,Vm.2S float32x2x2_t vzip_f32(float32x2_t a, float32x2_t b)
+ return {Type::FloatType(8), Type::FloatType(8)};
+ case ARM64_INTRIN_VADDV_S8: // ADDV Bd,Vn.8B int8_t vaddv_s8(int8x8_t a)
+ case ARM64_INTRIN_VADDV_U8: // ADDV Bd,Vn.8B uint8_t vaddv_u8(uint8x8_t a)
+ case ARM64_INTRIN_VADDVQ_S8: // ADDV Bd,Vn.16B int8_t vaddvq_s8(int8x16_t a)
+ case ARM64_INTRIN_VADDVQ_U8: // ADDV Bd,Vn.16B uint8_t vaddvq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VDUPB_LANE_P8: // DUP Bd,Vn.B[lane] poly8_t vdupb_lane_p8(poly8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPB_LANE_S8: // DUP Bd,Vn.B[lane] int8_t vdupb_lane_s8(int8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPB_LANE_U8: // DUP Bd,Vn.B[lane] uint8_t vdupb_lane_u8(uint8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPB_LANEQ_P8: // DUP Bd,Vn.B[lane] poly8_t vdupb_laneq_p8(poly8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUPB_LANEQ_S8: // DUP Bd,Vn.B[lane] int8_t vdupb_laneq_s8(int8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUPB_LANEQ_U8: // DUP Bd,Vn.B[lane] uint8_t vdupb_laneq_u8(uint8x16_t vec, const int lane)
+ case ARM64_INTRIN_VGET_LANE_P8: // UMOV Rd,Vn.B[lane] poly8_t vget_lane_p8(poly8x8_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_S8: // SMOV Rd,Vn.B[lane] int8_t vget_lane_s8(int8x8_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_U8: // UMOV Rd,Vn.B[lane] uint8_t vget_lane_u8(uint8x8_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_P8: // UMOV Rd,Vn.B[lane] poly8_t vgetq_lane_p8(poly8x16_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_S8: // SMOV Rd,Vn.B[lane] int8_t vgetq_lane_s8(int8x16_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_U8: // UMOV Rd,Vn.B[lane] uint8_t vgetq_lane_u8(uint8x16_t v, const int lane)
+ case ARM64_INTRIN_VMAXV_S8: // SMAXV Bd,Vn.8B int8_t vmaxv_s8(int8x8_t a)
+ case ARM64_INTRIN_VMAXV_U8: // UMAXV Bd,Vn.8B uint8_t vmaxv_u8(uint8x8_t a)
+ case ARM64_INTRIN_VMAXVQ_S8: // SMAXV Bd,Vn.16B int8_t vmaxvq_s8(int8x16_t a)
+ case ARM64_INTRIN_VMAXVQ_U8: // UMAXV Bd,Vn.16B uint8_t vmaxvq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VMINV_S8: // SMINV Bd,Vn.8B int8_t vminv_s8(int8x8_t a)
+ case ARM64_INTRIN_VMINV_U8: // UMINV Bd,Vn.8B uint8_t vminv_u8(uint8x8_t a)
+ case ARM64_INTRIN_VMINVQ_S8: // SMINV Bd,Vn.16B int8_t vminvq_s8(int8x16_t a)
+ case ARM64_INTRIN_VMINVQ_U8: // UMINV Bd,Vn.16B uint8_t vminvq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VQABSB_S8: // SQABS Bd,Bn int8_t vqabsb_s8(int8_t a)
+ case ARM64_INTRIN_VQADDB_S8: // SQADD Bd,Bn,Bm int8_t vqaddb_s8(int8_t a, int8_t b)
+ case ARM64_INTRIN_VQADDB_U8: // UQADD Bd,Bn,Bm uint8_t vqaddb_u8(uint8_t a, uint8_t b)
+ case ARM64_INTRIN_VQMOVNH_S16: // SQXTN Bd,Hn int8_t vqmovnh_s16(int16_t a)
+ case ARM64_INTRIN_VQMOVNH_U16: // UQXTN Bd,Hn uint8_t vqmovnh_u16(uint16_t a)
+ case ARM64_INTRIN_VQMOVUNH_S16: // SQXTUN Bd,Hn uint8_t vqmovunh_s16(int16_t a)
+ case ARM64_INTRIN_VQNEGB_S8: // SQNEG Bd,Bn int8_t vqnegb_s8(int8_t a)
+ case ARM64_INTRIN_VQRSHLB_S8: // SQRSHL Bd,Bn,Bm int8_t vqrshlb_s8(int8_t a, int8_t b)
+ case ARM64_INTRIN_VQRSHLB_U8: // UQRSHL Bd,Bn,Bm uint8_t vqrshlb_u8(uint8_t a, int8_t b)
+ case ARM64_INTRIN_VQRSHRNH_N_S16: // SQRSHRN Bd,Hn,#n int8_t vqrshrnh_n_s16(int16_t a, const int n)
+ case ARM64_INTRIN_VQRSHRNH_N_U16: // UQRSHRN Bd,Hn,#n uint8_t vqrshrnh_n_u16(uint16_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUNH_N_S16: // SQRSHRUN Bd,Hn,#n uint8_t vqrshrunh_n_s16(int16_t a, const int n)
+ case ARM64_INTRIN_VQSHLB_N_S8: // SQSHL Bd,Bn,#n int8_t vqshlb_n_s8(int8_t a, const int n)
+ case ARM64_INTRIN_VQSHLB_N_U8: // UQSHL Bd,Bn,#n uint8_t vqshlb_n_u8(uint8_t a, const int n)
+ case ARM64_INTRIN_VQSHLB_S8: // SQSHL Bd,Bn,Bm int8_t vqshlb_s8(int8_t a, int8_t b)
+ case ARM64_INTRIN_VQSHLB_U8: // UQSHL Bd,Bn,Bm uint8_t vqshlb_u8(uint8_t a, int8_t b)
+ case ARM64_INTRIN_VQSHLUB_N_S8: // SQSHLU Bd,Bn,#n uint8_t vqshlub_n_s8(int8_t a, const int n)
+ case ARM64_INTRIN_VQSHRNH_N_S16: // SQSHRN Bd,Hn,#n int8_t vqshrnh_n_s16(int16_t a, const int n)
+ case ARM64_INTRIN_VQSHRNH_N_U16: // UQSHRN Bd,Hn,#n uint8_t vqshrnh_n_u16(uint16_t a, const int n)
+ case ARM64_INTRIN_VQSHRUNH_N_S16: // SQSHRUN Bd,Hn,#n uint8_t vqshrunh_n_s16(int16_t a, const int n)
+ case ARM64_INTRIN_VQSUBB_S8: // SQSUB Bd,Bn,Bm int8_t vqsubb_s8(int8_t a, int8_t b)
+ case ARM64_INTRIN_VQSUBB_U8: // UQSUB Bd,Bn,Bm uint8_t vqsubb_u8(uint8_t a, uint8_t b)
+ case ARM64_INTRIN_VSQADDB_U8: // USQADD Bd,Bn uint8_t vsqaddb_u8(uint8_t a, int8_t b)
+ case ARM64_INTRIN_VUQADDB_S8: // SUQADD Bd,Bn int8_t vuqaddb_s8(int8_t a, uint8_t b)
+ return {Type::IntegerType(1, false)};
+ case ARM64_INTRIN_VABAL_HIGH_S16: // SABAL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vabal_high_s16(int32x4_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VABAL_HIGH_S32: // SABAL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vabal_high_s32(int64x2_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VABAL_HIGH_S8: // SABAL2 Vd.8H,Vn.16B,Vm.16B int16x8_t vabal_high_s8(int16x8_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VABAL_HIGH_U16: // UABAL2 Vd.4S,Vn.8H,Vm.8H uint32x4_t vabal_high_u16(uint32x4_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VABAL_HIGH_U32: // UABAL2 Vd.2D,Vn.4S,Vm.4S uint64x2_t vabal_high_u32(uint64x2_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VABAL_HIGH_U8: // UABAL2 Vd.8H,Vn.16B,Vm.16B uint16x8_t vabal_high_u8(uint16x8_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VABAL_S16: // SABAL Vd.4S,Vn.4H,Vm.4H int32x4_t vabal_s16(int32x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VABAL_S32: // SABAL Vd.2D,Vn.2S,Vm.2S int64x2_t vabal_s32(int64x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VABAL_S8: // SABAL Vd.8H,Vn.8B,Vm.8B int16x8_t vabal_s8(int16x8_t a, int8x8_t b, int8x8_t c)
+ case ARM64_INTRIN_VABAL_U16: // UABAL Vd.4S,Vn.4H,Vm.4H uint32x4_t vabal_u16(uint32x4_t a, uint16x4_t b, uint16x4_t c)
+ case ARM64_INTRIN_VABAL_U32: // UABAL Vd.2D,Vn.2S,Vm.2S uint64x2_t vabal_u32(uint64x2_t a, uint32x2_t b, uint32x2_t c)
+ case ARM64_INTRIN_VABAL_U8: // UABAL Vd.8H,Vn.8B,Vm.8B uint16x8_t vabal_u8(uint16x8_t a, uint8x8_t b, uint8x8_t c)
+ case ARM64_INTRIN_VABAQ_S16: // SABA Vd.8H,Vn.8H,Vm.8H int16x8_t vabaq_s16(int16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VABAQ_S32: // SABA Vd.4S,Vn.4S,Vm.4S int32x4_t vabaq_s32(int32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VABAQ_S8: // SABA Vd.16B,Vn.16B,Vm.16B int8x16_t vabaq_s8(int8x16_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VABAQ_U16: // UABA Vd.8H,Vn.8H,Vm.8H uint16x8_t vabaq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VABAQ_U32: // UABA Vd.4S,Vn.4S,Vm.4S uint32x4_t vabaq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VABAQ_U8: // UABA Vd.16B,Vn.16B,Vm.16B uint8x16_t vabaq_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VABDL_HIGH_S16: // SABDL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vabdl_high_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VABDL_HIGH_S32: // SABDL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vabdl_high_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VABDL_HIGH_S8: // SABDL2 Vd.8H,Vn.16B,Vm.16B int16x8_t vabdl_high_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VABDL_HIGH_U16: // UABDL2 Vd.4S,Vn.8H,Vm.8H uint32x4_t vabdl_high_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VABDL_HIGH_U32: // UABDL2 Vd.2D,Vn.4S,Vm.4S uint64x2_t vabdl_high_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VABDL_HIGH_U8: // UABDL2 Vd.8H,Vn.16B,Vm.16B uint16x8_t vabdl_high_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VABDL_S16: // SABDL Vd.4S,Vn.4H,Vm.4H int32x4_t vabdl_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VABDL_S32: // SABDL Vd.2D,Vn.2S,Vm.2S int64x2_t vabdl_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VABDL_S8: // SABDL Vd.8H,Vn.8B,Vm.8B int16x8_t vabdl_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VABDL_U16: // UABDL Vd.4S,Vn.4H,Vm.4H uint32x4_t vabdl_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VABDL_U32: // UABDL Vd.2D,Vn.2S,Vm.2S uint64x2_t vabdl_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VABDL_U8: // UABDL Vd.8H,Vn.8B,Vm.8B uint16x8_t vabdl_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VABDQ_S16: // SABD Vd.8H,Vn.8H,Vm.8H int16x8_t vabdq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VABDQ_S32: // SABD Vd.4S,Vn.4S,Vm.4S int32x4_t vabdq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VABDQ_S8: // SABD Vd.16B,Vn.16B,Vm.16B int8x16_t vabdq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VABDQ_U16: // UABD Vd.8H,Vn.8H,Vm.8H uint16x8_t vabdq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VABDQ_U32: // UABD Vd.4S,Vn.4S,Vm.4S uint32x4_t vabdq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VABDQ_U8: // UABD Vd.16B,Vn.16B,Vm.16B uint8x16_t vabdq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VABSQ_S16: // ABS Vd.8H,Vn.8H int16x8_t vabsq_s16(int16x8_t a)
+ case ARM64_INTRIN_VABSQ_S32: // ABS Vd.4S,Vn.4S int32x4_t vabsq_s32(int32x4_t a)
+ case ARM64_INTRIN_VABSQ_S64: // ABS Vd.2D,Vn.2D int64x2_t vabsq_s64(int64x2_t a)
+ case ARM64_INTRIN_VABSQ_S8: // ABS Vd.16B,Vn.16B int8x16_t vabsq_s8(int8x16_t a)
+ case ARM64_INTRIN_VADDHN_HIGH_S16: // ADDHN2 Vd.16B,Vn.8H,Vm.8H int8x16_t vaddhn_high_s16(int8x8_t r, int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VADDHN_HIGH_S32: // ADDHN2 Vd.8H,Vn.4S,Vm.4S int16x8_t vaddhn_high_s32(int16x4_t r, int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VADDHN_HIGH_S64: // ADDHN2 Vd.4S,Vn.2D,Vm.2D int32x4_t vaddhn_high_s64(int32x2_t r, int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VADDHN_HIGH_U16: // ADDHN2 Vd.16B,Vn.8H,Vm.8H uint8x16_t vaddhn_high_u16(uint8x8_t r, uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VADDHN_HIGH_U32: // ADDHN2 Vd.8H,Vn.4S,Vm.4S uint16x8_t vaddhn_high_u32(uint16x4_t r, uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VADDHN_HIGH_U64: // ADDHN2 Vd.4S,Vn.2D,Vm.2D uint32x4_t vaddhn_high_u64(uint32x2_t r, uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VADDL_HIGH_S16: // SADDL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vaddl_high_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VADDL_HIGH_S32: // SADDL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vaddl_high_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VADDL_HIGH_S8: // SADDL2 Vd.8H,Vn.16B,Vm.16B int16x8_t vaddl_high_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VADDL_HIGH_U16: // UADDL2 Vd.4S,Vn.8H,Vm.8H uint32x4_t vaddl_high_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VADDL_HIGH_U32: // UADDL2 Vd.2D,Vn.4S,Vm.4S uint64x2_t vaddl_high_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VADDL_HIGH_U8: // UADDL2 Vd.8H,Vn.16B,Vm.16B uint16x8_t vaddl_high_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VADDL_S16: // SADDL Vd.4S,Vn.4H,Vm.4H int32x4_t vaddl_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VADDL_S32: // SADDL Vd.2D,Vn.2S,Vm.2S int64x2_t vaddl_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VADDL_S8: // SADDL Vd.8H,Vn.8B,Vm.8B int16x8_t vaddl_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VADDL_U16: // UADDL Vd.4S,Vn.4H,Vm.4H uint32x4_t vaddl_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VADDL_U32: // UADDL Vd.2D,Vn.2S,Vm.2S uint64x2_t vaddl_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VADDL_U8: // UADDL Vd.8H,Vn.8B,Vm.8B uint16x8_t vaddl_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VADDQ_P128: // EOR Vd.16B,Vn.16B,Vm.16B poly128_t vaddq_p128(poly128_t a, poly128_t b)
+ case ARM64_INTRIN_VADDQ_P16: // EOR Vd.16B,Vn.16B,Vm.16B poly16x8_t vaddq_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VADDQ_P64: // EOR Vd.16B,Vn.16B,Vm.16B poly64x2_t vaddq_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VADDQ_P8: // EOR Vd.16B,Vn.16B,Vm.16B poly8x16_t vaddq_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VADDQ_S16: // ADD Vd.8H,Vn.8H,Vm.8H int16x8_t vaddq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VADDQ_S32: // ADD Vd.4S,Vn.4S,Vm.4S int32x4_t vaddq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VADDQ_S64: // ADD Vd.2D,Vn.2D,Vm.2D int64x2_t vaddq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VADDQ_S8: // ADD Vd.16B,Vn.16B,Vm.16B int8x16_t vaddq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VADDQ_U16: // ADD Vd.8H,Vn.8H,Vm.8H uint16x8_t vaddq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VADDQ_U32: // ADD Vd.4S,Vn.4S,Vm.4S uint32x4_t vaddq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VADDQ_U64: // ADD Vd.2D,Vn.2D,Vm.2D uint64x2_t vaddq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VADDQ_U8: // ADD Vd.16B,Vn.16B,Vm.16B uint8x16_t vaddq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VADDW_HIGH_S16: // SADDW2 Vd.4S,Vn.4S,Vm.8H int32x4_t vaddw_high_s16(int32x4_t a, int16x8_t b)
+ case ARM64_INTRIN_VADDW_HIGH_S32: // SADDW2 Vd.2D,Vn.2D,Vm.4S int64x2_t vaddw_high_s32(int64x2_t a, int32x4_t b)
+ case ARM64_INTRIN_VADDW_HIGH_S8: // SADDW2 Vd.8H,Vn.8H,Vm.16B int16x8_t vaddw_high_s8(int16x8_t a, int8x16_t b)
+ case ARM64_INTRIN_VADDW_HIGH_U16: // UADDW2 Vd.4S,Vn.4S,Vm.8H uint32x4_t vaddw_high_u16(uint32x4_t a, uint16x8_t b)
+ case ARM64_INTRIN_VADDW_HIGH_U32: // UADDW2 Vd.2D,Vn.2D,Vm.4S uint64x2_t vaddw_high_u32(uint64x2_t a, uint32x4_t b)
+ case ARM64_INTRIN_VADDW_HIGH_U8: // UADDW2 Vd.8H,Vn.8H,Vm.16B uint16x8_t vaddw_high_u8(uint16x8_t a, uint8x16_t b)
+ case ARM64_INTRIN_VADDW_S16: // SADDW Vd.4S,Vn.4S,Vm.4H int32x4_t vaddw_s16(int32x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VADDW_S32: // SADDW Vd.2D,Vn.2D,Vm.2S int64x2_t vaddw_s32(int64x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VADDW_S8: // SADDW Vd.8H,Vn.8H,Vm.8B int16x8_t vaddw_s8(int16x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VADDW_U16: // UADDW Vd.4S,Vn.4S,Vm.4H uint32x4_t vaddw_u16(uint32x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VADDW_U32: // UADDW Vd.2D,Vn.2D,Vm.2S uint64x2_t vaddw_u32(uint64x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VADDW_U8: // UADDW Vd.8H,Vn.8H,Vm.8B uint16x8_t vaddw_u8(uint16x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VAESDQ_U8: // AESD Vd.16B,Vn.16B uint8x16_t vaesdq_u8(uint8x16_t data, uint8x16_t key)
+ case ARM64_INTRIN_VAESEQ_U8: // AESE Vd.16B,Vn.16B uint8x16_t vaeseq_u8(uint8x16_t data, uint8x16_t key)
+ case ARM64_INTRIN_VAESIMCQ_U8: // AESIMC Vd.16B,Vn.16B uint8x16_t vaesimcq_u8(uint8x16_t data)
+ case ARM64_INTRIN_VAESMCQ_U8: // AESMC Vd.16B,Vn.16B uint8x16_t vaesmcq_u8(uint8x16_t data)
+ case ARM64_INTRIN_VANDQ_S16: // AND Vd.16B,Vn.16B,Vm.16B int16x8_t vandq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VANDQ_S32: // AND Vd.16B,Vn.16B,Vm.16B int32x4_t vandq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VANDQ_S64: // AND Vd.16B,Vn.16B,Vm.16B int64x2_t vandq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VANDQ_S8: // AND Vd.16B,Vn.16B,Vm.16B int8x16_t vandq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VANDQ_U16: // AND Vd.16B,Vn.16B,Vm.16B uint16x8_t vandq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VANDQ_U32: // AND Vd.16B,Vn.16B,Vm.16B uint32x4_t vandq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VANDQ_U64: // AND Vd.16B,Vn.16B,Vm.16B uint64x2_t vandq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VANDQ_U8: // AND Vd.16B,Vn.16B,Vm.16B uint8x16_t vandq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VBCAXQ_S16: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B int16x8_t vbcaxq_s16(int16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VBCAXQ_S32: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B int32x4_t vbcaxq_s32(int32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VBCAXQ_S64: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B int64x2_t vbcaxq_s64(int64x2_t a, int64x2_t b, int64x2_t c)
+ case ARM64_INTRIN_VBCAXQ_S8: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B int8x16_t vbcaxq_s8(int8x16_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VBCAXQ_U16: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B uint16x8_t vbcaxq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VBCAXQ_U32: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B uint32x4_t vbcaxq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VBCAXQ_U64: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B uint64x2_t vbcaxq_u64(uint64x2_t a, uint64x2_t b, uint64x2_t c)
+ case ARM64_INTRIN_VBCAXQ_U8: // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B uint8x16_t vbcaxq_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VBICQ_S16: // BIC Vd.16B,Vn.16B,Vm.16B int16x8_t vbicq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VBICQ_S32: // BIC Vd.16B,Vn.16B,Vm.16B int32x4_t vbicq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VBICQ_S64: // BIC Vd.16B,Vn.16B,Vm.16B int64x2_t vbicq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VBICQ_S8: // BIC Vd.16B,Vn.16B,Vm.16B int8x16_t vbicq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VBICQ_U16: // BIC Vd.16B,Vn.16B,Vm.16B uint16x8_t vbicq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VBICQ_U32: // BIC Vd.16B,Vn.16B,Vm.16B uint32x4_t vbicq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VBICQ_U64: // BIC Vd.16B,Vn.16B,Vm.16B uint64x2_t vbicq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VBICQ_U8: // BIC Vd.16B,Vn.16B,Vm.16B uint8x16_t vbicq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VBSLQ_P16: // BSL Vd.16B,Vn.16B,Vm.16B poly16x8_t vbslq_p16(uint16x8_t a, poly16x8_t b, poly16x8_t c)
+ case ARM64_INTRIN_VBSLQ_P64: // BSL Vd.16B,Vn.16B,Vm.16B poly64x2_t vbslq_p64(poly64x2_t a, poly64x2_t b, poly64x2_t c)
+ case ARM64_INTRIN_VBSLQ_P8: // BSL Vd.16B,Vn.16B,Vm.16B poly8x16_t vbslq_p8(uint8x16_t a, poly8x16_t b, poly8x16_t c)
+ case ARM64_INTRIN_VBSLQ_S16: // BSL Vd.16B,Vn.16B,Vm.16B int16x8_t vbslq_s16(uint16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VBSLQ_S32: // BSL Vd.16B,Vn.16B,Vm.16B int32x4_t vbslq_s32(uint32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VBSLQ_S64: // BSL Vd.16B,Vn.16B,Vm.16B int64x2_t vbslq_s64(uint64x2_t a, int64x2_t b, int64x2_t c)
+ case ARM64_INTRIN_VBSLQ_S8: // BSL Vd.16B,Vn.16B,Vm.16B int8x16_t vbslq_s8(uint8x16_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VBSLQ_U16: // BSL Vd.16B,Vn.16B,Vm.16B uint16x8_t vbslq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VBSLQ_U32: // BSL Vd.16B,Vn.16B,Vm.16B uint32x4_t vbslq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VBSLQ_U64: // BSL Vd.16B,Vn.16B,Vm.16B uint64x2_t vbslq_u64(uint64x2_t a, uint64x2_t b, uint64x2_t c)
+ case ARM64_INTRIN_VBSLQ_U8: // BSL Vd.16B,Vn.16B,Vm.16B uint8x16_t vbslq_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VCAGEQ_F16: // FACGE Vd.8H,Vn.8H,Vm.8H uint16x8_t vcageq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCAGEQ_F32: // FACGE Vd.4S,Vn.4S,Vm.4S uint32x4_t vcageq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCAGEQ_F64: // FACGE Vd.2D,Vn.2D,Vm.2D uint64x2_t vcageq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCAGTQ_F16: // FACGT Vd.8H,Vn.8H,Vm.8H uint16x8_t vcagtq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCAGTQ_F32: // FACGT Vd.4S,Vn.4S,Vm.4S uint32x4_t vcagtq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCAGTQ_F64: // FACGT Vd.2D,Vn.2D,Vm.2D uint64x2_t vcagtq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCALEQ_F16: // FACGE Vd.8H,Vn.8H,Vm.8H uint16x8_t vcaleq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCALEQ_F32: // FACGE Vd.4S,Vm.4S,Vn.4S uint32x4_t vcaleq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCALEQ_F64: // FACGE Vd.2D,Vm.2D,Vn.2D uint64x2_t vcaleq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCALTQ_F16: // FACGT Vd.8H,Vn.8H,Vm.8H uint16x8_t vcaltq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCALTQ_F32: // FACGT Vd.4S,Vm.4S,Vn.4S uint32x4_t vcaltq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCALTQ_F64: // FACGT Vd.2D,Vn.2D,Vm.2D uint64x2_t vcaltq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCEQQ_F16: // FCMEQ Vd.8H,Vn.8H,Vm.8H uint16x8_t vceqq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCEQQ_F32: // FCMEQ Vd.4S,Vn.4S,Vm.4S uint32x4_t vceqq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCEQQ_F64: // FCMEQ Vd.2D,Vn.2D,Vm.2D uint64x2_t vceqq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCEQQ_P64: // CMEQ Vd.2D,Vn.2D,Vm.2D uint64x2_t vceqq_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VCEQQ_P8: // CMEQ Vd.16B,Vn.16B,Vm.16B uint8x16_t vceqq_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VCEQQ_S16: // CMEQ Vd.8H,Vn.8H,Vm.8H uint16x8_t vceqq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VCEQQ_S32: // CMEQ Vd.4S,Vn.4S,Vm.4S uint32x4_t vceqq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VCEQQ_S64: // CMEQ Vd.2D,Vn.2D,Vm.2D uint64x2_t vceqq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VCEQQ_S8: // CMEQ Vd.16B,Vn.16B,Vm.16B uint8x16_t vceqq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VCEQQ_U16: // CMEQ Vd.8H,Vn.8H,Vm.8H uint16x8_t vceqq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VCEQQ_U32: // CMEQ Vd.4S,Vn.4S,Vm.4S uint32x4_t vceqq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VCEQQ_U64: // CMEQ Vd.2D,Vn.2D,Vm.2D uint64x2_t vceqq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VCEQQ_U8: // CMEQ Vd.16B,Vn.16B,Vm.16B uint8x16_t vceqq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VCEQZQ_F16: // FCMEQ Vd.8H,Vn.8H,#0 uint16x8_t vceqzq_f16(float16x8_t a)
+ case ARM64_INTRIN_VCEQZQ_F32: // FCMEQ Vd.4S,Vn.4S,#0 uint32x4_t vceqzq_f32(float32x4_t a)
+ case ARM64_INTRIN_VCEQZQ_F64: // FCMEQ Vd.2D,Vn.2D,#0 uint64x2_t vceqzq_f64(float64x2_t a)
+ case ARM64_INTRIN_VCEQZQ_P64: // CMEQ Vd.2D,Vn.2D,#0 uint64x2_t vceqzq_p64(poly64x2_t a)
+ case ARM64_INTRIN_VCEQZQ_P8: // CMEQ Vd.16B,Vn.16B,#0 uint8x16_t vceqzq_p8(poly8x16_t a)
+ case ARM64_INTRIN_VCEQZQ_S16: // CMEQ Vd.8H,Vn.8H,#0 uint16x8_t vceqzq_s16(int16x8_t a)
+ case ARM64_INTRIN_VCEQZQ_S32: // CMEQ Vd.4S,Vn.4S,#0 uint32x4_t vceqzq_s32(int32x4_t a)
+ case ARM64_INTRIN_VCEQZQ_S64: // CMEQ Vd.2D,Vn.2D,#0 uint64x2_t vceqzq_s64(int64x2_t a)
+ case ARM64_INTRIN_VCEQZQ_S8: // CMEQ Vd.16B,Vn.16B,#0 uint8x16_t vceqzq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCEQZQ_U16: // CMEQ Vd.8H,Vn.8H,#0 uint16x8_t vceqzq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VCEQZQ_U32: // CMEQ Vd.4S,Vn.4S,#0 uint32x4_t vceqzq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VCEQZQ_U64: // CMEQ Vd.2D,Vn.2D,#0 uint64x2_t vceqzq_u64(uint64x2_t a)
+ case ARM64_INTRIN_VCEQZQ_U8: // CMEQ Vd.16B,Vn.16B,#0 uint8x16_t vceqzq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VCGEQ_F16: // FCMGE Vd.8H,Vn.8H,Vm.8H uint16x8_t vcgeq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCGEQ_F32: // FCMGE Vd.4S,Vm.4S,Vn.4S uint32x4_t vcgeq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCGEQ_F64: // FCMGE Vd.2D,Vm.2D,Vn.2D uint64x2_t vcgeq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCGEQ_S16: // CMGE Vd.8H,Vm.8H,Vn.8H uint16x8_t vcgeq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VCGEQ_S32: // CMGE Vd.4S,Vm.4S,Vn.4S uint32x4_t vcgeq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VCGEQ_S64: // CMGE Vd.2D,Vm.2D,Vn.2D uint64x2_t vcgeq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VCGEQ_S8: // CMGE Vd.16B,Vm.16B,Vn.16B uint8x16_t vcgeq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VCGEQ_U16: // CMHS Vd.8H,Vm.8H,Vn.8H uint16x8_t vcgeq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VCGEQ_U32: // CMHS Vd.4S,Vm.4S,Vn.4S uint32x4_t vcgeq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VCGEQ_U64: // CMHS Vd.2D,Vm.2D,Vn.2D uint64x2_t vcgeq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VCGEQ_U8: // CMHS Vd.16B,Vm.16B,Vn.16B uint8x16_t vcgeq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VCGEZQ_F16: // FCMGE Vd.8H,Vn.8H,#0 uint16x8_t vcgezq_f16(float16x8_t a)
+ case ARM64_INTRIN_VCGEZQ_F32: // FCMGE Vd.4S,Vn.4S,#0 uint32x4_t vcgezq_f32(float32x4_t a)
+ case ARM64_INTRIN_VCGEZQ_F64: // FCMGE Vd.2D,Vn.2D,#0 uint64x2_t vcgezq_f64(float64x2_t a)
+ case ARM64_INTRIN_VCGEZQ_S16: // CMGE Vd.8H,Vn.8H,#0 uint16x8_t vcgezq_s16(int16x8_t a)
+ case ARM64_INTRIN_VCGEZQ_S32: // CMGE Vd.4S,Vn.4S,#0 uint32x4_t vcgezq_s32(int32x4_t a)
+ case ARM64_INTRIN_VCGEZQ_S64: // CMGE Vd.2D,Vn.2D,#0 uint64x2_t vcgezq_s64(int64x2_t a)
+ case ARM64_INTRIN_VCGEZQ_S8: // CMGE Vd.16B,Vn.16B,#0 uint8x16_t vcgezq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCGTQ_F16: // FCMGT Vd.8H,Vn.8H,Vm.8H uint16x8_t vcgtq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCGTQ_F32: // FCMGT Vd.4S,Vn.4S,Vm.4S uint32x4_t vcgtq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCGTQ_F64: // FCMGT Vd.2D,Vn.2D,Vm.2D uint64x2_t vcgtq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCGTQ_S16: // CMGT Vd.8H,Vn.8H,Vm.8H uint16x8_t vcgtq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VCGTQ_S32: // CMGT Vd.4S,Vn.4S,Vm.4S uint32x4_t vcgtq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VCGTQ_S64: // CMGT Vd.2D,Vn.2D,Vm.2D uint64x2_t vcgtq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VCGTQ_S8: // CMGT Vd.16B,Vn.16B,Vm.16B uint8x16_t vcgtq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VCGTQ_U16: // CMHI Vd.8H,Vn.8H,Vm.8H uint16x8_t vcgtq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VCGTQ_U32: // CMHI Vd.4S,Vn.4S,Vm.4S uint32x4_t vcgtq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VCGTQ_U64: // CMHI Vd.2D,Vn.2D,Vm.2D uint64x2_t vcgtq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VCGTQ_U8: // CMHI Vd.16B,Vn.16B,Vm.16B uint8x16_t vcgtq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VCGTZQ_F16: // FCMGT Vd.8H,Vn.8H,#0 uint16x8_t vcgtzq_f16(float16x8_t a)
+ case ARM64_INTRIN_VCGTZQ_F32: // FCMGT Vd.4S,Vn.4S,#0 uint32x4_t vcgtzq_f32(float32x4_t a)
+ case ARM64_INTRIN_VCGTZQ_F64: // FCMGT Vd.2D,Vn.2D,#0 uint64x2_t vcgtzq_f64(float64x2_t a)
+ case ARM64_INTRIN_VCGTZQ_S16: // CMGT Vd.8H,Vn.8H,#0 uint16x8_t vcgtzq_s16(int16x8_t a)
+ case ARM64_INTRIN_VCGTZQ_S32: // CMGT Vd.4S,Vn.4S,#0 uint32x4_t vcgtzq_s32(int32x4_t a)
+ case ARM64_INTRIN_VCGTZQ_S64: // CMGT Vd.2D,Vn.2D,#0 uint64x2_t vcgtzq_s64(int64x2_t a)
+ case ARM64_INTRIN_VCGTZQ_S8: // CMGT Vd.16B,Vn.16B,#0 uint8x16_t vcgtzq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCLEQ_F16: // FCMGE Vd.8H,Vn.8H,Vm.8H uint16x8_t vcleq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCLEQ_F32: // FCMGE Vd.4S,Vm.4S,Vn.4S uint32x4_t vcleq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCLEQ_F64: // FCMGE Vd.2D,Vm.2D,Vn.2D uint64x2_t vcleq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCLEQ_S16: // CMGE Vd.8H,Vm.8H,Vn.8H uint16x8_t vcleq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VCLEQ_S32: // CMGE Vd.4S,Vm.4S,Vn.4S uint32x4_t vcleq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VCLEQ_S64: // CMGE Vd.2D,Vm.2D,Vn.2D uint64x2_t vcleq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VCLEQ_S8: // CMGE Vd.16B,Vm.16B,Vn.16B uint8x16_t vcleq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VCLEQ_U16: // CMHS Vd.8H,Vm.8H,Vn.8H uint16x8_t vcleq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VCLEQ_U32: // CMHS Vd.4S,Vm.4S,Vn.4S uint32x4_t vcleq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VCLEQ_U64: // CMHS Vd.2D,Vm.2D,Vn.2D uint64x2_t vcleq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VCLEQ_U8: // CMHS Vd.16B,Vm.16B,Vn.16B uint8x16_t vcleq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VCLEZQ_F16: // FCMLE Vd.8H,Vn.8H,#0 uint16x8_t vclezq_f16(float16x8_t a)
+ case ARM64_INTRIN_VCLEZQ_F32: // FCMLE Vd.4S,Vn.4S,#0 uint32x4_t vclezq_f32(float32x4_t a)
+ case ARM64_INTRIN_VCLEZQ_F64: // FCMLE Vd.2D,Vn.2D,#0 uint64x2_t vclezq_f64(float64x2_t a)
+ case ARM64_INTRIN_VCLEZQ_S16: // CMLE Vd.8H,Vn.8H,#0 uint16x8_t vclezq_s16(int16x8_t a)
+ case ARM64_INTRIN_VCLEZQ_S32: // CMLE Vd.4S,Vn.4S,#0 uint32x4_t vclezq_s32(int32x4_t a)
+ case ARM64_INTRIN_VCLEZQ_S64: // CMLE Vd.2D,Vn.2D,#0 uint64x2_t vclezq_s64(int64x2_t a)
+ case ARM64_INTRIN_VCLEZQ_S8: // CMLE Vd.16B,Vn.16B,#0 uint8x16_t vclezq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCLSQ_S16: // CLS Vd.8H,Vn.8H int16x8_t vclsq_s16(int16x8_t a)
+ case ARM64_INTRIN_VCLSQ_S32: // CLS Vd.4S,Vn.4S int32x4_t vclsq_s32(int32x4_t a)
+ case ARM64_INTRIN_VCLSQ_S8: // CLS Vd.16B,Vn.16B int8x16_t vclsq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCLSQ_U16: // CLS Vd.8H,Vn.8H int16x8_t vclsq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VCLSQ_U32: // CLS Vd.4S,Vn.4S int32x4_t vclsq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VCLSQ_U8: // CLS Vd.16B,Vn.16B int8x16_t vclsq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VCLTQ_F16: // FCMGT Vd.8H,Vn.8H,Vm.8H uint16x8_t vcltq_f16(float16x8_t a, float16x8_t b)
+ case ARM64_INTRIN_VCLTQ_F32: // FCMGT Vd.4S,Vm.4S,Vn.4S uint32x4_t vcltq_f32(float32x4_t a, float32x4_t b)
+ case ARM64_INTRIN_VCLTQ_F64: // FCMGT Vd.2D,Vm.2D,Vn.2D uint64x2_t vcltq_f64(float64x2_t a, float64x2_t b)
+ case ARM64_INTRIN_VCLTQ_S16: // CMGT Vd.8H,Vm.8H,Vn.8H uint16x8_t vcltq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VCLTQ_S32: // CMGT Vd.4S,Vm.4S,Vn.4S uint32x4_t vcltq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VCLTQ_S64: // CMGT Vd.2D,Vm.2D,Vn.2D uint64x2_t vcltq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VCLTQ_S8: // CMGT Vd.16B,Vm.16B,Vn.16B uint8x16_t vcltq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VCLTQ_U16: // CMHI Vd.8H,Vm.8H,Vn.8H uint16x8_t vcltq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VCLTQ_U32: // CMHI Vd.4S,Vm.4S,Vn.4S uint32x4_t vcltq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VCLTQ_U64: // CMHI Vd.2D,Vm.2D,Vn.2D uint64x2_t vcltq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VCLTQ_U8: // CMHI Vd.16B,Vm.16B,Vn.16B uint8x16_t vcltq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VCLTZQ_F16: // FCMLT Vd.8H,Vn.8H,#0 uint16x8_t vcltzq_f16(float16x8_t a)
+ case ARM64_INTRIN_VCLTZQ_F32: // FCMLT Vd.4S,Vn.4S,#0 uint32x4_t vcltzq_f32(float32x4_t a)
+ case ARM64_INTRIN_VCLTZQ_F64: // FCMLT Vd.2D,Vn.2D,#0 uint64x2_t vcltzq_f64(float64x2_t a)
+ case ARM64_INTRIN_VCLTZQ_S16: // CMLT Vd.8H,Vn.8H,#0 uint16x8_t vcltzq_s16(int16x8_t a)
+ case ARM64_INTRIN_VCLTZQ_S32: // CMLT Vd.4S,Vn.4S,#0 uint32x4_t vcltzq_s32(int32x4_t a)
+ case ARM64_INTRIN_VCLTZQ_S64: // CMLT Vd.2D,Vn.2D,#0 uint64x2_t vcltzq_s64(int64x2_t a)
+ case ARM64_INTRIN_VCLTZQ_S8: // CMLT Vd.16B,Vn.16B,#0 uint8x16_t vcltzq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCLZQ_S16: // CLZ Vd.8H,Vn.8H int16x8_t vclzq_s16(int16x8_t a)
+ case ARM64_INTRIN_VCLZQ_S32: // CLZ Vd.4S,Vn.4S int32x4_t vclzq_s32(int32x4_t a)
+ case ARM64_INTRIN_VCLZQ_S8: // CLZ Vd.16B,Vn.16B int8x16_t vclzq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCLZQ_U16: // CLZ Vd.8H,Vn.8H uint16x8_t vclzq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VCLZQ_U32: // CLZ Vd.4S,Vn.4S uint32x4_t vclzq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VCLZQ_U8: // CLZ Vd.16B,Vn.16B uint8x16_t vclzq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VCNTQ_P8: // CNT Vd.16B,Vn.16B poly8x16_t vcntq_p8(poly8x16_t a)
+ case ARM64_INTRIN_VCNTQ_S8: // CNT Vd.16B,Vn.16B int8x16_t vcntq_s8(int8x16_t a)
+ case ARM64_INTRIN_VCNTQ_U8: // CNT Vd.16B,Vn.16B uint8x16_t vcntq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VCOMBINE_P16: // INS Vd.D[1],Vm.D[0] poly16x8_t vcombine_p16(poly16x4_t low, poly16x4_t high)
+ case ARM64_INTRIN_VCOMBINE_P64: // INS Vd.D[1],Vm.D[0] poly64x2_t vcombine_p64(poly64x1_t low, poly64x1_t high)
+ case ARM64_INTRIN_VCOMBINE_P8: // INS Vd.D[1],Vm.D[0] poly8x16_t vcombine_p8(poly8x8_t low, poly8x8_t high)
+ case ARM64_INTRIN_VCOMBINE_S16: // INS Vd.D[1],Vm.D[0] int16x8_t vcombine_s16(int16x4_t low, int16x4_t high)
+ case ARM64_INTRIN_VCOMBINE_S32: // INS Vd.D[1],Vm.D[0] int32x4_t vcombine_s32(int32x2_t low, int32x2_t high)
+ case ARM64_INTRIN_VCOMBINE_S64: // INS Vd.D[1],Vm.D[0] int64x2_t vcombine_s64(int64x1_t low, int64x1_t high)
+ case ARM64_INTRIN_VCOMBINE_S8: // INS Vd.D[1],Vm.D[0] int8x16_t vcombine_s8(int8x8_t low, int8x8_t high)
+ case ARM64_INTRIN_VCOMBINE_U16: // INS Vd.D[1],Vm.D[0] uint16x8_t vcombine_u16(uint16x4_t low, uint16x4_t high)
+ case ARM64_INTRIN_VCOMBINE_U32: // INS Vd.D[1],Vm.D[0] uint32x4_t vcombine_u32(uint32x2_t low, uint32x2_t high)
+ case ARM64_INTRIN_VCOMBINE_U64: // INS Vd.D[1],Vm.D[0] uint64x2_t vcombine_u64(uint64x1_t low, uint64x1_t high)
+ case ARM64_INTRIN_VCOMBINE_U8: // INS Vd.D[1],Vm.D[0] uint8x16_t vcombine_u8(uint8x8_t low, uint8x8_t high)
+ case ARM64_INTRIN_VCOPYQ_LANE_P16: // INS Vd.H[lane1],Vn.H[lane2] poly16x8_t vcopyq_lane_p16(poly16x8_t a, const int lane1, poly16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_P64: // INS Vd.D[lane1],Vn.D[lane2] poly64x2_t vcopyq_lane_p64(poly64x2_t a, const int lane1, poly64x1_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_P8: // INS Vd.B[lane1],Vn.B[lane2] poly8x16_t vcopyq_lane_p8(poly8x16_t a, const int lane1, poly8x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_S16: // INS Vd.H[lane1],Vn.H[lane2] int16x8_t vcopyq_lane_s16(int16x8_t a, const int lane1, int16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_S32: // INS Vd.S[lane1],Vn.S[lane2] int32x4_t vcopyq_lane_s32(int32x4_t a, const int lane1, int32x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_S64: // INS Vd.D[lane1],Vn.D[lane2] int64x2_t vcopyq_lane_s64(int64x2_t a, const int lane1, int64x1_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_S8: // INS Vd.B[lane1],Vn.B[lane2] int8x16_t vcopyq_lane_s8(int8x16_t a, const int lane1, int8x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_U16: // INS Vd.H[lane1],Vn.H[lane2] uint16x8_t vcopyq_lane_u16(uint16x8_t a, const int lane1, uint16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_U32: // INS Vd.S[lane1],Vn.S[lane2] uint32x4_t vcopyq_lane_u32(uint32x4_t a, const int lane1, uint32x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_U64: // INS Vd.D[lane1],Vn.D[lane2] uint64x2_t vcopyq_lane_u64(uint64x2_t a, const int lane1, uint64x1_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANE_U8: // INS Vd.B[lane1],Vn.B[lane2] uint8x16_t vcopyq_lane_u8(uint8x16_t a, const int lane1, uint8x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_P16: // INS Vd.H[lane1],Vn.H[lane2] poly16x8_t vcopyq_laneq_p16(poly16x8_t a, const int lane1, poly16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_P64: // INS Vd.D[lane1],Vn.D[lane2] poly64x2_t vcopyq_laneq_p64(poly64x2_t a, const int lane1, poly64x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_P8: // INS Vd.B[lane1],Vn.B[lane2] poly8x16_t vcopyq_laneq_p8(poly8x16_t a, const int lane1, poly8x16_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_S16: // INS Vd.H[lane1],Vn.H[lane2] int16x8_t vcopyq_laneq_s16(int16x8_t a, const int lane1, int16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_S32: // INS Vd.S[lane1],Vn.S[lane2] int32x4_t vcopyq_laneq_s32(int32x4_t a, const int lane1, int32x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_S64: // INS Vd.D[lane1],Vn.D[lane2] int64x2_t vcopyq_laneq_s64(int64x2_t a, const int lane1, int64x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_S8: // INS Vd.B[lane1],Vn.B[lane2] int8x16_t vcopyq_laneq_s8(int8x16_t a, const int lane1, int8x16_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_U16: // INS Vd.H[lane1],Vn.H[lane2] uint16x8_t vcopyq_laneq_u16(uint16x8_t a, const int lane1, uint16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_U32: // INS Vd.S[lane1],Vn.S[lane2] uint32x4_t vcopyq_laneq_u32(uint32x4_t a, const int lane1, uint32x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_U64: // INS Vd.D[lane1],Vn.D[lane2] uint64x2_t vcopyq_laneq_u64(uint64x2_t a, const int lane1, uint64x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPYQ_LANEQ_U8: // INS Vd.B[lane1],Vn.B[lane2] uint8x16_t vcopyq_laneq_u8(uint8x16_t a, const int lane1, uint8x16_t b, const int lane2)
+ case ARM64_INTRIN_VCVTAQ_S16_F16: // FCVTAS Vd.8H,Vn.8H int16x8_t vcvtaq_s16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTAQ_S32_F32: // FCVTAS Vd.4S,Vn.4S int32x4_t vcvtaq_s32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTAQ_S64_F64: // FCVTAS Vd.2D,Vn.2D int64x2_t vcvtaq_s64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTAQ_U16_F16: // FCVTAU Vd.8H,Vn.8H uint16x8_t vcvtaq_u16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTAQ_U32_F32: // FCVTAU Vd.4S,Vn.4S uint32x4_t vcvtaq_u32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTAQ_U64_F64: // FCVTAU Vd.2D,Vn.2D uint64x2_t vcvtaq_u64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTMQ_S16_F16: // FCVTMS Vd.8H,Vn.8H int16x8_t vcvtmq_s16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTMQ_S32_F32: // FCVTMS Vd.4S,Vn.4S int32x4_t vcvtmq_s32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTMQ_S64_F64: // FCVTMS Vd.2D,Vn.2D int64x2_t vcvtmq_s64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTMQ_U16_F16: // FCVTMU Vd.8H,Vn.8H uint16x8_t vcvtmq_u16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTMQ_U32_F32: // FCVTMU Vd.4S,Vn.4S uint32x4_t vcvtmq_u32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTMQ_U64_F64: // FCVTMU Vd.2D,Vn.2D uint64x2_t vcvtmq_u64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTNQ_S16_F16: // FCVTNS Vd.8H,Vn.8H int16x8_t vcvtnq_s16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTNQ_S32_F32: // FCVTNS Vd.4S,Vn.4S int32x4_t vcvtnq_s32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTNQ_S64_F64: // FCVTNS Vd.2D,Vn.2D int64x2_t vcvtnq_s64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTNQ_U16_F16: // FCVTNU Vd.8H,Vn.8H uint16x8_t vcvtnq_u16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTNQ_U32_F32: // FCVTNU Vd.4S,Vn.4S uint32x4_t vcvtnq_u32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTNQ_U64_F64: // FCVTNU Vd.2D,Vn.2D uint64x2_t vcvtnq_u64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTPQ_S16_F16: // FCVTPS Vd.8H,Vn.8H int16x8_t vcvtpq_s16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTPQ_S32_F32: // FCVTPS Vd.4S,Vn.4S int32x4_t vcvtpq_s32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTPQ_S64_F64: // FCVTPS Vd.2D,Vn.2D int64x2_t vcvtpq_s64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTPQ_U16_F16: // FCVTPU Vd.8H,Vn.8H uint16x8_t vcvtpq_u16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTPQ_U32_F32: // FCVTPU Vd.4S,Vn.4S uint32x4_t vcvtpq_u32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTPQ_U64_F64: // FCVTPU Vd.2D,Vn.2D uint64x2_t vcvtpq_u64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTQ_N_S16_F16: // FCVTZS Vd.8H,Vn.8H,#n int16x8_t vcvtq_n_s16_f16(float16x8_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_S32_F32: // FCVTZS Vd.4S,Vn.4S,#n int32x4_t vcvtq_n_s32_f32(float32x4_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_S64_F64: // FCVTZS Vd.2D,Vn.2D,#n int64x2_t vcvtq_n_s64_f64(float64x2_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_U16_F16: // FCVTZU Vd.8H,Vn.8H,#n uint16x8_t vcvtq_n_u16_f16(float16x8_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_U32_F32: // FCVTZU Vd.4S,Vn.4S,#n uint32x4_t vcvtq_n_u32_f32(float32x4_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_N_U64_F64: // FCVTZU Vd.2D,Vn.2D,#n uint64x2_t vcvtq_n_u64_f64(float64x2_t a, const int n)
+ case ARM64_INTRIN_VCVTQ_S16_F16: // FCVTZS Vd.8H,Vn.8H int16x8_t vcvtq_s16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTQ_S32_F32: // FCVTZS Vd.4S,Vn.4S int32x4_t vcvtq_s32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTQ_S64_F64: // FCVTZS Vd.2D,Vn.2D int64x2_t vcvtq_s64_f64(float64x2_t a)
+ case ARM64_INTRIN_VCVTQ_U16_F16: // FCVTZS Vd.8H,Vn.8H uint16x8_t vcvtq_u16_f16(float16x8_t a)
+ case ARM64_INTRIN_VCVTQ_U32_F32: // FCVTZU Vd.4S,Vn.4S uint32x4_t vcvtq_u32_f32(float32x4_t a)
+ case ARM64_INTRIN_VCVTQ_U64_F64: // FCVTZU Vd.2D,Vn.2D uint64x2_t vcvtq_u64_f64(float64x2_t a)
+ case ARM64_INTRIN_VDOTQ_LANE_S32: // SDOT Vd.4S,Vn.16B,Vm.4B[lane] int32x4_t vdotq_lane_s32(int32x4_t r, int8x16_t a, int8x8_t b, const int lane)
+ case ARM64_INTRIN_VDOTQ_LANE_U32: // UDOT Vd.4S,Vn.16B,Vm.4B[lane] uint32x4_t vdotq_lane_u32(uint32x4_t r, uint8x16_t a, uint8x8_t b, const int lane)
+ case ARM64_INTRIN_VDOTQ_LANEQ_S32: // SDOT Vd.4S,Vn.16B,Vm.4B[lane] int32x4_t vdotq_laneq_s32(int32x4_t r, int8x16_t a, int8x16_t b, const int lane)
+ case ARM64_INTRIN_VDOTQ_LANEQ_U32: // UDOT Vd.4S,Vn.16B,Vm.4B[lane] uint32x4_t vdotq_laneq_u32(uint32x4_t r, uint8x16_t a, uint8x16_t b, const int lane)
+ case ARM64_INTRIN_VDOTQ_S32: // SDOT Vd.4S,Vn.16B,Vm.16B int32x4_t vdotq_s32(int32x4_t r, int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VDOTQ_U32: // UDOT Vd.4S,Vn.16B,Vm.16B uint32x4_t vdotq_u32(uint32x4_t r, uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VDUPQ_LANE_P16: // DUP Vd.8H,Vn.H[lane] poly16x8_t vdupq_lane_p16(poly16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_P64: // DUP Vd.2D,Vn.D[lane] poly64x2_t vdupq_lane_p64(poly64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_P8: // DUP Vd.16B,Vn.B[lane] poly8x16_t vdupq_lane_p8(poly8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_S16: // DUP Vd.8H,Vn.H[lane] int16x8_t vdupq_lane_s16(int16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_S32: // DUP Vd.4S,Vn.S[lane] int32x4_t vdupq_lane_s32(int32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_S64: // DUP Vd.2D,Vn.D[lane] int64x2_t vdupq_lane_s64(int64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_S8: // DUP Vd.16B,Vn.B[lane] int8x16_t vdupq_lane_s8(int8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_U16: // DUP Vd.8H,Vn.H[lane] uint16x8_t vdupq_lane_u16(uint16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_U32: // DUP Vd.4S,Vn.S[lane] uint32x4_t vdupq_lane_u32(uint32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_U64: // DUP Vd.2D,Vn.D[lane] uint64x2_t vdupq_lane_u64(uint64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANE_U8: // DUP Vd.16B,Vn.B[lane] uint8x16_t vdupq_lane_u8(uint8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_P16: // DUP Vd.8H,Vn.H[lane] poly16x8_t vdupq_laneq_p16(poly16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_P64: // DUP Vd.2D,Vn.D[lane] poly64x2_t vdupq_laneq_p64(poly64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_P8: // DUP Vd.16B,Vn.B[lane] poly8x16_t vdupq_laneq_p8(poly8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_S16: // DUP Vd.8H,Vn.H[lane] int16x8_t vdupq_laneq_s16(int16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_S32: // DUP Vd.4S,Vn.S[lane] int32x4_t vdupq_laneq_s32(int32x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_S64: // DUP Vd.2D,Vn.D[lane] int64x2_t vdupq_laneq_s64(int64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_S8: // DUP Vd.16B,Vn.B[lane] int8x16_t vdupq_laneq_s8(int8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_U16: // DUP Vd.8H,Vn.H[lane] uint16x8_t vdupq_laneq_u16(uint16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_U32: // DUP Vd.4S,Vn.S[lane] uint32x4_t vdupq_laneq_u32(uint32x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_U64: // DUP Vd.2D,Vn.D[lane] uint64x2_t vdupq_laneq_u64(uint64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_LANEQ_U8: // DUP Vd.16B,Vn.B[lane] uint8x16_t vdupq_laneq_u8(uint8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUPQ_N_P16: // DUP Vd.8H,rn poly16x8_t vdupq_n_p16(poly16_t value)
+ case ARM64_INTRIN_VDUPQ_N_P64: // DUP Vd.2D,rn poly64x2_t vdupq_n_p64(poly64_t value)
+ case ARM64_INTRIN_VDUPQ_N_P8: // DUP Vd.16B,rn poly8x16_t vdupq_n_p8(poly8_t value)
+ case ARM64_INTRIN_VDUPQ_N_S16: // DUP Vd.8H,rn int16x8_t vdupq_n_s16(int16_t value)
+ case ARM64_INTRIN_VDUPQ_N_S32: // DUP Vd.4S,rn int32x4_t vdupq_n_s32(int32_t value)
+ case ARM64_INTRIN_VDUPQ_N_S64: // DUP Vd.2D,rn int64x2_t vdupq_n_s64(int64_t value)
+ case ARM64_INTRIN_VDUPQ_N_S8: // DUP Vd.16B,rn int8x16_t vdupq_n_s8(int8_t value)
+ case ARM64_INTRIN_VDUPQ_N_U16: // DUP Vd.8H,rn uint16x8_t vdupq_n_u16(uint16_t value)
+ case ARM64_INTRIN_VDUPQ_N_U32: // DUP Vd.4S,rn uint32x4_t vdupq_n_u32(uint32_t value)
+ case ARM64_INTRIN_VDUPQ_N_U64: // DUP Vd.2D,rn uint64x2_t vdupq_n_u64(uint64_t value)
+ case ARM64_INTRIN_VDUPQ_N_U8: // DUP Vd.16B,rn uint8x16_t vdupq_n_u8(uint8_t value)
+ case ARM64_INTRIN_VEOR3Q_S16: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B int16x8_t veor3q_s16(int16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VEOR3Q_S32: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B int32x4_t veor3q_s32(int32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VEOR3Q_S64: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B int64x2_t veor3q_s64(int64x2_t a, int64x2_t b, int64x2_t c)
+ case ARM64_INTRIN_VEOR3Q_S8: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B int8x16_t veor3q_s8(int8x16_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VEOR3Q_U16: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B uint16x8_t veor3q_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VEOR3Q_U32: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B uint32x4_t veor3q_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VEOR3Q_U64: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B uint64x2_t veor3q_u64(uint64x2_t a, uint64x2_t b, uint64x2_t c)
+ case ARM64_INTRIN_VEOR3Q_U8: // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B uint8x16_t veor3q_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VEORQ_S16: // EOR Vd.16B,Vn.16B,Vm.16B int16x8_t veorq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VEORQ_S32: // EOR Vd.16B,Vn.16B,Vm.16B int32x4_t veorq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VEORQ_S64: // EOR Vd.16B,Vn.16B,Vm.16B int64x2_t veorq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VEORQ_S8: // EOR Vd.16B,Vn.16B,Vm.16B int8x16_t veorq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VEORQ_U16: // EOR Vd.16B,Vn.16B,Vm.16B uint16x8_t veorq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VEORQ_U32: // EOR Vd.16B,Vn.16B,Vm.16B uint32x4_t veorq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VEORQ_U64: // EOR Vd.16B,Vn.16B,Vm.16B uint64x2_t veorq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VEORQ_U8: // EOR Vd.16B,Vn.16B,Vm.16B uint8x16_t veorq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VEXTQ_P16: // EXT Vd.16B,Vn.16B,Vm.16B,#n poly16x8_t vextq_p16(poly16x8_t a, poly16x8_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_P64: // EXT Vd.16B,Vn.16B,Vm.16B,#n poly64x2_t vextq_p64(poly64x2_t a, poly64x2_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_P8: // EXT Vd.16B,Vn.16B,Vm.16B,#n poly8x16_t vextq_p8(poly8x16_t a, poly8x16_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_S16: // EXT Vd.16B,Vn.16B,Vm.16B,#n int16x8_t vextq_s16(int16x8_t a, int16x8_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_S32: // EXT Vd.16B,Vn.16B,Vm.16B,#n int32x4_t vextq_s32(int32x4_t a, int32x4_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_S64: // EXT Vd.16B,Vn.16B,Vm.16B,#n int64x2_t vextq_s64(int64x2_t a, int64x2_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_S8: // EXT Vd.16B,Vn.16B,Vm.16B,#n int8x16_t vextq_s8(int8x16_t a, int8x16_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_U16: // EXT Vd.16B,Vn.16B,Vm.16B,#n uint16x8_t vextq_u16(uint16x8_t a, uint16x8_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_U32: // EXT Vd.16B,Vn.16B,Vm.16B,#n uint32x4_t vextq_u32(uint32x4_t a, uint32x4_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_U64: // EXT Vd.16B,Vn.16B,Vm.16B,#n uint64x2_t vextq_u64(uint64x2_t a, uint64x2_t b, const int n)
+ case ARM64_INTRIN_VEXTQ_U8: // EXT Vd.16B,Vn.16B,Vm.16B,#n uint8x16_t vextq_u8(uint8x16_t a, uint8x16_t b, const int n)
+ case ARM64_INTRIN_VHADDQ_S16: // SHADD Vd.8H,Vn.8H,Vm.8H int16x8_t vhaddq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VHADDQ_S32: // SHADD Vd.4S,Vn.4S,Vm.4S int32x4_t vhaddq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VHADDQ_S8: // SHADD Vd.16B,Vn.16B,Vm.16B int8x16_t vhaddq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VHADDQ_U16: // UHADD Vd.8H,Vn.8H,Vm.8H uint16x8_t vhaddq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VHADDQ_U32: // UHADD Vd.4S,Vn.4S,Vm.4S uint32x4_t vhaddq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VHADDQ_U8: // UHADD Vd.16B,Vn.16B,Vm.16B uint8x16_t vhaddq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VHSUBQ_S16: // SHSUB Vd.8H,Vn.8H,Vm.8H int16x8_t vhsubq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VHSUBQ_S32: // SHSUB Vd.4S,Vn.4S,Vm.4S int32x4_t vhsubq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VHSUBQ_S8: // SHSUB Vd.16B,Vn.16B,Vm.16B int8x16_t vhsubq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VHSUBQ_U16: // UHSUB Vd.8H,Vn.8H,Vm.8H uint16x8_t vhsubq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VHSUBQ_U32: // UHSUB Vd.4S,Vn.4S,Vm.4S uint32x4_t vhsubq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VHSUBQ_U8: // UHSUB Vd.16B,Vn.16B,Vm.16B uint8x16_t vhsubq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VLDRQ_P128: // LDR Qd,[Xn] poly128_t vldrq_p128(poly128_t const * ptr)
+ case ARM64_INTRIN_VMAXQ_S16: // SMAX Vd.8H,Vn.8H,Vm.8H int16x8_t vmaxq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VMAXQ_S32: // SMAX Vd.4S,Vn.4S,Vm.4S int32x4_t vmaxq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VMAXQ_S8: // SMAX Vd.16B,Vn.16B,Vm.16B int8x16_t vmaxq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VMAXQ_U16: // UMAX Vd.8H,Vn.8H,Vm.8H uint16x8_t vmaxq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VMAXQ_U32: // UMAX Vd.4S,Vn.4S,Vm.4S uint32x4_t vmaxq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VMAXQ_U8: // UMAX Vd.16B,Vn.16B,Vm.16B uint8x16_t vmaxq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VMINQ_S16: // SMIN Vd.8H,Vn.8H,Vm.8H int16x8_t vminq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VMINQ_S32: // SMIN Vd.4S,Vn.4S,Vm.4S int32x4_t vminq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VMINQ_S8: // SMIN Vd.16B,Vn.16B,Vm.16B int8x16_t vminq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VMINQ_U16: // UMIN Vd.8H,Vn.8H,Vm.8H uint16x8_t vminq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VMINQ_U32: // UMIN Vd.4S,Vn.4S,Vm.4S uint32x4_t vminq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VMINQ_U8: // UMIN Vd.16B,Vn.16B,Vm.16B uint8x16_t vminq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VMLAL_HIGH_LANE_S16: // SMLAL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vmlal_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_LANE_S32: // SMLAL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vmlal_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_LANE_U16: // UMLAL2 Vd.4S,Vn.8H,Vm.H[lane] uint32x4_t vmlal_high_lane_u16(uint32x4_t a, uint16x8_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_LANE_U32: // UMLAL2 Vd.2D,Vn.4S,Vm.S[lane] uint64x2_t vmlal_high_lane_u32(uint64x2_t a, uint32x4_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_LANEQ_S16: // SMLAL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vmlal_high_laneq_s16(int32x4_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_LANEQ_S32: // SMLAL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vmlal_high_laneq_s32(int64x2_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_LANEQ_U16: // UMLAL2 Vd.4S,Vn.8H,Vm.H[lane] uint32x4_t vmlal_high_laneq_u16(uint32x4_t a, uint16x8_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_LANEQ_U32: // UMLAL2 Vd.2D,Vn.4S,Vm.S[lane] uint64x2_t vmlal_high_laneq_u32(uint64x2_t a, uint32x4_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_HIGH_N_S16: // SMLAL2 Vd.4S,Vn.8H,Vm.H[0] int32x4_t vmlal_high_n_s16(int32x4_t a, int16x8_t b, int16_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_N_S32: // SMLAL2 Vd.2D,Vn.4S,Vm.S[0] int64x2_t vmlal_high_n_s32(int64x2_t a, int32x4_t b, int32_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_N_U16: // UMLAL2 Vd.4S,Vn.8H,Vm.H[0] uint32x4_t vmlal_high_n_u16(uint32x4_t a, uint16x8_t b, uint16_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_N_U32: // UMLAL2 Vd.2D,Vn.4S,Vm.S[0] uint64x2_t vmlal_high_n_u32(uint64x2_t a, uint32x4_t b, uint32_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_S16: // SMLAL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vmlal_high_s16(int32x4_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_S32: // SMLAL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vmlal_high_s32(int64x2_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_S8: // SMLAL2 Vd.8H,Vn.16B,Vm.16B int16x8_t vmlal_high_s8(int16x8_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_U16: // UMLAL2 Vd.4S,Vn.8H,Vm.8H uint32x4_t vmlal_high_u16(uint32x4_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_U32: // UMLAL2 Vd.2D,Vn.4S,Vm.4S uint64x2_t vmlal_high_u32(uint64x2_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VMLAL_HIGH_U8: // UMLAL2 Vd.8H,Vn.16B,Vm.16B uint16x8_t vmlal_high_u8(uint16x8_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VMLAL_LANE_S16: // SMLAL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vmlal_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_LANE_S32: // SMLAL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vmlal_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_LANE_U16: // UMLAL Vd.4S,Vn.4H,Vm.H[lane] uint32x4_t vmlal_lane_u16(uint32x4_t a, uint16x4_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_LANE_U32: // UMLAL Vd.2D,Vn.2S,Vm.S[lane] uint64x2_t vmlal_lane_u32(uint64x2_t a, uint32x2_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_LANEQ_S16: // SMLAL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vmlal_laneq_s16(int32x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_LANEQ_S32: // SMLAL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vmlal_laneq_s32(int64x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_LANEQ_U16: // UMLAL Vd.4S,Vn.4H,Vm.H[lane] uint32x4_t vmlal_laneq_u16(uint32x4_t a, uint16x4_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_LANEQ_U32: // UMLAL Vd.2D,Vn.2S,Vm.S[lane] uint64x2_t vmlal_laneq_u32(uint64x2_t a, uint32x2_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAL_N_S16: // SMLAL Vd.4S,Vn.4H,Vm.H[0] int32x4_t vmlal_n_s16(int32x4_t a, int16x4_t b, int16_t c)
+ case ARM64_INTRIN_VMLAL_N_S32: // SMLAL Vd.2D,Vn.2S,Vm.S[0] int64x2_t vmlal_n_s32(int64x2_t a, int32x2_t b, int32_t c)
+ case ARM64_INTRIN_VMLAL_N_U16: // UMLAL Vd.4S,Vn.4H,Vm.H[0] uint32x4_t vmlal_n_u16(uint32x4_t a, uint16x4_t b, uint16_t c)
+ case ARM64_INTRIN_VMLAL_N_U32: // UMLAL Vd.2D,Vn.2S,Vm.S[0] uint64x2_t vmlal_n_u32(uint64x2_t a, uint32x2_t b, uint32_t c)
+ case ARM64_INTRIN_VMLAL_S16: // SMLAL Vd.4S,Vn.4H,Vm.4H int32x4_t vmlal_s16(int32x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VMLAL_S32: // SMLAL Vd.2D,Vn.2S,Vm.2S int64x2_t vmlal_s32(int64x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VMLAL_S8: // SMLAL Vd.8H,Vn.8B,Vm.8B int16x8_t vmlal_s8(int16x8_t a, int8x8_t b, int8x8_t c)
+ case ARM64_INTRIN_VMLAL_U16: // UMLAL Vd.4S,Vn.4H,Vm.4H uint32x4_t vmlal_u16(uint32x4_t a, uint16x4_t b, uint16x4_t c)
+ case ARM64_INTRIN_VMLAL_U32: // UMLAL Vd.2D,Vn.2S,Vm.2S uint64x2_t vmlal_u32(uint64x2_t a, uint32x2_t b, uint32x2_t c)
+ case ARM64_INTRIN_VMLAL_U8: // UMLAL Vd.8H,Vn.8B,Vm.8B uint16x8_t vmlal_u8(uint16x8_t a, uint8x8_t b, uint8x8_t c)
+ case ARM64_INTRIN_VMLAQ_LANE_S16: // MLA Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vmlaq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_LANE_S32: // MLA Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vmlaq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_LANE_U16: // MLA Vd.8H,Vn.8H,Vm.H[lane] uint16x8_t vmlaq_lane_u16(uint16x8_t a, uint16x8_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_LANE_U32: // MLA Vd.4S,Vn.4S,Vm.S[lane] uint32x4_t vmlaq_lane_u32(uint32x4_t a, uint32x4_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_LANEQ_S16: // MLA Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vmlaq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_LANEQ_S32: // MLA Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vmlaq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_LANEQ_U16: // MLA Vd.8H,Vn.8H,Vm.H[lane] uint16x8_t vmlaq_laneq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_LANEQ_U32: // MLA Vd.4S,Vn.4S,Vm.S[lane] uint32x4_t vmlaq_laneq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLAQ_N_S16: // MLA Vd.8H,Vn.8H,Vm.H[0] int16x8_t vmlaq_n_s16(int16x8_t a, int16x8_t b, int16_t c)
+ case ARM64_INTRIN_VMLAQ_N_S32: // MLA Vd.4S,Vn.4S,Vm.S[0] int32x4_t vmlaq_n_s32(int32x4_t a, int32x4_t b, int32_t c)
+ case ARM64_INTRIN_VMLAQ_N_U16: // MLA Vd.8H,Vn.8H,Vm.H[0] uint16x8_t vmlaq_n_u16(uint16x8_t a, uint16x8_t b, uint16_t c)
+ case ARM64_INTRIN_VMLAQ_N_U32: // MLA Vd.4S,Vn.4S,Vm.S[0] uint32x4_t vmlaq_n_u32(uint32x4_t a, uint32x4_t b, uint32_t c)
+ case ARM64_INTRIN_VMLAQ_S16: // MLA Vd.8H,Vn.8H,Vm.8H int16x8_t vmlaq_s16(int16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VMLAQ_S32: // MLA Vd.4S,Vn.4S,Vm.4S int32x4_t vmlaq_s32(int32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VMLAQ_S8: // MLA Vd.16B,Vn.16B,Vm.16B int8x16_t vmlaq_s8(int8x16_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VMLAQ_U16: // MLA Vd.8H,Vn.8H,Vm.8H uint16x8_t vmlaq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VMLAQ_U32: // MLA Vd.4S,Vn.4S,Vm.4S uint32x4_t vmlaq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VMLAQ_U8: // MLA Vd.16B,Vn.16B,Vm.16B uint8x16_t vmlaq_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_LANE_S16: // SMLSL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vmlsl_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_LANE_S32: // SMLSL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vmlsl_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_LANE_U16: // UMLSL2 Vd.4S,Vn.8H,Vm.H[lane] uint32x4_t vmlsl_high_lane_u16(uint32x4_t a, uint16x8_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_LANE_U32: // UMLSL2 Vd.2D,Vn.4S,Vm.S[lane] uint64x2_t vmlsl_high_lane_u32(uint64x2_t a, uint32x4_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_LANEQ_S16: // SMLSL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vmlsl_high_laneq_s16(int32x4_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_LANEQ_S32: // SMLSL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vmlsl_high_laneq_s32(int64x2_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_LANEQ_U16: // UMLSL2 Vd.4S,Vn.8H,Vm.H[lane] uint32x4_t vmlsl_high_laneq_u16(uint32x4_t a, uint16x8_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_LANEQ_U32: // UMLSL2 Vd.2D,Vn.4S,Vm.S[lane] uint64x2_t vmlsl_high_laneq_u32(uint64x2_t a, uint32x4_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_HIGH_N_S16: // SMLSL2 Vd.4S,Vn.8H,Vm.H[0] int32x4_t vmlsl_high_n_s16(int32x4_t a, int16x8_t b, int16_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_N_S32: // SMLSL2 Vd.2D,Vn.4S,Vm.S[0] int64x2_t vmlsl_high_n_s32(int64x2_t a, int32x4_t b, int32_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_N_U16: // UMLSL2 Vd.4S,Vn.8H,Vm.H[0] uint32x4_t vmlsl_high_n_u16(uint32x4_t a, uint16x8_t b, uint16_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_N_U32: // UMLSL2 Vd.2D,Vn.4S,Vm.S[0] uint64x2_t vmlsl_high_n_u32(uint64x2_t a, uint32x4_t b, uint32_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_S16: // SMLSL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vmlsl_high_s16(int32x4_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_S32: // SMLSL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vmlsl_high_s32(int64x2_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_S8: // SMLSL2 Vd.8H,Vn.16B,Vm.16B int16x8_t vmlsl_high_s8(int16x8_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_U16: // UMLSL2 Vd.4S,Vn.8H,Vm.8H uint32x4_t vmlsl_high_u16(uint32x4_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_U32: // UMLSL2 Vd.2D,Vn.4S,Vm.4S uint64x2_t vmlsl_high_u32(uint64x2_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VMLSL_HIGH_U8: // UMLSL2 Vd.8H,Vn.16B,Vm.16B uint16x8_t vmlsl_high_u8(uint16x8_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VMLSL_LANE_S16: // SMLSL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vmlsl_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_LANE_S32: // SMLSL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vmlsl_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_LANE_U16: // UMLSL Vd.4S,Vn.4H,Vm.H[lane] uint32x4_t vmlsl_lane_u16(uint32x4_t a, uint16x4_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_LANE_U32: // UMLSL Vd.2D,Vn.2S,Vm.S[lane] uint64x2_t vmlsl_lane_u32(uint64x2_t a, uint32x2_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_LANEQ_S16: // SMLSL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vmlsl_laneq_s16(int32x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_LANEQ_S32: // SMLSL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vmlsl_laneq_s32(int64x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_LANEQ_U16: // UMLSL Vd.4S,Vn.4H,Vm.H[lane] uint32x4_t vmlsl_laneq_u16(uint32x4_t a, uint16x4_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_LANEQ_U32: // UMLSL Vd.2D,Vn.2S,Vm.S[lane] uint64x2_t vmlsl_laneq_u32(uint64x2_t a, uint32x2_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSL_N_S16: // SMLSL Vd.4S,Vn.4H,Vm.H[0] int32x4_t vmlsl_n_s16(int32x4_t a, int16x4_t b, int16_t c)
+ case ARM64_INTRIN_VMLSL_N_S32: // SMLSL Vd.2D,Vn.2S,Vm.S[0] int64x2_t vmlsl_n_s32(int64x2_t a, int32x2_t b, int32_t c)
+ case ARM64_INTRIN_VMLSL_N_U16: // UMLSL Vd.4S,Vn.4H,Vm.H[0] uint32x4_t vmlsl_n_u16(uint32x4_t a, uint16x4_t b, uint16_t c)
+ case ARM64_INTRIN_VMLSL_N_U32: // UMLSL Vd.2D,Vn.2S,Vm.S[0] uint64x2_t vmlsl_n_u32(uint64x2_t a, uint32x2_t b, uint32_t c)
+ case ARM64_INTRIN_VMLSL_S16: // SMLSL Vd.4S,Vn.4H,Vm.4H int32x4_t vmlsl_s16(int32x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VMLSL_S32: // SMLSL Vd.2D,Vn.2S,Vm.2S int64x2_t vmlsl_s32(int64x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VMLSL_S8: // SMLSL Vd.8H,Vn.8B,Vm.8B int16x8_t vmlsl_s8(int16x8_t a, int8x8_t b, int8x8_t c)
+ case ARM64_INTRIN_VMLSL_U16: // UMLSL Vd.4S,Vn.4H,Vm.4H uint32x4_t vmlsl_u16(uint32x4_t a, uint16x4_t b, uint16x4_t c)
+ case ARM64_INTRIN_VMLSL_U32: // UMLSL Vd.2D,Vn.2S,Vm.2S uint64x2_t vmlsl_u32(uint64x2_t a, uint32x2_t b, uint32x2_t c)
+ case ARM64_INTRIN_VMLSL_U8: // UMLSL Vd.8H,Vn.8B,Vm.8B uint16x8_t vmlsl_u8(uint16x8_t a, uint8x8_t b, uint8x8_t c)
+ case ARM64_INTRIN_VMLSQ_LANE_S16: // MLS Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vmlsq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_LANE_S32: // MLS Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vmlsq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_LANE_U16: // MLS Vd.8H,Vn.8H,Vm.H[lane] uint16x8_t vmlsq_lane_u16(uint16x8_t a, uint16x8_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_LANE_U32: // MLS Vd.4S,Vn.4S,Vm.S[lane] uint32x4_t vmlsq_lane_u32(uint32x4_t a, uint32x4_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_LANEQ_S16: // MLS Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vmlsq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_LANEQ_S32: // MLS Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vmlsq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_LANEQ_U16: // MLS Vd.8H,Vn.8H,Vm.H[lane] uint16x8_t vmlsq_laneq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_LANEQ_U32: // MLS Vd.4S,Vn.4S,Vm.S[lane] uint32x4_t vmlsq_laneq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLSQ_N_S16: // MLS Vd.8H,Vn.8H,Vm.H[0] int16x8_t vmlsq_n_s16(int16x8_t a, int16x8_t b, int16_t c)
+ case ARM64_INTRIN_VMLSQ_N_S32: // MLS Vd.4S,Vn.4S,Vm.S[0] int32x4_t vmlsq_n_s32(int32x4_t a, int32x4_t b, int32_t c)
+ case ARM64_INTRIN_VMLSQ_N_U16: // MLS Vd.8H,Vn.8H,Vm.H[0] uint16x8_t vmlsq_n_u16(uint16x8_t a, uint16x8_t b, uint16_t c)
+ case ARM64_INTRIN_VMLSQ_N_U32: // MLS Vd.4S,Vn.4S,Vm.S[0] uint32x4_t vmlsq_n_u32(uint32x4_t a, uint32x4_t b, uint32_t c)
+ case ARM64_INTRIN_VMLSQ_S16: // MLS Vd.8H,Vn.8H,Vm.8H int16x8_t vmlsq_s16(int16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VMLSQ_S32: // MLS Vd.4S,Vn.4S,Vm.4S int32x4_t vmlsq_s32(int32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VMLSQ_S8: // MLS Vd.16B,Vn.16B,Vm.16B int8x16_t vmlsq_s8(int8x16_t a, int8x16_t b, int8x16_t c)
+ case ARM64_INTRIN_VMLSQ_U16: // MLS Vd.8H,Vn.8H,Vm.8H uint16x8_t vmlsq_u16(uint16x8_t a, uint16x8_t b, uint16x8_t c)
+ case ARM64_INTRIN_VMLSQ_U32: // MLS Vd.4S,Vn.4S,Vm.4S uint32x4_t vmlsq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VMLSQ_U8: // MLS Vd.16B,Vn.16B,Vm.16B uint8x16_t vmlsq_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c)
+ case ARM64_INTRIN_VMMLAQ_S32: // SMMLA Vd.4S,Vn.16B,Vm.16B int32x4_t vmmlaq_s32(int32x4_t r, int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VMMLAQ_U32: // UMMLA Vd.4S,Vn.16B,Vm.16B uint32x4_t vmmlaq_u32(uint32x4_t r, uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VMOVL_HIGH_S16: // SSHLL2 Vd.4S,Vn.8H,#0 int32x4_t vmovl_high_s16(int16x8_t a)
+ case ARM64_INTRIN_VMOVL_HIGH_S32: // SSHLL2 Vd.2D,Vn.4S,#0 int64x2_t vmovl_high_s32(int32x4_t a)
+ case ARM64_INTRIN_VMOVL_HIGH_S8: // SSHLL2 Vd.8H,Vn.16B,#0 int16x8_t vmovl_high_s8(int8x16_t a)
+ case ARM64_INTRIN_VMOVL_HIGH_U16: // USHLL2 Vd.4S,Vn.8H,#0 uint32x4_t vmovl_high_u16(uint16x8_t a)
+ case ARM64_INTRIN_VMOVL_HIGH_U32: // USHLL2 Vd.2D,Vn.4S,#0 uint64x2_t vmovl_high_u32(uint32x4_t a)
+ case ARM64_INTRIN_VMOVL_HIGH_U8: // USHLL2 Vd.8H,Vn.16B,#0 uint16x8_t vmovl_high_u8(uint8x16_t a)
+ case ARM64_INTRIN_VMOVL_S16: // SSHLL Vd.4S,Vn.4H,#0 int32x4_t vmovl_s16(int16x4_t a)
+ case ARM64_INTRIN_VMOVL_S32: // SSHLL Vd.2D,Vn.2S,#0 int64x2_t vmovl_s32(int32x2_t a)
+ case ARM64_INTRIN_VMOVL_S8: // SSHLL Vd.8H,Vn.8B,#0 int16x8_t vmovl_s8(int8x8_t a)
+ case ARM64_INTRIN_VMOVL_U16: // USHLL Vd.4S,Vn.4H,#0 uint32x4_t vmovl_u16(uint16x4_t a)
+ case ARM64_INTRIN_VMOVL_U32: // USHLL Vd.2D,Vn.2S,#0 uint64x2_t vmovl_u32(uint32x2_t a)
+ case ARM64_INTRIN_VMOVL_U8: // USHLL Vd.8H,Vn.8B,#0 uint16x8_t vmovl_u8(uint8x8_t a)
+ case ARM64_INTRIN_VMOVN_HIGH_S16: // XTN2 Vd.16B,Vn.8H int8x16_t vmovn_high_s16(int8x8_t r, int16x8_t a)
+ case ARM64_INTRIN_VMOVN_HIGH_S32: // XTN2 Vd.8H,Vn.4S int16x8_t vmovn_high_s32(int16x4_t r, int32x4_t a)
+ case ARM64_INTRIN_VMOVN_HIGH_S64: // XTN2 Vd.4S,Vn.2D int32x4_t vmovn_high_s64(int32x2_t r, int64x2_t a)
+ case ARM64_INTRIN_VMOVN_HIGH_U16: // XTN2 Vd.16B,Vn.8H uint8x16_t vmovn_high_u16(uint8x8_t r, uint16x8_t a)
+ case ARM64_INTRIN_VMOVN_HIGH_U32: // XTN2 Vd.8H,Vn.4S uint16x8_t vmovn_high_u32(uint16x4_t r, uint32x4_t a)
+ case ARM64_INTRIN_VMOVN_HIGH_U64: // XTN2 Vd.4S,Vn.2D uint32x4_t vmovn_high_u64(uint32x2_t r, uint64x2_t a)
+ case ARM64_INTRIN_VMOVQ_N_P16: // DUP Vd.8H,rn poly16x8_t vmovq_n_p16(poly16_t value)
+ case ARM64_INTRIN_VMOVQ_N_P8: // DUP Vd.16B,rn poly8x16_t vmovq_n_p8(poly8_t value)
+ case ARM64_INTRIN_VMOVQ_N_S16: // DUP Vd.8H,rn int16x8_t vmovq_n_s16(int16_t value)
+ case ARM64_INTRIN_VMOVQ_N_S32: // DUP Vd.4S,rn int32x4_t vmovq_n_s32(int32_t value)
+ case ARM64_INTRIN_VMOVQ_N_S64: // DUP Vd.2D,rn int64x2_t vmovq_n_s64(int64_t value)
+ case ARM64_INTRIN_VMOVQ_N_S8: // DUP Vd.16B,rn int8x16_t vmovq_n_s8(int8_t value)
+ case ARM64_INTRIN_VMOVQ_N_U16: // DUP Vd.8H,rn uint16x8_t vmovq_n_u16(uint16_t value)
+ case ARM64_INTRIN_VMOVQ_N_U32: // DUP Vd.4S,rn uint32x4_t vmovq_n_u32(uint32_t value)
+ case ARM64_INTRIN_VMOVQ_N_U64: // DUP Vd.2D,rn uint64x2_t vmovq_n_u64(uint64_t value)
+ case ARM64_INTRIN_VMOVQ_N_U8: // DUP Vd.16B,rn uint8x16_t vmovq_n_u8(uint8_t value)
+ case ARM64_INTRIN_VMULL_HIGH_LANE_S16: // SMULL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vmull_high_lane_s16(int16x8_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULL_HIGH_LANE_S32: // SMULL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vmull_high_lane_s32(int32x4_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULL_HIGH_LANE_U16: // UMULL2 Vd.4S,Vn.8H,Vm.H[lane] uint32x4_t vmull_high_lane_u16(uint16x8_t a, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULL_HIGH_LANE_U32: // UMULL2 Vd.2D,Vn.4S,Vm.S[lane] uint64x2_t vmull_high_lane_u32(uint32x4_t a, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULL_HIGH_LANEQ_S16: // SMULL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vmull_high_laneq_s16(int16x8_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULL_HIGH_LANEQ_S32: // SMULL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vmull_high_laneq_s32(int32x4_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULL_HIGH_LANEQ_U16: // UMULL2 Vd.4S,Vn.8H,Vm.H[lane] uint32x4_t vmull_high_laneq_u16(uint16x8_t a, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULL_HIGH_LANEQ_U32: // UMULL2 Vd.2D,Vn.4S,Vm.S[lane] uint64x2_t vmull_high_laneq_u32(uint32x4_t a, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULL_HIGH_N_S16: // SMULL2 Vd.4S,Vn.8H,Vm.H[0] int32x4_t vmull_high_n_s16(int16x8_t a, int16_t b)
+ case ARM64_INTRIN_VMULL_HIGH_N_S32: // SMULL2 Vd.2D,Vn.4S,Vm.S[0] int64x2_t vmull_high_n_s32(int32x4_t a, int32_t b)
+ case ARM64_INTRIN_VMULL_HIGH_N_U16: // UMULL2 Vd.4S,Vn.8H,Vm.H[0] uint32x4_t vmull_high_n_u16(uint16x8_t a, uint16_t b)
+ case ARM64_INTRIN_VMULL_HIGH_N_U32: // UMULL2 Vd.2D,Vn.4S,Vm.S[0] uint64x2_t vmull_high_n_u32(uint32x4_t a, uint32_t b)
+ case ARM64_INTRIN_VMULL_HIGH_P64: // PMULL2 Vd.1Q,Vn.2D,Vm.2D poly128_t vmull_high_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VMULL_HIGH_P8: // PMULL2 Vd.8H,Vn.16B,Vm.16B poly16x8_t vmull_high_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VMULL_HIGH_S16: // SMULL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vmull_high_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VMULL_HIGH_S32: // SMULL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vmull_high_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VMULL_HIGH_S8: // SMULL2 Vd.8H,Vn.16B,Vm.16B int16x8_t vmull_high_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VMULL_HIGH_U16: // UMULL2 Vd.4S,Vn.8H,Vm.8H uint32x4_t vmull_high_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VMULL_HIGH_U32: // UMULL2 Vd.2D,Vn.4S,Vm.4S uint64x2_t vmull_high_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VMULL_HIGH_U8: // UMULL2 Vd.8H,Vn.16B,Vm.16B uint16x8_t vmull_high_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VMULL_LANE_S16: // SMULL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vmull_lane_s16(int16x4_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULL_LANE_S32: // SMULL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vmull_lane_s32(int32x2_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULL_LANE_U16: // UMULL Vd.4S,Vn.4H,Vm.H[lane] uint32x4_t vmull_lane_u16(uint16x4_t a, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULL_LANE_U32: // UMULL Vd.2D,Vn.2S,Vm.S[lane] uint64x2_t vmull_lane_u32(uint32x2_t a, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULL_LANEQ_S16: // SMULL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vmull_laneq_s16(int16x4_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULL_LANEQ_S32: // SMULL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vmull_laneq_s32(int32x2_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULL_LANEQ_U16: // UMULL Vd.4S,Vn.4H,Vm.H[lane] uint32x4_t vmull_laneq_u16(uint16x4_t a, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULL_LANEQ_U32: // UMULL Vd.2D,Vn.2S,Vm.S[lane] uint64x2_t vmull_laneq_u32(uint32x2_t a, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULL_N_S16: // SMULL Vd.4S,Vn.4H,Vm.H[0] int32x4_t vmull_n_s16(int16x4_t a, int16_t b)
+ case ARM64_INTRIN_VMULL_N_S32: // SMULL Vd.2D,Vn.2S,Vm.S[0] int64x2_t vmull_n_s32(int32x2_t a, int32_t b)
+ case ARM64_INTRIN_VMULL_N_U16: // UMULL Vd.4S,Vn.4H,Vm.H[0] uint32x4_t vmull_n_u16(uint16x4_t a, uint16_t b)
+ case ARM64_INTRIN_VMULL_N_U32: // UMULL Vd.2D,Vn.2S,Vm.S[0] uint64x2_t vmull_n_u32(uint32x2_t a, uint32_t b)
+ case ARM64_INTRIN_VMULL_P64: // PMULL Vd.1Q,Vn.1D,Vm.1D poly128_t vmull_p64(poly64_t a, poly64_t b)
+ case ARM64_INTRIN_VMULL_P8: // PMULL Vd.8H,Vn.8B,Vm.8B poly16x8_t vmull_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VMULL_S16: // SMULL Vd.4S,Vn.4H,Vm.4H int32x4_t vmull_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VMULL_S32: // SMULL Vd.2D,Vn.2S,Vm.2S int64x2_t vmull_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VMULL_S8: // SMULL Vd.8H,Vn.8B,Vm.8B int16x8_t vmull_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VMULL_U16: // UMULL Vd.4S,Vn.4H,Vm.4H uint32x4_t vmull_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VMULL_U32: // UMULL Vd.2D,Vn.2S,Vm.2S uint64x2_t vmull_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VMULL_U8: // UMULL Vd.8H,Vn.8B,Vm.8B uint16x8_t vmull_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VMULQ_LANE_S16: // MUL Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vmulq_lane_s16(int16x8_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANE_S32: // MUL Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vmulq_lane_s32(int32x4_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANE_U16: // MUL Vd.8H,Vn.8H,Vm.H[lane] uint16x8_t vmulq_lane_u16(uint16x8_t a, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANE_U32: // MUL Vd.4S,Vn.4S,Vm.S[lane] uint32x4_t vmulq_lane_u32(uint32x4_t a, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANEQ_S16: // MUL Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vmulq_laneq_s16(int16x8_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANEQ_S32: // MUL Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vmulq_laneq_s32(int32x4_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANEQ_U16: // MUL Vd.8H,Vn.8H,Vm.H[lane] uint16x8_t vmulq_laneq_u16(uint16x8_t a, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_LANEQ_U32: // MUL Vd.4S,Vn.4S,Vm.S[lane] uint32x4_t vmulq_laneq_u32(uint32x4_t a, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMULQ_N_S16: // MUL Vd.8H,Vn.8H,Vm.H[0] int16x8_t vmulq_n_s16(int16x8_t a, int16_t b)
+ case ARM64_INTRIN_VMULQ_N_S32: // MUL Vd.4S,Vn.4S,Vm.S[0] int32x4_t vmulq_n_s32(int32x4_t a, int32_t b)
+ case ARM64_INTRIN_VMULQ_N_U16: // MUL Vd.8H,Vn.8H,Vm.H[0] uint16x8_t vmulq_n_u16(uint16x8_t a, uint16_t b)
+ case ARM64_INTRIN_VMULQ_N_U32: // MUL Vd.4S,Vn.4S,Vm.S[0] uint32x4_t vmulq_n_u32(uint32x4_t a, uint32_t b)
+ case ARM64_INTRIN_VMULQ_P8: // PMUL Vd.16B,Vn.16B,Vm.16B poly8x16_t vmulq_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VMULQ_S16: // MUL Vd.8H,Vn.8H,Vm.8H int16x8_t vmulq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VMULQ_S32: // MUL Vd.4S,Vn.4S,Vm.4S int32x4_t vmulq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VMULQ_S8: // MUL Vd.16B,Vn.16B,Vm.16B int8x16_t vmulq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VMULQ_U16: // MUL Vd.8H,Vn.8H,Vm.8H uint16x8_t vmulq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VMULQ_U32: // MUL Vd.4S,Vn.4S,Vm.4S uint32x4_t vmulq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VMULQ_U8: // MUL Vd.16B,Vn.16B,Vm.16B uint8x16_t vmulq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VMVNQ_P8: // MVN Vd.16B,Vn.16B poly8x16_t vmvnq_p8(poly8x16_t a)
+ case ARM64_INTRIN_VMVNQ_S16: // MVN Vd.16B,Vn.16B int16x8_t vmvnq_s16(int16x8_t a)
+ case ARM64_INTRIN_VMVNQ_S32: // MVN Vd.16B,Vn.16B int32x4_t vmvnq_s32(int32x4_t a)
+ case ARM64_INTRIN_VMVNQ_S8: // MVN Vd.16B,Vn.16B int8x16_t vmvnq_s8(int8x16_t a)
+ case ARM64_INTRIN_VMVNQ_U16: // MVN Vd.16B,Vn.16B uint16x8_t vmvnq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VMVNQ_U32: // MVN Vd.16B,Vn.16B uint32x4_t vmvnq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VMVNQ_U8: // MVN Vd.16B,Vn.16B uint8x16_t vmvnq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VNEGQ_S16: // NEG Vd.8H,Vn.8H int16x8_t vnegq_s16(int16x8_t a)
+ case ARM64_INTRIN_VNEGQ_S32: // NEG Vd.4S,Vn.4S int32x4_t vnegq_s32(int32x4_t a)
+ case ARM64_INTRIN_VNEGQ_S64: // NEG Vd.2D,Vn.2D int64x2_t vnegq_s64(int64x2_t a)
+ case ARM64_INTRIN_VNEGQ_S8: // NEG Vd.16B,Vn.16B int8x16_t vnegq_s8(int8x16_t a)
+ case ARM64_INTRIN_VORNQ_S16: // ORN Vd.16B,Vn.16B,Vm.16B int16x8_t vornq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VORNQ_S32: // ORN Vd.16B,Vn.16B,Vm.16B int32x4_t vornq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VORNQ_S64: // ORN Vd.16B,Vn.16B,Vm.16B int64x2_t vornq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VORNQ_S8: // ORN Vd.16B,Vn.16B,Vm.16B int8x16_t vornq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VORNQ_U16: // ORN Vd.16B,Vn.16B,Vm.16B uint16x8_t vornq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VORNQ_U32: // ORN Vd.16B,Vn.16B,Vm.16B uint32x4_t vornq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VORNQ_U64: // ORN Vd.16B,Vn.16B,Vm.16B uint64x2_t vornq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VORNQ_U8: // ORN Vd.16B,Vn.16B,Vm.16B uint8x16_t vornq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VORRQ_S16: // ORR Vd.16B,Vn.16B,Vm.16B int16x8_t vorrq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VORRQ_S32: // ORR Vd.16B,Vn.16B,Vm.16B int32x4_t vorrq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VORRQ_S64: // ORR Vd.16B,Vn.16B,Vm.16B int64x2_t vorrq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VORRQ_S8: // ORR Vd.16B,Vn.16B,Vm.16B int8x16_t vorrq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VORRQ_U16: // ORR Vd.16B,Vn.16B,Vm.16B uint16x8_t vorrq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VORRQ_U32: // ORR Vd.16B,Vn.16B,Vm.16B uint32x4_t vorrq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VORRQ_U64: // ORR Vd.16B,Vn.16B,Vm.16B uint64x2_t vorrq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VORRQ_U8: // ORR Vd.16B,Vn.16B,Vm.16B uint8x16_t vorrq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VPADALQ_S16: // SADALP Vd.4S,Vn.8H int32x4_t vpadalq_s16(int32x4_t a, int16x8_t b)
+ case ARM64_INTRIN_VPADALQ_S32: // SADALP Vd.2D,Vn.4S int64x2_t vpadalq_s32(int64x2_t a, int32x4_t b)
+ case ARM64_INTRIN_VPADALQ_S8: // SADALP Vd.8H,Vn.16B int16x8_t vpadalq_s8(int16x8_t a, int8x16_t b)
+ case ARM64_INTRIN_VPADALQ_U16: // UADALP Vd.4S,Vn.8H uint32x4_t vpadalq_u16(uint32x4_t a, uint16x8_t b)
+ case ARM64_INTRIN_VPADALQ_U32: // UADALP Vd.2D,Vn.4S uint64x2_t vpadalq_u32(uint64x2_t a, uint32x4_t b)
+ case ARM64_INTRIN_VPADALQ_U8: // UADALP Vd.8H,Vn.16B uint16x8_t vpadalq_u8(uint16x8_t a, uint8x16_t b)
+ case ARM64_INTRIN_VPADDLQ_S16: // SADDLP Vd.4S,Vn.8H int32x4_t vpaddlq_s16(int16x8_t a)
+ case ARM64_INTRIN_VPADDLQ_S32: // SADDLP Vd.2D,Vn.4S int64x2_t vpaddlq_s32(int32x4_t a)
+ case ARM64_INTRIN_VPADDLQ_S8: // SADDLP Vd.8H,Vn.16B int16x8_t vpaddlq_s8(int8x16_t a)
+ case ARM64_INTRIN_VPADDLQ_U16: // UADDLP Vd.4S,Vn.8H uint32x4_t vpaddlq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VPADDLQ_U32: // UADDLP Vd.2D,Vn.4S uint64x2_t vpaddlq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VPADDLQ_U8: // UADDLP Vd.8H,Vn.16B uint16x8_t vpaddlq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VPADDQ_S16: // ADDP Vd.8H,Vn.8H,Vm.8H int16x8_t vpaddq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VPADDQ_S32: // ADDP Vd.4S,Vn.4S,Vm.4S int32x4_t vpaddq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VPADDQ_S64: // ADDP Vd.2D,Vn.2D,Vm.2D int64x2_t vpaddq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VPADDQ_S8: // ADDP Vd.16B,Vn.16B,Vm.16B int8x16_t vpaddq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VPADDQ_U16: // ADDP Vd.8H,Vn.8H,Vm.8H uint16x8_t vpaddq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VPADDQ_U32: // ADDP Vd.4S,Vn.4S,Vm.4S uint32x4_t vpaddq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VPADDQ_U64: // ADDP Vd.2D,Vn.2D,Vm.2D uint64x2_t vpaddq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VPADDQ_U8: // ADDP Vd.16B,Vn.16B,Vm.16B uint8x16_t vpaddq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VPMAXQ_S16: // SMAXP Vd.8H,Vn.8H,Vm.8H int16x8_t vpmaxq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VPMAXQ_S32: // SMAXP Vd.4S,Vn.4S,Vm.4S int32x4_t vpmaxq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VPMAXQ_S8: // SMAXP Vd.16B,Vn.16B,Vm.16B int8x16_t vpmaxq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VPMAXQ_U16: // UMAXP Vd.8H,Vn.8H,Vm.8H uint16x8_t vpmaxq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VPMAXQ_U32: // UMAXP Vd.4S,Vn.4S,Vm.4S uint32x4_t vpmaxq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VPMAXQ_U8: // UMAXP Vd.16B,Vn.16B,Vm.16B uint8x16_t vpmaxq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VPMINQ_S16: // SMINP Vd.8H,Vn.8H,Vm.8H int16x8_t vpminq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VPMINQ_S32: // SMINP Vd.4S,Vn.4S,Vm.4S int32x4_t vpminq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VPMINQ_S8: // SMINP Vd.16B,Vn.16B,Vm.16B int8x16_t vpminq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VPMINQ_U16: // UMINP Vd.8H,Vn.8H,Vm.8H uint16x8_t vpminq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VPMINQ_U32: // UMINP Vd.4S,Vn.4S,Vm.4S uint32x4_t vpminq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VPMINQ_U8: // UMINP Vd.16B,Vn.16B,Vm.16B uint8x16_t vpminq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VQABSQ_S16: // SQABS Vd.8H,Vn.8H int16x8_t vqabsq_s16(int16x8_t a)
+ case ARM64_INTRIN_VQABSQ_S32: // SQABS Vd.4S,Vn.4S int32x4_t vqabsq_s32(int32x4_t a)
+ case ARM64_INTRIN_VQABSQ_S64: // SQABS Vd.2D,Vn.2D int64x2_t vqabsq_s64(int64x2_t a)
+ case ARM64_INTRIN_VQABSQ_S8: // SQABS Vd.16B,Vn.16B int8x16_t vqabsq_s8(int8x16_t a)
+ case ARM64_INTRIN_VQADDQ_S16: // SQADD Vd.8H,Vn.8H,Vm.8H int16x8_t vqaddq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQADDQ_S32: // SQADD Vd.4S,Vn.4S,Vm.4S int32x4_t vqaddq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQADDQ_S64: // SQADD Vd.2D,Vn.2D,Vm.2D int64x2_t vqaddq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VQADDQ_S8: // SQADD Vd.16B,Vn.16B,Vm.16B int8x16_t vqaddq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VQADDQ_U16: // UQADD Vd.8H,Vn.8H,Vm.8H uint16x8_t vqaddq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VQADDQ_U32: // UQADD Vd.4S,Vn.4S,Vm.4S uint32x4_t vqaddq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VQADDQ_U64: // UQADD Vd.2D,Vn.2D,Vm.2D uint64x2_t vqaddq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VQADDQ_U8: // UQADD Vd.16B,Vn.16B,Vm.16B uint8x16_t vqaddq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VQDMLAL_HIGH_LANE_S16: // SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vqdmlal_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_HIGH_LANE_S32: // SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vqdmlal_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_HIGH_LANEQ_S16: // SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vqdmlal_high_laneq_s16(int32x4_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_HIGH_LANEQ_S32: // SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vqdmlal_high_laneq_s32(int64x2_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_HIGH_N_S16: // SQDMLAL2 Vd.4S,Vn.8H,Vm.H[0] int32x4_t vqdmlal_high_n_s16(int32x4_t a, int16x8_t b, int16_t c)
+ case ARM64_INTRIN_VQDMLAL_HIGH_N_S32: // SQDMLAL2 Vd.2D,Vn.4S,Vm.S[0] int64x2_t vqdmlal_high_n_s32(int64x2_t a, int32x4_t b, int32_t c)
+ case ARM64_INTRIN_VQDMLAL_HIGH_S16: // SQDMLAL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vqdmlal_high_s16(int32x4_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VQDMLAL_HIGH_S32: // SQDMLAL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vqdmlal_high_s32(int64x2_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VQDMLAL_LANE_S16: // SQDMLAL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vqdmlal_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_LANE_S32: // SQDMLAL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vqdmlal_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_LANEQ_S16: // SQDMLAL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vqdmlal_laneq_s16(int32x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_LANEQ_S32: // SQDMLAL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vqdmlal_laneq_s32(int64x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLAL_N_S16: // SQDMLAL Vd.4S,Vn.4H,Vm.H[0] int32x4_t vqdmlal_n_s16(int32x4_t a, int16x4_t b, int16_t c)
+ case ARM64_INTRIN_VQDMLAL_N_S32: // SQDMLAL Vd.2D,Vn.2S,Vm.S[0] int64x2_t vqdmlal_n_s32(int64x2_t a, int32x2_t b, int32_t c)
+ case ARM64_INTRIN_VQDMLAL_S16: // SQDMLAL Vd.4S,Vn.4H,Vm.4H int32x4_t vqdmlal_s16(int32x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VQDMLAL_S32: // SQDMLAL Vd.2D,Vn.2S,Vm.2S int64x2_t vqdmlal_s32(int64x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VQDMLSL_HIGH_LANE_S16: // SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vqdmlsl_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_HIGH_LANE_S32: // SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vqdmlsl_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_HIGH_LANEQ_S16: // SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vqdmlsl_high_laneq_s16(int32x4_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_HIGH_LANEQ_S32: // SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vqdmlsl_high_laneq_s32(int64x2_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_HIGH_N_S16: // SQDMLSL2 Vd.4S,Vn.8H,Vm.H[0] int32x4_t vqdmlsl_high_n_s16(int32x4_t a, int16x8_t b, int16_t c)
+ case ARM64_INTRIN_VQDMLSL_HIGH_N_S32: // SQDMLSL2 Vd.2D,Vn.4S,Vm.S[0] int64x2_t vqdmlsl_high_n_s32(int64x2_t a, int32x4_t b, int32_t c)
+ case ARM64_INTRIN_VQDMLSL_HIGH_S16: // SQDMLSL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vqdmlsl_high_s16(int32x4_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VQDMLSL_HIGH_S32: // SQDMLSL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vqdmlsl_high_s32(int64x2_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VQDMLSL_LANE_S16: // SQDMLSL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vqdmlsl_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_LANE_S32: // SQDMLSL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vqdmlsl_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_LANEQ_S16: // SQDMLSL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vqdmlsl_laneq_s16(int32x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_LANEQ_S32: // SQDMLSL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vqdmlsl_laneq_s32(int64x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSL_N_S16: // SQDMLSL Vd.4S,Vn.4H,Vm.H[0] int32x4_t vqdmlsl_n_s16(int32x4_t a, int16x4_t b, int16_t c)
+ case ARM64_INTRIN_VQDMLSL_N_S32: // SQDMLSL Vd.2D,Vn.2S,Vm.S[0] int64x2_t vqdmlsl_n_s32(int64x2_t a, int32x2_t b, int32_t c)
+ case ARM64_INTRIN_VQDMLSL_S16: // SQDMLSL Vd.4S,Vn.4H,Vm.4H int32x4_t vqdmlsl_s16(int32x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VQDMLSL_S32: // SQDMLSL Vd.2D,Vn.2S,Vm.2S int64x2_t vqdmlsl_s32(int64x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VQDMULHQ_LANE_S16: // SQDMULH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqdmulhq_lane_s16(int16x8_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULHQ_LANE_S32: // SQDMULH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqdmulhq_lane_s32(int32x4_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMULHQ_LANEQ_S16: // SQDMULH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqdmulhq_laneq_s16(int16x8_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMULHQ_LANEQ_S32: // SQDMULH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqdmulhq_laneq_s32(int32x4_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULHQ_N_S16: // SQDMULH Vd.8H,Vn.8H,Vm.H[0] int16x8_t vqdmulhq_n_s16(int16x8_t a, int16_t b)
+ case ARM64_INTRIN_VQDMULHQ_N_S32: // SQDMULH Vd.4S,Vn.4S,Vm.S[0] int32x4_t vqdmulhq_n_s32(int32x4_t a, int32_t b)
+ case ARM64_INTRIN_VQDMULHQ_S16: // SQDMULH Vd.8H,Vn.8H,Vm.8H int16x8_t vqdmulhq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQDMULHQ_S32: // SQDMULH Vd.4S,Vn.4S,Vm.4S int32x4_t vqdmulhq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQDMULL_HIGH_LANE_S16: // SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vqdmull_high_lane_s16(int16x8_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_HIGH_LANE_S32: // SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vqdmull_high_lane_s32(int32x4_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_HIGH_LANEQ_S16: // SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane] int32x4_t vqdmull_high_laneq_s16(int16x8_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_HIGH_LANEQ_S32: // SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane] int64x2_t vqdmull_high_laneq_s32(int32x4_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_HIGH_N_S16: // SQDMULL2 Vd.4S,Vn.8H,Vm.H[0] int32x4_t vqdmull_high_n_s16(int16x8_t a, int16_t b)
+ case ARM64_INTRIN_VQDMULL_HIGH_N_S32: // SQDMULL2 Vd.2D,Vn.4S,Vm.S[0] int64x2_t vqdmull_high_n_s32(int32x4_t a, int32_t b)
+ case ARM64_INTRIN_VQDMULL_HIGH_S16: // SQDMULL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vqdmull_high_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQDMULL_HIGH_S32: // SQDMULL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vqdmull_high_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQDMULL_LANE_S16: // SQDMULL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vqdmull_lane_s16(int16x4_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_LANE_S32: // SQDMULL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vqdmull_lane_s32(int32x2_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_LANEQ_S16: // SQDMULL Vd.4S,Vn.4H,Vm.H[lane] int32x4_t vqdmull_laneq_s16(int16x4_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_LANEQ_S32: // SQDMULL Vd.2D,Vn.2S,Vm.S[lane] int64x2_t vqdmull_laneq_s32(int32x2_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULL_N_S16: // SQDMULL Vd.4S,Vn.4H,Vm.H[0] int32x4_t vqdmull_n_s16(int16x4_t a, int16_t b)
+ case ARM64_INTRIN_VQDMULL_N_S32: // SQDMULL Vd.2D,Vn.2S,Vm.S[0] int64x2_t vqdmull_n_s32(int32x2_t a, int32_t b)
+ case ARM64_INTRIN_VQDMULL_S16: // SQDMULL Vd.4S,Vn.4H,Vm.4H int32x4_t vqdmull_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQDMULL_S32: // SQDMULL Vd.2D,Vn.2S,Vm.2S int64x2_t vqdmull_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQMOVN_HIGH_S16: // SQXTN2 Vd.16B,Vn.8H int8x16_t vqmovn_high_s16(int8x8_t r, int16x8_t a)
+ case ARM64_INTRIN_VQMOVN_HIGH_S32: // SQXTN2 Vd.8H,Vn.4S int16x8_t vqmovn_high_s32(int16x4_t r, int32x4_t a)
+ case ARM64_INTRIN_VQMOVN_HIGH_S64: // SQXTN2 Vd.4S,Vn.2D int32x4_t vqmovn_high_s64(int32x2_t r, int64x2_t a)
+ case ARM64_INTRIN_VQMOVN_HIGH_U16: // UQXTN2 Vd.16B,Vn.8H uint8x16_t vqmovn_high_u16(uint8x8_t r, uint16x8_t a)
+ case ARM64_INTRIN_VQMOVN_HIGH_U32: // UQXTN2 Vd.8H,Vn.4S uint16x8_t vqmovn_high_u32(uint16x4_t r, uint32x4_t a)
+ case ARM64_INTRIN_VQMOVN_HIGH_U64: // UQXTN2 Vd.4S,Vn.2D uint32x4_t vqmovn_high_u64(uint32x2_t r, uint64x2_t a)
+ case ARM64_INTRIN_VQMOVUN_HIGH_S16: // SQXTUN2 Vd.16B,Vn.8H uint8x16_t vqmovun_high_s16(uint8x8_t r, int16x8_t a)
+ case ARM64_INTRIN_VQMOVUN_HIGH_S32: // SQXTUN2 Vd.8H,Vn.4S uint16x8_t vqmovun_high_s32(uint16x4_t r, int32x4_t a)
+ case ARM64_INTRIN_VQMOVUN_HIGH_S64: // SQXTUN2 Vd.4S,Vn.2D uint32x4_t vqmovun_high_s64(uint32x2_t r, int64x2_t a)
+ case ARM64_INTRIN_VQNEGQ_S16: // SQNEG Vd.8H,Vn.8H int16x8_t vqnegq_s16(int16x8_t a)
+ case ARM64_INTRIN_VQNEGQ_S32: // SQNEG Vd.4S,Vn.4S int32x4_t vqnegq_s32(int32x4_t a)
+ case ARM64_INTRIN_VQNEGQ_S64: // SQNEG Vd.2D,Vn.2D int64x2_t vqnegq_s64(int64x2_t a)
+ case ARM64_INTRIN_VQNEGQ_S8: // SQNEG Vd.16B,Vn.16B int8x16_t vqnegq_s8(int8x16_t a)
+ case ARM64_INTRIN_VQRDMLAHQ_LANE_S16: // SQRDMLAH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqrdmlahq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAHQ_LANE_S32: // SQRDMLAH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqrdmlahq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAHQ_LANEQ_S16: // SQRDMLAH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqrdmlahq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAHQ_LANEQ_S32: // SQRDMLAH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqrdmlahq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAHQ_S16: // SQRDMLAH Vd.8H,Vn.8H,Vm.8H int16x8_t vqrdmlahq_s16(int16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VQRDMLAHQ_S32: // SQRDMLAH Vd.4S,Vn.4S,Vm.4S int32x4_t vqrdmlahq_s32(int32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VQRDMLSHQ_LANE_S16: // SQRDMLSH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqrdmlshq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHQ_LANE_S32: // SQRDMLSH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqrdmlshq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHQ_LANEQ_S16: // SQRDMLSH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqrdmlshq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHQ_LANEQ_S32: // SQRDMLSH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqrdmlshq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHQ_S16: // SQRDMLSH Vd.8H,Vn.8H,Vm.8H int16x8_t vqrdmlshq_s16(int16x8_t a, int16x8_t b, int16x8_t c)
+ case ARM64_INTRIN_VQRDMLSHQ_S32: // SQRDMLSH Vd.4S,Vn.4S,Vm.4S int32x4_t vqrdmlshq_s32(int32x4_t a, int32x4_t b, int32x4_t c)
+ case ARM64_INTRIN_VQRDMULHQ_LANE_S16: // SQRDMULH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqrdmulhq_lane_s16(int16x8_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHQ_LANE_S32: // SQRDMULH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqrdmulhq_lane_s32(int32x4_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHQ_LANEQ_S16: // SQRDMULH Vd.8H,Vn.8H,Vm.H[lane] int16x8_t vqrdmulhq_laneq_s16(int16x8_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHQ_LANEQ_S32: // SQRDMULH Vd.4S,Vn.4S,Vm.S[lane] int32x4_t vqrdmulhq_laneq_s32(int32x4_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHQ_N_S16: // SQRDMULH Vd.8H,Vn.8H,Vm.H[0] int16x8_t vqrdmulhq_n_s16(int16x8_t a, int16_t b)
+ case ARM64_INTRIN_VQRDMULHQ_N_S32: // SQRDMULH Vd.4S,Vn.4S,Vm.S[0] int32x4_t vqrdmulhq_n_s32(int32x4_t a, int32_t b)
+ case ARM64_INTRIN_VQRDMULHQ_S16: // SQRDMULH Vd.8H,Vn.8H,Vm.8H int16x8_t vqrdmulhq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQRDMULHQ_S32: // SQRDMULH Vd.4S,Vn.4S,Vm.4S int32x4_t vqrdmulhq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQRSHLQ_S16: // SQRSHL Vd.8H,Vn.8H,Vm.8H int16x8_t vqrshlq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQRSHLQ_S32: // SQRSHL Vd.4S,Vn.4S,Vm.4S int32x4_t vqrshlq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQRSHLQ_S64: // SQRSHL Vd.2D,Vn.2D,Vm.2D int64x2_t vqrshlq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VQRSHLQ_S8: // SQRSHL Vd.16B,Vn.16B,Vm.16B int8x16_t vqrshlq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VQRSHLQ_U16: // UQRSHL Vd.8H,Vn.8H,Vm.8H uint16x8_t vqrshlq_u16(uint16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQRSHLQ_U32: // UQRSHL Vd.4S,Vn.4S,Vm.4S uint32x4_t vqrshlq_u32(uint32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQRSHLQ_U64: // UQRSHL Vd.2D,Vn.2D,Vm.2D uint64x2_t vqrshlq_u64(uint64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VQRSHLQ_U8: // UQRSHL Vd.16B,Vn.16B,Vm.16B uint8x16_t vqrshlq_u8(uint8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VQRSHRN_HIGH_N_S16: // SQRSHRN2 Vd.16B,Vn.8H,#n int8x16_t vqrshrn_high_n_s16(int8x8_t r, int16x8_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_HIGH_N_S32: // SQRSHRN2 Vd.8H,Vn.4S,#n int16x8_t vqrshrn_high_n_s32(int16x4_t r, int32x4_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_HIGH_N_S64: // SQRSHRN2 Vd.4S,Vn.2D,#n int32x4_t vqrshrn_high_n_s64(int32x2_t r, int64x2_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_HIGH_N_U16: // UQRSHRN2 Vd.16B,Vn.8H,#n uint8x16_t vqrshrn_high_n_u16(uint8x8_t r, uint16x8_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_HIGH_N_U32: // UQRSHRN2 Vd.8H,Vn.4S,#n uint16x8_t vqrshrn_high_n_u32(uint16x4_t r, uint32x4_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_HIGH_N_U64: // UQRSHRN2 Vd.4S,Vn.2D,#n uint32x4_t vqrshrn_high_n_u64(uint32x2_t r, uint64x2_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUN_HIGH_N_S16: // SQRSHRUN2 Vd.16B,Vn.8H,#n uint8x16_t vqrshrun_high_n_s16(uint8x8_t r, int16x8_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUN_HIGH_N_S32: // SQRSHRUN2 Vd.8H,Vn.4S,#n uint16x8_t vqrshrun_high_n_s32(uint16x4_t r, int32x4_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUN_HIGH_N_S64: // SQRSHRUN2 Vd.4S,Vn.2D,#n uint32x4_t vqrshrun_high_n_s64(uint32x2_t r, int64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_S16: // SQSHL Vd.8H,Vn.8H,#n int16x8_t vqshlq_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_S32: // SQSHL Vd.4S,Vn.4S,#n int32x4_t vqshlq_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_S64: // SQSHL Vd.2D,Vn.2D,#n int64x2_t vqshlq_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_S8: // SQSHL Vd.16B,Vn.16B,#n int8x16_t vqshlq_n_s8(int8x16_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_U16: // UQSHL Vd.8H,Vn.8H,#n uint16x8_t vqshlq_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_U32: // UQSHL Vd.4S,Vn.4S,#n uint32x4_t vqshlq_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_U64: // UQSHL Vd.2D,Vn.2D,#n uint64x2_t vqshlq_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_N_U8: // UQSHL Vd.16B,Vn.16B,#n uint8x16_t vqshlq_n_u8(uint8x16_t a, const int n)
+ case ARM64_INTRIN_VQSHLQ_S16: // SQSHL Vd.8H,Vn.8H,Vm.8H int16x8_t vqshlq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQSHLQ_S32: // SQSHL Vd.4S,Vn.4S,Vm.4S int32x4_t vqshlq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQSHLQ_S64: // SQSHL Vd.2D,Vn.2D,Vm.2D int64x2_t vqshlq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VQSHLQ_S8: // SQSHL Vd.16B,Vn.16B,Vm.16B int8x16_t vqshlq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VQSHLQ_U16: // UQSHL Vd.8H,Vn.8H,Vm.8H uint16x8_t vqshlq_u16(uint16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQSHLQ_U32: // UQSHL Vd.4S,Vn.4S,Vm.4S uint32x4_t vqshlq_u32(uint32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQSHLQ_U64: // UQSHL Vd.2D,Vn.2D,Vm.2D uint64x2_t vqshlq_u64(uint64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VQSHLQ_U8: // UQSHL Vd.16B,Vn.16B,Vm.16B uint8x16_t vqshlq_u8(uint8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VQSHLUQ_N_S16: // SQSHLU Vd.8H,Vn.8H,#n uint16x8_t vqshluq_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHLUQ_N_S32: // SQSHLU Vd.4S,Vn.4S,#n uint32x4_t vqshluq_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHLUQ_N_S64: // SQSHLU Vd.2D,Vn.2D,#n uint64x2_t vqshluq_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHLUQ_N_S8: // SQSHLU Vd.16B,Vn.16B,#n uint8x16_t vqshluq_n_s8(int8x16_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_HIGH_N_S16: // SQSHRN2 Vd.16B,Vn.8H,#n int8x16_t vqshrn_high_n_s16(int8x8_t r, int16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_HIGH_N_S32: // SQSHRN2 Vd.8H,Vn.4S,#n int16x8_t vqshrn_high_n_s32(int16x4_t r, int32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_HIGH_N_S64: // SQSHRN2 Vd.4S,Vn.2D,#n int32x4_t vqshrn_high_n_s64(int32x2_t r, int64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_HIGH_N_U16: // UQSHRN2 Vd.16B,Vn.8H,#n uint8x16_t vqshrn_high_n_u16(uint8x8_t r, uint16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_HIGH_N_U32: // UQSHRN2 Vd.8H,Vn.4S,#n uint16x8_t vqshrn_high_n_u32(uint16x4_t r, uint32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_HIGH_N_U64: // UQSHRN2 Vd.4S,Vn.2D,#n uint32x4_t vqshrn_high_n_u64(uint32x2_t r, uint64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHRUN_HIGH_N_S16: // SQSHRUN2 Vd.16B,Vn.8H,#n uint8x16_t vqshrun_high_n_s16(uint8x8_t r, int16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHRUN_HIGH_N_S32: // SQSHRUN2 Vd.8H,Vn.4S,#n uint16x8_t vqshrun_high_n_s32(uint16x4_t r, int32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHRUN_HIGH_N_S64: // SQSHRUN2 Vd.4S,Vn.2D,#n uint32x4_t vqshrun_high_n_s64(uint32x2_t r, int64x2_t a, const int n)
+ case ARM64_INTRIN_VQSUBQ_S16: // SQSUB Vd.8H,Vn.8H,Vm.8H int16x8_t vqsubq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VQSUBQ_S32: // SQSUB Vd.4S,Vn.4S,Vm.4S int32x4_t vqsubq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VQSUBQ_S64: // SQSUB Vd.2D,Vn.2D,Vm.2D int64x2_t vqsubq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VQSUBQ_S8: // SQSUB Vd.16B,Vn.16B,Vm.16B int8x16_t vqsubq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VQSUBQ_U16: // UQSUB Vd.8H,Vn.8H,Vm.8H uint16x8_t vqsubq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VQSUBQ_U32: // UQSUB Vd.4S,Vn.4S,Vm.4S uint32x4_t vqsubq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VQSUBQ_U64: // UQSUB Vd.2D,Vn.2D,Vm.2D uint64x2_t vqsubq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VQSUBQ_U8: // UQSUB Vd.16B,Vn.16B,Vm.16B uint8x16_t vqsubq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VRADDHN_HIGH_S16: // RADDHN2 Vd.16B,Vn.8H,Vm.8H int8x16_t vraddhn_high_s16(int8x8_t r, int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VRADDHN_HIGH_S32: // RADDHN2 Vd.8H,Vn.4S,Vm.4S int16x8_t vraddhn_high_s32(int16x4_t r, int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VRADDHN_HIGH_S64: // RADDHN2 Vd.4S,Vn.2D,Vm.2D int32x4_t vraddhn_high_s64(int32x2_t r, int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VRADDHN_HIGH_U16: // RADDHN2 Vd.16B,Vn.8H,Vm.8H uint8x16_t vraddhn_high_u16(uint8x8_t r, uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VRADDHN_HIGH_U32: // RADDHN2 Vd.8H,Vn.4S,Vm.4S uint16x8_t vraddhn_high_u32(uint16x4_t r, uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VRADDHN_HIGH_U64: // RADDHN2 Vd.4S,Vn.2D,Vm.2D uint32x4_t vraddhn_high_u64(uint32x2_t r, uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VRAX1Q_U64: // RAX1 Vd.2D,Vn.2D,Vm.2D uint64x2_t vrax1q_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VRBITQ_P8: // RBIT Vd.16B,Vn.16B poly8x16_t vrbitq_p8(poly8x16_t a)
+ case ARM64_INTRIN_VRBITQ_S8: // RBIT Vd.16B,Vn.16B int8x16_t vrbitq_s8(int8x16_t a)
+ case ARM64_INTRIN_VRBITQ_U8: // RBIT Vd.16B,Vn.16B uint8x16_t vrbitq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VRECPEQ_U32: // URECPE Vd.4S,Vn.4S uint32x4_t vrecpeq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VREV16Q_P8: // REV16 Vd.16B,Vn.16B poly8x16_t vrev16q_p8(poly8x16_t vec)
+ case ARM64_INTRIN_VREV16Q_S8: // REV16 Vd.16B,Vn.16B int8x16_t vrev16q_s8(int8x16_t vec)
+ case ARM64_INTRIN_VREV16Q_U8: // REV16 Vd.16B,Vn.16B uint8x16_t vrev16q_u8(uint8x16_t vec)
+ case ARM64_INTRIN_VREV32Q_P16: // REV32 Vd.8H,Vn.8H poly16x8_t vrev32q_p16(poly16x8_t vec)
+ case ARM64_INTRIN_VREV32Q_P8: // REV32 Vd.16B,Vn.16B poly8x16_t vrev32q_p8(poly8x16_t vec)
+ case ARM64_INTRIN_VREV32Q_S16: // REV32 Vd.8H,Vn.8H int16x8_t vrev32q_s16(int16x8_t vec)
+ case ARM64_INTRIN_VREV32Q_S8: // REV32 Vd.16B,Vn.16B int8x16_t vrev32q_s8(int8x16_t vec)
+ case ARM64_INTRIN_VREV32Q_U16: // REV32 Vd.8H,Vn.8H uint16x8_t vrev32q_u16(uint16x8_t vec)
+ case ARM64_INTRIN_VREV32Q_U8: // REV32 Vd.16B,Vn.16B uint8x16_t vrev32q_u8(uint8x16_t vec)
+ case ARM64_INTRIN_VREV64Q_P16: // REV64 Vd.8H,Vn.8H poly16x8_t vrev64q_p16(poly16x8_t vec)
+ case ARM64_INTRIN_VREV64Q_P8: // REV64 Vd.16B,Vn.16B poly8x16_t vrev64q_p8(poly8x16_t vec)
+ case ARM64_INTRIN_VREV64Q_S16: // REV64 Vd.8H,Vn.8H int16x8_t vrev64q_s16(int16x8_t vec)
+ case ARM64_INTRIN_VREV64Q_S32: // REV64 Vd.4S,Vn.4S int32x4_t vrev64q_s32(int32x4_t vec)
+ case ARM64_INTRIN_VREV64Q_S8: // REV64 Vd.16B,Vn.16B int8x16_t vrev64q_s8(int8x16_t vec)
+ case ARM64_INTRIN_VREV64Q_U16: // REV64 Vd.8H,Vn.8H uint16x8_t vrev64q_u16(uint16x8_t vec)
+ case ARM64_INTRIN_VREV64Q_U32: // REV64 Vd.4S,Vn.4S uint32x4_t vrev64q_u32(uint32x4_t vec)
+ case ARM64_INTRIN_VREV64Q_U8: // REV64 Vd.16B,Vn.16B uint8x16_t vrev64q_u8(uint8x16_t vec)
+ case ARM64_INTRIN_VRHADDQ_S16: // SRHADD Vd.8H,Vn.8H,Vm.8H int16x8_t vrhaddq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VRHADDQ_S32: // SRHADD Vd.4S,Vn.4S,Vm.4S int32x4_t vrhaddq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VRHADDQ_S8: // SRHADD Vd.16B,Vn.16B,Vm.16B int8x16_t vrhaddq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VRHADDQ_U16: // URHADD Vd.8H,Vn.8H,Vm.8H uint16x8_t vrhaddq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VRHADDQ_U32: // URHADD Vd.4S,Vn.4S,Vm.4S uint32x4_t vrhaddq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VRHADDQ_U8: // URHADD Vd.16B,Vn.16B,Vm.16B uint8x16_t vrhaddq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VRSHLQ_S16: // SRSHL Vd.8H,Vn.8H,Vm.8H int16x8_t vrshlq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VRSHLQ_S32: // SRSHL Vd.4S,Vn.4S,Vm.4S int32x4_t vrshlq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VRSHLQ_S64: // SRSHL Vd.2D,Vn.2D,Vm.2D int64x2_t vrshlq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VRSHLQ_S8: // SRSHL Vd.16B,Vn.16B,Vm.16B int8x16_t vrshlq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VRSHLQ_U16: // URSHL Vd.8H,Vn.8H,Vm.8H uint16x8_t vrshlq_u16(uint16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VRSHLQ_U32: // URSHL Vd.4S,Vn.4S,Vm.4S uint32x4_t vrshlq_u32(uint32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VRSHLQ_U64: // URSHL Vd.2D,Vn.2D,Vm.2D uint64x2_t vrshlq_u64(uint64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VRSHLQ_U8: // URSHL Vd.16B,Vn.16B,Vm.16B uint8x16_t vrshlq_u8(uint8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VRSHRN_HIGH_N_S16: // RSHRN2 Vd.16B,Vn.8H,#n int8x16_t vrshrn_high_n_s16(int8x8_t r, int16x8_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_HIGH_N_S32: // RSHRN2 Vd.8H,Vn.4S,#n int16x8_t vrshrn_high_n_s32(int16x4_t r, int32x4_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_HIGH_N_S64: // RSHRN2 Vd.4S,Vn.2D,#n int32x4_t vrshrn_high_n_s64(int32x2_t r, int64x2_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_HIGH_N_U16: // RSHRN2 Vd.16B,Vn.8H,#n uint8x16_t vrshrn_high_n_u16(uint8x8_t r, uint16x8_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_HIGH_N_U32: // RSHRN2 Vd.8H,Vn.4S,#n uint16x8_t vrshrn_high_n_u32(uint16x4_t r, uint32x4_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_HIGH_N_U64: // RSHRN2 Vd.4S,Vn.2D,#n uint32x4_t vrshrn_high_n_u64(uint32x2_t r, uint64x2_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_S16: // SRSHR Vd.8H,Vn.8H,#n int16x8_t vrshrq_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_S32: // SRSHR Vd.4S,Vn.4S,#n int32x4_t vrshrq_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_S64: // SRSHR Vd.2D,Vn.2D,#n int64x2_t vrshrq_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_S8: // SRSHR Vd.16B,Vn.16B,#n int8x16_t vrshrq_n_s8(int8x16_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_U16: // URSHR Vd.8H,Vn.8H,#n uint16x8_t vrshrq_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_U32: // URSHR Vd.4S,Vn.4S,#n uint32x4_t vrshrq_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_U64: // URSHR Vd.2D,Vn.2D,#n uint64x2_t vrshrq_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VRSHRQ_N_U8: // URSHR Vd.16B,Vn.16B,#n uint8x16_t vrshrq_n_u8(uint8x16_t a, const int n)
+ case ARM64_INTRIN_VRSQRTEQ_U32: // URSQRTE Vd.4S,Vn.4S uint32x4_t vrsqrteq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VRSRAQ_N_S16: // SRSRA Vd.8H,Vn.8H,#n int16x8_t vrsraq_n_s16(int16x8_t a, int16x8_t b, const int n)
+ case ARM64_INTRIN_VRSRAQ_N_S32: // SRSRA Vd.4S,Vn.4S,#n int32x4_t vrsraq_n_s32(int32x4_t a, int32x4_t b, const int n)
+ case ARM64_INTRIN_VRSRAQ_N_S64: // SRSRA Vd.2D,Vn.2D,#n int64x2_t vrsraq_n_s64(int64x2_t a, int64x2_t b, const int n)
+ case ARM64_INTRIN_VRSRAQ_N_S8: // SRSRA Vd.16B,Vn.16B,#n int8x16_t vrsraq_n_s8(int8x16_t a, int8x16_t b, const int n)
+ case ARM64_INTRIN_VRSRAQ_N_U16: // URSRA Vd.8H,Vn.8H,#n uint16x8_t vrsraq_n_u16(uint16x8_t a, uint16x8_t b, const int n)
+ case ARM64_INTRIN_VRSRAQ_N_U32: // URSRA Vd.4S,Vn.4S,#n uint32x4_t vrsraq_n_u32(uint32x4_t a, uint32x4_t b, const int n)
+ case ARM64_INTRIN_VRSRAQ_N_U64: // URSRA Vd.2D,Vn.2D,#n uint64x2_t vrsraq_n_u64(uint64x2_t a, uint64x2_t b, const int n)
+ case ARM64_INTRIN_VRSRAQ_N_U8: // URSRA Vd.16B,Vn.16B,#n uint8x16_t vrsraq_n_u8(uint8x16_t a, uint8x16_t b, const int n)
+ case ARM64_INTRIN_VRSUBHN_HIGH_S16: // RSUBHN2 Vd.16B,Vn.8H,Vm.8H int8x16_t vrsubhn_high_s16(int8x8_t r, int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VRSUBHN_HIGH_S32: // RSUBHN2 Vd.8H,Vn.4S,Vm.4S int16x8_t vrsubhn_high_s32(int16x4_t r, int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VRSUBHN_HIGH_S64: // RSUBHN2 Vd.4S,Vn.2D,Vm.2D int32x4_t vrsubhn_high_s64(int32x2_t r, int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VRSUBHN_HIGH_U16: // RSUBHN2 Vd.16B,Vn.8H,Vm.8H uint8x16_t vrsubhn_high_u16(uint8x8_t r, uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VRSUBHN_HIGH_U32: // RSUBHN2 Vd.8H,Vn.4S,Vm.4S uint16x8_t vrsubhn_high_u32(uint16x4_t r, uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VRSUBHN_HIGH_U64: // RSUBHN2 Vd.4S,Vn.2D,Vm.2D uint32x4_t vrsubhn_high_u64(uint32x2_t r, uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VSETQ_LANE_P16: // MOV Vd.H[lane],Rn poly16x8_t vsetq_lane_p16(poly16_t a, poly16x8_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_P64: // MOV Vd.D[lane],Rn poly64x2_t vsetq_lane_p64(poly64_t a, poly64x2_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_P8: // MOV Vd.B[lane],Rn poly8x16_t vsetq_lane_p8(poly8_t a, poly8x16_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_S16: // MOV Vd.H[lane],Rn int16x8_t vsetq_lane_s16(int16_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_S32: // MOV Vd.S[lane],Rn int32x4_t vsetq_lane_s32(int32_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_S64: // MOV Vd.D[lane],Rn int64x2_t vsetq_lane_s64(int64_t a, int64x2_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_S8: // MOV Vd.B[lane],Rn int8x16_t vsetq_lane_s8(int8_t a, int8x16_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_U16: // MOV Vd.H[lane],Rn uint16x8_t vsetq_lane_u16(uint16_t a, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_U32: // MOV Vd.S[lane],Rn uint32x4_t vsetq_lane_u32(uint32_t a, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_U64: // MOV Vd.D[lane],Rn uint64x2_t vsetq_lane_u64(uint64_t a, uint64x2_t v, const int lane)
+ case ARM64_INTRIN_VSETQ_LANE_U8: // MOV Vd.B[lane],Rn uint8x16_t vsetq_lane_u8(uint8_t a, uint8x16_t v, const int lane)
+ case ARM64_INTRIN_VSHA1CQ_U32: // SHA1C Qd,Sn,Vm.4S uint32x4_t vsha1cq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+ case ARM64_INTRIN_VSHA1MQ_U32: // SHA1M Qd,Sn,Vm.4S uint32x4_t vsha1mq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+ case ARM64_INTRIN_VSHA1PQ_U32: // SHA1P Qd,Sn,Vm.4S uint32x4_t vsha1pq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+ case ARM64_INTRIN_VSHA1SU0Q_U32: // SHA1SU0 Vd.4S,Vn.4S,Vm.4S uint32x4_t vsha1su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11)
+ case ARM64_INTRIN_VSHA1SU1Q_U32: // SHA1SU1 Vd.4S,Vn.4S uint32x4_t vsha1su1q_u32(uint32x4_t tw0_3, uint32x4_t w12_15)
+ case ARM64_INTRIN_VSHA256H2Q_U32: // SHA256H2 Qd,Qn,Vm.4S uint32x4_t vsha256h2q_u32(uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk)
+ case ARM64_INTRIN_VSHA256HQ_U32: // SHA256H Qd,Qn,Vm.4S uint32x4_t vsha256hq_u32(uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk)
+ case ARM64_INTRIN_VSHA256SU0Q_U32: // SHA256SU0 Vd.4S,Vn.4S uint32x4_t vsha256su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7)
+ case ARM64_INTRIN_VSHA256SU1Q_U32: // SHA256SU1 Vd.4S,Vn.4S,Vm.4S uint32x4_t vsha256su1q_u32(uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15)
+ case ARM64_INTRIN_VSHA512H2Q_U64: // SHA512H2 Qd,Qn,Vm.2D uint64x2_t vsha512h2q_u64(uint64x2_t sum_ab, uint64x2_t hash_c_, uint64x2_t hash_ab)
+ case ARM64_INTRIN_VSHA512HQ_U64: // SHA512H Qd,Qn,Vm.2D uint64x2_t vsha512hq_u64(uint64x2_t hash_ed, uint64x2_t hash_gf, uint64x2_t kwh_kwh2)
+ case ARM64_INTRIN_VSHA512SU0Q_U64: // SHA512SU0 Vd.2D,Vn.2D uint64x2_t vsha512su0q_u64(uint64x2_t w0_1, uint64x2_t w2_)
+ case ARM64_INTRIN_VSHA512SU1Q_U64: // SHA512SU1 Vd.2D,Vn.2D,Vm.2D uint64x2_t vsha512su1q_u64(uint64x2_t s01_s02, uint64x2_t w14_15, uint64x2_t w9_10)
+ case ARM64_INTRIN_VSHLL_HIGH_N_S16: // SHLL2 Vd.4S,Vn.8H,#n int32x4_t vshll_high_n_s16(int16x8_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_HIGH_N_S16: // SSHLL2 Vd.4S,Vn.8H,#n int32x4_t vshll_high_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VSHLL_HIGH_N_S32: // SHLL2 Vd.2D,Vn.4S,#n int64x2_t vshll_high_n_s32(int32x4_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_HIGH_N_S32: // SSHLL2 Vd.2D,Vn.4S,#n int64x2_t vshll_high_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VSHLL_HIGH_N_S8: // SHLL2 Vd.8H,Vn.16B,#n int16x8_t vshll_high_n_s8(int8x16_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_HIGH_N_S8: // SSHLL2 Vd.8H,Vn.16B,#n int16x8_t vshll_high_n_s8(int8x16_t a, const int n)
+ case ARM64_INTRIN_VSHLL_HIGH_N_U16: // SHLL2 Vd.4S,Vn.8H,#n uint32x4_t vshll_high_n_u16(uint16x8_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_HIGH_N_U16: // USHLL2 Vd.4S,Vn.8H,#n uint32x4_t vshll_high_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VSHLL_HIGH_N_U32: // SHLL2 Vd.2D,Vn.4S,#n uint64x2_t vshll_high_n_u32(uint32x4_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_HIGH_N_U32: // USHLL2 Vd.2D,Vn.4S,#n uint64x2_t vshll_high_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VSHLL_HIGH_N_U8: // SHLL2 Vd.8H,Vn.16B,#n uint16x8_t vshll_high_n_u8(uint8x16_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_HIGH_N_U8: // USHLL2 Vd.8H,Vn.16B,#n uint16x8_t vshll_high_n_u8(uint8x16_t a, const int n)
+ case ARM64_INTRIN_VSHLL_N_S16: // SHLL Vd.4S,Vn.4H,#n int32x4_t vshll_n_s16(int16x4_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_N_S16: // SSHLL Vd.4S,Vn.4H,#n int32x4_t vshll_n_s16(int16x4_t a, const int n)
+ case ARM64_INTRIN_VSHLL_N_S32: // SHLL Vd.2D,Vn.2S,#n int64x2_t vshll_n_s32(int32x2_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_N_S32: // SSHLL Vd.2D,Vn.2S,#n int64x2_t vshll_n_s32(int32x2_t a, const int n)
+ case ARM64_INTRIN_VSHLL_N_S8: // SHLL Vd.8H,Vn.8B,#n int16x8_t vshll_n_s8(int8x8_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_N_S8: // SSHLL Vd.8H,Vn.8B,#n int16x8_t vshll_n_s8(int8x8_t a, const int n)
+ case ARM64_INTRIN_VSHLL_N_U16: // SHLL Vd.4S,Vn.4H,#n uint32x4_t vshll_n_u16(uint16x4_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_N_U16: // USHLL Vd.4S,Vn.4H,#n uint32x4_t vshll_n_u16(uint16x4_t a, const int n)
+ case ARM64_INTRIN_VSHLL_N_U32: // SHLL Vd.2D,Vn.2S,#n uint64x2_t vshll_n_u32(uint32x2_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_N_U32: // USHLL Vd.2D,Vn.2S,#n uint64x2_t vshll_n_u32(uint32x2_t a, const int n)
+ case ARM64_INTRIN_VSHLL_N_U8: // SHLL Vd.8H,Vn.8B,#n uint16x8_t vshll_n_u8(uint8x8_t a, const int n)
+ // case ARM64_INTRIN_VSHLL_N_U8: // USHLL Vd.8H,Vn.8B,#n uint16x8_t vshll_n_u8(uint8x8_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_S16: // SHL Vd.8H,Vn.8H,#n int16x8_t vshlq_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_S32: // SHL Vd.4S,Vn.4S,#n int32x4_t vshlq_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_S64: // SHL Vd.2D,Vn.2D,#n int64x2_t vshlq_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_S8: // SHL Vd.16B,Vn.16B,#n int8x16_t vshlq_n_s8(int8x16_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_U16: // SHL Vd.8H,Vn.8H,#n uint16x8_t vshlq_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_U32: // SHL Vd.4S,Vn.4S,#n uint32x4_t vshlq_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_U64: // SHL Vd.2D,Vn.2D,#n uint64x2_t vshlq_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_N_U8: // SHL Vd.16B,Vn.16B,#n uint8x16_t vshlq_n_u8(uint8x16_t a, const int n)
+ case ARM64_INTRIN_VSHLQ_S16: // SSHL Vd.8H,Vn.8H,Vm.8H int16x8_t vshlq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VSHLQ_S32: // SSHL Vd.4S,Vn.4S,Vm.4S int32x4_t vshlq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VSHLQ_S64: // SSHL Vd.2D,Vn.2D,Vm.2D int64x2_t vshlq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VSHLQ_S8: // SSHL Vd.16B,Vn.16B,Vm.16B int8x16_t vshlq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VSHLQ_U16: // USHL Vd.8H,Vn.8H,Vm.8H uint16x8_t vshlq_u16(uint16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VSHLQ_U32: // USHL Vd.4S,Vn.4S,Vm.4S uint32x4_t vshlq_u32(uint32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VSHLQ_U64: // USHL Vd.2D,Vn.2D,Vm.2D uint64x2_t vshlq_u64(uint64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VSHLQ_U8: // USHL Vd.16B,Vn.16B,Vm.16B uint8x16_t vshlq_u8(uint8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VSHRN_HIGH_N_S16: // SHRN2 Vd.16B,Vn.8H,#n int8x16_t vshrn_high_n_s16(int8x8_t r, int16x8_t a, const int n)
+ case ARM64_INTRIN_VSHRN_HIGH_N_S32: // SHRN2 Vd.8H,Vn.4S,#n int16x8_t vshrn_high_n_s32(int16x4_t r, int32x4_t a, const int n)
+ case ARM64_INTRIN_VSHRN_HIGH_N_S64: // SHRN2 Vd.4S,Vn.2D,#n int32x4_t vshrn_high_n_s64(int32x2_t r, int64x2_t a, const int n)
+ case ARM64_INTRIN_VSHRN_HIGH_N_U16: // SHRN2 Vd.16B,Vn.8H,#n uint8x16_t vshrn_high_n_u16(uint8x8_t r, uint16x8_t a, const int n)
+ case ARM64_INTRIN_VSHRN_HIGH_N_U32: // SHRN2 Vd.8H,Vn.4S,#n uint16x8_t vshrn_high_n_u32(uint16x4_t r, uint32x4_t a, const int n)
+ case ARM64_INTRIN_VSHRN_HIGH_N_U64: // SHRN2 Vd.4S,Vn.2D,#n uint32x4_t vshrn_high_n_u64(uint32x2_t r, uint64x2_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_S16: // SSHR Vd.8H,Vn.8H,#n int16x8_t vshrq_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_S32: // SSHR Vd.4S,Vn.4S,#n int32x4_t vshrq_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_S64: // SSHR Vd.2D,Vn.2D,#n int64x2_t vshrq_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_S8: // SSHR Vd.16B,Vn.16B,#n int8x16_t vshrq_n_s8(int8x16_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_U16: // USHR Vd.8H,Vn.8H,#n uint16x8_t vshrq_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_U32: // USHR Vd.4S,Vn.4S,#n uint32x4_t vshrq_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_U64: // USHR Vd.2D,Vn.2D,#n uint64x2_t vshrq_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VSHRQ_N_U8: // USHR Vd.16B,Vn.16B,#n uint8x16_t vshrq_n_u8(uint8x16_t a, const int n)
+ case ARM64_INTRIN_VSLIQ_N_P16: // SLI Vd.8H,Vn.8H,#n poly16x8_t vsliq_n_p16(poly16x8_t a, poly16x8_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_P64: // SLI Vd.2D,Vn.2D,#n poly64x2_t vsliq_n_p64(poly64x2_t a, poly64x2_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_P8: // SLI Vd.16B,Vn.16B,#n poly8x16_t vsliq_n_p8(poly8x16_t a, poly8x16_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_S16: // SLI Vd.8H,Vn.8H,#n int16x8_t vsliq_n_s16(int16x8_t a, int16x8_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_S32: // SLI Vd.4S,Vn.4S,#n int32x4_t vsliq_n_s32(int32x4_t a, int32x4_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_S64: // SLI Vd.2D,Vn.2D,#n int64x2_t vsliq_n_s64(int64x2_t a, int64x2_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_S8: // SLI Vd.16B,Vn.16B,#n int8x16_t vsliq_n_s8(int8x16_t a, int8x16_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_U16: // SLI Vd.8H,Vn.8H,#n uint16x8_t vsliq_n_u16(uint16x8_t a, uint16x8_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_U32: // SLI Vd.4S,Vn.4S,#n uint32x4_t vsliq_n_u32(uint32x4_t a, uint32x4_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_U64: // SLI Vd.2D,Vn.2D,#n uint64x2_t vsliq_n_u64(uint64x2_t a, uint64x2_t b, const int n)
+ case ARM64_INTRIN_VSLIQ_N_U8: // SLI Vd.16B,Vn.16B,#n uint8x16_t vsliq_n_u8(uint8x16_t a, uint8x16_t b, const int n)
+ case ARM64_INTRIN_VSM3PARTW1Q_U32: // SM3PARTW1 Vd.4S,Vn.4S,Vm.4S uint32x4_t vsm3partw1q_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VSM3PARTW2Q_U32: // SM3PARTW2 Vd.4S,Vn.4S,Vm.4S uint32x4_t vsm3partw2q_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VSM3SS1Q_U32: // SM3SS1 Vd.4S,Vn.4S,Vm.4S,Va.4S uint32x4_t vsm3ss1q_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c)
+ case ARM64_INTRIN_VSM3TT1AQ_U32: // SM3TT1A Vd.4S,Vn.4S,Vm.4S[imm2] uint32x4_t vsm3tt1aq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c, const int imm2)
+ case ARM64_INTRIN_VSM3TT1BQ_U32: // SM3TT1B Vd.4S,Vn.4S,Vm.4S[imm2] uint32x4_t vsm3tt1bq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c, const int imm2)
+ case ARM64_INTRIN_VSM3TT2AQ_U32: // SM3TT2A Vd.4S,Vn.4S,Vm.4S[imm2] uint32x4_t vsm3tt2aq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c, const int imm2)
+ case ARM64_INTRIN_VSM3TT2BQ_U32: // SM3TT2B Vd.4S,Vn.4S,Vm.4S[imm2] uint32x4_t vsm3tt2bq_u32(uint32x4_t a, uint32x4_t b, uint32x4_t c, const int imm2)
+ case ARM64_INTRIN_VSM4EKEYQ_U32: // SM4EKEY Vd.4S,Vn.4S,Vm.4S uint32x4_t vsm4ekeyq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VSM4EQ_U32: // SM4E Vd.4S,Vn.4S uint32x4_t vsm4eq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VSQADDQ_U16: // USQADD Vd.8H,Vn.8H uint16x8_t vsqaddq_u16(uint16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VSQADDQ_U32: // USQADD Vd.4S,Vn.4S uint32x4_t vsqaddq_u32(uint32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VSQADDQ_U64: // USQADD Vd.2D,Vn.2D uint64x2_t vsqaddq_u64(uint64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VSQADDQ_U8: // USQADD Vd.16B,Vn.16B uint8x16_t vsqaddq_u8(uint8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VSRAQ_N_S16: // SSRA Vd.8H,Vn.8H,#n int16x8_t vsraq_n_s16(int16x8_t a, int16x8_t b, const int n)
+ case ARM64_INTRIN_VSRAQ_N_S32: // SSRA Vd.4S,Vn.4S,#n int32x4_t vsraq_n_s32(int32x4_t a, int32x4_t b, const int n)
+ case ARM64_INTRIN_VSRAQ_N_S64: // SSRA Vd.2D,Vn.2D,#n int64x2_t vsraq_n_s64(int64x2_t a, int64x2_t b, const int n)
+ case ARM64_INTRIN_VSRAQ_N_S8: // SSRA Vd.16B,Vn.16B,#n int8x16_t vsraq_n_s8(int8x16_t a, int8x16_t b, const int n)
+ case ARM64_INTRIN_VSRAQ_N_U16: // USRA Vd.8H,Vn.8H,#n uint16x8_t vsraq_n_u16(uint16x8_t a, uint16x8_t b, const int n)
+ case ARM64_INTRIN_VSRAQ_N_U32: // USRA Vd.4S,Vn.4S,#n uint32x4_t vsraq_n_u32(uint32x4_t a, uint32x4_t b, const int n)
+ case ARM64_INTRIN_VSRAQ_N_U64: // USRA Vd.2D,Vn.2D,#n uint64x2_t vsraq_n_u64(uint64x2_t a, uint64x2_t b, const int n)
+ case ARM64_INTRIN_VSRAQ_N_U8: // USRA Vd.16B,Vn.16B,#n uint8x16_t vsraq_n_u8(uint8x16_t a, uint8x16_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_P16: // SRI Vd.8H,Vn.8H,#n poly16x8_t vsriq_n_p16(poly16x8_t a, poly16x8_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_P64: // SRI Vd.2D,Vn.2D,#n poly64x2_t vsriq_n_p64(poly64x2_t a, poly64x2_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_P8: // SRI Vd.16B,Vn.16B,#n poly8x16_t vsriq_n_p8(poly8x16_t a, poly8x16_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_S16: // SRI Vd.8H,Vn.8H,#n int16x8_t vsriq_n_s16(int16x8_t a, int16x8_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_S32: // SRI Vd.4S,Vn.4S,#n int32x4_t vsriq_n_s32(int32x4_t a, int32x4_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_S64: // SRI Vd.2D,Vn.2D,#n int64x2_t vsriq_n_s64(int64x2_t a, int64x2_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_S8: // SRI Vd.16B,Vn.16B,#n int8x16_t vsriq_n_s8(int8x16_t a, int8x16_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_U16: // SRI Vd.8H,Vn.8H,#n uint16x8_t vsriq_n_u16(uint16x8_t a, uint16x8_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_U32: // SRI Vd.4S,Vn.4S,#n uint32x4_t vsriq_n_u32(uint32x4_t a, uint32x4_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_U64: // SRI Vd.2D,Vn.2D,#n uint64x2_t vsriq_n_u64(uint64x2_t a, uint64x2_t b, const int n)
+ case ARM64_INTRIN_VSRIQ_N_U8: // SRI Vd.16B,Vn.16B,#n uint8x16_t vsriq_n_u8(uint8x16_t a, uint8x16_t b, const int n)
+ case ARM64_INTRIN_VSUBHN_HIGH_S16: // SUBHN2 Vd.16B,Vn.8H,Vm.8H int8x16_t vsubhn_high_s16(int8x8_t r, int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VSUBHN_HIGH_S32: // SUBHN2 Vd.8H,Vn.4S,Vm.4S int16x8_t vsubhn_high_s32(int16x4_t r, int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VSUBHN_HIGH_S64: // SUBHN2 Vd.4S,Vn.2D,Vm.2D int32x4_t vsubhn_high_s64(int32x2_t r, int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VSUBHN_HIGH_U16: // SUBHN2 Vd.16B,Vn.8H,Vm.8H uint8x16_t vsubhn_high_u16(uint8x8_t r, uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VSUBHN_HIGH_U32: // SUBHN2 Vd.8H,Vn.4S,Vm.4S uint16x8_t vsubhn_high_u32(uint16x4_t r, uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VSUBHN_HIGH_U64: // SUBHN2 Vd.4S,Vn.2D,Vm.2D uint32x4_t vsubhn_high_u64(uint32x2_t r, uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VSUBL_HIGH_S16: // SSUBL2 Vd.4S,Vn.8H,Vm.8H int32x4_t vsubl_high_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VSUBL_HIGH_S32: // SSUBL2 Vd.2D,Vn.4S,Vm.4S int64x2_t vsubl_high_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VSUBL_HIGH_S8: // SSUBL2 Vd.8H,Vn.16B,Vm.16B int16x8_t vsubl_high_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VSUBL_HIGH_U16: // USUBL2 Vd.4S,Vn.8H,Vm.8H uint32x4_t vsubl_high_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VSUBL_HIGH_U32: // USUBL2 Vd.2D,Vn.4S,Vm.4S uint64x2_t vsubl_high_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VSUBL_HIGH_U8: // USUBL2 Vd.8H,Vn.16B,Vm.16B uint16x8_t vsubl_high_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VSUBL_S16: // SSUBL Vd.4S,Vn.4H,Vm.4H int32x4_t vsubl_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VSUBL_S32: // SSUBL Vd.2D,Vn.2S,Vm.2S int64x2_t vsubl_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VSUBL_S8: // SSUBL Vd.8H,Vn.8B,Vm.8B int16x8_t vsubl_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VSUBL_U16: // USUBL Vd.4S,Vn.4H,Vm.4H uint32x4_t vsubl_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VSUBL_U32: // USUBL Vd.2D,Vn.2S,Vm.2S uint64x2_t vsubl_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VSUBL_U8: // USUBL Vd.8H,Vn.8B,Vm.8B uint16x8_t vsubl_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VSUBQ_S16: // SUB Vd.8H,Vn.8H,Vm.8H int16x8_t vsubq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VSUBQ_S32: // SUB Vd.4S,Vn.4S,Vm.4S int32x4_t vsubq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VSUBQ_S64: // SUB Vd.2D,Vn.2D,Vm.2D int64x2_t vsubq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VSUBQ_S8: // SUB Vd.16B,Vn.16B,Vm.16B int8x16_t vsubq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VSUBQ_U16: // SUB Vd.8H,Vn.8H,Vm.8H uint16x8_t vsubq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VSUBQ_U32: // SUB Vd.4S,Vn.4S,Vm.4S uint32x4_t vsubq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VSUBQ_U64: // SUB Vd.2D,Vn.2D,Vm.2D uint64x2_t vsubq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VSUBQ_U8: // SUB Vd.16B,Vn.16B,Vm.16B uint8x16_t vsubq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VSUBW_HIGH_S16: // SSUBW2 Vd.4S,Vn.4S,Vm.8H int32x4_t vsubw_high_s16(int32x4_t a, int16x8_t b)
+ case ARM64_INTRIN_VSUBW_HIGH_S32: // SSUBW2 Vd.2D,Vn.2D,Vm.4S int64x2_t vsubw_high_s32(int64x2_t a, int32x4_t b)
+ case ARM64_INTRIN_VSUBW_HIGH_S8: // SSUBW2 Vd.8H,Vn.8H,Vm.16B int16x8_t vsubw_high_s8(int16x8_t a, int8x16_t b)
+ case ARM64_INTRIN_VSUBW_HIGH_U16: // USUBW2 Vd.4S,Vn.4S,Vm.8H uint32x4_t vsubw_high_u16(uint32x4_t a, uint16x8_t b)
+ case ARM64_INTRIN_VSUBW_HIGH_U32: // USUBW2 Vd.2D,Vn.2D,Vm.4S uint64x2_t vsubw_high_u32(uint64x2_t a, uint32x4_t b)
+ case ARM64_INTRIN_VSUBW_HIGH_U8: // USUBW2 Vd.8H,Vn.8H,Vm.16B uint16x8_t vsubw_high_u8(uint16x8_t a, uint8x16_t b)
+ case ARM64_INTRIN_VSUBW_S16: // SSUBW Vd.4S,Vn.4S,Vm.4H int32x4_t vsubw_s16(int32x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VSUBW_S32: // SSUBW Vd.2D,Vn.2D,Vm.2S int64x2_t vsubw_s32(int64x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VSUBW_S8: // SSUBW Vd.8H,Vn.8H,Vm.8B int16x8_t vsubw_s8(int16x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VSUBW_U16: // USUBW Vd.4S,Vn.4S,Vm.4H uint32x4_t vsubw_u16(uint32x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VSUBW_U32: // USUBW Vd.2D,Vn.2D,Vm.2S uint64x2_t vsubw_u32(uint64x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VSUBW_U8: // USUBW Vd.8H,Vn.8H,Vm.8B uint16x8_t vsubw_u8(uint16x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VSUDOTQ_LANE_S32: // SUDOT Vd.4S,Vn.16B,Vm.4B[lane] int32x4_t vsudotq_lane_s32(int32x4_t r, int8x16_t a, uint8x8_t b, const int lane)
+ case ARM64_INTRIN_VSUDOTQ_LANEQ_S32: // SUDOT Vd.4S,Vn.16B,Vm.4B[lane] int32x4_t vsudotq_laneq_s32(int32x4_t r, int8x16_t a, uint8x16_t b, const int lane)
+ case ARM64_INTRIN_VTRN1Q_P16: // TRN1 Vd.8H,Vn.8H,Vm.8H poly16x8_t vtrn1q_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VTRN1Q_P64: // TRN1 Vd.2D,Vn.2D,Vm.2D poly64x2_t vtrn1q_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VTRN1Q_P8: // TRN1 Vd.16B,Vn.16B,Vm.16B poly8x16_t vtrn1q_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VTRN1Q_S16: // TRN1 Vd.8H,Vn.8H,Vm.8H int16x8_t vtrn1q_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VTRN1Q_S32: // TRN1 Vd.4S,Vn.4S,Vm.4S int32x4_t vtrn1q_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VTRN1Q_S64: // TRN1 Vd.2D,Vn.2D,Vm.2D int64x2_t vtrn1q_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VTRN1Q_S8: // TRN1 Vd.16B,Vn.16B,Vm.16B int8x16_t vtrn1q_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VTRN1Q_U16: // TRN1 Vd.8H,Vn.8H,Vm.8H uint16x8_t vtrn1q_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VTRN1Q_U32: // TRN1 Vd.4S,Vn.4S,Vm.4S uint32x4_t vtrn1q_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VTRN1Q_U64: // TRN1 Vd.2D,Vn.2D,Vm.2D uint64x2_t vtrn1q_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VTRN1Q_U8: // TRN1 Vd.16B,Vn.16B,Vm.16B uint8x16_t vtrn1q_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VTRN2Q_P16: // TRN2 Vd.8H,Vn.8H,Vm.8H poly16x8_t vtrn2q_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VTRN2Q_P64: // TRN2 Vd.2D,Vn.2D,Vm.2D poly64x2_t vtrn2q_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VTRN2Q_P8: // TRN2 Vd.16B,Vn.16B,Vm.16B poly8x16_t vtrn2q_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VTRN2Q_S16: // TRN2 Vd.8H,Vn.8H,Vm.8H int16x8_t vtrn2q_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VTRN2Q_S32: // TRN2 Vd.4S,Vn.4S,Vm.4S int32x4_t vtrn2q_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VTRN2Q_S64: // TRN2 Vd.2D,Vn.2D,Vm.2D int64x2_t vtrn2q_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VTRN2Q_S8: // TRN2 Vd.16B,Vn.16B,Vm.16B int8x16_t vtrn2q_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VTRN2Q_U16: // TRN2 Vd.8H,Vn.8H,Vm.8H uint16x8_t vtrn2q_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VTRN2Q_U32: // TRN2 Vd.4S,Vn.4S,Vm.4S uint32x4_t vtrn2q_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VTRN2Q_U64: // TRN2 Vd.2D,Vn.2D,Vm.2D uint64x2_t vtrn2q_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VTRN2Q_U8: // TRN2 Vd.16B,Vn.16B,Vm.16B uint8x16_t vtrn2q_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VTSTQ_P64: // CMTST Vd.2D,Vn.2D,Vm.2D uint64x2_t vtstq_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VTSTQ_P8: // CMTST Vd.16B,Vn.16B,Vm.16B uint8x16_t vtstq_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VTSTQ_S16: // CMTST Vd.8H,Vn.8H,Vm.8H uint16x8_t vtstq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VTSTQ_S32: // CMTST Vd.4S,Vn.4S,Vm.4S uint32x4_t vtstq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VTSTQ_S64: // CMTST Vd.2D,Vn.2D,Vm.2D uint64x2_t vtstq_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VTSTQ_S8: // CMTST Vd.16B,Vn.16B,Vm.16B uint8x16_t vtstq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VTSTQ_U16: // CMTST Vd.8H,Vn.8H,Vm.8H uint16x8_t vtstq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VTSTQ_U32: // CMTST Vd.4S,Vn.4S,Vm.4S uint32x4_t vtstq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VTSTQ_U64: // CMTST Vd.2D,Vn.2D,Vm.2D uint64x2_t vtstq_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VTSTQ_U8: // CMTST Vd.16B,Vn.16B,Vm.16B uint8x16_t vtstq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VUQADDQ_S16: // SUQADD Vd.8H,Vn.8H int16x8_t vuqaddq_s16(int16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VUQADDQ_S32: // SUQADD Vd.4S,Vn.4S int32x4_t vuqaddq_s32(int32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VUQADDQ_S64: // SUQADD Vd.2D,Vn.2D int64x2_t vuqaddq_s64(int64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VUQADDQ_S8: // SUQADD Vd.16B,Vn.16B int8x16_t vuqaddq_s8(int8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VUSDOTQ_LANE_S32: // USDOT Vd.4S,Vn.16B,Vm.4B[lane] int32x4_t vusdotq_lane_s32(int32x4_t r, uint8x16_t a, int8x8_t b, const int lane)
+ case ARM64_INTRIN_VUSDOTQ_LANEQ_S32: // USDOT Vd.4S,Vn.16B,Vm.4B[lane] int32x4_t vusdotq_laneq_s32(int32x4_t r, uint8x16_t a, int8x16_t b, const int lane)
+ case ARM64_INTRIN_VUSDOTQ_S32: // USDOT Vd.4S,Vn.16B,Vm.16B int32x4_t vusdotq_s32(int32x4_t r, uint8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VUSMMLAQ_S32: // USMMLA Vd.4S,Vn.16B,Vm.16B int32x4_t vusmmlaq_s32(int32x4_t r, uint8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VUZP1Q_P16: // UZP1 Vd.8H,Vn.8H,Vm.8H poly16x8_t vuzp1q_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VUZP1Q_P64: // UZP1 Vd.2D,Vn.2D,Vm.2D poly64x2_t vuzp1q_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VUZP1Q_P8: // UZP1 Vd.16B,Vn.16B,Vm.16B poly8x16_t vuzp1q_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VUZP1Q_S16: // UZP1 Vd.8H,Vn.8H,Vm.8H int16x8_t vuzp1q_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VUZP1Q_S32: // UZP1 Vd.4S,Vn.4S,Vm.4S int32x4_t vuzp1q_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VUZP1Q_S64: // UZP1 Vd.2D,Vn.2D,Vm.2D int64x2_t vuzp1q_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VUZP1Q_S8: // UZP1 Vd.16B,Vn.16B,Vm.16B int8x16_t vuzp1q_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VUZP1Q_U16: // UZP1 Vd.8H,Vn.8H,Vm.8H uint16x8_t vuzp1q_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VUZP1Q_U32: // UZP1 Vd.4S,Vn.4S,Vm.4S uint32x4_t vuzp1q_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VUZP1Q_U64: // UZP1 Vd.2D,Vn.2D,Vm.2D uint64x2_t vuzp1q_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VUZP1Q_U8: // UZP1 Vd.16B,Vn.16B,Vm.16B uint8x16_t vuzp1q_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VUZP2Q_P16: // UZP2 Vd.8H,Vn.8H,Vm.8H poly16x8_t vuzp2q_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VUZP2Q_P64: // UZP2 Vd.2D,Vn.2D,Vm.2D poly64x2_t vuzp2q_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VUZP2Q_P8: // UZP2 Vd.16B,Vn.16B,Vm.16B poly8x16_t vuzp2q_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VUZP2Q_S16: // UZP2 Vd.8H,Vn.8H,Vm.8H int16x8_t vuzp2q_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VUZP2Q_S32: // UZP2 Vd.4S,Vn.4S,Vm.4S int32x4_t vuzp2q_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VUZP2Q_S64: // UZP2 Vd.2D,Vn.2D,Vm.2D int64x2_t vuzp2q_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VUZP2Q_S8: // UZP2 Vd.16B,Vn.16B,Vm.16B int8x16_t vuzp2q_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VUZP2Q_U16: // UZP2 Vd.8H,Vn.8H,Vm.8H uint16x8_t vuzp2q_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VUZP2Q_U32: // UZP2 Vd.4S,Vn.4S,Vm.4S uint32x4_t vuzp2q_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VUZP2Q_U64: // UZP2 Vd.2D,Vn.2D,Vm.2D uint64x2_t vuzp2q_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VUZP2Q_U8: // UZP2 Vd.16B,Vn.16B,Vm.16B uint8x16_t vuzp2q_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VXARQ_U64: // XAR Vd.2D,Vn.2D,Vm.2D,imm6 uint64x2_t vxarq_u64(uint64x2_t a, uint64x2_t b, const int imm6)
+ case ARM64_INTRIN_VZIP1Q_P16: // ZIP1 Vd.8H,Vn.8H,Vm.8H poly16x8_t vzip1q_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VZIP1Q_P64: // ZIP1 Vd.2D,Vn.2D,Vm.2D poly64x2_t vzip1q_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VZIP1Q_P8: // ZIP1 Vd.16B,Vn.16B,Vm.16B poly8x16_t vzip1q_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VZIP1Q_S16: // ZIP1 Vd.8H,Vn.8H,Vm.8H int16x8_t vzip1q_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VZIP1Q_S32: // ZIP1 Vd.4S,Vn.4S,Vm.4S int32x4_t vzip1q_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VZIP1Q_S64: // ZIP1 Vd.2D,Vn.2D,Vm.2D int64x2_t vzip1q_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VZIP1Q_S8: // ZIP1 Vd.16B,Vn.16B,Vm.16B int8x16_t vzip1q_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VZIP1Q_U16: // ZIP1 Vd.8H,Vn.8H,Vm.8H uint16x8_t vzip1q_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VZIP1Q_U32: // ZIP1 Vd.4S,Vn.4S,Vm.4S uint32x4_t vzip1q_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VZIP1Q_U64: // ZIP1 Vd.2D,Vn.2D,Vm.2D uint64x2_t vzip1q_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VZIP1Q_U8: // ZIP1 Vd.16B,Vn.16B,Vm.16B uint8x16_t vzip1q_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VZIP2Q_P16: // ZIP2 Vd.8H,Vn.8H,Vm.8H poly16x8_t vzip2q_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VZIP2Q_P64: // ZIP2 Vd.2D,Vn.2D,Vm.2D poly64x2_t vzip2q_p64(poly64x2_t a, poly64x2_t b)
+ case ARM64_INTRIN_VZIP2Q_P8: // ZIP2 Vd.16B,Vn.16B,Vm.16B poly8x16_t vzip2q_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VZIP2Q_S16: // ZIP2 Vd.8H,Vn.8H,Vm.8H int16x8_t vzip2q_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VZIP2Q_S32: // ZIP2 Vd.4S,Vn.4S,Vm.4S int32x4_t vzip2q_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VZIP2Q_S64: // ZIP2 Vd.2D,Vn.2D,Vm.2D int64x2_t vzip2q_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VZIP2Q_S8: // ZIP2 Vd.16B,Vn.16B,Vm.16B int8x16_t vzip2q_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VZIP2Q_U16: // ZIP2 Vd.8H,Vn.8H,Vm.8H uint16x8_t vzip2q_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VZIP2Q_U32: // ZIP2 Vd.4S,Vn.4S,Vm.4S uint32x4_t vzip2q_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VZIP2Q_U64: // ZIP2 Vd.2D,Vn.2D,Vm.2D uint64x2_t vzip2q_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VZIP2Q_U8: // ZIP2 Vd.16B,Vn.16B,Vm.16B uint8x16_t vzip2q_u8(uint8x16_t a, uint8x16_t b)
+ return {Type::IntegerType(16, false)};
+ case ARM64_INTRIN_VTRNQ_P16: // TRN1 Vd1.8H,Vn.8H,Vm.8H poly16x8x2_t vtrnq_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VTRNQ_P8: // TRN1 Vd1.16B,Vn.16B,Vm.16B poly8x16x2_t vtrnq_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VTRNQ_S16: // TRN1 Vd1.8H,Vn.8H,Vm.8H int16x8x2_t vtrnq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VTRNQ_S32: // TRN1 Vd1.4S,Vn.4S,Vm.4S int32x4x2_t vtrnq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VTRNQ_S8: // TRN1 Vd1.16B,Vn.16B,Vm.16B int8x16x2_t vtrnq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VTRNQ_U16: // TRN1 Vd1.8H,Vn.8H,Vm.8H uint16x8x2_t vtrnq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VTRNQ_U32: // TRN1 Vd1.4S,Vn.4S,Vm.4S uint32x4x2_t vtrnq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VTRNQ_U8: // TRN1 Vd1.16B,Vn.16B,Vm.16B uint8x16x2_t vtrnq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VUZPQ_P16: // UZP1 Vd1.8H,Vn.8H,Vm.8H poly16x8x2_t vuzpq_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VUZPQ_P8: // UZP1 Vd1.16B,Vn.16B,Vm.16B poly8x16x2_t vuzpq_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VUZPQ_S16: // UZP1 Vd1.8H,Vn.8H,Vm.8H int16x8x2_t vuzpq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VUZPQ_S32: // UZP1 Vd1.4S,Vn.4S,Vm.4S int32x4x2_t vuzpq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VUZPQ_S8: // UZP1 Vd1.16B,Vn.16B,Vm.16B int8x16x2_t vuzpq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VUZPQ_U16: // UZP1 Vd1.8H,Vn.8H,Vm.8H uint16x8x2_t vuzpq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VUZPQ_U32: // UZP1 Vd1.4S,Vn.4S,Vm.4S uint32x4x2_t vuzpq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VUZPQ_U8: // UZP1 Vd1.16B,Vn.16B,Vm.16B uint8x16x2_t vuzpq_u8(uint8x16_t a, uint8x16_t b)
+ case ARM64_INTRIN_VZIPQ_P16: // ZIP1 Vd1.8H,Vn.8H,Vm.8H poly16x8x2_t vzipq_p16(poly16x8_t a, poly16x8_t b)
+ case ARM64_INTRIN_VZIPQ_P8: // ZIP1 Vd1.16B,Vn.16B,Vm.16B poly8x16x2_t vzipq_p8(poly8x16_t a, poly8x16_t b)
+ case ARM64_INTRIN_VZIPQ_S16: // ZIP1 Vd1.8H,Vn.8H,Vm.8H int16x8x2_t vzipq_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VZIPQ_S32: // ZIP1 Vd1.4S,Vn.4S,Vm.4S int32x4x2_t vzipq_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VZIPQ_S8: // ZIP1 Vd1.16B,Vn.16B,Vm.16B int8x16x2_t vzipq_s8(int8x16_t a, int8x16_t b)
+ case ARM64_INTRIN_VZIPQ_U16: // ZIP1 Vd1.8H,Vn.8H,Vm.8H uint16x8x2_t vzipq_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VZIPQ_U32: // ZIP1 Vd1.4S,Vn.4S,Vm.4S uint32x4x2_t vzipq_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VZIPQ_U8: // ZIP1 Vd1.16B,Vn.16B,Vm.16B uint8x16x2_t vzipq_u8(uint8x16_t a, uint8x16_t b)
+ return {Type::IntegerType(16, false), Type::IntegerType(16, false)};
+ case ARM64_INTRIN_VADDLV_S8: // SADDLV Hd,Vn.8B int16_t vaddlv_s8(int8x8_t a)
+ case ARM64_INTRIN_VADDLV_U8: // UADDLV Hd,Vn.8B uint16_t vaddlv_u8(uint8x8_t a)
+ case ARM64_INTRIN_VADDLVQ_S8: // SADDLV Hd,Vn.16B int16_t vaddlvq_s8(int8x16_t a)
+ case ARM64_INTRIN_VADDLVQ_U8: // UADDLV Hd,Vn.16B uint16_t vaddlvq_u8(uint8x16_t a)
+ case ARM64_INTRIN_VADDV_S16: // ADDV Hd,Vn.4H int16_t vaddv_s16(int16x4_t a)
+ case ARM64_INTRIN_VADDV_U16: // ADDV Hd,Vn.4H uint16_t vaddv_u16(uint16x4_t a)
+ case ARM64_INTRIN_VADDVQ_S16: // ADDV Hd,Vn.8H int16_t vaddvq_s16(int16x8_t a)
+ case ARM64_INTRIN_VADDVQ_U16: // ADDV Hd,Vn.8H uint16_t vaddvq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VCAGEH_F16: // FACGE Hd,Hn,Hm uint16_t vcageh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCAGTH_F16: // FACGT Hd,Hn,Hm uint16_t vcagth_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCALEH_F16: // FACGE Hd,Hn,Hm uint16_t vcaleh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCALTH_F16: // FACGT Hd,Hn,Hm uint16_t vcalth_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCEQH_F16: // FCMEQ Hd,Hn,Hm uint16_t vceqh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCEQZH_F16: // FCMEQ Hd,Hn,#0 uint16_t vceqzh_f16(float16_t a)
+ case ARM64_INTRIN_VCGEH_F16: // FCMGE Hd,Hn,Hm uint16_t vcgeh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCGEZH_F16: // FCMGE Hd,Hn,#0 uint16_t vcgezh_f16(float16_t a)
+ case ARM64_INTRIN_VCGTH_F16: // FCMGT Hd,Hn,Hm uint16_t vcgth_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCGTZH_F16: // FCMGT Hd,Hn,#0 uint16_t vcgtzh_f16(float16_t a)
+ case ARM64_INTRIN_VCLEH_F16: // FCMGE Hd,Hn,Hm uint16_t vcleh_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCLEZH_F16: // FCMLE Hd,Hn,#0 uint16_t vclezh_f16(float16_t a)
+ case ARM64_INTRIN_VCLTH_F16: // FCMGT Hd,Hn,Hm uint16_t vclth_f16(float16_t a, float16_t b)
+ case ARM64_INTRIN_VCLTZH_F16: // FCMLT Hd,Hn,#0 uint16_t vcltzh_f16(float16_t a)
+ case ARM64_INTRIN_VCVTAH_S16_F16: // FCVTAS Hd,Hn int16_t vcvtah_s16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTAH_U16_F16: // FCVTAU Hd,Hn uint16_t vcvtah_u16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTH_N_S16_F16: // FCVTZS Hd,Hn,#n int16_t vcvth_n_s16_f16(float16_t a, const int n)
+ case ARM64_INTRIN_VCVTH_N_U16_F16: // FCVTZU Hd,Hn,#n uint16_t vcvth_n_u16_f16(float16_t a, const int n)
+ case ARM64_INTRIN_VCVTH_S16_F16: // FCVTZS Hd,Hn int16_t vcvth_s16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTH_U16_F16: // FCVTZU Hd,Hn uint16_t vcvth_u16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTMH_S16_F16: // FCVTMS Hd,Hn int16_t vcvtmh_s16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTMH_U16_F16: // FCVTMU Hd,Hn uint16_t vcvtmh_u16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTNH_S16_F16: // FCVTNS Hd,Hn int16_t vcvtnh_s16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTNH_U16_F16: // FCVTNU Hd,Hn uint16_t vcvtnh_u16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTPH_S16_F16: // FCVTPS Hd,Hn int16_t vcvtph_s16_f16(float16_t a)
+ case ARM64_INTRIN_VCVTPH_U16_F16: // FCVTPU Hd,Hn uint16_t vcvtph_u16_f16(float16_t a)
+ case ARM64_INTRIN_VDUPH_LANE_P16: // DUP Hd,Vn.H[lane] poly16_t vduph_lane_p16(poly16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANE_S16: // DUP Hd,Vn.H[lane] int16_t vduph_lane_s16(int16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANE_U16: // DUP Hd,Vn.H[lane] uint16_t vduph_lane_u16(uint16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANEQ_P16: // DUP Hd,Vn.H[lane] poly16_t vduph_laneq_p16(poly16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANEQ_S16: // DUP Hd,Vn.H[lane] int16_t vduph_laneq_s16(int16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUPH_LANEQ_U16: // DUP Hd,Vn.H[lane] uint16_t vduph_laneq_u16(uint16x8_t vec, const int lane)
+ case ARM64_INTRIN_VGET_LANE_P16: // UMOV Rd,Vn.H[lane] poly16_t vget_lane_p16(poly16x4_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_S16: // SMOV Rd,Vn.H[lane] int16_t vget_lane_s16(int16x4_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_U16: // UMOV Rd,Vn.H[lane] uint16_t vget_lane_u16(uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_P16: // UMOV Rd,Vn.H[lane] poly16_t vgetq_lane_p16(poly16x8_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_S16: // SMOV Rd,Vn.H[lane] int16_t vgetq_lane_s16(int16x8_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_U16: // UMOV Rd,Vn.H[lane] uint16_t vgetq_lane_u16(uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMAXV_S16: // SMAXV Hd,Vn.4H int16_t vmaxv_s16(int16x4_t a)
+ case ARM64_INTRIN_VMAXV_U16: // UMAXV Hd,Vn.4H uint16_t vmaxv_u16(uint16x4_t a)
+ case ARM64_INTRIN_VMAXVQ_S16: // SMAXV Hd,Vn.8H int16_t vmaxvq_s16(int16x8_t a)
+ case ARM64_INTRIN_VMAXVQ_U16: // UMAXV Hd,Vn.8H uint16_t vmaxvq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VMINV_S16: // SMINV Hd,Vn.4H int16_t vminv_s16(int16x4_t a)
+ case ARM64_INTRIN_VMINV_U16: // UMINV Hd,Vn.4H uint16_t vminv_u16(uint16x4_t a)
+ case ARM64_INTRIN_VMINVQ_S16: // SMINV Hd,Vn.8H int16_t vminvq_s16(int16x8_t a)
+ case ARM64_INTRIN_VMINVQ_U16: // UMINV Hd,Vn.8H uint16_t vminvq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VQABSH_S16: // SQABS Hd,Hn int16_t vqabsh_s16(int16_t a)
+ case ARM64_INTRIN_VQADDH_S16: // SQADD Hd,Hn,Hm int16_t vqaddh_s16(int16_t a, int16_t b)
+ case ARM64_INTRIN_VQADDH_U16: // UQADD Hd,Hn,Hm uint16_t vqaddh_u16(uint16_t a, uint16_t b)
+ case ARM64_INTRIN_VQDMULHH_LANE_S16: // SQDMULH Hd,Hn,Vm.H[lane] int16_t vqdmulhh_lane_s16(int16_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULHH_LANEQ_S16: // SQDMULH Hd,Hn,Vm.H[lane] int16_t vqdmulhh_laneq_s16(int16_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMULHH_S16: // SQDMULH Hd,Hn,Hm int16_t vqdmulhh_s16(int16_t a, int16_t b)
+ case ARM64_INTRIN_VQMOVNS_S32: // SQXTN Hd,Sn int16_t vqmovns_s32(int32_t a)
+ case ARM64_INTRIN_VQMOVNS_U32: // UQXTN Hd,Sn uint16_t vqmovns_u32(uint32_t a)
+ case ARM64_INTRIN_VQMOVUNS_S32: // SQXTUN Hd,Sn uint16_t vqmovuns_s32(int32_t a)
+ case ARM64_INTRIN_VQNEGH_S16: // SQNEG Hd,Hn int16_t vqnegh_s16(int16_t a)
+ case ARM64_INTRIN_VQRDMLAHH_LANE_S16: // SQRDMLAH Hd,Hn,Vm.H[lane] int16_t vqrdmlahh_lane_s16(int16_t a, int16_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAHH_LANEQ_S16: // SQRDMLAH Hd,Hn,Vm.H[lane] int16_t vqrdmlahh_laneq_s16(int16_t a, int16_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAHH_S16: // SQRDMLSH Hd,Hn,Hm int16_t vqrdmlahh_s16(int16_t a, int16_t b, int16_t c)
+ case ARM64_INTRIN_VQRDMLSHH_LANE_S16: // SQRDMLSH Hd,Hn,Vm.H[lane] int16_t vqrdmlshh_lane_s16(int16_t a, int16_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHH_LANEQ_S16: // SQRDMLSH Hd,Hn,Vm.H[lane] int16_t vqrdmlshh_laneq_s16(int16_t a, int16_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHH_S16: // SQRDMLSH Hd,Hn,Hm int16_t vqrdmlshh_s16(int16_t a, int16_t b, int16_t c)
+ case ARM64_INTRIN_VQRDMULHH_LANE_S16: // SQRDMULH Hd,Hn,Vm.H[lane] int16_t vqrdmulhh_lane_s16(int16_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHH_LANEQ_S16: // SQRDMULH Hd,Hn,Vm.H[lane] int16_t vqrdmulhh_laneq_s16(int16_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHH_S16: // SQRDMULH Hd,Hn,Hm int16_t vqrdmulhh_s16(int16_t a, int16_t b)
+ case ARM64_INTRIN_VQRSHLH_S16: // SQRSHL Hd,Hn,Hm int16_t vqrshlh_s16(int16_t a, int16_t b)
+ case ARM64_INTRIN_VQRSHLH_U16: // UQRSHL Hd,Hn,Hm uint16_t vqrshlh_u16(uint16_t a, int16_t b)
+ case ARM64_INTRIN_VQRSHRNS_N_S32: // SQRSHRN Hd,Sn,#n int16_t vqrshrns_n_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VQRSHRNS_N_U32: // UQRSHRN Hd,Sn,#n uint16_t vqrshrns_n_u32(uint32_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUNS_N_S32: // SQRSHRUN Hd,Sn,#n uint16_t vqrshruns_n_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VQSHLH_N_S16: // SQSHL Hd,Hn,#n int16_t vqshlh_n_s16(int16_t a, const int n)
+ case ARM64_INTRIN_VQSHLH_N_U16: // UQSHL Hd,Hn,#n uint16_t vqshlh_n_u16(uint16_t a, const int n)
+ case ARM64_INTRIN_VQSHLH_S16: // SQSHL Hd,Hn,Hm int16_t vqshlh_s16(int16_t a, int16_t b)
+ case ARM64_INTRIN_VQSHLH_U16: // UQSHL Hd,Hn,Hm uint16_t vqshlh_u16(uint16_t a, int16_t b)
+ case ARM64_INTRIN_VQSHLUH_N_S16: // SQSHLU Hd,Hn,#n uint16_t vqshluh_n_s16(int16_t a, const int n)
+ case ARM64_INTRIN_VQSHRNS_N_S32: // SQSHRN Hd,Sn,#n int16_t vqshrns_n_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VQSHRNS_N_U32: // UQSHRN Hd,Sn,#n uint16_t vqshrns_n_u32(uint32_t a, const int n)
+ case ARM64_INTRIN_VQSHRUNS_N_S32: // SQSHRUN Hd,Sn,#n uint16_t vqshruns_n_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VQSUBH_S16: // SQSUB Hd,Hn,Hm int16_t vqsubh_s16(int16_t a, int16_t b)
+ case ARM64_INTRIN_VQSUBH_U16: // UQSUB Hd,Hn,Hm uint16_t vqsubh_u16(uint16_t a, uint16_t b)
+ case ARM64_INTRIN_VSQADDH_U16: // USQADD Hd,Hn uint16_t vsqaddh_u16(uint16_t a, int16_t b)
+ case ARM64_INTRIN_VUQADDH_S16: // SUQADD Hd,Hn int16_t vuqaddh_s16(int16_t a, uint16_t b)
+ return {Type::IntegerType(2, false)};
+ case ARM64_INTRIN___CRC32B: // CRC32B Wd,Wn,Wm uint32_t __crc32b(uint32_t a, uint8_t b)
+ case ARM64_INTRIN___CRC32CB: // CRC32CB Wd,Wn,Wm uint32_t __crc32cb(uint32_t a, uint8_t b)
+ case ARM64_INTRIN___CRC32CD: // CRC32CX Wd,Wn,Xm uint32_t __crc32cd(uint32_t a, uint64_t b)
+ case ARM64_INTRIN___CRC32CH: // CRC32CH Wd,Wn,Wm uint32_t __crc32ch(uint32_t a, uint16_t b)
+ case ARM64_INTRIN___CRC32CW: // CRC32CW Wd,Wn,Wm uint32_t __crc32cw(uint32_t a, uint32_t b)
+ case ARM64_INTRIN___CRC32D: // CRC32X Wd,Wn,Xm uint32_t __crc32d(uint32_t a, uint64_t b)
+ case ARM64_INTRIN___CRC32H: // CRC32H Wd,Wn,Wm uint32_t __crc32h(uint32_t a, uint16_t b)
+ case ARM64_INTRIN___CRC32W: // CRC32W Wd,Wn,Wm uint32_t __crc32w(uint32_t a, uint32_t b)
+ case ARM64_INTRIN_VADDLV_S16: // SADDLV Sd,Vn.4H int32_t vaddlv_s16(int16x4_t a)
+ case ARM64_INTRIN_VADDLV_U16: // UADDLV Sd,Vn.4H uint32_t vaddlv_u16(uint16x4_t a)
+ case ARM64_INTRIN_VADDLVQ_S16: // SADDLV Sd,Vn.8H int32_t vaddlvq_s16(int16x8_t a)
+ case ARM64_INTRIN_VADDLVQ_U16: // UADDLV Sd,Vn.8H uint32_t vaddlvq_u16(uint16x8_t a)
+ case ARM64_INTRIN_VADDV_S32: // ADDP Vd.2S,Vn.2S,Vm.2S int32_t vaddv_s32(int32x2_t a)
+ case ARM64_INTRIN_VADDV_U32: // ADDP Vd.2S,Vn.2S,Vm.2S uint32_t vaddv_u32(uint32x2_t a)
+ case ARM64_INTRIN_VADDVQ_S32: // ADDV Sd,Vn.4S int32_t vaddvq_s32(int32x4_t a)
+ case ARM64_INTRIN_VADDVQ_U32: // ADDV Sd,Vn.4S uint32_t vaddvq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VCAGES_F32: // FACGE Sd,Sn,Sm uint32_t vcages_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCAGTS_F32: // FACGT Sd,Sn,Sm uint32_t vcagts_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCALES_F32: // FACGE Sd,Sm,Sn uint32_t vcales_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCALTS_F32: // FACGT Sd,Sm,Sn uint32_t vcalts_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCEQS_F32: // FCMEQ Sd,Sn,Sm uint32_t vceqs_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCEQZS_F32: // FCMEQ Sd,Sn,#0 uint32_t vceqzs_f32(float32_t a)
+ case ARM64_INTRIN_VCGES_F32: // FCMGE Sd,Sn,Sm uint32_t vcges_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCGEZS_F32: // FCMGE Sd,Sn,#0 uint32_t vcgezs_f32(float32_t a)
+ case ARM64_INTRIN_VCGTS_F32: // FCMGT Sd,Sn,Sm uint32_t vcgts_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCGTZS_F32: // FCMGT Sd,Sn,#0 uint32_t vcgtzs_f32(float32_t a)
+ case ARM64_INTRIN_VCLES_F32: // FCMGE Sd,Sm,Sn uint32_t vcles_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCLEZS_F32: // FCMLE Sd,Sn,#0 uint32_t vclezs_f32(float32_t a)
+ case ARM64_INTRIN_VCLTS_F32: // FCMGT Sd,Sm,Sn uint32_t vclts_f32(float32_t a, float32_t b)
+ case ARM64_INTRIN_VCLTZS_F32: // FCMLT Sd,Sn,#0 uint32_t vcltzs_f32(float32_t a)
+ case ARM64_INTRIN_VCVT_S32_F64: // FCVTZS Wd,Dn int32x1_t vcvt_s32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVT_S32_F64: // FCVTZS Wd,Sn int32x1_t vcvt_s32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVT_U32_F64: // FCVTZU Wd,Dn uint32x1_t vcvt_u32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVT_U32_F64: // FCVTZU Wd,Sn uint32x1_t vcvt_u32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTA_S32_F64: // FCVTAS Wd,Dn int32x1_t vcvta_s32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTA_S32_F64: // FCVTAS Wd,Sn int32x1_t vcvta_s32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTA_U32_F64: // FCVTAU Wd,Dn uint32x1_t vcvta_u32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTA_U32_F64: // FCVTAU Wd,Sn uint32x1_t vcvta_u32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTAD_S32_F64: // FCVTAS Wd,Dn int32_t vcvtad_s32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTAD_S32_F64: // FCVTAS Wd,Sn int32_t vcvtad_s32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTAD_U32_F64: // FCVTAU Wd,Dn uint32_t vcvtad_u32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTAD_U32_F64: // FCVTAU Wd,Sn uint32_t vcvtad_u32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTAS_N_S32_F32: // FCVTAS Wd,Sn,#n int32_t vcvtas_n_s32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTAS_N_U32_F32: // FCVTAU Wd,Sn,#n uint32_t vcvtas_n_u32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTAS_S32_F32: // FCVTAS Sd,Sn int32_t vcvtas_s32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTAS_S32_F32: // FCVTAS Wd,Sn int32_t vcvtas_s32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTAS_U32_F32: // FCVTAU Sd,Sn uint32_t vcvtas_u32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTAS_U32_F32: // FCVTAU Wd,Sn uint32_t vcvtas_u32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTD_S32_F64: // FCVTZS Wd,Dn int32_t vcvtd_s32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTD_S32_F64: // FCVTZS Wd,Sn int32_t vcvtd_s32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTD_U32_F64: // FCVTZU Wd,Dn uint32_t vcvtd_u32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTD_U32_F64: // FCVTZU Wd,Sn uint32_t vcvtd_u32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTM_S32_F64: // FCVTMS Wd,Dn int32x1_t vcvtm_s32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTM_S32_F64: // FCVTMS Wd,Sn int32x1_t vcvtm_s32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTM_U32_F64: // FCVTMU Wd,Dn uint32x1_t vcvtm_u32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTM_U32_F64: // FCVTMU Wd,Sn uint32x1_t vcvtm_u32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTMD_S32_F64: // FCVTMS Wd,Dn int32_t vcvtmd_s32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTMD_S32_F64: // FCVTMS Wd,Sn int32_t vcvtmd_s32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTMD_U32_F64: // FCVTMU Wd,Dn uint32_t vcvtmd_u32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTMD_U32_F64: // FCVTMU Wd,Sn uint32_t vcvtmd_u32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTMS_N_S32_F32: // FCVTMS Wd,Sn,#n int32_t vcvtms_n_s32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTMS_N_U32_F32: // FCVTMU Wd,Sn,#n uint32_t vcvtms_n_u32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTMS_S32_F32: // FCVTMS Sd,Sn int32_t vcvtms_s32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTMS_S32_F32: // FCVTMS Wd,Sn int32_t vcvtms_s32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTMS_U32_F32: // FCVTMU Sd,Sn uint32_t vcvtms_u32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTMS_U32_F32: // FCVTMU Wd,Sn uint32_t vcvtms_u32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTN_S32_F64: // FCVTNS Wd,Dn int32x1_t vcvtn_s32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTN_S32_F64: // FCVTNS Wd,Sn int32x1_t vcvtn_s32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTN_U32_F64: // FCVTNU Wd,Dn uint32x1_t vcvtn_u32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTN_U32_F64: // FCVTNU Wd,Sn uint32x1_t vcvtn_u32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTND_S32_F64: // FCVTNS Wd,Dn int32_t vcvtnd_s32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTND_S32_F64: // FCVTNS Wd,Sn int32_t vcvtnd_s32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTND_U32_F64: // FCVTNU Wd,Dn uint32_t vcvtnd_u32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTND_U32_F64: // FCVTNU Wd,Sn uint32_t vcvtnd_u32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTNS_S32_F32: // FCVTNS Sd,Sn int32_t vcvtns_s32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTNS_S32_F32: // FCVTNS Wd,Sn int32_t vcvtns_s32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTNS_U32_F32: // FCVTNU Sd,Sn uint32_t vcvtns_u32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTNS_U32_F32: // FCVTNU Wd,Sn uint32_t vcvtns_u32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTP_S32_F64: // FCVTPS Wd,Dn int32x1_t vcvtp_s32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTP_S32_F64: // FCVTPS Wd,Sn int32x1_t vcvtp_s32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTP_U32_F64: // FCVTPU Wd,Dn uint32x1_t vcvtp_u32_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTP_U32_F64: // FCVTPU Wd,Sn uint32x1_t vcvtp_u32_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTPD_S32_F64: // FCVTPS Wd,Dn int32_t vcvtpd_s32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTPD_S32_F64: // FCVTPS Wd,Sn int32_t vcvtpd_s32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTPD_U32_F64: // FCVTPU Wd,Dn uint32_t vcvtpd_u32_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTPD_U32_F64: // FCVTPU Wd,Sn uint32_t vcvtpd_u32_f64(float64_t a)
+ case ARM64_INTRIN_VCVTPS_N_S32_F32: // FCVTPS Wd,Sn,#n int32_t vcvtps_n_s32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTPS_N_U32_F32: // FCVTPU Wd,Sn,#n uint32_t vcvtps_n_u32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTPS_S32_F32: // FCVTPS Sd,Sn int32_t vcvtps_s32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTPS_S32_F32: // FCVTPS Wd,Sn int32_t vcvtps_s32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTPS_U32_F32: // FCVTPU Sd,Sn uint32_t vcvtps_u32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTPS_U32_F32: // FCVTPU Wd,Sn uint32_t vcvtps_u32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTS_N_S32_F32: // FCVTZS Sd,Sn,#n int32_t vcvts_n_s32_f32(float32_t a, const int n)
+ // case ARM64_INTRIN_VCVTS_N_S32_F32: // FCVTZS Wd,Sn,#n int32_t vcvts_n_s32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTS_N_U32_F32: // FCVTZU Sd,Sn,#n uint32_t vcvts_n_u32_f32(float32_t a, const int n)
+ // case ARM64_INTRIN_VCVTS_N_U32_F32: // FCVTZU Wd,Sn,#n uint32_t vcvts_n_u32_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTS_N_U32_F64: // FCVTZU Wd,Dn,#n uint32_t vcvts_n_u32_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTS_S32_F32: // FCVTZS Sd,Sn int32_t vcvts_s32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTS_S32_F32: // FCVTZS Wd,Sn int32_t vcvts_s32_f32(float32_t a)
+ case ARM64_INTRIN_VCVTS_U32_F32: // FCVTZU Sd,Sn uint32_t vcvts_u32_f32(float32_t a)
+ // case ARM64_INTRIN_VCVTS_U32_F32: // FCVTZU Wd,Sn uint32_t vcvts_u32_f32(float32_t a)
+ case ARM64_INTRIN_VDUPS_LANE_S32: // DUP Sd,Vn.S[lane] int32_t vdups_lane_s32(int32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPS_LANE_U32: // DUP Sd,Vn.S[lane] uint32_t vdups_lane_u32(uint32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPS_LANEQ_S32: // DUP Sd,Vn.S[lane] int32_t vdups_laneq_s32(int32x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUPS_LANEQ_U32: // DUP Sd,Vn.S[lane] uint32_t vdups_laneq_u32(uint32x4_t vec, const int lane)
+ case ARM64_INTRIN_VGET_LANE_S32: // SMOV Rd,Vn.S[lane] int32_t vget_lane_s32(int32x2_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_U32: // UMOV Rd,Vn.S[lane] uint32_t vget_lane_u32(uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_S32: // SMOV Rd,Vn.S[lane] int32_t vgetq_lane_s32(int32x4_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_U32: // UMOV Rd,Vn.S[lane] uint32_t vgetq_lane_u32(uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMAXV_S32: // SMAXP Vd.2S,Vn.2S,Vm.2S int32_t vmaxv_s32(int32x2_t a)
+ case ARM64_INTRIN_VMAXV_U32: // UMAXP Vd.2S,Vn.2S,Vm.2S uint32_t vmaxv_u32(uint32x2_t a)
+ case ARM64_INTRIN_VMAXVQ_S32: // SMAXV Sd,Vn.4S int32_t vmaxvq_s32(int32x4_t a)
+ case ARM64_INTRIN_VMAXVQ_U32: // UMAXV Sd,Vn.4S uint32_t vmaxvq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VMINV_S32: // SMINP Vd.2S,Vn.2S,Vm.2S int32_t vminv_s32(int32x2_t a)
+ case ARM64_INTRIN_VMINV_U32: // UMINP Vd.2S,Vn.2S,Vm.2S uint32_t vminv_u32(uint32x2_t a)
+ case ARM64_INTRIN_VMINVQ_S32: // SMINV Sd,Vn.4S int32_t vminvq_s32(int32x4_t a)
+ case ARM64_INTRIN_VMINVQ_U32: // UMINV Sd,Vn.4S uint32_t vminvq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VQABSS_S32: // SQABS Sd,Sn int32_t vqabss_s32(int32_t a)
+ case ARM64_INTRIN_VQADDS_S32: // SQADD Sd,Sn,Sm int32_t vqadds_s32(int32_t a, int32_t b)
+ case ARM64_INTRIN_VQADDS_U32: // UQADD Sd,Sn,Sm uint32_t vqadds_u32(uint32_t a, uint32_t b)
+ case ARM64_INTRIN_VQDMLALH_LANE_S16: // SQDMLAL Sd,Hn,Vm.H[lane] int32_t vqdmlalh_lane_s16(int32_t a, int16_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLALH_LANEQ_S16: // SQDMLAL Sd,Hn,Vm.H[lane] int32_t vqdmlalh_laneq_s16(int32_t a, int16_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMLALH_S16: // SQDMLAL Sd,Hn,Hm int32_t vqdmlalh_s16(int32_t a, int16_t b, int16_t c)
+ case ARM64_INTRIN_VQDMLSLH_LANE_S16: // SQDMLSL Sd,Hn,Vm.H[lane] int32_t vqdmlslh_lane_s16(int32_t a, int16_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSLH_LANEQ_S16: // SQDMLSL Sd,Hn,Vm.H[lane] int32_t vqdmlslh_laneq_s16(int32_t a, int16_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSLH_S16: // SQDMLSL Sd,Hn,Hm int32_t vqdmlslh_s16(int32_t a, int16_t b, int16_t c)
+ case ARM64_INTRIN_VQDMULHS_LANE_S32: // SQDMULH Sd,Sn,Vm.H[lane] int32_t vqdmulhs_lane_s32(int32_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMULHS_LANEQ_S32: // SQDMULH Sd,Sn,Vm.H[lane] int32_t vqdmulhs_laneq_s32(int32_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULHS_S32: // SQDMULH Sd,Sn,Sm int32_t vqdmulhs_s32(int32_t a, int32_t b)
+ case ARM64_INTRIN_VQDMULLH_LANE_S16: // SQDMULL Sd,Hn,Vm.H[lane] int32_t vqdmullh_lane_s16(int16_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULLH_LANEQ_S16: // SQDMULL Sd,Hn,Vm.H[lane] int32_t vqdmullh_laneq_s16(int16_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMULLH_S16: // SQDMULL Sd,Hn,Hm int32_t vqdmullh_s16(int16_t a, int16_t b)
+ case ARM64_INTRIN_VQMOVND_S64: // SQXTN Sd,Dn int32_t vqmovnd_s64(int64_t a)
+ case ARM64_INTRIN_VQMOVND_U64: // UQXTN Sd,Dn uint32_t vqmovnd_u64(uint64_t a)
+ case ARM64_INTRIN_VQMOVUND_S64: // SQXTUN Sd,Dn uint32_t vqmovund_s64(int64_t a)
+ case ARM64_INTRIN_VQNEGS_S32: // SQNEG Sd,Sn int32_t vqnegs_s32(int32_t a)
+ case ARM64_INTRIN_VQRDMLAHS_LANE_S32: // SQRDMLAH Sd,Sn,Vm.S[lane] int32_t vqrdmlahs_lane_s32(int32_t a, int32_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAHS_LANEQ_S32: // SQRDMLAH Sd,Sn,Vm.S[lane] int32_t vqrdmlahs_laneq_s32(int32_t a, int32_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAHS_S32: // SQRDMLSH Sd,Sn,Sm int32_t vqrdmlahs_s32(int32_t a, int32_t b, int32_t c)
+ case ARM64_INTRIN_VQRDMLSHS_LANE_S32: // SQRDMLSH Sd,Sn,Vm.S[lane] int32_t vqrdmlshs_lane_s32(int32_t a, int32_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHS_LANEQ_S32: // SQRDMLSH Sd,Sn,Vm.S[lane] int32_t vqrdmlshs_laneq_s32(int32_t a, int32_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSHS_S32: // SQRDMLSH Sd,Sn,Sm int32_t vqrdmlshs_s32(int32_t a, int32_t b, int32_t c)
+ case ARM64_INTRIN_VQRDMULHS_LANE_S32: // SQRDMULH Sd,Sn,Vm.S[lane] int32_t vqrdmulhs_lane_s32(int32_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHS_LANEQ_S32: // SQRDMULH Sd,Sn,Vm.S[lane] int32_t vqrdmulhs_laneq_s32(int32_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULHS_S32: // SQRDMULH Sd,Sn,Sm int32_t vqrdmulhs_s32(int32_t a, int32_t b)
+ case ARM64_INTRIN_VQRSHLS_S32: // SQRSHL Sd,Sn,Sm int32_t vqrshls_s32(int32_t a, int32_t b)
+ case ARM64_INTRIN_VQRSHLS_U32: // UQRSHL Sd,Sn,Sm uint32_t vqrshls_u32(uint32_t a, int32_t b)
+ case ARM64_INTRIN_VQRSHRND_N_S64: // SQRSHRN Sd,Dn,#n int32_t vqrshrnd_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VQRSHRND_N_U64: // UQRSHRN Sd,Dn,#n uint32_t vqrshrnd_n_u64(uint64_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUND_N_S64: // SQRSHRUN Sd,Dn,#n uint32_t vqrshrund_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VQSHLS_N_S32: // SQSHL Sd,Sn,#n int32_t vqshls_n_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VQSHLS_N_U32: // UQSHL Sd,Sn,#n uint32_t vqshls_n_u32(uint32_t a, const int n)
+ case ARM64_INTRIN_VQSHLS_S32: // SQSHL Sd,Sn,Sm int32_t vqshls_s32(int32_t a, int32_t b)
+ case ARM64_INTRIN_VQSHLS_U32: // UQSHL Sd,Sn,Sm uint32_t vqshls_u32(uint32_t a, int32_t b)
+ case ARM64_INTRIN_VQSHLUS_N_S32: // SQSHLU Sd,Sn,#n uint32_t vqshlus_n_s32(int32_t a, const int n)
+ case ARM64_INTRIN_VQSHRND_N_S64: // SQSHRN Sd,Dn,#n int32_t vqshrnd_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VQSHRND_N_U64: // UQSHRN Sd,Dn,#n uint32_t vqshrnd_n_u64(uint64_t a, const int n)
+ case ARM64_INTRIN_VQSHRUND_N_S64: // SQSHRUN Sd,Dn,#n uint32_t vqshrund_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VQSUBS_S32: // SQSUB Sd,Sn,Sm int32_t vqsubs_s32(int32_t a, int32_t b)
+ case ARM64_INTRIN_VQSUBS_U32: // UQSUB Sd,Sn,Sm uint32_t vqsubs_u32(uint32_t a, uint32_t b)
+ case ARM64_INTRIN_VSHA1H_U32: // SHA1H Sd,Sn uint32_t vsha1h_u32(uint32_t hash_e)
+ case ARM64_INTRIN_VSQADDS_U32: // USQADD Sd,Sn uint32_t vsqadds_u32(uint32_t a, int32_t b)
+ case ARM64_INTRIN_VUQADDS_S32: // SUQADD Sd,Sn int32_t vuqadds_s32(int32_t a, uint32_t b)
+ return {Type::IntegerType(4, false)};
+ case ARM64_INTRIN_VABA_S16: // SABA Vd.4H,Vn.4H,Vm.4H int16x4_t vaba_s16(int16x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VABA_S32: // SABA Vd.2S,Vn.2S,Vm.2S int32x2_t vaba_s32(int32x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VABA_S8: // SABA Vd.8B,Vn.8B,Vm.8B int8x8_t vaba_s8(int8x8_t a, int8x8_t b, int8x8_t c)
+ case ARM64_INTRIN_VABA_U16: // UABA Vd.4H,Vn.4H,Vm.4H uint16x4_t vaba_u16(uint16x4_t a, uint16x4_t b, uint16x4_t c)
+ case ARM64_INTRIN_VABA_U32: // UABA Vd.2S,Vn.2S,Vm.2S uint32x2_t vaba_u32(uint32x2_t a, uint32x2_t b, uint32x2_t c)
+ case ARM64_INTRIN_VABA_U8: // UABA Vd.8B,Vn.8B,Vm.8B uint8x8_t vaba_u8(uint8x8_t a, uint8x8_t b, uint8x8_t c)
+ case ARM64_INTRIN_VABD_S16: // SABD Vd.4H,Vn.4H,Vm.4H int16x4_t vabd_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VABD_S32: // SABD Vd.2S,Vn.2S,Vm.2S int32x2_t vabd_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VABD_S8: // SABD Vd.8B,Vn.8B,Vm.8B int8x8_t vabd_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VABD_U16: // UABD Vd.4H,Vn.4H,Vm.4H uint16x4_t vabd_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VABD_U32: // UABD Vd.2S,Vn.2S,Vm.2S uint32x2_t vabd_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VABD_U8: // UABD Vd.8B,Vn.8B,Vm.8B uint8x8_t vabd_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VABS_S16: // ABS Vd.4H,Vn.4H int16x4_t vabs_s16(int16x4_t a)
+ case ARM64_INTRIN_VABS_S32: // ABS Vd.2S,Vn.2S int32x2_t vabs_s32(int32x2_t a)
+ case ARM64_INTRIN_VABS_S64: // ABS Dd,Dn int64x1_t vabs_s64(int64x1_t a)
+ case ARM64_INTRIN_VABS_S8: // ABS Vd.8B,Vn.8B int8x8_t vabs_s8(int8x8_t a)
+ case ARM64_INTRIN_VABSD_S64: // ABS Dd,Dn int64_t vabsd_s64(int64_t a)
+ case ARM64_INTRIN_VADD_P16: // EOR Vd.8B,Vn.8B,Vm.8B poly16x4_t vadd_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VADD_P64: // EOR Vd.8B,Vn.8B,Vm.8B poly64x1_t vadd_p64(poly64x1_t a, poly64x1_t b)
+ case ARM64_INTRIN_VADD_P8: // EOR Vd.8B,Vn.8B,Vm.8B poly8x8_t vadd_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VADD_S16: // ADD Vd.4H,Vn.4H,Vm.4H int16x4_t vadd_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VADD_S32: // ADD Vd.2S,Vn.2S,Vm.2S int32x2_t vadd_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VADD_S64: // ADD Dd,Dn,Dm int64x1_t vadd_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VADD_S8: // ADD Vd.8B,Vn.8B,Vm.8B int8x8_t vadd_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VADD_U16: // ADD Vd.4H,Vn.4H,Vm.4H uint16x4_t vadd_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VADD_U32: // ADD Vd.2S,Vn.2S,Vm.2S uint32x2_t vadd_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VADD_U64: // ADD Dd,Dn,Dm uint64x1_t vadd_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VADD_U8: // ADD Vd.8B,Vn.8B,Vm.8B uint8x8_t vadd_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VADDD_S64: // ADD Dd,Dn,Dm int64_t vaddd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VADDD_U64: // ADD Dd,Dn,Dm uint64_t vaddd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VADDHN_S16: // ADDHN Vd.8B,Vn.8H,Vm.8H int8x8_t vaddhn_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VADDHN_S32: // ADDHN Vd.4H,Vn.4S,Vm.4S int16x4_t vaddhn_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VADDHN_S64: // ADDHN Vd.2S,Vn.2D,Vm.2D int32x2_t vaddhn_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VADDHN_U16: // ADDHN Vd.8B,Vn.8H,Vm.8H uint8x8_t vaddhn_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VADDHN_U32: // ADDHN Vd.4H,Vn.4S,Vm.4S uint16x4_t vaddhn_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VADDHN_U64: // ADDHN Vd.2S,Vn.2D,Vm.2D uint32x2_t vaddhn_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VADDLV_S32: // SADDLP Vd.1D,Vn.2S int64_t vaddlv_s32(int32x2_t a)
+ case ARM64_INTRIN_VADDLV_U32: // UADDLP Vd.1D,Vn.2S uint64_t vaddlv_u32(uint32x2_t a)
+ case ARM64_INTRIN_VADDLVQ_S32: // SADDLV Dd,Vn.4S int64_t vaddlvq_s32(int32x4_t a)
+ case ARM64_INTRIN_VADDLVQ_U32: // UADDLV Dd,Vn.4S uint64_t vaddlvq_u32(uint32x4_t a)
+ case ARM64_INTRIN_VADDVQ_S64: // ADDP Dd,Vn.2D int64_t vaddvq_s64(int64x2_t a)
+ case ARM64_INTRIN_VADDVQ_U64: // ADDP Dd,Vn.2D uint64_t vaddvq_u64(uint64x2_t a)
+ case ARM64_INTRIN_VAND_S16: // AND Vd.8B,Vn.8B,Vm.8B int16x4_t vand_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VAND_S32: // AND Vd.8B,Vn.8B,Vm.8B int32x2_t vand_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VAND_S8: // AND Vd.8B,Vn.8B,Vm.8B int8x8_t vand_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VAND_U16: // AND Vd.8B,Vn.8B,Vm.8B uint16x4_t vand_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VAND_U32: // AND Vd.8B,Vn.8B,Vm.8B uint32x2_t vand_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VAND_U64: // AND Vd.8B,Vn.8B,Vm.8B uint64x1_t vand_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VAND_U8: // AND Vd.8B,Vn.8B,Vm.8B uint8x8_t vand_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VBIC_S16: // BIC Vd.8B,Vn.8B,Vm.8B int16x4_t vbic_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VBIC_S32: // BIC Vd.8B,Vn.8B,Vm.8B int32x2_t vbic_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VBIC_S64: // BIC Vd.8B,Vn.8B,Vm.8B int64x1_t vbic_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VBIC_S8: // BIC Vd.8B,Vn.8B,Vm.8B int8x8_t vbic_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VBIC_U16: // BIC Vd.8B,Vn.8B,Vm.8B uint16x4_t vbic_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VBIC_U32: // BIC Vd.8B,Vn.8B,Vm.8B uint32x2_t vbic_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VBIC_U64: // BIC Vd.8B,Vn.8B,Vm.8B uint64x1_t vbic_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VBIC_U8: // BIC Vd.8B,Vn.8B,Vm.8B uint8x8_t vbic_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VBSL_P16: // BSL Vd.8B,Vn.8B,Vm.8B poly16x4_t vbsl_p16(uint16x4_t a, poly16x4_t b, poly16x4_t c)
+ case ARM64_INTRIN_VBSL_P64: // BSL Vd.8B,Vn.8B,Vm.8B poly64x1_t vbsl_p64(poly64x1_t a, poly64x1_t b, poly64x1_t c)
+ case ARM64_INTRIN_VBSL_P8: // BSL Vd.8B,Vn.8B,Vm.8B poly8x8_t vbsl_p8(uint8x8_t a, poly8x8_t b, poly8x8_t c)
+ case ARM64_INTRIN_VBSL_S16: // BSL Vd.8B,Vn.8B,Vm.8B int16x4_t vbsl_s16(uint16x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VBSL_S32: // BSL Vd.8B,Vn.8B,Vm.8B int32x2_t vbsl_s32(uint32x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VBSL_S64: // BSL Vd.8B,Vn.8B,Vm.8B int64x1_t vbsl_s64(uint64x1_t a, int64x1_t b, int64x1_t c)
+ case ARM64_INTRIN_VBSL_S8: // BSL Vd.8B,Vn.8B,Vm.8B int8x8_t vbsl_s8(uint8x8_t a, int8x8_t b, int8x8_t c)
+ case ARM64_INTRIN_VBSL_U16: // BSL Vd.8B,Vn.8B,Vm.8B uint16x4_t vbsl_u16(uint16x4_t a, uint16x4_t b, uint16x4_t c)
+ case ARM64_INTRIN_VBSL_U32: // BSL Vd.8B,Vn.8B,Vm.8B uint32x2_t vbsl_u32(uint32x2_t a, uint32x2_t b, uint32x2_t c)
+ case ARM64_INTRIN_VBSL_U64: // BSL Vd.8B,Vn.8B,Vm.8B uint64x1_t vbsl_u64(uint64x1_t a, uint64x1_t b, uint64x1_t c)
+ case ARM64_INTRIN_VBSL_U8: // BSL Vd.8B,Vn.8B,Vm.8B uint8x8_t vbsl_u8(uint8x8_t a, uint8x8_t b, uint8x8_t c)
+ case ARM64_INTRIN_VCAGE_F16: // FACGE Vd.4H,Vn.4H,Vm.4H uint16x4_t vcage_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCAGE_F32: // FACGE Vd.2S,Vn.2S,Vm.2S uint32x2_t vcage_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCAGE_F64: // FACGE Dd,Dn,Dm uint64x1_t vcage_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCAGED_F64: // FACGE Dd,Dn,Dm uint64_t vcaged_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCAGT_F16: // FACGT Vd.4H,Vn.4H,Vm.4H uint16x4_t vcagt_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCAGT_F32: // FACGT Vd.2S,Vn.2S,Vm.2S uint32x2_t vcagt_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCAGT_F64: // FACGT Dd,Dn,Dm uint64x1_t vcagt_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCAGTD_F64: // FACGT Dd,Dn,Dm uint64_t vcagtd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCALE_F16: // FACGE Vd.4H,Vn.4H,Vm.4H uint16x4_t vcale_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCALE_F32: // FACGE Vd.2S,Vm.2S,Vn.2S uint32x2_t vcale_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCALE_F64: // FACGE Dd,Dm,Dn uint64x1_t vcale_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCALED_F64: // FACGE Dd,Dm,Dn uint64_t vcaled_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCALT_F16: // FACGT Vd.4H,Vn.4H,Vm.4H uint16x4_t vcalt_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCALT_F32: // FACGT Vd.2S,Vm.2S,Vn.2S uint32x2_t vcalt_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCALT_F64: // FACGT Dd,Dm,Dn uint64x1_t vcalt_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCALTD_F64: // FACGT Dd,Dm,Dn uint64_t vcaltd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCEQ_F16: // FCMEQ Vd.4H,Vn.4H,Vm.4H uint16x4_t vceq_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCEQ_F32: // FCMEQ Vd.2S,Vn.2S,Vm.2S uint32x2_t vceq_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCEQ_F64: // FCMEQ Dd,Dn,Dm uint64x1_t vceq_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCEQ_P64: // CMEQ Dd,Dn,Dm uint64x1_t vceq_p64(poly64x1_t a, poly64x1_t b)
+ case ARM64_INTRIN_VCEQ_P8: // CMEQ Vd.8B,Vn.8B,Vm.8B uint8x8_t vceq_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VCEQ_S16: // CMEQ Vd.4H,Vn.4H,Vm.4H uint16x4_t vceq_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VCEQ_S32: // CMEQ Vd.2S,Vn.2S,Vm.2S uint32x2_t vceq_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VCEQ_S64: // CMEQ Dd,Dn,Dm uint64x1_t vceq_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VCEQ_S8: // CMEQ Vd.8B,Vn.8B,Vm.8B uint8x8_t vceq_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VCEQ_U16: // CMEQ Vd.4H,Vn.4H,Vm.4H uint16x4_t vceq_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VCEQ_U32: // CMEQ Vd.2S,Vn.2S,Vm.2S uint32x2_t vceq_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VCEQ_U64: // CMEQ Dd,Dn,Dm uint64x1_t vceq_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VCEQ_U8: // CMEQ Vd.8B,Vn.8B,Vm.8B uint8x8_t vceq_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VCEQD_F64: // FCMEQ Dd,Dn,Dm uint64_t vceqd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCEQD_S64: // CMEQ Dd,Dn,Dm uint64_t vceqd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VCEQD_U64: // CMEQ Dd,Dn,Dm uint64_t vceqd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VCEQZ_F16: // FCMEQ Vd.4H,Vn.4H,#0 uint16x4_t vceqz_f16(float16x4_t a)
+ case ARM64_INTRIN_VCEQZ_F32: // FCMEQ Vd.2S,Vn.2S,#0 uint32x2_t vceqz_f32(float32x2_t a)
+ case ARM64_INTRIN_VCEQZ_F64: // FCMEQ Dd,Dn,#0 uint64x1_t vceqz_f64(float64x1_t a)
+ case ARM64_INTRIN_VCEQZ_P64: // CMEQ Dd,Dn,#0 uint64x1_t vceqz_p64(poly64x1_t a)
+ case ARM64_INTRIN_VCEQZ_P8: // CMEQ Vd.8B,Vn.8B,#0 uint8x8_t vceqz_p8(poly8x8_t a)
+ case ARM64_INTRIN_VCEQZ_S16: // CMEQ Vd.4H,Vn.4H,#0 uint16x4_t vceqz_s16(int16x4_t a)
+ case ARM64_INTRIN_VCEQZ_S32: // CMEQ Vd.2S,Vn.2S,#0 uint32x2_t vceqz_s32(int32x2_t a)
+ case ARM64_INTRIN_VCEQZ_S64: // CMEQ Dd,Dn,#0 uint64x1_t vceqz_s64(int64x1_t a)
+ case ARM64_INTRIN_VCEQZ_S8: // CMEQ Vd.8B,Vn.8B,#0 uint8x8_t vceqz_s8(int8x8_t a)
+ case ARM64_INTRIN_VCEQZ_U16: // CMEQ Vd.4H,Vn.4H,#0 uint16x4_t vceqz_u16(uint16x4_t a)
+ case ARM64_INTRIN_VCEQZ_U32: // CMEQ Vd.2S,Vn.2S,#0 uint32x2_t vceqz_u32(uint32x2_t a)
+ case ARM64_INTRIN_VCEQZ_U64: // CMEQ Dd,Dn,#0 uint64x1_t vceqz_u64(uint64x1_t a)
+ case ARM64_INTRIN_VCEQZ_U8: // CMEQ Vd.8B,Vn.8B,#0 uint8x8_t vceqz_u8(uint8x8_t a)
+ case ARM64_INTRIN_VCEQZD_F64: // FCMEQ Dd,Dn,#0 uint64_t vceqzd_f64(float64_t a)
+ case ARM64_INTRIN_VCEQZD_S64: // CMEQ Dd,Dn,#0 uint64_t vceqzd_s64(int64_t a)
+ case ARM64_INTRIN_VCEQZD_U64: // CMEQ Dd,Dn,#0 uint64_t vceqzd_u64(uint64_t a)
+ case ARM64_INTRIN_VCGE_F16: // FCMGE Vd.4H,Vn.4H,Vm.4H uint16x4_t vcge_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCGE_F32: // FCMGE Vd.2S,Vm.2S,Vn.2S uint32x2_t vcge_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCGE_F64: // FCMGE Dd,Dn,Dm uint64x1_t vcge_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCGE_S16: // CMGE Vd.4H,Vm.4H,Vn.4H uint16x4_t vcge_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VCGE_S32: // CMGE Vd.2S,Vm.2S,Vn.2S uint32x2_t vcge_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VCGE_S64: // CMGE Dd,Dn,Dm uint64x1_t vcge_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VCGE_S8: // CMGE Vd.8B,Vm.8B,Vn.8B uint8x8_t vcge_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VCGE_U16: // CMHS Vd.4H,Vm.4H,Vn.4H uint16x4_t vcge_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VCGE_U32: // CMHS Vd.2S,Vm.2S,Vn.2S uint32x2_t vcge_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VCGE_U64: // CMHS Dd,Dn,Dm uint64x1_t vcge_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VCGE_U8: // CMHS Vd.8B,Vm.8B,Vn.8B uint8x8_t vcge_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VCGED_F64: // FCMGE Dd,Dn,Dm uint64_t vcged_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCGED_S64: // CMGE Dd,Dn,Dm uint64_t vcged_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VCGED_U64: // CMHS Dd,Dn,Dm uint64_t vcged_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VCGEZ_F16: // FCMGE Vd.4H,Vn.4H,#0 uint16x4_t vcgez_f16(float16x4_t a)
+ case ARM64_INTRIN_VCGEZ_F32: // FCMGE Vd.2S,Vn.2S,#0 uint32x2_t vcgez_f32(float32x2_t a)
+ case ARM64_INTRIN_VCGEZ_F64: // FCMGE Dd,Dn,#0 uint64x1_t vcgez_f64(float64x1_t a)
+ case ARM64_INTRIN_VCGEZ_S16: // CMGE Vd.4H,Vn.4H,#0 uint16x4_t vcgez_s16(int16x4_t a)
+ case ARM64_INTRIN_VCGEZ_S32: // CMGE Vd.2S,Vn.2S,#0 uint32x2_t vcgez_s32(int32x2_t a)
+ case ARM64_INTRIN_VCGEZ_S64: // CMGE Dd,Dn,#0 uint64x1_t vcgez_s64(int64x1_t a)
+ case ARM64_INTRIN_VCGEZ_S8: // CMGE Vd.8B,Vn.8B,#0 uint8x8_t vcgez_s8(int8x8_t a)
+ case ARM64_INTRIN_VCGEZD_F64: // FCMGE Dd,Dn,#0 uint64_t vcgezd_f64(float64_t a)
+ case ARM64_INTRIN_VCGEZD_S64: // CMGE Dd,Dn,#0 uint64_t vcgezd_s64(int64_t a)
+ case ARM64_INTRIN_VCGT_F16: // FCMGT Vd.4H,Vn.4H,Vm.4H uint16x4_t vcgt_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCGT_F32: // FCMGT Vd.2S,Vn.2S,Vm.2S uint32x2_t vcgt_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCGT_F64: // FCMGT Dd,Dn,Dm uint64x1_t vcgt_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCGT_S16: // CMGT Vd.4H,Vn.4H,Vm.4H uint16x4_t vcgt_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VCGT_S32: // CMGT Vd.2S,Vn.2S,Vm.2S uint32x2_t vcgt_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VCGT_S64: // CMGT Dd,Dn,Dm uint64x1_t vcgt_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VCGT_S8: // CMGT Vd.8B,Vn.8B,Vm.8B uint8x8_t vcgt_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VCGT_U16: // CMHI Vd.4H,Vn.4H,Vm.4H uint16x4_t vcgt_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VCGT_U32: // CMHI Vd.2S,Vn.2S,Vm.2S uint32x2_t vcgt_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VCGT_U64: // CMHI Dd,Dn,Dm uint64x1_t vcgt_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VCGT_U8: // CMHI Vd.8B,Vn.8B,Vm.8B uint8x8_t vcgt_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VCGTD_F64: // FCMGT Dd,Dn,Dm uint64_t vcgtd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCGTD_S64: // CMGT Dd,Dn,Dm uint64_t vcgtd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VCGTD_U64: // CMHI Dd,Dn,Dm uint64_t vcgtd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VCGTZ_F16: // FCMGT Vd.4H,Vn.4H,#0 uint16x4_t vcgtz_f16(float16x4_t a)
+ case ARM64_INTRIN_VCGTZ_F32: // FCMGT Vd.2S,Vn.2S,#0 uint32x2_t vcgtz_f32(float32x2_t a)
+ case ARM64_INTRIN_VCGTZ_F64: // FCMGT Dd,Dn,#0 uint64x1_t vcgtz_f64(float64x1_t a)
+ case ARM64_INTRIN_VCGTZ_S16: // CMGT Vd.4H,Vn.4H,#0 uint16x4_t vcgtz_s16(int16x4_t a)
+ case ARM64_INTRIN_VCGTZ_S32: // CMGT Vd.2S,Vn.2S,#0 uint32x2_t vcgtz_s32(int32x2_t a)
+ case ARM64_INTRIN_VCGTZ_S64: // CMGT Dd,Dn,#0 uint64x1_t vcgtz_s64(int64x1_t a)
+ case ARM64_INTRIN_VCGTZ_S8: // CMGT Vd.8B,Vn.8B,#0 uint8x8_t vcgtz_s8(int8x8_t a)
+ case ARM64_INTRIN_VCGTZD_F64: // FCMGT Dd,Dn,#0 uint64_t vcgtzd_f64(float64_t a)
+ case ARM64_INTRIN_VCGTZD_S64: // CMGT Dd,Dn,#0 uint64_t vcgtzd_s64(int64_t a)
+ case ARM64_INTRIN_VCLE_F16: // FCMGE Vd.4H,Vn.4H,Vm.4H uint16x4_t vcle_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCLE_F32: // FCMGE Vd.2S,Vm.2S,Vn.2S uint32x2_t vcle_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCLE_F64: // FCMGE Dd,Dm,Dn uint64x1_t vcle_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCLE_S16: // CMGE Vd.4H,Vm.4H,Vn.4H uint16x4_t vcle_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VCLE_S32: // CMGE Vd.2S,Vm.2S,Vn.2S uint32x2_t vcle_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VCLE_S64: // CMGE Dd,Dm,Dn uint64x1_t vcle_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VCLE_S8: // CMGE Vd.8B,Vm.8B,Vn.8B uint8x8_t vcle_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VCLE_U16: // CMHS Vd.4H,Vm.4H,Vn.4H uint16x4_t vcle_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VCLE_U32: // CMHS Vd.2S,Vm.2S,Vn.2S uint32x2_t vcle_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VCLE_U64: // CMHS Dd,Dm,Dn uint64x1_t vcle_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VCLE_U8: // CMHS Vd.8B,Vm.8B,Vn.8B uint8x8_t vcle_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VCLED_F64: // FCMGE Dd,Dm,Dn uint64_t vcled_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCLED_S64: // CMGE Dd,Dm,Dn uint64_t vcled_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VCLED_U64: // CMHS Dd,Dm,Dn uint64_t vcled_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VCLEZ_F16: // FCMLE Vd.4H,Vn.4H,#0 uint16x4_t vclez_f16(float16x4_t a)
+ case ARM64_INTRIN_VCLEZ_F32: // CMLE Vd.2S,Vn.2S,#0 uint32x2_t vclez_f32(float32x2_t a)
+ case ARM64_INTRIN_VCLEZ_F64: // FCMLE Dd,Dn,#0 uint64x1_t vclez_f64(float64x1_t a)
+ case ARM64_INTRIN_VCLEZ_S16: // CMLE Vd.4H,Vn.4H,#0 uint16x4_t vclez_s16(int16x4_t a)
+ case ARM64_INTRIN_VCLEZ_S32: // CMLE Vd.2S,Vn.2S,#0 uint32x2_t vclez_s32(int32x2_t a)
+ case ARM64_INTRIN_VCLEZ_S64: // CMLE Dd,Dn,#0 uint64x1_t vclez_s64(int64x1_t a)
+ case ARM64_INTRIN_VCLEZ_S8: // CMLE Vd.8B,Vn.8B,#0 uint8x8_t vclez_s8(int8x8_t a)
+ case ARM64_INTRIN_VCLEZD_F64: // FCMLE Dd,Dn,#0 uint64_t vclezd_f64(float64_t a)
+ case ARM64_INTRIN_VCLEZD_S64: // CMLE Dd,Dn,#0 uint64_t vclezd_s64(int64_t a)
+ case ARM64_INTRIN_VCLS_S16: // CLS Vd.4H,Vn.4H int16x4_t vcls_s16(int16x4_t a)
+ case ARM64_INTRIN_VCLS_S32: // CLS Vd.2S,Vn.2S int32x2_t vcls_s32(int32x2_t a)
+ case ARM64_INTRIN_VCLS_S8: // CLS Vd.8B,Vn.8B int8x8_t vcls_s8(int8x8_t a)
+ case ARM64_INTRIN_VCLS_U16: // CLS Vd.4H,Vn.4H int16x4_t vcls_u16(uint16x4_t a)
+ case ARM64_INTRIN_VCLS_U32: // CLS Vd.2S,Vn.2S int32x2_t vcls_u32(uint32x2_t a)
+ case ARM64_INTRIN_VCLS_U8: // CLS Vd.8B,Vn.8B int8x8_t vcls_u8(uint8x8_t a)
+ case ARM64_INTRIN_VCLT_F16: // FCMGT Vd.4H,Vn.4H,Vm.4H uint16x4_t vclt_f16(float16x4_t a, float16x4_t b)
+ case ARM64_INTRIN_VCLT_F32: // FCMGT Vd.2S,Vm.2S,Vn.2S uint32x2_t vclt_f32(float32x2_t a, float32x2_t b)
+ case ARM64_INTRIN_VCLT_F64: // FCMGT Dd,Dm,Dn uint64x1_t vclt_f64(float64x1_t a, float64x1_t b)
+ case ARM64_INTRIN_VCLT_S16: // CMGT Vd.4H,Vm.4H,Vn.4H uint16x4_t vclt_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VCLT_S32: // CMGT Vd.2S,Vm.2S,Vn.2S uint32x2_t vclt_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VCLT_S64: // CMGT Dd,Dm,Dn uint64x1_t vclt_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VCLT_S8: // CMGT Vd.8B,Vm.8B,Vn.8B uint8x8_t vclt_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VCLT_U16: // CMHI Vd.4H,Vm.4H,Vn.4H uint16x4_t vclt_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VCLT_U32: // CMHI Vd.2S,Vm.2S,Vn.2S uint32x2_t vclt_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VCLT_U64: // CMHI Dd,Dm,Dn uint64x1_t vclt_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VCLT_U8: // CMHI Vd.8B,Vm.8B,Vn.8B uint8x8_t vclt_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VCLTD_F64: // FCMGT Dd,Dm,Dn uint64_t vcltd_f64(float64_t a, float64_t b)
+ case ARM64_INTRIN_VCLTD_S64: // CMGT Dd,Dm,Dn uint64_t vcltd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VCLTD_U64: // CMHI Dd,Dm,Dn uint64_t vcltd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VCLTZ_F16: // FCMLT Vd.4H,Vn.4H,#0 uint16x4_t vcltz_f16(float16x4_t a)
+ case ARM64_INTRIN_VCLTZ_F32: // FCMLT Vd.2S,Vn.2S,#0 uint32x2_t vcltz_f32(float32x2_t a)
+ case ARM64_INTRIN_VCLTZ_F64: // FCMLT Dd,Dn,#0 uint64x1_t vcltz_f64(float64x1_t a)
+ case ARM64_INTRIN_VCLTZ_S16: // CMLT Vd.4H,Vn.4H,#0 uint16x4_t vcltz_s16(int16x4_t a)
+ case ARM64_INTRIN_VCLTZ_S32: // CMLT Vd.2S,Vn.2S,#0 uint32x2_t vcltz_s32(int32x2_t a)
+ case ARM64_INTRIN_VCLTZ_S64: // CMLT Dd,Dn,#0 uint64x1_t vcltz_s64(int64x1_t a)
+ case ARM64_INTRIN_VCLTZ_S8: // CMLT Vd.8B,Vn.8B,#0 uint8x8_t vcltz_s8(int8x8_t a)
+ case ARM64_INTRIN_VCLTZD_F64: // FCMLT Dd,Dn,#0 uint64_t vcltzd_f64(float64_t a)
+ case ARM64_INTRIN_VCLTZD_S64: // CMLT Dd,Dn,#0 uint64_t vcltzd_s64(int64_t a)
+ case ARM64_INTRIN_VCLZ_S16: // CLZ Vd.4H,Vn.4H int16x4_t vclz_s16(int16x4_t a)
+ case ARM64_INTRIN_VCLZ_S32: // CLZ Vd.2S,Vn.2S int32x2_t vclz_s32(int32x2_t a)
+ case ARM64_INTRIN_VCLZ_S8: // CLZ Vd.8B,Vn.8B int8x8_t vclz_s8(int8x8_t a)
+ case ARM64_INTRIN_VCLZ_U16: // CLZ Vd.4H,Vn.4H uint16x4_t vclz_u16(uint16x4_t a)
+ case ARM64_INTRIN_VCLZ_U32: // CLZ Vd.2S,Vn.2S uint32x2_t vclz_u32(uint32x2_t a)
+ case ARM64_INTRIN_VCLZ_U8: // CLZ Vd.8B,Vn.8B uint8x8_t vclz_u8(uint8x8_t a)
+ case ARM64_INTRIN_VCNT_P8: // CNT Vd.8B,Vn.8B poly8x8_t vcnt_p8(poly8x8_t a)
+ case ARM64_INTRIN_VCNT_S8: // CNT Vd.8B,Vn.8B int8x8_t vcnt_s8(int8x8_t a)
+ case ARM64_INTRIN_VCNT_U8: // CNT Vd.8B,Vn.8B uint8x8_t vcnt_u8(uint8x8_t a)
+ case ARM64_INTRIN_VCOPY_LANE_P16: // INS Vd.H[lane1],Vn.H[lane2] poly16x4_t vcopy_lane_p16(poly16x4_t a, const int lane1, poly16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_P64: // DUP Dd,Vn.D[lane2] poly64x1_t vcopy_lane_p64(poly64x1_t a, const int lane1, poly64x1_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_P8: // INS Vd.B[lane1],Vn.B[lane2] poly8x8_t vcopy_lane_p8(poly8x8_t a, const int lane1, poly8x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_S16: // INS Vd.H[lane1],Vn.H[lane2] int16x4_t vcopy_lane_s16(int16x4_t a, const int lane1, int16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_S32: // INS Vd.S[lane1],Vn.S[lane2] int32x2_t vcopy_lane_s32(int32x2_t a, const int lane1, int32x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_S64: // DUP Dd,Vn.D[lane2] int64x1_t vcopy_lane_s64(int64x1_t a, const int lane1, int64x1_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_S8: // INS Vd.B[lane1],Vn.B[lane2] int8x8_t vcopy_lane_s8(int8x8_t a, const int lane1, int8x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_U16: // INS Vd.H[lane1],Vn.H[lane2] uint16x4_t vcopy_lane_u16(uint16x4_t a, const int lane1, uint16x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_U32: // INS Vd.S[lane1],Vn.S[lane2] uint32x2_t vcopy_lane_u32(uint32x2_t a, const int lane1, uint32x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_U64: // DUP Dd,Vn.D[lane2] uint64x1_t vcopy_lane_u64(uint64x1_t a, const int lane1, uint64x1_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANE_U8: // INS Vd.B[lane1],Vn.B[lane2] uint8x8_t vcopy_lane_u8(uint8x8_t a, const int lane1, uint8x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_P16: // INS Vd.H[lane1],Vn.H[lane2] poly16x4_t vcopy_laneq_p16(poly16x4_t a, const int lane1, poly16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_P64: // DUP Dd,Vn.D[lane2] poly64x1_t vcopy_laneq_p64(poly64x1_t a, const int lane1, poly64x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_P8: // INS Vd.B[lane1],Vn.B[lane2] poly8x8_t vcopy_laneq_p8(poly8x8_t a, const int lane1, poly8x16_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_S16: // INS Vd.H[lane1],Vn.H[lane2] int16x4_t vcopy_laneq_s16(int16x4_t a, const int lane1, int16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_S32: // INS Vd.S[lane1],Vn.S[lane2] int32x2_t vcopy_laneq_s32(int32x2_t a, const int lane1, int32x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_S64: // DUP Dd,Vn.D[lane2] int64x1_t vcopy_laneq_s64(int64x1_t a, const int lane1, int64x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_S8: // INS Vd.B[lane1],Vn.B[lane2] int8x8_t vcopy_laneq_s8(int8x8_t a, const int lane1, int8x16_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_U16: // INS Vd.H[lane1],Vn.H[lane2] uint16x4_t vcopy_laneq_u16(uint16x4_t a, const int lane1, uint16x8_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_U32: // INS Vd.S[lane1],Vn.S[lane2] uint32x2_t vcopy_laneq_u32(uint32x2_t a, const int lane1, uint32x4_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_U64: // DUP Dd,Vn.D[lane2] uint64x1_t vcopy_laneq_u64(uint64x1_t a, const int lane1, uint64x2_t b, const int lane2)
+ case ARM64_INTRIN_VCOPY_LANEQ_U8: // INS Vd.B[lane1],Vn.B[lane2] uint8x8_t vcopy_laneq_u8(uint8x8_t a, const int lane1, uint8x16_t b, const int lane2)
+ case ARM64_INTRIN_VCREATE_P16: // INS Vd.D[0],Xn poly16x4_t vcreate_p16(uint64_t a)
+ case ARM64_INTRIN_VCREATE_P64: // INS Vd.D[0],Xn poly64x1_t vcreate_p64(uint64_t a)
+ case ARM64_INTRIN_VCREATE_P8: // INS Vd.D[0],Xn poly8x8_t vcreate_p8(uint64_t a)
+ case ARM64_INTRIN_VCREATE_S16: // INS Vd.D[0],Xn int16x4_t vcreate_s16(uint64_t a)
+ case ARM64_INTRIN_VCREATE_S32: // INS Vd.D[0],Xn int32x2_t vcreate_s32(uint64_t a)
+ case ARM64_INTRIN_VCREATE_S64: // INS Vd.D[0],Xn int64x1_t vcreate_s64(uint64_t a)
+ case ARM64_INTRIN_VCREATE_S8: // INS Vd.D[0],Xn int8x8_t vcreate_s8(uint64_t a)
+ case ARM64_INTRIN_VCREATE_U16: // INS Vd.D[0],Xn uint16x4_t vcreate_u16(uint64_t a)
+ case ARM64_INTRIN_VCREATE_U32: // INS Vd.D[0],Xn uint32x2_t vcreate_u32(uint64_t a)
+ case ARM64_INTRIN_VCREATE_U64: // INS Vd.D[0],Xn uint64x1_t vcreate_u64(uint64_t a)
+ case ARM64_INTRIN_VCREATE_U8: // INS Vd.D[0],Xn uint8x8_t vcreate_u8(uint64_t a)
+ case ARM64_INTRIN_VCVT_N_S16_F16: // FCVTZS Vd.4H,Vn.4H,#n int16x4_t vcvt_n_s16_f16(float16x4_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_S32_F32: // FCVTZS Vd.2S,Vn.2S,#n int32x2_t vcvt_n_s32_f32(float32x2_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_S64_F64: // FCVTZS Dd,Dn,#n int64x1_t vcvt_n_s64_f64(float64x1_t a, const int n)
+ // case ARM64_INTRIN_VCVT_N_S64_F64: // FCVTZS Xd,Dn,#n int64x1_t vcvt_n_s64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_U16_F16: // FCVTZU Vd.4H,Vn.4H,#n uint16x4_t vcvt_n_u16_f16(float16x4_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_U32_F32: // FCVTZU Vd.2S,Vn.2S,#n uint32x2_t vcvt_n_u32_f32(float32x2_t a, const int n)
+ case ARM64_INTRIN_VCVT_N_U64_F64: // FCVTZU Dd,Dn,#n uint64x1_t vcvt_n_u64_f64(float64x1_t a, const int n)
+ // case ARM64_INTRIN_VCVT_N_U64_F64: // FCVTZU Xd,Dn,#n uint64x1_t vcvt_n_u64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVT_S16_F16: // FCVTZS Vd.4H,Vn.4H int16x4_t vcvt_s16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVT_S32_F32: // FCVTZS Vd.2S,Vn.2S int32x2_t vcvt_s32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVT_S64_F64: // FCVTZS Dd,Dn int64x1_t vcvt_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVT_S64_F64: // FCVTZS Xd,Dn int64x1_t vcvt_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVT_S64_F64: // FCVTZS Xd,Sn int64x1_t vcvt_s64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVT_U16_F16: // FCVTZS Vd.4H,Vn.4H uint16x4_t vcvt_u16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVT_U32_F32: // FCVTZU Vd.2S,Vn.2S uint32x2_t vcvt_u32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVT_U64_F32: // FCVTZU Xd,Sn uint64x1_t vcvt_u64_f32(float32x1_t a)
+ case ARM64_INTRIN_VCVT_U64_F64: // FCVTZU Xd,Dn uint64x1_t vcvt_u64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVT_U64_F64: // FCVTZU Xd,Sn uint64x1_t vcvt_u64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTA_N_S64_F64: // FCVTAS Xd,Dn,#n int64x1_t vcvta_n_s64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVTA_N_U64_F64: // FCVTAU Xd,Dn,#n uint64x1_t vcvta_n_u64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVTA_S16_F16: // FCVTAS Vd.4H,Vn.4H int16x4_t vcvta_s16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTA_S32_F32: // FCVTAS Vd.2S,Vn.2S int32x2_t vcvta_s32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTA_S64_F64: // FCVTAS Dd,Dn int64x1_t vcvta_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTA_S64_F64: // FCVTAS Xd,Dn int64x1_t vcvta_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTA_S64_F64: // FCVTAS Xd,Sn int64x1_t vcvta_s64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTA_U16_F16: // FCVTAU Vd.4H,Vn.4H uint16x4_t vcvta_u16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTA_U32_F32: // FCVTAU Vd.2S,Vn.2S uint32x2_t vcvta_u32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTA_U64_F64: // FCVTAU Dd,Dn uint64x1_t vcvta_u64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTA_U64_F64: // FCVTAU Xd,Dn uint64x1_t vcvta_u64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTA_U64_F64: // FCVTAU Xd,Sn uint64x1_t vcvta_u64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTAD_N_S64_F64: // FCVTAS Xd,Dn,#n int64_t vcvtad_n_s64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTAD_N_U64_F64: // FCVTAU Xd,Dn,#n uint64_t vcvtad_n_u64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTAD_S64_F64: // FCVTAS Dd,Dn int64_t vcvtad_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTAD_S64_F64: // FCVTAS Xd,Dn int64_t vcvtad_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTAD_S64_F64: // FCVTAS Xd,Sn int64_t vcvtad_s64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTAD_U64_F64: // FCVTAU Dd,Dn uint64_t vcvtad_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTAD_U64_F64: // FCVTAU Xd,Dn uint64_t vcvtad_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTAD_U64_F64: // FCVTAU Xd,Sn uint64_t vcvtad_u64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTD_N_S64_F64: // FCVTZS Dd,Dn,#n int64_t vcvtd_n_s64_f64(float64_t a, const int n)
+ // case ARM64_INTRIN_VCVTD_N_S64_F64: // FCVTZS Xd,Dn,#n int64_t vcvtd_n_s64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTD_N_U64_F64: // FCVTZU Dd,Dn,#n uint64_t vcvtd_n_u64_f64(float64_t a, const int n)
+ // case ARM64_INTRIN_VCVTD_N_U64_F64: // FCVTZU Xd,Dn,#n uint64_t vcvtd_n_u64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTD_S64_F64: // FCVTZS Dd,Dn int64_t vcvtd_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTD_S64_F64: // FCVTZS Xd,Dn int64_t vcvtd_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTD_S64_F64: // FCVTZS Xd,Sn int64_t vcvtd_s64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTD_U64_F64: // FCVTZU Dd,Dn uint64_t vcvtd_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTD_U64_F64: // FCVTZU Xd,Dn uint64_t vcvtd_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTD_U64_F64: // FCVTZU Xd,Sn uint64_t vcvtd_u64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTM_N_S64_F64: // FCVTMS Xd,Dn,#n int64x1_t vcvtm_n_s64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVTM_N_U64_F64: // FCVTMU Xd,Dn,#n uint64x1_t vcvtm_n_u64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVTM_S16_F16: // FCVTMS Vd.4H,Vn.4H int16x4_t vcvtm_s16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTM_S32_F32: // FCVTMS Vd.2S,Vn.2S int32x2_t vcvtm_s32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTM_S64_F64: // FCVTMS Dd,Dn int64x1_t vcvtm_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTM_S64_F64: // FCVTMS Xd,Dn int64x1_t vcvtm_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTM_S64_F64: // FCVTMS Xd,Sn int64x1_t vcvtm_s64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTM_U16_F16: // FCVTMU Vd.4H,Vn.4H uint16x4_t vcvtm_u16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTM_U32_F32: // FCVTMU Vd.2S,Vn.2S uint32x2_t vcvtm_u32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTM_U64_F64: // FCVTMU Dd,Dn uint64x1_t vcvtm_u64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTM_U64_F64: // FCVTMU Xd,Dn uint64x1_t vcvtm_u64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTM_U64_F64: // FCVTMU Xd,Sn uint64x1_t vcvtm_u64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTMD_N_S64_F64: // FCVTMS Xd,Dn,#n int64_t vcvtmd_n_s64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTMD_N_U64_F64: // FCVTMU Xd,Dn,#n uint64_t vcvtmd_n_u64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTMD_S64_F64: // FCVTMS Dd,Dn int64_t vcvtmd_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTMD_S64_F64: // FCVTMS Xd,Dn int64_t vcvtmd_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTMD_S64_F64: // FCVTMS Xd,Sn int64_t vcvtmd_s64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTMD_U64_F64: // FCVTMU Dd,Dn uint64_t vcvtmd_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTMD_U64_F64: // FCVTMU Xd,Dn uint64_t vcvtmd_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTMD_U64_F64: // FCVTMU Xd,Sn uint64_t vcvtmd_u64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTN_S16_F16: // FCVTNS Vd.4H,Vn.4H int16x4_t vcvtn_s16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTN_S32_F32: // FCVTNS Vd.2S,Vn.2S int32x2_t vcvtn_s32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTN_S64_F64: // FCVTNS Dd,Dn int64x1_t vcvtn_s64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTN_U16_F16: // FCVTNU Vd.4H,Vn.4H uint16x4_t vcvtn_u16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTN_U32_F32: // FCVTNU Vd.2S,Vn.2S uint32x2_t vcvtn_u32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTN_U64_F64: // FCVTNU Dd,Dn uint64x1_t vcvtn_u64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTND_S64_F64: // FCVTNS Dd,Dn int64_t vcvtnd_s64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTND_U64_F64: // FCVTNU Dd,Dn uint64_t vcvtnd_u64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTP_N_S64_F64: // FCVTPS Xd,Dn,#n int64x1_t vcvtp_n_s64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVTP_N_U64_F64: // FCVTPU Xd,Dn,#n uint64x1_t vcvtp_n_u64_f64(float64x1_t a, const int n)
+ case ARM64_INTRIN_VCVTP_S16_F16: // FCVTPS Vd.4H,Vn.4H int16x4_t vcvtp_s16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTP_S32_F32: // FCVTPS Vd.2S,Vn.2S int32x2_t vcvtp_s32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTP_S64_F64: // FCVTPS Dd,Dn int64x1_t vcvtp_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTP_S64_F64: // FCVTPS Xd,Dn int64x1_t vcvtp_s64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTP_S64_F64: // FCVTPS Xd,Sn int64x1_t vcvtp_s64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTP_U16_F16: // FCVTPU Vd.4H,Vn.4H uint16x4_t vcvtp_u16_f16(float16x4_t a)
+ case ARM64_INTRIN_VCVTP_U32_F32: // FCVTPU Vd.2S,Vn.2S uint32x2_t vcvtp_u32_f32(float32x2_t a)
+ case ARM64_INTRIN_VCVTP_U64_F64: // FCVTPU Xd,Dn uint64x1_t vcvtp_u64_f64(float64x1_t a)
+ // case ARM64_INTRIN_VCVTP_U64_F64: // FCVTPU Xd,Sn uint64x1_t vcvtp_u64_f64(float64x1_t a)
+ case ARM64_INTRIN_VCVTPD_N_S64_F64: // FCVTPS Xd,Dn,#n int64_t vcvtpd_n_s64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTPD_N_U64_F64: // FCVTPU Xd,Dn,#n uint64_t vcvtpd_n_u64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VCVTPD_S64_F64: // FCVTPS Dd,Dn int64_t vcvtpd_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTPD_S64_F64: // FCVTPS Xd,Dn int64_t vcvtpd_s64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTPD_S64_F64: // FCVTPS Xd,Sn int64_t vcvtpd_s64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTPD_U64_F64: // FCVTPU Dd,Dn uint64_t vcvtpd_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTPD_U64_F64: // FCVTPU Xd,Dn uint64_t vcvtpd_u64_f64(float64_t a)
+ // case ARM64_INTRIN_VCVTPD_U64_F64: // FCVTPU Xd,Sn uint64_t vcvtpd_u64_f64(float64_t a)
+ case ARM64_INTRIN_VCVTS_N_U64_F32: // FCVTZU Xd,Sn,#n uint64_t vcvts_n_u64_f32(float32_t a, const int n)
+ case ARM64_INTRIN_VCVTS_N_U64_F64: // FCVTZU Xd,Dn,#n uint64_t vcvts_n_u64_f64(float64_t a, const int n)
+ case ARM64_INTRIN_VDOT_LANE_S32: // SDOT Vd.2S,Vn.8B,Vm.4B[lane] int32x2_t vdot_lane_s32(int32x2_t r, int8x8_t a, int8x8_t b, const int lane)
+ case ARM64_INTRIN_VDOT_LANE_U32: // UDOT Vd.2S,Vn.8B,Vm.4B[lane] uint32x2_t vdot_lane_u32(uint32x2_t r, uint8x8_t a, uint8x8_t b, const int lane)
+ case ARM64_INTRIN_VDOT_LANEQ_S32: // SDOT Vd.2S,Vn.8B,Vm.4B[lane] int32x2_t vdot_laneq_s32(int32x2_t r, int8x8_t a, int8x16_t b, const int lane)
+ case ARM64_INTRIN_VDOT_LANEQ_U32: // UDOT Vd.2S,Vn.8B,Vm.4B[lane] uint32x2_t vdot_laneq_u32(uint32x2_t r, uint8x8_t a, uint8x16_t b, const int lane)
+ case ARM64_INTRIN_VDOT_S32: // SDOT Vd.2S,Vn.8B,Vm.8B int32x2_t vdot_s32(int32x2_t r, int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VDOT_U32: // UDOT Vd.2S,Vn.8B,Vm.8B uint32x2_t vdot_u32(uint32x2_t r, uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VDUP_LANE_P16: // DUP Vd.4H,Vn.H[lane] poly16x4_t vdup_lane_p16(poly16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_P64: // DUP Dd,Vn.D[lane] poly64x1_t vdup_lane_p64(poly64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_P8: // DUP Vd.8B,Vn.B[lane] poly8x8_t vdup_lane_p8(poly8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_S16: // DUP Vd.4H,Vn.H[lane] int16x4_t vdup_lane_s16(int16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_S32: // DUP Vd.2S,Vn.S[lane] int32x2_t vdup_lane_s32(int32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_S64: // DUP Dd,Vn.D[lane] int64x1_t vdup_lane_s64(int64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_S8: // DUP Vd.8B,Vn.B[lane] int8x8_t vdup_lane_s8(int8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_U16: // DUP Vd.4H,Vn.H[lane] uint16x4_t vdup_lane_u16(uint16x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_U32: // DUP Vd.2S,Vn.S[lane] uint32x2_t vdup_lane_u32(uint32x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_U64: // DUP Dd,Vn.D[lane] uint64x1_t vdup_lane_u64(uint64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANE_U8: // DUP Vd.8B,Vn.B[lane] uint8x8_t vdup_lane_u8(uint8x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_P16: // DUP Vd.4H,Vn.H[lane] poly16x4_t vdup_laneq_p16(poly16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_P64: // DUP Dd,Vn.D[lane] poly64x1_t vdup_laneq_p64(poly64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_P8: // DUP Vd.8B,Vn.B[lane] poly8x8_t vdup_laneq_p8(poly8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_S16: // DUP Vd.4H,Vn.H[lane] int16x4_t vdup_laneq_s16(int16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_S32: // DUP Vd.2S,Vn.S[lane] int32x2_t vdup_laneq_s32(int32x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_S64: // DUP Dd,Vn.D[lane] int64x1_t vdup_laneq_s64(int64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_S8: // DUP Vd.8B,Vn.B[lane] int8x8_t vdup_laneq_s8(int8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_U16: // DUP Vd.4H,Vn.H[lane] uint16x4_t vdup_laneq_u16(uint16x8_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_U32: // DUP Vd.2S,Vn.S[lane] uint32x2_t vdup_laneq_u32(uint32x4_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_U64: // DUP Dd,Vn.D[lane] uint64x1_t vdup_laneq_u64(uint64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_LANEQ_U8: // DUP Vd.8B,Vn.B[lane] uint8x8_t vdup_laneq_u8(uint8x16_t vec, const int lane)
+ case ARM64_INTRIN_VDUP_N_P16: // DUP Vd.4H,rn poly16x4_t vdup_n_p16(poly16_t value)
+ case ARM64_INTRIN_VDUP_N_P64: // INS Vd.D[0],rn poly64x1_t vdup_n_p64(poly64_t value)
+ case ARM64_INTRIN_VDUP_N_P8: // DUP Vd.8B,rn poly8x8_t vdup_n_p8(poly8_t value)
+ case ARM64_INTRIN_VDUP_N_S16: // DUP Vd.4H,rn int16x4_t vdup_n_s16(int16_t value)
+ case ARM64_INTRIN_VDUP_N_S32: // DUP Vd.2S,rn int32x2_t vdup_n_s32(int32_t value)
+ case ARM64_INTRIN_VDUP_N_S64: // INS Vd.D[0],rn int64x1_t vdup_n_s64(int64_t value)
+ case ARM64_INTRIN_VDUP_N_S8: // DUP Vd.8B,rn int8x8_t vdup_n_s8(int8_t value)
+ case ARM64_INTRIN_VDUP_N_U16: // DUP Vd.4H,rn uint16x4_t vdup_n_u16(uint16_t value)
+ case ARM64_INTRIN_VDUP_N_U32: // DUP Vd.2S,rn uint32x2_t vdup_n_u32(uint32_t value)
+ case ARM64_INTRIN_VDUP_N_U64: // INS Vd.D[0],rn uint64x1_t vdup_n_u64(uint64_t value)
+ case ARM64_INTRIN_VDUP_N_U8: // DUP Vd.8B,rn uint8x8_t vdup_n_u8(uint8_t value)
+ case ARM64_INTRIN_VDUPD_LANE_S64: // DUP Dd,Vn.D[lane] int64_t vdupd_lane_s64(int64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUPD_LANE_U64: // DUP Dd,Vn.D[lane] uint64_t vdupd_lane_u64(uint64x1_t vec, const int lane)
+ case ARM64_INTRIN_VDUPD_LANEQ_S64: // DUP Dd,Vn.D[lane] int64_t vdupd_laneq_s64(int64x2_t vec, const int lane)
+ case ARM64_INTRIN_VDUPD_LANEQ_U64: // DUP Dd,Vn.D[lane] uint64_t vdupd_laneq_u64(uint64x2_t vec, const int lane)
+ case ARM64_INTRIN_VEOR_S16: // EOR Vd.8B,Vn.8B,Vm.8B int16x4_t veor_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VEOR_S32: // EOR Vd.8B,Vn.8B,Vm.8B int32x2_t veor_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VEOR_S64: // EOR Vd.8B,Vn.8B,Vm.8B int64x1_t veor_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VEOR_S8: // EOR Vd.8B,Vn.8B,Vm.8B int8x8_t veor_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VEOR_U16: // EOR Vd.8B,Vn.8B,Vm.8B uint16x4_t veor_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VEOR_U32: // EOR Vd.8B,Vn.8B,Vm.8B uint32x2_t veor_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VEOR_U64: // EOR Vd.8B,Vn.8B,Vm.8B uint64x1_t veor_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VEOR_U8: // EOR Vd.8B,Vn.8B,Vm.8B uint8x8_t veor_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VEXT_P16: // EXT Vd.8B,Vn.8B,Vm.8B,#n poly16x4_t vext_p16(poly16x4_t a, poly16x4_t b, const int n)
+ case ARM64_INTRIN_VEXT_P64: // EXT Vd.8B,Vn.8B,Vm.8B,#n poly64x1_t vext_p64(poly64x1_t a, poly64x1_t b, const int n)
+ case ARM64_INTRIN_VEXT_P8: // EXT Vd.8B,Vn.8B,Vm.8B,#n poly8x8_t vext_p8(poly8x8_t a, poly8x8_t b, const int n)
+ case ARM64_INTRIN_VEXT_S16: // EXT Vd.8B,Vn.8B,Vm.8B,#n int16x4_t vext_s16(int16x4_t a, int16x4_t b, const int n)
+ case ARM64_INTRIN_VEXT_S32: // EXT Vd.8B,Vn.8B,Vm.8B,#n int32x2_t vext_s32(int32x2_t a, int32x2_t b, const int n)
+ case ARM64_INTRIN_VEXT_S64: // EXT Vd.8B,Vn.8B,Vm.8B,#n int64x1_t vext_s64(int64x1_t a, int64x1_t b, const int n)
+ case ARM64_INTRIN_VEXT_S8: // EXT Vd.8B,Vn.8B,Vm.8B,#n int8x8_t vext_s8(int8x8_t a, int8x8_t b, const int n)
+ case ARM64_INTRIN_VEXT_U16: // EXT Vd.8B,Vn.8B,Vm.8B,#n uint16x4_t vext_u16(uint16x4_t a, uint16x4_t b, const int n)
+ case ARM64_INTRIN_VEXT_U32: // EXT Vd.8B,Vn.8B,Vm.8B,#n uint32x2_t vext_u32(uint32x2_t a, uint32x2_t b, const int n)
+ case ARM64_INTRIN_VEXT_U64: // EXT Vd.8B,Vn.8B,Vm.8B,#n uint64x1_t vext_u64(uint64x1_t a, uint64x1_t b, const int n)
+ case ARM64_INTRIN_VEXT_U8: // EXT Vd.8B,Vn.8B,Vm.8B,#n uint8x8_t vext_u8(uint8x8_t a, uint8x8_t b, const int n)
+ case ARM64_INTRIN_VGET_HIGH_P16: // DUP Vd.1D,Vn.D[1] poly16x4_t vget_high_p16(poly16x8_t a)
+ case ARM64_INTRIN_VGET_HIGH_P64: // DUP Vd.1D,Vn.D[1] poly64x1_t vget_high_p64(poly64x2_t a)
+ case ARM64_INTRIN_VGET_HIGH_P8: // DUP Vd.1D,Vn.D[1] poly8x8_t vget_high_p8(poly8x16_t a)
+ case ARM64_INTRIN_VGET_HIGH_S16: // DUP Vd.1D,Vn.D[1] int16x4_t vget_high_s16(int16x8_t a)
+ case ARM64_INTRIN_VGET_HIGH_S32: // DUP Vd.1D,Vn.D[1] int32x2_t vget_high_s32(int32x4_t a)
+ case ARM64_INTRIN_VGET_HIGH_S64: // DUP Vd.1D,Vn.D[1] int64x1_t vget_high_s64(int64x2_t a)
+ case ARM64_INTRIN_VGET_HIGH_S8: // DUP Vd.1D,Vn.D[1] int8x8_t vget_high_s8(int8x16_t a)
+ case ARM64_INTRIN_VGET_HIGH_U16: // DUP Vd.1D,Vn.D[1] uint16x4_t vget_high_u16(uint16x8_t a)
+ case ARM64_INTRIN_VGET_HIGH_U32: // DUP Vd.1D,Vn.D[1] uint32x2_t vget_high_u32(uint32x4_t a)
+ case ARM64_INTRIN_VGET_HIGH_U64: // DUP Vd.1D,Vn.D[1] uint64x1_t vget_high_u64(uint64x2_t a)
+ case ARM64_INTRIN_VGET_HIGH_U8: // DUP Vd.1D,Vn.D[1] uint8x8_t vget_high_u8(uint8x16_t a)
+ case ARM64_INTRIN_VGET_LANE_P64: // UMOV Rd,Vn.D[lane] poly64_t vget_lane_p64(poly64x1_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_S64: // UMOV Rd,Vn.D[lane] int64_t vget_lane_s64(int64x1_t v, const int lane)
+ case ARM64_INTRIN_VGET_LANE_U64: // UMOV Rd,Vn.D[lane] uint64_t vget_lane_u64(uint64x1_t v, const int lane)
+ case ARM64_INTRIN_VGET_LOW_P16: // DUP Vd.1D,Vn.D[0] poly16x4_t vget_low_p16(poly16x8_t a)
+ case ARM64_INTRIN_VGET_LOW_P64: // DUP Vd.1D,Vn.D[0] poly64x1_t vget_low_p64(poly64x2_t a)
+ case ARM64_INTRIN_VGET_LOW_P8: // DUP Vd.1D,Vn.D[0] poly8x8_t vget_low_p8(poly8x16_t a)
+ case ARM64_INTRIN_VGET_LOW_S16: // DUP Vd.1D,Vn.D[0] int16x4_t vget_low_s16(int16x8_t a)
+ case ARM64_INTRIN_VGET_LOW_S32: // DUP Vd.1D,Vn.D[0] int32x2_t vget_low_s32(int32x4_t a)
+ case ARM64_INTRIN_VGET_LOW_S64: // DUP Vd.1D,Vn.D[0] int64x1_t vget_low_s64(int64x2_t a)
+ case ARM64_INTRIN_VGET_LOW_S8: // DUP Vd.1D,Vn.D[0] int8x8_t vget_low_s8(int8x16_t a)
+ case ARM64_INTRIN_VGET_LOW_U16: // DUP Vd.1D,Vn.D[0] uint16x4_t vget_low_u16(uint16x8_t a)
+ case ARM64_INTRIN_VGET_LOW_U32: // DUP Vd.1D,Vn.D[0] uint32x2_t vget_low_u32(uint32x4_t a)
+ case ARM64_INTRIN_VGET_LOW_U64: // DUP Vd.1D,Vn.D[0] uint64x1_t vget_low_u64(uint64x2_t a)
+ case ARM64_INTRIN_VGET_LOW_U8: // DUP Vd.1D,Vn.D[0] uint8x8_t vget_low_u8(uint8x16_t a)
+ case ARM64_INTRIN_VGETQ_LANE_P64: // UMOV Rd,Vn.D[lane] poly64_t vgetq_lane_p64(poly64x2_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_S64: // UMOV Rd,Vn.D[lane] int64_t vgetq_lane_s64(int64x2_t v, const int lane)
+ case ARM64_INTRIN_VGETQ_LANE_U64: // UMOV Rd,Vn.D[lane] uint64_t vgetq_lane_u64(uint64x2_t v, const int lane)
+ case ARM64_INTRIN_VHADD_S16: // SHADD Vd.4H,Vn.4H,Vm.4H int16x4_t vhadd_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VHADD_S32: // SHADD Vd.2S,Vn.2S,Vm.2S int32x2_t vhadd_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VHADD_S8: // SHADD Vd.8B,Vn.8B,Vm.8B int8x8_t vhadd_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VHADD_U16: // UHADD Vd.4H,Vn.4H,Vm.4H uint16x4_t vhadd_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VHADD_U32: // UHADD Vd.2S,Vn.2S,Vm.2S uint32x2_t vhadd_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VHADD_U8: // UHADD Vd.8B,Vn.8B,Vm.8B uint8x8_t vhadd_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VHSUB_S16: // SHSUB Vd.4H,Vn.4H,Vm.4H int16x4_t vhsub_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VHSUB_S32: // SHSUB Vd.2S,Vn.2S,Vm.2S int32x2_t vhsub_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VHSUB_S8: // SHSUB Vd.8B,Vn.8B,Vm.8B int8x8_t vhsub_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VHSUB_U16: // UHSUB Vd.4H,Vn.4H,Vm.4H uint16x4_t vhsub_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VHSUB_U32: // UHSUB Vd.2S,Vn.2S,Vm.2S uint32x2_t vhsub_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VHSUB_U8: // UHSUB Vd.8B,Vn.8B,Vm.8B uint8x8_t vhsub_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VMAX_S16: // SMAX Vd.4H,Vn.4H,Vm.4H int16x4_t vmax_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VMAX_S32: // SMAX Vd.2S,Vn.2S,Vm.2S int32x2_t vmax_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VMAX_S8: // SMAX Vd.8B,Vn.8B,Vm.8B int8x8_t vmax_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VMAX_U16: // UMAX Vd.4H,Vn.4H,Vm.4H uint16x4_t vmax_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VMAX_U32: // UMAX Vd.2S,Vn.2S,Vm.2S uint32x2_t vmax_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VMAX_U8: // UMAX Vd.8B,Vn.8B,Vm.8B uint8x8_t vmax_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VMIN_S16: // SMIN Vd.4H,Vn.4H,Vm.4H int16x4_t vmin_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VMIN_S32: // SMIN Vd.2S,Vn.2S,Vm.2S int32x2_t vmin_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VMIN_S8: // SMIN Vd.8B,Vn.8B,Vm.8B int8x8_t vmin_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VMIN_U16: // UMIN Vd.4H,Vn.4H,Vm.4H uint16x4_t vmin_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VMIN_U32: // UMIN Vd.2S,Vn.2S,Vm.2S uint32x2_t vmin_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VMIN_U8: // UMIN Vd.8B,Vn.8B,Vm.8B uint8x8_t vmin_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VMLA_LANE_S16: // MLA Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vmla_lane_s16(int16x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLA_LANE_S32: // MLA Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vmla_lane_s32(int32x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLA_LANE_U16: // MLA Vd.4H,Vn.4H,Vm.H[lane] uint16x4_t vmla_lane_u16(uint16x4_t a, uint16x4_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLA_LANE_U32: // MLA Vd.2S,Vn.2S,Vm.S[lane] uint32x2_t vmla_lane_u32(uint32x2_t a, uint32x2_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLA_LANEQ_S16: // MLA Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vmla_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLA_LANEQ_S32: // MLA Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vmla_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLA_LANEQ_U16: // MLA Vd.4H,Vn.4H,Vm.H[lane] uint16x4_t vmla_laneq_u16(uint16x4_t a, uint16x4_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLA_LANEQ_U32: // MLA Vd.2S,Vn.2S,Vm.S[lane] uint32x2_t vmla_laneq_u32(uint32x2_t a, uint32x2_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLA_N_S16: // MLA Vd.4H,Vn.4H,Vm.H[0] int16x4_t vmla_n_s16(int16x4_t a, int16x4_t b, int16_t c)
+ case ARM64_INTRIN_VMLA_N_S32: // MLA Vd.2S,Vn.2S,Vm.S[0] int32x2_t vmla_n_s32(int32x2_t a, int32x2_t b, int32_t c)
+ case ARM64_INTRIN_VMLA_N_U16: // MLA Vd.4H,Vn.4H,Vm.H[0] uint16x4_t vmla_n_u16(uint16x4_t a, uint16x4_t b, uint16_t c)
+ case ARM64_INTRIN_VMLA_N_U32: // MLA Vd.2S,Vn.2S,Vm.S[0] uint32x2_t vmla_n_u32(uint32x2_t a, uint32x2_t b, uint32_t c)
+ case ARM64_INTRIN_VMLA_S16: // MLA Vd.4H,Vn.4H,Vm.4H int16x4_t vmla_s16(int16x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VMLA_S32: // MLA Vd.2S,Vn.2S,Vm.2S int32x2_t vmla_s32(int32x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VMLA_S8: // MLA Vd.8B,Vn.8B,Vm.8B int8x8_t vmla_s8(int8x8_t a, int8x8_t b, int8x8_t c)
+ case ARM64_INTRIN_VMLA_U16: // MLA Vd.4H,Vn.4H,Vm.4H uint16x4_t vmla_u16(uint16x4_t a, uint16x4_t b, uint16x4_t c)
+ case ARM64_INTRIN_VMLA_U32: // MLA Vd.2S,Vn.2S,Vm.2S uint32x2_t vmla_u32(uint32x2_t a, uint32x2_t b, uint32x2_t c)
+ case ARM64_INTRIN_VMLA_U8: // MLA Vd.8B,Vn.8B,Vm.8B uint8x8_t vmla_u8(uint8x8_t a, uint8x8_t b, uint8x8_t c)
+ case ARM64_INTRIN_VMLS_LANE_S16: // MLS Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vmls_lane_s16(int16x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLS_LANE_S32: // MLS Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vmls_lane_s32(int32x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLS_LANE_U16: // MLS Vd.4H,Vn.4H,Vm.H[lane] uint16x4_t vmls_lane_u16(uint16x4_t a, uint16x4_t b, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMLS_LANE_U32: // MLS Vd.2S,Vn.2S,Vm.S[lane] uint32x2_t vmls_lane_u32(uint32x2_t a, uint32x2_t b, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMLS_LANEQ_S16: // MLS Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vmls_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLS_LANEQ_S32: // MLS Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vmls_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLS_LANEQ_U16: // MLS Vd.4H,Vn.4H,Vm.H[lane] uint16x4_t vmls_laneq_u16(uint16x4_t a, uint16x4_t b, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMLS_LANEQ_U32: // MLS Vd.2S,Vn.2S,Vm.S[lane] uint32x2_t vmls_laneq_u32(uint32x2_t a, uint32x2_t b, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMLS_N_S16: // MLS Vd.4H,Vn.4H,Vm.H[0] int16x4_t vmls_n_s16(int16x4_t a, int16x4_t b, int16_t c)
+ case ARM64_INTRIN_VMLS_N_S32: // MLS Vd.2S,Vn.2S,Vm.S[0] int32x2_t vmls_n_s32(int32x2_t a, int32x2_t b, int32_t c)
+ case ARM64_INTRIN_VMLS_N_U16: // MLS Vd.4H,Vn.4H,Vm.H[0] uint16x4_t vmls_n_u16(uint16x4_t a, uint16x4_t b, uint16_t c)
+ case ARM64_INTRIN_VMLS_N_U32: // MLS Vd.2S,Vn.2S,Vm.S[0] uint32x2_t vmls_n_u32(uint32x2_t a, uint32x2_t b, uint32_t c)
+ case ARM64_INTRIN_VMLS_S16: // MLS Vd.4H,Vn.4H,Vm.4H int16x4_t vmls_s16(int16x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VMLS_S32: // MLS Vd.2S,Vn.2S,Vm.2S int32x2_t vmls_s32(int32x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VMLS_S8: // MLS Vd.8B,Vn.8B,Vm.8B int8x8_t vmls_s8(int8x8_t a, int8x8_t b, int8x8_t c)
+ case ARM64_INTRIN_VMLS_U16: // MLS Vd.4H,Vn.4H,Vm.4H uint16x4_t vmls_u16(uint16x4_t a, uint16x4_t b, uint16x4_t c)
+ case ARM64_INTRIN_VMLS_U32: // MLS Vd.2S,Vn.2S,Vm.2S uint32x2_t vmls_u32(uint32x2_t a, uint32x2_t b, uint32x2_t c)
+ case ARM64_INTRIN_VMLS_U8: // MLS Vd.8B,Vn.8B,Vm.8B uint8x8_t vmls_u8(uint8x8_t a, uint8x8_t b, uint8x8_t c)
+ case ARM64_INTRIN_VMOV_N_P16: // DUP Vd.4H,rn poly16x4_t vmov_n_p16(poly16_t value)
+ case ARM64_INTRIN_VMOV_N_P8: // DUP Vd.8B,rn poly8x8_t vmov_n_p8(poly8_t value)
+ case ARM64_INTRIN_VMOV_N_S16: // DUP Vd.4H,rn int16x4_t vmov_n_s16(int16_t value)
+ case ARM64_INTRIN_VMOV_N_S32: // DUP Vd.2S,rn int32x2_t vmov_n_s32(int32_t value)
+ case ARM64_INTRIN_VMOV_N_S64: // DUP Vd.1D,rn int64x1_t vmov_n_s64(int64_t value)
+ case ARM64_INTRIN_VMOV_N_S8: // DUP Vd.8B,rn int8x8_t vmov_n_s8(int8_t value)
+ case ARM64_INTRIN_VMOV_N_U16: // DUP Vd.4H,rn uint16x4_t vmov_n_u16(uint16_t value)
+ case ARM64_INTRIN_VMOV_N_U32: // DUP Vd.2S,rn uint32x2_t vmov_n_u32(uint32_t value)
+ case ARM64_INTRIN_VMOV_N_U64: // DUP Vd.1D,rn uint64x1_t vmov_n_u64(uint64_t value)
+ case ARM64_INTRIN_VMOV_N_U8: // DUP Vd.8B,rn uint8x8_t vmov_n_u8(uint8_t value)
+ case ARM64_INTRIN_VMOVN_S16: // XTN Vd.8B,Vn.8H int8x8_t vmovn_s16(int16x8_t a)
+ case ARM64_INTRIN_VMOVN_S32: // XTN Vd.4H,Vn.4S int16x4_t vmovn_s32(int32x4_t a)
+ case ARM64_INTRIN_VMOVN_S64: // XTN Vd.2S,Vn.2D int32x2_t vmovn_s64(int64x2_t a)
+ case ARM64_INTRIN_VMOVN_U16: // XTN Vd.8B,Vn.8H uint8x8_t vmovn_u16(uint16x8_t a)
+ case ARM64_INTRIN_VMOVN_U32: // XTN Vd.4H,Vn.4S uint16x4_t vmovn_u32(uint32x4_t a)
+ case ARM64_INTRIN_VMOVN_U64: // XTN Vd.2S,Vn.2D uint32x2_t vmovn_u64(uint64x2_t a)
+ case ARM64_INTRIN_VMUL_LANE_S16: // MUL Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vmul_lane_s16(int16x4_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANE_S32: // MUL Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vmul_lane_s32(int32x2_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANE_U16: // MUL Vd.4H,Vn.4H,Vm.H[lane] uint16x4_t vmul_lane_u16(uint16x4_t a, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANE_U32: // MUL Vd.2S,Vn.2S,Vm.S[lane] uint32x2_t vmul_lane_u32(uint32x2_t a, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANEQ_S16: // MUL Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vmul_laneq_s16(int16x4_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANEQ_S32: // MUL Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vmul_laneq_s32(int32x2_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANEQ_U16: // MUL Vd.4H,Vn.4H,Vm.H[lane] uint16x4_t vmul_laneq_u16(uint16x4_t a, uint16x8_t v, const int lane)
+ case ARM64_INTRIN_VMUL_LANEQ_U32: // MUL Vd.2S,Vn.2S,Vm.S[lane] uint32x2_t vmul_laneq_u32(uint32x2_t a, uint32x4_t v, const int lane)
+ case ARM64_INTRIN_VMUL_N_S16: // MUL Vd.4H,Vn.4H,Vm.H[0] int16x4_t vmul_n_s16(int16x4_t a, int16_t b)
+ case ARM64_INTRIN_VMUL_N_S32: // MUL Vd.2S,Vn.2S,Vm.S[0] int32x2_t vmul_n_s32(int32x2_t a, int32_t b)
+ case ARM64_INTRIN_VMUL_N_U16: // MUL Vd.4H,Vn.4H,Vm.H[0] uint16x4_t vmul_n_u16(uint16x4_t a, uint16_t b)
+ case ARM64_INTRIN_VMUL_N_U32: // MUL Vd.2S,Vn.2S,Vm.S[0] uint32x2_t vmul_n_u32(uint32x2_t a, uint32_t b)
+ case ARM64_INTRIN_VMUL_P8: // PMUL Vd.8B,Vn.8B,Vm.8B poly8x8_t vmul_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VMUL_S16: // MUL Vd.4H,Vn.4H,Vm.4H int16x4_t vmul_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VMUL_S32: // MUL Vd.2S,Vn.2S,Vm.2S int32x2_t vmul_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VMUL_S8: // MUL Vd.8B,Vn.8B,Vm.8B int8x8_t vmul_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VMUL_U16: // MUL Vd.4H,Vn.4H,Vm.4H uint16x4_t vmul_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VMUL_U32: // MUL Vd.2S,Vn.2S,Vm.2S uint32x2_t vmul_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VMUL_U8: // MUL Vd.8B,Vn.8B,Vm.8B uint8x8_t vmul_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VMVN_P8: // MVN Vd.8B,Vn.8B poly8x8_t vmvn_p8(poly8x8_t a)
+ case ARM64_INTRIN_VMVN_S16: // MVN Vd.8B,Vn.8B int16x4_t vmvn_s16(int16x4_t a)
+ case ARM64_INTRIN_VMVN_S32: // MVN Vd.8B,Vn.8B int32x2_t vmvn_s32(int32x2_t a)
+ case ARM64_INTRIN_VMVN_S8: // MVN Vd.8B,Vn.8B int8x8_t vmvn_s8(int8x8_t a)
+ case ARM64_INTRIN_VMVN_U16: // MVN Vd.8B,Vn.8B uint16x4_t vmvn_u16(uint16x4_t a)
+ case ARM64_INTRIN_VMVN_U32: // MVN Vd.8B,Vn.8B uint32x2_t vmvn_u32(uint32x2_t a)
+ case ARM64_INTRIN_VMVN_U8: // MVN Vd.8B,Vn.8B uint8x8_t vmvn_u8(uint8x8_t a)
+ case ARM64_INTRIN_VNEG_S16: // NEG Vd.4H,Vn.4H int16x4_t vneg_s16(int16x4_t a)
+ case ARM64_INTRIN_VNEG_S32: // NEG Vd.2S,Vn.2S int32x2_t vneg_s32(int32x2_t a)
+ case ARM64_INTRIN_VNEG_S64: // NEG Dd,Dn int64x1_t vneg_s64(int64x1_t a)
+ case ARM64_INTRIN_VNEG_S8: // NEG Vd.8B,Vn.8B int8x8_t vneg_s8(int8x8_t a)
+ case ARM64_INTRIN_VNEGD_S64: // NEG Dd,Dn int64_t vnegd_s64(int64_t a)
+ case ARM64_INTRIN_VORN_S16: // ORN Vd.8B,Vn.8B,Vm.8B int16x4_t vorn_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VORN_S32: // ORN Vd.8B,Vn.8B,Vm.8B int32x2_t vorn_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VORN_S64: // ORN Vd.8B,Vn.8B,Vm.8B int64x1_t vorn_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VORN_S8: // ORN Vd.8B,Vn.8B,Vm.8B int8x8_t vorn_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VORN_U16: // ORN Vd.8B,Vn.8B,Vm.8B uint16x4_t vorn_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VORN_U32: // ORN Vd.8B,Vn.8B,Vm.8B uint32x2_t vorn_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VORN_U64: // ORN Vd.8B,Vn.8B,Vm.8B uint64x1_t vorn_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VORN_U8: // ORN Vd.8B,Vn.8B,Vm.8B uint8x8_t vorn_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VORR_S16: // ORR Vd.8B,Vn.8B,Vm.8B int16x4_t vorr_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VORR_S32: // ORR Vd.8B,Vn.8B,Vm.8B int32x2_t vorr_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VORR_S64: // ORR Vd.8B,Vn.8B,Vm.8B int64x1_t vorr_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VORR_S8: // ORR Vd.8B,Vn.8B,Vm.8B int8x8_t vorr_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VORR_U16: // ORR Vd.8B,Vn.8B,Vm.8B uint16x4_t vorr_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VORR_U32: // ORR Vd.8B,Vn.8B,Vm.8B uint32x2_t vorr_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VORR_U64: // ORR Vd.8B,Vn.8B,Vm.8B uint64x1_t vorr_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VORR_U8: // ORR Vd.8B,Vn.8B,Vm.8B uint8x8_t vorr_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VPADAL_S16: // SADALP Vd.2S,Vn.4H int32x2_t vpadal_s16(int32x2_t a, int16x4_t b)
+ case ARM64_INTRIN_VPADAL_S32: // SADALP Vd.1D,Vn.2S int64x1_t vpadal_s32(int64x1_t a, int32x2_t b)
+ case ARM64_INTRIN_VPADAL_S8: // SADALP Vd.4H,Vn.8B int16x4_t vpadal_s8(int16x4_t a, int8x8_t b)
+ case ARM64_INTRIN_VPADAL_U16: // UADALP Vd.2S,Vn.4H uint32x2_t vpadal_u16(uint32x2_t a, uint16x4_t b)
+ case ARM64_INTRIN_VPADAL_U32: // UADALP Vd.1D,Vn.2S uint64x1_t vpadal_u32(uint64x1_t a, uint32x2_t b)
+ case ARM64_INTRIN_VPADAL_U8: // UADALP Vd.4H,Vn.8B uint16x4_t vpadal_u8(uint16x4_t a, uint8x8_t b)
+ case ARM64_INTRIN_VPADD_S16: // ADDP Vd.4H,Vn.4H,Vm.4H int16x4_t vpadd_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VPADD_S32: // ADDP Vd.2S,Vn.2S,Vm.2S int32x2_t vpadd_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VPADD_S8: // ADDP Vd.8B,Vn.8B,Vm.8B int8x8_t vpadd_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VPADD_U16: // ADDP Vd.4H,Vn.4H,Vm.4H uint16x4_t vpadd_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VPADD_U32: // ADDP Vd.2S,Vn.2S,Vm.2S uint32x2_t vpadd_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VPADD_U8: // ADDP Vd.8B,Vn.8B,Vm.8B uint8x8_t vpadd_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VPADDD_S64: // ADDP Dd,Vn.2D int64_t vpaddd_s64(int64x2_t a)
+ case ARM64_INTRIN_VPADDD_U64: // ADDP Dd,Vn.2D uint64_t vpaddd_u64(uint64x2_t a)
+ case ARM64_INTRIN_VPADDL_S16: // SADDLP Vd.2S,Vn.4H int32x2_t vpaddl_s16(int16x4_t a)
+ case ARM64_INTRIN_VPADDL_S32: // SADDLP Vd.1D,Vn.2S int64x1_t vpaddl_s32(int32x2_t a)
+ case ARM64_INTRIN_VPADDL_S8: // SADDLP Vd.4H,Vn.8B int16x4_t vpaddl_s8(int8x8_t a)
+ case ARM64_INTRIN_VPADDL_U16: // UADDLP Vd.2S,Vn.4H uint32x2_t vpaddl_u16(uint16x4_t a)
+ case ARM64_INTRIN_VPADDL_U32: // UADDLP Vd.1D,Vn.2S uint64x1_t vpaddl_u32(uint32x2_t a)
+ case ARM64_INTRIN_VPADDL_U8: // UADDLP Vd.4H,Vn.8B uint16x4_t vpaddl_u8(uint8x8_t a)
+ case ARM64_INTRIN_VPMAX_S16: // SMAXP Vd.4H,Vn.4H,Vm.4H int16x4_t vpmax_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VPMAX_S32: // SMAXP Vd.2S,Vn.2S,Vm.2S int32x2_t vpmax_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VPMAX_S8: // SMAXP Vd.8B,Vn.8B,Vm.8B int8x8_t vpmax_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VPMAX_U16: // UMAXP Vd.4H,Vn.4H,Vm.4H uint16x4_t vpmax_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VPMAX_U32: // UMAXP Vd.2S,Vn.2S,Vm.2S uint32x2_t vpmax_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VPMAX_U8: // UMAXP Vd.8B,Vn.8B,Vm.8B uint8x8_t vpmax_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VPMIN_S16: // SMINP Vd.4H,Vn.4H,Vm.4H int16x4_t vpmin_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VPMIN_S32: // SMINP Vd.2S,Vn.2S,Vm.2S int32x2_t vpmin_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VPMIN_S8: // SMINP Vd.8B,Vn.8B,Vm.8B int8x8_t vpmin_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VPMIN_U16: // UMINP Vd.4H,Vn.4H,Vm.4H uint16x4_t vpmin_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VPMIN_U32: // UMINP Vd.2S,Vn.2S,Vm.2S uint32x2_t vpmin_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VPMIN_U8: // UMINP Vd.8B,Vn.8B,Vm.8B uint8x8_t vpmin_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VQABS_S16: // SQABS Vd.4H,Vn.4H int16x4_t vqabs_s16(int16x4_t a)
+ case ARM64_INTRIN_VQABS_S32: // SQABS Vd.2S,Vn.2S int32x2_t vqabs_s32(int32x2_t a)
+ case ARM64_INTRIN_VQABS_S64: // SQABS Dd,Dn int64x1_t vqabs_s64(int64x1_t a)
+ case ARM64_INTRIN_VQABS_S8: // SQABS Vd.8B,Vn.8B int8x8_t vqabs_s8(int8x8_t a)
+ case ARM64_INTRIN_VQABSD_S64: // SQABS Dd,Dn int64_t vqabsd_s64(int64_t a)
+ case ARM64_INTRIN_VQADD_S16: // SQADD Vd.4H,Vn.4H,Vm.4H int16x4_t vqadd_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQADD_S32: // SQADD Vd.2S,Vn.2S,Vm.2S int32x2_t vqadd_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQADD_S64: // SQADD Dd,Dn,Dm int64x1_t vqadd_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VQADD_S8: // SQADD Vd.8B,Vn.8B,Vm.8B int8x8_t vqadd_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VQADD_U16: // UQADD Vd.4H,Vn.4H,Vm.4H uint16x4_t vqadd_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VQADD_U32: // UQADD Vd.2S,Vn.2S,Vm.2S uint32x2_t vqadd_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VQADD_U64: // UQADD Dd,Dn,Dm uint64x1_t vqadd_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VQADD_U8: // UQADD Vd.8B,Vn.8B,Vm.8B uint8x8_t vqadd_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VQADDD_S64: // SQADD Dd,Dn,Dm int64_t vqaddd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VQADDD_U64: // UQADD Dd,Dn,Dm uint64_t vqaddd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VQDMLALS_LANE_S32: // SQDMLAL Dd,Sn,Vm.S[lane] int64_t vqdmlals_lane_s32(int64_t a, int32_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMLALS_LANEQ_S32: // SQDMLAL Dd,Sn,Vm.S[lane] int64_t vqdmlals_laneq_s32(int64_t a, int32_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLALS_S32: // SQDMLAL Dd,Sn,Sm int64_t vqdmlals_s32(int64_t a, int32_t b, int32_t c)
+ case ARM64_INTRIN_VQDMLSLS_LANE_S32: // SQDMLSL Dd,Sn,Vm.S[lane] int64_t vqdmlsls_lane_s32(int64_t a, int32_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSLS_LANEQ_S32: // SQDMLSL Dd,Sn,Vm.S[lane] int64_t vqdmlsls_laneq_s32(int64_t a, int32_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMLSLS_S32: // SQDMLSL Dd,Sn,Sm int64_t vqdmlsls_s32(int64_t a, int32_t b, int32_t c)
+ case ARM64_INTRIN_VQDMULH_LANE_S16: // SQDMULH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqdmulh_lane_s16(int16x4_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULH_LANE_S32: // SQDMULH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqdmulh_lane_s32(int32x2_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMULH_LANEQ_S16: // SQDMULH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqdmulh_laneq_s16(int16x4_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQDMULH_LANEQ_S32: // SQDMULH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqdmulh_laneq_s32(int32x2_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULH_N_S16: // SQDMULH Vd.4H,Vn.4H,Vm.H[0] int16x4_t vqdmulh_n_s16(int16x4_t a, int16_t b)
+ case ARM64_INTRIN_VQDMULH_N_S32: // SQDMULH Vd.2S,Vn.2S,Vm.S[0] int32x2_t vqdmulh_n_s32(int32x2_t a, int32_t b)
+ case ARM64_INTRIN_VQDMULH_S16: // SQDMULH Vd.4H,Vn.4H,Vm.4H int16x4_t vqdmulh_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQDMULH_S32: // SQDMULH Vd.2S,Vn.2S,Vm.2S int32x2_t vqdmulh_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQDMULLS_LANE_S32: // SQDMULL Dd,Sn,Vm.S[lane] int64_t vqdmulls_lane_s32(int32_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQDMULLS_LANEQ_S32: // SQDMULL Dd,Sn,Vm.S[lane] int64_t vqdmulls_laneq_s32(int32_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQDMULLS_S32: // SQDMULL Dd,Sn,Sm int64_t vqdmulls_s32(int32_t a, int32_t b)
+ case ARM64_INTRIN_VQMOVN_S16: // SQXTN Vd.8B,Vn.8H int8x8_t vqmovn_s16(int16x8_t a)
+ case ARM64_INTRIN_VQMOVN_S32: // SQXTN Vd.4H,Vn.4S int16x4_t vqmovn_s32(int32x4_t a)
+ case ARM64_INTRIN_VQMOVN_S64: // SQXTN Vd.2S,Vn.2D int32x2_t vqmovn_s64(int64x2_t a)
+ case ARM64_INTRIN_VQMOVN_U16: // UQXTN Vd.8B,Vn.8H uint8x8_t vqmovn_u16(uint16x8_t a)
+ case ARM64_INTRIN_VQMOVN_U32: // UQXTN Vd.4H,Vn.4S uint16x4_t vqmovn_u32(uint32x4_t a)
+ case ARM64_INTRIN_VQMOVN_U64: // UQXTN Vd.2S,Vn.2D uint32x2_t vqmovn_u64(uint64x2_t a)
+ case ARM64_INTRIN_VQMOVUN_S16: // SQXTUN Vd.8B,Vn.8H uint8x8_t vqmovun_s16(int16x8_t a)
+ case ARM64_INTRIN_VQMOVUN_S32: // SQXTUN Vd.4H,Vn.4S uint16x4_t vqmovun_s32(int32x4_t a)
+ case ARM64_INTRIN_VQMOVUN_S64: // SQXTUN Vd.2S,Vn.2D uint32x2_t vqmovun_s64(int64x2_t a)
+ case ARM64_INTRIN_VQNEG_S16: // SQNEG Vd.4H,Vn.4H int16x4_t vqneg_s16(int16x4_t a)
+ case ARM64_INTRIN_VQNEG_S32: // SQNEG Vd.2S,Vn.2S int32x2_t vqneg_s32(int32x2_t a)
+ case ARM64_INTRIN_VQNEG_S64: // SQNEG Dd,Dn int64x1_t vqneg_s64(int64x1_t a)
+ case ARM64_INTRIN_VQNEG_S8: // SQNEG Vd.8B,Vn.8B int8x8_t vqneg_s8(int8x8_t a)
+ case ARM64_INTRIN_VQNEGD_S64: // SQNEG Dd,Dn int64_t vqnegd_s64(int64_t a)
+ case ARM64_INTRIN_VQRDMLAH_LANE_S16: // SQRDMLAH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqrdmlah_lane_s16(int16x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAH_LANE_S32: // SQRDMLAH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqrdmlah_lane_s32(int32x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAH_LANEQ_S16: // SQRDMLAH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqrdmlah_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAH_LANEQ_S32: // SQRDMLAH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqrdmlah_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLAH_S16: // SQRDMLAH Vd.4H,Vn.4H,Vm.4H int16x4_t vqrdmlah_s16(int16x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VQRDMLAH_S32: // SQRDMLAH Vd.2S,Vn.2S,Vm.2S int32x2_t vqrdmlah_s32(int32x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VQRDMLSH_LANE_S16: // SQRDMLSH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqrdmlsh_lane_s16(int16x4_t a, int16x4_t b, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSH_LANE_S32: // SQRDMLSH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqrdmlsh_lane_s32(int32x2_t a, int32x2_t b, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSH_LANEQ_S16: // SQRDMLSH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqrdmlsh_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSH_LANEQ_S32: // SQRDMLSH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqrdmlsh_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMLSH_S16: // SQRDMLSH Vd.4H,Vn.4H,Vm.4H int16x4_t vqrdmlsh_s16(int16x4_t a, int16x4_t b, int16x4_t c)
+ case ARM64_INTRIN_VQRDMLSH_S32: // SQRDMLSH Vd.2S,Vn.2S,Vm.2S int32x2_t vqrdmlsh_s32(int32x2_t a, int32x2_t b, int32x2_t c)
+ case ARM64_INTRIN_VQRDMULH_LANE_S16: // SQRDMULH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqrdmulh_lane_s16(int16x4_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULH_LANE_S32: // SQRDMULH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqrdmulh_lane_s32(int32x2_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULH_LANEQ_S16: // SQRDMULH Vd.4H,Vn.4H,Vm.H[lane] int16x4_t vqrdmulh_laneq_s16(int16x4_t a, int16x8_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULH_LANEQ_S32: // SQRDMULH Vd.2S,Vn.2S,Vm.S[lane] int32x2_t vqrdmulh_laneq_s32(int32x2_t a, int32x4_t v, const int lane)
+ case ARM64_INTRIN_VQRDMULH_N_S16: // SQRDMULH Vd.4H,Vn.4H,Vm.H[0] int16x4_t vqrdmulh_n_s16(int16x4_t a, int16_t b)
+ case ARM64_INTRIN_VQRDMULH_N_S32: // SQRDMULH Vd.2S,Vn.2S,Vm.S[0] int32x2_t vqrdmulh_n_s32(int32x2_t a, int32_t b)
+ case ARM64_INTRIN_VQRDMULH_S16: // SQRDMULH Vd.4H,Vn.4H,Vm.4H int16x4_t vqrdmulh_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQRDMULH_S32: // SQRDMULH Vd.2S,Vn.2S,Vm.2S int32x2_t vqrdmulh_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQRSHL_S16: // SQRSHL Vd.4H,Vn.4H,Vm.4H int16x4_t vqrshl_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQRSHL_S32: // SQRSHL Vd.2S,Vn.2S,Vm.2S int32x2_t vqrshl_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQRSHL_S64: // SQRSHL Dd,Dn,Dm int64x1_t vqrshl_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VQRSHL_S8: // SQRSHL Vd.8B,Vn.8B,Vm.8B int8x8_t vqrshl_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VQRSHL_U16: // UQRSHL Vd.4H,Vn.4H,Vm.4H uint16x4_t vqrshl_u16(uint16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQRSHL_U32: // UQRSHL Vd.2S,Vn.2S,Vm.2S uint32x2_t vqrshl_u32(uint32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQRSHL_U64: // UQRSHL Dd,Dn,Dm uint64x1_t vqrshl_u64(uint64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VQRSHL_U8: // UQRSHL Vd.8B,Vn.8B,Vm.8B uint8x8_t vqrshl_u8(uint8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VQRSHLD_S64: // SQRSHL Dd,Dn,Dm int64_t vqrshld_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VQRSHLD_U64: // UQRSHL Dd,Dn,Dm uint64_t vqrshld_u64(uint64_t a, int64_t b)
+ case ARM64_INTRIN_VQRSHRN_N_S16: // SQRSHRN Vd.8B,Vn.8H,#n int8x8_t vqrshrn_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_N_S32: // SQRSHRN Vd.4H,Vn.4S,#n int16x4_t vqrshrn_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_N_S64: // SQRSHRN Vd.2S,Vn.2D,#n int32x2_t vqrshrn_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_N_U16: // UQRSHRN Vd.8B,Vn.8H,#n uint8x8_t vqrshrn_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_N_U32: // UQRSHRN Vd.4H,Vn.4S,#n uint16x4_t vqrshrn_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VQRSHRN_N_U64: // UQRSHRN Vd.2S,Vn.2D,#n uint32x2_t vqrshrn_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUN_N_S16: // SQRSHRUN Vd.8B,Vn.8H,#n uint8x8_t vqrshrun_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUN_N_S32: // SQRSHRUN Vd.4H,Vn.4S,#n uint16x4_t vqrshrun_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VQRSHRUN_N_S64: // SQRSHRUN Vd.2S,Vn.2D,#n uint32x2_t vqrshrun_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_S16: // SQSHL Vd.4H,Vn.4H,#n int16x4_t vqshl_n_s16(int16x4_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_S32: // SQSHL Vd.2S,Vn.2S,#n int32x2_t vqshl_n_s32(int32x2_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_S64: // SQSHL Dd,Dn,#n int64x1_t vqshl_n_s64(int64x1_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_S8: // SQSHL Vd.8B,Vn.8B,#n int8x8_t vqshl_n_s8(int8x8_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_U16: // UQSHL Vd.4H,Vn.4H,#n uint16x4_t vqshl_n_u16(uint16x4_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_U32: // UQSHL Vd.2S,Vn.2S,#n uint32x2_t vqshl_n_u32(uint32x2_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_U64: // UQSHL Dd,Dn,#n uint64x1_t vqshl_n_u64(uint64x1_t a, const int n)
+ case ARM64_INTRIN_VQSHL_N_U8: // UQSHL Vd.8B,Vn.8B,#n uint8x8_t vqshl_n_u8(uint8x8_t a, const int n)
+ case ARM64_INTRIN_VQSHL_S16: // SQSHL Vd.4H,Vn.4H,Vm.4H int16x4_t vqshl_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQSHL_S32: // SQSHL Vd.2S,Vn.2S,Vm.2S int32x2_t vqshl_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQSHL_S64: // SQSHL Dd,Dn,Dm int64x1_t vqshl_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VQSHL_S8: // SQSHL Vd.8B,Vn.8B,Vm.8B int8x8_t vqshl_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VQSHL_U16: // UQSHL Vd.4H,Vn.4H,Vm.4H uint16x4_t vqshl_u16(uint16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQSHL_U32: // UQSHL Vd.2S,Vn.2S,Vm.2S uint32x2_t vqshl_u32(uint32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQSHL_U64: // UQSHL Dd,Dn,Dm uint64x1_t vqshl_u64(uint64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VQSHL_U8: // UQSHL Vd.8B,Vn.8B,Vm.8B uint8x8_t vqshl_u8(uint8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VQSHLD_N_S64: // SQSHL Dd,Dn,#n int64_t vqshld_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VQSHLD_N_U64: // UQSHL Dd,Dn,#n uint64_t vqshld_n_u64(uint64_t a, const int n)
+ case ARM64_INTRIN_VQSHLD_S64: // SQSHL Dd,Dn,Dm int64_t vqshld_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VQSHLD_U64: // UQSHL Dd,Dn,Dm uint64_t vqshld_u64(uint64_t a, int64_t b)
+ case ARM64_INTRIN_VQSHLU_N_S16: // SQSHLU Vd.4H,Vn.4H,#n uint16x4_t vqshlu_n_s16(int16x4_t a, const int n)
+ case ARM64_INTRIN_VQSHLU_N_S32: // SQSHLU Vd.2S,Vn.2S,#n uint32x2_t vqshlu_n_s32(int32x2_t a, const int n)
+ case ARM64_INTRIN_VQSHLU_N_S64: // SQSHLU Dd,Dn,#n uint64x1_t vqshlu_n_s64(int64x1_t a, const int n)
+ case ARM64_INTRIN_VQSHLU_N_S8: // SQSHLU Vd.8B,Vn.8B,#n uint8x8_t vqshlu_n_s8(int8x8_t a, const int n)
+ case ARM64_INTRIN_VQSHLUD_N_S64: // SQSHLU Dd,Dn,#n uint64_t vqshlud_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_N_S16: // SQSHRN Vd.8B,Vn.8H,#n int8x8_t vqshrn_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_N_S32: // SQSHRN Vd.4H,Vn.4S,#n int16x4_t vqshrn_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_N_S64: // SQSHRN Vd.2S,Vn.2D,#n int32x2_t vqshrn_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_N_U16: // UQSHRN Vd.8B,Vn.8H,#n uint8x8_t vqshrn_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_N_U32: // UQSHRN Vd.4H,Vn.4S,#n uint16x4_t vqshrn_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHRN_N_U64: // UQSHRN Vd.2S,Vn.2D,#n uint32x2_t vqshrn_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VQSHRUN_N_S16: // SQSHRUN Vd.8B,Vn.8H,#n uint8x8_t vqshrun_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VQSHRUN_N_S32: // SQSHRUN Vd.4H,Vn.4S,#n uint16x4_t vqshrun_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VQSHRUN_N_S64: // SQSHRUN Vd.2S,Vn.2D,#n uint32x2_t vqshrun_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VQSUB_S16: // SQSUB Vd.4H,Vn.4H,Vm.4H int16x4_t vqsub_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VQSUB_S32: // SQSUB Vd.2S,Vn.2S,Vm.2S int32x2_t vqsub_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VQSUB_S64: // SQSUB Dd,Dn,Dm int64x1_t vqsub_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VQSUB_S8: // SQSUB Vd.8B,Vn.8B,Vm.8B int8x8_t vqsub_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VQSUB_U16: // UQSUB Vd.4H,Vn.4H,Vm.4H uint16x4_t vqsub_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VQSUB_U32: // UQSUB Vd.2S,Vn.2S,Vm.2S uint32x2_t vqsub_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VQSUB_U64: // UQSUB Dd,Dn,Dm uint64x1_t vqsub_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VQSUB_U8: // UQSUB Vd.8B,Vn.8B,Vm.8B uint8x8_t vqsub_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VQSUBD_S64: // SQSUB Dd,Dn,Dm int64_t vqsubd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VQSUBD_U64: // UQSUB Dd,Dn,Dm uint64_t vqsubd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VRADDHN_S16: // RADDHN Vd.8B,Vn.8H,Vm.8H int8x8_t vraddhn_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VRADDHN_S32: // RADDHN Vd.4H,Vn.4S,Vm.4S int16x4_t vraddhn_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VRADDHN_S64: // RADDHN Vd.2S,Vn.2D,Vm.2D int32x2_t vraddhn_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VRADDHN_U16: // RADDHN Vd.8B,Vn.8H,Vm.8H uint8x8_t vraddhn_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VRADDHN_U32: // RADDHN Vd.4H,Vn.4S,Vm.4S uint16x4_t vraddhn_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VRADDHN_U64: // RADDHN Vd.2S,Vn.2D,Vm.2D uint32x2_t vraddhn_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VRBIT_P8: // RBIT Vd.8B,Vn.8B poly8x8_t vrbit_p8(poly8x8_t a)
+ case ARM64_INTRIN_VRBIT_S8: // RBIT Vd.8B,Vn.8B int8x8_t vrbit_s8(int8x8_t a)
+ case ARM64_INTRIN_VRBIT_U8: // RBIT Vd.8B,Vn.8B uint8x8_t vrbit_u8(uint8x8_t a)
+ case ARM64_INTRIN_VRECPE_U32: // URECPE Vd.2S,Vn.2S uint32x2_t vrecpe_u32(uint32x2_t a)
+ case ARM64_INTRIN_VREV16_P8: // REV16 Vd.8B,Vn.8B poly8x8_t vrev16_p8(poly8x8_t vec)
+ case ARM64_INTRIN_VREV16_S8: // REV16 Vd.8B,Vn.8B int8x8_t vrev16_s8(int8x8_t vec)
+ case ARM64_INTRIN_VREV16_U8: // REV16 Vd.8B,Vn.8B uint8x8_t vrev16_u8(uint8x8_t vec)
+ case ARM64_INTRIN_VREV32_P16: // REV32 Vd.4H,Vn.4H poly16x4_t vrev32_p16(poly16x4_t vec)
+ case ARM64_INTRIN_VREV32_P8: // REV32 Vd.8B,Vn.8B poly8x8_t vrev32_p8(poly8x8_t vec)
+ case ARM64_INTRIN_VREV32_S16: // REV32 Vd.4H,Vn.4H int16x4_t vrev32_s16(int16x4_t vec)
+ case ARM64_INTRIN_VREV32_S8: // REV32 Vd.8B,Vn.8B int8x8_t vrev32_s8(int8x8_t vec)
+ case ARM64_INTRIN_VREV32_U16: // REV32 Vd.4H,Vn.4H uint16x4_t vrev32_u16(uint16x4_t vec)
+ case ARM64_INTRIN_VREV32_U8: // REV32 Vd.8B,Vn.8B uint8x8_t vrev32_u8(uint8x8_t vec)
+ case ARM64_INTRIN_VREV64_P16: // REV64 Vd.4H,Vn.4H poly16x4_t vrev64_p16(poly16x4_t vec)
+ case ARM64_INTRIN_VREV64_P8: // REV64 Vd.8B,Vn.8B poly8x8_t vrev64_p8(poly8x8_t vec)
+ case ARM64_INTRIN_VREV64_S16: // REV64 Vd.4H,Vn.4H int16x4_t vrev64_s16(int16x4_t vec)
+ case ARM64_INTRIN_VREV64_S32: // REV64 Vd.2S,Vn.2S int32x2_t vrev64_s32(int32x2_t vec)
+ case ARM64_INTRIN_VREV64_S8: // REV64 Vd.8B,Vn.8B int8x8_t vrev64_s8(int8x8_t vec)
+ case ARM64_INTRIN_VREV64_U16: // REV64 Vd.4H,Vn.4H uint16x4_t vrev64_u16(uint16x4_t vec)
+ case ARM64_INTRIN_VREV64_U32: // REV64 Vd.2S,Vn.2S uint32x2_t vrev64_u32(uint32x2_t vec)
+ case ARM64_INTRIN_VREV64_U8: // REV64 Vd.8B,Vn.8B uint8x8_t vrev64_u8(uint8x8_t vec)
+ case ARM64_INTRIN_VRHADD_S16: // SRHADD Vd.4H,Vn.4H,Vm.4H int16x4_t vrhadd_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VRHADD_S32: // SRHADD Vd.2S,Vn.2S,Vm.2S int32x2_t vrhadd_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VRHADD_S8: // SRHADD Vd.8B,Vn.8B,Vm.8B int8x8_t vrhadd_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VRHADD_U16: // URHADD Vd.4H,Vn.4H,Vm.4H uint16x4_t vrhadd_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VRHADD_U32: // URHADD Vd.2S,Vn.2S,Vm.2S uint32x2_t vrhadd_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VRHADD_U8: // URHADD Vd.8B,Vn.8B,Vm.8B uint8x8_t vrhadd_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VRSHL_S16: // SRSHL Vd.4H,Vn.4H,Vm.4H int16x4_t vrshl_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VRSHL_S32: // SRSHL Vd.2S,Vn.2S,Vm.2S int32x2_t vrshl_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VRSHL_S64: // SRSHL Dd,Dn,Dm int64x1_t vrshl_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VRSHL_S8: // SRSHL Vd.8B,Vn.8B,Vm.8B int8x8_t vrshl_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VRSHL_U16: // URSHL Vd.4H,Vn.4H,Vm.4H uint16x4_t vrshl_u16(uint16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VRSHL_U32: // URSHL Vd.2S,Vn.2S,Vm.2S uint32x2_t vrshl_u32(uint32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VRSHL_U64: // URSHL Dd,Dn,Dm uint64x1_t vrshl_u64(uint64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VRSHL_U8: // URSHL Vd.8B,Vn.8B,Vm.8B uint8x8_t vrshl_u8(uint8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VRSHLD_S64: // SRSHL Dd,Dn,Dm int64_t vrshld_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VRSHLD_U64: // URSHL Dd,Dn,Dm uint64_t vrshld_u64(uint64_t a, int64_t b)
+ case ARM64_INTRIN_VRSHR_N_S16: // SRSHR Vd.4H,Vn.4H,#n int16x4_t vrshr_n_s16(int16x4_t a, const int n)
+ case ARM64_INTRIN_VRSHR_N_S32: // SRSHR Vd.2S,Vn.2S,#n int32x2_t vrshr_n_s32(int32x2_t a, const int n)
+ case ARM64_INTRIN_VRSHR_N_S64: // SRSHR Dd,Dn,#n int64x1_t vrshr_n_s64(int64x1_t a, const int n)
+ case ARM64_INTRIN_VRSHR_N_S8: // SRSHR Vd.8B,Vn.8B,#n int8x8_t vrshr_n_s8(int8x8_t a, const int n)
+ case ARM64_INTRIN_VRSHR_N_U16: // URSHR Vd.4H,Vn.4H,#n uint16x4_t vrshr_n_u16(uint16x4_t a, const int n)
+ case ARM64_INTRIN_VRSHR_N_U32: // URSHR Vd.2S,Vn.2S,#n uint32x2_t vrshr_n_u32(uint32x2_t a, const int n)
+ case ARM64_INTRIN_VRSHR_N_U64: // URSHR Dd,Dn,#n uint64x1_t vrshr_n_u64(uint64x1_t a, const int n)
+ case ARM64_INTRIN_VRSHR_N_U8: // URSHR Vd.8B,Vn.8B,#n uint8x8_t vrshr_n_u8(uint8x8_t a, const int n)
+ case ARM64_INTRIN_VRSHRD_N_S64: // SRSHR Dd,Dn,#n int64_t vrshrd_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VRSHRD_N_U64: // URSHR Dd,Dn,#n uint64_t vrshrd_n_u64(uint64_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_N_S16: // RSHRN Vd.8B,Vn.8H,#n int8x8_t vrshrn_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_N_S32: // RSHRN Vd.4H,Vn.4S,#n int16x4_t vrshrn_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_N_S64: // RSHRN Vd.2S,Vn.2D,#n int32x2_t vrshrn_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_N_U16: // RSHRN Vd.8B,Vn.8H,#n uint8x8_t vrshrn_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_N_U32: // RSHRN Vd.4H,Vn.4S,#n uint16x4_t vrshrn_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VRSHRN_N_U64: // RSHRN Vd.2S,Vn.2D,#n uint32x2_t vrshrn_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VRSQRTE_U32: // URSQRTE Vd.2S,Vn.2S uint32x2_t vrsqrte_u32(uint32x2_t a)
+ case ARM64_INTRIN_VRSRA_N_S16: // SRSRA Vd.4H,Vn.4H,#n int16x4_t vrsra_n_s16(int16x4_t a, int16x4_t b, const int n)
+ case ARM64_INTRIN_VRSRA_N_S32: // SRSRA Vd.2S,Vn.2S,#n int32x2_t vrsra_n_s32(int32x2_t a, int32x2_t b, const int n)
+ case ARM64_INTRIN_VRSRA_N_S64: // SRSRA Dd,Dn,#n int64x1_t vrsra_n_s64(int64x1_t a, int64x1_t b, const int n)
+ case ARM64_INTRIN_VRSRA_N_S8: // SRSRA Vd.8B,Vn.8B,#n int8x8_t vrsra_n_s8(int8x8_t a, int8x8_t b, const int n)
+ case ARM64_INTRIN_VRSRA_N_U16: // URSRA Vd.4H,Vn.4H,#n uint16x4_t vrsra_n_u16(uint16x4_t a, uint16x4_t b, const int n)
+ case ARM64_INTRIN_VRSRA_N_U32: // URSRA Vd.2S,Vn.2S,#n uint32x2_t vrsra_n_u32(uint32x2_t a, uint32x2_t b, const int n)
+ case ARM64_INTRIN_VRSRA_N_U64: // URSRA Dd,Dn,#n uint64x1_t vrsra_n_u64(uint64x1_t a, uint64x1_t b, const int n)
+ case ARM64_INTRIN_VRSRA_N_U8: // URSRA Vd.8B,Vn.8B,#n uint8x8_t vrsra_n_u8(uint8x8_t a, uint8x8_t b, const int n)
+ case ARM64_INTRIN_VRSRAD_N_S64: // SRSRA Dd,Dn,#n int64_t vrsrad_n_s64(int64_t a, int64_t b, const int n)
+ case ARM64_INTRIN_VRSRAD_N_U64: // URSRA Dd,Dn,#n uint64_t vrsrad_n_u64(uint64_t a, uint64_t b, const int n)
+ case ARM64_INTRIN_VRSUBHN_S16: // RSUBHN Vd.8B,Vn.8H,Vm.8H int8x8_t vrsubhn_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VRSUBHN_S32: // RSUBHN Vd.4H,Vn.4S,Vm.4S int16x4_t vrsubhn_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VRSUBHN_S64: // RSUBHN Vd.2S,Vn.2D,Vm.2D int32x2_t vrsubhn_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VRSUBHN_U16: // RSUBHN Vd.8B,Vn.8H,Vm.8H uint8x8_t vrsubhn_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VRSUBHN_U32: // RSUBHN Vd.4H,Vn.4S,Vm.4S uint16x4_t vrsubhn_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VRSUBHN_U64: // RSUBHN Vd.2S,Vn.2D,Vm.2D uint32x2_t vrsubhn_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VSET_LANE_P16: // MOV Vd.H[lane],Rn poly16x4_t vset_lane_p16(poly16_t a, poly16x4_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_P64: // MOV Vd.D[lane],Rn poly64x1_t vset_lane_p64(poly64_t a, poly64x1_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_P8: // MOV Vd.B[lane],Rn poly8x8_t vset_lane_p8(poly8_t a, poly8x8_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_S16: // MOV Vd.H[lane],Rn int16x4_t vset_lane_s16(int16_t a, int16x4_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_S32: // MOV Vd.S[lane],Rn int32x2_t vset_lane_s32(int32_t a, int32x2_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_S64: // MOV Vd.D[lane],Rn int64x1_t vset_lane_s64(int64_t a, int64x1_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_S8: // MOV Vd.B[lane],Rn int8x8_t vset_lane_s8(int8_t a, int8x8_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_U16: // MOV Vd.H[lane],Rn uint16x4_t vset_lane_u16(uint16_t a, uint16x4_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_U32: // MOV Vd.S[lane],Rn uint32x2_t vset_lane_u32(uint32_t a, uint32x2_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_U64: // MOV Vd.D[lane],Rn uint64x1_t vset_lane_u64(uint64_t a, uint64x1_t v, const int lane)
+ case ARM64_INTRIN_VSET_LANE_U8: // MOV Vd.B[lane],Rn uint8x8_t vset_lane_u8(uint8_t a, uint8x8_t v, const int lane)
+ case ARM64_INTRIN_VSHL_N_S16: // SHL Vd.4H,Vn.4H,#n int16x4_t vshl_n_s16(int16x4_t a, const int n)
+ case ARM64_INTRIN_VSHL_N_S32: // SHL Vd.2S,Vn.2S,#n int32x2_t vshl_n_s32(int32x2_t a, const int n)
+ case ARM64_INTRIN_VSHL_N_S64: // SHL Dd,Dn,#n int64x1_t vshl_n_s64(int64x1_t a, const int n)
+ case ARM64_INTRIN_VSHL_N_S8: // SHL Vd.8B,Vn.8B,#n int8x8_t vshl_n_s8(int8x8_t a, const int n)
+ case ARM64_INTRIN_VSHL_N_U16: // SHL Vd.4H,Vn.4H,#n uint16x4_t vshl_n_u16(uint16x4_t a, const int n)
+ case ARM64_INTRIN_VSHL_N_U32: // SHL Vd.2S,Vn.2S,#n uint32x2_t vshl_n_u32(uint32x2_t a, const int n)
+ case ARM64_INTRIN_VSHL_N_U64: // SHL Dd,Dn,#n uint64x1_t vshl_n_u64(uint64x1_t a, const int n)
+ case ARM64_INTRIN_VSHL_N_U8: // SHL Vd.8B,Vn.8B,#n uint8x8_t vshl_n_u8(uint8x8_t a, const int n)
+ case ARM64_INTRIN_VSHL_S16: // SSHL Vd.4H,Vn.4H,Vm.4H int16x4_t vshl_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VSHL_S32: // SSHL Vd.2S,Vn.2S,Vm.2S int32x2_t vshl_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VSHL_S64: // SSHL Dd,Dn,Dm int64x1_t vshl_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VSHL_S8: // SSHL Vd.8B,Vn.8B,Vm.8B int8x8_t vshl_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VSHL_U16: // USHL Vd.4H,Vn.4H,Vm.4H uint16x4_t vshl_u16(uint16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VSHL_U32: // USHL Vd.2S,Vn.2S,Vm.2S uint32x2_t vshl_u32(uint32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VSHL_U64: // USHL Dd,Dn,Dm uint64x1_t vshl_u64(uint64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VSHL_U8: // USHL Vd.8B,Vn.8B,Vm.8B uint8x8_t vshl_u8(uint8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VSHLD_N_S64: // SHL Dd,Dn,#n int64_t vshld_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VSHLD_N_U64: // SHL Dd,Dn,#n uint64_t vshld_n_u64(uint64_t a, const int n)
+ case ARM64_INTRIN_VSHLD_S64: // SSHL Dd,Dn,Dm int64_t vshld_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VSHLD_U64: // USHL Dd,Dn,Dm uint64_t vshld_u64(uint64_t a, int64_t b)
+ case ARM64_INTRIN_VSHR_N_S16: // SSHR Vd.4H,Vn.4H,#n int16x4_t vshr_n_s16(int16x4_t a, const int n)
+ case ARM64_INTRIN_VSHR_N_S32: // SSHR Vd.2S,Vn.2S,#n int32x2_t vshr_n_s32(int32x2_t a, const int n)
+ case ARM64_INTRIN_VSHR_N_S64: // SSHR Dd,Dn,#n int64x1_t vshr_n_s64(int64x1_t a, const int n)
+ case ARM64_INTRIN_VSHR_N_S8: // SSHR Vd.8B,Vn.8B,#n int8x8_t vshr_n_s8(int8x8_t a, const int n)
+ case ARM64_INTRIN_VSHR_N_U16: // USHR Vd.4H,Vn.4H,#n uint16x4_t vshr_n_u16(uint16x4_t a, const int n)
+ case ARM64_INTRIN_VSHR_N_U32: // USHR Vd.2S,Vn.2S,#n uint32x2_t vshr_n_u32(uint32x2_t a, const int n)
+ case ARM64_INTRIN_VSHR_N_U64: // USHR Dd,Dn,#n uint64x1_t vshr_n_u64(uint64x1_t a, const int n)
+ case ARM64_INTRIN_VSHR_N_U8: // USHR Vd.8B,Vn.8B,#n uint8x8_t vshr_n_u8(uint8x8_t a, const int n)
+ case ARM64_INTRIN_VSHRD_N_S64: // SSHR Dd,Dn,#n int64_t vshrd_n_s64(int64_t a, const int n)
+ case ARM64_INTRIN_VSHRD_N_U64: // USHR Dd,Dn,#n uint64_t vshrd_n_u64(uint64_t a, const int n)
+ case ARM64_INTRIN_VSHRN_N_S16: // SHRN Vd.8B,Vn.8H,#n int8x8_t vshrn_n_s16(int16x8_t a, const int n)
+ case ARM64_INTRIN_VSHRN_N_S32: // SHRN Vd.4H,Vn.4S,#n int16x4_t vshrn_n_s32(int32x4_t a, const int n)
+ case ARM64_INTRIN_VSHRN_N_S64: // SHRN Vd.2S,Vn.2D,#n int32x2_t vshrn_n_s64(int64x2_t a, const int n)
+ case ARM64_INTRIN_VSHRN_N_U16: // SHRN Vd.8B,Vn.8H,#n uint8x8_t vshrn_n_u16(uint16x8_t a, const int n)
+ case ARM64_INTRIN_VSHRN_N_U32: // SHRN Vd.4H,Vn.4S,#n uint16x4_t vshrn_n_u32(uint32x4_t a, const int n)
+ case ARM64_INTRIN_VSHRN_N_U64: // SHRN Vd.2S,Vn.2D,#n uint32x2_t vshrn_n_u64(uint64x2_t a, const int n)
+ case ARM64_INTRIN_VSLI_N_P16: // SLI Vd.4H,Vn.4H,#n poly16x4_t vsli_n_p16(poly16x4_t a, poly16x4_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_P64: // SLI Dd,Dn,#n poly64x1_t vsli_n_p64(poly64x1_t a, poly64x1_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_P8: // SLI Vd.8B,Vn.8B,#n poly8x8_t vsli_n_p8(poly8x8_t a, poly8x8_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_S16: // SLI Vd.4H,Vn.4H,#n int16x4_t vsli_n_s16(int16x4_t a, int16x4_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_S32: // SLI Vd.2S,Vn.2S,#n int32x2_t vsli_n_s32(int32x2_t a, int32x2_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_S64: // SLI Dd,Dn,#n int64x1_t vsli_n_s64(int64x1_t a, int64x1_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_S8: // SLI Vd.8B,Vn.8B,#n int8x8_t vsli_n_s8(int8x8_t a, int8x8_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_U16: // SLI Vd.4H,Vn.4H,#n uint16x4_t vsli_n_u16(uint16x4_t a, uint16x4_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_U32: // SLI Vd.2S,Vn.2S,#n uint32x2_t vsli_n_u32(uint32x2_t a, uint32x2_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_U64: // SLI Dd,Dn,#n uint64x1_t vsli_n_u64(uint64x1_t a, uint64x1_t b, const int n)
+ case ARM64_INTRIN_VSLI_N_U8: // SLI Vd.8B,Vn.8B,#n uint8x8_t vsli_n_u8(uint8x8_t a, uint8x8_t b, const int n)
+ case ARM64_INTRIN_VSLID_N_S64: // SLI Dd,Dn,#n int64_t vslid_n_s64(int64_t a, int64_t b, const int n)
+ case ARM64_INTRIN_VSLID_N_U64: // SLI Dd,Dn,#n uint64_t vslid_n_u64(uint64_t a, uint64_t b, const int n)
+ case ARM64_INTRIN_VSQADD_U16: // USQADD Vd.4H,Vn.4H uint16x4_t vsqadd_u16(uint16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VSQADD_U32: // USQADD Vd.2S,Vn.2S uint32x2_t vsqadd_u32(uint32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VSQADD_U64: // USQADD Dd,Dn uint64x1_t vsqadd_u64(uint64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VSQADD_U8: // USQADD Vd.8B,Vn.8B uint8x8_t vsqadd_u8(uint8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VSQADDD_U64: // USQADD Dd,Dn uint64_t vsqaddd_u64(uint64_t a, int64_t b)
+ case ARM64_INTRIN_VSRA_N_S16: // SSRA Vd.4H,Vn.4H,#n int16x4_t vsra_n_s16(int16x4_t a, int16x4_t b, const int n)
+ case ARM64_INTRIN_VSRA_N_S32: // SSRA Vd.2S,Vn.2S,#n int32x2_t vsra_n_s32(int32x2_t a, int32x2_t b, const int n)
+ case ARM64_INTRIN_VSRA_N_S64: // SSRA Dd,Dn,#n int64x1_t vsra_n_s64(int64x1_t a, int64x1_t b, const int n)
+ case ARM64_INTRIN_VSRA_N_S8: // SSRA Vd.8B,Vn.8B,#n int8x8_t vsra_n_s8(int8x8_t a, int8x8_t b, const int n)
+ case ARM64_INTRIN_VSRA_N_U16: // USRA Vd.4H,Vn.4H,#n uint16x4_t vsra_n_u16(uint16x4_t a, uint16x4_t b, const int n)
+ case ARM64_INTRIN_VSRA_N_U32: // USRA Vd.2S,Vn.2S,#n uint32x2_t vsra_n_u32(uint32x2_t a, uint32x2_t b, const int n)
+ case ARM64_INTRIN_VSRA_N_U64: // USRA Dd,Dn,#n uint64x1_t vsra_n_u64(uint64x1_t a, uint64x1_t b, const int n)
+ case ARM64_INTRIN_VSRA_N_U8: // USRA Vd.8B,Vn.8B,#n uint8x8_t vsra_n_u8(uint8x8_t a, uint8x8_t b, const int n)
+ case ARM64_INTRIN_VSRAD_N_S64: // SSRA Dd,Dn,#n int64_t vsrad_n_s64(int64_t a, int64_t b, const int n)
+ case ARM64_INTRIN_VSRAD_N_U64: // USRA Dd,Dn,#n uint64_t vsrad_n_u64(uint64_t a, uint64_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_P16: // SRI Vd.4H,Vn.4H,#n poly16x4_t vsri_n_p16(poly16x4_t a, poly16x4_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_P64: // SRI Dd,Dn,#n poly64x1_t vsri_n_p64(poly64x1_t a, poly64x1_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_P8: // SRI Vd.8B,Vn.8B,#n poly8x8_t vsri_n_p8(poly8x8_t a, poly8x8_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_S16: // SRI Vd.4H,Vn.4H,#n int16x4_t vsri_n_s16(int16x4_t a, int16x4_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_S32: // SRI Vd.2S,Vn.2S,#n int32x2_t vsri_n_s32(int32x2_t a, int32x2_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_S64: // SRI Dd,Dn,#n int64x1_t vsri_n_s64(int64x1_t a, int64x1_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_S8: // SRI Vd.8B,Vn.8B,#n int8x8_t vsri_n_s8(int8x8_t a, int8x8_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_U16: // SRI Vd.4H,Vn.4H,#n uint16x4_t vsri_n_u16(uint16x4_t a, uint16x4_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_U32: // SRI Vd.2S,Vn.2S,#n uint32x2_t vsri_n_u32(uint32x2_t a, uint32x2_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_U64: // SRI Dd,Dn,#n uint64x1_t vsri_n_u64(uint64x1_t a, uint64x1_t b, const int n)
+ case ARM64_INTRIN_VSRI_N_U8: // SRI Vd.8B,Vn.8B,#n uint8x8_t vsri_n_u8(uint8x8_t a, uint8x8_t b, const int n)
+ case ARM64_INTRIN_VSRID_N_S64: // SRI Dd,Dn,#n int64_t vsrid_n_s64(int64_t a, int64_t b, const int n)
+ case ARM64_INTRIN_VSRID_N_U64: // SRI Dd,Dn,#n uint64_t vsrid_n_u64(uint64_t a, uint64_t b, const int n)
+ case ARM64_INTRIN_VSUB_S16: // SUB Vd.4H,Vn.4H,Vm.4H int16x4_t vsub_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VSUB_S32: // SUB Vd.2S,Vn.2S,Vm.2S int32x2_t vsub_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VSUB_S64: // SUB Dd,Dn,Dm int64x1_t vsub_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VSUB_S8: // SUB Vd.8B,Vn.8B,Vm.8B int8x8_t vsub_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VSUB_U16: // SUB Vd.4H,Vn.4H,Vm.4H uint16x4_t vsub_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VSUB_U32: // SUB Vd.2S,Vn.2S,Vm.2S uint32x2_t vsub_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VSUB_U64: // SUB Dd,Dn,Dm uint64x1_t vsub_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VSUB_U8: // SUB Vd.8B,Vn.8B,Vm.8B uint8x8_t vsub_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VSUBD_S64: // SUB Dd,Dn,Dm int64_t vsubd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VSUBD_U64: // SUB Dd,Dn,Dm uint64_t vsubd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VSUBHN_S16: // SUBHN Vd.8B,Vn.8H,Vm.8H int8x8_t vsubhn_s16(int16x8_t a, int16x8_t b)
+ case ARM64_INTRIN_VSUBHN_S32: // SUBHN Vd.4H,Vn.4S,Vm.4S int16x4_t vsubhn_s32(int32x4_t a, int32x4_t b)
+ case ARM64_INTRIN_VSUBHN_S64: // SUBHN Vd.2S,Vn.2D,Vm.2D int32x2_t vsubhn_s64(int64x2_t a, int64x2_t b)
+ case ARM64_INTRIN_VSUBHN_U16: // SUBHN Vd.8B,Vn.8H,Vm.8H uint8x8_t vsubhn_u16(uint16x8_t a, uint16x8_t b)
+ case ARM64_INTRIN_VSUBHN_U32: // SUBHN Vd.4H,Vn.4S,Vm.4S uint16x4_t vsubhn_u32(uint32x4_t a, uint32x4_t b)
+ case ARM64_INTRIN_VSUBHN_U64: // SUBHN Vd.2S,Vn.2D,Vm.2D uint32x2_t vsubhn_u64(uint64x2_t a, uint64x2_t b)
+ case ARM64_INTRIN_VSUDOT_LANE_S32: // SUDOT Vd.2S,Vn.8B,Vm.4B[lane] int32x2_t vsudot_lane_s32(int32x2_t r, int8x8_t a, uint8x8_t b, const int lane)
+ case ARM64_INTRIN_VSUDOT_LANEQ_S32: // SUDOT Vd.2S,Vn.8B,Vm.4B[lane] int32x2_t vsudot_laneq_s32(int32x2_t r, int8x8_t a, uint8x16_t b, const int lane)
+ case ARM64_INTRIN_VTRN1_P16: // TRN1 Vd.4H,Vn.4H,Vm.4H poly16x4_t vtrn1_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VTRN1_P8: // TRN1 Vd.8B,Vn.8B,Vm.8B poly8x8_t vtrn1_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VTRN1_S16: // TRN1 Vd.4H,Vn.4H,Vm.4H int16x4_t vtrn1_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VTRN1_S32: // TRN1 Vd.2S,Vn.2S,Vm.2S int32x2_t vtrn1_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VTRN1_S8: // TRN1 Vd.8B,Vn.8B,Vm.8B int8x8_t vtrn1_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VTRN1_U16: // TRN1 Vd.4H,Vn.4H,Vm.4H uint16x4_t vtrn1_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VTRN1_U32: // TRN1 Vd.2S,Vn.2S,Vm.2S uint32x2_t vtrn1_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VTRN1_U8: // TRN1 Vd.8B,Vn.8B,Vm.8B uint8x8_t vtrn1_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VTRN2_P16: // TRN2 Vd.4H,Vn.4H,Vm.4H poly16x4_t vtrn2_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VTRN2_P8: // TRN2 Vd.8B,Vn.8B,Vm.8B poly8x8_t vtrn2_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VTRN2_S16: // TRN2 Vd.4H,Vn.4H,Vm.4H int16x4_t vtrn2_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VTRN2_S32: // TRN2 Vd.2S,Vn.2S,Vm.2S int32x2_t vtrn2_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VTRN2_S8: // TRN2 Vd.8B,Vn.8B,Vm.8B int8x8_t vtrn2_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VTRN2_U16: // TRN2 Vd.4H,Vn.4H,Vm.4H uint16x4_t vtrn2_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VTRN2_U32: // TRN2 Vd.2S,Vn.2S,Vm.2S uint32x2_t vtrn2_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VTRN2_U8: // TRN2 Vd.8B,Vn.8B,Vm.8B uint8x8_t vtrn2_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VTST_P64: // CMTST Dd,Dn,Dm uint64x1_t vtst_p64(poly64x1_t a, poly64x1_t b)
+ case ARM64_INTRIN_VTST_P8: // CMTST Vd.8B,Vn.8B,Vm.8B uint8x8_t vtst_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VTST_S16: // CMTST Vd.4H,Vn.4H,Vm.4H uint16x4_t vtst_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VTST_S32: // CMTST Vd.2S,Vn.2S,Vm.2S uint32x2_t vtst_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VTST_S64: // CMTST Dd,Dn,Dm uint64x1_t vtst_s64(int64x1_t a, int64x1_t b)
+ case ARM64_INTRIN_VTST_S8: // CMTST Vd.8B,Vn.8B,Vm.8B uint8x8_t vtst_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VTST_U16: // CMTST Vd.4H,Vn.4H,Vm.4H uint16x4_t vtst_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VTST_U32: // CMTST Vd.2S,Vn.2S,Vm.2S uint32x2_t vtst_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VTST_U64: // CMTST Dd,Dn,Dm uint64x1_t vtst_u64(uint64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VTST_U8: // CMTST Vd.8B,Vn.8B,Vm.8B uint8x8_t vtst_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VTSTD_S64: // CMTST Dd,Dn,Dm uint64_t vtstd_s64(int64_t a, int64_t b)
+ case ARM64_INTRIN_VTSTD_U64: // CMTST Dd,Dn,Dm uint64_t vtstd_u64(uint64_t a, uint64_t b)
+ case ARM64_INTRIN_VUQADD_S16: // SUQADD Vd.4H,Vn.4H int16x4_t vuqadd_s16(int16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VUQADD_S32: // SUQADD Vd.2S,Vn.2S int32x2_t vuqadd_s32(int32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VUQADD_S64: // SUQADD Dd,Dn int64x1_t vuqadd_s64(int64x1_t a, uint64x1_t b)
+ case ARM64_INTRIN_VUQADD_S8: // SUQADD Vd.8B,Vn.8B int8x8_t vuqadd_s8(int8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VUQADDD_S64: // SUQADD Dd,Dn int64_t vuqaddd_s64(int64_t a, uint64_t b)
+ case ARM64_INTRIN_VUSDOT_LANE_S32: // USDOT Vd.2S,Vn.8B,Vm.4B[lane] int32x2_t vusdot_lane_s32(int32x2_t r, uint8x8_t a, int8x8_t b, const int lane)
+ case ARM64_INTRIN_VUSDOT_LANEQ_S32: // USDOT Vd.2S,Vn.8B,Vm.4B[lane] int32x2_t vusdot_laneq_s32(int32x2_t r, uint8x8_t a, int8x16_t b, const int lane)
+ case ARM64_INTRIN_VUSDOT_S32: // USDOT Vd.2S,Vn.8B,Vm.8B int32x2_t vusdot_s32(int32x2_t r, uint8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VUZP1_P16: // UZP1 Vd.4H,Vn.4H,Vm.4H poly16x4_t vuzp1_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VUZP1_P8: // UZP1 Vd.8B,Vn.8B,Vm.8B poly8x8_t vuzp1_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VUZP1_S16: // UZP1 Vd.4H,Vn.4H,Vm.4H int16x4_t vuzp1_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VUZP1_S32: // UZP1 Vd.2S,Vn.2S,Vm.2S int32x2_t vuzp1_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VUZP1_S8: // UZP1 Vd.8B,Vn.8B,Vm.8B int8x8_t vuzp1_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VUZP1_U16: // UZP1 Vd.4H,Vn.4H,Vm.4H uint16x4_t vuzp1_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VUZP1_U32: // UZP1 Vd.2S,Vn.2S,Vm.2S uint32x2_t vuzp1_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VUZP1_U8: // UZP1 Vd.8B,Vn.8B,Vm.8B uint8x8_t vuzp1_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VUZP2_P16: // UZP2 Vd.4H,Vn.4H,Vm.4H poly16x4_t vuzp2_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VUZP2_P8: // UZP2 Vd.8B,Vn.8B,Vm.8B poly8x8_t vuzp2_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VUZP2_S16: // UZP2 Vd.4H,Vn.4H,Vm.4H int16x4_t vuzp2_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VUZP2_S32: // UZP2 Vd.2S,Vn.2S,Vm.2S int32x2_t vuzp2_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VUZP2_S8: // UZP2 Vd.8B,Vn.8B,Vm.8B int8x8_t vuzp2_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VUZP2_U16: // UZP2 Vd.4H,Vn.4H,Vm.4H uint16x4_t vuzp2_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VUZP2_U32: // UZP2 Vd.2S,Vn.2S,Vm.2S uint32x2_t vuzp2_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VUZP2_U8: // UZP2 Vd.8B,Vn.8B,Vm.8B uint8x8_t vuzp2_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VZIP1_P16: // ZIP1 Vd.4H,Vn.4H,Vm.4H poly16x4_t vzip1_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VZIP1_P8: // ZIP1 Vd.8B,Vn.8B,Vm.8B poly8x8_t vzip1_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VZIP1_S16: // ZIP1 Vd.4H,Vn.4H,Vm.4H int16x4_t vzip1_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VZIP1_S32: // ZIP1 Vd.2S,Vn.2S,Vm.2S int32x2_t vzip1_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VZIP1_S8: // ZIP1 Vd.8B,Vn.8B,Vm.8B int8x8_t vzip1_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VZIP1_U16: // ZIP1 Vd.4H,Vn.4H,Vm.4H uint16x4_t vzip1_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VZIP1_U32: // ZIP1 Vd.2S,Vn.2S,Vm.2S uint32x2_t vzip1_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VZIP1_U8: // ZIP1 Vd.8B,Vn.8B,Vm.8B uint8x8_t vzip1_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VZIP2_P16: // ZIP2 Vd.4H,Vn.4H,Vm.4H poly16x4_t vzip2_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VZIP2_P8: // ZIP2 Vd.8B,Vn.8B,Vm.8B poly8x8_t vzip2_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VZIP2_S16: // ZIP2 Vd.4H,Vn.4H,Vm.4H int16x4_t vzip2_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VZIP2_S32: // ZIP2 Vd.2S,Vn.2S,Vm.2S int32x2_t vzip2_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VZIP2_S8: // ZIP2 Vd.8B,Vn.8B,Vm.8B int8x8_t vzip2_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VZIP2_U16: // ZIP2 Vd.4H,Vn.4H,Vm.4H uint16x4_t vzip2_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VZIP2_U32: // ZIP2 Vd.2S,Vn.2S,Vm.2S uint32x2_t vzip2_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VZIP2_U8: // ZIP2 Vd.8B,Vn.8B,Vm.8B uint8x8_t vzip2_u8(uint8x8_t a, uint8x8_t b)
+ return {Type::IntegerType(8, false)};
+ case ARM64_INTRIN_VTRN_P16: // TRN1 Vd1.4H,Vn.4H,Vm.4H poly16x4x2_t vtrn_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VTRN_P8: // TRN1 Vd1.8B,Vn.8B,Vm.8B poly8x8x2_t vtrn_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VTRN_S16: // TRN1 Vd1.4H,Vn.4H,Vm.4H int16x4x2_t vtrn_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VTRN_S32: // TRN1 Vd1.2S,Vn.2S,Vm.2S int32x2x2_t vtrn_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VTRN_S8: // TRN1 Vd1.8B,Vn.8B,Vm.8B int8x8x2_t vtrn_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VTRN_U16: // TRN1 Vd1.4H,Vn.4H,Vm.4H uint16x4x2_t vtrn_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VTRN_U32: // TRN1 Vd1.2S,Vn.2S,Vm.2S uint32x2x2_t vtrn_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VTRN_U8: // TRN1 Vd1.8B,Vn.8B,Vm.8B uint8x8x2_t vtrn_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VUZP_P16: // UZP1 Vd1.4H,Vn.4H,Vm.4H poly16x4x2_t vuzp_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VUZP_P8: // UZP1 Vd1.8B,Vn.8B,Vm.8B poly8x8x2_t vuzp_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VUZP_S16: // UZP1 Vd1.4H,Vn.4H,Vm.4H int16x4x2_t vuzp_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VUZP_S32: // UZP1 Vd1.2S,Vn.2S,Vm.2S int32x2x2_t vuzp_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VUZP_S8: // UZP1 Vd1.8B,Vn.8B,Vm.8B int8x8x2_t vuzp_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VUZP_U16: // UZP1 Vd1.4H,Vn.4H,Vm.4H uint16x4x2_t vuzp_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VUZP_U32: // UZP1 Vd1.2S,Vn.2S,Vm.2S uint32x2x2_t vuzp_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VUZP_U8: // UZP1 Vd1.8B,Vn.8B,Vm.8B uint8x8x2_t vuzp_u8(uint8x8_t a, uint8x8_t b)
+ case ARM64_INTRIN_VZIP_P16: // ZIP1 Vd1.4H,Vn.4H,Vm.4H poly16x4x2_t vzip_p16(poly16x4_t a, poly16x4_t b)
+ case ARM64_INTRIN_VZIP_P8: // ZIP1 Vd1.8B,Vn.8B,Vm.8B poly8x8x2_t vzip_p8(poly8x8_t a, poly8x8_t b)
+ case ARM64_INTRIN_VZIP_S16: // ZIP1 Vd1.4H,Vn.4H,Vm.4H int16x4x2_t vzip_s16(int16x4_t a, int16x4_t b)
+ case ARM64_INTRIN_VZIP_S32: // ZIP1 Vd1.2S,Vn.2S,Vm.2S int32x2x2_t vzip_s32(int32x2_t a, int32x2_t b)
+ case ARM64_INTRIN_VZIP_S8: // ZIP1 Vd1.8B,Vn.8B,Vm.8B int8x8x2_t vzip_s8(int8x8_t a, int8x8_t b)
+ case ARM64_INTRIN_VZIP_U16: // ZIP1 Vd1.4H,Vn.4H,Vm.4H uint16x4x2_t vzip_u16(uint16x4_t a, uint16x4_t b)
+ case ARM64_INTRIN_VZIP_U32: // ZIP1 Vd1.2S,Vn.2S,Vm.2S uint32x2x2_t vzip_u32(uint32x2_t a, uint32x2_t b)
+ case ARM64_INTRIN_VZIP_U8: // ZIP1 Vd1.8B,Vn.8B,Vm.8B uint8x8x2_t vzip_u8(uint8x8_t a, uint8x8_t b)
+ return {Type::IntegerType(8, false), Type::IntegerType(8, false)};
+
default:
return vector<Confidence<Ref<Type>>>();
}
@@ -13825,9 +14391,9 @@ static void add_input_reg(
}
static void add_input_imm(
- vector<ExprId>& inputs, LowLevelILFunction& il, InstructionOperand& operand)
+ vector<ExprId>& inputs, LowLevelILFunction& il, InstructionOperand& operand, size_t size=0)
{
- inputs.push_back(il.Const(0, operand.immediate));
+ inputs.push_back(il.Const(size, operand.immediate));
}
static void add_input_lane(
@@ -13858,17 +14424,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_ABS_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VABS_S8; // ABS Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VABSQ_S8; // ABS Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VABS_S16; // ABS Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VABSQ_S16; // ABS Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VABS_S32; // ABS Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VABSQ_S32; // ABS Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VABSQ_S64; // ABS Vd.2D,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -13879,67 +14445,76 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_ADDHN_ASIMDDIFF_N:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VADDHN_S16; // ADDHN Vd.8B,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VADDHN_S32; // ADDHN Vd.4H,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VADDHN_S64; // ADDHN Vd.2S,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VADDHN_U16; // ADDHN Vd.8B,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VADDHN_U32; // ADDHN Vd.4H,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VADDHN_U64; // ADDHN Vd.2S,Vn.2D,Vm.2D
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VADDHN_HIGH_S16; // ADDHN2 Vd.16B,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VADDHN_HIGH_S32; // ADDHN2 Vd.8H,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VADDHN_HIGH_S64; // ADDHN2 Vd.4S,Vn.2D,Vm.2D
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint8x16_t vaddhn_high_u16(uint8x8_t r, uint16x8_t a, uint16x8_t b)
+ // argprep: r -> Vd.8B; a -> Vn.8H; b -> Vm.8H
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VADDHN_HIGH_U16; // ADDHN2 Vd.16B,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint16x8_t vaddhn_high_u32(uint16x4_t r, uint32x4_t a, uint32x4_t b)
+ // argprep: r -> Vd.4H; a -> Vn.4S; b -> Vm.4S
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VADDHN_HIGH_U32; // ADDHN2 Vd.8H,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint32x4_t vaddhn_high_u64(uint32x2_t r, uint64x2_t a, uint64x2_t b)
+ // argprep: r -> Vd.2S; a -> Vn.2D; b -> Vm.2D
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VADDHN_HIGH_U64; // ADDHN2 Vd.4S,Vn.2D,Vm.2D
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint8x8_t vaddhn_u16(uint16x8_t a, uint16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VADDHN_U16; // ADDHN Vd.8B,Vn.8H,Vm.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint16x4_t vaddhn_u32(uint32x4_t a, uint32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VADDHN_U32; // ADDHN Vd.4H,Vn.4S,Vm.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint32x2_t vaddhn_u64(uint64x2_t a, uint64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VADDHN_U64; // ADDHN Vd.2S,Vn.2D,Vm.2D
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_ADDP_ASIMDSAME_ONLY:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VPADD_S8; // ADDP Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VPADD_S16; // ADDP Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VPADD_S32; // ADDP Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VPADD_U8; // ADDP Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VPADD_U16; // ADDP Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vpadd_u32(uint32x2_t a, uint32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VPADD_U32; // ADDP Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VPADDQ_S8; // ADDP Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VPADDQ_S16; // ADDP Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VPADDQ_S32; // ADDP Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VPADDQ_S64; // ADDP Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VPADDQ_U8; // ADDP Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vpadd_u16(uint16x4_t a, uint16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VPADD_U16; // ADDP Vd.4H,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // uint8x8_t vpadd_u8(uint8x8_t a, uint8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VPADD_U8; // ADDP Vd.8B,Vn.8B,Vm.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vpaddq_u16(uint16x8_t a, uint16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VPADDQ_U16; // ADDP Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vpaddq_u32(uint32x4_t a, uint32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VPADDQ_U32; // ADDP Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vpaddq_u64(uint64x2_t a, uint64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VPADDQ_U64; // ADDP Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VADDV_S32; // ADDP Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VADDV_U32; // ADDP Vd.2S,Vn.2S,Vm.2S
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // uint8x16_t vpaddq_u8(uint8x16_t a, uint8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VPADDQ_U8; // ADDP Vd.16B,Vn.16B,Vm.16B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -13950,39 +14525,70 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_ADDV_ASIMDALL_ONLY:
- intrin_id = ARM64_INTRIN_VADDV_S8; // ADDV Bd,Vn.8B
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // uint16_t vaddv_u16(uint16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VADDV_U16; // ADDV Hd,Vn.4H
+ else if ((instr.operands[0].reg[0] >= REG_B0 && instr.operands[0].reg[0] <= REG_B31) && instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ // uint8_t vaddv_u8(uint8x8_t a)
+ // argprep: a -> Vn.8B
+ // results: Bd -> result
+ intrin_id = ARM64_INTRIN_VADDV_U8; // ADDV Bd,Vn.8B
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint16_t vaddvq_u16(uint16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VADDVQ_U16; // ADDV Hd,Vn.8H
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint32_t vaddvq_u32(uint32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VADDVQ_U32; // ADDV Sd,Vn.4S
+ else if ((instr.operands[0].reg[0] >= REG_B0 && instr.operands[0].reg[0] <= REG_B31) && instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ // uint8_t vaddvq_u8(uint8x16_t a)
+ // argprep: a -> Vn.16B
+ // results: Bd -> result
+ intrin_id = ARM64_INTRIN_VADDVQ_U8; // ADDV Bd,Vn.16B
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_ADD_ASIMDSAME_ONLY:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VADD_S8; // ADD Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VADDQ_S8; // ADD Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VADD_S16; // ADD Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VADDQ_S16; // ADD Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VADD_S32; // ADD Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VADDQ_S32; // ADD Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VADDQ_S64; // ADD Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VADD_U8; // ADD Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VADDQ_U8; // ADD Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vadd_u16(uint16x4_t a, uint16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VADD_U16; // ADD Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VADDQ_U16; // ADD Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vadd_u32(uint32x2_t a, uint32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VADD_U32; // ADD Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // uint8x8_t vadd_u8(uint8x8_t a, uint8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VADD_U8; // ADD Vd.8B,Vn.8B,Vm.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vaddq_u16(uint16x8_t a, uint16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VADDQ_U16; // ADD Vd.8H,Vn.8H,Vm.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vaddq_u32(uint32x4_t a, uint32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VADDQ_U32; // ADD Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vaddq_u64(uint64x2_t a, uint64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VADDQ_U64; // ADD Vd.2D,Vn.2D,Vm.2D
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // uint8x16_t vaddq_u8(uint8x16_t a, uint8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VADDQ_U8; // ADD Vd.16B,Vn.16B,Vm.16B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -14018,34 +14624,34 @@ bool NeonGetLowLevelILForInstruction(
case ENC_AND_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VAND_S8; // AND Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VANDQ_S8; // AND Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VAND_S16; // AND Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VANDQ_S16; // AND Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VAND_S32; // AND Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VANDQ_S32; // AND Vd.16B,Vn.16B,Vm.16B
// if(None) intrin_id = ARM64_INTRIN_VAND_S64; // AND Dd,Dn,Dm
if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VANDQ_S64; // AND Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VAND_U8; // AND Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VANDQ_U8; // AND Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VAND_U16; // AND Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VANDQ_U16; // AND Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VAND_U32; // AND Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VANDQ_U32; // AND Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VAND_U64; // AND Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VANDQ_U64; // AND Vd.16B,Vn.16B,Vm.16B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -14054,19 +14660,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_BCAX_VVV16_CRYPTO4:
if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VBCAXQ_U8; // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VBCAXQ_U16; // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VBCAXQ_U32; // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VBCAXQ_U64; // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VBCAXQ_S8; // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VBCAXQ_S16; // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VBCAXQ_S32; // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VBCAXQ_S64; // BCAX Vd.16B,Vn.16B,Vm.16B,Va.16B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -14076,9 +14682,9 @@ bool NeonGetLowLevelILForInstruction(
case ENC_BFCVTN_ASIMDMISC_4S:
if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCVT_BF16_F32; // BFCVTN Vd.4H,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCVTQ_LOW_BF16_F32; // BFCVTN Vd.4H,Vn.4S
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VCVTQ_HIGH_BF16_F32; // BFCVTN2 Vd.8H,Vn.4S
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -14091,11 +14697,11 @@ bool NeonGetLowLevelILForInstruction(
case ENC_BFDOT_ASIMDELEM_E:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VBFDOT_LANE_F32; // BFDOT Vd.2S,Vn.4H,Vm.2H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VBFDOTQ_LANEQ_F32; // BFDOT Vd.4S,Vn.8H,Vm.2H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VBFDOT_LANEQ_F32; // BFDOT Vd.2S,Vn.4H,Vm.2H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VBFDOTQ_LANE_F32; // BFDOT Vd.4S,Vn.8H,Vm.2H[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -14106,13 +14712,46 @@ bool NeonGetLowLevelILForInstruction(
case ENC_BFDOT_ASIMDSAME2_D:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VBFDOT_F32; // BFDOT Vd.2S,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VBFDOTQ_F32; // BFDOT Vd.4S,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_BFMLAL_ASIMDELEM_F:
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // float32x4_t vbfmlalbq_laneq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b, const int lane)
+ // argprep: r -> Vd.4S; a -> Vn.8H; b -> Vm.8H; lane -> <lane>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VBFMLALBQ_LANEQ_F32; // BFMLALB Vd.4S,Vn.8H,Vm.H[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // float32x4_t vbfmlaltq_laneq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b, const int lane)
+ // argprep: r -> Vd.4S; a -> Vn.8H; b -> Vm.8H; lane -> <lane>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VBFMLALTQ_LANEQ_F32; // BFMLALT Vd.4S,Vn.8H,Vm.H[lane]
+ add_input_reg(inputs, il, instr.operands[0]);
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_input_lane(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_BFMLAL_ASIMDSAME2_F_:
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // float32x4_t vbfmlalbq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b)
+ // argprep: r -> Vd.4S; a -> Vn.8H; b -> Vm.8H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VBFMLALBQ_F32; // BFMLALB Vd.4S,Vn.8H,Vm.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // float32x4_t vbfmlaltq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b)
+ // argprep: r -> Vd.4S; a -> Vn.8H; b -> Vm.8H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VBFMLALTQ_F32; // BFMLALT Vd.4S,Vn.8H,Vm.8H
+ add_input_reg(inputs, il, instr.operands[0]);
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_BFMMLA_ASIMDSAME2_E:
intrin_id = ARM64_INTRIN_VBFMMLAQ_F32; // BFMMLA Vd.4S,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[0]);
@@ -14123,7 +14762,7 @@ bool NeonGetLowLevelILForInstruction(
case ENC_BIC_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VBIC_S8; // BIC Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VBICQ_S8; // BIC Vd.16B,Vn.16B,Vm.16B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -14134,7 +14773,7 @@ bool NeonGetLowLevelILForInstruction(
// Although, the bit instruction is just a bsl instruction with a specific operand order.
if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VBSL_S8; // BSL Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VBSLQ_S8; // BSL Vd.16B,Vn.16B,Vm.16B
// As per bsl & bit documentation:
//
@@ -14160,7 +14799,7 @@ bool NeonGetLowLevelILForInstruction(
// Although, the bif instruction is just a bsl instruction with a specific operand order.
if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VBSL_S8; // BIF Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VBSLQ_S8; // BIF Vd.16B,Vn.16B,Vm.16B
// As per BSL documentation:
//
@@ -14184,7 +14823,7 @@ bool NeonGetLowLevelILForInstruction(
case ENC_BSL_ASIMDSAME_ONLY:
if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VBSL_S8; // BSL Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VBSLQ_S8; // BSL Vd.16B,Vn.16B,Vm.16B
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -14192,134 +14831,149 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_CLS_ASIMDMISC_R:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCLS_S8; // CLS Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCLSQ_S8; // CLS Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCLS_S16; // CLS Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCLSQ_S16; // CLS Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCLS_S32; // CLS Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCLSQ_S32; // CLS Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCLS_U8; // CLS Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCLSQ_U8; // CLS Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // int16x4_t vcls_u16(uint16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCLS_U16; // CLS Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCLSQ_U16; // CLS Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // int32x2_t vcls_u32(uint32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCLS_U32; // CLS Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ // int8x8_t vcls_u8(uint8x8_t a)
+ // argprep: a -> Vn.8B
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VCLS_U8; // CLS Vd.8B,Vn.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // int16x8_t vclsq_u16(uint16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCLSQ_U16; // CLS Vd.8H,Vn.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // int32x4_t vclsq_u32(uint32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCLSQ_U32; // CLS Vd.4S,Vn.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ // int8x16_t vclsq_u8(uint8x16_t a)
+ // argprep: a -> Vn.16B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VCLSQ_U8; // CLS Vd.16B,Vn.16B
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_CLZ_ASIMDMISC_R:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCLZ_S8; // CLZ Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCLZQ_S8; // CLZ Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCLZ_S16; // CLZ Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCLZQ_S16; // CLZ Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCLZ_S32; // CLZ Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCLZQ_S32; // CLZ Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCLZ_U8; // CLZ Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCLZQ_U8; // CLZ Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vclz_u16(uint16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCLZ_U16; // CLZ Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCLZQ_U16; // CLZ Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vclz_u32(uint32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCLZ_U32; // CLZ Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ // uint8x8_t vclz_u8(uint8x8_t a)
+ // argprep: a -> Vn.8B
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VCLZ_U8; // CLZ Vd.8B,Vn.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vclzq_u16(uint16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCLZQ_U16; // CLZ Vd.8H,Vn.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vclzq_u32(uint32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCLZQ_U32; // CLZ Vd.4S,Vn.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ // uint8x16_t vclzq_u8(uint8x16_t a)
+ // argprep: a -> Vn.16B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VCLZQ_U8; // CLZ Vd.16B,Vn.16B
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_CMEQ_ASIMDMISC_Z:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCEQZ_S8; // CMEQ Vd.8B,Vn.8B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCEQZQ_S8; // CMEQ Vd.16B,Vn.16B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCEQZ_S16; // CMEQ Vd.4H,Vn.4H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCEQZQ_S16; // CMEQ Vd.8H,Vn.8H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCEQZ_S32; // CMEQ Vd.2S,Vn.2S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCEQZQ_S32; // CMEQ Vd.4S,Vn.4S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint8x8_t vceqz_u8(uint8x8_t a)
+ // argprep: a -> Vn.8B
+ // results: Vd.8B -> result
intrin_id = ARM64_INTRIN_VCEQZ_U8; // CMEQ Vd.8B,Vn.8B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCEQZQ_U8; // CMEQ Vd.16B,Vn.16B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16x4_t vceqz_u16(uint16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCEQZ_U16; // CMEQ Vd.4H,Vn.4H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCEQZQ_U16; // CMEQ Vd.8H,Vn.8H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32x2_t vceqz_u32(uint32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCEQZ_U32; // CMEQ Vd.2S,Vn.2S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCEQZQ_U32; // CMEQ Vd.4S,Vn.4S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCEQZ_P8; // CMEQ Vd.8B,Vn.8B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCEQZQ_P8; // CMEQ Vd.16B,Vn.16B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VCEQZQ_S64; // CMEQ Vd.2D,Vn.2D,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint64x2_t vceqzq_u64(uint64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCEQZQ_U64; // CMEQ Vd.2D,Vn.2D,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VCEQZQ_P64; // CMEQ Vd.2D,Vn.2D,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint8x16_t vceqzq_u8(uint8x16_t a)
+ // argprep: a -> Vn.16B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VCEQZQ_U8; // CMEQ Vd.16B,Vn.16B,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16x8_t vceqzq_u16(uint16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCEQZQ_U16; // CMEQ Vd.8H,Vn.8H,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32x4_t vceqzq_u32(uint32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VCEQZQ_U32; // CMEQ Vd.4S,Vn.4S,#0
add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_CMEQ_ASIMDSAME_ONLY:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCEQ_S8; // CMEQ Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCEQQ_S8; // CMEQ Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCEQ_S16; // CMEQ Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCEQQ_S16; // CMEQ Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCEQ_S32; // CMEQ Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCEQQ_S32; // CMEQ Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // uint8x8_t vceq_u8(uint8x8_t a, uint8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8B -> result
intrin_id = ARM64_INTRIN_VCEQ_U8; // CMEQ Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCEQQ_U8; // CMEQ Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vceq_u16(uint16x4_t a, uint16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCEQ_U16; // CMEQ Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCEQQ_U16; // CMEQ Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vceq_u32(uint32x2_t a, uint32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCEQ_U32; // CMEQ Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCEQQ_U32; // CMEQ Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCEQ_P8; // CMEQ Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCEQQ_P8; // CMEQ Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VCEQQ_S64; // CMEQ Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vceqq_u64(uint64x2_t a, uint64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCEQQ_U64; // CMEQ Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VCEQQ_P64; // CMEQ Vd.2D,Vn.2D,Vm.2D
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // uint8x16_t vceqq_u8(uint8x16_t a, uint8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VCEQQ_U8; // CMEQ Vd.16B,Vn.16B,Vm.16B
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vceqq_u16(uint16x8_t a, uint16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCEQQ_U16; // CMEQ Vd.8H,Vn.8H,Vm.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vceqq_u32(uint32x4_t a, uint32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VCEQQ_U32; // CMEQ Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -14338,52 +14992,59 @@ bool NeonGetLowLevelILForInstruction(
case ENC_CMGE_ASIMDMISC_Z:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VCGEZ_S8; // CMGE Vd.8B,Vn.8B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VCGEZQ_S8; // CMGE Vd.16B,Vn.16B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCGEZ_S16; // CMGE Vd.4H,Vn.4H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VCGEZQ_S16; // CMGE Vd.8H,Vn.8H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VCGEZ_S32; // CMGE Vd.2S,Vn.2S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VCGEZQ_S32; // CMGE Vd.4S,Vn.4S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VCGEZQ_S64; // CMGE Vd.2D,Vn.2D,#0
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_CMGE_ASIMDSAME_ONLY:
- if (instr.operands[2].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCGE_S8; // CMGE Vd.8B,Vm.8B,Vn.8B
- if (instr.operands[2].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCGEQ_S8; // CMGE Vd.16B,Vm.16B,Vn.16B
- if (instr.operands[2].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCGE_S16; // CMGE Vd.4H,Vm.4H,Vn.4H
- if (instr.operands[2].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCGEQ_S16; // CMGE Vd.8H,Vm.8H,Vn.8H
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCGE_S32; // CMGE Vd.2S,Vm.2S,Vn.2S
- if (instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCGEQ_S32; // CMGE Vd.4S,Vm.4S,Vn.4S
- if (instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VCGEQ_S64; // CMGE Vd.2D,Vm.2D,Vn.2D
- if (instr.operands[2].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCLE_S8; // CMGE Vd.8B,Vm.8B,Vn.8B
- if (instr.operands[2].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCLEQ_S8; // CMGE Vd.16B,Vm.16B,Vn.16B
- if (instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vcle_s16(int16x4_t a, int16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCLE_S16; // CMGE Vd.4H,Vm.4H,Vn.4H
- if (instr.operands[2].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCLEQ_S16; // CMGE Vd.8H,Vm.8H,Vn.8H
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vcle_s32(int32x2_t a, int32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCLE_S32; // CMGE Vd.2S,Vm.2S,Vn.2S
- if (instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ // uint8x8_t vcle_s8(int8x8_t a, int8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VCLE_S8; // CMGE Vd.8B,Vm.8B,Vn.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vcleq_s16(int16x8_t a, int16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCLEQ_S16; // CMGE Vd.8H,Vm.8H,Vn.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vcleq_s32(int32x4_t a, int32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCLEQ_S32; // CMGE Vd.4S,Vm.4S,Vn.4S
- if (instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vcleq_s64(int64x2_t a, int64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCLEQ_S64; // CMGE Vd.2D,Vm.2D,Vn.2D
- add_input_reg(inputs, il, instr.operands[2]);
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ // uint8x16_t vcleq_s8(int8x16_t a, int8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VCLEQ_S8; // CMGE Vd.16B,Vm.16B,Vn.16B
add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_CMGE_ASISDMISC_Z:
@@ -14400,50 +15061,92 @@ bool NeonGetLowLevelILForInstruction(
case ENC_CMGT_ASIMDMISC_Z:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VCGTZ_S8; // CMGT Vd.8B,Vn.8B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VCGTZQ_S8; // CMGT Vd.16B,Vn.16B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCGTZ_S16; // CMGT Vd.4H,Vn.4H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VCGTZQ_S16; // CMGT Vd.8H,Vn.8H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VCGTZ_S32; // CMGT Vd.2S,Vn.2S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VCGTZQ_S32; // CMGT Vd.4S,Vn.4S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VCGTZQ_S64; // CMGT Vd.2D,Vn.2D,#0
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_CMGT_ASIMDSAME_ONLY:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCGT_S8; // CMGT Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCGTQ_S8; // CMGT Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vcgt_s16(int16x4_t a, int16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCGT_S16; // CMGT Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCGTQ_S16; // CMGT Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vcgt_s32(int32x2_t a, int32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCGT_S32; // CMGT Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // uint8x8_t vcgt_s8(int8x8_t a, int8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VCGT_S8; // CMGT Vd.8B,Vn.8B,Vm.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vcgtq_s16(int16x8_t a, int16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCGTQ_S16; // CMGT Vd.8H,Vn.8H,Vm.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vcgtq_s32(int32x4_t a, int32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCGTQ_S32; // CMGT Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vcgtq_s64(int64x2_t a, int64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCGTQ_S64; // CMGT Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[2].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCLT_S8; // CMGT Vd.8B,Vm.8B,Vn.8B
- if (instr.operands[2].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCLTQ_S8; // CMGT Vd.16B,Vm.16B,Vn.16B
- if (instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // uint8x16_t vcgtq_s8(int8x16_t a, int8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VCGTQ_S8; // CMGT Vd.16B,Vn.16B,Vm.16B
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vclt_s16(int16x4_t a, int16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCLT_S16; // CMGT Vd.4H,Vm.4H,Vn.4H
- if (instr.operands[2].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCLTQ_S16; // CMGT Vd.8H,Vm.8H,Vn.8H
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vclt_s32(int32x2_t a, int32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCLT_S32; // CMGT Vd.2S,Vm.2S,Vn.2S
- if (instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ // uint8x8_t vclt_s8(int8x8_t a, int8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VCLT_S8; // CMGT Vd.8B,Vm.8B,Vn.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vcltq_s16(int16x8_t a, int16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCLTQ_S16; // CMGT Vd.8H,Vm.8H,Vn.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vcltq_s32(int32x4_t a, int32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCLTQ_S32; // CMGT Vd.4S,Vm.4S,Vn.4S
- if (instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vcltq_s64(int64x2_t a, int64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCLTQ_S64; // CMGT Vd.2D,Vm.2D,Vn.2D
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ // uint8x16_t vcltq_s8(int8x16_t a, int8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VCLTQ_S8; // CMGT Vd.16B,Vm.16B,Vn.16B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -14460,34 +15163,76 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_CMHI_ASIMDSAME_ONLY:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCGT_U8; // CMHI Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCGTQ_U8; // CMHI Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vcgt_u16(uint16x4_t a, uint16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCGT_U16; // CMHI Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCGTQ_U16; // CMHI Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vcgt_u32(uint32x2_t a, uint32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCGT_U32; // CMHI Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // uint8x8_t vcgt_u8(uint8x8_t a, uint8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VCGT_U8; // CMHI Vd.8B,Vn.8B,Vm.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vcgtq_u16(uint16x8_t a, uint16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCGTQ_U16; // CMHI Vd.8H,Vn.8H,Vm.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vcgtq_u32(uint32x4_t a, uint32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCGTQ_U32; // CMHI Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vcgtq_u64(uint64x2_t a, uint64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCGTQ_U64; // CMHI Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[2].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCLT_U8; // CMHI Vd.8B,Vm.8B,Vn.8B
- if (instr.operands[2].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCLTQ_U8; // CMHI Vd.16B,Vm.16B,Vn.16B
- if (instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // uint8x16_t vcgtq_u8(uint8x16_t a, uint8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VCGTQ_U8; // CMHI Vd.16B,Vn.16B,Vm.16B
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vclt_u16(uint16x4_t a, uint16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCLT_U16; // CMHI Vd.4H,Vm.4H,Vn.4H
- if (instr.operands[2].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCLTQ_U16; // CMHI Vd.8H,Vm.8H,Vn.8H
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vclt_u32(uint32x2_t a, uint32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCLT_U32; // CMHI Vd.2S,Vm.2S,Vn.2S
- if (instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ // uint8x8_t vclt_u8(uint8x8_t a, uint8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VCLT_U8; // CMHI Vd.8B,Vm.8B,Vn.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vcltq_u16(uint16x8_t a, uint16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCLTQ_U16; // CMHI Vd.8H,Vm.8H,Vn.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vcltq_u32(uint32x4_t a, uint32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCLTQ_U32; // CMHI Vd.4S,Vm.4S,Vn.4S
- if (instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vcltq_u64(uint64x2_t a, uint64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCLTQ_U64; // CMHI Vd.2D,Vm.2D,Vn.2D
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ // uint8x16_t vcltq_u8(uint8x16_t a, uint8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VCLTQ_U8; // CMHI Vd.16B,Vm.16B,Vn.16B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -14499,36 +15244,43 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_CMHS_ASIMDSAME_ONLY:
- if (instr.operands[2].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCGE_U8; // CMHS Vd.8B,Vm.8B,Vn.8B
- if (instr.operands[2].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCGEQ_U8; // CMHS Vd.16B,Vm.16B,Vn.16B
- if (instr.operands[2].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCGE_U16; // CMHS Vd.4H,Vm.4H,Vn.4H
- if (instr.operands[2].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCGEQ_U16; // CMHS Vd.8H,Vm.8H,Vn.8H
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCGE_U32; // CMHS Vd.2S,Vm.2S,Vn.2S
- if (instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCGEQ_U32; // CMHS Vd.4S,Vm.4S,Vn.4S
- if (instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VCGEQ_U64; // CMHS Vd.2D,Vm.2D,Vn.2D
- if (instr.operands[2].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VCLE_U8; // CMHS Vd.8B,Vm.8B,Vn.8B
- if (instr.operands[2].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VCLEQ_U8; // CMHS Vd.16B,Vm.16B,Vn.16B
- if (instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vcle_u16(uint16x4_t a, uint16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCLE_U16; // CMHS Vd.4H,Vm.4H,Vn.4H
- if (instr.operands[2].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCLEQ_U16; // CMHS Vd.8H,Vm.8H,Vn.8H
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vcle_u32(uint32x2_t a, uint32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCLE_U32; // CMHS Vd.2S,Vm.2S,Vn.2S
- if (instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ // uint8x8_t vcle_u8(uint8x8_t a, uint8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VCLE_U8; // CMHS Vd.8B,Vm.8B,Vn.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vcleq_u16(uint16x8_t a, uint16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCLEQ_U16; // CMHS Vd.8H,Vm.8H,Vn.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vcleq_u32(uint32x4_t a, uint32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCLEQ_U32; // CMHS Vd.4S,Vm.4S,Vn.4S
- if (instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vcleq_u64(uint64x2_t a, uint64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCLEQ_U64; // CMHS Vd.2D,Vm.2D,Vn.2D
- add_input_reg(inputs, il, instr.operands[2]);
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ // uint8x16_t vcleq_u8(uint8x16_t a, uint8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VCLEQ_U8; // CMHS Vd.16B,Vm.16B,Vn.16B
add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_CMHS_ASISDSAME_ONLY:
@@ -14540,19 +15292,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_CMLE_ASIMDMISC_Z:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VCLEZ_S8; // CMLE Vd.8B,Vn.8B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VCLEZQ_S8; // CMLE Vd.16B,Vn.16B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCLEZ_S16; // CMLE Vd.4H,Vn.4H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VCLEZQ_S16; // CMLE Vd.8H,Vn.8H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VCLEZ_S32; // CMLE Vd.2S,Vn.2S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VCLEZQ_S32; // CMLE Vd.4S,Vn.4S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VCLEZQ_S64; // CMLE Vd.2D,Vn.2D,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VCLEZ_F32; // CMLE Vd.2S,Vn.2S,#0
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -14565,17 +15317,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_CMLT_ASIMDMISC_Z:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VCLTZ_S8; // CMLT Vd.8B,Vn.8B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VCLTZQ_S8; // CMLT Vd.16B,Vn.16B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCLTZ_S16; // CMLT Vd.4H,Vn.4H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VCLTZQ_S16; // CMLT Vd.8H,Vn.8H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VCLTZ_S32; // CMLT Vd.2S,Vn.2S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VCLTZQ_S32; // CMLT Vd.4S,Vn.4S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VCLTZQ_S64; // CMLT Vd.2D,Vn.2D,#0
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -14586,40 +15338,41 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_CMTST_ASIMDSAME_ONLY:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VTST_S8; // CMTST Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VTSTQ_S8; // CMTST Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VTST_S16; // CMTST Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VTSTQ_S16; // CMTST Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VTST_S32; // CMTST Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VTSTQ_S32; // CMTST Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // uint8x8_t vtst_u8(uint8x8_t a, uint8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8B -> result
intrin_id = ARM64_INTRIN_VTST_U8; // CMTST Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VTSTQ_U8; // CMTST Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vtst_u16(uint16x4_t a, uint16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VTST_U16; // CMTST Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VTSTQ_U16; // CMTST Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vtst_u32(uint32x2_t a, uint32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VTST_U32; // CMTST Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VTSTQ_U32; // CMTST Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VTST_P8; // CMTST Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VTSTQ_P8; // CMTST Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VTSTQ_S64; // CMTST Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vtstq_u64(uint64x2_t a, uint64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VTSTQ_U64; // CMTST Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VTSTQ_P64; // CMTST Vd.2D,Vn.2D,Vm.2D
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // uint8x16_t vtstq_u8(uint8x16_t a, uint8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VTSTQ_U8; // CMTST Vd.16B,Vn.16B,Vm.16B
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vtstq_u16(uint16x8_t a, uint16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VTSTQ_U16; // CMTST Vd.8H,Vn.8H,Vm.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vtstq_u32(uint32x4_t a, uint32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VTSTQ_U32; // CMTST Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -14633,15 +15386,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_CNT_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VCNT_S8; // CNT Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VCNTQ_S8; // CNT Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VCNT_U8; // CNT Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VCNTQ_U8; // CNT Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VCNT_P8; // CNT Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VCNTQ_P8; // CNT Vd.16B,Vn.16B
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -14695,21 +15448,182 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_DUP_ASIMDINS_DR_R:
- // This instrinsic is already handled in GetLowLevelIlForInstruction, in il.cpp
- break; // Should be unreachable
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vmov_n_u16(uint16_t value)
+ // argprep: value -> Wn
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VMOV_N_U16; // DUP Vd.4H,rn
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vmov_n_u32(uint32_t value)
+ // argprep: value -> Wn
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VMOV_N_U32; // DUP Vd.2S,rn
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
+ // uint8x8_t vmov_n_u8(uint8_t value)
+ // argprep: value -> Wn
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VMOV_N_U8; // DUP Vd.8B,rn
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vmovq_n_u16(uint16_t value)
+ // argprep: value -> Wn
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VMOVQ_N_U16; // DUP Vd.8H,rn
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vmovq_n_u32(uint32_t value)
+ // argprep: value -> Wn
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VMOVQ_N_U32; // DUP Vd.4S,rn
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vmovq_n_u64(uint64_t value)
+ // argprep: value -> Xn
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VMOVQ_N_U64; // DUP Vd.2D,rn
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ // uint8x16_t vmovq_n_u8(uint8_t value)
+ // argprep: value -> Wn
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VMOVQ_N_U8; // DUP Vd.16B,rn
+ else if (instr.operands[0].arrSpec == ARRSPEC_1DOUBLE)
+ // uint64x1_t vmov_n_u64(uint64_t value)
+ // argprep: value -> Xn
+ // results: Vd.1D -> result
+ intrin_id = ARM64_INTRIN_VMOV_N_U64; // DUP Vd.1D,rn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_DUP_ASISDONE_ONLY:
case ENC_MOV_DUP_ASISDONE_ONLY: // The lifter use this instead of ENC_DUP_ASISDONE_ONLY
// NOTE(ek0): The decoder only returns the base arrSpec. Not sure if intended,
// so in the meantime we'll lift to the LANEQ version of the intrinsic.
- if (instr.operands[1].arrSpec == ARRSPEC_1BYTE)
- intrin_id = ARM64_INTRIN_VDUPB_LANEQ_S8; // DUP Bd, Vn.B[lane]
- else if (instr.operands[1].arrSpec == ARRSPEC_1HALF)
- intrin_id = ARM64_INTRIN_VDUPH_LANEQ_S16; // DUP Hd,Vn.H[lane]
- else if (instr.operands[1].arrSpec == ARRSPEC_1SINGLE)
- intrin_id = ARM64_INTRIN_VDUPS_LANEQ_S32; // DUP Sd,Vn.S[lane]
- else if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VDUPD_LANEQ_S64; // DUP Dd,Vn.D[lane]
- else
- break; // Should be unreachable
+ // if (instr.operands[1].arrSpec == ARRSPEC_1BYTE)
+ // intrin_id = ARM64_INTRIN_VDUPB_LANEQ_S8; // DUP Bd, Vn.B[lane]
+ // else if (instr.operands[1].arrSpec == ARRSPEC_1HALF)
+ // intrin_id = ARM64_INTRIN_VDUPH_LANEQ_S16; // DUP Hd,Vn.H[lane]
+ // else if (instr.operands[1].arrSpec == ARRSPEC_1SINGLE)
+ // intrin_id = ARM64_INTRIN_VDUPS_LANEQ_S32; // DUP Sd,Vn.S[lane]
+ // else if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
+ // intrin_id = ARM64_INTRIN_VDUPD_LANEQ_S64; // DUP Dd,Vn.D[lane]
+ // else
+ // break; // Should be unreachable
+ // add_input_reg(inputs, il, instr.operands[1]);
+ // add_input_lane(inputs, il, instr.operands[1]);
+ // add_output_reg(outputs, il, instr.operands[0]);
+
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && instr.operands[1].arrSpec == ARRSPEC_1DOUBLE && instr.operands[1].laneUsed)
+ // float64x1_t vcopy_lane_f64(float64x1_t a, const int lane1, float64x1_t b, const int lane2)
+ // argprep: a -> UNUSED; lane1 -> <lane1>; b -> Vn.1D; lane2 -> <lane2>
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCOPY_LANE_F64; // DUP Dd,Vn.D[lane2]
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].laneUsed)
+ // float64x1_t vcopy_laneq_f64(float64x1_t a, const int lane1, float64x2_t b, const int lane2)
+ // argprep: a -> UNUSED; lane1 -> <lane1>; b -> Vn.2D; lane2 -> <lane2>
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCOPY_LANEQ_F64; // DUP Dd,Vn.D[lane2]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[1].laneUsed)
+ // bfloat16x4_t vdup_lane_bf16(bfloat16x4_t vec, const int lane)
+ // argprep: vec -> Vn.4H; lane -> <lane>
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VDUP_LANE_BF16; // DUP Vd.4H,Vn.H[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].laneUsed)
+ // float32x2_t vdup_lane_f32(float32x2_t vec, const int lane)
+ // argprep: vec -> Vn.2S; lane -> <lane>
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VDUP_LANE_F32; // DUP Vd.2S,Vn.S[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[1].laneUsed)
+ // poly8x8_t vdup_lane_p8(poly8x8_t vec, const int lane)
+ // argprep: vec -> Vn.8B; lane -> <lane>
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VDUP_LANE_P8; // DUP Vd.8B,Vn.B[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[1].laneUsed)
+ // bfloat16x4_t vdup_laneq_bf16(bfloat16x8_t vec, const int lane)
+ // argprep: vec -> Vn.8H; lane -> <lane>
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VDUP_LANEQ_BF16; // DUP Vd.4H,Vn.H[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].laneUsed)
+ // float32x2_t vdup_laneq_f32(float32x4_t vec, const int lane)
+ // argprep: vec -> Vn.4S; lane -> <lane>
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VDUP_LANEQ_F32; // DUP Vd.2S,Vn.S[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[1].laneUsed)
+ // poly8x8_t vdup_laneq_p8(poly8x16_t vec, const int lane)
+ // argprep: vec -> Vn.16B; lane -> <lane>
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VDUP_LANEQ_P8; // DUP Vd.8B,Vn.B[lane]
+ else if ((instr.operands[0].reg[0] >= REG_B0 && instr.operands[0].reg[0] <= REG_B31) && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[1].laneUsed)
+ // poly8_t vdupb_lane_p8(poly8x8_t vec, const int lane)
+ // argprep: vec -> Vn.8B; lane -> <lane>
+ // results: Bd -> result
+ intrin_id = ARM64_INTRIN_VDUPB_LANE_P8; // DUP Bd,Vn.B[lane]
+ else if ((instr.operands[0].reg[0] >= REG_B0 && instr.operands[0].reg[0] <= REG_B31) && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[1].laneUsed)
+ // poly8_t vdupb_laneq_p8(poly8x16_t vec, const int lane)
+ // argprep: vec -> Vn.16B; lane -> <lane>
+ // results: Bd -> result
+ intrin_id = ARM64_INTRIN_VDUPB_LANEQ_P8; // DUP Bd,Vn.B[lane]
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[1].laneUsed)
+ // bfloat16_t vduph_lane_bf16(bfloat16x4_t vec, const int lane)
+ // argprep: vec -> Vn.4H; lane -> <lane>
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VDUPH_LANE_BF16; // DUP Hd,Vn.H[lane]
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[1].laneUsed)
+ // bfloat16_t vduph_laneq_bf16(bfloat16x8_t vec, const int lane)
+ // argprep: vec -> Vn.8H; lane -> <lane>
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VDUPH_LANEQ_BF16; // DUP Hd,Vn.H[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[1].laneUsed)
+ // bfloat16x8_t vdupq_lane_bf16(bfloat16x4_t vec, const int lane)
+ // argprep: vec -> Vn.4H; lane -> <lane>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VDUPQ_LANE_BF16; // DUP Vd.8H,Vn.H[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].laneUsed)
+ // float32x4_t vdupq_lane_f32(float32x2_t vec, const int lane)
+ // argprep: vec -> Vn.2S; lane -> <lane>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VDUPQ_LANE_F32; // DUP Vd.4S,Vn.S[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_1DOUBLE && instr.operands[1].laneUsed)
+ // float64x2_t vdupq_lane_f64(float64x1_t vec, const int lane)
+ // argprep: vec -> Vn.1D; lane -> <lane>
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VDUPQ_LANE_F64; // DUP Vd.2D,Vn.D[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[1].laneUsed)
+ // poly8x16_t vdupq_lane_p8(poly8x8_t vec, const int lane)
+ // argprep: vec -> Vn.8B; lane -> <lane>
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VDUPQ_LANE_P8; // DUP Vd.16B,Vn.B[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[1].laneUsed)
+ // bfloat16x8_t vdupq_laneq_bf16(bfloat16x8_t vec, const int lane)
+ // argprep: vec -> Vn.8H; lane -> <lane>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VDUPQ_LANEQ_BF16; // DUP Vd.8H,Vn.H[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].laneUsed)
+ // float32x4_t vdupq_laneq_f32(float32x4_t vec, const int lane)
+ // argprep: vec -> Vn.4S; lane -> <lane>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VDUPQ_LANEQ_F32; // DUP Vd.4S,Vn.S[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].laneUsed)
+ // float64x2_t vdupq_laneq_f64(float64x2_t vec, const int lane)
+ // argprep: vec -> Vn.2D; lane -> <lane>
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VDUPQ_LANEQ_F64; // DUP Vd.2D,Vn.D[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[1].laneUsed)
+ // poly8x16_t vdupq_laneq_p8(poly8x16_t vec, const int lane)
+ // argprep: vec -> Vn.16B; lane -> <lane>
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VDUPQ_LANEQ_P8; // DUP Vd.16B,Vn.B[lane]
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].laneUsed)
+ // float32_t vdups_lane_f32(float32x2_t vec, const int lane)
+ // argprep: vec -> Vn.2S; lane -> <lane>
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VDUPS_LANE_F32; // DUP Sd,Vn.S[lane]
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].laneUsed)
+ // float32_t vdups_laneq_f32(float32x4_t vec, const int lane)
+ // argprep: vec -> Vn.4S; lane -> <lane>
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VDUPS_LANEQ_F32; // DUP Sd,Vn.S[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_1DOUBLE && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].laneUsed)
+ // float64x1_t vget_high_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.1D -> result
+ intrin_id = ARM64_INTRIN_VGET_HIGH_F64; // DUP Vd.1D,Vn.D[1]
add_input_reg(inputs, il, instr.operands[1]);
add_input_lane(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -14739,19 +15653,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_EOR3_VVV16_CRYPTO4:
if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEOR3Q_U8; // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEOR3Q_U16; // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEOR3Q_U32; // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEOR3Q_U64; // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEOR3Q_S8; // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEOR3Q_S16; // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEOR3Q_S32; // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEOR3Q_S64; // EOR3 Vd.16B,Vn.16B,Vm.16B,Va.16B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -14761,49 +15675,49 @@ bool NeonGetLowLevelILForInstruction(
case ENC_EOR_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEOR_S8; // EOR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEORQ_S8; // EOR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEOR_S16; // EOR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEORQ_S16; // EOR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEOR_S32; // EOR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEORQ_S32; // EOR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEOR_S64; // EOR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEORQ_S64; // EOR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEOR_U8; // EOR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEORQ_U8; // EOR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEOR_U16; // EOR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEORQ_U16; // EOR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEOR_U32; // EOR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEORQ_U32; // EOR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEOR_U64; // EOR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEORQ_U64; // EOR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VADD_P8; // EOR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VADD_P16; // EOR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VADD_P64; // EOR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VADDQ_P8; // EOR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VADDQ_P16; // EOR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VADDQ_P64; // EOR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VADDQ_P128; // EOR Vd.16B,Vn.16B,Vm.16B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -14812,75 +15726,76 @@ bool NeonGetLowLevelILForInstruction(
case ENC_EXT_ASIMDEXT_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEXT_S8; // EXT Vd.8B,Vn.8B,Vm.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEXTQ_S8; // EXT Vd.16B,Vn.16B,Vm.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEXT_S16; // EXT Vd.8B,Vn.8B,Vm.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEXTQ_S16; // EXT Vd.16B,Vn.16B,Vm.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEXT_S32; // EXT Vd.8B,Vn.8B,Vm.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEXTQ_S32; // EXT Vd.16B,Vn.16B,Vm.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEXT_S64; // EXT Vd.8B,Vn.8B,Vm.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEXTQ_S64; // EXT Vd.16B,Vn.16B,Vm.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEXT_U8; // EXT Vd.8B,Vn.8B,Vm.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEXTQ_U8; // EXT Vd.16B,Vn.16B,Vm.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEXT_U16; // EXT Vd.8B,Vn.8B,Vm.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEXTQ_U16; // EXT Vd.16B,Vn.16B,Vm.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEXT_U32; // EXT Vd.8B,Vn.8B,Vm.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEXTQ_U32; // EXT Vd.16B,Vn.16B,Vm.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEXT_U64; // EXT Vd.8B,Vn.8B,Vm.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEXTQ_U64; // EXT Vd.16B,Vn.16B,Vm.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEXT_P64; // EXT Vd.8B,Vn.8B,Vm.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEXTQ_P64; // EXT Vd.16B,Vn.16B,Vm.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEXT_F32; // EXT Vd.8B,Vn.8B,Vm.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEXTQ_F32; // EXT Vd.16B,Vn.16B,Vm.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEXT_F64; // EXT Vd.8B,Vn.8B,Vm.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEXTQ_F64; // EXT Vd.16B,Vn.16B,Vm.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEXT_P8; // EXT Vd.8B,Vn.8B,Vm.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEXTQ_P8; // EXT Vd.16B,Vn.16B,Vm.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEXT_P16; // EXT Vd.8B,Vn.8B,Vm.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEXTQ_P16; // EXT Vd.16B,Vn.16B,Vm.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VEXT_F16; // EXT Vd.8B,Vn.8B,Vm.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VEXTQ_F16; // EXT Vd.16B,Vn.16B,Vm.16B,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_input_imm(inputs, il, instr.operands[3]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FABD_ASIMDSAME_ONLY:
case ENC_FABD_ASIMDSAMEFP16_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VABD_F32; // FABD Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VABDQ_F32; // FABD Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VABDQ_F64; // FABD Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VABD_F16; // FABD Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VABDQ_F16; // FABD Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -14892,50 +15807,72 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FABD_ASISDSAME_ONLY:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].reg[0] >= REG_D0 && instr.operands[2].reg[0] <= REG_D31))
+ // float64_t vabdd_f64(float64_t a, float64_t b)
+ // argprep: a -> Dn; b -> Dm
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VABDD_F64; // FABD Dd,Dn,Dm
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].reg[0] >= REG_S0 && instr.operands[2].reg[0] <= REG_S31))
+ // float32_t vabds_f32(float32_t a, float32_t b)
+ // argprep: a -> Sn; b -> Sm
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VABDS_F32; // FABD Sd,Sn,Sm
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FABS_D_FLOATDP1:
intrin_id = ARM64_INTRIN_VABS_F64; // FABS Dd,Dn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FABS_S_FLOATDP1:
+ intrin_id = ARM64_INTRIN_VABS_F32; // FABS Sd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FABS_H_FLOATDP1:
intrin_id = ARM64_INTRIN_VABSH_F16; // FABS Hd,Hn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FABS_ASIMDMISC_R:
case ENC_FABS_ASIMDMISCFP16_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VABS_F32; // FABS Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VABSQ_F32; // FABS Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VABSQ_F64; // FABS Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VABS_F16; // FABS Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VABSQ_F16; // FABS Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FACGE_ASIMDSAME_ONLY:
case ENC_FACGE_ASIMDSAMEFP16_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VCAGE_F32; // FACGE Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VCAGEQ_F32; // FACGE Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VCAGEQ_F64; // FACGE Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VCALE_F32; // FACGE Vd.2S,Vm.2S,Vn.2S
- if (instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VCALEQ_F32; // FACGE Vd.4S,Vm.4S,Vn.4S
- if (instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VCALEQ_F64; // FACGE Vd.2D,Vm.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCAGE_F16; // FACGE Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VCAGEQ_F16; // FACGE Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCALE_F16; // FACGE Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VCALEQ_F16; // FACGE Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -14947,26 +15884,27 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FACGT_ASIMDSAME_ONLY:
case ENC_FACGT_ASIMDSAMEFP16_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VCAGT_F32; // FACGT Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VCAGTQ_F32; // FACGT Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VCAGTQ_F64; // FACGT Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VCALT_F32; // FACGT Vd.2S,Vm.2S,Vn.2S
- if (instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VCALTQ_F32; // FACGT Vd.4S,Vm.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VCALTQ_F64; // FACGT Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCAGT_F16; // FACGT Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VCAGTQ_F16; // FACGT Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCALT_F16; // FACGT Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VCALTQ_F16; // FACGT Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -14979,22 +15917,56 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FADDP_ASIMDSAMEFP16_ONLY:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // float16x4_t vpadd_f16(float16x4_t a, float16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VPADD_F16; // FADDP Vd.4H,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // float16x8_t vpaddq_f16(float16x8_t a, float16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VPADDQ_F16; // FADDP Vd.8H,Vn.8H,Vm.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FADDP_ASIMDSAME_ONLY:
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // float32_t vaddvq_f32(float32x4_t a)
+ // argprep: a -> Vm.4S
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VADDVQ_F32; // FADDP Vt.4S,Vn.4S,Vm.4S; FADDP Sd,Vt.2S
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // float32x2_t vpadd_f32(float32x2_t a, float32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VPADD_F32; // FADDP Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // float32x4_t vpaddq_f32(float32x4_t a, float32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VPADDQ_F32; // FADDP Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // float64x2_t vpaddq_f64(float64x2_t a, float64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VPADDQ_F64; // FADDP Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VPADD_F16; // FADDP Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VPADDQ_F16; // FADDP Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_FADDP_ASISDPAIR_ONLY_H:
- intrin_id = ARM64_INTRIN_VPADDS_F32; // FADDP Sd,Vn.2S
+ case ENC_FADDP_ASISDPAIR_ONLY_SD:
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // float32_t vpadds_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VPADDS_F32; // FADDP Sd,Vn.2S
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // float64_t vpaddd_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VPADDD_F64; // FADDP Dd,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
@@ -15004,704 +15976,2041 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FADD_S_FLOATDP2:
+ intrin_id = ARM64_INTRIN_VADD_F32; // FADD Sd,Sn,Sm
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FADD_H_FLOATDP2:
intrin_id = ARM64_INTRIN_VADDH_F16; // FADD Hd,Hn,Hm
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FADD_ASIMDSAME_ONLY:
case ENC_FADD_ASIMDSAMEFP16_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VADD_F32; // FADD Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VADDQ_F32; // FADD Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VADDQ_F64; // FADD Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VADD_F16; // FADD Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VADDQ_F16; // FADD Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCADD_ASIMDSAME2_C:
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCADD_ROT90_F16; // FCADD Vd.4H,Vn.4H,Vm.4H,#90
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCADD_ROT90_F32; // FCADD Vd.2S,Vn.2S,Vm.2S,#90
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCADDQ_ROT90_F16; // FCADD Vd.8H,Vn.8H,Vm.8H,#90
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCADDQ_ROT90_F32; // FCADD Vd.4S,Vn.4S,Vm.4S,#90
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VCADDQ_ROT90_F64; // FCADD Vd.2D,Vn.2D,Vm.2D,#90
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCADD_ROT270_F16; // FCADD Vd.4H,Vn.4H,Vm.4H,#270
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCADD_ROT270_F32; // FCADD Vd.2S,Vn.2S,Vm.2S,#270
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCADDQ_ROT270_F16; // FCADD Vd.8H,Vn.8H,Vm.8H,#270
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCADDQ_ROT270_F32; // FCADD Vd.4S,Vn.4S,Vm.4S,#270
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VCADDQ_ROT270_F64; // FCADD Vd.2D,Vn.2D,Vm.2D,#270
+ if (instr.operands[3].immediate == 90) {
+ if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ intrin_id = ARM64_INTRIN_VCADD_ROT90_F16; // FCADD Vd.4H,Vn.4H,Vm.4H,#90
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ intrin_id = ARM64_INTRIN_VCADD_ROT90_F32; // FCADD Vd.2S,Vn.2S,Vm.2S,#90
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ intrin_id = ARM64_INTRIN_VCADDQ_ROT90_F16; // FCADD Vd.8H,Vn.8H,Vm.8H,#90
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ intrin_id = ARM64_INTRIN_VCADDQ_ROT90_F32; // FCADD Vd.4S,Vn.4S,Vm.4S,#90
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ intrin_id = ARM64_INTRIN_VCADDQ_ROT90_F64; // FCADD Vd.2D,Vn.2D,Vm.2D,#90
+ }
+ if (instr.operands[3].immediate == 270) {
+ if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ intrin_id = ARM64_INTRIN_VCADD_ROT270_F16; // FCADD Vd.4H,Vn.4H,Vm.4H,#270
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ intrin_id = ARM64_INTRIN_VCADD_ROT270_F32; // FCADD Vd.2S,Vn.2S,Vm.2S,#270
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ intrin_id = ARM64_INTRIN_VCADDQ_ROT270_F16; // FCADD Vd.8H,Vn.8H,Vm.8H,#270
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ intrin_id = ARM64_INTRIN_VCADDQ_ROT270_F32; // FCADD Vd.4S,Vn.4S,Vm.4S,#270
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ intrin_id = ARM64_INTRIN_VCADDQ_ROT270_F64; // FCADD Vd.2D,Vn.2D,Vm.2D,#270
+ }
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCMEQ_ASIMDMISCFP16_FZ:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16x4_t vceqz_f16(float16x4_t a)
+ // immediate: #0
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCEQZ_F16; // FCMEQ Vd.4H,Vn.4H,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16x8_t vceqzq_f16(float16x8_t a)
+ // immediate: #0
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCEQZQ_F16; // FCMEQ Vd.8H,Vn.8H,#0
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMEQ_ASIMDMISC_FZ:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32x2_t vceqz_f32(float32x2_t a)
+ // immediate: #0
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCEQZ_F32; // FCMEQ Vd.2S,Vn.2S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32x4_t vceqzq_f32(float32x4_t a)
+ // immediate: #0
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCEQZQ_F32; // FCMEQ Vd.4S,Vn.4S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint64x2_t vceqzq_f64(float64x2_t a)
+ // immediate: #0
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCEQZQ_F64; // FCMEQ Vd.2D,Vn.2D,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCEQZ_F16; // FCMEQ Vd.4H,Vn.4H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCEQZQ_F16; // FCMEQ Vd.8H,Vn.8H,#0
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCMEQ_ASIMDSAMEFP16_ONLY:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vceq_f16(float16x4_t a, float16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCEQ_F16; // FCMEQ Vd.4H,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vceqq_f16(float16x8_t a, float16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCEQQ_F16; // FCMEQ Vd.8H,Vn.8H,Vm.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMEQ_ASIMDSAME_ONLY:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vceq_f32(float32x2_t a, float32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCEQ_F32; // FCMEQ Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vceqq_f32(float32x4_t a, float32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCEQQ_F32; // FCMEQ Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vceqq_f64(float64x2_t a, float64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCEQQ_F64; // FCMEQ Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCEQ_F16; // FCMEQ Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCEQQ_F16; // FCMEQ Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FCMEQ_ASISDMISCFP16_FZ:
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16_t vceqzh_f16(float16_t a)
+ // immediate: #0
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCEQZH_F16; // FCMEQ Hd,Hn,#0
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMEQ_ASISDMISC_FZ:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint64x1_t vceqz_f64(float64x1_t a)
+ // immediate: #0
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCEQZ_F64; // FCMEQ Dd,Dn,#0
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint64_t vceqzd_f64(float64_t a)
+ // immediate: #0
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCEQZD_F64; // FCMEQ Dd,Dn,#0
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32_t vceqzs_f32(float32_t a)
+ // immediate: #0
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCEQZS_F32; // FCMEQ Sd,Sn,#0
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FCMEQ_ASISDSAMEFP16_ONLY:
- intrin_id = ARM64_INTRIN_VCEQ_F64; // FCMEQ Dd,Dn,Dm
+ // uint16_t vceqh_f16(float16_t a, float16_t b)
+ // argprep: a -> Hn; b -> Hm
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCEQH_F16; // FCMEQ Hd,Hn,Hm
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMEQ_ASISDSAME_ONLY:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].reg[0] >= REG_D0 && instr.operands[2].reg[0] <= REG_D31))
+ // uint64x1_t vceq_f64(float64x1_t a, float64x1_t b)
+ // argprep: a -> Dn; b -> Dm
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCEQ_F64; // FCMEQ Dd,Dn,Dm
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].reg[0] >= REG_D0 && instr.operands[2].reg[0] <= REG_D31))
+ // uint64_t vceqd_f64(float64_t a, float64_t b)
+ // argprep: a -> Dn; b -> Dm
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCEQD_F64; // FCMEQ Dd,Dn,Dm
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].reg[0] >= REG_S0 && instr.operands[2].reg[0] <= REG_S31))
+ // uint32_t vceqs_f32(float32_t a, float32_t b)
+ // argprep: a -> Sn; b -> Sm
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCEQS_F32; // FCMEQ Sd,Sn,Sm
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCMGE_ASIMDMISCFP16_FZ:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16x4_t vcgez_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCGEZ_F16; // FCMGE Vd.4H,Vn.4H,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16x8_t vcgezq_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCGEZQ_F16; // FCMGE Vd.8H,Vn.8H,#0
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMGE_ASIMDMISC_FZ:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32x2_t vcgez_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCGEZ_F32; // FCMGE Vd.2S,Vn.2S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32x4_t vcgezq_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCGEZQ_F32; // FCMGE Vd.4S,Vn.4S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint64x2_t vcgezq_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCGEZQ_F64; // FCMGE Vd.2D,Vn.2D,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCGEZ_F16; // FCMGE Vd.4H,Vn.4H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCGEZQ_F16; // FCMGE Vd.8H,Vn.8H,#0
add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCMGE_ASIMDSAMEFP16_ONLY:
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCGE_F32; // FCMGE Vd.2S,Vm.2S,Vn.2S
- if (instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCGEQ_F32; // FCMGE Vd.4S,Vm.4S,Vn.4S
- if (instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VCGEQ_F64; // FCMGE Vd.2D,Vm.2D,Vn.2D
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vcle_f16(float16x4_t a, float16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCLE_F16; // FCMGE Vd.4H,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vcleq_f16(float16x8_t a, float16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCLEQ_F16; // FCMGE Vd.8H,Vn.8H,Vm.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMGE_ASIMDSAME_ONLY:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vcle_f32(float32x2_t a, float32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCLE_F32; // FCMGE Vd.2S,Vm.2S,Vn.2S
- if (instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vcleq_f32(float32x4_t a, float32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCLEQ_F32; // FCMGE Vd.4S,Vm.4S,Vn.4S
- if (instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vcleq_f64(float64x2_t a, float64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCLEQ_F64; // FCMGE Vd.2D,Vm.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCGE_F16; // FCMGE Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCGEQ_F16; // FCMGE Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCLE_F16; // FCMGE Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCLEQ_F16; // FCMGE Vd.8H,Vn.8H,Vm.8H
+ add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMGE_ASISDMISCFP16_FZ:
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16_t vcgezh_f16(float16_t a)
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCGEZH_F16; // FCMGE Hd,Hn,#0
add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMGE_ASISDMISC_FZ:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint64_t vcgezd_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCGEZD_F64; // FCMGE Dd,Dn,#0
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32_t vcgezs_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCGEZS_F32; // FCMGE Sd,Sn,#0
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCMGE_ASISDSAMEFP16_ONLY:
- intrin_id = ARM64_INTRIN_VCGE_F64; // FCMGE Dd,Dn,Dm
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].reg[0] >= REG_H0 && instr.operands[2].reg[0] <= REG_H31))
+ // uint16_t vcleh_f16(float16_t a, float16_t b)
+ // argprep: a -> Hn; b -> Hm
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCLEH_F16; // FCMGE Hd,Hn,Hm
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMGE_ASISDSAME_ONLY:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].reg[0] >= REG_D0 && instr.operands[2].reg[0] <= REG_D31))
+ // uint64_t vcged_f64(float64_t a, float64_t b)
+ // argprep: a -> Dn; b -> Dm
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCGED_F64; // FCMGE Dd,Dn,Dm
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].reg[0] >= REG_S0 && instr.operands[2].reg[0] <= REG_S31))
+ // uint32_t vcges_f32(float32_t a, float32_t b)
+ // argprep: a -> Sn; b -> Sm
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCGES_F32; // FCMGE Sd,Sn,Sm
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[2].reg[0] >= REG_D0 && instr.operands[2].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint64_t vcled_f64(float64_t a, float64_t b)
+ // argprep: a -> Dn; b -> Dm
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCLED_F64; // FCMGE Dd,Dm,Dn
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[2].reg[0] >= REG_S0 && instr.operands[2].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint32_t vcles_f32(float32_t a, float32_t b)
+ // argprep: a -> Sn; b -> Sm
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCLES_F32; // FCMGE Sd,Sm,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCMGT_ASIMDMISCFP16_FZ:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16x4_t vcgtz_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCGTZ_F16; // FCMGT Vd.4H,Vn.4H,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16x8_t vcgtzq_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCGTZQ_F16; // FCMGT Vd.8H,Vn.8H,#0
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMGT_ASIMDMISC_FZ:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32x2_t vcgtz_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCGTZ_F32; // FCMGT Vd.2S,Vn.2S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32x4_t vcgtzq_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCGTZQ_F32; // FCMGT Vd.4S,Vn.4S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint64x2_t vcgtzq_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCGTZQ_F64; // FCMGT Vd.2D,Vn.2D,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCGTZ_F16; // FCMGT Vd.4H,Vn.4H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCGTZQ_F16; // FCMGT Vd.8H,Vn.8H,#0
add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCMGT_ASIMDSAMEFP16_ONLY:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vclt_f16(float16x4_t a, float16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCLT_F16; // FCMGT Vd.4H,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vcltq_f16(float16x8_t a, float16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCLTQ_F16; // FCMGT Vd.8H,Vn.8H,Vm.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMGT_ASIMDSAME_ONLY:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vcgt_f32(float32x2_t a, float32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCGT_F32; // FCMGT Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vcgtq_f32(float32x4_t a, float32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCGTQ_F32; // FCMGT Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vcgtq_f64(float64x2_t a, float64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCGTQ_F64; // FCMGT Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vclt_f32(float32x2_t a, float32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCLT_F32; // FCMGT Vd.2S,Vm.2S,Vn.2S
- if (instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vcltq_f32(float32x4_t a, float32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCLTQ_F32; // FCMGT Vd.4S,Vm.4S,Vn.4S
- if (instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vcltq_f64(float64x2_t a, float64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCLTQ_F64; // FCMGT Vd.2D,Vm.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCGT_F16; // FCMGT Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCGTQ_F16; // FCMGT Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCLT_F16; // FCMGT Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCLTQ_F16; // FCMGT Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FCMGT_ASISDMISC_FZ:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint64_t vcgtzd_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCGTZD_F64; // FCMGT Dd,Dn,#0
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32_t vcgtzs_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCGTZS_F32; // FCMGT Sd,Sn,#0
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FCMGT_ASISDSAMEFP16_ONLY:
- intrin_id = ARM64_INTRIN_VCGT_F64; // FCMGT Dd,Dn,Dm
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].reg[0] >= REG_H0 && instr.operands[2].reg[0] <= REG_H31))
+ // uint16_t vclth_f16(float16_t a, float16_t b)
+ // argprep: a -> Hn; b -> Hm
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCLTH_F16; // FCMGT Hd,Hn,Hm
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ {
+ // uint16_t vcgtzh_f16(float16_t a)
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCGTZH_F16; // FCMGT Hd,Hn,#0
+ add_input_imm(inputs, il, instr.operands[2]);
+ }
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMGT_ASISDSAME_ONLY:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].reg[0] >= REG_D0 && instr.operands[2].reg[0] <= REG_D31))
+ // uint64_t vcgtd_f64(float64_t a, float64_t b)
+ // argprep: a -> Dn; b -> Dm
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCGTD_F64; // FCMGT Dd,Dn,Dm
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].reg[0] >= REG_S0 && instr.operands[2].reg[0] <= REG_S31))
+ // uint32_t vcgts_f32(float32_t a, float32_t b)
+ // argprep: a -> Sn; b -> Sm
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCGTS_F32; // FCMGT Sd,Sn,Sm
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[2].reg[0] >= REG_D0 && instr.operands[2].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint64_t vcltd_f64(float64_t a, float64_t b)
+ // argprep: a -> Dn; b -> Dm
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCLTD_F64; // FCMGT Dd,Dm,Dn
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[2].reg[0] >= REG_S0 && instr.operands[2].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint32_t vclts_f32(float32_t a, float32_t b)
+ // argprep: a -> Sn; b -> Sm
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCLTS_F32; // FCMGT Sd,Sm,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_FCMLA_ASIMDSAME2_C:
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCMLA_F16; // FCMLA Vd.4H,Vn.4H,Vm.4H,#0
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCMLA_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S,#0
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCMLA_LANE_F16; // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#0
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCMLA_LANE_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#0
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ case ENC_FCMLA_ASIMDELEM_C_H:
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 0))
+ // float16x4_t vcmla_laneq_f16(float16x4_t r, float16x4_t a, float16x8_t b, const int lane)
+ // argprep: r -> Vd.4H; a -> Vn.4H; b -> Vm.H; lane -> <lane>
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCMLA_LANEQ_F16; // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#0
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCMLAQ_F16; // FCMLA Vd.8H,Vn.8H,Vm.8H,#0
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCMLAQ_F32; // FCMLA Vd.4S,Vn.4S,Vm.4S,#0
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VCMLAQ_F64; // FCMLA Vd.2D,Vn.2D,Vm.2D,#0
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCMLAQ_LANE_F16; // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#0
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCMLAQ_LANE_F32; // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#0
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCMLAQ_LANEQ_F16; // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#0
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCMLAQ_LANEQ_F32; // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#0
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCMLA_ROT90_F16; // FCMLA Vd.4H,Vn.4H,Vm.4H,#90
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCMLA_ROT90_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S,#90
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCMLA_ROT90_LANE_F16; // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#90
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCMLA_ROT90_LANE_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#90
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 180))
+ // float16x4_t vcmla_rot180_laneq_f16(float16x4_t r, float16x4_t a, float16x8_t b, const int lane)
+ // argprep: r -> Vd.4H; a -> Vn.4H; b -> Vm.H; lane -> <lane>
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCMLA_ROT180_LANEQ_F16; // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#180
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 270))
+ // float16x4_t vcmla_rot270_laneq_f16(float16x4_t r, float16x4_t a, float16x8_t b, const int lane)
+ // argprep: r -> Vd.4H; a -> Vn.4H; b -> Vm.H; lane -> <lane>
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCMLA_ROT270_LANEQ_F16; // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#270
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 90))
+ // float16x4_t vcmla_rot90_laneq_f16(float16x4_t r, float16x4_t a, float16x8_t b, const int lane)
+ // argprep: r -> Vd.4H; a -> Vn.4H; b -> Vm.H; lane -> <lane>
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCMLA_ROT90_LANEQ_F16; // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#90
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCMLAQ_ROT90_F16; // FCMLA Vd.8H,Vn.8H,Vm.8H,#90
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCMLAQ_ROT90_F32; // FCMLA Vd.4S,Vn.4S,Vm.4S,#90
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VCMLAQ_ROT90_F64; // FCMLA Vd.2D,Vn.2D,Vm.2D,#90
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCMLAQ_ROT90_LANE_F16; // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#90
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCMLAQ_ROT90_LANE_F32; // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#90
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 0))
+ // float16x8_t vcmlaq_laneq_f16(float16x8_t r, float16x8_t a, float16x8_t b, const int lane)
+ // argprep: r -> Vd.8H; a -> Vn.8H; b -> Vm.H; lane -> <lane>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCMLAQ_LANEQ_F16; // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 180))
+ // float16x8_t vcmlaq_rot180_laneq_f16(float16x8_t r, float16x8_t a, float16x8_t b, const int lane)
+ // argprep: r -> Vd.8H; a -> Vn.8H; b -> Vm.H; lane -> <lane>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCMLAQ_ROT180_LANEQ_F16; // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#180
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 270))
+ // float16x8_t vcmlaq_rot270_laneq_f16(float16x8_t r, float16x8_t a, float16x8_t b, const int lane)
+ // argprep: r -> Vd.8H; a -> Vn.8H; b -> Vm.H; lane -> <lane>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCMLAQ_ROT270_LANEQ_F16; // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#270
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 90))
+ // float16x8_t vcmlaq_rot90_laneq_f16(float16x8_t r, float16x8_t a, float16x8_t b, const int lane)
+ // argprep: r -> Vd.8H; a -> Vn.8H; b -> Vm.H; lane -> <lane>
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VCMLAQ_ROT90_LANEQ_F16; // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#90
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ add_input_reg(inputs, il, instr.operands[0]);
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_input_lane(inputs, il, instr.operands[2]);
+ add_input_imm(inputs, il, instr.operands[3]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMLA_ASIMDELEM_C_S:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 0))
+ // float32x2_t vcmla_lane_f32(float32x2_t r, float32x2_t a, float32x2_t b, const int lane)
+ // argprep: r -> Vd.2S; a -> Vn.2S; b -> Vm.2S; lane -> <lane>
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VCMLA_LANE_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 180))
+ // float32x2_t vcmla_rot180_lane_f32(float32x2_t r, float32x2_t a, float32x2_t b, const int lane)
+ // argprep: r -> Vd.2S; a -> Vn.2S; b -> Vm.2S; lane -> <lane>
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VCMLA_ROT180_LANE_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#180
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 270))
+ // float32x2_t vcmla_rot270_lane_f32(float32x2_t r, float32x2_t a, float32x2_t b, const int lane)
+ // argprep: r -> Vd.2S; a -> Vn.2S; b -> Vm.2S; lane -> <lane>
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VCMLA_ROT270_LANE_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#270
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 270))
+ // float16x4_t vcmla_rot270_laneq_f16(float16x4_t r, float16x4_t a, float16x8_t b, const int lane)
+ // argprep: r -> Vd.4H; a -> Vn.4H; b -> Vm.H; lane -> <lane>
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCMLA_ROT270_LANEQ_F16; // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#270
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].laneUsed && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 270))
+ // float32x2_t vcmla_rot270_laneq_f32(float32x2_t r, float32x2_t a, float32x4_t b, const int lane)
+ // argprep: r -> Vd.2S; a -> Vm.D[1]; b -> Vn.2S; lane -> <lane>
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VCMLA_ROT270_LANEQ_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#270
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 90))
+ // float32x2_t vcmla_rot90_lane_f32(float32x2_t r, float32x2_t a, float32x2_t b, const int lane)
+ // argprep: r -> Vd.2S; a -> Vn.2S; b -> Vm.2S; lane -> <lane>
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VCMLA_ROT90_LANE_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#90
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 0))
+ // float32x4_t vcmlaq_laneq_f32(float32x4_t r, float32x4_t a, float32x4_t b, const int lane)
+ // argprep: r -> Vd.4S; a -> Vn.4S; b -> Vm.S; lane -> <lane>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VCMLAQ_LANEQ_F32; // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 180))
+ // float32x4_t vcmlaq_rot180_laneq_f32(float32x4_t r, float32x4_t a, float32x4_t b, const int lane)
+ // argprep: r -> Vd.4S; a -> Vn.4S; b -> Vm.S; lane -> <lane>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VCMLAQ_ROT180_LANEQ_F32; // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#180
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 270))
+ // float32x4_t vcmlaq_rot270_laneq_f32(float32x4_t r, float32x4_t a, float32x4_t b, const int lane)
+ // argprep: r -> Vd.4S; a -> Vn.4S; b -> Vm.S; lane -> <lane>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VCMLAQ_ROT270_LANEQ_F32; // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#270
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 90))
+ // float32x4_t vcmlaq_rot90_laneq_f32(float32x4_t r, float32x4_t a, float32x4_t b, const int lane)
+ // argprep: r -> Vd.4S; a -> Vn.4S; b -> Vm.S; lane -> <lane>
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCMLAQ_ROT90_LANEQ_F32; // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#90
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ add_input_reg(inputs, il, instr.operands[0]);
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_input_lane(inputs, il, instr.operands[2]);
+ add_input_imm(inputs, il, instr.operands[3]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMLA_ASIMDSAME2_C:
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 0))
+ // float16x4_t vcmla_f16(float16x4_t r, float16x4_t a, float16x4_t b)
+ // argprep: r -> Vd.4H; a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCMLA_F16; // FCMLA Vd.4H,Vn.4H,Vm.4H,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 0))
+ // float32x2_t vcmla_f32(float32x2_t r, float32x2_t a, float32x2_t b)
+ // argprep: r -> Vd.2S; a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VCMLA_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // float32x2_t vcmla_laneq_f32(float32x2_t r, float32x2_t a, float32x4_t b, const int lane)
+ // argprep: r -> Vd.2S; a -> Vm.D[1]; b -> Vn.2S; lane -> <lane>
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VCMLA_LANEQ_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 180))
+ // float16x4_t vcmla_rot180_f16(float16x4_t r, float16x4_t a, float16x4_t b)
+ // argprep: r -> Vd.4H; a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCMLA_ROT180_F16; // FCMLA Vd.4H,Vn.4H,Vm.4H,#180
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 180))
+ // float32x2_t vcmla_rot180_f32(float32x2_t r, float32x2_t a, float32x2_t b)
+ // argprep: r -> Vd.2S; a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCMLA_ROT180_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S,#180
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 180))
+ // float32x2_t vcmla_rot180_laneq_f32(float32x2_t r, float32x2_t a, float32x4_t b, const int lane)
+ // argprep: r -> Vd.2S; a -> Vm.D[1]; b -> Vn.2S; lane -> <lane>
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VCMLA_ROT180_LANEQ_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S,#180
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 270))
+ // float16x4_t vcmla_rot270_f16(float16x4_t r, float16x4_t a, float16x4_t b)
+ // argprep: r -> Vd.4H; a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCMLA_ROT270_F16; // FCMLA Vd.4H,Vn.4H,Vm.4H,#270
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 270))
+ // float32x2_t vcmla_rot270_f32(float32x2_t r, float32x2_t a, float32x2_t b)
+ // argprep: r -> Vd.2S; a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VCMLA_ROT270_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S,#270
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 90))
+ // float16x4_t vcmla_rot90_f16(float16x4_t r, float16x4_t a, float16x4_t b)
+ // argprep: r -> Vd.4H; a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCMLA_ROT90_F16; // FCMLA Vd.4H,Vn.4H,Vm.4H,#90
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 90))
+ // float32x2_t vcmla_rot90_f32(float32x2_t r, float32x2_t a, float32x2_t b)
+ // argprep: r -> Vd.2S; a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VCMLA_ROT90_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S,#90
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 90))
+ // float32x2_t vcmla_rot90_laneq_f32(float32x2_t r, float32x2_t a, float32x4_t b, const int lane)
+ // argprep: r -> Vd.2S; a -> Vm.D[1]; b -> Vn.2S; lane -> <lane>
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VCMLA_ROT90_LANEQ_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S,#90
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 0))
+ // float16x8_t vcmlaq_f16(float16x8_t r, float16x8_t a, float16x8_t b)
+ // argprep: r -> Vd.8H; a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCMLAQ_F16; // FCMLA Vd.8H,Vn.8H,Vm.8H,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 0))
+ // float32x4_t vcmlaq_f32(float32x4_t r, float32x4_t a, float32x4_t b)
+ // argprep: r -> Vd.4S; a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VCMLAQ_F32; // FCMLA Vd.4S,Vn.4S,Vm.4S,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 0))
+ // float64x2_t vcmlaq_f64(float64x2_t r, float64x2_t a, float64x2_t b)
+ // argprep: r -> Vd.2D; a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VCMLAQ_F64; // FCMLA Vd.2D,Vn.2D,Vm.2D,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 180))
+ // float16x8_t vcmlaq_rot180_f16(float16x8_t r, float16x8_t a, float16x8_t b)
+ // argprep: r -> Vd.8H; a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VCMLAQ_ROT180_F16; // FCMLA Vd.8H,Vn.8H,Vm.8H,#180
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 180))
+ // float32x4_t vcmlaq_rot180_f32(float32x4_t r, float32x4_t a, float32x4_t b)
+ // argprep: r -> Vd.4S; a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCMLAQ_ROT180_F32; // FCMLA Vd.4S,Vn.4S,Vm.4S,#180
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 180))
+ // float64x2_t vcmlaq_rot180_f64(float64x2_t r, float64x2_t a, float64x2_t b)
+ // argprep: r -> Vd.2D; a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCMLAQ_ROT180_F64; // FCMLA Vd.2D,Vn.2D,Vm.2D,#180
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCMLA_ROT270_F16; // FCMLA Vd.4H,Vn.4H,Vm.4H,#270
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCMLA_ROT270_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S,#270
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 270))
+ // float16x8_t vcmlaq_rot270_f16(float16x8_t r, float16x8_t a, float16x8_t b)
+ // argprep: r -> Vd.8H; a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VCMLAQ_ROT270_F16; // FCMLA Vd.8H,Vn.8H,Vm.8H,#270
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 270))
+ // float32x4_t vcmlaq_rot270_f32(float32x4_t r, float32x4_t a, float32x4_t b)
+ // argprep: r -> Vd.4S; a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCMLAQ_ROT270_F32; // FCMLA Vd.4S,Vn.4S,Vm.4S,#270
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 270))
+ // float64x2_t vcmlaq_rot270_f64(float64x2_t r, float64x2_t a, float64x2_t b)
+ // argprep: r -> Vd.2D; a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCMLAQ_ROT270_F64; // FCMLA Vd.2D,Vn.2D,Vm.2D,#270
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 90))
+ // float16x8_t vcmlaq_rot90_f16(float16x8_t r, float16x8_t a, float16x8_t b)
+ // argprep: r -> Vd.8H; a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCMLAQ_ROT90_F16; // FCMLA Vd.8H,Vn.8H,Vm.8H,#90
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 90))
+ // float32x4_t vcmlaq_rot90_f32(float32x4_t r, float32x4_t a, float32x4_t b)
+ // argprep: r -> Vd.4S; a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VCMLAQ_ROT90_F32; // FCMLA Vd.4S,Vn.4S,Vm.4S,#90
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 90))
+ // float64x2_t vcmlaq_rot90_f64(float64x2_t r, float64x2_t a, float64x2_t b)
+ // argprep: r -> Vd.2D; a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VCMLAQ_ROT90_F64; // FCMLA Vd.2D,Vn.2D,Vm.2D,#90
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
+ add_input_imm(inputs, il, instr.operands[3]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCMLE_ASIMDMISCFP16_FZ:
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCLEZQ_F32; // FCMLE Vd.4S,Vn.4S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VCLEZQ_F64; // FCMLE Vd.2D,Vn.2D,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16x4_t vclez_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCLEZ_F16; // FCMLE Vd.4H,Vn.4H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16x8_t vclezq_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VCLEZQ_F16; // FCMLE Vd.8H,Vn.8H,#0
add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMLE_ASIMDMISC_FZ:
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32x4_t vclezq_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VCLEZQ_F32; // FCMLE Vd.4S,Vn.4S,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint64x2_t vclezq_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VCLEZQ_F64; // FCMLE Vd.2D,Vn.2D,#0
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCMLE_ASISDMISCFP16_FZ:
- intrin_id = ARM64_INTRIN_VCLEZ_F64; // FCMLE Dd,Dn,#0
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16_t vclezh_f16(float16_t a)
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCLEZH_F16; // FCMLE Hd,Hn,#0
add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMLE_ASISDMISC_FZ:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint64_t vclezd_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCLEZD_F64; // FCMLE Dd,Dn,#0
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32_t vclezs_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCLEZS_F32; // FCMLE Sd,Sn,#0
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCMLT_ASIMDMISCFP16_FZ:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16x4_t vcltz_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCLTZ_F16; // FCMLT Vd.4H,Vn.4H,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16x8_t vcltzq_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCLTZQ_F16; // FCMLT Vd.8H,Vn.8H,#0
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMLT_ASIMDMISC_FZ:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32x2_t vcltz_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCLTZ_F32; // FCMLT Vd.2S,Vn.2S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32x4_t vcltzq_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCLTZQ_F32; // FCMLT Vd.4S,Vn.4S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint64x2_t vcltzq_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCLTZQ_F64; // FCMLT Vd.2D,Vn.2D,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCLTZ_F16; // FCMLT Vd.4H,Vn.4H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCLTZQ_F16; // FCMLT Vd.8H,Vn.8H,#0
add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCMLT_ASISDMISCFP16_FZ:
- intrin_id = ARM64_INTRIN_VCLTZ_F64; // FCMLT Dd,Dn,#0
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16_t vcltzh_f16(float16_t a)
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCLTZH_F16; // FCMLT Hd,Hn,#0
add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCMLT_ASISDMISC_FZ:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint64_t vcltzd_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCLTZD_F64; // FCMLT Dd,Dn,#0
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32_t vcltzs_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCLTZS_F32; // FCMLT Sd,Sn,#0
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTAS_32D_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTA_S64_F64; // FCVTAS Dd,Dn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int32_t vcvtad_s32_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTAD_S32_F64; // FCVTAS Wd,Dn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTAS_32S_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTAS_S32_F32; // FCVTAS Sd,Sn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int32_t vcvtas_s32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTAS_S32_F32; // FCVTAS Wd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ // case ENC_FCVTAS_64D_FLOAT2FIX:
+ // if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // // int64_t vcvtad_n_s64_f64(float64_t a, const int n)
+ // // argprep: a -> Dn; n -> n
+ // // results: Xd -> result
+ // intrin_id = ARM64_INTRIN_VCVTAD_N_S64_F64; // FCVTAS Xd,Dn,#n
+ // add_input_reg(inputs, il, instr.operands[1]);
+ // add_input_imm(inputs, il, instr.operands[2]);
+ // add_output_reg(outputs, il, instr.operands[0]);
+ // break;
+ case ENC_FCVTAS_64D_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int64_t vcvtad_s64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTAD_S64_F64; // FCVTAS Xd,Dn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTAS_64S_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int64_t vcvtad_s64_f64(float64_t a)
+ // argprep: a -> Sn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTAD_S64_F64; // FCVTAS Xd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTAS_ASIMDMISCFP16_R:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // int16x4_t vcvta_s16_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCVTA_S16_F16; // FCVTAS Vd.4H,Vn.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // int16x8_t vcvtaq_s16_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCVTAQ_S16_F16; // FCVTAS Vd.8H,Vn.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTAS_ASIMDMISC_R:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // int32x2_t vcvta_s32_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCVTA_S32_F32; // FCVTAS Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // int32x4_t vcvtaq_s32_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCVTAQ_S32_F32; // FCVTAS Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // int64x2_t vcvtaq_s64_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCVTAQ_S64_F64; // FCVTAS Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCVTA_S16_F16; // FCVTAS Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCVTAQ_S16_F16; // FCVTAS Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTAS_ASISDMISCFP16_R:
- intrin_id = ARM64_INTRIN_VCVTAH_S16_F16; // FCVTAS Hd,Hn
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31))
+ // int64_t vcvtah_s64_f16(float16_t a)
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCVTAH_S64_F16; // FCVTAS Hd,Hn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTAS_ASISDMISC_R:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int64_t vcvtad_s64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCVTAD_S64_F64; // FCVTAS Dd,Dn
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int32_t vcvtas_s32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCVTAS_S32_F32; // FCVTAS Sd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTAU_32D_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTA_U64_F64; // FCVTAU Dd,Dn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint32_t vcvtad_u32_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTAD_U32_F64; // FCVTAU Wd,Dn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTAU_32S_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTAS_U32_F32; // FCVTAU Sd,Sn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint32_t vcvtas_u32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTAS_U32_F32; // FCVTAU Wd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTAU_64D_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint64_t vcvtad_u64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTAD_U64_F64; // FCVTAU Xd,Dn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTAU_64S_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint64_t vcvtad_u64_f64(float64_t a)
+ // argprep: a -> Sn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTAD_U64_F64; // FCVTAU Xd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTAU_ASIMDMISCFP16_R:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vcvta_u16_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCVTA_U16_F16; // FCVTAU Vd.4H,Vn.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vcvtaq_u16_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCVTAQ_U16_F16; // FCVTAU Vd.8H,Vn.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTAU_ASIMDMISC_R:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vcvta_u32_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCVTA_U32_F32; // FCVTAU Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vcvtaq_u32_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCVTAQ_U32_F32; // FCVTAU Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vcvtaq_u64_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCVTAQ_U64_F64; // FCVTAU Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCVTA_U16_F16; // FCVTAU Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCVTAQ_U16_F16; // FCVTAU Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTAU_ASISDMISCFP16_R:
- intrin_id = ARM64_INTRIN_VCVTAH_U16_F16; // FCVTAU Hd,Hn
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31))
+ // uint64_t vcvtah_u64_f16(float16_t a)
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCVTAH_U64_F16; // FCVTAU Hd,Hn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTAU_ASISDMISC_R:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint64_t vcvtad_u64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCVTAD_U64_F64; // FCVTAU Dd,Dn
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint32_t vcvtas_u32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCVTAS_U32_F32; // FCVTAU Sd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTL_ASIMDMISC_L:
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // float32x4_t vcvt_f32_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCVT_F32_F16; // FCVTL Vd.4S,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCVT_HIGH_F32_F16; // FCVTL2 Vd.4S,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // float64x2_t vcvt_f64_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCVT_F64_F32; // FCVTL Vd.2D,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // float32x4_t vcvt_high_f32_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VCVT_HIGH_F32_F16; // FCVTL2 Vd.4S,Vn.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // float64x2_t vcvt_high_f64_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCVT_HIGH_F64_F32; // FCVTL2 Vd.2D,Vn.4S
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTMS_32D_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTM_S64_F64; // FCVTMS Dd,Dn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int32_t vcvtmd_s32_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTMD_S32_F64; // FCVTMS Wd,Dn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTMS_32S_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTMS_S32_F32; // FCVTMS Sd,Sn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int32_t vcvtms_s32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTMS_S32_F32; // FCVTMS Wd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTMS_64D_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int64_t vcvtmd_s64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTMD_S64_F64; // FCVTMS Xd,Dn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTMS_64S_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int64_t vcvtmd_s64_f64(float64_t a)
+ // argprep: a -> Sn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTMD_S64_F64; // FCVTMS Xd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTMS_ASIMDMISCFP16_R:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // int16x4_t vcvtm_s16_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCVTM_S16_F16; // FCVTMS Vd.4H,Vn.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // int16x8_t vcvtmq_s16_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCVTMQ_S16_F16; // FCVTMS Vd.8H,Vn.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTMS_ASIMDMISC_R:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // int32x2_t vcvtm_s32_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCVTM_S32_F32; // FCVTMS Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // int32x4_t vcvtmq_s32_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCVTMQ_S32_F32; // FCVTMS Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // int64x2_t vcvtmq_s64_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCVTMQ_S64_F64; // FCVTMS Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCVTM_S16_F16; // FCVTMS Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCVTMQ_S16_F16; // FCVTMS Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTMS_ASISDMISCFP16_R:
- intrin_id = ARM64_INTRIN_VCVTMH_S16_F16; // FCVTMS Hd,Hn
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31))
+ // int64_t vcvtmh_s64_f16(float16_t a)
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCVTMH_S64_F16; // FCVTMS Hd,Hn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTMS_ASISDMISC_R:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int64_t vcvtmd_s64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCVTMD_S64_F64; // FCVTMS Dd,Dn
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int32_t vcvtms_s32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCVTMS_S32_F32; // FCVTMS Sd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTMU_32D_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTM_U64_F64; // FCVTMU Dd,Dn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint32_t vcvtmd_u32_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTMD_U32_F64; // FCVTMU Wd,Dn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTMU_32S_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTMS_U32_F32; // FCVTMU Sd,Sn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint32_t vcvtms_u32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTMS_U32_F32; // FCVTMU Wd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTMU_64D_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint64_t vcvtmd_u64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTMD_U64_F64; // FCVTMU Xd,Dn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTMU_64S_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint64_t vcvtmd_u64_f64(float64_t a)
+ // argprep: a -> Sn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTMD_U64_F64; // FCVTMU Xd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTMU_ASIMDMISCFP16_R:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vcvtm_u16_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCVTM_U16_F16; // FCVTMU Vd.4H,Vn.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vcvtmq_u16_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCVTMQ_U16_F16; // FCVTMU Vd.8H,Vn.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTMU_ASIMDMISC_R:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vcvtm_u32_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCVTM_U32_F32; // FCVTMU Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vcvtmq_u32_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCVTMQ_U32_F32; // FCVTMU Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vcvtmq_u64_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCVTMQ_U64_F64; // FCVTMU Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCVTM_U16_F16; // FCVTMU Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCVTMQ_U16_F16; // FCVTMU Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTMU_ASISDMISCFP16_R:
- intrin_id = ARM64_INTRIN_VCVTMH_U16_F16; // FCVTMU Hd,Hn
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31))
+ // uint64_t vcvtmh_u64_f16(float16_t a)
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCVTMH_U64_F16; // FCVTMU Hd,Hn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTMU_ASISDMISC_R:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint64_t vcvtmd_u64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCVTMD_U64_F64; // FCVTMU Dd,Dn
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint32_t vcvtms_u32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCVTMS_U32_F32; // FCVTMU Sd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTNS_32D_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTN_S64_F64; // FCVTNS Dd,Dn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int32_t vcvtnd_s32_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTND_S32_F64; // FCVTNS Wd,Dn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTNS_32S_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTNS_S32_F32; // FCVTNS Sd,Sn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int32_t vcvtns_s32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTNS_S32_F32; // FCVTNS Wd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTNS_64S_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int64_t vcvtns_s64_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTNS_S64_F32; // FCVTNS Xd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTNS_64D_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int64_t vcvtnd_s64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTND_S64_F64; // FCVTNS Xd,Dn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTNS_ASIMDMISCFP16_R:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // int16x4_t vcvtn_s16_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCVTN_S16_F16; // FCVTNS Vd.4H,Vn.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // int16x8_t vcvtnq_s16_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCVTNQ_S16_F16; // FCVTNS Vd.8H,Vn.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTNS_ASIMDMISC_R:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // int32x2_t vcvtn_s32_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCVTN_S32_F32; // FCVTNS Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // int32x4_t vcvtnq_s32_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCVTNQ_S32_F32; // FCVTNS Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // int64x2_t vcvtnq_s64_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCVTNQ_S64_F64; // FCVTNS Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCVTN_S16_F16; // FCVTNS Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCVTNQ_S16_F16; // FCVTNS Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTNS_ASISDMISCFP16_R:
- intrin_id = ARM64_INTRIN_VCVTNH_S16_F16; // FCVTNS Hd,Hn
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31))
+ // int64_t vcvtnh_s64_f16(float16_t a)
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCVTNH_S64_F16; // FCVTNS Hd,Hn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTNS_ASISDMISC_R:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int64_t vcvtnd_s64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCVTND_S64_F64; // FCVTNS Dd,Dn
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int32_t vcvtns_s32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCVTNS_S32_F32; // FCVTNS Sd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTNU_32D_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTN_U64_F64; // FCVTNU Dd,Dn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int32_t vcvtnd_u32_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTND_S32_F64; // FCVTNU Wd,Dn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTNU_32S_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTNS_U32_F32; // FCVTNU Sd,Sn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int32_t vcvtns_u32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTNS_U32_F32; // FCVTNU Wd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTNU_64S_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int64_t vcvtns_u64_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTNS_U64_F32; // FCVTNU Xd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTNU_64D_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int64_t vcvtnd_u64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTND_S64_F64; // FCVTNU Xd,Dn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTNU_ASIMDMISCFP16_R:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vcvtn_u16_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCVTN_U16_F16; // FCVTNU Vd.4H,Vn.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vcvtnq_u16_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCVTNQ_U16_F16; // FCVTNU Vd.8H,Vn.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTNU_ASIMDMISC_R:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vcvtn_u32_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCVTN_U32_F32; // FCVTNU Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vcvtnq_u32_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCVTNQ_U32_F32; // FCVTNU Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vcvtnq_u64_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCVTNQ_U64_F64; // FCVTNU Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCVTN_U16_F16; // FCVTNU Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCVTNQ_U16_F16; // FCVTNU Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTNU_ASISDMISCFP16_R:
- intrin_id = ARM64_INTRIN_VCVTNH_U16_F16; // FCVTNU Hd,Hn
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31))
+ // uint64_t vcvtnh_u64_f16(float16_t a)
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCVTNH_U64_F16; // FCVTNU Hd,Hn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTNU_ASISDMISC_R:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint64_t vcvtnd_u64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCVTND_U64_F64; // FCVTNU Dd,Dn
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint32_t vcvtns_u32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCVTNS_U32_F32; // FCVTNU Sd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTN_ASIMDMISC_N:
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // float16x4_t vcvt_f16_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCVT_F16_F32; // FCVTN Vd.4H,Vn.4S
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCVT_HIGH_F16_F32; // FCVTN2 Vd.8H,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // float32x2_t vcvt_f32_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCVT_F32_F64; // FCVTN Vd.2S,Vn.2D
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // float16x8_t vcvt_high_f16_f32(float16x4_t r, float32x4_t a)
+ // argprep: r -> Vd.4H; a -> Vn.4S
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCVT_HIGH_F16_F32; // FCVTN2 Vd.8H,Vn.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // float32x4_t vcvt_high_f32_f64(float32x2_t r, float64x2_t a)
+ // argprep: r -> Vd.2S; a -> Vn.2D
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCVT_HIGH_F32_F64; // FCVTN2 Vd.4S,Vn.2D
+ add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTPS_32D_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTP_S64_F64; // FCVTPS Dd,Dn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int32_t vcvtpd_s32_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTPD_S32_F64; // FCVTPS Wd,Dn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTPS_32S_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTPS_S32_F32; // FCVTPS Sd,Sn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int32_t vcvtps_s32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTPS_S32_F32; // FCVTPS Wd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTPS_64D_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int64_t vcvtpd_s64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTPD_S64_F64; // FCVTPS Xd,Dn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTPS_64S_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int64_t vcvtpd_s64_f64(float64_t a)
+ // argprep: a -> Sn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTPD_S64_F64; // FCVTPS Xd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTPS_ASIMDMISCFP16_R:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // int16x4_t vcvtp_s16_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCVTP_S16_F16; // FCVTPS Vd.4H,Vn.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // int16x8_t vcvtpq_s16_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCVTPQ_S16_F16; // FCVTPS Vd.8H,Vn.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTPS_ASIMDMISC_R:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // int32x2_t vcvtp_s32_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCVTP_S32_F32; // FCVTPS Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // int32x4_t vcvtpq_s32_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCVTPQ_S32_F32; // FCVTPS Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // int64x2_t vcvtpq_s64_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCVTPQ_S64_F64; // FCVTPS Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCVTP_S16_F16; // FCVTPS Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCVTPQ_S16_F16; // FCVTPS Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTPS_ASISDMISCFP16_R:
- intrin_id = ARM64_INTRIN_VCVTPH_S16_F16; // FCVTPS Hd,Hn
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31))
+ // int64_t vcvtph_s64_f16(float16_t a)
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCVTPH_S64_F16; // FCVTPS Hd,Hn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTPS_ASISDMISC_R:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int64_t vcvtpd_s64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCVTPD_S64_F64; // FCVTPS Dd,Dn
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int32_t vcvtps_s32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCVTPS_S32_F32; // FCVTPS Sd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTPU_32D_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTP_U64_F64; // FCVTPU Dd,Dn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint32_t vcvtpd_u32_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTPD_U32_F64; // FCVTPU Wd,Dn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ // case ENC_FCVTPU_32S_FLOAT2FIX:
+ // if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // // uint32_t vcvtps_n_u32_f32(float32_t a, const int n)
+ // // argprep: a -> Sn; n -> n
+ // // results: Wd -> result
+ // intrin_id = ARM64_INTRIN_VCVTPS_N_U32_F32; // FCVTPU Wd,Sn,#n
+ // add_input_reg(inputs, il, instr.operands[1]);
+ // add_input_imm(inputs, il, instr.operands[2]);
+ // add_output_reg(outputs, il, instr.operands[0]);
+ // break;
case ENC_FCVTPU_32S_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTPS_U32_F32; // FCVTPU Sd,Sn
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint32_t vcvtps_u32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTPS_U32_F32; // FCVTPU Wd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ // case ENC_FCVTPU_64D_FLOAT2FIX:
+ // if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // // uint64_t vcvtpd_n_u64_f64(float64_t a, const int n)
+ // // argprep: a -> Dn; n -> n
+ // // results: Xd -> result
+ // intrin_id = ARM64_INTRIN_VCVTPD_N_U64_F64; // FCVTPU Xd,Dn,#n
+ // add_input_reg(inputs, il, instr.operands[1]);
+ // add_input_imm(inputs, il, instr.operands[2]);
+ // add_output_reg(outputs, il, instr.operands[0]);
+ // break;
+ case ENC_FCVTPU_64D_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint64_t vcvtpd_u64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTPD_U64_F64; // FCVTPU Xd,Dn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTPU_64S_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint64_t vcvtpd_u64_f64(float64_t a)
+ // argprep: a -> Sn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTPD_U64_F64; // FCVTPU Xd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTPU_ASIMDMISCFP16_R:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vcvtp_u16_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCVTP_U16_F16; // FCVTPU Vd.4H,Vn.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vcvtpq_u16_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCVTPQ_U16_F16; // FCVTPU Vd.8H,Vn.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTPU_ASIMDMISC_R:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vcvtp_u32_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCVTP_U32_F32; // FCVTPU Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vcvtpq_u32_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCVTPQ_U32_F32; // FCVTPU Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vcvtpq_u64_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCVTPQ_U64_F64; // FCVTPU Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCVTP_U16_F16; // FCVTPU Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCVTPQ_U16_F16; // FCVTPU Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTPU_ASISDMISCFP16_R:
- intrin_id = ARM64_INTRIN_VCVTPH_U16_F16; // FCVTPU Hd,Hn
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31))
+ // uint64_t vcvtph_u64_f16(float16_t a)
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCVTPH_U64_F16; // FCVTPU Hd,Hn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTPU_ASISDMISC_R:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint64_t vcvtpd_u64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCVTPD_U64_F64; // FCVTPU Dd,Dn
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint32_t vcvtps_u32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCVTPS_U32_F32; // FCVTPU Sd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTXN_ASIMDMISC_N:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // float32x2_t vcvtx_f32_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCVTX_F32_F64; // FCVTXN Vd.2S,Vn.2D
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // float32x4_t vcvtx_high_f32_f64(float32x2_t r, float64x2_t a)
+ // argprep: r -> Vd.2S; a -> Vn.2D
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCVTX_HIGH_F32_F64; // FCVTXN2 Vd.4S,Vn.2D
+ add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTXN_ASISDMISC_N:
- intrin_id = ARM64_INTRIN_VCVTXD_F32_F64; // FCVTXN Sd,Dn
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // float32_t vcvtxd_f32_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCVTXD_F32_F64; // FCVTXN Sd,Dn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_FCVTZS_64D_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTD_S64_F64; // FCVTZS Xd,Dn
+ case ENC_FCVTZS_32D_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int32_t vcvtd_s32_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTD_S32_F64; // FCVTZS Wd,Dn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_FCVTZS_32D_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVT_S64_F64; // FCVTZS Dd,Dn
+ case ENC_FCVTZS_32S_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int32_t vcvts_s32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTS_S32_F32; // FCVTZS Wd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_FCVTZS_32S_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTS_S32_F32; // FCVTZS Sd,Sn
+ case ENC_FCVTZS_64D_FLOAT2FIX:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int64_t vcvtd_n_s64_f64(float64_t a, const int n)
+ // argprep: a -> Dn; n -> n
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTD_N_S64_F64; // FCVTZS Xd,Dn,#n
add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_FCVTZS_ASIMDMISCFP16_R:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCVT_S32_F32; // FCVTZS Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCVTQ_S32_F32; // FCVTZS Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VCVTQ_S64_F64; // FCVTZS Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ case ENC_FCVTZS_64D_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int64_t vcvtd_s64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTD_S64_F64; // FCVTZS Xd,Dn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTZS_64S_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int64_t vcvts_s64_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTS_S64_F32; // FCVTZS Xd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTZS_ASIMDSHF_C:
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int16x4_t vcvt_n_s16_f16(float16x4_t a, const int n)
+ // argprep: a -> Vn.4H; n -> n
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCVT_N_S16_F16; // FCVTZS Vd.4H,Vn.4H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int32x2_t vcvt_n_s32_f32(float32x2_t a, const int n)
+ // argprep: a -> Vn.2S; n -> n
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCVT_N_S32_F32; // FCVTZS Vd.2S,Vn.2S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int16x8_t vcvtq_n_s16_f16(float16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> n
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCVTQ_N_S16_F16; // FCVTZS Vd.8H,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int32x4_t vcvtq_n_s32_f32(float32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> n
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCVTQ_N_S32_F32; // FCVTZS Vd.4S,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int64x2_t vcvtq_n_s64_f64(float64x2_t a, const int n)
+ // argprep: a -> Vn.2D; n -> n
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCVTQ_N_S64_F64; // FCVTZS Vd.2D,Vn.2D,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCVT_S16_F16; // FCVTZS Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCVTQ_S16_F16; // FCVTZS Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTZS_ASIMDMISCFP16_R:
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vcvt_u16_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCVT_U16_F16; // FCVTZS Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vcvtq_u16_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VCVTQ_U16_F16; // FCVTZS Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCVT_N_S16_F16; // FCVTZS Vd.4H,Vn.4H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCVTQ_N_S16_F16; // FCVTZS Vd.8H,Vn.8H,#n
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_FCVTZS_ASISDMISCFP16_R:
- intrin_id = ARM64_INTRIN_VCVTH_S16_F16; // FCVTZS Hd,Hn
+ case ENC_FCVTZS_ASIMDMISC_R:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // int32x2_t vcvt_s32_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VCVT_S32_F32; // FCVTZS Vd.2S,Vn.2S
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // int32x4_t vcvtq_s32_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VCVTQ_S32_F32; // FCVTZS Vd.4S,Vn.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // int64x2_t vcvtq_s64_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VCVTQ_S64_F64; // FCVTZS Vd.2D,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_FCVTZU_64D_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTD_U64_F64; // FCVTZU Xd,Dn
+ case ENC_FCVTZS_ASISDMISCFP16_R:
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31))
+ // int16_t vcvth_s16_f16(float16_t a)
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCVTH_S16_F16; // FCVTZS Hd,Hn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_FCVTZU_32D_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVT_U64_F64; // FCVTZU Dd,Dn
+ case ENC_FCVTZS_ASISDMISC_R:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int64_t vcvtd_s64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCVTD_S64_F64; // FCVTZS Dd,Dn
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int32_t vcvts_s32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCVTS_S32_F32; // FCVTZS Sd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_FCVTZU_32S_FLOAT2INT:
- intrin_id = ARM64_INTRIN_VCVTS_U32_F32; // FCVTZU Sd,Sn
+ case ENC_FCVTZS_ASISDSHF_C:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int64_t vcvtd_n_s64_f64(float64_t a, const int n)
+ // argprep: a -> Dn; n -> n
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCVTD_N_S64_F64; // FCVTZS Dd,Dn,#n
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int16_t vcvth_n_s16_f16(float16_t a, const int n)
+ // argprep: a -> Hn; n -> n
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCVTH_N_S16_F16; // FCVTZS Hd,Hn,#n
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int32_t vcvts_n_s32_f32(float32_t a, const int n)
+ // argprep: a -> Sn; n -> n
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCVTS_N_S32_F32; // FCVTZS Sd,Sn,#n
add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_UCVTF_D32_FLOAT2FIX:
- intrin_id = ARM64_INTRIN_VCVTD_N_F64_U32; // UCVTF <Dd>, <Wn>, #<fbits>
+ case ENC_FCVTZU_32D_FLOAT2FIX:
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32_t vcvts_n_u32_f64(float64_t a, const int n)
+ // argprep: a -> Dn; n -> n
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTD_N_U32_F64; // FCVTZU Wd,Dn,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_UCVTF_D64_FLOAT2FIX:
- intrin_id = ARM64_INTRIN_VCVTD_N_F64_U64; // UCVTF <Dd>, <Xn>, #<fbits>
+ case ENC_FCVTZU_32D_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint32_t vcvtd_u32_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTD_U32_F64; // FCVTZU Wd,Dn
add_input_reg(inputs, il, instr.operands[1]);
- add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_UCVTF_H32_FLOAT2FIX:
- intrin_id = ARM64_INTRIN_VCVTH_N_F16_U32; // UCVTF <Hd>, <Wn>, #<fbits>
+ case ENC_FCVTZU_32S_FLOAT2FIX:
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32_t vcvts_n_u32_f32(float32_t a, const int n)
+ // argprep: a -> Sn; n -> n
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTS_N_U32_F32; // FCVTZU Wd,Sn,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_UCVTF_H64_FLOAT2FIX: // UCVTF <Hd>, <Xn>, #<fbits>
- intrin_id = ARM64_INTRIN_VCVTH_N_F16_U64;
+ case ENC_FCVTZU_32S_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_W0 && instr.operands[0].reg[0] <= REG_WSP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint32_t vcvts_u32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTS_U32_F32; // FCVTZU Wd,Sn
add_input_reg(inputs, il, instr.operands[1]);
- add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTZU_64D_FLOAT2FIX:
- intrin_id = ARM64_INTRIN_VCVTD_N_U64_F64; // FCVTZU Xd, Dn, #n
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint64_t vcvts_n_u32_f64(float64_t a, const int n)
+ // argprep: a -> Dn; n -> n
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTD_N_U32_F64; // FCVTZU Xd,Dn,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_UCVTF_S32_FLOAT2FIX:
- intrin_id = ARM64_INTRIN_VCVTS_N_F32_U32; // ucvtf <Sd>, <Wn>, #<fbits>
+ case ENC_FCVTZU_64D_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint64_t vcvtd_u64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTD_U64_F64; // FCVTZU Xd,Dn
add_input_reg(inputs, il, instr.operands[1]);
- add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_UCVTF_S64_FLOAT2FIX:
- intrin_id = ARM64_INTRIN_VCVTS_N_F32_U64; // ucvtf <Sd>, <Xn>, #<fbits>
+ case ENC_FCVTZU_64S_FLOAT2FIX:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint64_t vcvts_n_u32_f32(float32_t a, const int n)
+ // argprep: a -> Sn; n -> n
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTS_N_U64_F32; // FCVTZU Xd,Sn,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FCVTZU_64S_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_X0 && instr.operands[0].reg[0] <= REG_SP) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint61_t vcvtd_u64_f32(float32x1_t a)
+ // argprep: a -> Sn
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVT_U64_F32; // FCVTZU Xd,Sn FIXME: ARM64_INTRIN_VCVTD_U64_F32
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FCVTZU_ASIMDMISC_R:
- // Lift instruction such as fcvtzu v23.4s, v22.4s and fcvtzu v9.2d, v18.2d
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vcvt_u32_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCVT_U32_F32; // FCVTZU Vd.2S,Vn.2S
- else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vcvtq_u32_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCVTQ_U32_F32; // FCVTZU Vd.4S,Vn.4S
- else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vcvtq_u64_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCVTQ_U64_F64; // FCVTZU Vd.2D,Vn.2D
- else
- break; // Should be unreachable.
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FCVTZU_ASIMDSHF_C:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x4_t vcvt_n_u16_f16(float16x4_t a, const int n)
+ // argprep: a -> Vn.4H; n -> n
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VCVT_N_U16_F16; // FCVTZU Vd.4H,Vn.4H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x2_t vcvt_n_u32_f32(float32x2_t a, const int n)
+ // argprep: a -> Vn.2S; n -> n
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCVT_N_U32_F32; // FCVTZU Vd.2S,Vn.2S,#n
- else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x8_t vcvtq_n_u16_f16(float16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> n
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCVTQ_N_U16_F16; // FCVTZU Vd.8H,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x4_t vcvtq_n_u32_f32(float32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> n
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCVTQ_N_U32_F32; // FCVTZU Vd.4S,Vn.4S,#n
- else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint64x2_t vcvtq_n_u64_f64(float64x2_t a, const int n)
+ // argprep: a -> Vn.2D; n -> n
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCVTQ_N_U64_F64; // FCVTZU Vd.2D,Vn.2D,#n
- else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCVT_N_U16_F16; // FCVTZU Vd.4H,Vn.4H,#n
- else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCVTQ_N_U16_F16; // FCVTZU Vd.8H,Vn.8H,#n
- else
- break; // Should be unreachable
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_FCVTZU_ASIMDMISCFP16_R:
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VCVT_U16_F16; // FCVTZU Vd.4H,Vn.4H
- else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCVTQ_U16_F16; // FCVTZU Vd.8H,Vn.8H
- else
- break; // Should be unreachable
+ case ENC_FCVTZU_ASISDMISCFP16_R:
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31))
+ // uint16_t vcvth_u16_f16(float16_t a)
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCVTH_U16_F16; // FCVTZU Hd,Hn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_FCVTZU_ASISDMISCFP16_R:
- intrin_id = ARM64_INTRIN_VCVTH_U16_F16; // FCVTZU Hd,Hn
+ case ENC_FCVTZU_ASISDMISC_R:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint64_t vcvtd_u64_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCVTD_U64_F64; // FCVTZU Dd,Dn
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint32_t vcvts_u32_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCVTS_U32_F32; // FCVTZU Sd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FCVTZU_ASISDSHF_C:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint64_t vcvtd_n_u64_f64(float64_t a, const int n)
+ // argprep: a -> Dn; n -> n
+ // results: Xd -> result
+ intrin_id = ARM64_INTRIN_VCVTD_N_U64_F64; // FCVTZU Dd,Dn,#n
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16_t vcvth_n_u16_f16(float16_t a, const int n)
+ // argprep: a -> Hn; n -> n
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCVTH_N_U16_F16; // FCVTZU Hd,Hn,#n
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32_t vcvts_n_u32_f32(float32_t a, const int n)
+ // argprep: a -> Sn; n -> n
+ // results: Wd -> result
+ intrin_id = ARM64_INTRIN_VCVTS_N_U32_F32; // FCVTZU Sd,Sn,#n
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_SCVTF_D32_FLOAT2FIX:
+ intrin_id = ARM64_INTRIN_VCVTD_N_F64_S32; // SCVTF <Dd>, <Wn>, #<fbits>
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_SCVTF_D64_FLOAT2FIX:
+ intrin_id = ARM64_INTRIN_VCVTD_N_F64_S64; // SCVTF <Dd>, <Xn>, #<fbits>
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_SCVTF_H32_FLOAT2FIX:
+ intrin_id = ARM64_INTRIN_VCVTH_N_F16_S32; // SCVTF <Hd>, <Wn>, #<fbits>
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_SCVTF_H64_FLOAT2FIX: // SCVTF <Hd>, <Xn>, #<fbits>
+ intrin_id = ARM64_INTRIN_VCVTH_N_F16_S64;
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_SCVTF_S32_FLOAT2FIX:
+ intrin_id = ARM64_INTRIN_VCVTS_N_F32_S32; // scvtf <Sd>, <Wn>, #<fbits>
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_SCVTF_S64_FLOAT2FIX:
+ intrin_id = ARM64_INTRIN_VCVTS_N_F32_S64; // scvtf <Sd>, <Xn>, #<fbits>
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_UCVTF_D32_FLOAT2FIX:
+ intrin_id = ARM64_INTRIN_VCVTD_N_F64_U32; // UCVTF <Dd>, <Wn>, #<fbits>
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_UCVTF_D64_FLOAT2FIX:
+ intrin_id = ARM64_INTRIN_VCVTD_N_F64_U64; // UCVTF <Dd>, <Xn>, #<fbits>
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_UCVTF_H32_FLOAT2FIX:
+ intrin_id = ARM64_INTRIN_VCVTH_N_F16_U32; // UCVTF <Hd>, <Wn>, #<fbits>
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_UCVTF_H64_FLOAT2FIX: // UCVTF <Hd>, <Xn>, #<fbits>
+ intrin_id = ARM64_INTRIN_VCVTH_N_F16_U64;
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_UCVTF_S32_FLOAT2FIX:
+ intrin_id = ARM64_INTRIN_VCVTS_N_F32_U32; // ucvtf <Sd>, <Wn>, #<fbits>
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_UCVTF_S64_FLOAT2FIX:
+ intrin_id = ARM64_INTRIN_VCVTS_N_F32_U64; // ucvtf <Sd>, <Xn>, #<fbits>
add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FDIV_D_FLOATDP2:
@@ -15710,22 +18019,29 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FDIV_S_FLOATDP2:
+ intrin_id = ARM64_INTRIN_VDIV_F32; // FDIV Sd,Sn,Sm
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FDIV_H_FLOATDP2:
intrin_id = ARM64_INTRIN_VDIVH_F16; // FDIV Hd,Hn,Hm
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FDIV_ASIMDSAME_ONLY:
case ENC_FDIV_ASIMDSAMEFP16_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VDIV_F32; // FDIV Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VDIVQ_F32; // FDIV Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VDIVQ_F64; // FDIV Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VDIV_F16; // FDIV Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VDIVQ_F16; // FDIV Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -15738,6 +18054,13 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FMADD_S_FLOATDP3:
+ intrin_id = ARM64_INTRIN_VFMA_F32; // FMADD Sd,Sn,Sm,Sa
+ add_input_reg(inputs, il, instr.operands[3]);
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FMADD_H_FLOATDP3:
intrin_id = ARM64_INTRIN_VFMAH_F16; // FMADD Hd,Hn,Hm,Ha
add_input_reg(inputs, il, instr.operands[3]);
@@ -15746,78 +18069,185 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMAXNMP_ASIMDSAMEFP16_ONLY:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // float16x4_t vpmaxnm_f16(float16x4_t a, float16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VPMAXNM_F16; // FMAXNMP Vd.4H,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // float16x8_t vpmaxnmq_f16(float16x8_t a, float16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VPMAXNMQ_F16; // FMAXNMP Vd.8H,Vn.8H,Vm.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMAXNMP_ASIMDSAME_ONLY:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // float32x2_t vpmaxnm_f32(float32x2_t a, float32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VPMAXNM_F32; // FMAXNMP Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // float32x4_t vpmaxnmq_f32(float32x4_t a, float32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VPMAXNMQ_F32; // FMAXNMP Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // float64x2_t vpmaxnmq_f64(float64x2_t a, float64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VPMAXNMQ_F64; // FMAXNMP Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VPMAXNM_F16; // FMAXNMP Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VPMAXNMQ_F16; // FMAXNMP Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMAXNMP_ASISDPAIR_ONLY_H:
- intrin_id = ARM64_INTRIN_VPMAXNMS_F32; // FMAXNMP Sd,Vn.2S
+ // None of these are valid instructions, but they are in the spec
+ // if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // // float16_t vmaxnmv_f16(float16x4_t a)
+ // // argprep: a -> Vn.4H
+ // // results: Hd -> result
+ // intrin_id = ARM64_INTRIN_VMAXNMV_F16; // FMAXNMP Hd,Vn.4H
+ // else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // // float16_t vmaxnmvq_f16(float16x8_t a)
+ // // argprep: a -> Vn.8H
+ // // results: Hd -> result
+ // intrin_id = ARM64_INTRIN_VMAXNMVQ_F16; // FMAXNMP Hd,Vn.8H
+ // The only valid instruction is FMAXNMP Hd,Vn.2H
+ intrin_id = ARM64_INTRIN_VMAXNMV_F16; // FMAXNMP Hd,Vn.2H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMAXNMP_ASISDPAIR_ONLY_SD:
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // float32_t vpmaxnms_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VPMAXNMS_F32; // FMAXNMP Sd,Vn.2S
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // float64_t vpmaxnmqd_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VPMAXNMQD_F64; // FMAXNMP Dd,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMAXNMV_ASIMDALL_ONLY_H:
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // float16_t vmaxnmvq_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VMAXNMVQ_F16; // FMAXNMV Hd,Hn.4H
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // float16_t vmaxnmvq_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VMAXNMVQ_F16; // FMAXNMV Hd,Hn.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMAXNMV_ASIMDALL_ONLY_SD:
intrin_id = ARM64_INTRIN_VMAXNMVQ_F32; // FMAXNMV Sd,Vn.4S
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMAXNM_D_FLOATDP2:
- intrin_id = ARM64_INTRIN_VMAXNM_F64; // FMAXNM Dd,Dn,Dm
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].reg[0] >= REG_D0 && instr.operands[2].reg[0] <= REG_D31))
+ // float64x1_t vmaxnm_f64(float64x1_t a, float64x1_t b)
+ // argprep: a -> Dn; b -> Dm
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VMAXNM_F64; // FMAXNM Dd,Dn,Dm
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMAXNM_H_FLOATDP2:
- intrin_id = ARM64_INTRIN_VMAXNMH_F16; // FMAXNM Hd,Hn,Hm
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].reg[0] >= REG_H0 && instr.operands[2].reg[0] <= REG_H31))
+ // float16_t vmaxnmh_f16(float16_t a, float16_t b)
+ // argprep: a -> Hn; b -> Hm
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VMAXNMH_F16; // FMAXNM Hd,Hn,Hm
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FMAXNM_S_FLOATDP2:
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].reg[0] >= REG_S0 && instr.operands[2].reg[0] <= REG_S31))
+ // float32x1_t vmaxnm_f32(float32x1_t a, float32x1_t b)
+ // argprep: a -> Sn; b -> Sm
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VMAXNM_F32; // FMAXNM Sd,Sn,Sm
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break; case ENC_FMAXNM_ASIMDSAME_ONLY:
case ENC_FMAXNM_ASIMDSAMEFP16_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VMAXNM_F32; // FMAXNM Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ intrin_id = ARM64_INTRIN_VMAXNM__F32; // FMAXNM Vd.2S,Vn.2S,Vm.2S
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMAXNMQ_F32; // FMAXNM Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMAXNMQ_F64; // FMAXNM Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMAXNM_F16; // FMAXNM Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMAXNMQ_F16; // FMAXNM Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FMAXP_ASIMDSAME_ONLY:
case ENC_FMAXP_ASIMDSAMEFP16_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VPMAX_F32; // FMAXP Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VPMAXQ_F32; // FMAXP Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VPMAXQ_F64; // FMAXP Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VPMAX_F16; // FMAXP Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VPMAXQ_F16; // FMAXP Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMAXP_ASISDPAIR_ONLY_H:
- intrin_id = ARM64_INTRIN_VPMAXS_F32; // FMAXP Sd,Vn.2S
+ intrin_id = ARM64_INTRIN_VMAXV_F16; // FMAXP Hd,Vn.2H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMAXP_ASISDPAIR_ONLY_SD:
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // float32_t vpmaxs_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VPMAXS_F32; // FMAXP Sd,Vn.2S
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // float64_t vpmaxqd_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VPMAXQD_F64; // FMAXP Dd,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMAXV_ASIMDALL_ONLY_H:
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // float16_t vmaxvq_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VMAXVQ_F16; // FMAXV Hd,Hn.4H
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // float16_t vmaxvq_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VMAXVQ_F16; // FMAXV Hd,Hn.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMAXV_ASIMDALL_ONLY_SD:
intrin_id = ARM64_INTRIN_VMAXVQ_F32; // FMAXV Sd,Vn.4S
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -15828,48 +18258,85 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FMAX_S_FLOATDP2:
+ intrin_id = ARM64_INTRIN_VMAX_F32; // FMAX Sd,Sn,Sm
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FMAX_H_FLOATDP2:
intrin_id = ARM64_INTRIN_VMAXH_F16; // FMAX Hd,Hn,Hm
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FMAX_ASIMDSAME_ONLY:
case ENC_FMAX_ASIMDSAMEFP16_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMAX_F32; // FMAX Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMAXQ_F32; // FMAX Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMAXQ_F64; // FMAX Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMAX_F16; // FMAX Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMAXQ_F16; // FMAX Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FMINNMP_ASIMDSAME_ONLY:
case ENC_FMINNMP_ASIMDSAMEFP16_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VPMINNM_F32; // FMINNMP Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VPMINNMQ_F32; // FMINNMP Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VPMINNMQ_F64; // FMINNMP Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VPMINNM_F16; // FMINNMP Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VPMINNMQ_F16; // FMINNMP Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMINNMP_ASISDPAIR_ONLY_H:
- intrin_id = ARM64_INTRIN_VPMINNMS_F32; // FMINNMP Sd,Vn.2S
+ // intrin_id = ARM64_INTRIN_VPMINNMS_F32; // FMINNMP Sd,Vn.2S
+ intrin_id = ARM64_INTRIN_VMINNMV_F16; // FMINP Hd,Vn.2H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMINNMP_ASISDPAIR_ONLY_SD:
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // float32_t vpminnms_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VPMINNMS_F32; // FMINNMP Sd,Vn.2S
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // float64_t vpminnmqd_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VPMINNMQD_F64; // FMINNMP Dd,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMINNMV_ASIMDALL_ONLY_H:
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // float16_t vminnmv_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VMINNMV_F16; // FMINNMV Hd,Vn.4H
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // float16_t vminnmvq_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VMINNMVQ_F16; // FMINNMV Hd,Vn.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMINNMV_ASIMDALL_ONLY_SD:
intrin_id = ARM64_INTRIN_VMINNMVQ_F32; // FMINNMV Sd,Vn.4S
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -15880,54 +18347,115 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FMINNM_S_FLOATDP2:
+ intrin_id = ARM64_INTRIN_VMINNM_F32; // FMINNM Sd,Sn,Sm
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FMINNM_H_FLOATDP2:
intrin_id = ARM64_INTRIN_VMINNMH_F16; // FMINNM Hd,Hn,Hm
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FMINNM_ASIMDSAME_ONLY:
case ENC_FMINNM_ASIMDSAMEFP16_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMINNM_F32; // FMINNM Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMINNMQ_F32; // FMINNM Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMINNMQ_F64; // FMINNM Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMINNM_F16; // FMINNM Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMINNMQ_F16; // FMINNM Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FMINP_ASIMDSAME_ONLY:
case ENC_FMINP_ASIMDSAMEFP16_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VPMIN_F32; // FMINP Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VPMINQ_F32; // FMINP Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VPMINQ_F64; // FMINP Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VPMIN_F16; // FMINP Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VPMINQ_F16; // FMINP Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMINP_ASISDPAIR_ONLY_H:
- intrin_id = ARM64_INTRIN_VPMINS_F32; // FMINP Sd,Vn.2S
+ // intrin_id = ARM64_INTRIN_VPMINS_F32; // FMINP Sd,Vn.2S
+ intrin_id = ARM64_INTRIN_VMINV_F16; // FMINP Hd,Vn.2H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMINP_ASISDPAIR_ONLY_SD:
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // float32_t vpmins_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VPMINS_F32; // FMINP Sd,Vn.2S
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // float64_t vpminqd_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VPMINQD_F64; // FMINP Dd,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMINV_ASIMDALL_ONLY_H:
- intrin_id = ARM64_INTRIN_VMINVQ_F32; // FMINV Sd,Vn.4S
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // float16_t vminv_f16(float16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VMINV_F16; // FMINV Hd,Vn.4H
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // float16_t vminvq_f16(float16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VMINVQ_F16; // FMINV Hd,Vn.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMINV_ASIMDALL_ONLY_SD:
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // float32_t vminv_f32(float32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VMINV_F32; // FMINV Sd,Vn.2S
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // float32_t vminvq_f32(float32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VMINVQ_F32; // FMINV Sd,Vn.4S
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // float64_t vminvq_f64(float64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VMINVQ_F64; // FMINV Dd,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMIN_D_FLOATDP2:
- intrin_id = ARM64_INTRIN_VMIN_F64; // FMIN Dd,Dn,Dm
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].reg[0] >= REG_D0 && instr.operands[2].reg[0] <= REG_D31))
+ // float64x1_t vmin_f64(float64x1_t a, float64x1_t b)
+ // argprep: a -> Dn; b -> Dm
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VMIN_F64; // FMIN Dd,Dn,Dm
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMIN_S_FLOATDP2:
+ intrin_id = ARM64_INTRIN_VMIN_F32; // FMIN Sd,Sn,Sm
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -15938,16 +18466,17 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FMIN_ASIMDSAME_ONLY:
case ENC_FMIN_ASIMDSAMEFP16_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMIN_F32; // FMIN Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMINQ_F32; // FMIN Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMINQ_F64; // FMIN Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMIN_F16; // FMIN Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMINQ_F16; // FMIN Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -15956,11 +18485,11 @@ bool NeonGetLowLevelILForInstruction(
case ENC_FMLAL2_ASIMDELEM_LH:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VFMLAL_LANE_HIGH_F16; // FMLAL2 Vd.2S,Vn.2H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VFMLALQ_LANE_HIGH_F16; // FMLAL2 Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VFMLAL_LANEQ_HIGH_F16; // FMLAL2 Vd.2S,Vn.2H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VFMLALQ_LANEQ_HIGH_F16; // FMLAL2 Vd.4S,Vn.4H,Vm.H[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -15971,7 +18500,7 @@ bool NeonGetLowLevelILForInstruction(
case ENC_FMLAL2_ASIMDSAME_F:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VFMLAL_HIGH_F16; // FMLAL2 Vd.2S,Vn.2H,Vm.2H
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VFMLALQ_HIGH_F16; // FMLAL2 Vd.4S,Vn.4H,Vm.4H
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -15981,11 +18510,11 @@ bool NeonGetLowLevelILForInstruction(
case ENC_FMLAL_ASIMDELEM_LH:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VFMLAL_LANE_LOW_F16; // FMLAL Vd.2S,Vn.2H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VFMLAL_LANEQ_LOW_F16; // FMLAL Vd.2S,Vn.2H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VFMLALQ_LANE_LOW_F16; // FMLAL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VFMLALQ_LANEQ_LOW_F16; // FMLAL Vd.4S,Vn.4H,Vm.H[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -15996,7 +18525,7 @@ bool NeonGetLowLevelILForInstruction(
case ENC_FMLAL_ASIMDSAME_F:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VFMLAL_LOW_F16; // FMLAL Vd.2S,Vn.2H,Vm.2H
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VFMLALQ_LOW_F16; // FMLAL Vd.4S,Vn.4H,Vm.4H
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -16004,25 +18533,15 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMLA_ASIMDELEM_RH_H:
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VFMA_LANE_F32; // FMLA Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VFMAQ_LANE_F32; // FMLA Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VFMAQ_LANE_F64; // FMLA Vd.2D,Vn.2D,Vm.D[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VFMA_LANEQ_F32; // FMLA Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VFMAQ_LANEQ_F32; // FMLA Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VFMAQ_LANEQ_F64; // FMLA Vd.2D,Vn.2D,Vm.D[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VFMA_LANE_F16; // FMLA Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VFMAQ_LANE_F16; // FMLA Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // float16x4_t vfma_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t v, const int lane)
+ // argprep: a -> Vd.4H; b -> Vn.4H; v -> Vm.8H; lane -> <lane>
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VFMA_LANEQ_F16; // FMLA Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // float16x8_t vfmaq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t v, const int lane)
+ // argprep: a -> Vd.8H; b -> Vn.8H; v -> Vm.8H; lane -> <lane>
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VFMAQ_LANEQ_F16; // FMLA Vd.8H,Vn.8H,Vm.H[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -16030,34 +18549,128 @@ bool NeonGetLowLevelILForInstruction(
add_input_lane(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_FMLA_ASIMDSAMEFP16_ONLY:
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VFMA_F32; // FMLA Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VFMAQ_F32; // FMLA Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VFMAQ_F64; // FMLA Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ case ENC_FMLA_ASIMDELEM_R_SD:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].laneUsed)
+ // float32x2_t vfma_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v, const int lane)
+ // argprep: a -> Vd.2S; b -> Vn.2S; v -> Vm.2S; lane -> <lane>
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VFMA_LANE_F32; // FMLA Vd.2S,Vn.2S,Vm.S[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].laneUsed)
+ // float32x2_t vfma_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v, const int lane)
+ // argprep: a -> Vd.2S; b -> Vn.2S; v -> Vm.4S; lane -> <lane>
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VFMA_LANEQ_F32; // FMLA Vd.2S,Vn.2S,Vm.S[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].laneUsed)
+ // float16x4_t vfma_n_f16(float16x4_t a, float16x4_t b, float16_t n)
+ // argprep: a -> Vd.4H; b -> Vn.4H; n -> <n>
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VFMA_N_F16; // FMLA Vd.4H,Vn.4H,Vm.H[0]
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].laneUsed)
+ // float32x2_t vfma_n_f32(float32x2_t a, float32x2_t b, float32_t n)
+ // argprep: a -> Vd.2S; b -> Vn.2S; n -> <n>
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VFMA_N_F32; // FMLA Vd.2S,Vn.2S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].laneUsed)
+ // float32x4_t vfmaq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v, const int lane)
+ // argprep: a -> Vd.4S; b -> Vn.4S; v -> Vm.2S; lane -> <lane>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VFMAQ_LANE_F32; // FMLA Vd.4S,Vn.4S,Vm.S[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_1DOUBLE && instr.operands[2].laneUsed)
+ // float64x2_t vfmaq_lane_f64(float64x2_t a, float64x2_t b, float64x1_t v, const int lane)
+ // argprep: a -> Vd.2D; b -> Vn.2D; v -> Vm.1D; lane -> <lane>
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VFMAQ_LANE_F64; // FMLA Vd.2D,Vn.2D,Vm.D[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].laneUsed)
+ // float32x4_t vfmaq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v, const int lane)
+ // argprep: a -> Vd.4S; b -> Vn.4S; v -> Vm.4S; lane -> <lane>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VFMAQ_LANEQ_F32; // FMLA Vd.4S,Vn.4S,Vm.S[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].laneUsed)
+ // float64x2_t vfmaq_laneq_f64(float64x2_t a, float64x2_t b, float64x2_t v, const int lane)
+ // argprep: a -> Vd.2D; b -> Vn.2D; v -> Vm.2D; lane -> <lane>
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VFMAQ_LANEQ_F64; // FMLA Vd.2D,Vn.2D,Vm.D[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].laneUsed)
+ // float32x4_t vfmaq_n_f32(float32x4_t a, float32x4_t b, float32_t n)
+ // argprep: a -> Vd.4S; b -> Vn.4S; n -> <n>
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VFMAQ_N_F32; // FMLA Vd.4S,Vn.4S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].laneUsed)
+ // float64x2_t vfmaq_n_f64(float64x2_t a, float64x2_t b, float64_t n)
+ // argprep: a -> Vd.2D; b -> Vn.2D; n -> <n>
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VFMAQ_N_F64; // FMLA Vd.2D,Vn.2D,Vm.D[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ add_input_reg(inputs, il, instr.operands[0]);
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_lane(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMLA_ASIMDSAMEFP16_ONLY:
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // float16x4_t vfma_f16(float16x4_t a, float16x4_t b, float16x4_t c)
+ // argprep: a -> Vd.4H; b -> Vn.4H; c -> Vm.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VFMA_F16; // FMLA Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // float16x8_t vfmaq_f16(float16x8_t a, float16x8_t b, float16x8_t c)
+ // argprep: a -> Vd.8H; b -> Vn.8H; c -> Vm.8H
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VFMAQ_F16; // FMLA Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VFMA_N_F16; // FMLA Vd.4H,Vn.4H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // float16x8_t vfmaq_n_f16(float16x8_t a, float16x8_t b, float16_t n)
+ // argprep: a -> Vd.8H; b -> Vn.8H; n -> Vm.H[0]
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VFMAQ_N_F16; // FMLA Vd.8H,Vn.8H,Vm.H[0]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
+ add_input_lane(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMLA_ASIMDSAME_ONLY:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // float32x2_t vfma_f32(float32x2_t a, float32x2_t b, float32x2_t c)
+ // argprep: a -> Vd.2S; b -> Vn.2S; c -> Vm.2S
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VFMA_F32; // FMLA Vd.2S,Vn.2S,Vm.2S
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // float32x4_t vfmaq_f32(float32x4_t a, float32x4_t b, float32x4_t c)
+ // argprep: a -> Vd.4S; b -> Vn.4S; c -> Vm.4S
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VFMAQ_F32; // FMLA Vd.4S,Vn.4S,Vm.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // float64x2_t vfmaq_f64(float64x2_t a, float64x2_t b, float64x2_t c)
+ // argprep: a -> Vd.2D; b -> Vn.2D; c -> Vm.2D
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VFMAQ_F64; // FMLA Vd.2D,Vn.2D,Vm.2D
+ add_input_reg(inputs, il, instr.operands[0]);
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMLA_ASISDELEM_RH_H:
- intrin_id = ARM64_INTRIN_VFMA_LANE_F64; // FMLA Dd,Dn,Vm.D[lane]
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // float16_t vfmah_laneq_f16(float16_t a, float16_t b, float16x8_t v, const int lane)
+ // argprep: a -> Hd; b -> Hn; v -> Vm.8H; lane -> <lane>
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VFMAH_LANEQ_F16; // FMLA Hd,Hn,Vm.H[lane]
+ add_input_reg(inputs, il, instr.operands[0]);
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_input_lane(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMLA_ASISDELEM_R_SD:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && instr.operands[2].arrSpec == ARRSPEC_1DOUBLE && instr.operands[2].laneUsed)
+ // float64_t vfmad_laneq_f64(float64_t a, float64_t b, float64x2_t v, const int lane)
+ // argprep: a -> Dd; b -> Dn; v -> Vm.2D; lane -> <lane>
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VFMAD_LANEQ_F64; // FMLA Dd,Dn,Vm.D[lane]
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // float32_t vfmas_laneq_f32(float32_t a, float32_t b, float32x4_t v, const int lane)
+ // argprep: a -> Sd; b -> Sn; v -> Vm.4S; lane -> <lane>
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VFMAS_LANEQ_F32; // FMLA Sd,Sn,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -16067,11 +18680,11 @@ bool NeonGetLowLevelILForInstruction(
case ENC_FMLSL2_ASIMDELEM_LH:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VFMLSL_LANE_HIGH_F16; // FMLSL2 Vd.2S,Vn.2H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VFMLSLQ_LANE_HIGH_F16; // FMLSL2 Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VFMLSL_LANEQ_HIGH_F16; // FMLSL2 Vd.2S,Vn.2H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VFMLSLQ_LANEQ_HIGH_F16; // FMLSL2 Vd.4S,Vn.4H,Vm.H[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -16082,7 +18695,7 @@ bool NeonGetLowLevelILForInstruction(
case ENC_FMLSL2_ASIMDSAME_F:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VFMLSL_HIGH_F16; // FMLSL2 Vd.2S,Vn.2H,Vm.2H
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VFMLSLQ_HIGH_F16; // FMLSL2 Vd.4S,Vn.4H,Vm.4H
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -16092,11 +18705,11 @@ bool NeonGetLowLevelILForInstruction(
case ENC_FMLSL_ASIMDELEM_LH:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VFMLSL_LANE_LOW_F16; // FMLSL Vd.2S,Vn.2H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VFMLSL_LANEQ_LOW_F16; // FMLSL Vd.2S,Vn.2H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VFMLSLQ_LANE_LOW_F16; // FMLSL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VFMLSLQ_LANEQ_LOW_F16; // FMLSL Vd.4S,Vn.4H,Vm.H[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -16107,7 +18720,7 @@ bool NeonGetLowLevelILForInstruction(
case ENC_FMLSL_ASIMDSAME_F:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VFMLSL_LOW_F16; // FMLSL Vd.2S,Vn.2H,Vm.2H
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VFMLSLQ_LOW_F16; // FMLSL Vd.4S,Vn.4H,Vm.4H
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -16115,26 +18728,38 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMLS_ASIMDELEM_RH_H:
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VFMS_LANE_F32; // FMLS Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VFMSQ_LANE_F32; // FMLS Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VFMSQ_LANE_F64; // FMLS Vd.2D,Vn.2D,Vm.D[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // float16x4_t vfms_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t v, const int lane)
+ // argprep: a -> Vd.4H; b -> Vn.4H; v -> Vm.8H; lane -> <lane>
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VFMS_LANEQ_F16; // FMLS Vd.4H,Vn.4H,Vm.H[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // float16x8_t vfmsq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t v, const int lane)
+ // argprep: a -> Vd.8H; b -> Vn.8H; v -> Vm.8H; lane -> <lane>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VFMSQ_LANEQ_F16; // FMLS Vd.8H,Vn.8H,Vm.H[lane]
+ add_input_reg(inputs, il, instr.operands[0]);
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_input_lane(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMLS_ASIMDELEM_R_SD:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // float32x2_t vfms_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v, const int lane)
+ // argprep: a -> Vd.2S; b -> Vn.2S; v -> Vm.4S; lane -> <lane>
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VFMS_LANEQ_F32; // FMLS Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // float32x4_t vfmsq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v, const int lane)
+ // argprep: a -> Vd.4S; b -> Vn.4S; v -> Vm.4S; lane -> <lane>
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VFMSQ_LANEQ_F32; // FMLS Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_1DOUBLE && instr.operands[2].laneUsed)
+ // float64x2_t vfmsq_laneq_f64(float64x2_t a, float64x2_t b, float64x2_t v, const int lane)
+ // argprep: a -> Vd.2D; b -> Vn.2D; v -> Vm.2D; lane -> <lane>
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VFMSQ_LANEQ_F64; // FMLS Vd.2D,Vn.2D,Vm.D[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VFMS_LANE_F16; // FMLS Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VFMSQ_LANE_F16; // FMLS Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VFMS_LANEQ_F16; // FMLS Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VFMSQ_LANEQ_F16; // FMLS Vd.8H,Vn.8H,Vm.H[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -16142,33 +18767,90 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMLS_ASIMDSAMEFP16_ONLY:
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // float16x4_t vfms_f16(float16x4_t a, float16x4_t b, float16x4_t c)
+ // argprep: a -> Vd.4H; b -> Vn.4H; c -> Vm.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VFMS_F16; // FMLS Vd.4H,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].laneUsed)
+ // float16x4_t vfms_n_f16(float16x4_t a, float16x4_t b, float16_t n)
+ // argprep: a -> Vd.4H; b -> Vn.4H; n -> <n>
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VFMS_N_F16; // FMLS Vd.4H,Vn.4H,Vm.H[0]
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // float16x8_t vfmsq_f16(float16x8_t a, float16x8_t b, float16x8_t c)
+ // argprep: a -> Vd.8H; b -> Vn.8H; c -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VFMSQ_F16; // FMLS Vd.8H,Vn.8H,Vm.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].laneUsed)
+ // float16x8_t vfmsq_n_f16(float16x8_t a, float16x8_t b, float16_t n)
+ // argprep: a -> Vd.8H; b -> Vn.8H; n -> <n>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VFMSQ_N_F16; // FMLS Vd.8H,Vn.8H,Vm.H[0]
+ add_input_reg(inputs, il, instr.operands[0]);
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_lane(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMLS_ASIMDSAME_ONLY:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // float32x2_t vfms_f32(float32x2_t a, float32x2_t b, float32x2_t c)
+ // argprep: a -> Vd.2S; b -> Vn.2S; c -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VFMS_F32; // FMLS Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].laneUsed)
+ // float32x2_t vfms_n_f32(float32x2_t a, float32x2_t b, float32_t n)
+ // argprep: a -> Vd.2S; b -> Vn.2S; n -> <n>
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VFMS_N_F32; // FMLS Vd.2S,Vn.2S,Vm.S[0]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // float32x4_t vfmsq_f32(float32x4_t a, float32x4_t b, float32x4_t c)
+ // argprep: a -> Vd.4S; b -> Vn.4S; c -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VFMSQ_F32; // FMLS Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // float64x2_t vfmsq_f64(float64x2_t a, float64x2_t b, float64x2_t c)
+ // argprep: a -> Vd.2D; b -> Vn.2D; c -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VFMSQ_F64; // FMLS Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VFMS_N_F32; // FMLS Vd.2S,Vn.2S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].laneUsed)
+ // float32x4_t vfmsq_n_f32(float32x4_t a, float32x4_t b, float32_t n)
+ // argprep: a -> Vd.4S; b -> Vn.4S; n -> <n>
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VFMSQ_N_F32; // FMLS Vd.4S,Vn.4S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].laneUsed)
+ // float64x2_t vfmsq_n_f64(float64x2_t a, float64x2_t b, float64_t n)
+ // argprep: a -> Vd.2D; b -> Vn.2D; n -> <n>
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VFMSQ_N_F64; // FMLS Vd.2D,Vn.2D,Vm.D[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VFMS_F16; // FMLS Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VFMSQ_F16; // FMLS Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VFMS_N_F16; // FMLS Vd.4H,Vn.4H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VFMSQ_N_F16; // FMLS Vd.8H,Vn.8H,Vm.H[0]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
- add_input_reg(inputs, il, instr.operands[2]);
+ add_input_lane(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMLS_ASISDELEM_RH_H:
- intrin_id = ARM64_INTRIN_VFMS_LANE_F64; // FMLS Dd,Dn,Vm.D[lane]
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // float16_t vfmsh_laneq_f16(float16_t a, float16_t b, float16x8_t v, const int lane)
+ // argprep: a -> Hd; b -> Hn; v -> Vm.8H; lane -> <lane>
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VFMSH_LANEQ_F16; // FMLS Hd,Hn,Vm.H[lane]
+ add_input_reg(inputs, il, instr.operands[0]);
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_input_lane(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMLS_ASISDELEM_R_SD:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && instr.operands[2].arrSpec == ARRSPEC_1DOUBLE && instr.operands[2].laneUsed)
+ // float64_t vfmsd_laneq_f64(float64_t a, float64_t b, float64x2_t v, const int lane)
+ // argprep: a -> Dd; b -> Dn; v -> Vm.2D; lane -> <lane>
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VFMSD_LANEQ_F64; // FMLS Dd,Dn,Vm.D[lane]
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // float32_t vfmss_laneq_f32(float32_t a, float32_t b, float32x4_t v, const int lane)
+ // argprep: a -> Sd; b -> Sn; v -> Vm.4S; lane -> <lane>
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VFMSS_LANEQ_F32; // FMLS Sd,Sn,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -16182,6 +18864,13 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FMSUB_S_FLOATDP3:
+ intrin_id = ARM64_INTRIN_VFMS_F64; // FMSUB Sd,Sn,Sm,Sa
+ add_input_reg(inputs, il, instr.operands[3]);
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FMSUB_H_FLOATDP3:
intrin_id = ARM64_INTRIN_VFMSH_F16; // FMSUB Hd,Hn,Hm,Ha
add_input_reg(inputs, il, instr.operands[3]);
@@ -16190,59 +18879,136 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMULX_ASIMDELEM_RH_H:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VMULX_LANE_F32; // FMULX Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VMULXQ_LANE_F32; // FMULX Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VMULXQ_LANE_F64; // FMULX Vd.2D,Vn.2D,Vm.D[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // float16x4_t vmulx_laneq_f16(float16x4_t a, float16x8_t v, const int lane)
+ // argprep: a -> Vn.4H; v -> Vm.8H; lane -> <lane>
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VMULX_LANEQ_F16; // FMULX Vd.4H,Vn.4H,Vm.H[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // float16x8_t vmulxq_laneq_f16(float16x8_t a, float16x8_t v, const int lane)
+ // argprep: a -> Vn.8H; v -> Vm.8H; lane -> <lane>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VMULXQ_LANEQ_F16; // FMULX Vd.8H,Vn.8H,Vm.H[lane]
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_input_lane(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMULX_ASIMDELEM_R_SD:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // float32x2_t vmulx_laneq_f32(float32x2_t a, float32x4_t v, const int lane)
+ // argprep: a -> Vn.2S; v -> Vm.4S; lane -> <lane>
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VMULX_LANEQ_F32; // FMULX Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // float32x4_t vmulxq_laneq_f32(float32x4_t a, float32x4_t v, const int lane)
+ // argprep: a -> Vn.4S; v -> Vm.4S; lane -> <lane>
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VMULXQ_LANEQ_F32; // FMULX Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_1DOUBLE && instr.operands[2].laneUsed)
+ // float64x2_t vmulxq_laneq_f64(float64x2_t a, float64x2_t v, const int lane)
+ // argprep: a -> Vn.2D; v -> Vm.2D; lane -> <lane>
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VMULXQ_LANEQ_F64; // FMULX Vd.2D,Vn.2D,Vm.D[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VMULX_LANE_F16; // FMULX Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VMULXQ_LANE_F16; // FMULX Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VMULX_LANEQ_F16; // FMULX Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VMULXQ_LANEQ_F16; // FMULX Vd.8H,Vn.8H,Vm.H[lane]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_input_lane(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMULX_ASIMDSAMEFP16_ONLY:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VMULX_F32; // FMULX Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VMULXQ_F32; // FMULX Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VMULXQ_F64; // FMULX Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // float16x4_t vmulx_f16(float16x4_t a, float16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VMULX_F16; // FMULX Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VMULXQ_F16; // FMULX Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // float16x4_t vmulx_n_f16(float16x4_t a, float16_t n)
+ // argprep: a -> Vn.4H; n -> Vm.H[0]
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VMULX_N_F16; // FMULX Vd.4H,Vn.4H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // float16x8_t vmulxq_f16(float16x8_t a, float16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VMULXQ_F16; // FMULX Vd.8H,Vn.8H,Vm.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // float16x8_t vmulxq_n_f16(float16x8_t a, float16_t n)
+ // argprep: a -> Vn.8H; n -> Vm.H[0]
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VMULXQ_N_F16; // FMULX Vd.8H,Vn.8H,Vm.H[0]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
+ add_input_lane(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMULX_ASIMDSAME_ONLY:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // float32x2_t vmulx_f32(float32x2_t a, float32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VMULX_F32; // FMULX Vd.2S,Vn.2S,Vm.2S
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // float32x4_t vmulxq_f32(float32x4_t a, float32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VMULXQ_F32; // FMULX Vd.4S,Vn.4S,Vm.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // float64x2_t vmulxq_f64(float64x2_t a, float64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VMULXQ_F64; // FMULX Vd.2D,Vn.2D,Vm.2D
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMULX_ASISDELEM_RH_H:
- intrin_id = ARM64_INTRIN_VMULX_LANE_F64; // FMULX Dd,Dn,Vm.D[lane]
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // float16_t vmulxh_laneq_f16(float16_t a, float16x8_t v, const int lane)
+ // argprep: a -> Hn; v -> Vm.8H; lane -> <lane>
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VMULXH_LANEQ_F16; // FMULX Hd,Hn,Vm.H[lane]
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_input_lane(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMULX_ASISDELEM_R_SD:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && instr.operands[2].arrSpec == ARRSPEC_1DOUBLE && instr.operands[2].laneUsed)
+ // float64_t vmulxd_laneq_f64(float64_t a, float64x2_t v, const int lane)
+ // argprep: a -> Dn; v -> Vm.2D; lane -> <lane>
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VMULXD_LANEQ_F64; // FMULX Dd,Dn,Vm.D[lane]
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // float32_t vmulxs_laneq_f32(float32_t a, float32x4_t v, const int lane)
+ // argprep: a -> Sn; v -> Vm.4S; lane -> <lane>
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VMULXS_LANEQ_F32; // FMULX Sd,Sn,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_input_lane(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMULX_ASISDSAMEFP16_ONLY:
- intrin_id = ARM64_INTRIN_VMULX_F64; // FMULX Dd,Dn,Dm
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].reg[0] >= REG_H0 && instr.operands[2].reg[0] <= REG_H31))
+ // float16_t vmulxh_f16(float16_t a, float16_t b)
+ // argprep: a -> Hn; b -> Hm
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VMULXH_F16; // FMULX Hd,Hn,Hm
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMULX_ASISDSAME_ONLY:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].reg[0] >= REG_D0 && instr.operands[2].reg[0] <= REG_D31))
+ // float64_t vmulxd_f64(float64_t a, float64_t b)
+ // argprep: a -> Dn; b -> Dm
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VMULXD_F64; // FMULX Dd,Dn,Dm
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].reg[0] >= REG_S0 && instr.operands[2].reg[0] <= REG_S31))
+ // float32_t vmulxs_f32(float32_t a, float32_t b)
+ // argprep: a -> Sn; b -> Sm
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VMULXS_F32; // FMULX Sd,Sn,Sm
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -16260,58 +19026,175 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMUL_ASIMDELEM_RH_H:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES && instr.operands[2].laneUsed)
+ // float16x4_t vmul_lane_f16(float16x4_t a, float16x4_t v, const int lane)
+ // argprep: a -> Vn.4H; v -> Vm.4H; lane -> <lane>
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VMUL_LANE_F16; // FMUL Vd.4H,Vn.4H,Vm.H[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES && instr.operands[2].laneUsed)
+ // float16x4_t vmul_laneq_f16(float16x4_t a, float16x8_t v, const int lane)
+ // argprep: a -> Vn.4H; v -> Vm.8H; lane -> <lane>
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VMUL_LANEQ_F16; // FMUL Vd.4H,Vn.4H,Vm.H[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES && instr.operands[2].laneUsed)
+ // float16x8_t vmulq_lane_f16(float16x8_t a, float16x4_t v, const int lane)
+ // argprep: a -> Vn.8H; v -> Vm.4H; lane -> <lane>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VMULQ_LANE_F16; // FMUL Vd.8H,Vn.8H,Vm.H[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES && instr.operands[2].laneUsed)
+ // float16x8_t vmulq_laneq_f16(float16x8_t a, float16x8_t v, const int lane)
+ // argprep: a -> Vn.8H; v -> Vm.8H; lane -> <lane>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VMULQ_LANEQ_F16; // FMUL Vd.8H,Vn.8H,Vm.H[lane]
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_input_lane(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMUL_ASIMDELEM_R_SD:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].laneUsed)
+ // float32x2_t vmul_lane_f32(float32x2_t a, float32x2_t v, const int lane)
+ // argprep: a -> Vn.2S; v -> Vm.2S; lane -> <lane>
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VMUL_LANE_F32; // FMUL Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].laneUsed)
+ // float32x2_t vmul_laneq_f32(float32x2_t a, float32x4_t v, const int lane)
+ // argprep: a -> Vn.2S; v -> Vm.4S; lane -> <lane>
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VMUL_LANEQ_F32; // FMUL Vd.2S,Vn.2S,Vm.S[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].laneUsed)
+ // float32x4_t vmulq_lane_f32(float32x4_t a, float32x2_t v, const int lane)
+ // argprep: a -> Vn.4S; v -> Vm.2S; lane -> <lane>
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VMULQ_LANE_F32; // FMUL Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_1DOUBLE && instr.operands[2].laneUsed)
+ // float64x2_t vmulq_lane_f64(float64x2_t a, float64x1_t v, const int lane)
+ // argprep: a -> Vn.2D; v -> Vm.1D; lane -> <lane>
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VMULQ_LANE_F64; // FMUL Vd.2D,Vn.2D,Vm.D[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VMUL_LANEQ_F32; // FMUL Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].laneUsed)
+ // float32x4_t vmulq_laneq_f32(float32x4_t a, float32x4_t v, const int lane)
+ // argprep: a -> Vn.4S; v -> Vm.4S; lane -> <lane>
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VMULQ_LANEQ_F32; // FMUL Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].laneUsed)
+ // float64x2_t vmulq_laneq_f64(float64x2_t a, float64x2_t v, const int lane)
+ // argprep: a -> Vn.2D; v -> Vm.2D; lane -> <lane>
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VMULQ_LANEQ_F64; // FMUL Vd.2D,Vn.2D,Vm.D[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VMUL_LANE_F16; // FMUL Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VMULQ_LANE_F16; // FMUL Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VMUL_LANEQ_F16; // FMUL Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VMULQ_LANEQ_F16; // FMUL Vd.8H,Vn.8H,Vm.H[lane]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_input_lane(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMUL_ASIMDSAMEFP16_ONLY:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // float16x4_t vmul_f16(float16x4_t a, float16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VMUL_F16; // FMUL Vd.4H,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].laneUsed)
+ // float16x4_t vmul_n_f16(float16x4_t a, float16_t n)
+ // argprep: a -> Vn.4H; n -> <n>
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VMUL_N_F16; // FMUL Vd.4H,Vn.4H,Vm.H[0]
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // float16x8_t vmulq_f16(float16x8_t a, float16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VMULQ_F16; // FMUL Vd.8H,Vn.8H,Vm.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].laneUsed)
+ // float16x8_t vmulq_n_f16(float16x8_t a, float16_t n)
+ // argprep: a -> Vn.8H; n -> <n>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VMULQ_N_F16; // FMUL Vd.8H,Vn.8H,Vm.H[0]
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_lane(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMUL_ASIMDSAME_ONLY:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // float32x2_t vmul_f32(float32x2_t a, float32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VMUL_F32; // FMUL Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // float32x2_t vmul_n_f32(float32x2_t a, float32_t b)
+ // argprep: a -> Vn.2S; b -> Vm.S[0]
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VMUL_N_F32; // FMUL Vd.2S,Vn.2S,Vm.S[0]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // float32x4_t vmulq_f32(float32x4_t a, float32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VMULQ_F32; // FMUL Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // float64x2_t vmulq_f64(float64x2_t a, float64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VMULQ_F64; // FMUL Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VMUL_N_F32; // FMUL Vd.2S,Vn.2S,Vm.S[0]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // float32x4_t vmulq_n_f32(float32x4_t a, float32_t b)
+ // argprep: a -> Vn.4S; b -> Vm.S[0]
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VMULQ_N_F32; // FMUL Vd.4S,Vn.4S,Vm.S[0]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_1DOUBLE && instr.operands[2].laneUsed)
+ // float64x2_t vmulq_n_f64(float64x2_t a, float64_t b)
+ // argprep: a -> Vn.2D; b -> Vm.D[0]
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VMULQ_N_F64; // FMUL Vd.2D,Vn.2D,Vm.D[0]
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VMUL_F16; // FMUL Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VMULQ_F16; // FMUL Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VMUL_N_F16; // FMUL Vd.4H,Vn.4H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VMULQ_N_F16; // FMUL Vd.8H,Vn.8H,Vm.H[0]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
+ add_input_lane(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FMUL_ASISDELEM_RH_H:
- intrin_id = ARM64_INTRIN_VMUL_LANE_F64; // FMUL Dd,Dn,Vm.D[lane]
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && instr.operands[2].arrSpec == ARRSPEC_1DOUBLE && instr.operands[2].laneUsed)
+ // float64_t vmuld_lane_f64(float64_t a, float64x1_t v, const int lane)
+ // argprep: a -> Dn; v -> Vm.1D; lane -> <lane>
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VMULD_LANE_F64; // FMUL Dd,Dn,Vm.S[lane]
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && instr.operands[2].arrSpec == ARRSPEC_4HALVES && instr.operands[2].laneUsed)
+ // float16_t vmulh_lane_f16(float16_t a, float16x4_t v, const int lane)
+ // argprep: a -> Hn; v -> Vm.4H; lane -> <lane>
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VMULH_LANE_F16; // FMUL Hd,Hn,Vm.H[lane]
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && instr.operands[2].arrSpec == ARRSPEC_8HALVES && instr.operands[2].laneUsed)
+ // float16_t vmulh_laneq_f16(float16_t a, float16x8_t v, const int lane)
+ // argprep: a -> Hn; v -> Vm.8H; lane -> <lane>
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VMULH_LANEQ_F16; // FMUL Hd,Hn,Vm.H[lane]
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_input_lane(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FMUL_ASISDELEM_R_SD:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && instr.operands[2].arrSpec == ARRSPEC_1DOUBLE && instr.operands[2].laneUsed)
+ // float64x1_t vmul_lane_f64(float64x1_t a, float64x1_t v, const int lane)
+ // argprep: a -> Dn; v -> Vm.1D; lane -> <lane>
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VMUL_LANE_F64; // FMUL Dd,Dn,Vm.D[lane]
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].laneUsed)
+ // float64_t vmuld_laneq_f64(float64_t a, float64x2_t v, const int lane)
+ // argprep: a -> Dn; v -> Vm.2D; lane -> <lane>
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VMULD_LANEQ_F64; // FMUL Dd,Dn,Vm.D[lane]
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && instr.operands[2].arrSpec == ARRSPEC_1DOUBLE && instr.operands[2].laneUsed)
+ // float64x1_t vmul_n_f64(float64x1_t a, float64_t b)
+ // argprep: a -> Dn; b -> Vm.D[0]
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VMUL_N_F64; // FMUL Dd,Dn,Vm.D[0]
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].laneUsed)
+ // float32_t vmuls_lane_f32(float32_t a, float32x2_t v, const int lane)
+ // argprep: a -> Sn; v -> Vm.2S; lane -> <lane>
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VMULS_LANE_F32; // FMUL Sd,Sn,Vm.S[lane]
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && instr.operands[2].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].laneUsed)
+ // float32_t vmuls_laneq_f32(float32_t a, float32x4_t v, const int lane)
+ // argprep: a -> Sn; v -> Vm.4S; lane -> <lane>
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VMULS_LANEQ_F32; // FMUL Sd,Sn,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_input_lane(inputs, il, instr.operands[2]);
@@ -16322,35 +19205,42 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FNEG_S_FLOATDP1:
+ intrin_id = ARM64_INTRIN_VNEG_F64; // FNEG Sd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FNEG_H_FLOATDP1:
intrin_id = ARM64_INTRIN_VNEGH_F16; // FNEG Hd,Hn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FNEG_ASIMDMISC_R:
case ENC_FNEG_ASIMDMISCFP16_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VNEG_F32; // FNEG Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VNEGQ_F32; // FNEG Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VNEGQ_F64; // FNEG Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VNEG_F16; // FNEG Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VNEGQ_F16; // FNEG Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRECPE_ASIMDMISC_R:
case ENC_FRECPE_ASIMDMISCFP16_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRECPE_F32; // FRECPE Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRECPEQ_F32; // FRECPE Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRECPEQ_F64; // FRECPE Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRECPE_F16; // FRECPE Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRECPEQ_F16; // FRECPE Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -16360,16 +19250,17 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRECPS_ASIMDSAME_ONLY:
case ENC_FRECPS_ASIMDSAMEFP16_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRECPS_F32; // FRECPS Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRECPSQ_F32; // FRECPS Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRECPSQ_F64; // FRECPS Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRECPS_F16; // FRECPS Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRECPSQ_F16; // FRECPS Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -16391,12 +19282,20 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRINT32X_S_FLOATDP1:
+ // float32x1_t vrnd32x_f64(float32x1_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VRND32X_F64; // FRINT32X Sd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FRINT32X_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRND32X_F32; // FRINT32X Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRND32XQ_F32; // FRINT32X Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRND32XQ_F64; // FRINT32X Vd.2D,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -16406,12 +19305,20 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRINT32Z_S_FLOATDP1:
+ // float32x1_t vrnd32z_f32(float32x1_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VRND32Z_F32; // FRINT32Z Sd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FRINT32Z_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRND32Z_F32; // FRINT32Z Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRND32ZQ_F32; // FRINT32Z Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRND32ZQ_F64; // FRINT32Z Vd.2D,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -16421,12 +19328,20 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRINT64X_S_FLOATDP1:
+ // float32x1_t vrnd64x_f32(float32x1_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VRND64X_F32; // FRINT64X Sd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FRINT64X_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRND64X_F32; // FRINT64X Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRND64XQ_F32; // FRINT64X Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRND64XQ_F64; // FRINT64X Vd.2D,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -16436,12 +19351,20 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRINT64Z_S_FLOATDP1:
+ // float64x1_t vrnd64z_f32(float32x1_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VRND64Z_F32; // FRINT64Z Sd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FRINT64Z_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRND64Z_F32; // FRINT64Z Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRND64ZQ_F32; // FRINT64Z Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRND64ZQ_F64; // FRINT64Z Vd.2D,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -16456,16 +19379,25 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRINTA_S_FLOATDP1:
+ // float32x1_t vrnda_f32(float32x1_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VRNDA_F32; // FRINTA Sd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FRINTA_ASIMDMISC_R:
case ENC_FRINTA_ASIMDMISCFP16_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRNDA_F32; // FRINTA Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRNDAQ_F32; // FRINTA Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRNDAQ_F64; // FRINTA Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRNDA_F16; // FRINTA Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRNDAQ_F16; // FRINTA Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -16480,16 +19412,25 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRINTI_S_FLOATDP1:
+ // float32x1_t vrndi_f32(float32x1_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VRNDI_F32; // FRINTI Sd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FRINTI_ASIMDMISC_R:
case ENC_FRINTI_ASIMDMISCFP16_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRNDI_F32; // FRINTI Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRNDIQ_F32; // FRINTI Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRNDIQ_F64; // FRINTI Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRNDI_F16; // FRINTI Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRNDIQ_F16; // FRINTI Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -16504,16 +19445,25 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRINTM_S_FLOATDP1:
+ // float32x1_t vrndm_f32(float32x1_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VRNDM_F32; // FRINTM Sd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FRINTM_ASIMDMISC_R:
case ENC_FRINTM_ASIMDMISCFP16_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRNDM_F32; // FRINTM Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRNDMQ_F32; // FRINTM Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRNDMQ_F64; // FRINTM Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRNDM_F16; // FRINTM Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRNDMQ_F16; // FRINTM Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -16533,16 +19483,17 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRINTN_ASIMDMISC_R:
case ENC_FRINTN_ASIMDMISCFP16_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRNDN_F32; // FRINTN Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRNDNQ_F32; // FRINTN Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRNDNQ_F64; // FRINTN Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRNDN_F16; // FRINTN Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRNDNQ_F16; // FRINTN Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -16557,16 +19508,25 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRINTP_S_FLOATDP1:
+ // float32x1_t vrndp_f32(float32x1_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VRNDP_F32; // FRINTP Sd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FRINTP_ASIMDMISC_R:
case ENC_FRINTP_ASIMDMISCFP16_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRNDP_F32; // FRINTP Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRNDPQ_F32; // FRINTP Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRNDPQ_F64; // FRINTP Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRNDP_F16; // FRINTP Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRNDPQ_F16; // FRINTP Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -16581,16 +19541,25 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRINTX_S_FLOATDP1:
+ // float32x1_t vrndx_f32(float32x1_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VRNDX_F32; // FRINTX Sd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FRINTX_ASIMDMISC_R:
case ENC_FRINTX_ASIMDMISCFP16_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRNDX_F32; // FRINTX Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRNDXQ_F32; // FRINTX Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRNDXQ_F64; // FRINTX Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRNDX_F16; // FRINTX Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRNDXQ_F16; // FRINTX Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -16600,35 +19569,42 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRINTZ_S_FLOATDP1:
+ intrin_id = ARM64_INTRIN_VRND_F64; // FRINTZ Dd,Dn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FRINTZ_H_FLOATDP1:
intrin_id = ARM64_INTRIN_VRNDH_F16; // FRINTZ Hd,Hn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRINTZ_ASIMDMISC_R:
case ENC_FRINTZ_ASIMDMISCFP16_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRND_F32; // FRINTZ Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRNDQ_F32; // FRINTZ Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRNDQ_F64; // FRINTZ Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRND_F16; // FRINTZ Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRNDQ_F16; // FRINTZ Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRSQRTE_ASIMDMISC_R:
case ENC_FRSQRTE_ASIMDMISCFP16_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRSQRTE_F32; // FRSQRTE Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRSQRTEQ_F32; // FRSQRTE Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRSQRTEQ_F64; // FRSQRTE Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRSQRTE_F16; // FRSQRTE Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRSQRTEQ_F16; // FRSQRTE Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -16638,22 +19614,43 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FRSQRTE_ASISDMISC_R:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // float64_t vrsqrted_f64(float64_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VRSQRTED_F64; // FRSQRTE Dd,Dn
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // float32_t vrsqrtes_f32(float32_t a)
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VRSQRTES_F32; // FRSQRTE Sd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FRSQRTS_ASIMDSAME_ONLY:
case ENC_FRSQRTS_ASIMDSAMEFP16_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRSQRTS_F32; // FRSQRTS Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRSQRTSQ_F32; // FRSQRTS Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRSQRTSQ_F64; // FRSQRTS Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRSQRTS_F16; // FRSQRTS Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRSQRTSQ_F16; // FRSQRTS Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_FRSQRTS_ASISDSAMEFP16_ONLY:
+ intrin_id = ARM64_INTRIN_VRSQRTSH_F16; // FRSQRTS Hd,Hn,Hm
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_FRSQRTS_ASISDSAME_ONLY:
intrin_id = ARM64_INTRIN_VRSQRTS_F64; // FRSQRTS Dd,Dn,Dm
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -16664,21 +19661,27 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FSQRT_S_FLOATDP1:
+ intrin_id = ARM64_INTRIN_VSQRT_F32; // FSQRT Sd,Sn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
case ENC_FSQRT_H_FLOATDP1:
intrin_id = ARM64_INTRIN_VSQRTH_F16; // FSQRT Hd,Hn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FSQRT_ASIMDMISC_R:
case ENC_FSQRT_ASIMDMISCFP16_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VSQRT_F32; // FSQRT Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSQRTQ_F32; // FSQRT Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSQRTQ_F64; // FSQRT Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VSQRT_F16; // FSQRT Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSQRTQ_F16; // FSQRT Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -16695,65 +19698,76 @@ bool NeonGetLowLevelILForInstruction(
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_FSUB_ASIMDSAME_ONLY:
case ENC_FSUB_ASIMDSAMEFP16_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VSUB_F32; // FSUB Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSUBQ_F32; // FSUB Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSUBQ_F64; // FSUB Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VSUB_F16; // FSUB Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSUBQ_F16; // FSUB Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_INS_ASIMDINS_IR_R:
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VCREATE_S8; // INS Vd.D[0],Xn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VCREATE_S16; // INS Vd.D[0],Xn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VCREATE_S32; // INS Vd.D[0],Xn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VCREATE_S64; // INS Vd.D[0],Xn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
+ case ENC_MOV_INS_ASIMDINS_IR_R:
+ if (instr.operands[0].arrSpec == ARRSPEC_1DOUBLE && (instr.operands[1].reg[0] >= REG_X0 && instr.operands[1].reg[0] <= REG_SP) && instr.operands[0].laneUsed)
+ // uint8x8_t vcreate_u8(uint64_t a)
+ // argprep: a -> Xn
+ // results: Vd.8B -> result
intrin_id = ARM64_INTRIN_VCREATE_U8; // INS Vd.D[0],Xn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VCREATE_U16; // INS Vd.D[0],Xn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VCREATE_U32; // INS Vd.D[0],Xn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VCREATE_U64; // INS Vd.D[0],Xn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VCREATE_P64; // INS Vd.D[0],Xn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VCREATE_F16; // INS Vd.D[0],Xn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VCREATE_F32; // INS Vd.D[0],Xn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VCREATE_P8; // INS Vd.D[0],Xn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VCREATE_P16; // INS Vd.D[0],Xn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VCREATE_F64; // INS Vd.D[0],Xn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VDUP_N_S64; // INS Vd.D[0],rn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
+ else if (instr.operands[0].arrSpec == ARRSPEC_1DOUBLE && instr.operands[0].laneUsed)
+ // uint64x1_t vdup_n_u64(uint64_t value)
+ // argprep: value -> Xn
+ // results: Vd.1D -> result
intrin_id = ARM64_INTRIN_VDUP_N_U64; // INS Vd.D[0],rn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VDUP_N_P64; // INS Vd.D[0],rn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VDUP_N_F64; // INS Vd.D[0],rn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VCREATE_BF16; // INS Vd.D[0],Xn
- if (instr.operands[1].arrSpec == ARRSPEC_1HALF)
- intrin_id = ARM64_INTRIN_VSET_LANE_BF16; // INS Vd.H[lane],Vn.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_1HALF)
+ else if (instr.operands[0].arrSpec == ARRSPEC_1HALF && instr.operands[1].arrSpec == ARRSPEC_1HALF && instr.operands[0].laneUsed && instr.operands[1].laneUsed)
+ // bfloat16x8_t vsetq_lane_bf16(bfloat16_t a, bfloat16x8_t v, const int lane)
+ // argprep: a -> Vn.H; v -> Vd.8H; lane -> <lane>
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VSETQ_LANE_BF16; // INS Vd.H[lane],Vn.H[0]
add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[0]);
+ add_input_lane(inputs, il, instr.operands[0]);
+ add_input_lane(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_INS_ASIMDINS_IV_V:
+ case ENC_MOV_INS_ASIMDINS_IV_V:
+ if (instr.operands[0].arrSpec == ARRSPEC_1DOUBLE && instr.operands[2].arrSpec == ARRSPEC_1DOUBLE && instr.operands[0].laneUsed && instr.operands[1].laneUsed)
+ // uint8x16_t vcombine_u8(uint8x8_t low, uint8x8_t high)
+ // argprep: low -> Vn.8B; high -> Vm.8B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VCOMBINE_U8; // INS Vd.D[1],Vm.D[0]
+ else if (instr.operands[0].arrSpec == ARRSPEC_1HALF && instr.operands[1].arrSpec == ARRSPEC_1HALF && instr.operands[0].laneUsed && instr.operands[1].laneUsed)
+ // uint16x8_t vcopyq_laneq_u16(uint16x8_t a, const int lane1, uint16x8_t b, const int lane2)
+ // argprep: a -> Vd.8H; lane1 -> <lane1>; b -> Vn.8H; lane2 -> <lane2>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCOPYQ_LANEQ_U16; // INS Vd.H[lane1],Vn.H[lane2]
+ else if (instr.operands[0].arrSpec == ARRSPEC_1SINGLE && instr.operands[1].arrSpec == ARRSPEC_1SINGLE && instr.operands[0].laneUsed && instr.operands[1].laneUsed)
+ // uint32x4_t vcopyq_laneq_u32(uint32x4_t a, const int lane1, uint32x4_t b, const int lane2)
+ // argprep: a -> Vd.4S; lane1 -> <lane1>; b -> Vn.4S; lane2 -> <lane2>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VCOPYQ_LANEQ_U32; // INS Vd.S[lane1],Vn.S[lane2]
+ else if (instr.operands[0].arrSpec == ARRSPEC_1BYTE && instr.operands[1].arrSpec == ARRSPEC_1BYTE && instr.operands[0].laneUsed && instr.operands[1].laneUsed)
+ // uint8x16_t vcopyq_laneq_u8(uint8x16_t a, const int lane1, uint8x16_t b, const int lane2)
+ // argprep: a -> Vd.16B; lane1 -> <lane1>; b -> Vn.16B; lane2 -> <lane2>
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VCOPYQ_LANEQ_U8; // INS Vd.B[lane1],Vn.B[lane2]
+ else if (instr.operands[0].arrSpec == ARRSPEC_1DOUBLE && instr.operands[1].arrSpec == ARRSPEC_1DOUBLE && instr.operands[0].laneUsed && instr.operands[1].laneUsed)
+ // uint64x2_t vcopyq_laneq_u64(uint64x2_t a, const int lane1, uint64x2_t b, const int lane2)
+ // argprep: a -> Vd.2D; lane1 -> <lane1>; b -> Vn.2D; lane2 -> <lane2>
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VCOPYQ_LANEQ_U64; // INS Vd.D[lane1],Vn.D[lane2]
+ add_input_reg(inputs, il, instr.operands[0]);
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_lane(inputs, il, instr.operands[0]);
+ add_input_lane(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_LDR_Q_LOADLIT:
@@ -16784,35 +19798,35 @@ bool NeonGetLowLevelILForInstruction(
case ENC_MLA_ASIMDELEM_R:
if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLA_LANE_S16; // MLA Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLAQ_LANE_S16; // MLA Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLA_LANE_S32; // MLA Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAQ_LANE_S32; // MLA Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLA_LANE_U16; // MLA Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLAQ_LANE_U16; // MLA Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLA_LANE_U32; // MLA Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAQ_LANE_U32; // MLA Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLA_LANEQ_S16; // MLA Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLAQ_LANEQ_S16; // MLA Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLA_LANEQ_S32; // MLA Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAQ_LANEQ_S32; // MLA Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLA_LANEQ_U16; // MLA Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLAQ_LANEQ_U16; // MLA Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLA_LANEQ_U32; // MLA Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAQ_LANEQ_U32; // MLA Vd.4S,Vn.4S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -16823,43 +19837,43 @@ bool NeonGetLowLevelILForInstruction(
case ENC_MLA_ASIMDSAME_ONLY:
if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMLA_S8; // MLA Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMLAQ_S8; // MLA Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLA_S16; // MLA Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLAQ_S16; // MLA Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLA_S32; // MLA Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAQ_S32; // MLA Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMLA_U8; // MLA Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMLAQ_U8; // MLA Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLA_U16; // MLA Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLAQ_U16; // MLA Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLA_U32; // MLA Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAQ_U32; // MLA Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLA_N_S16; // MLA Vd.4H,Vn.4H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLAQ_N_S16; // MLA Vd.8H,Vn.8H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLA_N_S32; // MLA Vd.2S,Vn.2S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAQ_N_S32; // MLA Vd.4S,Vn.4S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLA_N_U16; // MLA Vd.4H,Vn.4H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLAQ_N_U16; // MLA Vd.8H,Vn.8H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLA_N_U32; // MLA Vd.2S,Vn.2S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAQ_N_U32; // MLA Vd.4S,Vn.4S,Vm.S[0]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -16869,35 +19883,35 @@ bool NeonGetLowLevelILForInstruction(
case ENC_MLS_ASIMDELEM_R:
if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLS_LANE_S16; // MLS Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLSQ_LANE_S16; // MLS Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLS_LANE_S32; // MLS Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSQ_LANE_S32; // MLS Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLS_LANE_U16; // MLS Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLSQ_LANE_U16; // MLS Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLS_LANE_U32; // MLS Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSQ_LANE_U32; // MLS Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLS_LANEQ_S16; // MLS Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLSQ_LANEQ_S16; // MLS Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLS_LANEQ_S32; // MLS Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSQ_LANEQ_S32; // MLS Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLS_LANEQ_U16; // MLS Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLSQ_LANEQ_U16; // MLS Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLS_LANEQ_U32; // MLS Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSQ_LANEQ_U32; // MLS Vd.4S,Vn.4S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -16908,149 +19922,108 @@ bool NeonGetLowLevelILForInstruction(
case ENC_MLS_ASIMDSAME_ONLY:
if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMLS_S8; // MLS Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMLSQ_S8; // MLS Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLS_S16; // MLS Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLSQ_S16; // MLS Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLS_S32; // MLS Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSQ_S32; // MLS Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMLS_U8; // MLS Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMLSQ_U8; // MLS Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLS_U16; // MLS Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLSQ_U16; // MLS Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLS_U32; // MLS Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSQ_U32; // MLS Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLS_N_S16; // MLS Vd.4H,Vn.4H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLSQ_N_S16; // MLS Vd.8H,Vn.8H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLS_N_S32; // MLS Vd.2S,Vn.2S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSQ_N_S32; // MLS Vd.4S,Vn.4S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMLS_N_U16; // MLS Vd.4H,Vn.4H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLSQ_N_U16; // MLS Vd.8H,Vn.8H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMLS_N_U32; // MLS Vd.2S,Vn.2S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSQ_N_U32; // MLS Vd.4S,Vn.4S,Vm.S[0]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_MOV_INS_ASIMDINS_IR_R:
- if (instr.operands[1].arrSpec == ARRSPEC_1BYTE)
- intrin_id = ARM64_INTRIN_VSET_LANE_U8; // MOV Vd.B[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1HALF)
- intrin_id = ARM64_INTRIN_VSET_LANE_U16; // MOV Vd.H[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1SINGLE)
- intrin_id = ARM64_INTRIN_VSET_LANE_U32; // MOV Vd.S[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VSET_LANE_U64; // MOV Vd.D[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VSET_LANE_P64; // MOV Vd.D[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1BYTE)
- intrin_id = ARM64_INTRIN_VSET_LANE_S8; // MOV Vd.B[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1HALF)
- intrin_id = ARM64_INTRIN_VSET_LANE_S16; // MOV Vd.H[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1SINGLE)
- intrin_id = ARM64_INTRIN_VSET_LANE_S32; // MOV Vd.S[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VSET_LANE_S64; // MOV Vd.D[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1BYTE)
- intrin_id = ARM64_INTRIN_VSET_LANE_P8; // MOV Vd.B[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1HALF)
- intrin_id = ARM64_INTRIN_VSET_LANE_P16; // MOV Vd.H[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1SINGLE)
- intrin_id = ARM64_INTRIN_VSET_LANE_F32; // MOV Vd.S[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VSET_LANE_F64; // MOV Vd.D[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1BYTE)
- intrin_id = ARM64_INTRIN_VSETQ_LANE_U8; // MOV Vd.B[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1HALF)
- intrin_id = ARM64_INTRIN_VSETQ_LANE_U16; // MOV Vd.H[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1SINGLE)
- intrin_id = ARM64_INTRIN_VSETQ_LANE_U32; // MOV Vd.S[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VSETQ_LANE_U64; // MOV Vd.D[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VSETQ_LANE_P64; // MOV Vd.D[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1BYTE)
- intrin_id = ARM64_INTRIN_VSETQ_LANE_S8; // MOV Vd.B[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1HALF)
- intrin_id = ARM64_INTRIN_VSETQ_LANE_S16; // MOV Vd.H[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1SINGLE)
- intrin_id = ARM64_INTRIN_VSETQ_LANE_S32; // MOV Vd.S[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VSETQ_LANE_S64; // MOV Vd.D[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1BYTE)
- intrin_id = ARM64_INTRIN_VSETQ_LANE_P8; // MOV Vd.B[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1HALF)
- intrin_id = ARM64_INTRIN_VSETQ_LANE_P16; // MOV Vd.H[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1SINGLE)
- intrin_id = ARM64_INTRIN_VSETQ_LANE_F32; // MOV Vd.S[lane],Rn
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VSETQ_LANE_F64; // MOV Vd.D[lane],Rn
- add_input_reg(inputs, il, instr.operands[1]);
- add_input_reg(inputs, il, instr.operands[0]);
- add_input_lane(inputs, il, instr.operands[0]);
- add_output_reg(outputs, il, instr.operands[0]);
- break;
+ // case ENC_MOV_ORR_ASIMDSAME_ONLY:
+ // if (instr.operands[1].arrSpec == ARRSPEC_1HALF)
+ // intrin_id = ARM64_INTRIN_VSET_LANE_F16; // MOV Vd.H[lane],Vn.H[0]
+ // if (instr.operands[1].arrSpec == ARRSPEC_1HALF)
+ // intrin_id = ARM64_INTRIN_VSETQ_LANE_F16; // MOV Vd.H[lane],Vn.H[0]
+ // add_input_reg(inputs, il, instr.operands[1]);
+ // add_input_reg(inputs, il, instr.operands[0]);
+ // add_input_lane(inputs, il, instr.operands[0]);
+ // add_output_reg(outputs, il, instr.operands[0]);
+ // break;
case ENC_MOV_ORR_ASIMDSAME_ONLY:
- if (instr.operands[1].arrSpec == ARRSPEC_1HALF)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_1HALF && instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[0].laneUsed && instr.operands[1].laneUsed)
+ // float16x4_t vset_lane_f16(float16_t a, float16x4_t v, const int lane)
+ // argprep: a -> Vn.H; v -> Vd.4H; lane -> <lane>
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VSET_LANE_F16; // MOV Vd.H[lane],Vn.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_1HALF)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_1HALF && instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[0].laneUsed && instr.operands[1].laneUsed)
+ // float16x8_t vsetq_lane_f16(float16_t a, float16x8_t v, const int lane)
+ // argprep: a -> Vn.H; v -> Vd.8H; lane -> <lane>
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VSETQ_LANE_F16; // MOV Vd.H[lane],Vn.H[0]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[0]);
add_input_lane(inputs, il, instr.operands[0]);
+ add_input_lane(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_MUL_ASIMDELEM_R:
if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMUL_LANE_S16; // MUL Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMULQ_LANE_S16; // MUL Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMUL_LANE_S32; // MUL Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMULQ_LANE_S32; // MUL Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMUL_LANE_U16; // MUL Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMULQ_LANE_U16; // MUL Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMUL_LANE_U32; // MUL Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMULQ_LANE_U32; // MUL Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMUL_LANEQ_S16; // MUL Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMULQ_LANEQ_S16; // MUL Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMUL_LANEQ_S32; // MUL Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMULQ_LANEQ_S32; // MUL Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMUL_LANEQ_U16; // MUL Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMULQ_LANEQ_U16; // MUL Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMUL_LANEQ_U32; // MUL Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMULQ_LANEQ_U32; // MUL Vd.4S,Vn.4S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -17060,43 +20033,43 @@ bool NeonGetLowLevelILForInstruction(
case ENC_MUL_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMUL_S8; // MUL Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMULQ_S8; // MUL Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMUL_S16; // MUL Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMULQ_S16; // MUL Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMUL_S32; // MUL Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMULQ_S32; // MUL Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMUL_U8; // MUL Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMULQ_U8; // MUL Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMUL_U16; // MUL Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMULQ_U16; // MUL Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMUL_U32; // MUL Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMULQ_U32; // MUL Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMUL_N_S16; // MUL Vd.4H,Vn.4H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMULQ_N_S16; // MUL Vd.8H,Vn.8H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMUL_N_S32; // MUL Vd.2S,Vn.2S,Vm.S[0]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMULQ_N_S32; // MUL Vd.4S,Vn.4S,Vm.S[0]
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMUL_N_U16; // MUL Vd.4H,Vn.4H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMULQ_N_U16; // MUL Vd.8H,Vn.8H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMUL_N_U32; // MUL Vd.2S,Vn.2S,Vm.S[0]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMULQ_N_U32; // MUL Vd.4S,Vn.4S,Vm.S[0]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -17105,31 +20078,31 @@ bool NeonGetLowLevelILForInstruction(
case ENC_MVN_NOT_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMVN_S8; // MVN Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMVNQ_S8; // MVN Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMVN_S16; // MVN Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMVNQ_S16; // MVN Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMVN_S32; // MVN Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMVNQ_S32; // MVN Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMVN_U8; // MVN Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMVNQ_U8; // MVN Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMVN_U16; // MVN Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMVNQ_U16; // MVN Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMVN_U32; // MVN Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMVNQ_U32; // MVN Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMVN_P8; // MVN Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMVNQ_P8; // MVN Vd.16B,Vn.16B
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -17137,17 +20110,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_NEG_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VNEG_S8; // NEG Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VNEGQ_S8; // NEG Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VNEG_S16; // NEG Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VNEGQ_S16; // NEG Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VNEG_S32; // NEG Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VNEGQ_S32; // NEG Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VNEGQ_S64; // NEG Vd.2D,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -17160,35 +20133,35 @@ bool NeonGetLowLevelILForInstruction(
case ENC_ORN_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORN_S8; // ORN Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORNQ_S8; // ORN Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORN_S16; // ORN Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORNQ_S16; // ORN Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORN_S32; // ORN Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORNQ_S32; // ORN Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORN_S64; // ORN Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORNQ_S64; // ORN Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORN_U8; // ORN Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORNQ_U8; // ORN Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORN_U16; // ORN Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORNQ_U16; // ORN Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORN_U32; // ORN Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORNQ_U32; // ORN Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORN_U64; // ORN Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORNQ_U64; // ORN Vd.16B,Vn.16B,Vm.16B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -17197,35 +20170,35 @@ bool NeonGetLowLevelILForInstruction(
case ENC_ORR_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORR_S8; // ORR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORRQ_S8; // ORR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORR_S16; // ORR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORRQ_S16; // ORR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORR_S32; // ORR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORRQ_S32; // ORR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORR_S64; // ORR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORRQ_S64; // ORR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORR_U8; // ORR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORRQ_U8; // ORR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORR_U16; // ORR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORRQ_U16; // ORR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORR_U32; // ORR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORRQ_U32; // ORR Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VORR_U64; // ORR Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VORRQ_U64; // ORR Vd.16B,Vn.16B,Vm.16B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -17234,11 +20207,11 @@ bool NeonGetLowLevelILForInstruction(
case ENC_PMULL_ASIMDDIFF_L:
if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMULL_P8; // PMULL Vd.8H,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMULL_HIGH_P8; // PMULL2 Vd.8H,Vn.16B,Vm.16B
- if (instr.operands[0].arrSpec == ARRSPEC_FULL && instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
+ else if (instr.operands[0].arrSpec == ARRSPEC_FULL && instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
intrin_id = ARM64_INTRIN_VMULL_P64; // PMULL Vd.1Q,Vn.1D,Vm.1D
- if (instr.operands[0].arrSpec == ARRSPEC_FULL && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_FULL && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMULL_HIGH_P64; // PMULL2 Vd.1Q,Vn.2D,Vm.2D
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -17247,37 +20220,43 @@ bool NeonGetLowLevelILForInstruction(
case ENC_PMUL_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMUL_P8; // PMUL Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMULQ_P8; // PMUL Vd.16B,Vn.16B,Vm.16B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_RADDHN_ASIMDDIFF_N:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VRADDHN_S16; // RADDHN Vd.8B,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VRADDHN_S32; // RADDHN Vd.4H,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VRADDHN_S64; // RADDHN Vd.2S,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VRADDHN_U16; // RADDHN Vd.8B,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VRADDHN_U32; // RADDHN Vd.4H,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VRADDHN_U64; // RADDHN Vd.2S,Vn.2D,Vm.2D
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VRADDHN_HIGH_S16; // RADDHN2 Vd.16B,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VRADDHN_HIGH_S32; // RADDHN2 Vd.8H,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VRADDHN_HIGH_S64; // RADDHN2 Vd.4S,Vn.2D,Vm.2D
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint8x16_t vraddhn_high_u16(uint8x8_t r, uint16x8_t a, uint16x8_t b)
+ // argprep: r -> Vd.8B; a -> Vn.8H; b -> Vm.8H
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VRADDHN_HIGH_U16; // RADDHN2 Vd.16B,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint16x8_t vraddhn_high_u32(uint16x4_t r, uint32x4_t a, uint32x4_t b)
+ // argprep: r -> Vd.4H; a -> Vn.4S; b -> Vm.4S
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VRADDHN_HIGH_U32; // RADDHN2 Vd.8H,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint32x4_t vraddhn_high_u64(uint32x2_t r, uint64x2_t a, uint64x2_t b)
+ // argprep: r -> Vd.2S; a -> Vn.2D; b -> Vm.2D
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VRADDHN_HIGH_U64; // RADDHN2 Vd.4S,Vn.2D,Vm.2D
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint8x8_t vraddhn_u16(uint16x8_t a, uint16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VRADDHN_U16; // RADDHN Vd.8B,Vn.8H,Vm.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint16x4_t vraddhn_u32(uint32x4_t a, uint32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VRADDHN_U32; // RADDHN Vd.4H,Vn.4S,Vm.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint32x2_t vraddhn_u64(uint64x2_t a, uint64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VRADDHN_U64; // RADDHN Vd.2S,Vn.2D,Vm.2D
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -17291,15 +20270,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_RBIT_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VRBIT_S8; // RBIT Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VRBITQ_S8; // RBIT Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VRBIT_U8; // RBIT Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VRBITQ_U8; // RBIT Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VRBIT_P8; // RBIT Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VRBITQ_P8; // RBIT Vd.16B,Vn.16B
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -17307,15 +20286,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_REV16_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VREV16_S8; // REV16 Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VREV16Q_S8; // REV16 Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VREV16_U8; // REV16 Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VREV16Q_U8; // REV16 Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VREV16_P8; // REV16 Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VREV16Q_P8; // REV16 Vd.16B,Vn.16B
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -17323,27 +20302,27 @@ bool NeonGetLowLevelILForInstruction(
case ENC_REV32_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VREV32_S8; // REV32 Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VREV32Q_S8; // REV32 Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VREV32_S16; // REV32 Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VREV32Q_S16; // REV32 Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VREV32_U8; // REV32 Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VREV32Q_U8; // REV32 Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VREV32_U16; // REV32 Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VREV32Q_U16; // REV32 Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VREV32_P8; // REV32 Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VREV32Q_P8; // REV32 Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VREV32_P16; // REV32 Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VREV32Q_P16; // REV32 Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -17351,101 +20330,113 @@ bool NeonGetLowLevelILForInstruction(
case ENC_REV64_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VREV64_S8; // REV64 Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VREV64Q_S8; // REV64 Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VREV64_S16; // REV64 Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VREV64Q_S16; // REV64 Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VREV64_S32; // REV64 Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VREV64Q_S32; // REV64 Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VREV64_U8; // REV64 Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VREV64Q_U8; // REV64 Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VREV64_U16; // REV64 Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VREV64Q_U16; // REV64 Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VREV64_U32; // REV64 Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VREV64Q_U32; // REV64 Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VREV64_F32; // REV64 Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VREV64Q_F32; // REV64 Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VREV64_P8; // REV64 Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VREV64Q_P8; // REV64 Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VREV64_P16; // REV64 Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VREV64Q_P16; // REV64 Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VREV64_F16; // REV64 Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VREV64Q_F16; // REV64 Vd.8H,Vn.8H
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_RSHRN_ASIMDSHF_N:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VRSHRN_N_S16; // RSHRN Vd.8B,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VRSHRN_N_S32; // RSHRN Vd.4H,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VRSHRN_N_S64; // RSHRN Vd.2S,Vn.2D,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VRSHRN_N_U16; // RSHRN Vd.8B,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VRSHRN_N_U32; // RSHRN Vd.4H,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VRSHRN_N_U64; // RSHRN Vd.2S,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VRSHRN_HIGH_N_S16; // RSHRN2 Vd.16B,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VRSHRN_HIGH_N_S32; // RSHRN2 Vd.8H,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VRSHRN_HIGH_N_S64; // RSHRN2 Vd.4S,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x16_t vrshrn_high_n_u16(uint8x8_t r, uint16x8_t a, const int n)
+ // argprep: r -> Vd.8B; a -> Vn.8H; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VRSHRN_HIGH_N_U16; // RSHRN2 Vd.16B,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x8_t vrshrn_high_n_u32(uint16x4_t r, uint32x4_t a, const int n)
+ // argprep: r -> Vd.4H; a -> Vn.4S; n -> n
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VRSHRN_HIGH_N_U32; // RSHRN2 Vd.8H,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x4_t vrshrn_high_n_u64(uint32x2_t r, uint64x2_t a, const int n)
+ // argprep: r -> Vd.4S; a -> Vn.2D; n -> n
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VRSHRN_HIGH_N_U64; // RSHRN2 Vd.4S,Vn.2D,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x8_t vrshrn_n_u16(uint16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> n
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VRSHRN_N_U16; // RSHRN Vd.8B,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x4_t vrshrn_n_u32(uint32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> n
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VRSHRN_N_U32; // RSHRN Vd.4H,Vn.4S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x2_t vrshrn_n_u64(uint64x2_t a, const int n)
+ // argprep: a -> Vn.2D; n -> n
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VRSHRN_N_U64; // RSHRN Vd.2S,Vn.2D,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_RSUBHN_ASIMDDIFF_N:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VRSUBHN_S16; // RSUBHN Vd.8B,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VRSUBHN_S32; // RSUBHN Vd.4H,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VRSUBHN_S64; // RSUBHN Vd.2S,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VRSUBHN_U16; // RSUBHN Vd.8B,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VRSUBHN_U32; // RSUBHN Vd.4H,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VRSUBHN_U64; // RSUBHN Vd.2S,Vn.2D,Vm.2D
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VRSUBHN_HIGH_S16; // RSUBHN2 Vd.16B,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VRSUBHN_HIGH_S32; // RSUBHN2 Vd.8H,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VRSUBHN_HIGH_S64; // RSUBHN2 Vd.4S,Vn.2D,Vm.2D
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint8x16_t vrsubhn_high_u16(uint8x8_t r, uint16x8_t a, uint16x8_t b)
+ // argprep: r -> Vd.8B; a -> Vn.8H; b -> Vm.8H
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VRSUBHN_HIGH_U16; // RSUBHN2 Vd.16B,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint16x8_t vrsubhn_high_u32(uint16x4_t r, uint32x4_t a, uint32x4_t b)
+ // argprep: r -> Vd.4H; a -> Vn.4S; b -> Vm.4S
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VRSUBHN_HIGH_U32; // RSUBHN2 Vd.8H,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint32x4_t vrsubhn_high_u64(uint32x2_t r, uint64x2_t a, uint64x2_t b)
+ // argprep: r -> Vd.2S; a -> Vn.2D; b -> Vm.2D
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VRSUBHN_HIGH_U64; // RSUBHN2 Vd.4S,Vn.2D,Vm.2D
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint8x8_t vrsubhn_u16(uint16x8_t a, uint16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VRSUBHN_U16; // RSUBHN Vd.8B,Vn.8H,Vm.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint16x4_t vrsubhn_u32(uint32x4_t a, uint32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VRSUBHN_U32; // RSUBHN Vd.4H,Vn.4S,Vm.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint32x2_t vrsubhn_u64(uint64x2_t a, uint64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VRSUBHN_U64; // RSUBHN Vd.2S,Vn.2D,Vm.2D
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -17453,15 +20444,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SABAL_ASIMDDIFF_L:
if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VABAL_S8; // SABAL Vd.8H,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VABAL_S16; // SABAL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VABAL_S32; // SABAL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VABAL_HIGH_S8; // SABAL2 Vd.8H,Vn.16B,Vm.16B
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VABAL_HIGH_S16; // SABAL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VABAL_HIGH_S32; // SABAL2 Vd.2D,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -17471,15 +20462,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SABA_ASIMDSAME_ONLY:
if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VABA_S8; // SABA Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VABAQ_S8; // SABA Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VABA_S16; // SABA Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VABAQ_S16; // SABA Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VABA_S32; // SABA Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VABAQ_S32; // SABA Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -17487,18 +20478,36 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SABDL_ASIMDDIFF_L:
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VABDL_S8; // SABDL Vd.8H,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VABDL_S16; // SABDL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VABDL_S32; // SABDL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VABDL_HIGH_S8; // SABDL2 Vd.8H,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // int32x4_t vabdl_high_s16(int16x8_t a, int16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VABDL_HIGH_S16; // SABDL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // int64x2_t vabdl_high_s32(int32x4_t a, int32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VABDL_HIGH_S32; // SABDL2 Vd.2D,Vn.4S,Vm.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // int16x8_t vabdl_high_s8(int8x16_t a, int8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VABDL_HIGH_S8; // SABDL2 Vd.8H,Vn.16B,Vm.16B
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // int32x4_t vabdl_s16(int16x4_t a, int16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VABDL_S16; // SABDL Vd.4S,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // int64x2_t vabdl_s32(int32x2_t a, int32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VABDL_S32; // SABDL Vd.2D,Vn.2S,Vm.2S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // int16x8_t vabdl_s8(int8x8_t a, int8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VABDL_S8; // SABDL Vd.8H,Vn.8B,Vm.8B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -17506,15 +20515,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SABD_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VABD_S8; // SABD Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VABDQ_S8; // SABD Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VABD_S16; // SABD Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VABDQ_S16; // SABD Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VABD_S32; // SABD Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VABDQ_S32; // SABD Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -17523,15 +20532,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SADALP_ASIMDMISC_P:
if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VPADAL_S8; // SADALP Vd.4H,Vn.8B
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VPADALQ_S8; // SADALP Vd.8H,Vn.16B
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VPADAL_S16; // SADALP Vd.2S,Vn.4H
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VPADALQ_S16; // SADALP Vd.4S,Vn.8H
- if (instr.operands[0].arrSpec == ARRSPEC_1DOUBLE)
+ else if (instr.operands[0].arrSpec == ARRSPEC_1DOUBLE)
intrin_id = ARM64_INTRIN_VPADAL_S32; // SADALP Vd.1D,Vn.2S
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VPADALQ_S32; // SADALP Vd.2D,Vn.4S
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -17540,17 +20549,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SADDLP_ASIMDMISC_P:
if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VPADDL_S8; // SADDLP Vd.4H,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VPADDLQ_S8; // SADDLP Vd.8H,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VPADDL_S16; // SADDLP Vd.2S,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VPADDLQ_S16; // SADDLP Vd.4S,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
+ else if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
intrin_id = ARM64_INTRIN_VPADDL_S32; // SADDLP Vd.1D,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VPADDLQ_S32; // SADDLP Vd.2D,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
+ else if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
intrin_id = ARM64_INTRIN_VADDLV_S32; // SADDLP Vd.1D,Vn.2S
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -17561,18 +20570,36 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SADDL_ASIMDDIFF_L:
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VADDL_S8; // SADDL Vd.8H,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VADDL_S16; // SADDL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VADDL_S32; // SADDL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VADDL_HIGH_S8; // SADDL2 Vd.8H,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // int32x4_t vaddl_high_s16(int16x8_t a, int16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VADDL_HIGH_S16; // SADDL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // int64x2_t vaddl_high_s32(int32x4_t a, int32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VADDL_HIGH_S32; // SADDL2 Vd.2D,Vn.4S,Vm.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // int16x8_t vaddl_high_s8(int8x16_t a, int8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VADDL_HIGH_S8; // SADDL2 Vd.8H,Vn.16B,Vm.16B
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // int32x4_t vaddl_s16(int16x4_t a, int16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VADDL_S16; // SADDL Vd.4S,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // int64x2_t vaddl_s32(int32x2_t a, int32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VADDL_S32; // SADDL Vd.2D,Vn.2S,Vm.2S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // int16x8_t vaddl_s8(int8x8_t a, int8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VADDL_S8; // SADDL Vd.8H,Vn.8B,Vm.8B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -17580,52 +20607,142 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SADDW_ASIMDDIFF_W:
if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VADDW_S8; // SADDW Vd.8H,Vn.8H,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VADDW_S16; // SADDW Vd.4S,Vn.4S,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VADDW_S32; // SADDW Vd.2D,Vn.2D,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VADDW_HIGH_S8; // SADDW2 Vd.8H,Vn.8H,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VADDW_HIGH_S16; // SADDW2 Vd.4S,Vn.4S,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VADDW_HIGH_S32; // SADDW2 Vd.2D,Vn.2D,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SCVTF_ASIMDMISCFP16_R:
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // float16x8_t vcvtq_f16_s16(int16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCVTQ_F16_S16; // SCVTF Vd.8H,Vn.8H
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_SCVTF_ASIMDMISC_R:
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // float32x2_t vcvt_f32_s32(int32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VCVT_F32_S32; // SCVTF Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // float32x4_t vcvtq_f32_s32(int32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VCVTQ_F32_S32; // SCVTF Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // float64x2_t vcvtq_f64_s64(int64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VCVTQ_F64_S64; // SCVTF Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VCVT_N_F32_S32; // SCVTF Vd.2S,Vn.2S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCVTQ_N_F32_S32; // SCVTF Vd.4S,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VCVTQ_N_F64_S64; // SCVTF Vd.2D,Vn.2D,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_SCVTF_ASIMDSHF_C:
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // float16x4_t vcvt_f16_s16(int16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCVT_F16_S16; // SCVTF Vd.4H,Vn.4H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VCVTQ_F16_S16; // SCVTF Vd.8H,Vn.8H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // float16x4_t vcvt_n_f16_s16(int16x4_t a, const int n)
+ // argprep: a -> Vn.4H; n -> <n>
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VCVT_N_F16_S16; // SCVTF Vd.4H,Vn.4H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // float32x2_t vcvt_n_f32_s32(int32x2_t a, const int n)
+ // argprep: a -> Vn.2S; n -> <n>
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VCVT_N_F32_S32; // SCVTF Vd.2S,Vn.2S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // float16x8_t vcvtq_f16_s16(int16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VCVTQ_F16_S16; // SCVTF Vd.8H,Vn.8H,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // float16x8_t vcvtq_n_f16_s16(int16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> <n>
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VCVTQ_N_F16_S16; // SCVTF Vd.8H,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // float32x4_t vcvtq_n_f32_s32(int32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> <n>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VCVTQ_N_F32_S32; // SCVTF Vd.4S,Vn.4S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // float64x2_t vcvtq_n_f64_s64(int64x2_t a, const int n)
+ // argprep: a -> Vn.2D; n -> <n>
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VCVTQ_N_F64_S64; // SCVTF Vd.2D,Vn.2D,#n
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_SCVTF_ASISDMISCFP16_R:
+ if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31))
+ // float16_t vcvth_f16_s16(int16_t a)
+ // argprep: a -> Hn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCVTH_F16_S16; // SCVTF Hd,Hn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_SCVTF_ASISDSHF_C:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // float64x1_t vcvt_n_f64_s64(int64x1_t a, const int n)
+ // argprep: a -> Dn; n -> <n>
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCVT_N_F64_S64; // SCVTF Dd,Dn,#n
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // float16_t vcvth_n_f16_s16(int16_t a, const int n)
+ // argprep: a -> Hn; n -> <n>
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VCVTH_N_F16_S16; // SCVTF Hd,Hn,#n
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // float32_t vcvts_n_f32_s32(int32_t a, const int n)
+ // argprep: a -> Sn; n -> <n>
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCVTS_N_F32_S32; // SCVTF Sd,Sn,#n
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_imm(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_SCVTF_D32_FLOAT2INT:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // float64x1_t vcvt_f64_s64(int64x1_t a)
+ // argprep: a -> Dn
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VCVT_F64_S64; // SCVTF Dd,Dn
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_output_reg(outputs, il, instr.operands[0]);
+ break;
+ case ENC_SCVTF_S32_FLOAT2INT:
+ // float32_t vcvts_f32_s32(int32_t a)
+ // asig: SCVTF Sd,Sn
+ // argprep: a -> Sn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VCVTS_F32_S32; // SCVTF Sd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SDOT_ASIMDELEM_D:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VDOT_LANE_S32; // SDOT Vd.2S,Vn.8B,Vm.4B[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VDOTQ_LANEQ_S32; // SDOT Vd.4S,Vn.16B,Vm.4B[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VDOT_LANEQ_S32; // SDOT Vd.2S,Vn.8B,Vm.4B[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VDOTQ_LANE_S32; // SDOT Vd.4S,Vn.16B,Vm.4B[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -17636,7 +20753,7 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SDOT_ASIMDSAME2_D:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VDOT_S32; // SDOT Vd.2S,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VDOTQ_S32; // SDOT Vd.4S,Vn.16B,Vm.16B
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -17739,79 +20856,126 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SHADD_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VHADD_S8; // SHADD Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VHADDQ_S8; // SHADD Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VHADD_S16; // SHADD Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VHADDQ_S16; // SHADD Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VHADD_S32; // SHADD Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VHADDQ_S32; // SHADD Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SHLL_ASIMDMISC_S:
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSHLL_N_S8; // SHLL Vd.8H,Vn.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VSHLL_N_S16; // SHLL Vd.4S,Vn.4H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VSHLL_N_S32; // SHLL Vd.2D,Vn.2S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSHLL_N_U8; // SHLL Vd.8H,Vn.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VSHLL_N_U16; // SHLL Vd.4S,Vn.4H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VSHLL_N_U32; // SHLL Vd.2D,Vn.2S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_S8; // SHLL2 Vd.8H,Vn.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 16))
+ // float32x4_t vcvt_f32_bf16(bfloat16x4_t a)
+ // immediate: #16
+ // argprep: a -> Vn.8H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VCVT_F32_BF16; // SHLL Vd.4S,Vn.8H,#16
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 16))
+ // float32x4_t vcvtq_high_f32_bf16(bfloat16x8_t a)
+ // immediate: #16
+ // argprep: a -> Vn.8H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VCVTQ_HIGH_F32_BF16; // SHLL2 Vd.4S,Vn.8H,#16
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 16))
+ // float32x4_t vcvtq_low_f32_bf16(bfloat16x8_t a)
+ // immediate: #16
+ // argprep: a -> Vn.8H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VCVTQ_LOW_F32_BF16; // SHLL Vd.4S,Vn.8H,#16
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // int32x4_t vshll_high_n_s16(int16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> <n>
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_S16; // SHLL2 Vd.4S,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // int64x2_t vshll_high_n_s32(int32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> <n>
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_S32; // SHLL2 Vd.2D,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_U8; // SHLL2 Vd.8H,Vn.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ // int16x8_t vshll_high_n_s8(int8x16_t a, const int n)
+ // argprep: a -> Vn.16B; n -> <n>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_S8; // SHLL2 Vd.8H,Vn.16B,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint32x4_t vshll_high_n_u16(uint16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> <n>
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_U16; // SHLL2 Vd.4S,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint64x2_t vshll_high_n_u32(uint32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> <n>
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_U32; // SHLL2 Vd.2D,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCVT_F32_BF16; // SHLL Vd.4S,Vn.8H,#16
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCVTQ_LOW_F32_BF16; // SHLL Vd.4S,Vn.8H,#16
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VCVTQ_HIGH_F32_BF16; // SHLL2 Vd.4S,Vn.8H,#16
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ // uint16x8_t vshll_high_n_u8(uint8x16_t a, const int n)
+ // argprep: a -> Vn.16B; n -> <n>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_U8; // SHLL2 Vd.8H,Vn.16B,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // int32x4_t vshll_n_s16(int16x4_t a, const int n)
+ // argprep: a -> Vn.4H; n -> <n>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VSHLL_N_S16; // SHLL Vd.4S,Vn.4H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // int64x2_t vshll_n_s32(int32x2_t a, const int n)
+ // argprep: a -> Vn.2S; n -> <n>
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VSHLL_N_S32; // SHLL Vd.2D,Vn.2S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ // int16x8_t vshll_n_s8(int8x8_t a, const int n)
+ // argprep: a -> Vn.8B; n -> <n>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VSHLL_N_S8; // SHLL Vd.8H,Vn.8B,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // uint32x4_t vshll_n_u16(uint16x4_t a, const int n)
+ // argprep: a -> Vn.4H; n -> <n>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VSHLL_N_U16; // SHLL Vd.4S,Vn.4H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint64x2_t vshll_n_u32(uint32x2_t a, const int n)
+ // argprep: a -> Vn.2S; n -> <n>
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VSHLL_N_U32; // SHLL Vd.2D,Vn.2S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ // uint16x8_t vshll_n_u8(uint8x8_t a, const int n)
+ // argprep: a -> Vn.8B; n -> <n>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VSHLL_N_U8; // SHLL Vd.8H,Vn.8B,#n
add_input_reg(inputs, il, instr.operands[1]);
- add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SHL_ASIMDSHF_R:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VSHL_N_S8; // SHL Vd.8B,Vn.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VSHL_N_S16; // SHL Vd.4H,Vn.4H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSHLQ_N_S16; // SHL Vd.8H,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VSHL_N_S32; // SHL Vd.2S,Vn.2S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSHLQ_N_S32; // SHL Vd.4S,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSHLQ_N_S64; // SHL Vd.2D,Vn.2D,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VSHL_N_U8; // SHL Vd.8B,Vn.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VSHL_N_U16; // SHL Vd.4H,Vn.4H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSHLQ_N_U16; // SHL Vd.8H,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VSHL_N_U32; // SHL Vd.2S,Vn.2S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSHLQ_N_U32; // SHL Vd.4S,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSHLQ_N_U64; // SHL Vd.2D,Vn.2D,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
@@ -17832,30 +20996,36 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SHRN_ASIMDSHF_N:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VSHRN_N_S16; // SHRN Vd.8B,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VSHRN_N_S32; // SHRN Vd.4H,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VSHRN_N_S64; // SHRN Vd.2S,Vn.2D,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VSHRN_N_U16; // SHRN Vd.8B,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VSHRN_N_U32; // SHRN Vd.4H,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VSHRN_N_U64; // SHRN Vd.2S,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VSHRN_HIGH_N_S16; // SHRN2 Vd.16B,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSHRN_HIGH_N_S32; // SHRN2 Vd.8H,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VSHRN_HIGH_N_S64; // SHRN2 Vd.4S,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x16_t vshrn_high_n_u16(uint8x8_t r, uint16x8_t a, const int n)
+ // argprep: r -> Vd.8B; a -> Vn.8H; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VSHRN_HIGH_N_U16; // SHRN2 Vd.16B,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x8_t vshrn_high_n_u32(uint16x4_t r, uint32x4_t a, const int n)
+ // argprep: r -> Vd.4H; a -> Vn.4S; n -> n
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VSHRN_HIGH_N_U32; // SHRN2 Vd.8H,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x4_t vshrn_high_n_u64(uint32x2_t r, uint64x2_t a, const int n)
+ // argprep: r -> Vd.2S; a -> Vn.2D; n -> n
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VSHRN_HIGH_N_U64; // SHRN2 Vd.4S,Vn.2D,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x8_t vshrn_n_u16(uint16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> n
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VSHRN_N_U16; // SHRN Vd.8B,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x4_t vshrn_n_u32(uint32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> n
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VSHRN_N_U32; // SHRN Vd.4H,Vn.4S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x2_t vshrn_n_u64(uint64x2_t a, const int n)
+ // argprep: a -> Vn.2D; n -> n
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VSHRN_N_U64; // SHRN Vd.2S,Vn.2D,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -17863,70 +21033,68 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SHSUB_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VHSUB_S8; // SHSUB Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VHSUBQ_S8; // SHSUB Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VHSUB_S16; // SHSUB Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VHSUBQ_S16; // SHSUB Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VHSUB_S32; // SHSUB Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VHSUBQ_S32; // SHSUB Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_SLI_ASISDSHF_R:
case ENC_SLI_ASIMDSHF_R:
- if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VSLI_N_S8; // SLI Vd.8B,Vn.8B,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VSLI_N_S16; // SLI Vd.4H,Vn.4H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSLIQ_N_S16; // SLI Vd.8H,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VSLI_N_S32; // SLI Vd.2S,Vn.2S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VSLIQ_N_S32; // SLI Vd.4S,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VSLIQ_N_S64; // SLI Vd.2D,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VSLI_N_U8; // SLI Vd.8B,Vn.8B,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x4_t vsli_n_u16(uint16x4_t a, uint16x4_t b, const int n)
+ // argprep: a -> Vd.4H; b -> Vn.4H; n -> n
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VSLI_N_U16; // SLI Vd.4H,Vn.4H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSLIQ_N_U16; // SLI Vd.8H,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x8_t vsli_n_u8(uint8x8_t a, uint8x8_t b, const int n)
+ // argprep: a -> Vd.8B; b -> Vn.8B; n -> n
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VSLI_N_U8; // SLI Vd.8B,Vn.8B,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x2_t vsli_n_u32(uint32x2_t a, uint32x2_t b, const int n)
+ // argprep: a -> Vd.2S; b -> Vn.2S; n -> n
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VSLI_N_U32; // SLI Vd.2S,Vn.2S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VSLIQ_N_U32; // SLI Vd.4S,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x8_t vsliq_n_u16(uint16x8_t a, uint16x8_t b, const int n)
+ // argprep: a -> Vd.8H; b -> Vn.8H; n -> n
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VSLIQ_N_U16; // SLI Vd.8H,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint64x2_t vsliq_n_u64(uint64x2_t a, uint64x2_t b, const int n)
+ // argprep: a -> Vd.2D; b -> Vn.2D; n -> n
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VSLIQ_N_U64; // SLI Vd.2D,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VSLIQ_N_P64; // SLI Vd.2D,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VSLI_N_P8; // SLI Vd.8B,Vn.8B,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VSLI_N_P16; // SLI Vd.4H,Vn.4H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSLIQ_N_P16; // SLI Vd.8H,Vn.8H,#n
- add_input_reg(inputs, il, instr.operands[0]);
- add_input_reg(inputs, il, instr.operands[1]);
- add_input_imm(inputs, il, instr.operands[2]);
- add_output_reg(outputs, il, instr.operands[0]);
- break;
- case ENC_SLI_ASISDSHF_R:
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VSLIQ_N_S8; // SLI Vd.16B,Vn.16B,#n
- // if(None) intrin_id = ARM64_INTRIN_VSLI_N_S64; // SLI Dd,Dn,#n
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x4_t vsliq_n_u32(uint32x4_t a, uint32x4_t b, const int n)
+ // argprep: a -> Vd.4S; b -> Vn.4S; n -> n
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VSLIQ_N_U32; // SLI Vd.4S,Vn.4S,#n
+ // add_input_reg(inputs, il, instr.operands[0]);
+ // add_input_reg(inputs, il, instr.operands[1]);
+ // add_input_imm(inputs, il, instr.operands[2]);
+ // add_output_reg(outputs, il, instr.operands[0]);
+ // break;
+ // case ENC_SLI_ASISDSHF_R:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint64_t vslid_n_u64(uint64_t a, uint64_t b, const int n)
+ // argprep: a -> Dd; b -> Dn; n -> n
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VSLID_N_U64; // SLI Dd,Dn,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x16_t vsliq_n_u8(uint8x16_t a, uint8x16_t b, const int n)
+ // argprep: a -> Vd.16B; b -> Vn.16B; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VSLIQ_N_U8; // SLI Vd.16B,Vn.16B,#n
- // if(None) intrin_id = ARM64_INTRIN_VSLI_N_U64; // SLI Dd,Dn,#n
- // if(None) intrin_id = ARM64_INTRIN_VSLI_N_P64; // SLI Dd,Dn,#n
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VSLIQ_N_P8; // SLI Vd.16B,Vn.16B,#n
- // if(None) intrin_id = ARM64_INTRIN_VSLID_N_S64; // SLI Dd,Dn,#n
- // if(None) intrin_id = ARM64_INTRIN_VSLID_N_U64; // SLI Dd,Dn,#n
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
@@ -18000,17 +21168,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SMAXP_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VPMAX_S8; // SMAXP Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VPMAX_S16; // SMAXP Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VPMAX_S32; // SMAXP Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VPMAXQ_S8; // SMAXP Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VPMAXQ_S16; // SMAXP Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VPMAXQ_S32; // SMAXP Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMAXV_S32; // SMAXP Vd.2S,Vn.2S,Vm.2S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -18024,15 +21192,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SMAX_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMAX_S8; // SMAX Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMAXQ_S8; // SMAX Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMAX_S16; // SMAX Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMAXQ_S16; // SMAX Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMAX_S32; // SMAX Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMAXQ_S32; // SMAX Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -18041,17 +21209,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SMINP_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VPMIN_S8; // SMINP Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VPMIN_S16; // SMINP Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VPMIN_S32; // SMINP Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VPMINQ_S8; // SMINP Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VPMINQ_S16; // SMINP Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VPMINQ_S32; // SMINP Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMINV_S32; // SMINP Vd.2S,Vn.2S,Vm.2S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -18065,15 +21233,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SMIN_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMIN_S8; // SMIN Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMINQ_S8; // SMIN Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMIN_S16; // SMIN Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMINQ_S16; // SMIN Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMIN_S32; // SMIN Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMINQ_S32; // SMIN Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -18082,23 +21250,23 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SMLAL_ASIMDDIFF_L:
if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLAL_S8; // SMLAL Vd.8H,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_S16; // SMLAL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_S32; // SMLAL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_S8; // SMLAL2 Vd.8H,Vn.16B,Vm.16B
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_S16; // SMLAL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_S32; // SMLAL2 Vd.2D,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_N_S16; // SMLAL Vd.4S,Vn.4H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_N_S32; // SMLAL Vd.2D,Vn.2S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_N_S16; // SMLAL2 Vd.4S,Vn.8H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_N_S32; // SMLAL2 Vd.2D,Vn.4S,Vm.S[0]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -18108,19 +21276,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SMLAL_ASIMDELEM_L:
if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_LANE_S16; // SMLAL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_LANE_S32; // SMLAL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_LANE_S16; // SMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_LANE_S32; // SMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_LANEQ_S16; // SMLAL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_LANEQ_S32; // SMLAL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_LANEQ_S16; // SMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_LANEQ_S32; // SMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -18131,23 +21299,23 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SMLSL_ASIMDDIFF_L:
if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLSL_S8; // SMLSL Vd.8H,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_S16; // SMLSL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_S32; // SMLSL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_S8; // SMLSL2 Vd.8H,Vn.16B,Vm.16B
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_S16; // SMLSL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_S32; // SMLSL2 Vd.2D,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_N_S16; // SMLSL Vd.4S,Vn.4H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_N_S32; // SMLSL Vd.2D,Vn.2S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_N_S16; // SMLSL2 Vd.4S,Vn.8H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_N_S32; // SMLSL2 Vd.2D,Vn.4S,Vm.S[0]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -18157,19 +21325,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SMLSL_ASIMDELEM_L:
if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_LANE_S16; // SMLSL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_LANE_S32; // SMLSL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_LANE_S16; // SMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_LANE_S32; // SMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_LANEQ_S16; // SMLSL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_LANEQ_S32; // SMLSL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_LANEQ_S16; // SMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_LANEQ_S32; // SMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -18193,45 +21361,49 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SMULL_ASIMDDIFF_L:
if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMULL_S8; // SMULL Vd.8H,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMULL_S16; // SMULL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMULL_S32; // SMULL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMULL_HIGH_S8; // SMULL2 Vd.8H,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMULL_HIGH_S16; // SMULL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMULL_HIGH_S32; // SMULL2 Vd.2D,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMULL_N_S16; // SMULL Vd.4S,Vn.4H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMULL_N_S32; // SMULL Vd.2D,Vn.2S,Vm.S[0]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMULL_HIGH_N_S16; // SMULL2 Vd.4S,Vn.8H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMULL_HIGH_N_S32; // SMULL2 Vd.2D,Vn.4S,Vm.S[0]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SMULL_ASIMDELEM_L:
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VMULL_LANE_S16; // SMULL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VMULL_LANE_S32; // SMULL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VMULL_HIGH_LANE_S16; // SMULL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VMULL_HIGH_LANE_S32; // SMULL2 Vd.2D,Vn.4S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VMULL_LANEQ_S16; // SMULL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VMULL_LANEQ_S32; // SMULL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // int32x4_t vmull_high_laneq_s16(int16x8_t a, int16x8_t v, const int lane)
+ // argprep: a -> Vn.8H; v -> Vm.8H; lane -> <lane>
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VMULL_HIGH_LANEQ_S16; // SMULL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // int64x2_t vmull_high_laneq_s32(int32x4_t a, int32x4_t v, const int lane)
+ // argprep: a -> Vn.4S; v -> Vm.4S; lane -> <lane>
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VMULL_HIGH_LANEQ_S32; // SMULL2 Vd.2D,Vn.4S,Vm.S[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // int32x4_t vmull_laneq_s16(int16x4_t a, int16x8_t v, const int lane)
+ // argprep: a -> Vn.4H; v -> Vm.8H; lane -> <lane>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VMULL_LANEQ_S16; // SMULL Vd.4S,Vn.4H,Vm.H[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // int64x2_t vmull_laneq_s32(int32x2_t a, int32x4_t v, const int lane)
+ // argprep: a -> Vn.2S; v -> Vm.4S; lane -> <lane>
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VMULL_LANEQ_S32; // SMULL Vd.2D,Vn.2S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_input_lane(inputs, il, instr.operands[2]);
@@ -18240,17 +21412,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQABS_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VQABS_S8; // SQABS Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VQABSQ_S8; // SQABS Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQABS_S16; // SQABS Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQABSQ_S16; // SQABS Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQABS_S32; // SQABS Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQABSQ_S32; // SQABS Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQABSQ_S64; // SQABS Vd.2D,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -18263,17 +21435,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQADD_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VQADD_S8; // SQADD Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VQADDQ_S8; // SQADD Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQADD_S16; // SQADD Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQADDQ_S16; // SQADD Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQADD_S32; // SQADD Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQADDQ_S32; // SQADD Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQADDQ_S64; // SQADD Vd.2D,Vn.2D,Vm.2D
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -18288,19 +21460,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQDMLAL_ASIMDDIFF_L:
if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLAL_S16; // SQDMLAL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLAL_S32; // SQDMLAL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLAL_HIGH_S16; // SQDMLAL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLAL_HIGH_S32; // SQDMLAL2 Vd.2D,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLAL_N_S16; // SQDMLAL Vd.4S,Vn.4H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLAL_N_S32; // SQDMLAL Vd.2D,Vn.2S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLAL_HIGH_N_S16; // SQDMLAL2 Vd.4S,Vn.8H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLAL_HIGH_N_S32; // SQDMLAL2 Vd.2D,Vn.4S,Vm.S[0]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -18310,19 +21482,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQDMLAL_ASIMDELEM_L:
if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLAL_LANE_S16; // SQDMLAL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLAL_LANE_S32; // SQDMLAL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLAL_HIGH_LANE_S16; // SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLAL_HIGH_LANE_S32; // SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLAL_LANEQ_S16; // SQDMLAL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLAL_LANEQ_S32; // SQDMLAL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLAL_HIGH_LANEQ_S16; // SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLAL_HIGH_LANEQ_S32; // SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -18348,19 +21520,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQDMLSL_ASIMDDIFF_L:
if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLSL_S16; // SQDMLSL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLSL_S32; // SQDMLSL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLSL_HIGH_S16; // SQDMLSL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLSL_HIGH_S32; // SQDMLSL2 Vd.2D,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLSL_N_S16; // SQDMLSL Vd.4S,Vn.4H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLSL_N_S32; // SQDMLSL Vd.2D,Vn.2S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLSL_HIGH_N_S16; // SQDMLSL2 Vd.4S,Vn.8H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLSL_HIGH_N_S32; // SQDMLSL2 Vd.2D,Vn.4S,Vm.S[0]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -18370,19 +21542,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQDMLSL_ASIMDELEM_L:
if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLSL_LANE_S16; // SQDMLSL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLSL_LANE_S32; // SQDMLSL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLSL_HIGH_LANE_S16; // SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLSL_HIGH_LANE_S32; // SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLSL_LANEQ_S16; // SQDMLSL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLSL_LANEQ_S32; // SQDMLSL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMLSL_HIGH_LANEQ_S16; // SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQDMLSL_HIGH_LANEQ_S32; // SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -18408,19 +21580,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQDMULH_ASIMDELEM_R:
if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQDMULH_LANE_S16; // SQDMULH Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQDMULHQ_LANE_S16; // SQDMULH Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQDMULH_LANE_S32; // SQDMULH Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMULHQ_LANE_S32; // SQDMULH Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQDMULH_LANEQ_S16; // SQDMULH Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQDMULHQ_LANEQ_S16; // SQDMULH Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQDMULH_LANEQ_S32; // SQDMULH Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMULHQ_LANEQ_S32; // SQDMULH Vd.4S,Vn.4S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -18430,19 +21602,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQDMULH_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQDMULH_S16; // SQDMULH Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQDMULHQ_S16; // SQDMULH Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQDMULH_S32; // SQDMULH Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMULHQ_S32; // SQDMULH Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQDMULH_N_S16; // SQDMULH Vd.4H,Vn.4H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQDMULHQ_N_S16; // SQDMULH Vd.8H,Vn.8H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQDMULH_N_S32; // SQDMULH Vd.2S,Vn.2S,Vm.S[0]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQDMULHQ_N_S32; // SQDMULH Vd.4S,Vn.4S,Vm.S[0]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -18462,56 +21634,102 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQDMULL_ASIMDDIFF_L:
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VQDMULL_S16; // SQDMULL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VQDMULL_S32; // SQDMULL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // int32x4_t vqdmull_high_n_s16(int16x8_t a, int16_t b)
+ // argprep: a -> Vn.8H; b -> Vm.H[0]
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VQDMULL_HIGH_N_S16; // SQDMULL2 Vd.4S,Vn.8H,Vm.H[0]
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // int64x2_t vqdmull_high_n_s32(int32x4_t a, int32_t b)
+ // argprep: a -> Vn.4S; b -> Vm.S[0]
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VQDMULL_HIGH_N_S32; // SQDMULL2 Vd.2D,Vn.4S,Vm.S[0]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // int32x4_t vqdmull_high_s16(int16x8_t a, int16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VQDMULL_HIGH_S16; // SQDMULL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // int64x2_t vqdmull_high_s32(int32x4_t a, int32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VQDMULL_HIGH_S32; // SQDMULL2 Vd.2D,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // int32x4_t vqdmull_n_s16(int16x4_t a, int16_t b)
+ // argprep: a -> Vn.4H; b -> Vm.H[0]
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VQDMULL_N_S16; // SQDMULL Vd.4S,Vn.4H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // int64x2_t vqdmull_n_s32(int32x2_t a, int32_t b)
+ // argprep: a -> Vn.2S; b -> Vm.S[0]
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VQDMULL_N_S32; // SQDMULL Vd.2D,Vn.2S,Vm.S[0]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VQDMULL_HIGH_N_S16; // SQDMULL2 Vd.4S,Vn.8H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VQDMULL_HIGH_N_S32; // SQDMULL2 Vd.2D,Vn.4S,Vm.S[0]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // int32x4_t vqdmull_s16(int16x4_t a, int16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VQDMULL_S16; // SQDMULL Vd.4S,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // int64x2_t vqdmull_s32(int32x2_t a, int32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VQDMULL_S32; // SQDMULL Vd.2D,Vn.2S,Vm.2S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQDMULL_ASIMDELEM_L:
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VQDMULL_LANE_S16; // SQDMULL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VQDMULL_LANE_S32; // SQDMULL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VQDMULL_HIGH_LANE_S16; // SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VQDMULL_HIGH_LANE_S32; // SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VQDMULL_LANEQ_S16; // SQDMULL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VQDMULL_LANEQ_S32; // SQDMULL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // int32x4_t vqdmull_high_laneq_s16(int16x8_t a, int16x8_t v, const int lane)
+ // argprep: a -> Vn.8H; v -> Vm.8H; lane -> <lane>
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VQDMULL_HIGH_LANEQ_S16; // SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // int64x2_t vqdmull_high_laneq_s32(int32x4_t a, int32x4_t v, const int lane)
+ // argprep: a -> Vn.4S; v -> Vm.4S; lane -> <lane>
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VQDMULL_HIGH_LANEQ_S32; // SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // int32x4_t vqdmull_laneq_s16(int16x4_t a, int16x8_t v, const int lane)
+ // argprep: a -> Vn.4H; v -> Vm.8H; lane -> <lane>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VQDMULL_LANEQ_S16; // SQDMULL Vd.4S,Vn.4H,Vm.H[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // int64x2_t vqdmull_laneq_s32(int32x2_t a, int32x4_t v, const int lane)
+ // argprep: a -> Vn.2S; v -> Vm.4S; lane -> <lane>
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VQDMULL_LANEQ_S32; // SQDMULL Vd.2D,Vn.2S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_input_lane(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQDMULL_ASISDDIFF_ONLY:
- intrin_id = ARM64_INTRIN_VQDMULLH_S16; // SQDMULL Sd,Hn,Hm
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].reg[0] >= REG_H0 && instr.operands[2].reg[0] <= REG_H31))
+ // int32_t vqdmullh_s16(int16_t a, int16_t b)
+ // argprep: a -> Hn; b -> Hm
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VQDMULLH_S16; // SQDMULL Sd,Hn,Hm
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].reg[0] >= REG_S0 && instr.operands[2].reg[0] <= REG_S31))
+ // int64_t vqdmulls_s32(int32_t a, int32_t b)
+ // argprep: a -> Sn; b -> Sm
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VQDMULLS_S32; // SQDMULL Dd,Sn,Sm
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQDMULL_ASISDELEM_L:
- intrin_id = ARM64_INTRIN_VQDMULLH_LANE_S16; // SQDMULL Sd,Hn,Vm.H[lane]
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // int32_t vqdmullh_laneq_s16(int16_t a, int16x8_t v, const int lane)
+ // argprep: a -> Hn; v -> Vm.8H; lane -> <lane>
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VQDMULLH_LANEQ_S16; // SQDMULL Sd,Hn,Vm.H[lane]
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // int64_t vqdmulls_laneq_s32(int32_t a, int32x4_t v, const int lane)
+ // argprep: a -> Sn; v -> Vm.4S; lane -> <lane>
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VQDMULLS_LANEQ_S32; // SQDMULL Dd,Sn,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_input_lane(inputs, il, instr.operands[2]);
@@ -18520,17 +21738,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQNEG_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VQNEG_S8; // SQNEG Vd.8B,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VQNEGQ_S8; // SQNEG Vd.16B,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQNEG_S16; // SQNEG Vd.4H,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQNEGQ_S16; // SQNEG Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQNEG_S32; // SQNEG Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQNEGQ_S32; // SQNEG Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQNEGQ_S64; // SQNEG Vd.2D,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -18543,19 +21761,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQRDMLAH_ASIMDELEM_R:
if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQRDMLAH_LANE_S16; // SQRDMLAH Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQRDMLAHQ_LANE_S16; // SQRDMLAH Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQRDMLAH_LANEQ_S16; // SQRDMLAH Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQRDMLAHQ_LANEQ_S16; // SQRDMLAH Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQRDMLAH_LANE_S32; // SQRDMLAH Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQRDMLAHQ_LANE_S32; // SQRDMLAH Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQRDMLAH_LANEQ_S32; // SQRDMLAH Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQRDMLAHQ_LANEQ_S32; // SQRDMLAH Vd.4S,Vn.4S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -18566,11 +21784,11 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQRDMLAH_ASIMDSAME2_ONLY:
if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQRDMLAH_S16; // SQRDMLAH Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQRDMLAH_S32; // SQRDMLAH Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQRDMLAHQ_S16; // SQRDMLAH Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQRDMLAHQ_S32; // SQRDMLAH Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -18588,19 +21806,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQRDMLSH_ASIMDELEM_R:
if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQRDMLSH_LANE_S16; // SQRDMLSH Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQRDMLSHQ_LANE_S16; // SQRDMLSH Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQRDMLSH_LANEQ_S16; // SQRDMLSH Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQRDMLSHQ_LANEQ_S16; // SQRDMLSH Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQRDMLSH_LANE_S32; // SQRDMLSH Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQRDMLSHQ_LANE_S32; // SQRDMLSH Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQRDMLSH_LANEQ_S32; // SQRDMLSH Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQRDMLSHQ_LANEQ_S32; // SQRDMLSH Vd.4S,Vn.4S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -18611,11 +21829,11 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQRDMLSH_ASIMDSAME2_ONLY:
if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQRDMLSH_S16; // SQRDMLSH Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQRDMLSH_S32; // SQRDMLSH Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQRDMLSHQ_S16; // SQRDMLSH Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQRDMLSHQ_S32; // SQRDMLSH Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -18640,19 +21858,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQRDMULH_ASIMDELEM_R:
if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQRDMULH_LANE_S16; // SQRDMULH Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQRDMULHQ_LANE_S16; // SQRDMULH Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQRDMULH_LANE_S32; // SQRDMULH Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQRDMULHQ_LANE_S32; // SQRDMULH Vd.4S,Vn.4S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQRDMULH_LANEQ_S16; // SQRDMULH Vd.4H,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQRDMULHQ_LANEQ_S16; // SQRDMULH Vd.8H,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQRDMULH_LANEQ_S32; // SQRDMULH Vd.2S,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQRDMULHQ_LANEQ_S32; // SQRDMULH Vd.4S,Vn.4S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -18662,19 +21880,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQRDMULH_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQRDMULH_S16; // SQRDMULH Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQRDMULHQ_S16; // SQRDMULH Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQRDMULH_S32; // SQRDMULH Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQRDMULHQ_S32; // SQRDMULH Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQRDMULH_N_S16; // SQRDMULH Vd.4H,Vn.4H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQRDMULHQ_N_S16; // SQRDMULH Vd.8H,Vn.8H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQRDMULH_N_S32; // SQRDMULH Vd.2S,Vn.2S,Vm.S[0]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQRDMULHQ_N_S32; // SQRDMULH Vd.4S,Vn.4S,Vm.S[0]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -18696,17 +21914,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQRSHL_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VQRSHL_S8; // SQRSHL Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VQRSHLQ_S8; // SQRSHL Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQRSHL_S16; // SQRSHL Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQRSHLQ_S16; // SQRSHL Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQRSHL_S32; // SQRSHL Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQRSHLQ_S32; // SQRSHL Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQRSHLQ_S64; // SQRSHL Vd.2D,Vn.2D,Vm.2D
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -18719,63 +21937,145 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQRSHRN_ASIMDSHF_N:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VQRSHRN_N_S16; // SQRSHRN Vd.8B,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VQRSHRN_N_S32; // SQRSHRN Vd.4H,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VQRSHRN_N_S64; // SQRSHRN Vd.2S,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int8x16_t vqrshrn_high_n_s16(int8x8_t r, int16x8_t a, const int n)
+ // argprep: r -> Vd.8B; a -> Vn.8H; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VQRSHRN_HIGH_N_S16; // SQRSHRN2 Vd.16B,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int16x8_t vqrshrn_high_n_s32(int16x4_t r, int32x4_t a, const int n)
+ // argprep: r -> Vd.4H; a -> Vn.4S; n -> n
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VQRSHRN_HIGH_N_S32; // SQRSHRN2 Vd.8H,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int32x4_t vqrshrn_high_n_s64(int32x2_t r, int64x2_t a, const int n)
+ // argprep: r -> Vd.2S; a -> Vn.2D; n -> n
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VQRSHRN_HIGH_N_S64; // SQRSHRN2 Vd.4S,Vn.2D,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int8x8_t vqrshrn_n_s16(int16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> n
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VQRSHRN_N_S16; // SQRSHRN Vd.8B,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int16x4_t vqrshrn_n_s32(int32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> n
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VQRSHRN_N_S32; // SQRSHRN Vd.4H,Vn.4S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int32x2_t vqrshrn_n_s64(int64x2_t a, const int n)
+ // argprep: a -> Vn.2D; n -> n
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VQRSHRN_N_S64; // SQRSHRN Vd.2S,Vn.2D,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQRSHRN_ASISDSHF_N:
- intrin_id = ARM64_INTRIN_VQRSHRNH_N_S16; // SQRSHRN Bd,Hn,#n
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int32_t vqrshrnd_n_s64(int64_t a, const int n)
+ // argprep: a -> Dn; n -> n
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VQRSHRND_N_S64; // SQRSHRN Sd,Dn,#n
+ else if ((instr.operands[0].reg[0] >= REG_B0 && instr.operands[0].reg[0] <= REG_B31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int8_t vqrshrnh_n_s16(int16_t a, const int n)
+ // argprep: a -> Hn; n -> n
+ // results: Bd -> result
+ intrin_id = ARM64_INTRIN_VQRSHRNH_N_S16; // SQRSHRN Bd,Hn,#n
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int16_t vqrshrns_n_s32(int32_t a, const int n)
+ // argprep: a -> Sn; n -> n
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VQRSHRNS_N_S32; // SQRSHRN Hd,Sn,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQRSHRUN_ASIMDSHF_N:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VQRSHRUN_N_S16; // SQRSHRUN Vd.8B,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VQRSHRUN_N_S32; // SQRSHRUN Vd.4H,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VQRSHRUN_N_S64; // SQRSHRUN Vd.2S,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x16_t vqrshrun_high_n_s16(uint8x8_t r, int16x8_t a, const int n)
+ // argprep: r -> Vd.8B; a -> Vn.8H; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VQRSHRUN_HIGH_N_S16; // SQRSHRUN2 Vd.16B,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x8_t vqrshrun_high_n_s32(uint16x4_t r, int32x4_t a, const int n)
+ // argprep: r -> Vd.4H; a -> Vn.4S; n -> n
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VQRSHRUN_HIGH_N_S32; // SQRSHRUN2 Vd.8H,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x4_t vqrshrun_high_n_s64(uint32x2_t r, int64x2_t a, const int n)
+ // argprep: r -> Vd.2S; a -> Vn.2D; n -> n
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VQRSHRUN_HIGH_N_S64; // SQRSHRUN2 Vd.4S,Vn.2D,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x8_t vqrshrun_n_s16(int16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> n
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VQRSHRUN_N_S16; // SQRSHRUN Vd.8B,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x4_t vqrshrun_n_s32(int32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> n
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VQRSHRUN_N_S32; // SQRSHRUN Vd.4H,Vn.4S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x2_t vqrshrun_n_s64(int64x2_t a, const int n)
+ // argprep: a -> Vn.2D; n -> n
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VQRSHRUN_N_S64; // SQRSHRUN Vd.2S,Vn.2D,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQRSHRUN_ASISDSHF_N:
- intrin_id = ARM64_INTRIN_VQRSHRUNH_N_S16; // SQRSHRUN Bd,Hn,#n
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32_t vqrshrund_n_s64(int64_t a, const int n)
+ // argprep: a -> Dn; n -> n
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VQRSHRUND_N_S64; // SQRSHRUN Sd,Dn,#n
+ else if ((instr.operands[0].reg[0] >= REG_B0 && instr.operands[0].reg[0] <= REG_B31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8_t vqrshrunh_n_s16(int16_t a, const int n)
+ // argprep: a -> Hn; n -> n
+ // results: Bd -> result
+ intrin_id = ARM64_INTRIN_VQRSHRUNH_N_S16; // SQRSHRUN Bd,Hn,#n
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16_t vqrshruns_n_s32(int32_t a, const int n)
+ // argprep: a -> Sn; n -> n
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VQRSHRUNS_N_S32; // SQRSHRUN Hd,Sn,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQSHLU_ASIMDSHF_R:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VQSHLU_N_S8; // SQSHLU Vd.8B,Vn.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x4_t vqshlu_n_s16(int16x4_t a, const int n)
+ // argprep: a -> Vn.4H; n -> n
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VQSHLU_N_S16; // SQSHLU Vd.4H,Vn.4H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VQSHLUQ_N_S16; // SQSHLU Vd.8H,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x2_t vqshlu_n_s32(int32x2_t a, const int n)
+ // argprep: a -> Vn.2S; n -> n
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VQSHLU_N_S32; // SQSHLU Vd.2S,Vn.2S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x8_t vqshlu_n_s8(int8x8_t a, const int n)
+ // argprep: a -> Vn.8B; n -> n
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VQSHLU_N_S8; // SQSHLU Vd.8B,Vn.8B,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x8_t vqshluq_n_s16(int16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> n
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VQSHLUQ_N_S16; // SQSHLU Vd.8H,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x4_t vqshluq_n_s32(int32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> n
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VQSHLUQ_N_S32; // SQSHLU Vd.4S,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint64x2_t vqshluq_n_s64(int64x2_t a, const int n)
+ // argprep: a -> Vn.2D; n -> n
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VQSHLUQ_N_S64; // SQSHLU Vd.2D,Vn.2D,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
@@ -18796,19 +22096,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQSHL_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VQSHL_S8; // SQSHL Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VQSHLQ_S8; // SQSHL Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQSHL_S16; // SQSHL Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQSHLQ_S16; // SQSHL Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQSHL_S32; // SQSHL Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQSHLQ_S32; // SQSHL Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQSHLQ_S64; // SQSHL Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VQSHLQ_N_S8; // SQSHL Vd.16B,Vn.16B,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -18821,47 +22121,111 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQSHRN_ASIMDSHF_N:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VQSHRN_N_S16; // SQSHRN Vd.8B,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VQSHRN_N_S32; // SQSHRN Vd.4H,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VQSHRN_N_S64; // SQSHRN Vd.2S,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int8x16_t vqshrn_high_n_s16(int8x8_t r, int16x8_t a, const int n)
+ // argprep: r -> Vd.8B; a -> Vn.8H; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VQSHRN_HIGH_N_S16; // SQSHRN2 Vd.16B,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int16x8_t vqshrn_high_n_s32(int16x4_t r, int32x4_t a, const int n)
+ // argprep: r -> Vd.4H; a -> Vn.4S; n -> n
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VQSHRN_HIGH_N_S32; // SQSHRN2 Vd.8H,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int32x4_t vqshrn_high_n_s64(int32x2_t r, int64x2_t a, const int n)
+ // argprep: r -> Vd.2S; a -> Vn.2D; n -> n
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VQSHRN_HIGH_N_S64; // SQSHRN2 Vd.4S,Vn.2D,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int8x8_t vqshrn_n_s16(int16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> n
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VQSHRN_N_S16; // SQSHRN Vd.8B,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int16x4_t vqshrn_n_s32(int32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> n
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VQSHRN_N_S32; // SQSHRN Vd.4H,Vn.4S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int32x2_t vqshrn_n_s64(int64x2_t a, const int n)
+ // argprep: a -> Vn.2D; n -> n
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VQSHRN_N_S64; // SQSHRN Vd.2S,Vn.2D,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQSHRN_ASISDSHF_N:
- intrin_id = ARM64_INTRIN_VQSHRNH_N_S16; // SQSHRN Bd,Hn,#n
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int32_t vqshrnd_n_s64(int64_t a, const int n)
+ // argprep: a -> Dn; n -> n
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VQSHRND_N_S64; // SQSHRN Sd,Dn,#n
+ else if ((instr.operands[0].reg[0] >= REG_B0 && instr.operands[0].reg[0] <= REG_B31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int8_t vqshrnh_n_s16(int16_t a, const int n)
+ // argprep: a -> Hn; n -> n
+ // results: Bd -> result
+ intrin_id = ARM64_INTRIN_VQSHRNH_N_S16; // SQSHRN Bd,Hn,#n
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int16_t vqshrns_n_s32(int32_t a, const int n)
+ // argprep: a -> Sn; n -> n
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VQSHRNS_N_S32; // SQSHRN Hd,Sn,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQSHRUN_ASIMDSHF_N:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VQSHRUN_N_S16; // SQSHRUN Vd.8B,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VQSHRUN_N_S32; // SQSHRUN Vd.4H,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VQSHRUN_N_S64; // SQSHRUN Vd.2S,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x16_t vqshrun_high_n_s16(uint8x8_t r, int16x8_t a, const int n)
+ // argprep: r -> Vd.8B; a -> Vn.8H; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VQSHRUN_HIGH_N_S16; // SQSHRUN2 Vd.16B,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x8_t vqshrun_high_n_s32(uint16x4_t r, int32x4_t a, const int n)
+ // argprep: r -> Vd.4H; a -> Vn.4S; n -> n
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VQSHRUN_HIGH_N_S32; // SQSHRUN2 Vd.8H,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x4_t vqshrun_high_n_s64(uint32x2_t r, int64x2_t a, const int n)
+ // argprep: r -> Vd.2S; a -> Vn.2D; n -> n
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VQSHRUN_HIGH_N_S64; // SQSHRUN2 Vd.4S,Vn.2D,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x8_t vqshrun_n_s16(int16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> n
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VQSHRUN_N_S16; // SQSHRUN Vd.8B,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x4_t vqshrun_n_s32(int32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> n
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VQSHRUN_N_S32; // SQSHRUN Vd.4H,Vn.4S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x2_t vqshrun_n_s64(int64x2_t a, const int n)
+ // argprep: a -> Vn.2D; n -> n
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VQSHRUN_N_S64; // SQSHRUN Vd.2S,Vn.2D,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQSHRUN_ASISDSHF_N:
- intrin_id = ARM64_INTRIN_VQSHRUNH_N_S16; // SQSHRUN Bd,Hn,#n
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32_t vqshrund_n_s64(int64_t a, const int n)
+ // argprep: a -> Dn; n -> n
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VQSHRUND_N_S64; // SQSHRUN Sd,Dn,#n
+ else if ((instr.operands[0].reg[0] >= REG_B0 && instr.operands[0].reg[0] <= REG_B31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8_t vqshrunh_n_s16(int16_t a, const int n)
+ // argprep: a -> Hn; n -> n
+ // results: Bd -> result
+ intrin_id = ARM64_INTRIN_VQSHRUNH_N_S16; // SQSHRUN Bd,Hn,#n
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16_t vqshruns_n_s32(int32_t a, const int n)
+ // argprep: a -> Sn; n -> n
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VQSHRUNS_N_S32; // SQSHRUN Hd,Sn,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -18869,17 +22233,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SQSUB_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VQSUB_S8; // SQSUB Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VQSUBQ_S8; // SQSUB Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQSUB_S16; // SQSUB Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQSUBQ_S16; // SQSUB Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQSUB_S32; // SQSUB Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQSUBQ_S32; // SQSUB Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQSUBQ_S64; // SQSUB Vd.2D,Vn.2D,Vm.2D
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -18892,59 +22256,123 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQXTN_ASIMDMISC_N:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VQMOVN_S16; // SQXTN Vd.8B,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VQMOVN_S32; // SQXTN Vd.4H,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VQMOVN_S64; // SQXTN Vd.2S,Vn.2D
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // int8x16_t vqmovn_high_s16(int8x8_t r, int16x8_t a)
+ // argprep: r -> Vd.8B; a -> Vn.8H
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VQMOVN_HIGH_S16; // SQXTN2 Vd.16B,Vn.8H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // int16x8_t vqmovn_high_s32(int16x4_t r, int32x4_t a)
+ // argprep: r -> Vd.4H; a -> Vn.4S
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VQMOVN_HIGH_S32; // SQXTN2 Vd.8H,Vn.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // int32x4_t vqmovn_high_s64(int32x2_t r, int64x2_t a)
+ // argprep: r -> Vd.2S; a -> Vn.2D
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VQMOVN_HIGH_S64; // SQXTN2 Vd.4S,Vn.2D
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // int8x8_t vqmovn_s16(int16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VQMOVN_S16; // SQXTN Vd.8B,Vn.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // int16x4_t vqmovn_s32(int32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VQMOVN_S32; // SQXTN Vd.4H,Vn.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // int32x2_t vqmovn_s64(int64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VQMOVN_S64; // SQXTN Vd.2S,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQXTN_ASISDMISC_N:
- intrin_id = ARM64_INTRIN_VQMOVNH_S16; // SQXTN Bd,Hn
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // int32_t vqmovnd_s64(int64_t a)
+ // argprep: a -> Dn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VQMOVND_S64; // SQXTN Sd,Dn
+ else if ((instr.operands[0].reg[0] >= REG_B0 && instr.operands[0].reg[0] <= REG_B31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31))
+ // int8_t vqmovnh_s16(int16_t a)
+ // argprep: a -> Hn
+ // results: Bd -> result
+ intrin_id = ARM64_INTRIN_VQMOVNH_S16; // SQXTN Bd,Hn
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // int16_t vqmovns_s32(int32_t a)
+ // argprep: a -> Sn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VQMOVNS_S32; // SQXTN Hd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQXTUN_ASIMDMISC_N:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VQMOVUN_S16; // SQXTUN Vd.8B,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VQMOVUN_S32; // SQXTUN Vd.4H,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VQMOVUN_S64; // SQXTUN Vd.2S,Vn.2D
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint8x16_t vqmovun_high_s16(uint8x8_t r, int16x8_t a)
+ // argprep: r -> Vd.8B; a -> Vn.8H
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VQMOVUN_HIGH_S16; // SQXTUN2 Vd.16B,Vn.8H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint16x8_t vqmovun_high_s32(uint16x4_t r, int32x4_t a)
+ // argprep: r -> Vd.4H; a -> Vn.4S
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VQMOVUN_HIGH_S32; // SQXTUN2 Vd.8H,Vn.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // uint32x4_t vqmovun_high_s64(uint32x2_t r, int64x2_t a)
+ // argprep: r -> Vd.2S; a -> Vn.2D
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VQMOVUN_HIGH_S64; // SQXTUN2 Vd.4S,Vn.2D
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint8x8_t vqmovun_s16(int16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VQMOVUN_S16; // SQXTUN Vd.8B,Vn.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint16x4_t vqmovun_s32(int32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VQMOVUN_S32; // SQXTUN Vd.4H,Vn.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // uint32x2_t vqmovun_s64(int64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VQMOVUN_S64; // SQXTUN Vd.2S,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SQXTUN_ASISDMISC_N:
- intrin_id = ARM64_INTRIN_VQMOVUNH_S16; // SQXTUN Bd,Hn
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31))
+ // uint32_t vqmovund_s64(int64_t a)
+ // argprep: a -> Dn
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VQMOVUND_S64; // SQXTUN Sd,Dn
+ else if ((instr.operands[0].reg[0] >= REG_B0 && instr.operands[0].reg[0] <= REG_B31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31))
+ // uint8_t vqmovunh_s16(int16_t a)
+ // argprep: a -> Hn
+ // results: Bd -> result
+ intrin_id = ARM64_INTRIN_VQMOVUNH_S16; // SQXTUN Bd,Hn
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31))
+ // uint16_t vqmovuns_s32(int32_t a)
+ // argprep: a -> Sn
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VQMOVUNS_S32; // SQXTUN Hd,Sn
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SRHADD_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VRHADD_S8; // SRHADD Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VRHADDQ_S8; // SRHADD Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRHADD_S16; // SRHADD Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRHADDQ_S16; // SRHADD Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRHADD_S32; // SRHADD Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRHADDQ_S32; // SRHADD Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -18953,35 +22381,35 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SRI_ASIMDSHF_R:
if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VSRI_N_S8; // SRI Vd.8B,Vn.8B,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VSRI_N_S16; // SRI Vd.4H,Vn.4H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSRIQ_N_S16; // SRI Vd.8H,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VSRI_N_S32; // SRI Vd.2S,Vn.2S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSRIQ_N_S32; // SRI Vd.4S,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSRIQ_N_S64; // SRI Vd.2D,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VSRI_N_U8; // SRI Vd.8B,Vn.8B,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VSRI_N_U16; // SRI Vd.4H,Vn.4H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSRIQ_N_U16; // SRI Vd.8H,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VSRI_N_U32; // SRI Vd.2S,Vn.2S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSRIQ_N_U32; // SRI Vd.4S,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSRIQ_N_U64; // SRI Vd.2D,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSRIQ_N_P64; // SRI Vd.2D,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VSRI_N_P8; // SRI Vd.8B,Vn.8B,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VSRI_N_P16; // SRI Vd.4H,Vn.4H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSRIQ_N_P16; // SRI Vd.8H,Vn.8H,#n
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -18989,17 +22417,16 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SRI_ASISDSHF_R:
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VSRIQ_N_S8; // SRI Vd.16B,Vn.16B,#n
- // if(None) intrin_id = ARM64_INTRIN_VSRI_N_S64; // SRI Dd,Dn,#n
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint64_t vsrid_n_u64(uint64_t a, uint64_t b, const int n)
+ // argprep: a -> Dd; b -> Dn; n -> n
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VSRID_N_U64; // SRI Dd,Dn,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x16_t vsriq_n_u8(uint8x16_t a, uint8x16_t b, const int n)
+ // argprep: a -> Vd.16B; b -> Vn.16B; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VSRIQ_N_U8; // SRI Vd.16B,Vn.16B,#n
- // if(None) intrin_id = ARM64_INTRIN_VSRI_N_U64; // SRI Dd,Dn,#n
- // if(None) intrin_id = ARM64_INTRIN_VSRI_N_P64; // SRI Dd,Dn,#n
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VSRIQ_N_P8; // SRI Vd.16B,Vn.16B,#n
- // if(None) intrin_id = ARM64_INTRIN_VSRID_N_S64; // SRI Dd,Dn,#n
- // if(None) intrin_id = ARM64_INTRIN_VSRID_N_U64; // SRI Dd,Dn,#n
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
@@ -19008,17 +22435,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SRSHL_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VRSHL_S8; // SRSHL Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VRSHLQ_S8; // SRSHL Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRSHL_S16; // SRSHL Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRSHLQ_S16; // SRSHL Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRSHL_S32; // SRSHL Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRSHLQ_S32; // SRSHL Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRSHLQ_S64; // SRSHL Vd.2D,Vn.2D,Vm.2D
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -19033,107 +22460,205 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SRSHR_ASIMDSHF_R:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VRSHR_N_S8; // SRSHR Vd.8B,Vn.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRSHR_N_S16; // SRSHR Vd.4H,Vn.4H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRSHRQ_N_S16; // SRSHR Vd.8H,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRSHR_N_S32; // SRSHR Vd.2S,Vn.2S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRSHRQ_N_S32; // SRSHR Vd.4S,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRSHRQ_N_S64; // SRSHR Vd.2D,Vn.2D,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SRSHR_ASISDSHF_R:
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int64_t vrshrd_n_s64(int64_t a, const int n)
+ // argprep: a -> Dn; n -> n
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VRSHRD_N_S64; // SRSHR Dd,Dn,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int8x16_t vrshrq_n_s8(int8x16_t a, const int n)
+ // argprep: a -> Vn.16B; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VRSHRQ_N_S8; // SRSHR Vd.16B,Vn.16B,#n
- // if(None) intrin_id = ARM64_INTRIN_VRSHR_N_S64; // SRSHR Dd,Dn,#n
- // if(None) intrin_id = ARM64_INTRIN_VRSHRD_N_S64; // SRSHR Dd,Dn,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_SRSRA_ASISDSHF_R:
case ENC_SRSRA_ASIMDSHF_R:
- if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VRSRA_N_S8; // SRSRA Vd.8B,Vn.8B,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int16x4_t vrsra_n_s16(int16x4_t a, int16x4_t b, const int n)
+ // argprep: a -> Vd.4H; b -> Vn.4H; n -> n
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VRSRA_N_S16; // SRSRA Vd.4H,Vn.4H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VRSRAQ_N_S16; // SRSRA Vd.8H,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int32x2_t vrsra_n_s32(int32x2_t a, int32x2_t b, const int n)
+ // argprep: a -> Vd.2S; b -> Vn.2S; n -> n
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VRSRA_N_S32; // SRSRA Vd.2S,Vn.2S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int8x8_t vrsra_n_s8(int8x8_t a, int8x8_t b, const int n)
+ // argprep: a -> Vd.8B; b -> Vn.8B; n -> n
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VRSRA_N_S8; // SRSRA Vd.8B,Vn.8B,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int16x8_t vrsraq_n_s16(int16x8_t a, int16x8_t b, const int n)
+ // argprep: a -> Vd.8H; b -> Vn.8H; n -> n
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VRSRAQ_N_S16; // SRSRA Vd.8H,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int32x4_t vrsraq_n_s32(int32x4_t a, int32x4_t b, const int n)
+ // argprep: a -> Vd.4S; b -> Vn.4S; n -> n
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VRSRAQ_N_S32; // SRSRA Vd.4S,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int64x2_t vrsraq_n_s64(int64x2_t a, int64x2_t b, const int n)
+ // argprep: a -> Vd.2D; b -> Vn.2D; n -> n
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VRSRAQ_N_S64; // SRSRA Vd.2D,Vn.2D,#n
- add_input_reg(inputs, il, instr.operands[0]);
- add_input_reg(inputs, il, instr.operands[1]);
- add_input_imm(inputs, il, instr.operands[2]);
- add_output_reg(outputs, il, instr.operands[0]);
- break;
- case ENC_SRSRA_ASISDSHF_R:
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ // add_input_reg(inputs, il, instr.operands[0]);
+ // add_input_reg(inputs, il, instr.operands[1]);
+ // add_input_imm(inputs, il, instr.operands[2]);
+ // add_output_reg(outputs, il, instr.operands[0]);
+ // break;
+ // case ENC_SRSRA_ASISDSHF_R:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int64_t vrsrad_n_s64(int64_t a, int64_t b, const int n)
+ // argprep: a -> Dd; b -> Dn; n -> n
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VRSRAD_N_S64; // SRSRA Dd,Dn,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int8x16_t vrsraq_n_s8(int8x16_t a, int8x16_t b, const int n)
+ // argprep: a -> Vd.16B; b -> Vn.16B; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VRSRAQ_N_S8; // SRSRA Vd.16B,Vn.16B,#n
- // if(None) intrin_id = ARM64_INTRIN_VRSRA_N_S64; // SRSRA Dd,Dn,#n
- // if(None) intrin_id = ARM64_INTRIN_VRSRAD_N_S64; // SRSRA Dd,Dn,#n
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_SXTL_SSHLL_ASIMDSHF_L:
case ENC_SSHLL_ASIMDSHF_L:
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSHLL_N_S8; // SSHLL Vd.8H,Vn.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VSHLL_N_S16; // SSHLL Vd.4S,Vn.4H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VSHLL_N_S32; // SSHLL Vd.2D,Vn.2S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_S8; // SSHLL2 Vd.8H,Vn.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_S16; // SSHLL2 Vd.4S,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_S32; // SSHLL2 Vd.2D,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VMOVL_S8; // SSHLL Vd.8H,Vn.8B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VMOVL_S16; // SSHLL Vd.4S,Vn.4H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VMOVL_S32; // SSHLL Vd.2D,Vn.2S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VMOVL_HIGH_S8; // SSHLL2 Vd.8H,Vn.16B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // int32x4_t vmovl_high_s16(int16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VMOVL_HIGH_S16; // SSHLL2 Vd.4S,Vn.8H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // int64x2_t vmovl_high_s32(int32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VMOVL_HIGH_S32; // SSHLL2 Vd.2D,Vn.4S,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // int16x8_t vmovl_high_s8(int8x16_t a)
+ // argprep: a -> Vn.16B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VMOVL_HIGH_S8; // SSHLL2 Vd.8H,Vn.16B,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // int32x4_t vmovl_s16(int16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VMOVL_S16; // SSHLL Vd.4S,Vn.4H,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // int64x2_t vmovl_s32(int32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VMOVL_S32; // SSHLL Vd.2D,Vn.2S,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // int16x8_t vmovl_s8(int8x8_t a)
+ // argprep: a -> Vn.8B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VMOVL_S8; // SSHLL Vd.8H,Vn.8B,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int32x4_t vshll_high_n_s16(int16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> <n>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_S16; // SSHLL2 Vd.4S,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int64x2_t vshll_high_n_s32(int32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> <n>
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_S32; // SSHLL2 Vd.2D,Vn.4S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int16x8_t vshll_high_n_s8(int8x16_t a, const int n)
+ // argprep: a -> Vn.16B; n -> <n>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_S8; // SSHLL2 Vd.8H,Vn.16B,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int32x4_t vshll_n_s16(int16x4_t a, const int n)
+ // argprep: a -> Vn.4H; n -> <n>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VSHLL_N_S16; // SSHLL Vd.4S,Vn.4H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int64x2_t vshll_n_s32(int32x2_t a, const int n)
+ // argprep: a -> Vn.2S; n -> <n>
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VSHLL_N_S32; // SSHLL Vd.2D,Vn.2S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int16x8_t vshll_n_s8(int8x8_t a, const int n)
+ // argprep: a -> Vn.8B; n -> <n>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VSHLL_N_S8; // SSHLL Vd.8H,Vn.8B,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SSHL_ASIMDSAME_ONLY:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VSHL_S8; // SSHL Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VSHLQ_S8; // SSHL Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // int16x4_t vshl_s16(int16x4_t a, int16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VSHL_S16; // SSHL Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSHLQ_S16; // SSHL Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // int32x2_t vshl_s32(int32x2_t a, int32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VSHL_S32; // SSHL Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // int8x8_t vshl_s8(int8x8_t a, int8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VSHL_S8; // SSHL Vd.8B,Vn.8B,Vm.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // int16x8_t vshlq_s16(int16x8_t a, int16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VSHLQ_S16; // SSHL Vd.8H,Vn.8H,Vm.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // int32x4_t vshlq_s32(int32x4_t a, int32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VSHLQ_S32; // SSHL Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // int64x2_t vshlq_s64(int64x2_t a, int64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VSHLQ_S64; // SSHL Vd.2D,Vn.2D,Vm.2D
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // int8x16_t vshlq_s8(int8x16_t a, int8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VSHLQ_S8; // SSHL Vd.16B,Vn.16B,Vm.16B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SSHL_ASISDSAME_ONLY:
- intrin_id = ARM64_INTRIN_VSHL_S64; // SSHL Dd,Dn,Dm
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].reg[0] >= REG_D0 && instr.operands[2].reg[0] <= REG_D31))
+ // int64x1_t vshl_s64(int64x1_t a, int64x1_t b)
+ // argprep: a -> Dn; b -> Dm
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VSHL_S64; // SSHL Dd,Dn,Dm
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].reg[0] >= REG_D0 && instr.operands[2].reg[0] <= REG_D31))
+ // int64_t vshld_s64(int64_t a, int64_t b)
+ // argprep: a -> Dn; b -> Dm
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VSHLD_S64; // SSHL Dd,Dn,Dm
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -19141,15 +22666,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SSHR_ASIMDSHF_R:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VSHR_N_S8; // SSHR Vd.8B,Vn.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VSHR_N_S16; // SSHR Vd.4H,Vn.4H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSHRQ_N_S16; // SSHR Vd.8H,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VSHR_N_S32; // SSHR Vd.2S,Vn.2S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSHRQ_N_S32; // SSHR Vd.4S,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSHRQ_N_S64; // SSHR Vd.2D,Vn.2D,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
@@ -19167,15 +22692,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SSRA_ASIMDSHF_R:
if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VSRA_N_S8; // SSRA Vd.8B,Vn.8B,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VSRA_N_S16; // SSRA Vd.4H,Vn.4H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSRAQ_N_S16; // SSRA Vd.8H,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VSRA_N_S32; // SSRA Vd.2S,Vn.2S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSRAQ_N_S32; // SSRA Vd.4S,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSRAQ_N_S64; // SSRA Vd.2D,Vn.2D,#n
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -19183,28 +22708,52 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SSRA_ASISDSHF_R:
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int64_t vsrad_n_s64(int64_t a, int64_t b, const int n)
+ // argprep: a -> Dd; b -> Dn; n -> n
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VSRAD_N_S64; // SSRA Dd,Dn,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // int8x16_t vsraq_n_s8(int8x16_t a, int8x16_t b, const int n)
+ // argprep: a -> Vd.16B; b -> Vn.16B; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VSRAQ_N_S8; // SSRA Vd.16B,Vn.16B,#n
- // if(None) intrin_id = ARM64_INTRIN_VSRA_N_S64; // SSRA Dd,Dn,#n
- // if(None) intrin_id = ARM64_INTRIN_VSRAD_N_S64; // SSRA Dd,Dn,#n
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SSUBL_ASIMDDIFF_L:
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSUBL_S8; // SSUBL Vd.8H,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VSUBL_S16; // SSUBL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VSUBL_S32; // SSUBL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSUBL_HIGH_S8; // SSUBL2 Vd.8H,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // int32x4_t vsubl_high_s16(int16x8_t a, int16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VSUBL_HIGH_S16; // SSUBL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // int64x2_t vsubl_high_s32(int32x4_t a, int32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VSUBL_HIGH_S32; // SSUBL2 Vd.2D,Vn.4S,Vm.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // int16x8_t vsubl_high_s8(int8x16_t a, int8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VSUBL_HIGH_S8; // SSUBL2 Vd.8H,Vn.16B,Vm.16B
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // int32x4_t vsubl_s16(int16x4_t a, int16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VSUBL_S16; // SSUBL Vd.4S,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // int64x2_t vsubl_s32(int32x2_t a, int32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VSUBL_S32; // SSUBL Vd.2D,Vn.2S,Vm.2S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // int16x8_t vsubl_s8(int8x8_t a, int8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VSUBL_S8; // SSUBL Vd.8H,Vn.8B,Vm.8B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -19212,45 +22761,51 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SSUBW_ASIMDDIFF_W:
if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSUBW_S8; // SSUBW Vd.8H,Vn.8H,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSUBW_S16; // SSUBW Vd.4S,Vn.4S,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSUBW_S32; // SSUBW Vd.2D,Vn.2D,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSUBW_HIGH_S8; // SSUBW2 Vd.8H,Vn.8H,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSUBW_HIGH_S16; // SSUBW2 Vd.4S,Vn.4S,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSUBW_HIGH_S32; // SSUBW2 Vd.2D,Vn.2D,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_SUBHN_ASIMDDIFF_N:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VSUBHN_S16; // SUBHN Vd.8B,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VSUBHN_S32; // SUBHN Vd.4H,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VSUBHN_S64; // SUBHN Vd.2S,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VSUBHN_U16; // SUBHN Vd.8B,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VSUBHN_U32; // SUBHN Vd.4H,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VSUBHN_U64; // SUBHN Vd.2S,Vn.2D,Vm.2D
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VSUBHN_HIGH_S16; // SUBHN2 Vd.16B,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSUBHN_HIGH_S32; // SUBHN2 Vd.8H,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VSUBHN_HIGH_S64; // SUBHN2 Vd.4S,Vn.2D,Vm.2D
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint8x16_t vsubhn_high_u16(uint8x8_t r, uint16x8_t a, uint16x8_t b)
+ // argprep: r -> Vd.8B; a -> Vn.8H; b -> Vm.8H
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VSUBHN_HIGH_U16; // SUBHN2 Vd.16B,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint16x8_t vsubhn_high_u32(uint16x4_t r, uint32x4_t a, uint32x4_t b)
+ // argprep: r -> Vd.4H; a -> Vn.4S; b -> Vm.4S
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VSUBHN_HIGH_U32; // SUBHN2 Vd.8H,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint32x4_t vsubhn_high_u64(uint32x2_t r, uint64x2_t a, uint64x2_t b)
+ // argprep: r -> Vd.2S; a -> Vn.2D; b -> Vm.2D
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VSUBHN_HIGH_U64; // SUBHN2 Vd.4S,Vn.2D,Vm.2D
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint8x8_t vsubhn_u16(uint16x8_t a, uint16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VSUBHN_U16; // SUBHN Vd.8B,Vn.8H,Vm.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint16x4_t vsubhn_u32(uint32x4_t a, uint32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VSUBHN_U32; // SUBHN Vd.4H,Vn.4S,Vm.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint32x2_t vsubhn_u64(uint64x2_t a, uint64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VSUBHN_U64; // SUBHN Vd.2S,Vn.2D,Vm.2D
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -19258,31 +22813,31 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SUB_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VSUB_S8; // SUB Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VSUBQ_S8; // SUB Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VSUB_S16; // SUB Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSUBQ_S16; // SUB Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VSUB_S32; // SUB Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSUBQ_S32; // SUB Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSUBQ_S64; // SUB Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VSUB_U8; // SUB Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VSUBQ_U8; // SUB Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VSUB_U16; // SUB Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSUBQ_U16; // SUB Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VSUB_U32; // SUB Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSUBQ_U32; // SUB Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSUBQ_U64; // SUB Vd.2D,Vn.2D,Vm.2D
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -19297,11 +22852,11 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SUDOT_ASIMDELEM_D:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VSUDOT_LANE_S32; // SUDOT Vd.2S,Vn.8B,Vm.4B[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VSUDOT_LANEQ_S32; // SUDOT Vd.2S,Vn.8B,Vm.4B[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSUDOTQ_LANE_S32; // SUDOT Vd.4S,Vn.16B,Vm.4B[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSUDOTQ_LANEQ_S32; // SUDOT Vd.4S,Vn.16B,Vm.4B[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -19312,17 +22867,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_SUQADD_ASIMDMISC_R:
if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VUQADD_S8; // SUQADD Vd.8B,Vn.8B
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VUQADDQ_S8; // SUQADD Vd.16B,Vn.16B
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VUQADD_S16; // SUQADD Vd.4H,Vn.4H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VUQADDQ_S16; // SUQADD Vd.8H,Vn.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VUQADD_S32; // SUQADD Vd.2S,Vn.2S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VUQADDQ_S32; // SUQADD Vd.4S,Vn.4S
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VUQADDQ_S64; // SUQADD Vd.2D,Vn.2D
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -19335,20 +22890,92 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_TBL_ASIMDTBL_L1_1:
- intrin_id = ARM64_INTRIN_VTBL1_S8;
+ case ENC_TBX_ASIMDTBL_L1_1:
+ if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
+ if (instr.encoding == ENC_TBL_ASIMDTBL_L1_1)
+ intrin_id = ARM64_INTRIN_VTBL1_S8; // TBL Vd.8B,{Vn.16B},Vm.8B
+ else
+ intrin_id = ARM64_INTRIN_VTBX1_S8; // TBX Vd.8B,{Vn.16B},Vm.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.encoding == ENC_TBL_ASIMDTBL_L1_1)
+ intrin_id = ARM64_INTRIN_VQTBL1Q_S8; // TBL Vd.16B,{Vn.16B},Vm.16B
+ else
+ intrin_id = ARM64_INTRIN_VQTBX1Q_S8; // TBX Vd.16B,{Vn.16B},Vm.16B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ // Technically, the intrinsics for 2, 3, and 4 vector TBL take a vector of vectors (like int8x16x4 for vqtbl4),
+ // but it is simpler to just pass all the vector registers as parameters to the intrinsic.
case ENC_TBL_ASIMDTBL_L2_2:
- // TODO
+ case ENC_TBX_ASIMDTBL_L2_2:
+ {
+ if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
+ if (instr.encoding == ENC_TBL_ASIMDTBL_L2_2)
+ intrin_id = ARM64_INTRIN_VTBL2_S8; // TBL Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+ else
+ intrin_id = ARM64_INTRIN_VTBX2_S8; // TBX Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.encoding == ENC_TBL_ASIMDTBL_L2_2)
+ intrin_id = ARM64_INTRIN_VQTBL2Q_S8; // TBL Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+ else
+ intrin_id = ARM64_INTRIN_VQTBX2Q_S8; // TBX Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+ InstructionOperand tmp;
+ tmp.reg[0] = (Register) (instr.operands[1].reg[0] + 1);
+ add_input_reg(inputs, il, tmp);
+ add_input_reg(inputs, il, instr.operands[1]);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
break;
+ }
case ENC_TBL_ASIMDTBL_L3_3:
- // TODO
+ case ENC_TBX_ASIMDTBL_L3_3:
+ {
+ if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
+ if (instr.encoding == ENC_TBL_ASIMDTBL_L3_3)
+ intrin_id = ARM64_INTRIN_VTBL3_S8; // TBL Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+ else
+ intrin_id = ARM64_INTRIN_VTBX3_S8; // TBX Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.encoding == ENC_TBL_ASIMDTBL_L3_3)
+ intrin_id = ARM64_INTRIN_VQTBL3Q_S8; // TBL Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+ else
+ intrin_id = ARM64_INTRIN_VQTBX3Q_S8; // TBX Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+ add_input_reg(inputs, il, instr.operands[1]);
+ InstructionOperand tmp;
+ tmp.reg[0] = (Register) (instr.operands[1].reg[0] + 1);
+ add_input_reg(inputs, il, tmp);
+ tmp.reg[0] = (Register) (instr.operands[1].reg[0] + 2);
+ add_input_reg(inputs, il, tmp);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
break;
+ }
case ENC_TBL_ASIMDTBL_L4_4:
- // TODO
+ case ENC_TBX_ASIMDTBL_L4_4:
+ {
+ if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
+ if (instr.encoding == ENC_TBL_ASIMDTBL_L4_4)
+ intrin_id = ARM64_INTRIN_VTBL4_S8; // TBL Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+ else
+ intrin_id = ARM64_INTRIN_VTBX4_S8; // TBX Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.encoding == ENC_TBL_ASIMDTBL_L4_4)
+ intrin_id = ARM64_INTRIN_VQTBL4Q_S8; // TBL Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+ else
+ intrin_id = ARM64_INTRIN_VQTBX4Q_S8; // TBX Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+ add_input_reg(inputs, il, instr.operands[1]);
+ InstructionOperand tmp;
+ tmp.reg[0] = (Register) (instr.operands[1].reg[0] + 1);
+ add_input_reg(inputs, il, tmp);
+ tmp.reg[0] = (Register) (instr.operands[1].reg[0] + 2);
+ add_input_reg(inputs, il, tmp);
+ tmp.reg[0] = (Register) (instr.operands[1].reg[0] + 3);
+ add_input_reg(inputs, il, tmp);
+ add_input_reg(inputs, il, instr.operands[2]);
+ add_output_reg(outputs, il, instr.operands[0]);
break;
+ }
case ENC_ST2_ASISDLSE_R2:
case ENC_ST2_ASISDLSEP_I2_I:
// Handling: st2 {Vt.8B - Vt2.8B}, [Xn] [, <IMM>]
@@ -19358,13 +22985,13 @@ bool NeonGetLowLevelILForInstruction(
intrin_id = ARM64_INTRIN_VST2_S8; // ST2 {Vt.8B - Vt2.8B}, [Xn], <IMM>
if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VST2Q_S8; // ST2 {Vt.16B - Vt2.16B}, [Xn], <IMM>
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VST2_S16; // ST2 {Vt.4H - Vt2.4H}, [Xn], <IMM>
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VST2Q_S16; // ST2 {Vt.8H - Vt2.8H}, [Xn], <IMM>
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VST2_S32; // ST2 {Vt.2S - Vt2.2S}, [Xn], <IMM>
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VST2Q_S32; // ST2 {Vt.4S - Vt2.4S}, [Xn], <IMM>
if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VST2Q_S64; // ST2 {Vt.2D - Vt2.2D}, [Xn], <IMM>
@@ -19374,51 +23001,51 @@ bool NeonGetLowLevelILForInstruction(
case ENC_TRN1_ASIMDPERM_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VTRN1_S8; // TRN1 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VTRN1Q_S8; // TRN1 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VTRN1_S16; // TRN1 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VTRN1Q_S16; // TRN1 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VTRN1_S32; // TRN1 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VTRN1Q_S32; // TRN1 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VTRN1Q_S64; // TRN1 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VTRN1_U8; // TRN1 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VTRN1Q_U8; // TRN1 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VTRN1_U16; // TRN1 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VTRN1Q_U16; // TRN1 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VTRN1_U32; // TRN1 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VTRN1Q_U32; // TRN1 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VTRN1Q_U64; // TRN1 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VTRN1Q_P64; // TRN1 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VTRN1_F32; // TRN1 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VTRN1Q_F32; // TRN1 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VTRN1Q_F64; // TRN1 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VTRN1_P8; // TRN1 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VTRN1Q_P8; // TRN1 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VTRN1_P16; // TRN1 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VTRN1Q_P16; // TRN1 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VTRN1_F16; // TRN1 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VTRN1Q_F16; // TRN1 Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -19427,51 +23054,51 @@ bool NeonGetLowLevelILForInstruction(
case ENC_TRN2_ASIMDPERM_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VTRN2_S8; // TRN2 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VTRN2Q_S8; // TRN2 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VTRN2_S16; // TRN2 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VTRN2Q_S16; // TRN2 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VTRN2_S32; // TRN2 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VTRN2Q_S32; // TRN2 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VTRN2Q_S64; // TRN2 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VTRN2_U8; // TRN2 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VTRN2Q_U8; // TRN2 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VTRN2_U16; // TRN2 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VTRN2Q_U16; // TRN2 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VTRN2_U32; // TRN2 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VTRN2Q_U32; // TRN2 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VTRN2Q_U64; // TRN2 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VTRN2Q_P64; // TRN2 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VTRN2_F32; // TRN2 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VTRN2Q_F32; // TRN2 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VTRN2Q_F64; // TRN2 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VTRN2_P8; // TRN2 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VTRN2Q_P8; // TRN2 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VTRN2_P16; // TRN2 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VTRN2Q_P16; // TRN2 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VTRN2_F16; // TRN2 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VTRN2Q_F16; // TRN2 Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -19480,15 +23107,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UABAL_ASIMDDIFF_L:
if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VABAL_U8; // UABAL Vd.8H,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VABAL_U16; // UABAL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VABAL_U32; // UABAL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VABAL_HIGH_U8; // UABAL2 Vd.8H,Vn.16B,Vm.16B
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VABAL_HIGH_U16; // UABAL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VABAL_HIGH_U32; // UABAL2 Vd.2D,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -19498,15 +23125,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UABA_ASIMDSAME_ONLY:
if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VABA_U8; // UABA Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VABAQ_U8; // UABA Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VABA_U16; // UABA Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VABAQ_U16; // UABA Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VABA_U32; // UABA Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VABAQ_U32; // UABA Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -19514,18 +23141,36 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_UABDL_ASIMDDIFF_L:
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VABDL_U8; // UABDL Vd.8H,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VABDL_U16; // UABDL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VABDL_U32; // UABDL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VABDL_HIGH_U8; // UABDL2 Vd.8H,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint32x4_t vabdl_high_u16(uint16x8_t a, uint16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VABDL_HIGH_U16; // UABDL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint64x2_t vabdl_high_u32(uint32x4_t a, uint32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VABDL_HIGH_U32; // UABDL2 Vd.2D,Vn.4S,Vm.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // uint16x8_t vabdl_high_u8(uint8x16_t a, uint8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VABDL_HIGH_U8; // UABDL2 Vd.8H,Vn.16B,Vm.16B
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // uint32x4_t vabdl_u16(uint16x4_t a, uint16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VABDL_U16; // UABDL Vd.4S,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // uint64x2_t vabdl_u32(uint32x2_t a, uint32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VABDL_U32; // UABDL Vd.2D,Vn.2S,Vm.2S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // uint16x8_t vabdl_u8(uint8x8_t a, uint8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VABDL_U8; // UABDL Vd.8H,Vn.8B,Vm.8B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -19533,90 +23178,189 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UABD_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VABD_U8; // UABD Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VABDQ_U8; // UABD Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VABD_U16; // UABD Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VABDQ_U16; // UABD Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VABD_U32; // UABD Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VABDQ_U32; // UABD Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_UADALP_ASIMDMISC_P:
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VPADAL_U8; // UADALP Vd.4H,Vn.8B
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VPADALQ_U8; // UADALP Vd.8H,Vn.16B
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // uint32x2_t vpadal_u16(uint32x2_t a, uint16x4_t b)
+ // argprep: a -> Vd.2S; b -> Vn.4H
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VPADAL_U16; // UADALP Vd.2S,Vn.4H
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VPADALQ_U16; // UADALP Vd.4S,Vn.8H
- if (instr.operands[0].arrSpec == ARRSPEC_1DOUBLE)
+ else if (instr.operands[0].arrSpec == ARRSPEC_1DOUBLE && instr.operands[0].arrSpec == ARRSPEC_1DOUBLE && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint64x1_t vpadal_u32(uint64x1_t a, uint32x2_t b)
+ // argprep: a -> Vd.1D; b -> Vn.2S
+ // results: Vd.1D -> result
intrin_id = ARM64_INTRIN_VPADAL_U32; // UADALP Vd.1D,Vn.2S
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ // uint16x4_t vpadal_u8(uint16x4_t a, uint8x8_t b)
+ // argprep: a -> Vd.4H; b -> Vn.8B
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VPADAL_U8; // UADALP Vd.4H,Vn.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint32x4_t vpadalq_u16(uint32x4_t a, uint16x8_t b)
+ // argprep: a -> Vd.4S; b -> Vn.8H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VPADALQ_U16; // UADALP Vd.4S,Vn.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint64x2_t vpadalq_u32(uint64x2_t a, uint32x4_t b)
+ // argprep: a -> Vd.2D; b -> Vn.4S
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VPADALQ_U32; // UADALP Vd.2D,Vn.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ // uint16x8_t vpadalq_u8(uint16x8_t a, uint8x16_t b)
+ // argprep: a -> Vd.8H; b -> Vn.16B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VPADALQ_U8; // UADALP Vd.8H,Vn.16B
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_UADDLP_ASIMDMISC_P:
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VPADDL_U8; // UADDLP Vd.4H,Vn.8B
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VPADDLQ_U8; // UADDLP Vd.8H,Vn.16B
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint64_t vaddlv_u32(uint32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VADDLV_U32; // UADDLP Vd.1D,Vn.2S
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // uint32x2_t vpaddl_u16(uint16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VPADDL_U16; // UADDLP Vd.2S,Vn.4H
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VPADDLQ_U16; // UADDLP Vd.4S,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
+ else if (instr.operands[0].arrSpec == ARRSPEC_1DOUBLE && instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ // uint64x1_t vpaddl_u32(uint32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.1D -> result
intrin_id = ARM64_INTRIN_VPADDL_U32; // UADDLP Vd.1D,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ // uint16x4_t vpaddl_u8(uint8x8_t a)
+ // argprep: a -> Vn.8B
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VPADDL_U8; // UADDLP Vd.4H,Vn.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint32x4_t vpaddlq_u16(uint16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VPADDLQ_U16; // UADDLP Vd.4S,Vn.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint64x2_t vpaddlq_u32(uint32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VPADDLQ_U32; // UADDLP Vd.2D,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_1DOUBLE)
- intrin_id = ARM64_INTRIN_VADDLV_U32; // UADDLP Vd.1D,Vn.2S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ // uint16x8_t vpaddlq_u8(uint8x16_t a)
+ // argprep: a -> Vn.16B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VPADDLQ_U8; // UADDLP Vd.8H,Vn.16B
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_UADDLV_ASIMDALL_ONLY:
- intrin_id = ARM64_INTRIN_VADDLV_U8; // UADDLV Hd,Vn.8B
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ // uint32_t vaddlv_u16(uint16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VADDLV_U16; // UADDLV Sd,Vn.4H
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ // uint16_t vaddlv_u8(uint8x8_t a)
+ // argprep: a -> Vn.8B
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VADDLV_U8; // UADDLV Hd,Vn.8B
+ else if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint32_t vaddlvq_u16(uint16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VADDLVQ_U16; // UADDLV Sd,Vn.8H
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint64_t vaddlvq_u32(uint32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VADDLVQ_U32; // UADDLV Dd,Vn.4S
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ // uint16_t vaddlvq_u8(uint8x16_t a)
+ // argprep: a -> Vn.16B
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VADDLVQ_U8; // UADDLV Hd,Vn.16B
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_UADDL_ASIMDDIFF_L:
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VADDL_U8; // UADDL Vd.8H,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VADDL_U16; // UADDL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VADDL_U32; // UADDL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VADDL_HIGH_U8; // UADDL2 Vd.8H,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint32x4_t vaddl_high_u16(uint16x8_t a, uint16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VADDL_HIGH_U16; // UADDL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint64x2_t vaddl_high_u32(uint32x4_t a, uint32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VADDL_HIGH_U32; // UADDL2 Vd.2D,Vn.4S,Vm.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // uint16x8_t vaddl_high_u8(uint8x16_t a, uint8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VADDL_HIGH_U8; // UADDL2 Vd.8H,Vn.16B,Vm.16B
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // uint32x4_t vaddl_u16(uint16x4_t a, uint16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VADDL_U16; // UADDL Vd.4S,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // uint64x2_t vaddl_u32(uint32x2_t a, uint32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VADDL_U32; // UADDL Vd.2D,Vn.2S,Vm.2S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // uint16x8_t vaddl_u8(uint8x8_t a, uint8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VADDL_U8; // UADDL Vd.8H,Vn.8B,Vm.8B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_UADDW_ASIMDDIFF_W:
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VADDW_U8; // UADDW Vd.8H,Vn.8H,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VADDW_U16; // UADDW Vd.4S,Vn.4S,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VADDW_U32; // UADDW Vd.2D,Vn.2D,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VADDW_HIGH_U8; // UADDW2 Vd.8H,Vn.8H,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint32x4_t vaddw_high_u16(uint32x4_t a, uint16x8_t b)
+ // argprep: a -> Vn.4S; b -> Vm.8H
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VADDW_HIGH_U16; // UADDW2 Vd.4S,Vn.4S,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint64x2_t vaddw_high_u32(uint64x2_t a, uint32x4_t b)
+ // argprep: a -> Vn.2D; b -> Vm.4S
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VADDW_HIGH_U32; // UADDW2 Vd.2D,Vn.2D,Vm.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // uint16x8_t vaddw_high_u8(uint16x8_t a, uint8x16_t b)
+ // argprep: a -> Vn.8H; b -> Vm.16B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VADDW_HIGH_U8; // UADDW2 Vd.8H,Vn.8H,Vm.16B
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // uint32x4_t vaddw_u16(uint32x4_t a, uint16x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VADDW_U16; // UADDW Vd.4S,Vn.4S,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // uint64x2_t vaddw_u32(uint64x2_t a, uint32x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2S
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VADDW_U32; // UADDW Vd.2D,Vn.2D,Vm.2S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // uint16x8_t vaddw_u8(uint16x8_t a, uint8x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VADDW_U8; // UADDW Vd.8H,Vn.8H,Vm.8B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -19671,30 +23415,26 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_UCVTF_ASIMDMISC_R:
- intrin_id = ARM64_INTRIN_VCVT_F32_U32;
- add_input_reg(inputs, il, instr.operands[1]);
- add_output_reg(outputs, il, instr.operands[0]);
- break;
case ENC_UCVTF_ASIMDMISCFP16_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VCVT_F32_U32; // UCVTF Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VCVTQ_F32_U32; // UCVTF Vd.4S,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VCVTQ_F64_U64; // UCVTF Vd.2D,Vn.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VCVT_N_F32_U32; // UCVTF Vd.2S,Vn.2S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VCVTQ_N_F32_U32; // UCVTF Vd.4S,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VCVTQ_N_F64_U64; // UCVTF Vd.2D,Vn.2D,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCVT_F16_U16; // UCVTF Vd.4H,Vn.4H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VCVTQ_F16_U16; // UCVTF Vd.8H,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCVT_N_F16_U16; // UCVTF Vd.4H,Vn.4H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VCVTQ_N_F16_U16; // UCVTF Vd.8H,Vn.8H,#n
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -19702,11 +23442,11 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UDOT_ASIMDELEM_D:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VDOT_LANE_U32; // UDOT Vd.2S,Vn.8B,Vm.4B[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VDOTQ_LANEQ_U32; // UDOT Vd.4S,Vn.16B,Vm.4B[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VDOT_LANEQ_U32; // UDOT Vd.2S,Vn.8B,Vm.4B[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VDOTQ_LANE_U32; // UDOT Vd.4S,Vn.16B,Vm.4B[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -19717,7 +23457,7 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UDOT_ASIMDSAME2_D:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VDOT_U32; // UDOT Vd.2S,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VDOTQ_U32; // UDOT Vd.4S,Vn.16B,Vm.16B
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -19727,15 +23467,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UHADD_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VHADD_U8; // UHADD Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VHADDQ_U8; // UHADD Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VHADD_U16; // UHADD Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VHADDQ_U16; // UHADD Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VHADD_U32; // UHADD Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VHADDQ_U32; // UHADD Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -19744,15 +23484,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UHSUB_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VHSUB_U8; // UHSUB Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VHSUBQ_U8; // UHSUB Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VHSUB_U16; // UHSUB Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VHSUBQ_U16; // UHSUB Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VHSUB_U32; // UHSUB Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VHSUBQ_U32; // UHSUB Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -19761,17 +23501,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UMAXP_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VPMAX_U8; // UMAXP Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VPMAX_U16; // UMAXP Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VPMAX_U32; // UMAXP Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VPMAXQ_U8; // UMAXP Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VPMAXQ_U16; // UMAXP Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VPMAXQ_U32; // UMAXP Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMAXV_U32; // UMAXP Vd.2S,Vn.2S,Vm.2S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -19785,15 +23525,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UMAX_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMAX_U8; // UMAX Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMAXQ_U8; // UMAX Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMAX_U16; // UMAX Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMAXQ_U16; // UMAX Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMAX_U32; // UMAX Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMAXQ_U32; // UMAX Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -19802,17 +23542,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UMINP_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VPMIN_U8; // UMINP Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VPMIN_U16; // UMINP Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VPMIN_U32; // UMINP Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VPMINQ_U8; // UMINP Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VPMINQ_U16; // UMINP Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VPMINQ_U32; // UMINP Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMINV_U32; // UMINP Vd.2S,Vn.2S,Vm.2S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -19826,15 +23566,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UMIN_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMIN_U8; // UMIN Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMINQ_U8; // UMIN Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMIN_U16; // UMIN Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMINQ_U16; // UMIN Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMIN_U32; // UMIN Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMINQ_U32; // UMIN Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -19843,23 +23583,23 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UMLAL_ASIMDDIFF_L:
if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLAL_U8; // UMLAL Vd.8H,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_U16; // UMLAL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_U32; // UMLAL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_U8; // UMLAL2 Vd.8H,Vn.16B,Vm.16B
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_U16; // UMLAL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_U32; // UMLAL2 Vd.2D,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_N_U16; // UMLAL Vd.4S,Vn.4H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_N_U32; // UMLAL Vd.2D,Vn.2S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_N_U16; // UMLAL2 Vd.4S,Vn.8H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_N_U32; // UMLAL2 Vd.2D,Vn.4S,Vm.S[0]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -19869,19 +23609,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UMLAL_ASIMDELEM_L:
if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_LANE_U16; // UMLAL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_LANE_U32; // UMLAL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_LANE_U16; // UMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_LANE_U32; // UMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_LANEQ_U16; // UMLAL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_LANEQ_U32; // UMLAL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_LANEQ_U16; // UMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLAL_HIGH_LANEQ_U32; // UMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -19892,23 +23632,23 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UMLSL_ASIMDDIFF_L:
if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLSL_U8; // UMLSL Vd.8H,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_U16; // UMLSL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_U32; // UMLSL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_U8; // UMLSL2 Vd.8H,Vn.16B,Vm.16B
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_U16; // UMLSL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_U32; // UMLSL2 Vd.2D,Vn.4S,Vm.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_N_U16; // UMLSL Vd.4S,Vn.4H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_N_U32; // UMLSL Vd.2D,Vn.2S,Vm.S[0]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_N_U16; // UMLSL2 Vd.4S,Vn.8H,Vm.H[0]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_N_U32; // UMLSL2 Vd.2D,Vn.4S,Vm.S[0]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -19918,19 +23658,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UMLSL_ASIMDELEM_L:
if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_LANE_U16; // UMLSL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_LANE_U32; // UMLSL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_LANE_U16; // UMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_LANE_U32; // UMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_LANEQ_U16; // UMLSL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_LANEQ_U32; // UMLSL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_LANEQ_U16; // UMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VMLSL_HIGH_LANEQ_U32; // UMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -19952,47 +23692,81 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_UMULL_ASIMDDIFF_L:
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VMULL_U8; // UMULL Vd.8H,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VMULL_U16; // UMULL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VMULL_U32; // UMULL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VMULL_HIGH_U8; // UMULL2 Vd.8H,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // uint32x4_t vmull_high_n_u16(uint16x8_t a, uint16_t b)
+ // argprep: a -> Vn.8H; b -> Vm.H[0]
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VMULL_HIGH_N_U16; // UMULL2 Vd.4S,Vn.8H,Vm.H[0]
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // uint64x2_t vmull_high_n_u32(uint32x4_t a, uint32_t b)
+ // argprep: a -> Vn.4S; b -> Vm.S[0]
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VMULL_HIGH_N_U32; // UMULL2 Vd.2D,Vn.4S,Vm.S[0]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint32x4_t vmull_high_u16(uint16x8_t a, uint16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VMULL_HIGH_U16; // UMULL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint64x2_t vmull_high_u32(uint32x4_t a, uint32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VMULL_HIGH_U32; // UMULL2 Vd.2D,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // uint16x8_t vmull_high_u8(uint8x16_t a, uint8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VMULL_HIGH_U8; // UMULL2 Vd.8H,Vn.16B,Vm.16B
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // uint32x4_t vmull_n_u16(uint16x4_t a, uint16_t b)
+ // argprep: a -> Vn.4H; b -> Vm.H[0]
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VMULL_N_U16; // UMULL Vd.4S,Vn.4H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // uint64x2_t vmull_n_u32(uint32x2_t a, uint32_t b)
+ // argprep: a -> Vn.2S; b -> Vm.S[0]
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VMULL_N_U32; // UMULL Vd.2D,Vn.2S,Vm.S[0]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VMULL_HIGH_N_U16; // UMULL2 Vd.4S,Vn.8H,Vm.H[0]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VMULL_HIGH_N_U32; // UMULL2 Vd.2D,Vn.4S,Vm.S[0]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // uint32x4_t vmull_u16(uint16x4_t a, uint16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VMULL_U16; // UMULL Vd.4S,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // uint64x2_t vmull_u32(uint32x2_t a, uint32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VMULL_U32; // UMULL Vd.2D,Vn.2S,Vm.2S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // uint16x8_t vmull_u8(uint8x8_t a, uint8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VMULL_U8; // UMULL Vd.8H,Vn.8B,Vm.8B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_UMULL_ASIMDELEM_L:
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VMULL_LANE_U16; // UMULL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VMULL_LANE_U32; // UMULL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VMULL_HIGH_LANE_U16; // UMULL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VMULL_HIGH_LANE_U32; // UMULL2 Vd.2D,Vn.4S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VMULL_LANEQ_U16; // UMULL Vd.4S,Vn.4H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VMULL_LANEQ_U32; // UMULL Vd.2D,Vn.2S,Vm.S[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // uint32x4_t vmull_high_laneq_u16(uint16x8_t a, uint16x8_t v, const int lane)
+ // argprep: a -> Vn.8H; v -> Vm.8H; lane -> <lane>
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VMULL_HIGH_LANEQ_U16; // UMULL2 Vd.4S,Vn.8H,Vm.H[lane]
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // uint64x2_t vmull_high_laneq_u32(uint32x4_t a, uint32x4_t v, const int lane)
+ // argprep: a -> Vn.4S; v -> Vm.4S; lane -> <lane>
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VMULL_HIGH_LANEQ_U32; // UMULL2 Vd.2D,Vn.4S,Vm.S[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed)
+ // uint32x4_t vmull_laneq_u16(uint16x4_t a, uint16x8_t v, const int lane)
+ // argprep: a -> Vn.4H; v -> Vm.8H; lane -> <lane>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VMULL_LANEQ_U16; // UMULL Vd.4S,Vn.4H,Vm.H[lane]
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_1SINGLE && instr.operands[2].laneUsed)
+ // uint64x2_t vmull_laneq_u32(uint32x2_t a, uint32x4_t v, const int lane)
+ // argprep: a -> Vn.2S; v -> Vm.4S; lane -> <lane>
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VMULL_LANEQ_U32; // UMULL Vd.2D,Vn.2S,Vm.S[lane]
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_input_lane(inputs, il, instr.operands[2]);
@@ -20001,17 +23775,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UQADD_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VQADD_U8; // UQADD Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VQADDQ_U8; // UQADD Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQADD_U16; // UQADD Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQADDQ_U16; // UQADD Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQADD_U32; // UQADD Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQADDQ_U32; // UQADD Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQADDQ_U64; // UQADD Vd.2D,Vn.2D,Vm.2D
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -20026,17 +23800,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UQRSHL_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VQRSHL_U8; // UQRSHL Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VQRSHLQ_U8; // UQRSHL Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQRSHL_U16; // UQRSHL Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQRSHLQ_U16; // UQRSHL Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQRSHL_U32; // UQRSHL Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQRSHLQ_U32; // UQRSHL Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQRSHLQ_U64; // UQRSHL Vd.2D,Vn.2D,Vm.2D
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -20049,24 +23823,56 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_UQRSHRN_ASIMDSHF_N:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VQRSHRN_N_U16; // UQRSHRN Vd.8B,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VQRSHRN_N_U32; // UQRSHRN Vd.4H,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VQRSHRN_N_U64; // UQRSHRN Vd.2S,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x16_t vqrshrn_high_n_u16(uint8x8_t r, uint16x8_t a, const int n)
+ // argprep: r -> Vd.8B; a -> Vn.8H; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VQRSHRN_HIGH_N_U16; // UQRSHRN2 Vd.16B,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x8_t vqrshrn_high_n_u32(uint16x4_t r, uint32x4_t a, const int n)
+ // argprep: r -> Vd.4H; a -> Vn.4S; n -> n
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VQRSHRN_HIGH_N_U32; // UQRSHRN2 Vd.8H,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x4_t vqrshrn_high_n_u64(uint32x2_t r, uint64x2_t a, const int n)
+ // argprep: r -> Vd.2S; a -> Vn.2D; n -> n
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VQRSHRN_HIGH_N_U64; // UQRSHRN2 Vd.4S,Vn.2D,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x8_t vqrshrn_n_u16(uint16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> n
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VQRSHRN_N_U16; // UQRSHRN Vd.8B,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x4_t vqrshrn_n_u32(uint32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> n
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VQRSHRN_N_U32; // UQRSHRN Vd.4H,Vn.4S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x2_t vqrshrn_n_u64(uint64x2_t a, const int n)
+ // argprep: a -> Vn.2D; n -> n
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VQRSHRN_N_U64; // UQRSHRN Vd.2S,Vn.2D,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_UQRSHRN_ASISDSHF_N:
- intrin_id = ARM64_INTRIN_VQRSHRNH_N_U16; // UQRSHRN Bd,Hn,#n
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32_t vqrshrnd_n_u64(uint64_t a, const int n)
+ // argprep: a -> Dn; n -> n
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VQRSHRND_N_U64; // UQRSHRN Sd,Dn,#n
+ else if ((instr.operands[0].reg[0] >= REG_B0 && instr.operands[0].reg[0] <= REG_B31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8_t vqrshrnh_n_u16(uint16_t a, const int n)
+ // argprep: a -> Hn; n -> n
+ // results: Bd -> result
+ intrin_id = ARM64_INTRIN_VQRSHRNH_N_U16; // UQRSHRN Bd,Hn,#n
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16_t vqrshrns_n_u32(uint32_t a, const int n)
+ // argprep: a -> Sn; n -> n
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VQRSHRNS_N_U32; // UQRSHRN Hd,Sn,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -20074,19 +23880,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UQSHL_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VQSHL_U8; // UQSHL Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VQSHLQ_U8; // UQSHL Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQSHL_U16; // UQSHL Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQSHLQ_U16; // UQSHL Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQSHL_U32; // UQSHL Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQSHLQ_U32; // UQSHL Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQSHLQ_U64; // UQSHL Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VQSHLQ_N_U8; // UQSHL Vd.16B,Vn.16B,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -20099,24 +23905,56 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_UQSHRN_ASIMDSHF_N:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VQSHRN_N_U16; // UQSHRN Vd.8B,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VQSHRN_N_U32; // UQSHRN Vd.4H,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VQSHRN_N_U64; // UQSHRN Vd.2S,Vn.2D,#n
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x16_t vqshrn_high_n_u16(uint8x8_t r, uint16x8_t a, const int n)
+ // argprep: r -> Vd.8B; a -> Vn.8H; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VQSHRN_HIGH_N_U16; // UQSHRN2 Vd.16B,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x8_t vqshrn_high_n_u32(uint16x4_t r, uint32x4_t a, const int n)
+ // argprep: r -> Vd.4H; a -> Vn.4S; n -> n
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VQSHRN_HIGH_N_U32; // UQSHRN2 Vd.8H,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x4_t vqshrn_high_n_u64(uint32x2_t r, uint64x2_t a, const int n)
+ // argprep: r -> Vd.2S; a -> Vn.2D; n -> n
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VQSHRN_HIGH_N_U64; // UQSHRN2 Vd.4S,Vn.2D,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x8_t vqshrn_n_u16(uint16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> n
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VQSHRN_N_U16; // UQSHRN Vd.8B,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x4_t vqshrn_n_u32(uint32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> n
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VQSHRN_N_U32; // UQSHRN Vd.4H,Vn.4S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x2_t vqshrn_n_u64(uint64x2_t a, const int n)
+ // argprep: a -> Vn.2D; n -> n
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VQSHRN_N_U64; // UQSHRN Vd.2S,Vn.2D,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_UQSHRN_ASISDSHF_N:
- intrin_id = ARM64_INTRIN_VQSHRNH_N_U16; // UQSHRN Bd,Hn,#n
+ if ((instr.operands[0].reg[0] >= REG_S0 && instr.operands[0].reg[0] <= REG_S31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32_t vqshrnd_n_u64(uint64_t a, const int n)
+ // argprep: a -> Dn; n -> n
+ // results: Sd -> result
+ intrin_id = ARM64_INTRIN_VQSHRND_N_U64; // UQSHRN Sd,Dn,#n
+ else if ((instr.operands[0].reg[0] >= REG_B0 && instr.operands[0].reg[0] <= REG_B31) && (instr.operands[1].reg[0] >= REG_H0 && instr.operands[1].reg[0] <= REG_H31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8_t vqshrnh_n_u16(uint16_t a, const int n)
+ // argprep: a -> Hn; n -> n
+ // results: Bd -> result
+ intrin_id = ARM64_INTRIN_VQSHRNH_N_U16; // UQSHRN Bd,Hn,#n
+ else if ((instr.operands[0].reg[0] >= REG_H0 && instr.operands[0].reg[0] <= REG_H31) && (instr.operands[1].reg[0] >= REG_S0 && instr.operands[1].reg[0] <= REG_S31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16_t vqshrns_n_u32(uint32_t a, const int n)
+ // argprep: a -> Sn; n -> n
+ // results: Hd -> result
+ intrin_id = ARM64_INTRIN_VQSHRNS_N_U32; // UQSHRN Hd,Sn,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -20124,17 +23962,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UQSUB_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VQSUB_U8; // UQSUB Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VQSUBQ_U8; // UQSUB Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VQSUB_U16; // UQSUB Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VQSUBQ_U16; // UQSUB Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VQSUB_U32; // UQSUB Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VQSUBQ_U32; // UQSUB Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VQSUBQ_U64; // UQSUB Vd.2D,Vn.2D,Vm.2D
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -20147,18 +23985,36 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_UQXTN_ASIMDMISC_N:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VQMOVN_U16; // UQXTN Vd.8B,Vn.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VQMOVN_U32; // UQXTN Vd.4H,Vn.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VQMOVN_U64; // UQXTN Vd.2S,Vn.2D
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint8x16_t vqmovn_high_u16(uint8x8_t r, uint16x8_t a)
+ // argprep: r -> Vd.8B; a -> Vn.8H
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VQMOVN_HIGH_U16; // UQXTN2 Vd.16B,Vn.8H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint16x8_t vqmovn_high_u32(uint16x4_t r, uint32x4_t a)
+ // argprep: r -> Vd.4H; a -> Vn.4S
+ // results: Vd.8H -> result
intrin_id = ARM64_INTRIN_VQMOVN_HIGH_U32; // UQXTN2 Vd.8H,Vn.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // uint32x4_t vqmovn_high_u64(uint32x2_t r, uint64x2_t a)
+ // argprep: r -> Vd.2S; a -> Vn.2D
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VQMOVN_HIGH_U64; // UQXTN2 Vd.4S,Vn.2D
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ // uint8x8_t vqmovn_u16(uint16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VQMOVN_U16; // UQXTN Vd.8B,Vn.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ // uint16x4_t vqmovn_u32(uint32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.4H -> result
+ intrin_id = ARM64_INTRIN_VQMOVN_U32; // UQXTN Vd.4H,Vn.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ // uint32x2_t vqmovn_u64(uint64x2_t a)
+ // argprep: a -> Vn.2D
+ // results: Vd.2S -> result
+ intrin_id = ARM64_INTRIN_VQMOVN_U64; // UQXTN Vd.2S,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
@@ -20170,7 +24026,7 @@ bool NeonGetLowLevelILForInstruction(
case ENC_URECPE_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRECPE_U32; // URECPE Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRECPEQ_U32; // URECPE Vd.4S,Vn.4S
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -20178,15 +24034,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_URHADD_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VRHADD_U8; // URHADD Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VRHADDQ_U8; // URHADD Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRHADD_U16; // URHADD Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRHADDQ_U16; // URHADD Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRHADD_U32; // URHADD Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRHADDQ_U32; // URHADD Vd.4S,Vn.4S,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -20195,17 +24051,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_URSHL_ASIMDSAME_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VRSHL_U8; // URSHL Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VRSHLQ_U8; // URSHL Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VRSHL_U16; // URSHL Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VRSHLQ_U16; // URSHL Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRSHL_U32; // URSHL Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRSHLQ_U32; // URSHL Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VRSHLQ_U64; // URSHL Vd.2D,Vn.2D,Vm.2D
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -20218,27 +24074,51 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_URSHR_ASIMDSHF_R:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VRSHR_N_U8; // URSHR Vd.8B,Vn.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x4_t vrshr_n_u16(uint16x4_t a, const int n)
+ // argprep: a -> Vn.4H; n -> n
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VRSHR_N_U16; // URSHR Vd.4H,Vn.4H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VRSHRQ_N_U16; // URSHR Vd.8H,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x2_t vrshr_n_u32(uint32x2_t a, const int n)
+ // argprep: a -> Vn.2S; n -> n
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VRSHR_N_U32; // URSHR Vd.2S,Vn.2S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x8_t vrshr_n_u8(uint8x8_t a, const int n)
+ // argprep: a -> Vn.8B; n -> n
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VRSHR_N_U8; // URSHR Vd.8B,Vn.8B,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x8_t vrshrq_n_u16(uint16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> n
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VRSHRQ_N_U16; // URSHR Vd.8H,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x4_t vrshrq_n_u32(uint32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> n
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VRSHRQ_N_U32; // URSHR Vd.4S,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint64x2_t vrshrq_n_u64(uint64x2_t a, const int n)
+ // argprep: a -> Vn.2D; n -> n
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VRSHRQ_N_U64; // URSHR Vd.2D,Vn.2D,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_URSHR_ASISDSHF_R:
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint64_t vrshrd_n_u64(uint64_t a, const int n)
+ // argprep: a -> Dn; n -> n
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VRSHRD_N_U64; // URSHR Dd,Dn,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x16_t vrshrq_n_u8(uint8x16_t a, const int n)
+ // argprep: a -> Vn.16B; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VRSHRQ_N_U8; // URSHR Vd.16B,Vn.16B,#n
- // if(None) intrin_id = ARM64_INTRIN_VRSHR_N_U64; // URSHR Dd,Dn,#n
- // if(None) intrin_id = ARM64_INTRIN_VRSHRD_N_U64; // URSHR Dd,Dn,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -20246,34 +24126,59 @@ bool NeonGetLowLevelILForInstruction(
case ENC_URSQRTE_ASIMDMISC_R:
if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VRSQRTE_U32; // URSQRTE Vd.2S,Vn.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VRSQRTEQ_U32; // URSQRTE Vd.4S,Vn.4S
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_URSRA_ASISDSHF_R:
case ENC_URSRA_ASIMDSHF_R:
- if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VRSRA_N_U8; // URSRA Vd.8B,Vn.8B,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x4_t vrsra_n_u16(uint16x4_t a, uint16x4_t b, const int n)
+ // argprep: a -> Vd.4H; b -> Vn.4H; n -> n
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VRSRA_N_U16; // URSRA Vd.4H,Vn.4H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VRSRAQ_N_U16; // URSRA Vd.8H,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x2_t vrsra_n_u32(uint32x2_t a, uint32x2_t b, const int n)
+ // argprep: a -> Vd.2S; b -> Vn.2S; n -> n
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VRSRA_N_U32; // URSRA Vd.2S,Vn.2S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x8_t vrsra_n_u8(uint8x8_t a, uint8x8_t b, const int n)
+ // argprep: a -> Vd.8B; b -> Vn.8B; n -> n
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VRSRA_N_U8; // URSRA Vd.8B,Vn.8B,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x8_t vrsraq_n_u16(uint16x8_t a, uint16x8_t b, const int n)
+ // argprep: a -> Vd.8H; b -> Vn.8H; n -> n
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VRSRAQ_N_U16; // URSRA Vd.8H,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x4_t vrsraq_n_u32(uint32x4_t a, uint32x4_t b, const int n)
+ // argprep: a -> Vd.4S; b -> Vn.4S; n -> n
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VRSRAQ_N_U32; // URSRA Vd.4S,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint64x2_t vrsraq_n_u64(uint64x2_t a, uint64x2_t b, const int n)
+ // argprep: a -> Vd.2D; b -> Vn.2D; n -> n
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VRSRAQ_N_U64; // URSRA Vd.2D,Vn.2D,#n
- add_input_reg(inputs, il, instr.operands[0]);
- add_input_reg(inputs, il, instr.operands[1]);
- add_input_imm(inputs, il, instr.operands[2]);
- add_output_reg(outputs, il, instr.operands[0]);
- break;
- case ENC_URSRA_ASISDSHF_R:
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ // add_input_reg(inputs, il, instr.operands[0]);
+ // add_input_reg(inputs, il, instr.operands[1]);
+ // add_input_imm(inputs, il, instr.operands[2]);
+ // add_output_reg(outputs, il, instr.operands[0]);
+ // break;
+ // case ENC_URSRA_ASISDSHF_R:
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint64_t vrsrad_n_u64(uint64_t a, uint64_t b, const int n)
+ // argprep: a -> Dd; b -> Dn; n -> n
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VRSRAD_N_U64; // URSRA Dd,Dn,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x16_t vrsraq_n_u8(uint8x16_t a, uint8x16_t b, const int n)
+ // argprep: a -> Vd.16B; b -> Vn.16B; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VRSRAQ_N_U8; // URSRA Vd.16B,Vn.16B,#n
- // if(None) intrin_id = ARM64_INTRIN_VRSRA_N_U64; // URSRA Dd,Dn,#n
- // if(None) intrin_id = ARM64_INTRIN_VRSRAD_N_U64; // URSRA Dd,Dn,#n
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
@@ -20282,11 +24187,11 @@ bool NeonGetLowLevelILForInstruction(
case ENC_USDOT_ASIMDELEM_D:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VUSDOT_LANE_S32; // USDOT Vd.2S,Vn.8B,Vm.4B[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VUSDOT_LANEQ_S32; // USDOT Vd.2S,Vn.8B,Vm.4B[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VUSDOTQ_LANE_S32; // USDOT Vd.4S,Vn.16B,Vm.4B[lane]
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VUSDOTQ_LANEQ_S32; // USDOT Vd.4S,Vn.16B,Vm.4B[lane]
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -20297,84 +24202,134 @@ bool NeonGetLowLevelILForInstruction(
case ENC_USDOT_ASIMDSAME2_D:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VUSDOT_S32; // USDOT Vd.2S,Vn.8B,Vm.8B
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VUSDOTQ_S32; // USDOT Vd.4S,Vn.16B,Vm.16B
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
+ case ENC_UXTL_USHLL_ASIMDSHF_L:
case ENC_USHLL_ASIMDSHF_L:
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSHLL_N_U8; // USHLL Vd.8H,Vn.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VSHLL_N_U16; // USHLL Vd.4S,Vn.4H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VSHLL_N_U32; // USHLL Vd.2D,Vn.2S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_U8; // USHLL2 Vd.8H,Vn.16B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_U16; // USHLL2 Vd.4S,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_U32; // USHLL2 Vd.2D,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VMOVL_U8; // USHLL Vd.8H,Vn.8B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VMOVL_U16; // USHLL Vd.4S,Vn.4H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VMOVL_U32; // USHLL Vd.2D,Vn.2S,#0
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VMOVL_HIGH_U8; // USHLL2 Vd.8H,Vn.16B,#0
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32x4_t vmovl_high_u16(uint16x8_t a)
+ // argprep: a -> Vn.8H
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VMOVL_HIGH_U16; // USHLL2 Vd.4S,Vn.8H,#0
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint64x2_t vmovl_high_u32(uint32x4_t a)
+ // argprep: a -> Vn.4S
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VMOVL_HIGH_U32; // USHLL2 Vd.2D,Vn.4S,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16x8_t vmovl_high_u8(uint8x16_t a)
+ // argprep: a -> Vn.16B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VMOVL_HIGH_U8; // USHLL2 Vd.8H,Vn.16B,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint32x4_t vmovl_u16(uint16x4_t a)
+ // argprep: a -> Vn.4H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VMOVL_U16; // USHLL Vd.4S,Vn.4H,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint64x2_t vmovl_u32(uint32x2_t a)
+ // argprep: a -> Vn.2S
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VMOVL_U32; // USHLL Vd.2D,Vn.2S,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32 && instr.operands[2].immediate == 0))
+ // uint16x8_t vmovl_u8(uint8x8_t a)
+ // argprep: a -> Vn.8B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VMOVL_U8; // USHLL Vd.8H,Vn.8B,#0
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x4_t vshll_high_n_u16(uint16x8_t a, const int n)
+ // argprep: a -> Vn.8H; n -> <n>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_U16; // USHLL2 Vd.4S,Vn.8H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint64x2_t vshll_high_n_u32(uint32x4_t a, const int n)
+ // argprep: a -> Vn.4S; n -> <n>
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_U32; // USHLL2 Vd.2D,Vn.4S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x8_t vshll_high_n_u8(uint8x16_t a, const int n)
+ // argprep: a -> Vn.16B; n -> <n>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VSHLL_HIGH_N_U8; // USHLL2 Vd.8H,Vn.16B,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint32x4_t vshll_n_u16(uint16x4_t a, const int n)
+ // argprep: a -> Vn.4H; n -> <n>
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VSHLL_N_U16; // USHLL Vd.4S,Vn.4H,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint64x2_t vshll_n_u32(uint32x2_t a, const int n)
+ // argprep: a -> Vn.2S; n -> <n>
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VSHLL_N_U32; // USHLL Vd.2D,Vn.2S,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint16x8_t vshll_n_u8(uint8x8_t a, const int n)
+ // argprep: a -> Vn.8B; n -> <n>
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VSHLL_N_U8; // USHLL Vd.8H,Vn.8B,#n
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_USHL_ASIMDSAME_ONLY:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VSHL_U8; // USHL Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
- intrin_id = ARM64_INTRIN_VSHLQ_U8; // USHL Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // uint16x4_t vshl_u16(uint16x4_t a, int16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4H -> result
intrin_id = ARM64_INTRIN_VSHL_U16; // USHL Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSHLQ_U16; // USHL Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // uint32x2_t vshl_u32(uint32x2_t a, int32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2S -> result
intrin_id = ARM64_INTRIN_VSHL_U32; // USHL Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // uint8x8_t vshl_u8(uint8x8_t a, int8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8B -> result
+ intrin_id = ARM64_INTRIN_VSHL_U8; // USHL Vd.8B,Vn.8B,Vm.8B
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint16x8_t vshlq_u16(uint16x8_t a, int16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VSHLQ_U16; // USHL Vd.8H,Vn.8H,Vm.8H
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint32x4_t vshlq_u32(uint32x4_t a, int32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VSHLQ_U32; // USHL Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2DOUBLES && instr.operands[2].arrSpec == ARRSPEC_2DOUBLES)
+ // uint64x2_t vshlq_u64(uint64x2_t a, int64x2_t b)
+ // argprep: a -> Vn.2D; b -> Vm.2D
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VSHLQ_U64; // USHL Vd.2D,Vn.2D,Vm.2D
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // uint8x16_t vshlq_u8(uint8x16_t a, int8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.16B -> result
+ intrin_id = ARM64_INTRIN_VSHLQ_U8; // USHL Vd.16B,Vn.16B,Vm.16B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_USHL_ASISDSAME_ONLY:
- intrin_id = ARM64_INTRIN_VSHL_U64; // USHL Dd,Dn,Dm
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].reg[0] >= REG_D0 && instr.operands[2].reg[0] <= REG_D31))
+ // uint64x1_t vshl_u64(uint64x1_t a, int64x1_t b)
+ // argprep: a -> Dn; b -> Dm
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VSHL_U64; // USHL Dd,Dn,Dm
+ else if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].reg[0] >= REG_D0 && instr.operands[2].reg[0] <= REG_D31))
+ // uint64_t vshld_u64(uint64_t a, int64_t b)
+ // argprep: a -> Dn; b -> Dm
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VSHLD_U64; // USHL Dd,Dn,Dm
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
- case ENC_USHR_ASIMDSHF_R:
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
- intrin_id = ARM64_INTRIN_VSHR_N_U8; // USHR Vd.8B,Vn.8B,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
- intrin_id = ARM64_INTRIN_VSHR_N_U16; // USHR Vd.4H,Vn.4H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSHRQ_N_U16; // USHR Vd.8H,Vn.8H,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
- intrin_id = ARM64_INTRIN_VSHR_N_U32; // USHR Vd.2S,Vn.2S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VSHRQ_N_U32; // USHR Vd.4S,Vn.4S,#n
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VSHRQ_N_U64; // USHR Vd.2D,Vn.2D,#n
- add_input_reg(inputs, il, instr.operands[1]);
- add_input_imm(inputs, il, instr.operands[2]);
- add_output_reg(outputs, il, instr.operands[0]);
- break;
case ENC_USHR_ASISDSHF_R:
if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VSHRQ_N_U8; // USHR Vd.16B,Vn.16B,#n
@@ -20394,17 +24349,17 @@ bool NeonGetLowLevelILForInstruction(
case ENC_USQADD_ASIMDMISC_R:
if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VSQADD_U8; // USQADD Vd.8B,Vn.8B
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VSQADDQ_U8; // USQADD Vd.16B,Vn.16B
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VSQADD_U16; // USQADD Vd.4H,Vn.4H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSQADDQ_U16; // USQADD Vd.8H,Vn.8H
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VSQADD_U32; // USQADD Vd.2S,Vn.2S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSQADDQ_U32; // USQADD Vd.4S,Vn.4S
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSQADDQ_U64; // USQADD Vd.2D,Vn.2D
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -20419,15 +24374,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_USRA_ASIMDSHF_R:
if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VSRA_N_U8; // USRA Vd.8B,Vn.8B,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VSRA_N_U16; // USRA Vd.4H,Vn.4H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSRAQ_N_U16; // USRA Vd.8H,Vn.8H,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VSRA_N_U32; // USRA Vd.2S,Vn.2S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSRAQ_N_U32; // USRA Vd.4S,Vn.4S,#n
- if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSRAQ_N_U64; // USRA Vd.2D,Vn.2D,#n
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -20435,28 +24390,52 @@ bool NeonGetLowLevelILForInstruction(
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_USRA_ASISDSHF_R:
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ if ((instr.operands[0].reg[0] >= REG_D0 && instr.operands[0].reg[0] <= REG_D31) && (instr.operands[1].reg[0] >= REG_D0 && instr.operands[1].reg[0] <= REG_D31) && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint64_t vsrad_n_u64(uint64_t a, uint64_t b, const int n)
+ // argprep: a -> Dd; b -> Dn; n -> n
+ // results: Dd -> result
+ intrin_id = ARM64_INTRIN_VSRAD_N_U64; // USRA Dd,Dn,#n
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && (instr.operands[2].operandClass && instr.operands[2].operandClass <= FIMM32))
+ // uint8x16_t vsraq_n_u8(uint8x16_t a, uint8x16_t b, const int n)
+ // argprep: a -> Vd.16B; b -> Vn.16B; n -> n
+ // results: Vd.16B -> result
intrin_id = ARM64_INTRIN_VSRAQ_N_U8; // USRA Vd.16B,Vn.16B,#n
- // if(None) intrin_id = ARM64_INTRIN_VSRA_N_U64; // USRA Dd,Dn,#n
- // if(None) intrin_id = ARM64_INTRIN_VSRAD_N_U64; // USRA Dd,Dn,#n
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
add_input_imm(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
break;
case ENC_USUBL_ASIMDDIFF_L:
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSUBL_U8; // USUBL Vd.8H,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
- intrin_id = ARM64_INTRIN_VSUBL_U16; // USUBL Vd.4S,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
- intrin_id = ARM64_INTRIN_VSUBL_U32; // USUBL Vd.2D,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
- intrin_id = ARM64_INTRIN_VSUBL_HIGH_U8; // USUBL2 Vd.8H,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_8HALVES && instr.operands[2].arrSpec == ARRSPEC_8HALVES)
+ // uint32x4_t vsubl_high_u16(uint16x8_t a, uint16x8_t b)
+ // argprep: a -> Vn.8H; b -> Vm.8H
+ // results: Vd.4S -> result
intrin_id = ARM64_INTRIN_VSUBL_HIGH_U16; // USUBL2 Vd.4S,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_4SINGLES && instr.operands[2].arrSpec == ARRSPEC_4SINGLES)
+ // uint64x2_t vsubl_high_u32(uint32x4_t a, uint32x4_t b)
+ // argprep: a -> Vn.4S; b -> Vm.4S
+ // results: Vd.2D -> result
intrin_id = ARM64_INTRIN_VSUBL_HIGH_U32; // USUBL2 Vd.2D,Vn.4S,Vm.4S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_16BYTES && instr.operands[2].arrSpec == ARRSPEC_16BYTES)
+ // uint16x8_t vsubl_high_u8(uint8x16_t a, uint8x16_t b)
+ // argprep: a -> Vn.16B; b -> Vm.16B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VSUBL_HIGH_U8; // USUBL2 Vd.8H,Vn.16B,Vm.16B
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_4HALVES)
+ // uint32x4_t vsubl_u16(uint16x4_t a, uint16x4_t b)
+ // argprep: a -> Vn.4H; b -> Vm.4H
+ // results: Vd.4S -> result
+ intrin_id = ARM64_INTRIN_VSUBL_U16; // USUBL Vd.4S,Vn.4H,Vm.4H
+ else if (instr.operands[0].arrSpec == ARRSPEC_2DOUBLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES)
+ // uint64x2_t vsubl_u32(uint32x2_t a, uint32x2_t b)
+ // argprep: a -> Vn.2S; b -> Vm.2S
+ // results: Vd.2D -> result
+ intrin_id = ARM64_INTRIN_VSUBL_U32; // USUBL Vd.2D,Vn.2S,Vm.2S
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES && instr.operands[1].arrSpec == ARRSPEC_8BYTES && instr.operands[2].arrSpec == ARRSPEC_8BYTES)
+ // uint16x8_t vsubl_u8(uint8x8_t a, uint8x8_t b)
+ // argprep: a -> Vn.8B; b -> Vm.8B
+ // results: Vd.8H -> result
+ intrin_id = ARM64_INTRIN_VSUBL_U8; // USUBL Vd.8H,Vn.8B,Vm.8B
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -20464,15 +24443,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_USUBW_ASIMDDIFF_W:
if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSUBW_U8; // USUBW Vd.8H,Vn.8H,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSUBW_U16; // USUBW Vd.4S,Vn.4S,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSUBW_U32; // USUBW Vd.2D,Vn.2D,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VSUBW_HIGH_U8; // USUBW2 Vd.8H,Vn.8H,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VSUBW_HIGH_U16; // USUBW2 Vd.4S,Vn.4S,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VSUBW_HIGH_U32; // USUBW2 Vd.2D,Vn.2D,Vm.4S
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -20481,51 +24460,51 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UZP1_ASIMDPERM_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VUZP1_S8; // UZP1 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VUZP1Q_S8; // UZP1 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VUZP1_S16; // UZP1 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VUZP1Q_S16; // UZP1 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VUZP1_S32; // UZP1 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VUZP1Q_S32; // UZP1 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VUZP1Q_S64; // UZP1 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VUZP1_U8; // UZP1 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VUZP1Q_U8; // UZP1 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VUZP1_U16; // UZP1 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VUZP1Q_U16; // UZP1 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VUZP1_U32; // UZP1 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VUZP1Q_U32; // UZP1 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VUZP1Q_U64; // UZP1 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VUZP1Q_P64; // UZP1 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VUZP1_F32; // UZP1 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VUZP1Q_F32; // UZP1 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VUZP1Q_F64; // UZP1 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VUZP1_P8; // UZP1 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VUZP1Q_P8; // UZP1 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VUZP1_P16; // UZP1 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VUZP1Q_P16; // UZP1 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VUZP1_F16; // UZP1 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VUZP1Q_F16; // UZP1 Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -20534,51 +24513,51 @@ bool NeonGetLowLevelILForInstruction(
case ENC_UZP2_ASIMDPERM_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VUZP2_S8; // UZP2 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VUZP2Q_S8; // UZP2 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VUZP2_S16; // UZP2 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VUZP2Q_S16; // UZP2 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VUZP2_S32; // UZP2 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VUZP2Q_S32; // UZP2 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VUZP2Q_S64; // UZP2 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VUZP2_U8; // UZP2 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VUZP2Q_U8; // UZP2 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VUZP2_U16; // UZP2 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VUZP2Q_U16; // UZP2 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VUZP2_U32; // UZP2 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VUZP2Q_U32; // UZP2 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VUZP2Q_U64; // UZP2 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VUZP2Q_P64; // UZP2 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VUZP2_F32; // UZP2 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VUZP2Q_F32; // UZP2 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VUZP2Q_F64; // UZP2 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VUZP2_P8; // UZP2 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VUZP2Q_P8; // UZP2 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VUZP2_P16; // UZP2 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VUZP2Q_P16; // UZP2 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VUZP2_F16; // UZP2 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VUZP2Q_F16; // UZP2 Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -20594,28 +24573,28 @@ bool NeonGetLowLevelILForInstruction(
case ENC_XTN_ASIMDMISC_N:
if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMOVN_S16; // XTN Vd.8B,Vn.8H
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMOVN_S32; // XTN Vd.4H,Vn.4S
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMOVN_S64; // XTN Vd.2S,Vn.2D
- if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VMOVN_U16; // XTN Vd.8B,Vn.8H
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VMOVN_U32; // XTN Vd.4H,Vn.4S
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VMOVN_U64; // XTN Vd.2S,Vn.2D
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMOVN_HIGH_S16; // XTN2 Vd.16B,Vn.8H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMOVN_HIGH_S32; // XTN2 Vd.8H,Vn.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMOVN_HIGH_S64; // XTN2 Vd.4S,Vn.2D
- if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VMOVN_HIGH_U16; // XTN2 Vd.16B,Vn.8H
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VMOVN_HIGH_U32; // XTN2 Vd.8H,Vn.4S
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VMOVN_HIGH_U64; // XTN2 Vd.4S,Vn.2D
add_input_reg(inputs, il, instr.operands[1]);
add_output_reg(outputs, il, instr.operands[0]);
@@ -20623,51 +24602,51 @@ bool NeonGetLowLevelILForInstruction(
case ENC_ZIP1_ASIMDPERM_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VZIP1_S8; // ZIP1 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VZIP1Q_S8; // ZIP1 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VZIP1_S16; // ZIP1 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VZIP1Q_S16; // ZIP1 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VZIP1_S32; // ZIP1 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VZIP1Q_S32; // ZIP1 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VZIP1Q_S64; // ZIP1 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VZIP1_U8; // ZIP1 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VZIP1Q_U8; // ZIP1 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VZIP1_U16; // ZIP1 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VZIP1Q_U16; // ZIP1 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VZIP1_U32; // ZIP1 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VZIP1Q_U32; // ZIP1 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VZIP1Q_U64; // ZIP1 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VZIP1Q_P64; // ZIP1 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VZIP1_F32; // ZIP1 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VZIP1Q_F32; // ZIP1 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VZIP1Q_F64; // ZIP1 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VZIP1_P8; // ZIP1 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VZIP1Q_P8; // ZIP1 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VZIP1_P16; // ZIP1 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VZIP1Q_P16; // ZIP1 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VZIP1_F16; // ZIP1 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VZIP1Q_F16; // ZIP1 Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -20676,51 +24655,51 @@ bool NeonGetLowLevelILForInstruction(
case ENC_ZIP2_ASIMDPERM_ONLY:
if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VZIP2_S8; // ZIP2 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VZIP2Q_S8; // ZIP2 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VZIP2_S16; // ZIP2 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VZIP2Q_S16; // ZIP2 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VZIP2_S32; // ZIP2 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VZIP2Q_S32; // ZIP2 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VZIP2Q_S64; // ZIP2 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VZIP2_U8; // ZIP2 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VZIP2Q_U8; // ZIP2 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VZIP2_U16; // ZIP2 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VZIP2Q_U16; // ZIP2 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VZIP2_U32; // ZIP2 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VZIP2Q_U32; // ZIP2 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VZIP2Q_U64; // ZIP2 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VZIP2Q_P64; // ZIP2 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VZIP2_F32; // ZIP2 Vd.2S,Vn.2S,Vm.2S
- if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VZIP2Q_F32; // ZIP2 Vd.4S,Vn.4S,Vm.4S
- if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_2DOUBLES)
intrin_id = ARM64_INTRIN_VZIP2Q_F64; // ZIP2 Vd.2D,Vn.2D,Vm.2D
- if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8BYTES)
intrin_id = ARM64_INTRIN_VZIP2_P8; // ZIP2 Vd.8B,Vn.8B,Vm.8B
- if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_16BYTES)
intrin_id = ARM64_INTRIN_VZIP2Q_P8; // ZIP2 Vd.16B,Vn.16B,Vm.16B
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VZIP2_P16; // ZIP2 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VZIP2Q_P16; // ZIP2 Vd.8H,Vn.8H,Vm.8H
- if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VZIP2_F16; // ZIP2 Vd.4H,Vn.4H,Vm.4H
- if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[1].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VZIP2Q_F16; // ZIP2 Vd.8H,Vn.8H,Vm.8H
add_input_reg(inputs, il, instr.operands[1]);
add_input_reg(inputs, il, instr.operands[2]);
@@ -20755,19 +24734,19 @@ bool NeonGetLowLevelILForInstruction(
case ENC_FCMLA_Z_ZZZI_H:
if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCMLA_ROT180_LANE_F16; // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#180
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCMLA_ROT180_LANEQ_F16; // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#180
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VCMLAQ_ROT180_LANE_F16; // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#180
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VCMLAQ_ROT180_LANEQ_F16; // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#180
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCMLA_ROT270_LANE_F16; // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#270
- if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4HALVES)
intrin_id = ARM64_INTRIN_VCMLA_ROT270_LANEQ_F16; // FCMLA Vd.4H,Vn.4H,Vm.H[lane],#270
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VCMLAQ_ROT270_LANE_F16; // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#270
- if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_8HALVES)
intrin_id = ARM64_INTRIN_VCMLAQ_ROT270_LANEQ_F16; // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#270
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
@@ -20778,15 +24757,15 @@ bool NeonGetLowLevelILForInstruction(
case ENC_FCMLA_Z_ZZZI_S:
if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VCMLA_ROT180_LANE_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#180
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VCMLAQ_ROT180_LANE_F32; // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#180
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VCMLAQ_ROT180_LANEQ_F32; // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#180
- if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES)
intrin_id = ARM64_INTRIN_VCMLA_ROT270_LANE_F32; // FCMLA Vd.2S,Vn.2S,Vm.2S[lane],#270
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VCMLAQ_ROT270_LANE_F32; // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#270
- if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
+ else if (instr.operands[0].arrSpec == ARRSPEC_4SINGLES)
intrin_id = ARM64_INTRIN_VCMLAQ_ROT270_LANEQ_F32; // FCMLA Vd.4S,Vn.4S,Vm.S[lane],#270
add_input_reg(inputs, il, instr.operands[0]);
add_input_reg(inputs, il, instr.operands[1]);
diff --git a/arch/arm64/neon_intrinsics.h b/arch/arm64/neon_intrinsics.h
index e2dd9616..087b8664 100644
--- a/arch/arm64/neon_intrinsics.h
+++ b/arch/arm64/neon_intrinsics.h
@@ -3926,6 +3926,63 @@ enum NeonIntrinsic : uint32_t
ARM64_INTRIN_VBFMLALBQ_LANEQ_F32,
ARM64_INTRIN_VBFMLALTQ_LANE_F32,
ARM64_INTRIN_VBFMLALTQ_LANEQ_F32,
+ // Added to resolve collisions between vector and scalar variants of the intrinsic
+ ARM64_INTRIN_VMAX__F32,
+ ARM64_INTRIN_VMAXNM__F32,
+ // Added to fill in obvious gaps
+ ARM64_INTRIN_VCVTNS_S64_F32,
+ ARM64_INTRIN_VCVTN_S32_F64,
+ ARM64_INTRIN_VCVTD_N_F64_S32,
+ ARM64_INTRIN_VCVTS_N_F32_S64,
+ ARM64_INTRIN_VCVT_S32_F64,
+ ARM64_INTRIN_VCVT_U32_F64,
+ ARM64_INTRIN_VCVTA_S32_F64,
+ ARM64_INTRIN_VCVTA_U32_F64,
+ ARM64_INTRIN_VCVTAD_S32_F64,
+ ARM64_INTRIN_VCVTAD_U32_F64,
+ ARM64_INTRIN_VCVTAS_N_S32_F32,
+ ARM64_INTRIN_VCVTAS_N_U32_F32,
+ ARM64_INTRIN_VCVTD_S32_F64,
+ ARM64_INTRIN_VCVTD_U32_F64,
+ ARM64_INTRIN_VCVTM_S32_F64,
+ ARM64_INTRIN_VCVTM_U32_F64,
+ ARM64_INTRIN_VCVTMD_S32_F64,
+ ARM64_INTRIN_VCVTMD_U32_F64,
+ ARM64_INTRIN_VCVTMS_N_S32_F32,
+ ARM64_INTRIN_VCVTMS_N_U32_F32,
+ ARM64_INTRIN_VCVTN_U32_F64,
+ ARM64_INTRIN_VCVTND_S32_F64,
+ ARM64_INTRIN_VCVTND_U32_F64,
+ ARM64_INTRIN_VCVTP_S32_F64,
+ ARM64_INTRIN_VCVTP_U32_F64,
+ ARM64_INTRIN_VCVTPD_S32_F64,
+ ARM64_INTRIN_VCVTPD_U32_F64,
+ ARM64_INTRIN_VCVTPS_N_S32_F32,
+ ARM64_INTRIN_VCVTPS_N_U32_F32,
+ ARM64_INTRIN_VCVTA_N_S64_F64,
+ ARM64_INTRIN_VCVTA_N_U64_F64,
+ ARM64_INTRIN_VCVTAD_N_S64_F64,
+ ARM64_INTRIN_VCVTAD_N_U64_F64,
+ ARM64_INTRIN_VCVTM_N_S64_F64,
+ ARM64_INTRIN_VCVTM_N_U64_F64,
+ ARM64_INTRIN_VCVTMD_N_S64_F64,
+ ARM64_INTRIN_VCVTMD_N_U64_F64,
+ ARM64_INTRIN_VCVTP_N_S64_F64,
+ ARM64_INTRIN_VCVTP_N_U64_F64,
+ ARM64_INTRIN_VCVTPD_N_S64_F64,
+ ARM64_INTRIN_VCVTPD_N_U64_F64,
+ ARM64_INTRIN_VCVTNS_U64_F32,
+ ARM64_INTRIN_VCVTPS_U64_F32,
+ ARM64_INTRIN_VCVTPS_S64_F32,
+ ARM64_INTRIN_VCVTS_S64_F32,
+ ARM64_INTRIN_VCVTS_U64_F32,
+ ARM64_INTRIN_VCVTD_N_U64_F32,
+ ARM64_INTRIN_VCVTD_N_U32_F64,
+ ARM64_INTRIN_VCVTS_N_U64_F32,
+ ARM64_INTRIN_VCVTS_N_U32_F64,
+ ARM64_INTRIN_VCVTS_N_U64_F64,
+ ARM64_INTRIN_VCVT_U64_F32,
+ // The end, add more above
ARM64_INTRIN_NEON_END
};
diff --git a/arch/arm64/test_gen.py b/arch/arm64/test_gen.py
index ebbe7c45..9c07fdea 100755
--- a/arch/arm64/test_gen.py
+++ b/arch/arm64/test_gen.py
@@ -5,9 +5,9 @@
import re, sys, codecs
-N_SAMPLES = 8 # number of samples for each encoding
+N_SAMPLES = 4 # number of samples for each encoding
-from arm64test import lift
+from arm64test import lift, ATTR_PTR_AUTH, path_il_h
if not sys.argv[1:]:
sys.exit(-1)
@@ -28,15 +28,26 @@ def disassemble(addr, data):
def print_case(data, comment=""):
ilstr, attributes = lift(data)
il_lines = ilstr.split(";")
- print("\t(b'%s', " % ("".join(["\\x%02X" % b for b in data])), end="")
+ if len(il_lines) == 2 and len(ilstr) < 60:
+ il_lines = [ilstr]
+ # print("\t(b'%s', " % ("".join(["\\x%02X" % b for b in data])), end="")
+ print(" (b'%s', " % ("".join(["\\x%02X" % b for b in data])), end="")
for i, line in enumerate(il_lines):
if i != 0:
- print("\t\t\t\t\t\t ", end="")
+ # print("\t\t\t\t\t\t ", end="")
+ print(" " * (4 * 6 + 1), end="")
print("'%s" % line, end="")
if i != len(il_lines) - 1:
print(";' + \\")
+ # comment = comment or ""
+ # comment += " %s" % len(il_lines)
comment = " # " + comment if comment else ""
- print("'),%s" % comment)
+ attr = ''
+ if attributes:
+ # attr = ", \"%s\"" % repr(list(attributes)[0])
+ if ATTR_PTR_AUTH in attributes:
+ attr = ", ATTR_PTR_AUTH"
+ print("'%s),%s" % (attr, comment))
def gather_samples(mnems, encodings):
@@ -44,43 +55,50 @@ def gather_samples(mnems, encodings):
global N_SAMPLES
fpath = "./disassembler/test_cases.txt"
- with open(fpath) as fp:
- lines = fp.readlines()
+ with open(fpath, "rt") as fp:
+ lines_read = fp.read()
mnems = [re.compile(x, re.IGNORECASE) for x in mnems]
samples = 0
current_encoding = None
- for line in lines:
- if line.startswith("// NOTE:"):
+ # not_sample_line_pat = re.compile(r"^// (\w*) .*", re.IGNORECASE)
+ encoding_line_pat = re.compile(r"^// (\w*_\w*?) .*", re.IGNORECASE)
+ # sample_line_pat = re.compile(r"^(..)(..)(..)(..) (.*)$")
+ sample_line_pat = re.compile(r"^([\dA-F]{2})([\dA-F]{2})([\dA-F]{2})([\dA-F]{2}) (.*)$", re.IGNORECASE)
+ for i, line in enumerate(lines_read.splitlines()):
+ _line = line.strip().upper()
+ if _line.startswith("// NOTE:"):
continue
- if line.startswith("// SYNTAX:"):
+ if _line.startswith("// SYNTAX:"):
continue
- if line.startswith("// https:"):
+ if _line.startswith("// https:"):
continue
- if line.startswith(
- "// 1101010100|L=0|OP0=00|OP1=011|CRN=0011|CRM=0100|1|OPC=00|RT=11111"
- ):
+ if _line.startswith("// HTTPS:"):
continue
- if line.strip().endswith("// TCOMMIT"):
+ if _line.startswith("// 1101010100|L=0|OP0=00|OP1=011|CRN=0011|CRM=0100|1|OPC=00|RT=11111"):
continue
- if line.strip().endswith("// DRPS"):
+ if _line.endswith("// TCOMMIT"):
continue
- if line.strip().endswith("// ERET"):
+ if _line.endswith("// DRPS"):
continue
- if line.strip().endswith("// ERETAA"):
+ if _line.endswith("// ERET"):
continue
- if line.strip().endswith("// ERETAB"):
+ if _line.endswith("// ERETAA"):
continue
- if line.strip().endswith("// PSSBB"):
+ if _line.endswith("// ERETAB"):
continue
- if line.strip().endswith("// SSBB"):
+ if _line.endswith("// PSSBB"):
continue
- if line.strip().endswith("// PSSBB_DSB_BO_BARRIERS"):
+ if _line.endswith("// SSBB"):
+ continue
+ if _line.endswith("// PSSBB_DSB_BO_BARRIERS"):
continue
- if re.match(r"^// .*? .*", line):
- m = re.match(r"^// (.*?) .*", line)
+ # if re.match(r"^// .*? .*", line):
+ m = encoding_line_pat.match(line)
+ if m:
+ # m = re.match(r"^// (.*?) .*", line)
# example:
# // BFCVT_Z_P_Z_S2BF 01100101|opc=10|0010|opc2=10|101|Pg=xxx|Zn=xxxxx|Zd=xxxxx
@@ -88,7 +106,13 @@ def gather_samples(mnems, encodings):
samples = 0
continue
- m = re.match(r"^(..)(..)(..)(..) (.*)$", line)
+ # if not_sample_line_pat.match(line):
+ # continue
+ if line.startswith("//"):
+ continue
+
+ # m = re.match(r"^(..)(..)(..)(..) (.*)$", line)
+ m = sample_line_pat.match(line)
if m:
# example:
# 658AB9BB bfcvt z27.h, p6/m, z13.s
@@ -108,13 +132,14 @@ def gather_samples(mnems, encodings):
# if samples == 0:
# print('\t# %s' % encoding)
- print("\t# %s %s" % (instxt.ljust(64), current_encoding))
+ # print("\t# %s %s" % (instxt.ljust(64), current_encoding))
+ print(" # %s %s" % (instxt.ljust(64), current_encoding))
print_case(data)
samples += 1
continue
- print("unable to parse line: %r" % line)
+ print("unable to parse line (%d): %r" % (i + 1, line))
sys.exit(-1)
@@ -164,8 +189,33 @@ elif sys.argv[1] == "recompute_arm64test":
lines = [x.rstrip() for x in fp.readlines()]
i = 0
+ preserve = False
+ with open(path_il_h, "rt") as f:
+ LIFT_PAC_AS_INTRINSIC = "'#define LIFT_PAC_AS_INTRINSIC 1\n'" in f.readlines()
+ # print(f"{LIFT_PAC_AS_INTRINSIC=!r}", file=sys.stdout)
while i < len(lines):
- m = re.match(r"^\t\(b\'\\x(..)\\x(..)\\x(..)\\x(..)\'.*$", lines[i])
+ if "testing that select PAC instructions lift to " in lines[i]:
+ if "testing that select PAC instructions lift to intrinsics" in lines[i]:
+ preserve = not LIFT_PAC_AS_INTRINSIC
+ elif "testing that select PAC instructions lift to NOP" in lines[i]:
+ preserve = LIFT_PAC_AS_INTRINSIC
+ # print(f"{LIFT_PAC_AS_INTRINSIC=!r} {preserve=!r}", file=sys.stdout)
+ if preserve:
+ print(lines[i])
+ i += 1
+ continue
+ m = re.match(r"^(?:\t| {4})\(b\'\\x(..)\\x(..)\\x(..)\\x(..)\'.*$", lines[i])
+ if m:
+ while i + 1 < len(lines) and re.match(r"^\s+\'.*$", lines[i + 1]):
+ lines[i] += lines[i + 1]
+ del lines[i + 1]
+ # if i + 1 < len(lines):
+ # if re.match(r"^\s+\'.*$", lines[i + 1]):
+ # while i + 1 < len(lines) and re.match(r"^\s+\'.*$", lines[i + 1]):
+ # lines[i] += lines[i + 1]
+ # del lines[i + 1]
+
+ # m = re.match(r"^(?:\t| {4})\(b\'\\x(..)\\x(..)\\x(..)\\x(..)\'.*($\n^.*)*?$\n(?=^ {4}\(b)", lines[i], re.M)
if not m:
print(lines[i])
i += 1
@@ -182,5 +232,5 @@ elif sys.argv[1] == "recompute_arm64test":
print_case(data, comment)
i += 1
- while lines[i].startswith("\t\t\t\t\t\t"):
+ while lines[i].startswith("\t\t\t\t\t\t") or lines[i].startswith(" " * (4 * 6)):
i += 1