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-rw-r--r--rust/src/architecture.rs2
-rw-r--r--rust/src/llil/function.rs2
-rw-r--r--rust/src/llil/instruction.rs2
-rw-r--r--rust/src/llil/lifting.rs4
-rw-r--r--rust/src/llil/operation.rs8
5 files changed, 9 insertions, 9 deletions
diff --git a/rust/src/architecture.rs b/rust/src/architecture.rs
index edc16209..9b5af6ee 100644
--- a/rust/src/architecture.rs
+++ b/rust/src/architecture.rs
@@ -1472,7 +1472,7 @@ impl Architecture for CoreArchitecture {
if res {
Ok(result.get_data().to_vec())
} else {
- Err(error.unwrap_or("Assemble failed".into()))
+ Err(error.unwrap_or_else(|| "Assemble failed".into()))
}
}
diff --git a/rust/src/llil/function.rs b/rust/src/llil/function.rs
index 20d2cb04..6d561731 100644
--- a/rust/src/llil/function.rs
+++ b/rust/src/llil/function.rs
@@ -103,7 +103,7 @@ where
use binaryninjacore_sys::BNLowLevelILGetInstructionStart;
let loc: Location = loc.into();
- let arch_handle = loc.arch.unwrap_or(*self.arch().as_ref());
+ let arch_handle = loc.arch.unwrap_or_else(|| *self.arch().as_ref());
unsafe {
let instr_idx = BNLowLevelILGetInstructionStart(self.handle, arch_handle.0, loc.addr);
diff --git a/rust/src/llil/instruction.rs b/rust/src/llil/instruction.rs
index 36733472..ab02b175 100644
--- a/rust/src/llil/instruction.rs
+++ b/rust/src/llil/instruction.rs
@@ -115,7 +115,7 @@ where
LLIL_SYSCALL => InstrInfo::Syscall(Operation::new(self.function, op)),
LLIL_INTRINSIC => InstrInfo::Intrinsic(Operation::new(self.function, op)),
_ => {
- common_info(self.function, op).unwrap_or({
+ common_info(self.function, op).unwrap_or_else(|| {
// Hopefully this is a bare value. If it isn't (expression
// from wrong function form or similar) it won't really cause
// any problems as it'll come back as undefined when queried.
diff --git a/rust/src/llil/lifting.rs b/rust/src/llil/lifting.rs
index bd023933..f40f9529 100644
--- a/rust/src/llil/lifting.rs
+++ b/rust/src/llil/lifting.rs
@@ -1380,7 +1380,7 @@ where
use binaryninjacore_sys::BNLowLevelILSetCurrentAddress;
let loc: Location = loc.into();
- let arch = loc.arch.unwrap_or(*self.arch().as_ref());
+ let arch = loc.arch.unwrap_or_else(|| *self.arch().as_ref());
unsafe {
BNLowLevelILSetCurrentAddress(self.handle, arch.0, loc.addr);
@@ -1391,7 +1391,7 @@ where
use binaryninjacore_sys::BNGetLowLevelILLabelForAddress;
let loc: Location = loc.into();
- let arch = loc.arch.unwrap_or(*self.arch().as_ref());
+ let arch = loc.arch.unwrap_or_else(|| *self.arch().as_ref());
let res = unsafe { BNGetLowLevelILLabelForAddress(self.handle, arch.0, loc.addr) };
diff --git a/rust/src/llil/operation.rs b/rust/src/llil/operation.rs
index 4daa7cb2..f90fafd8 100644
--- a/rust/src/llil/operation.rs
+++ b/rust/src/llil/operation.rs
@@ -124,7 +124,7 @@ where
.arch()
.register_from_id(raw_id)
.map(Register::ArchReg)
- .unwrap_or({
+ .unwrap_or_else(|| {
error!(
"got garbage register from LLIL_SET_REG @ 0x{:x}",
self.op.address
@@ -163,7 +163,7 @@ where
.arch()
.register_from_id(raw_id)
.map(Register::ArchReg)
- .unwrap_or({
+ .unwrap_or_else(|| {
error!(
"got garbage register from LLIL_SET_REG_SPLIT @ 0x{:x}",
self.op.address
@@ -184,7 +184,7 @@ where
.arch()
.register_from_id(raw_id)
.map(Register::ArchReg)
- .unwrap_or({
+ .unwrap_or_else(|| {
error!(
"got garbage register from LLIL_SET_REG_SPLIT @ 0x{:x}",
self.op.address
@@ -277,7 +277,7 @@ where
.arch()
.register_from_id(raw_id)
.map(Register::ArchReg)
- .unwrap_or({
+ .unwrap_or_else(|| {
error!(
"got garbage register from LLIL_REG @ 0x{:x}",
self.op.address