diff options
Diffstat (limited to 'rust')
| -rw-r--r-- | rust/src/high_level_il/instruction.rs | 29 | ||||
| -rw-r--r-- | rust/src/high_level_il/lift.rs | 15 | ||||
| -rw-r--r-- | rust/src/low_level_il/expression.rs | 27 | ||||
| -rw-r--r-- | rust/src/low_level_il/lifting.rs | 41 | ||||
| -rw-r--r-- | rust/src/medium_level_il/instruction.rs | 29 | ||||
| -rw-r--r-- | rust/src/medium_level_il/lift.rs | 15 |
6 files changed, 147 insertions, 9 deletions
diff --git a/rust/src/high_level_il/instruction.rs b/rust/src/high_level_il/instruction.rs index 0fbbb297..8b675657 100644 --- a/rust/src/high_level_il/instruction.rs +++ b/rust/src/high_level_il/instruction.rs @@ -227,6 +227,22 @@ impl HighLevelILInstruction { left: HighLevelExpressionIndex::from(op.operands[0]), right: HighLevelExpressionIndex::from(op.operands[1]), }), + HLIL_MINS => Op::MinSigned(BinaryOp { + left: HighLevelExpressionIndex::from(op.operands[0]), + right: HighLevelExpressionIndex::from(op.operands[1]), + }), + HLIL_MAXS => Op::MaxSigned(BinaryOp { + left: HighLevelExpressionIndex::from(op.operands[0]), + right: HighLevelExpressionIndex::from(op.operands[1]), + }), + HLIL_MINU => Op::MinUnsigned(BinaryOp { + left: HighLevelExpressionIndex::from(op.operands[0]), + right: HighLevelExpressionIndex::from(op.operands[1]), + }), + HLIL_MAXU => Op::MaxUnsigned(BinaryOp { + left: HighLevelExpressionIndex::from(op.operands[0]), + right: HighLevelExpressionIndex::from(op.operands[1]), + }), HLIL_CMP_E => Op::CmpE(BinaryOp { left: HighLevelExpressionIndex::from(op.operands[0]), right: HighLevelExpressionIndex::from(op.operands[1]), @@ -430,6 +446,9 @@ impl HighLevelILInstruction { HLIL_CLS => Op::Cls(UnaryOp { src: HighLevelExpressionIndex::from(op.operands[0]), }), + HLIL_ABS => Op::Abs(UnaryOp { + src: HighLevelExpressionIndex::from(op.operands[0]), + }), HLIL_SX => Op::Sx(UnaryOp { src: HighLevelExpressionIndex::from(op.operands[0]), }), @@ -695,6 +714,10 @@ impl HighLevelILInstruction { ModuDp(op) => Lifted::ModuDp(self.lift_binary_op(op)), Mods(op) => Lifted::Mods(self.lift_binary_op(op)), ModsDp(op) => Lifted::ModsDp(self.lift_binary_op(op)), + MinSigned(op) => Lifted::MinSigned(self.lift_binary_op(op)), + MaxSigned(op) => Lifted::MaxSigned(self.lift_binary_op(op)), + MinUnsigned(op) => Lifted::MinUnsigned(self.lift_binary_op(op)), + MaxUnsigned(op) => Lifted::MaxUnsigned(self.lift_binary_op(op)), CmpE(op) => Lifted::CmpE(self.lift_binary_op(op)), CmpNe(op) => Lifted::CmpNe(self.lift_binary_op(op)), CmpSlt(op) => Lifted::CmpSlt(self.lift_binary_op(op)), @@ -818,6 +841,7 @@ impl HighLevelILInstruction { Ctz(op) => Lifted::Ctz(self.lift_unary_op(op)), Rbit(op) => Lifted::Rbit(self.lift_unary_op(op)), Cls(op) => Lifted::Cls(self.lift_unary_op(op)), + Abs(op) => Lifted::Abs(self.lift_unary_op(op)), Sx(op) => Lifted::Sx(self.lift_unary_op(op)), Zx(op) => Lifted::Zx(self.lift_unary_op(op)), LowPart(op) => Lifted::LowPart(self.lift_unary_op(op)), @@ -1152,6 +1176,10 @@ pub enum HighLevelILInstructionKind { ModuDp(BinaryOp), Mods(BinaryOp), ModsDp(BinaryOp), + MinSigned(BinaryOp), + MaxSigned(BinaryOp), + MinUnsigned(BinaryOp), + MaxUnsigned(BinaryOp), CmpE(BinaryOp), CmpNe(BinaryOp), CmpSlt(BinaryOp), @@ -1203,6 +1231,7 @@ pub enum HighLevelILInstructionKind { Ctz(UnaryOp), Rbit(UnaryOp), Cls(UnaryOp), + Abs(UnaryOp), Sx(UnaryOp), Zx(UnaryOp), LowPart(UnaryOp), diff --git a/rust/src/high_level_il/lift.rs b/rust/src/high_level_il/lift.rs index 3d32b369..1de6248a 100644 --- a/rust/src/high_level_il/lift.rs +++ b/rust/src/high_level_il/lift.rs @@ -71,6 +71,10 @@ pub enum HighLevelILLiftedInstructionKind { ModuDp(LiftedBinaryOp), Mods(LiftedBinaryOp), ModsDp(LiftedBinaryOp), + MinSigned(LiftedBinaryOp), + MaxSigned(LiftedBinaryOp), + MinUnsigned(LiftedBinaryOp), + MaxUnsigned(LiftedBinaryOp), CmpE(LiftedBinaryOp), CmpNe(LiftedBinaryOp), CmpSlt(LiftedBinaryOp), @@ -122,6 +126,7 @@ pub enum HighLevelILLiftedInstructionKind { Ctz(LiftedUnaryOp), Rbit(LiftedUnaryOp), Cls(LiftedUnaryOp), + Abs(LiftedUnaryOp), Sx(LiftedUnaryOp), Zx(LiftedUnaryOp), LowPart(LiftedUnaryOp), @@ -207,6 +212,10 @@ impl HighLevelILLiftedInstruction { ModuDp(_) => "ModuDp", Mods(_) => "Mods", ModsDp(_) => "ModsDp", + MinSigned(_) => "MinSigned", + MaxSigned(_) => "MaxSigned", + MinUnsigned(_) => "MinUnsigned", + MaxUnsigned(_) => "MaxUnsigned", CmpE(_) => "CmpE", CmpNe(_) => "CmpNe", CmpSlt(_) => "CmpSlt", @@ -258,6 +267,7 @@ impl HighLevelILLiftedInstruction { Ctz(_) => "Ctz", Rbit(_) => "Rbit", Cls(_) => "Cls", + Abs(_) => "Abs", Sx(_) => "Sx", Zx(_) => "Zx", LowPart(_) => "LowPart", @@ -319,7 +329,8 @@ impl HighLevelILLiftedInstruction { ], Add(op) | Sub(op) | And(op) | Or(op) | Xor(op) | Lsl(op) | Lsr(op) | Asr(op) | Rol(op) | Ror(op) | Mul(op) | MuluDp(op) | MulsDp(op) | Divu(op) | DivuDp(op) - | Divs(op) | DivsDp(op) | Modu(op) | ModuDp(op) | Mods(op) | ModsDp(op) | CmpE(op) + | Divs(op) | DivsDp(op) | Modu(op) | ModuDp(op) | Mods(op) | ModsDp(op) + | MinSigned(op) | MaxSigned(op) | MinUnsigned(op) | MaxUnsigned(op) | CmpE(op) | CmpNe(op) | CmpSlt(op) | CmpUlt(op) | CmpSle(op) | CmpUle(op) | CmpSge(op) | CmpUge(op) | CmpSgt(op) | CmpUgt(op) | TestBit(op) | AddOverflow(op) | Fadd(op) | Fsub(op) | Fmul(op) | Fdiv(op) | FcmpE(op) | FcmpNe(op) | FcmpLt(op) | FcmpLe(op) @@ -377,7 +388,7 @@ impl HighLevelILLiftedInstruction { Operand::ConstantData(op.constant_data.clone()), )], Deref(op) | AddressOf(op) | PassByRef(op) | ReturnByRef(op) | Neg(op) | Not(op) - | Bswap(op) | Popcnt(op) | Clz(op) | Ctz(op) | Rbit(op) | Cls(op) + | Bswap(op) | Popcnt(op) | Clz(op) | Ctz(op) | Rbit(op) | Cls(op) | Abs(op) | Sx(op) | Zx(op) | LowPart(op) | BoolToInt(op) | UnimplMem(op) | Fsqrt(op) | Fneg(op) | Fabs(op) | FloatToInt(op) | IntToFloat(op) | FloatConv(op) | RoundToInt(op) | Floor(op) | Ceil(op) | Ftrunc(op) => { diff --git a/rust/src/low_level_il/expression.rs b/rust/src/low_level_il/expression.rs index 92d57675..83e93375 100644 --- a/rust/src/low_level_il/expression.rs +++ b/rust/src/low_level_il/expression.rs @@ -315,6 +315,13 @@ where Ctz(Operation<'func, M, F, operation::UnaryOp>), Rbit(Operation<'func, M, F, operation::UnaryOp>), Cls(Operation<'func, M, F, operation::UnaryOp>), + + MinSigned(Operation<'func, M, F, operation::BinaryOp>), + MaxSigned(Operation<'func, M, F, operation::BinaryOp>), + MinUnsigned(Operation<'func, M, F, operation::BinaryOp>), + MaxUnsigned(Operation<'func, M, F, operation::BinaryOp>), + Abs(Operation<'func, M, F, operation::UnaryOp>), + Sx(Operation<'func, M, F, operation::UnaryOp>), Zx(Operation<'func, M, F, operation::UnaryOp>), LowPart(Operation<'func, M, F, operation::UnaryOp>), @@ -479,6 +486,12 @@ where LLIL_RBIT => LowLevelILExpressionKind::Rbit(Operation::new(function, op, index)), LLIL_CLS => LowLevelILExpressionKind::Cls(Operation::new(function, op, index)), + LLIL_MINS => LowLevelILExpressionKind::MinSigned(Operation::new(function, op, index)), + LLIL_MAXS => LowLevelILExpressionKind::MaxSigned(Operation::new(function, op, index)), + LLIL_MINU => LowLevelILExpressionKind::MinUnsigned(Operation::new(function, op, index)), + LLIL_MAXU => LowLevelILExpressionKind::MaxUnsigned(Operation::new(function, op, index)), + LLIL_ABS => LowLevelILExpressionKind::Abs(Operation::new(function, op, index)), + LLIL_SX => LowLevelILExpressionKind::Sx(Operation::new(function, op, index)), LLIL_ZX => LowLevelILExpressionKind::Zx(Operation::new(function, op, index)), LLIL_LOW_PART => LowLevelILExpressionKind::LowPart(Operation::new(function, op, index)), @@ -614,7 +627,8 @@ where | Lsr(ref op) | Asr(ref op) | Rol(ref op) | Ror(ref op) | Mul(ref op) | MulsDp(ref op) | MuluDp(ref op) | Divu(ref op) | Divs(ref op) | Modu(ref op) | Mods(ref op) | Fadd(ref op) | Fsub(ref op) | Fmul(ref op) | Fdiv(ref op) - | DivuDp(ref op) | DivsDp(ref op) | ModuDp(ref op) | ModsDp(ref op) => Some(op), + | DivuDp(ref op) | DivsDp(ref op) | ModuDp(ref op) | ModsDp(ref op) + | MinSigned(ref op) | MaxSigned(ref op) | MinUnsigned(ref op) | MaxUnsigned(ref op) => Some(op), _ => None, } } @@ -633,7 +647,7 @@ where match *self { Neg(ref op) | Not(ref op) | Bswap(ref op) | Popcnt(ref op) | Clz(ref op) | Ctz(ref op) - | Rbit(ref op) | Cls(ref op) | Sx(ref op) | Zx(ref op) | LowPart(ref op) + | Rbit(ref op) | Cls(ref op) | Abs(ref op) | Sx(ref op) | Zx(ref op) | LowPart(ref op) | BoolToInt(ref op) | Fsqrt(ref op) | Fneg(ref op) | Fabs(ref op) | FloatToInt(ref op) | IntToFloat(ref op) | FloatConv(ref op) | RoundToInt(ref op) | Floor(ref op) | Ceil(ref op) | Ftrunc(ref op) => Some(op), @@ -673,12 +687,13 @@ where | Mul(ref op) | MulsDp(ref op) | MuluDp(ref op) | Divu(ref op) | Divs(ref op) | Modu(ref op) | Mods(ref op) | Fadd(ref op) | Fsub(ref op) | Fmul(ref op) | DivuDp(ref op) | DivsDp(ref op) | ModuDp(ref op) | ModsDp(ref op) | Fdiv(ref op) + | MinSigned(ref op) | MaxSigned(ref op) | MinUnsigned(ref op) | MaxUnsigned(ref op) | TestBit(ref op) => { visit!(op.left()); visit!(op.right()); } Neg(ref op) | Not(ref op) | Bswap(ref op) | Popcnt(ref op) | Clz(ref op) | Ctz(ref op) - | Rbit(ref op) | Cls(ref op) | Sx(ref op) | Zx(ref op) | LowPart(ref op) + | Rbit(ref op) | Cls(ref op) | Abs(ref op) | Sx(ref op) | Zx(ref op) | LowPart(ref op) | BoolToInt(ref op) | Fsqrt(ref op) | Fneg(ref op) | Fabs(ref op) | FloatToInt(ref op) | IntToFloat(ref op) | FloatConv(ref op) | RoundToInt(ref op) | Floor(ref op) | Ceil(ref op) | Ftrunc(ref op) => { @@ -768,12 +783,13 @@ where | Xor(ref op) | Lsl(ref op) | Lsr(ref op) | Asr(ref op) | Rol(ref op) | Ror(ref op) | Mul(ref op) | MulsDp(ref op) | MuluDp(ref op) | Divu(ref op) | Divs(ref op) | Modu(ref op) | Mods(ref op) | Fadd(ref op) | Fsub(ref op) | Fmul(ref op) + | MinSigned(ref op) | MaxSigned(ref op) | MinUnsigned(ref op) | MaxUnsigned(ref op) | Fdiv(ref op) | TestBit(ref op) => &op.op, DivuDp(ref op) | DivsDp(ref op) | ModuDp(ref op) | ModsDp(ref op) => &op.op, Neg(ref op) | Not(ref op) | Bswap(ref op) | Popcnt(ref op) | Clz(ref op) | Ctz(ref op) - | Rbit(ref op) | Cls(ref op) | Sx(ref op) | Zx(ref op) | LowPart(ref op) + | Rbit(ref op) | Cls(ref op) | Abs(ref op) | Sx(ref op) | Zx(ref op) | LowPart(ref op) | BoolToInt(ref op) | Fsqrt(ref op) | Fneg(ref op) | Fabs(ref op) | FloatToInt(ref op) | IntToFloat(ref op) | FloatConv(ref op) | RoundToInt(ref op) | Floor(ref op) | Ceil(ref op) | Ftrunc(ref op) => &op.op, @@ -842,12 +858,13 @@ impl LowLevelILExpressionKind<'_, Mutable, NonSSA> { | Xor(ref op) | Lsl(ref op) | Lsr(ref op) | Asr(ref op) | Rol(ref op) | Ror(ref op) | Mul(ref op) | MulsDp(ref op) | MuluDp(ref op) | Divu(ref op) | Divs(ref op) | Modu(ref op) | Mods(ref op) | Fadd(ref op) | Fsub(ref op) | Fmul(ref op) + | MinSigned(ref op) | MaxSigned(ref op) | MinUnsigned(ref op) | MaxUnsigned(ref op) | Fdiv(ref op) | TestBit(ref op) => op.flag_write(), DivuDp(ref op) | DivsDp(ref op) | ModuDp(ref op) | ModsDp(ref op) => op.flag_write(), Neg(ref op) | Not(ref op) | Bswap(ref op) | Popcnt(ref op) | Clz(ref op) | Ctz(ref op) - | Rbit(ref op) | Cls(ref op) | Sx(ref op) | Zx(ref op) | LowPart(ref op) + | Rbit(ref op) | Cls(ref op) | Abs(ref op) | Sx(ref op) | Zx(ref op) | LowPart(ref op) | BoolToInt(ref op) | Fsqrt(ref op) | Fneg(ref op) | Fabs(ref op) | FloatToInt(ref op) | IntToFloat(ref op) | FloatConv(ref op) | RoundToInt(ref op) | Floor(ref op) | Ceil(ref op) | Ftrunc(ref op) => op.flag_write(), diff --git a/rust/src/low_level_il/lifting.rs b/rust/src/low_level_il/lifting.rs index ebd6e980..dcbc5198 100644 --- a/rust/src/low_level_il/lifting.rs +++ b/rust/src/low_level_il/lifting.rs @@ -100,6 +100,7 @@ pub enum LowLevelILFlagWriteOp<R: ArchReg> { Ctz(usize, LowLevelILRegisterOrConstant<R>), Rbit(usize, LowLevelILRegisterOrConstant<R>), Cls(usize, LowLevelILRegisterOrConstant<R>), + Abs(usize, LowLevelILRegisterOrConstant<R>), Sx(usize, LowLevelILRegisterOrConstant<R>), Zx(usize, LowLevelILRegisterOrConstant<R>), LowPart(usize, LowLevelILRegisterOrConstant<R>), @@ -187,6 +188,26 @@ pub enum LowLevelILFlagWriteOp<R: ArchReg> { LowLevelILRegisterOrConstant<R>, LowLevelILRegisterOrConstant<R>, ), + MinSigned( + usize, + LowLevelILRegisterOrConstant<R>, + LowLevelILRegisterOrConstant<R>, + ), + MaxSigned( + usize, + LowLevelILRegisterOrConstant<R>, + LowLevelILRegisterOrConstant<R>, + ), + MinUnsigned( + usize, + LowLevelILRegisterOrConstant<R>, + LowLevelILRegisterOrConstant<R>, + ), + MaxUnsigned( + usize, + LowLevelILRegisterOrConstant<R>, + LowLevelILRegisterOrConstant<R>, + ), DivuDp( usize, LowLevelILRegisterOrConstant<R>, @@ -305,6 +326,7 @@ impl<R: ArchReg> LowLevelILFlagWriteOp<R> { (1, LLIL_CTZ) => op!(Ctz, 0), (1, LLIL_RBIT) => op!(Rbit, 0), (1, LLIL_CLS) => op!(Cls, 0), + (1, LLIL_ABS) => op!(Abs, 0), (1, LLIL_SX) => op!(Sx, 0), (1, LLIL_ZX) => op!(Zx, 0), (1, LLIL_LOW_PART) => op!(LowPart, 0), @@ -328,6 +350,10 @@ impl<R: ArchReg> LowLevelILFlagWriteOp<R> { (2, LLIL_DIVS) => op!(Divs, 0, 1), (2, LLIL_MODU) => op!(Modu, 0, 1), (2, LLIL_MODS) => op!(Mods, 0, 1), + (2, LLIL_MINS) => op!(MinSigned, 0, 1), + (2, LLIL_MAXS) => op!(MaxSigned, 0, 1), + (2, LLIL_MINU) => op!(MinUnsigned, 0, 1), + (2, LLIL_MAXU) => op!(MaxUnsigned, 0, 1), (2, LLIL_DIVU_DP) => op!(DivuDp, 0, 1), (2, LLIL_DIVS_DP) => op!(DivsDp, 0, 1), (2, LLIL_MODU_DP) => op!(ModuDp, 0, 1), @@ -369,6 +395,7 @@ impl<R: ArchReg> LowLevelILFlagWriteOp<R> { Ctz(size, ..) => (size, LLIL_CTZ), Rbit(size, ..) => (size, LLIL_RBIT), Cls(size, ..) => (size, LLIL_CLS), + Abs(size, ..) => (size, LLIL_ABS), Sx(size, ..) => (size, LLIL_SX), Zx(size, ..) => (size, LLIL_ZX), LowPart(size, ..) => (size, LLIL_LOW_PART), @@ -392,6 +419,10 @@ impl<R: ArchReg> LowLevelILFlagWriteOp<R> { Divs(size, ..) => (size, LLIL_DIVS), Modu(size, ..) => (size, LLIL_MODU), Mods(size, ..) => (size, LLIL_MODS), + MinSigned(size, ..) => (size, LLIL_MINS), + MaxSigned(size, ..) => (size, LLIL_MAXS), + MinUnsigned(size, ..) => (size, LLIL_MINU), + MaxUnsigned(size, ..) => (size, LLIL_MAXU), DivuDp(size, ..) => (size, LLIL_DIVU_DP), DivsDp(size, ..) => (size, LLIL_DIVS_DP), ModuDp(size, ..) => (size, LLIL_MODU_DP), @@ -428,6 +459,7 @@ impl<R: ArchReg> LowLevelILFlagWriteOp<R> { | Ctz(_, op0) | Rbit(_, op0) | Cls(_, op0) + | Abs(_, op0) | Sx(_, op0) | Zx(_, op0) | LowPart(_, op0) @@ -456,6 +488,10 @@ impl<R: ArchReg> LowLevelILFlagWriteOp<R> { | Divs(_, op0, op1) | Modu(_, op0, op1) | Mods(_, op0, op1) + | MinSigned(_, op0, op1) + | MaxSigned(_, op0, op1) + | MinUnsigned(_, op0, op1) + | MaxUnsigned(_, op0, op1) | DivuDp(_, op0, op1) | DivsDp(_, op0, op1) | ModuDp(_, op0, op1) @@ -1452,6 +1488,7 @@ impl LowLevelILMutableFunction { sized_unary_op_lifter!(ctz, LLIL_CTZ, ValueExpr); sized_unary_op_lifter!(rbit, LLIL_RBIT, ValueExpr); sized_unary_op_lifter!(cls, LLIL_CLS, ValueExpr); + sized_unary_op_lifter!(abs, LLIL_ABS, ValueExpr); size_changing_unary_op_lifter!(sx, LLIL_SX, ValueExpr); size_changing_unary_op_lifter!(zx, LLIL_ZX, ValueExpr); @@ -1478,6 +1515,10 @@ impl LowLevelILMutableFunction { binary_op_lifter!(divu, LLIL_DIVU); binary_op_lifter!(mods, LLIL_MODS); binary_op_lifter!(modu, LLIL_MODU); + binary_op_lifter!(min_signed, LLIL_MINS); + binary_op_lifter!(max_signed, LLIL_MAXS); + binary_op_lifter!(min_unsigned, LLIL_MINU); + binary_op_lifter!(max_unsigned, LLIL_MAXU); binary_op_carry_lifter!(adc, LLIL_ADC); binary_op_carry_lifter!(sbb, LLIL_SBB); diff --git a/rust/src/medium_level_il/instruction.rs b/rust/src/medium_level_il/instruction.rs index 77a0be27..69936e60 100644 --- a/rust/src/medium_level_il/instruction.rs +++ b/rust/src/medium_level_il/instruction.rs @@ -334,6 +334,22 @@ impl MediumLevelILInstruction { left: MediumLevelExpressionIndex::from(op.operands[0]), right: MediumLevelExpressionIndex::from(op.operands[1]), }), + MLIL_MINS => Op::MinSigned(BinaryOp { + left: MediumLevelExpressionIndex::from(op.operands[0]), + right: MediumLevelExpressionIndex::from(op.operands[1]), + }), + MLIL_MAXS => Op::MaxSigned(BinaryOp { + left: MediumLevelExpressionIndex::from(op.operands[0]), + right: MediumLevelExpressionIndex::from(op.operands[1]), + }), + MLIL_MINU => Op::MinUnsigned(BinaryOp { + left: MediumLevelExpressionIndex::from(op.operands[0]), + right: MediumLevelExpressionIndex::from(op.operands[1]), + }), + MLIL_MAXU => Op::MaxUnsigned(BinaryOp { + left: MediumLevelExpressionIndex::from(op.operands[0]), + right: MediumLevelExpressionIndex::from(op.operands[1]), + }), MLIL_CMP_E => Op::CmpE(BinaryOp { left: MediumLevelExpressionIndex::from(op.operands[0]), right: MediumLevelExpressionIndex::from(op.operands[1]), @@ -593,6 +609,9 @@ impl MediumLevelILInstruction { MLIL_CLS => Op::Cls(UnaryOp { src: MediumLevelExpressionIndex::from(op.operands[0] as usize), }), + MLIL_ABS => Op::Abs(UnaryOp { + src: MediumLevelExpressionIndex::from(op.operands[0] as usize), + }), MLIL_SX => Op::Sx(UnaryOp { src: MediumLevelExpressionIndex::from(op.operands[0] as usize), }), @@ -941,6 +960,10 @@ impl MediumLevelILInstruction { ModuDp(op) => Lifted::ModuDp(self.lift_binary_op(op)), Mods(op) => Lifted::Mods(self.lift_binary_op(op)), ModsDp(op) => Lifted::ModsDp(self.lift_binary_op(op)), + MinSigned(op) => Lifted::MinSigned(self.lift_binary_op(op)), + MaxSigned(op) => Lifted::MaxSigned(self.lift_binary_op(op)), + MinUnsigned(op) => Lifted::MinUnsigned(self.lift_binary_op(op)), + MaxUnsigned(op) => Lifted::MaxUnsigned(self.lift_binary_op(op)), CmpE(op) => Lifted::CmpE(self.lift_binary_op(op)), CmpNe(op) => Lifted::CmpNe(self.lift_binary_op(op)), CmpSlt(op) => Lifted::CmpSlt(self.lift_binary_op(op)), @@ -1123,6 +1146,7 @@ impl MediumLevelILInstruction { Ctz(op) => Lifted::Ctz(self.lift_unary_op(op)), Rbit(op) => Lifted::Rbit(self.lift_unary_op(op)), Cls(op) => Lifted::Cls(self.lift_unary_op(op)), + Abs(op) => Lifted::Abs(self.lift_unary_op(op)), Sx(op) => Lifted::Sx(self.lift_unary_op(op)), Zx(op) => Lifted::Zx(self.lift_unary_op(op)), LowPart(op) => Lifted::LowPart(self.lift_unary_op(op)), @@ -1843,6 +1867,10 @@ pub enum MediumLevelILInstructionKind { ModuDp(BinaryOp), Mods(BinaryOp), ModsDp(BinaryOp), + MinSigned(BinaryOp), + MaxSigned(BinaryOp), + MinUnsigned(BinaryOp), + MaxUnsigned(BinaryOp), CmpE(BinaryOp), CmpNe(BinaryOp), CmpSlt(BinaryOp), @@ -1904,6 +1932,7 @@ pub enum MediumLevelILInstructionKind { Ctz(UnaryOp), Rbit(UnaryOp), Cls(UnaryOp), + Abs(UnaryOp), Sx(UnaryOp), Zx(UnaryOp), LowPart(UnaryOp), diff --git a/rust/src/medium_level_il/lift.rs b/rust/src/medium_level_il/lift.rs index 2f0d6653..f886d93a 100644 --- a/rust/src/medium_level_il/lift.rs +++ b/rust/src/medium_level_il/lift.rs @@ -102,6 +102,10 @@ pub enum MediumLevelILLiftedInstructionKind { ModuDp(LiftedBinaryOp), Mods(LiftedBinaryOp), ModsDp(LiftedBinaryOp), + MinSigned(LiftedBinaryOp), + MaxSigned(LiftedBinaryOp), + MinUnsigned(LiftedBinaryOp), + MaxUnsigned(LiftedBinaryOp), CmpE(LiftedBinaryOp), CmpNe(LiftedBinaryOp), CmpSlt(LiftedBinaryOp), @@ -160,6 +164,7 @@ pub enum MediumLevelILLiftedInstructionKind { Ctz(LiftedUnaryOp), Rbit(LiftedUnaryOp), Cls(LiftedUnaryOp), + Abs(LiftedUnaryOp), Sx(LiftedUnaryOp), Zx(LiftedUnaryOp), LowPart(LiftedUnaryOp), @@ -264,6 +269,10 @@ impl MediumLevelILLiftedInstruction { ModuDp(_) => "ModuDp", Mods(_) => "Mods", ModsDp(_) => "ModsDp", + MinSigned(_) => "MinSigned", + MaxSigned(_) => "MaxSigned", + MinUnsigned(_) => "MinUnsigned", + MaxUnsigned(_) => "MaxUnsigned", CmpE(_) => "CmpE", CmpNe(_) => "CmpNe", CmpSlt(_) => "CmpSlt", @@ -325,6 +334,7 @@ impl MediumLevelILLiftedInstruction { Ctz(_) => "Ctz", Rbit(_) => "Rbit", Cls(_) => "Cls", + Abs(_) => "Abs", Sx(_) => "Sx", Zx(_) => "Zx", LowPart(_) => "LowPart", @@ -469,7 +479,8 @@ impl MediumLevelILLiftedInstruction { ], Add(op) | Sub(op) | And(op) | Or(op) | Xor(op) | Lsl(op) | Lsr(op) | Asr(op) | Rol(op) | Ror(op) | Mul(op) | MuluDp(op) | MulsDp(op) | Divu(op) | DivuDp(op) - | Divs(op) | DivsDp(op) | Modu(op) | ModuDp(op) | Mods(op) | ModsDp(op) | CmpE(op) + | Divs(op) | DivsDp(op) | Modu(op) | ModuDp(op) | Mods(op) | ModsDp(op) + | MinSigned(op) | MaxSigned(op) | MinUnsigned(op) | MaxUnsigned(op) | CmpE(op) | CmpNe(op) | CmpSlt(op) | CmpUlt(op) | CmpSle(op) | CmpUle(op) | CmpSge(op) | CmpUge(op) | CmpSgt(op) | CmpUgt(op) | TestBit(op) | AddOverflow(op) | FcmpE(op) | FcmpNe(op) | FcmpLt(op) | FcmpLe(op) | FcmpGe(op) | FcmpGt(op) | FcmpO(op) @@ -555,7 +566,7 @@ impl MediumLevelILLiftedInstruction { ("stack", Operand::Expr(*op.stack.clone())), ], Neg(op) | Not(op) | Bswap(op) | Popcnt(op) | Clz(op) | Ctz(op) | Rbit(op) | Cls(op) - | Sx(op) | Zx(op) | LowPart(op) | BoolToInt(op) | UnimplMem(op) + | Abs(op) | Sx(op) | Zx(op) | LowPart(op) | BoolToInt(op) | UnimplMem(op) | Fsqrt(op) | Fneg(op) | Fabs(op) | FloatToInt(op) | IntToFloat(op) | FloatConv(op) | RoundToInt(op) | Floor(op) | Ceil(op) | Ftrunc(op) | Load(op) => { vec![("src", Operand::Expr(*op.src.clone()))] |