| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-08-14 | [thumb2] improved disassembly and lifting of VCVT instruction for scalar ↵ | Galen Williamson | |
| floating-point/integer cases | |||
| 2025-08-14 | Corrected python docstring for LowLevelILFunction.float_convert | Galen Williamson | |
| [thumb2] removed redundant format suffixes from disassembly of VFP instruction [thumb2] Corrected lifting of VCVT instruction | |||
| 2025-08-14 | [armv7/thumb2] Fix Lifting for PC-relative vldr instruction does not align ↵ | Galen Williamson | |
| PC when calculating address #6947 Updated thumb2 pcode parser used by disassembler generator to use Tatsu instead of deprecated Grako | |||
| 2025-07-02 | Fix thumb2 lifting to prevent temp reg spillover for post dec stm instruction. | Brian Potchik | |
| 2025-06-09 | [thumb2] Converted MSR system registers into enum | Galen Williamson | |
| 2025-06-09 | WIP improve thumb2 MSR lifting | Galen Williamson | |
| 2025-06-09 | [thumb2] add intrinsics for rbit and clz instructions | Galen Williamson | |
| 2025-06-02 | Add IL for thumb2 CP instructions | jonathanzetier | |
| 2025-04-28 | [thumb2] correctly set flags for mov{s} and mvn{s} instruction variants with ↵ | Galen Williamson | |
| 32-bit encodings, addresses #6698 | |||
| 2025-04-08 | [aarch64] lift all LD[1-4]R? and ST[1-4] opcodes, lift ST/LDCLR, ST/LDEOR, ↵ | Galen Williamson | |
| ST/LDSET, and their variants Also fixes all outstanding issues in arm64test.py, including intrinsics, dc, at, and tlbi | |||
| 2025-01-17 | [thumb2] Fix #6328: "Invalid intrinsic lifting for MRS instruction: ↵ | Galen Williamson | |
| destination register incorrectly specified" by correctly specifying the intrinsic outputs | |||
| 2024-08-27 | Fixed fall-through VMOV lifting | Galen Williamson | |
| Conditions were not cascading, caused instructions to generate il for multiple variants of VMOV | |||
| 2024-08-27 | Cleaned up formatting on new and old code | Galen Williamson | |
| 2024-08-27 | Constraint NEON instructions using operation flags | Mason Reed | |
| Also fix some formatting issues | |||
| 2024-08-27 | Use split registers for VMOV | Mason Reed | |
| 2024-08-27 | Fix VPOP not setting registers | Mason Reed | |
| 2024-08-27 | Fix VDIV constraints and lift VNEG | Mason Reed | |
| 2024-08-27 | Fix unconstrained VADD and VABS | Mason Reed | |
| 2024-08-27 | Lift VMRS and mark system registers | Mason Reed | |
| System registers needed to be marked to prevent the registers from being passed as arguments | |||
| 2024-08-27 | Lift VSUB, VDIV, VMUL, VFMA | Mason Reed | |
| VSUB already existed but it was lifted as a regular SUB instruction | |||
| 2024-08-27 | Lift more variants of VCVT and correct a missed variant case | Mason Reed | |
| 2024-08-27 | Lift VSTMIA, VLDMIA | Mason Reed | |
| 2024-08-27 | Fix non R register groups referencing PC for 15th register index | Mason Reed | |
| Any usage of d15, s15, q15 was completely broken | |||
| 2024-08-27 | Lift misc V_ thumb instrunctions | Mason Reed | |
| 2024-08-27 | Lift VMOV | Mason Reed | |
| 2024-08-27 | Lift VLDR and VSTR | Mason Reed | |
| 2024-08-27 | Lift VPOP and VPUSH | Mason Reed | |
| 2024-08-27 | Fix getting incorrect S and D registers in lifted il | Mason Reed | |
| 2024-08-21 | Fix thumb2 lifting of REV | Mason Reed | |
| 2024-03-05 | Move architecture modules into the API repo | Rusty Wagner | |
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index : public/binaryninja-api.git | |
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