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AgeCommit message (Collapse)Author
2026-06-04[armv7] Emit bswap, clz, and rbit instructions during liftingMark Rowe
2026-05-19Fix Thumb-2 out-of-bounds read during liftingBrandon Miller
Fix for sentry crash BINARYNINJA-89
2026-04-13[Thumb2] Fix IT instruction infoJosh Ferrell
2026-03-30Fix compiler warnings seen with Clang 21Mark Rowe
2026-02-27[MachO] Fix relocations from chained fixups not respecting addendsMark Rowe
The addends were correctly stored in the relocation info and displayed as offsets in linear view, but the relocation handlers never applied them. Reading from an address containing such a relocation would give an incorrect value.
2026-01-01update copyrights for 2026Jordan Wiens
2025-12-29Use session scoped logger instance for unhandled relocation informationMason Reed
Ran into this when running over certain object files on ppc, we can do it for all of them though.
2025-12-20Fix many of the warnings that show up when compiling with GCC 15.2Mark Rowe
2025-09-22[armv7] Add support for R_ARM_PC24 relocationNick Shipp
2025-08-14[thumb2] silence parentheses-equality warnings when compiling generated ↵Galen Williamson
thumb2 disassembler
2025-08-14[armv7] add explicit signedness to conversions for scalar forms of VCVTGalen Williamson
2025-08-14[thumb2] improved disassembly and lifting of VCVT instruction for scalar ↵Galen Williamson
floating-point/integer cases
2025-08-14Corrected python docstring for LowLevelILFunction.float_convertGalen Williamson
[thumb2] removed redundant format suffixes from disassembly of VFP instruction [thumb2] Corrected lifting of VCVT instruction
2025-08-14[armv7] Add lifting for VCVT floating-point scalar variantsGalen Williamson
2025-08-14[thumb2] Updated thumb2 disassembler generator to use Tatsu-generated parser ↵Galen Williamson
instead of deprecated Grako
2025-08-14[armv7/thumb2] Fix Lifting for PC-relative vldr instruction does not align ↵Galen Williamson
PC when calculating address #6947 Updated thumb2 pcode parser used by disassembler generator to use Tatsu instead of deprecated Grako
2025-08-01Add LogForException APIs to pass stack trace information separate from the ↵Rusty Wagner
message
2025-07-30[CMake] Specify CONFIGURE_DEPENDS for all file(GLOB ..)Mark Rowe
This ensures that CMake detects when files that match the glob are added or removed.
2025-07-03arm/thumb: signal that returns can switch archRyan Snyder
2025-07-02Fix thumb2 lifting to prevent temp reg spillover for post dec stm instruction.Brian Potchik
2025-06-25Update CXX_STANDARD to 20.Alexander Taylor
Also update minimum CMake version.
2025-06-25Remove implicit conversions from Confidence to underlying type, these can ↵Rusty Wagner
cause bugs and also issues with C++20
2025-06-09[thumb2] Converted MSR system registers into enumGalen Williamson
2025-06-09WIP improve thumb2 MSR liftingGalen Williamson
2025-06-09[thumb2] add intrinsics for rbit and clz instructionsGalen Williamson
2025-06-02Add IL for thumb2 CP instructionsjonathanzetier
2025-06-02Update README.mdjonathanzetier
It looks like the build instructions hadn't been updated after the arch plugins were moved back to binaryninja-api.
2025-05-13[CMake] Report compatibility with 3.15 to silence deprecation warningsGlenn Smith
2025-04-28[thumb2] correctly set flags for mov{s} and mvn{s} instruction variants with ↵Galen Williamson
32-bit encodings, addresses #6698
2025-04-08[aarch64] lift all LD[1-4]R? and ST[1-4] opcodes, lift ST/LDCLR, ST/LDEOR, ↵Galen Williamson
ST/LDSET, and their variants Also fixes all outstanding issues in arm64test.py, including intrinsics, dc, at, and tlbi
2025-03-28belated copyright year updateJordan Wiens
2025-03-06ARMv7: Fix lifting of instructions that use register-shifted registersJosh Ferrell
2025-03-06ARMv7: update test_lift.py and test.pyJosh Ferrell
2025-03-06ARMv7: Add support for register-shifted registersJosh Ferrell
2025-02-05Fixes: Unsupported ELF relocations: R_ARM_THM_MOVW_ABS_NC, ↵Galen Williamson
R_ARM_THM_MOVT_ABS #6215
2025-02-02Fix upper 16 registers not being listed in ARMv7 register list operandMason Reed
Fixes #6383
2025-01-17[thumb2] Fix #6328: "Invalid intrinsic lifting for MRS instruction: ↵Galen Williamson
destination register incorrectly specified" by correctly specifying the intrinsic outputs
2024-09-13Ultimate.Alexander Taylor
2024-08-27Fixed fall-through VMOV liftingGalen Williamson
Conditions were not cascading, caused instructions to generate il for multiple variants of VMOV
2024-08-27Cleaned up formatting on new and old codeGalen Williamson
2024-08-27Constraint NEON instructions using operation flagsMason Reed
Also fix some formatting issues
2024-08-27Use split registers for VMOVMason Reed
2024-08-27Fix VPOP not setting registersMason Reed
2024-08-27Fix VDIV constraints and lift VNEGMason Reed
2024-08-27Fix unconstrained VADD and VABSMason Reed
2024-08-27Lift VMRS and mark system registersMason Reed
System registers needed to be marked to prevent the registers from being passed as arguments
2024-08-27Lift VSUB, VDIV, VMUL, VFMAMason Reed
VSUB already existed but it was lifted as a regular SUB instruction
2024-08-27Lift more variants of VCVT and correct a missed variant caseMason Reed
2024-08-27Lift VSTMIA, VLDMIAMason Reed
2024-08-27Fix non R register groups referencing PC for 15th register indexMason Reed
Any usage of d15, s15, q15 was completely broken