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R_ARM_THM_MOVT_ABS #6215
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Fixes #6383
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destination register incorrectly specified" by correctly specifying the intrinsic outputs
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Conditions were not cascading, caused instructions to generate il for multiple variants of VMOV
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Also fix some formatting issues
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System registers needed to be marked to prevent the registers from being passed as arguments
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VSUB already existed but it was lifted as a regular SUB instruction
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Any usage of d15, s15, q15 was completely broken
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A user reported in public slack that the definition doesn't agree on
endianness
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tokens in lower levels, and improve token usage in disassembly
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