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Also wrapped & to suppress build warning
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target.
It is not always the case, especially under certian compiler optimizations that a R_MIPS_HI16 relocation is followed by one or more R_MIPS_LO16 relocations. Removing this requirement to fulfill the relocation regardless of the preceeding relocation.
Adding the following relocations:
* R_MIPS_HIGHEST
* R_MIPS_HIGHER
* R_MIPS_GPREL16
* (R_MIPS_64 << 8) | R_MIPS_REL32
* R_MIPS_GPREL32
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For 64-bit architectures, the results weren't properly sign-extended when
they were supposed to be for 32-bit operations.
This doesn't change the fact that the source of the register size is
still suspect, and this new sign extension may not properly take place for
64-bit architectures using 32-bit addresses, but solving that will take a
bit more examination in general.
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Except for SYNCI, I didn't have any test cases for these, but they're
fairly simple.
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This makes it easier to see which instructions still need to be lifted
versus those which never should be lifted.
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These aren't really needed; if it's for a 32-bit architecture that can't
handle 64-bit shifts, then the instruction won't be decoded in the first
place. Because the registerSize is derived from the address size, it may
interfere with 64-bit architectures that are using signed 32-bit
addresses.
There are a few other places that check registerSize (for example, the
32->64 bit sign extension idiom and MADD, MADDU) that are suspect, but
not included in this commit. The difference is that for 64-bit shifts,
checking at all for the register size is the problem; for those, the
check is still needed to figure out whether to sign extend or not, but
the value of registerSize is suspect.
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Previously, prtinf type library is not being appropriately applied.
#3092
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tokens in lower levels, and improve token usage in disassembly
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