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2024-12-03Multiple fixes for HI16/LO16 relocs for MIPS64Brandon Miller
Some binaries consist of LO16 entires that are BEFORE associated HI16 entries. Also, prior to this commit we don't appear to be applying HI16 relocations at all for MIPS64. mips_decompose was being called with MIPS_32 and failing prior to fixing up the relocation
2024-11-25Fix regression with MIPS_HI16/MIPS_LO16 relocsBrandon Miller
2024-10-30Undo whitespace changes from user MIPS reloc PRBrandon Miller
Also wrapped & to suppress build warning
2024-10-30Implicit addends in MIPS do not seem to be honored. Adding the addend to the ↵James Hogan
target. It is not always the case, especially under certian compiler optimizations that a R_MIPS_HI16 relocation is followed by one or more R_MIPS_LO16 relocations. Removing this requirement to fulfill the relocation regardless of the preceeding relocation. Adding the following relocations: * R_MIPS_HIGHEST * R_MIPS_HIGHER * R_MIPS_GPREL16 * (R_MIPS_64 << 8) | R_MIPS_REL32 * R_MIPS_GPREL32
2024-09-13Fix many warningsJosh Ferrell
2024-09-13Ultimate.Alexander Taylor
2024-08-30Add support for loading mipsel64 filesJosh Ferrell
2024-08-12Add decode, disassembly, IL for TLBINV, TLBINVFnoone
2024-08-12Sign-extend results of 32-bit operations on HI, LOnoone
For 64-bit architectures, the results weren't properly sign-extended when they were supposed to be for 32-bit operations. This doesn't change the fact that the source of the register size is still suspect, and this new sign extension may not properly take place for 64-bit architectures using 32-bit addresses, but solving that will take a bit more examination in general.
2024-08-12Add IL, intrinsics for TLB-related instructionsnoone
2024-08-12Add intrinsics for some system instructionsnoone
Except for SYNCI, I didn't have any test cases for these, but they're fairly simple.
2024-08-12Differentiate some enums in IL switch statementnoone
This makes it easier to see which instructions still need to be lifted versus those which never should be lifted.
2024-08-12Remove checks for 64-bit shift instructionsnoone
These aren't really needed; if it's for a 32-bit architecture that can't handle 64-bit shifts, then the instruction won't be decoded in the first place. Because the registerSize is derived from the address size, it may interfere with 64-bit architectures that are using signed 32-bit addresses. There are a few other places that check registerSize (for example, the 32->64 bit sign extension idiom and MADD, MADDU) that are suspect, but not included in this commit. The difference is that for 64-bit shifts, checking at all for the register size is the problem; for those, the check is still needed to figure out whether to sign extend or not, but the value of registerSize is suspect.
2024-07-09Fix warning in mips arch (skip-note, skip-ci)Mason Reed
2024-07-08Add Cavium Octeon MIPS Instructions and more general MIPS fixesnoone
2024-05-31improve efficiencyZichuan Li
2024-05-31Fixed type propagation issue in AARCH64 and MIPSZichuan Li
Previously, prtinf type library is not being appropriately applied. #3092
2024-05-24arch: multiple delay slot support, suppress spurious mips warningRyan Snyder
2024-04-25Recognize uClibc MIPS ELF PLT entriesJosh Ferrell
2024-03-15Separate local variable tokens in higher level ILs from stack variable ↵Rusty Wagner
tokens in lower levels, and improve token usage in disassembly
2024-03-05Move architecture modules into the API repoRusty Wagner