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AgeCommit message (Collapse)Author
2024-06-19Add data_variable_at_address and fixed the type propagation issue in riscvZichuan Li
2024-06-11More descriptive error for TP-relative reloc.Alexander Taylor
2024-05-24arch: multiple delay slot support, suppress spurious mips warningRyan Snyder
2024-05-01riscv: account for minor rust API updatesRyan Snyder
2024-04-09riscv : Remove uses of BnString per #5244KyleMiles
2024-03-20Implement Hash, PartialEq & Eq for riscv Registermason
2024-03-15Separate local variable tokens in higher level ILs from stack variable ↵Rusty Wagner
tokens in lower levels, and improve token usage in disassembly
2024-03-08Fix RISC-V CSRRW, CSRRS, and CSRRC instr disassPete Dietl
Make the CSR instructions show the CSR 12-bit immediate operand as an unsigned integer. This is a special case of the I-instruction format, where it is same except that the 12-bit immediate is treated as unsigned rather than signed.
2024-01-04Add RISC-V relocations required by Linux kernel modulesRusty Wagner
2024-01-04Add RISC-V architecture pluginRusty Wagner