| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-07-12 | Regenerate Cargo lock file after bindgen update. | Alexander Taylor | |
| 2024-06-19 | Add data_variable_at_address and fixed the type propagation issue in riscv | Zichuan Li | |
| 2024-06-12 | Disassemble SFENCE.VM instruction | Mason Reed | |
| 2024-06-11 | More descriptive error for TP-relative reloc. | Alexander Taylor | |
| 2024-05-24 | arch: multiple delay slot support, suppress spurious mips warning | Ryan Snyder | |
| 2024-05-01 | riscv: account for minor rust API updates | Ryan Snyder | |
| 2024-04-09 | riscv : Remove uses of BnString per #5244 | KyleMiles | |
| 2024-03-21 | Update to Rust 1.77 | Rusty Wagner | |
| 2024-03-20 | Implement Hash, PartialEq & Eq for riscv Register | mason | |
| 2024-03-15 | Separate local variable tokens in higher level ILs from stack variable ↵ | Rusty Wagner | |
| tokens in lower levels, and improve token usage in disassembly | |||
| 2024-03-14 | Update to Rust 1.76 | Rusty Wagner | |
| 2024-03-08 | Fix RISC-V CSRRW, CSRRS, and CSRRC instr disass | Pete Dietl | |
| Make the CSR instructions show the CSR 12-bit immediate operand as an unsigned integer. This is a special case of the I-instruction format, where it is same except that the 12-bit immediate is treated as unsigned rather than signed. | |||
| 2024-02-01 | RISC-V: Fix disassembly of compressed JAL instruction | Pete Dietl | |
| Change integer register involved via compressed JAL instruction from 0 (x0 (zero)) to 1 (x1 (ra)) | |||
| 2024-01-04 | Add RISC-V relocations required by Linux kernel modules | Rusty Wagner | |
| 2024-01-04 | Add RISC-V architecture plugin | Rusty Wagner | |
 |
index : public/binaryninja-api.git | |
| [no description] |
| summaryrefslogtreecommitdiff |