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2026-06-06Better MIPS n32 support.Alexander Taylor
2026-06-06Add little-endian octeon mips archJonathan Eskeldson
2026-06-05[aarch64] Emit abs, min, and max instructions during liftingMark Rowe
2026-06-05[aarch64] Fix incorrect lifting of double precision FMOV immediateMark Rowe
2026-06-04[armv7] Emit bswap, clz, and rbit instructions during liftingMark Rowe
2026-06-04[x86] Emit bswap, popcnt, clz, and ctz instructions during liftingMark Rowe
2026-06-04[aarch64] Emit bswap, popcnt, clz, ctz, cls, and rbit instructions during ↵Mark Rowe
lifting Intrinsics are still used when lfiting vector instructions, and for 64-bit `rev16` instructions that are not easily composed from the new instructions.
2026-05-22Refactor calling convention Rust API to allow default implementationsRusty Wagner
Also implements the new calling convention APIs in Rust
2026-05-22Implement return value location handling for x86/x86_64 ELF ABIRusty Wagner
2026-05-22Initial support for Go and Pascal calling conventionsRusty Wagner
2026-05-22Add handling of structure returns and parameters in Windows x86/x64 calling ↵Rusty Wagner
conventions
2026-05-22Add handling of structure returns and parameters in aarch64 calling conventionRusty Wagner
2026-05-19Fix Thumb-2 out-of-bounds read during liftingBrandon Miller
Fix for sentry crash BINARYNINJA-89
2026-05-10[Rust] Refactor `binary_view` moduleMason Reed
- Remove the "viral" `BinaryViewExt` trait and its blanket impl - Split up the binary view type from the custom trait impl - Simplify and fix bugs regarding custom binary view initialization - Rewrite Minidump binary view example, parses the PE headers to create proper sections now - Add some extra documentation - Add unit test for custom binary view
2026-04-22[arm64] Update header names in MakefilesfG!
The names of generated headers were not updated after they were changed in b095215397ca.
2026-04-15RISC-V: Special handling for 0000 (trap).Alexander Taylor
Some compilers will stick 0000 (an invalid instruction) after jumps or calls in a noreturn function, which we lifted as an invalid instruction. If our analysis didn't catch that the function is noreturn, it would trigger guided analysis mode for these functions due to the invalid instruction. This is a workaround that we've applied to x86 and aarch64 as well.
2026-04-14[aarch64] Fix handling of ARM64_RELOC_GOT_LOAD_PAGEOFF12 and ↵Josh Ferrell
ARM64_RELOC_GOT_LOAD_PAGE21
2026-04-13[aarch64] Add support for ARM64_RELOC_BRANCH26, ARM64_RELOC_GOT_LOAD_PAGE21, ↵Josh Ferrell
ARM64_RELOC_GOT_LOAD_PAGEOFF12
2026-04-13[Thumb2] Fix IT instruction infoJosh Ferrell
2026-03-30Fix compiler warnings seen with Clang 21Mark Rowe
2026-03-27Ensure rounding flag is properly emitted on some x86 floating point instructionsPeter LaFosse
2026-03-23[Swift] Add arm64 calling conventionsMark Rowe
The Swift ABI repurposes three callee-saved registers for implicit parameters (self, error, and async context). Supporting the various combinations of these requires registering several different calling conventions. The demangler is taught to explicitly apply these calling conventions to functions that need them.
2026-03-06Implement DTPOFF64 and DTPMOD64 relocations.Alexander Taylor
Finally closes #5463.
2026-02-27[MachO] Fix relocations from chained fixups not respecting addendsMark Rowe
The addends were correctly stored in the relocation info and displayed as offsets in linear view, but the relocation handlers never applied them. Reading from an address containing such a relocation would give an incorrect value.
2026-02-23[x86] Intel APX support (#6423)Avery
Co-authored-by: Mason Reed <mason@vector35.com>
2026-02-23[Rust] Fix plugins being referenced in `cargo about` outputMason Reed
2026-02-20Allow calling conventions to specify a list of registers that are required ↵Rusty Wagner
to be considered for heuristic calling convention detection
2026-02-09Fix outdated object names in AArch64 disassembler MakefilesJon Palmisciano
2026-01-30Update function recognizer to detect ILP32 plt entriesBrandon Miller
2026-01-23Add missing x86_64 relocations.Alexander Taylor
2026-01-23Lifted new PPC insns, MIPS reloc fix.Alexander Taylor
2026-01-23Implement R_386_IRELATIVE relocation handling.Alexander Taylor
Closes #7851.
2026-01-20swap order for some ppc floating point that were backwardJordan Wiens
2026-01-16Update x86 arch README to remove outdated info.Alexander Taylor
2026-01-12Fix(ppcvle): Correct si_split16 immediate decoding for I16A-form instructionschedahub
2026-01-11[Rust] Enter more session scoped tracing spans for debug info and binary ↵Mason Reed
view callbacks
2026-01-11[Rust] Replace `log` with `tracing`Mason Reed
- Added more documentation - Replaced global named logger for plugins, fixing the issue when the CU has multiple (e.g. statically linked demo) - Simplified some misc code This is a breaking change, but I believe there is no better time to make it, we cannot continue to use the `log` crate, it is too limited for our needs.
2026-01-01update copyrights for 2026Jordan Wiens
2025-12-29Use session scoped logger instance for unhandled relocation informationMason Reed
Ran into this when running over certain object files on ppc, we can do it for all of them though.
2025-12-20Fix many of the warnings that show up when compiling with GCC 15.2Mark Rowe
2025-12-11[MIPS] Don't add a default branch type for jalrBrandon Miller
2025-12-11[MIPS] Mark `jalr[.hb] $zero, $ra` as a return instructionRong "Mantle" Bao
2025-12-10[Rust] Remove `UnusedRegisterStackInfo` and update architecture documentationMason Reed
2025-12-10[Rust] Move architecture module code into more reasonable filesMason Reed
To keep backwards compatibility for commonly referenced code we re-export them within the architecture module. Also does some light refactoring of some newly added APIs to keep them more consistent with other parts of the codebase.
2025-12-08[AArch64] Update system registers based on ARM's 2025-09 dataMark Rowe
This change consists of two parts: 1. Updating the system register enumeration and names based on the latest data from ARM. 2. Removing register names that conflict with the official names from ARM. The conflicting register names came a data set of Apple-specific system register names. These would ideally not be baked into the AArch64 disassembler at all, but would be added by Binary Ninja's Apple platform. The exact mechanism for doing that is still TBD. Fixes https://github.com/Vector35/binaryninja-api/issues/7664.
2025-12-05[Rust] Do not clean out-of-tree dependencies for incremental buildsMason Reed
We already do this for a number of plugins / crates, this commit goes over the rest to make sure that they all do this. We keep cleaning binaryninjacore-sys as we want to generate the core bindings immediately on changes to binaryninjacore.h
2025-12-05[Rust] Fix misc clippy lints and warningsMason Reed
These are introduced after changing to Rust 1.91.1
2025-11-17Fix some compiler warningsRusty Wagner
2025-11-05[ARM64] only extend if load is smallyrp
[ARM64] remove zero extend from ubfx, ubfiz [ARM64] only zero extend fmov when needed arm64: resolve ambiguity Resolves #7307
2025-11-03Fix VLE I16L-form instructions to use rD instead of rAchedahub