| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-11-19 | Fix MSP430 conditional jump lifting | Mason Reed | |
| 2024-11-11 | Add actual logger api to rust | Mason Reed | |
| 2024-11-06 | Fixes Vector35/binaryninja-api#5968: "PowerPC flag names no longer ↵ | Galen Williamson | |
| recognized (due to changes in capstone register numbering)": handles new capstone flag numbers, allows assembling `isel` instructions with capstone syntax, disassembles flag registers with capstone syntax | |||
| 2024-11-05 | Updated capstone to 5.0.3 to fix xori instr lifting | Alex Mullins | |
| 2024-11-04 | Fix undefined behavior with COFF relocations | Mason Reed | |
| Was causing major instability with WARP signature generation | |||
| 2024-11-04 | Remove ability to panic on pre-initialized logger in rust | Mason Reed | |
| Typically this would never occur, however due to the mystical nature of linkers this somehow has happened outside of demo builds | |||
| 2024-10-30 | Undo whitespace changes from user MIPS reloc PR | Brandon Miller | |
| Also wrapped & to suppress build warning | |||
| 2024-10-30 | Implicit addends in MIPS do not seem to be honored. Adding the addend to the ↵ | James Hogan | |
| target. It is not always the case, especially under certian compiler optimizations that a R_MIPS_HI16 relocation is followed by one or more R_MIPS_LO16 relocations. Removing this requirement to fulfill the relocation regardless of the preceeding relocation. Adding the following relocations: * R_MIPS_HIGHEST * R_MIPS_HIGHER * R_MIPS_GPREL16 * (R_MIPS_64 << 8) | R_MIPS_REL32 * R_MIPS_GPREL32 | |||
| 2024-10-23 | Calling Conventions for register specific arc functions | kat | |
| 2024-10-14 | Update bindgen to 0.70.1 and remove untracked lockfiles | Mason Reed | |
| 2024-09-14 | Add mpidr_el1 aarch64 sysreg | Josh Ferrell | |
| 2024-09-13 | Fix many warnings | Josh Ferrell | |
| 2024-09-13 | Ultimate. | Alexander Taylor | |
| 2024-09-08 | Respect ELF view endianness when calculating AArch64 relocations | Michael Krasnitski | |
| 2024-08-30 | Add support for loading mipsel64 files | Josh Ferrell | |
| 2024-08-29 | Fix misc rust warnings | Mason Reed | |
| 2024-08-27 | Fixed fall-through VMOV lifting | Galen Williamson | |
| Conditions were not cascading, caused instructions to generate il for multiple variants of VMOV | |||
| 2024-08-27 | Cleaned up formatting on new and old code | Galen Williamson | |
| 2024-08-27 | Constraint NEON instructions using operation flags | Mason Reed | |
| Also fix some formatting issues | |||
| 2024-08-27 | Use split registers for VMOV | Mason Reed | |
| 2024-08-27 | Fix VPOP not setting registers | Mason Reed | |
| 2024-08-27 | Fix VDIV constraints and lift VNEG | Mason Reed | |
| 2024-08-27 | Fix unconstrained VADD and VABS | Mason Reed | |
| 2024-08-27 | Lift VMRS and mark system registers | Mason Reed | |
| System registers needed to be marked to prevent the registers from being passed as arguments | |||
| 2024-08-27 | Lift VSUB, VDIV, VMUL, VFMA | Mason Reed | |
| VSUB already existed but it was lifted as a regular SUB instruction | |||
| 2024-08-27 | Lift more variants of VCVT and correct a missed variant case | Mason Reed | |
| 2024-08-27 | Lift VSTMIA, VLDMIA | Mason Reed | |
| 2024-08-27 | Fix non R register groups referencing PC for 15th register index | Mason Reed | |
| Any usage of d15, s15, q15 was completely broken | |||
| 2024-08-27 | Lift misc V_ thumb instrunctions | Mason Reed | |
| 2024-08-27 | Lift VMOV | Mason Reed | |
| 2024-08-27 | Lift VLDR and VSTR | Mason Reed | |
| 2024-08-27 | Lift VPOP and VPUSH | Mason Reed | |
| 2024-08-27 | Fix getting incorrect S and D registers in lifted il | Mason Reed | |
| 2024-08-27 | Remove duplicate conditional checks in v_ lifts | Mason Reed | |
| 2024-08-22 | Specialize relocation warning for 32-bit/64-bit. | Alexander Taylor | |
| 2024-08-22 | Fix MSP430 lifting bugs causing crashes and errors. | Alexander Taylor | |
| 2024-08-22 | Make MSP430 correctly load after ELF view. | Alexander Taylor | |
| 2024-08-22 | Fix MSP430 dependencies. | Alexander Taylor | |
| 2024-08-22 | Fix build error in MSP430, update README. | Alexander Taylor | |
| 2024-08-22 | Add msp430 architecture | Joe Rozner | |
| 2024-08-21 | Fix thumb2 lifting of REV | Mason Reed | |
| 2024-08-12 | Add decode, disassembly, IL for TLBINV, TLBINVF | noone | |
| 2024-08-12 | Sign-extend results of 32-bit operations on HI, LO | noone | |
| For 64-bit architectures, the results weren't properly sign-extended when they were supposed to be for 32-bit operations. This doesn't change the fact that the source of the register size is still suspect, and this new sign extension may not properly take place for 64-bit architectures using 32-bit addresses, but solving that will take a bit more examination in general. | |||
| 2024-08-12 | Add IL, intrinsics for TLB-related instructions | noone | |
| 2024-08-12 | Add intrinsics for some system instructions | noone | |
| Except for SYNCI, I didn't have any test cases for these, but they're fairly simple. | |||
| 2024-08-12 | Differentiate some enums in IL switch statement | noone | |
| This makes it easier to see which instructions still need to be lifted versus those which never should be lifted. | |||
| 2024-08-12 | Remove checks for 64-bit shift instructions | noone | |
| These aren't really needed; if it's for a 32-bit architecture that can't handle 64-bit shifts, then the instruction won't be decoded in the first place. Because the registerSize is derived from the address size, it may interfere with 64-bit architectures that are using signed 32-bit addresses. There are a few other places that check registerSize (for example, the 32->64 bit sign extension idiom and MADD, MADDU) that are suspect, but not included in this commit. The difference is that for 64-bit shifts, checking at all for the register size is the problem; for those, the check is still needed to figure out whether to sign extend or not, but the value of registerSize is suspect. | |||
| 2024-08-06 | Add flag role for carry flag when subtraction is implemented with addition | Rusty Wagner | |
| 2024-08-02 | Properly lift push r16 instructions in x86. Fix ↵ | Xusheng | |
| https://github.com/Vector35/binaryninja-api/issues/4028 | |||
| 2024-07-24 | change parameter name to align the function definition | Zichuan Li | |
| A user reported in public slack that the definition doesn't agree on endianness | |||
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index : public/binaryninja-api.git | |
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