| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-07-12 | Regenerate Cargo lock file after bindgen update. | Alexander Taylor | |
| 2024-07-09 | [arm64] cleaned up dangling else warnings and removed unneeded ENC_LDR_Q* ↵ | Galen Williamson | |
| case from neon_intrinsics.cpp | |||
| 2024-07-09 | Fix warning in mips arch (skip-note, skip-ci) | Mason Reed | |
| 2024-07-08 | Add Cavium Octeon MIPS Instructions and more general MIPS fixes | noone | |
| 2024-07-08 | [arm64] Full review of intrinsics; lifting of many instructions added, ↵ | Galen Williamson | |
| improved, and/or fixed Merged https://github.com/Vector35/binaryninja-api/pull/5461: Author: yrp <yrp604@protonmail.com> Date: Sat May 25 21:00:26 2024 -0700 arm64: lift sxtl, sxtl2, sshll, sshll2 Partial list of detailed changes squashed into this commit (see https://github.com/Vector35/binaryninja-api/tree/arm64_improving_intrinsics for detailed commit history): * add lifting for sshll/sxtl * reverted neon_intrinsics.cpp to restore scvtf intrinsics * lifted sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and changed the lifting of uxtl/2 to be consistent with sxtl/2 * reformatted arm64test.py and added tests for sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and uxtl/2 fix scvtf (unroll because no intrinsic) and fsub (missing register assignment) half-precision vector cases * added preferIntrinsics setting to arm64 * added lifting for movn * fixed incorrect int/float conversions for FMOV, made half-precision immediates survive the lift to M/HLIL * fix missing break in SCVT; optimize MOVK * improved preferIntrinsics * fixed bad lifting introduced for movn * fixed bad settings definition for preferIntrinsics * added intrinsic definition for DUP from general register * added direct lifting of scalar version of FADDP, and fixed intrinsics for vector version * added direct lifting of scalar version of FABD, and fixed intrinsics for vector version * fixes to test_gen.py: gets the correct encoding instead of sometimes getting fooled by the mnemonic * fixed lifting of UCVTF; reviewed/fixed all intrinsics through SQXTUN * reviewed/fixed remaining intrinsics after SQXTUN * added lifting for FNMUL * WIP intrinsics improvements * WIP intrinsics improvements 2 * WIP intrinsics improvements: FCVT*_asisdmisc_R * added B.AL, B.NV, CASP* * direct lifting of scalar FSQRT instruction * SETREG now elides setting of targeting zero registers * fixed test_gen.py to correctly regenerate arm64test.py * unroll vector MOV operations, USHL no longer uses intrinsic for scalars * updated existing tests in arm64test.py for latest lifting changes * fixed CASH* and CASB* incorrectly accessing temp register in comparison (resulting in comparing to NOP) * lifting all variants of TBL as intrinsic * fixes/improvements to test_gen.py * lifting all variants of TBX as intrinsic * added tests for CAS*, UMUL*, UADD*, FABD, FABS, FADDP, FMAX, FMAXNM, FMIN, FMINNM, FNEG, FNMUL, FCMEQ, FCMGE, FCMGT, FMLA, FMLS * added tests for all aliases of SBFM | |||
| 2024-06-19 | Add data_variable_at_address and fixed the type propagation issue in riscv | Zichuan Li | |
| 2024-06-13 | [arm64]: fix broken compilation on windows | Galen Williamson | |
| no Elvis operator ?:( api\arch\arm64\il.cpp(894): error C2059: syntax error: ':' api\arch\arm64\il.cpp(1839): error C7555: use of designated initializers requires at least '/std:c++20' | |||
| 2024-06-13 | [arm64] fixed lifting for LDADD*, filled in lifting for alias STADD*, fixed ↵ | Galen Williamson | |
| tests for recently added system registers dczid_el0 and ctr_el0; fixes #5603 | |||
| 2024-06-13 | [arm64] fixes and improvements to test_gen.py | Galen Williamson | |
| 2024-06-12 | Disassemble SFENCE.VM instruction | Mason Reed | |
| 2024-06-11 | More descriptive error for TP-relative reloc. | Alexander Taylor | |
| 2024-06-11 | Add some missing arm64 system registers | Josh Ferrell | |
| 2024-06-11 | Fix lifting of pair load operations when first and third operand are equal ↵ | Josh Ferrell | |
| and reduce code duplication | |||
| 2024-05-31 | improve efficiency | Zichuan Li | |
| 2024-05-31 | Fixed type propagation issue in AARCH64 and MIPS | Zichuan Li | |
| Previously, prtinf type library is not being appropriately applied. #3092 | |||
| 2024-05-30 | [arm64] lift scvtf | Galen Williamson | |
| * only scalar variants for integer and floating point * updated arm64test.py for scvtf * removed intrinsics for scvtf, scalar integer and floating point variants | |||
| 2024-05-29 | improve lifting of arm64 CSET instruction per Vector35/binaryninja-api#5134 | Galen Williamson | |
| 2024-05-29 | Fix crash when reopening a binary with a valid X86_64_RELOC_SUBTRACTOR entry | Josh Ferrell | |
| 2024-05-24 | arch: multiple delay slot support, suppress spurious mips warning | Ryan Snyder | |
| 2024-05-01 | riscv: account for minor rust API updates | Ryan Snyder | |
| 2024-04-25 | Recognize uClibc MIPS ELF PLT entries | Josh Ferrell | |
| 2024-04-12 | Prevent slowdown when compiling with clang on not mac | Josh Ferrell | |
| 2024-04-10 | Update xed to v2024.04.01 | Xusheng | |
| 2024-04-09 | riscv : Remove uses of BnString per #5244 | KyleMiles | |
| 2024-04-08 | Fix lifting for movs* and stos* instructions. | Brian Potchik | |
| 2024-03-26 | added lifting for EXTSW LD LDU LDUX LDX SLD SRAD SRADI SRD STD STDU STDUX STDX | Galen Williamson | |
| 2024-03-25 | [arch-x86] improve lifting for *movd* and *movq* instructions | Galen Williamson | |
| 2024-03-22 | Remove FloatTruncate as its implied by 'FloatToInt' | Peter LaFosse | |
| 2024-03-21 | Update to Rust 1.77 | Rusty Wagner | |
| 2024-03-20 | Implement Hash, PartialEq & Eq for riscv Register | mason | |
| 2024-03-15 | Separate local variable tokens in higher level ILs from stack variable ↵ | Rusty Wagner | |
| tokens in lower levels, and improve token usage in disassembly | |||
| 2024-03-14 | Update to Rust 1.76 | Rusty Wagner | |
| 2024-03-12 | moved over from https://github.com/Vector35/arch-armv7/pull/81 | Galen Williamson | |
| 2024-03-08 | Fix RISC-V CSRRW, CSRRS, and CSRRC instr disass | Pete Dietl | |
| Make the CSR instructions show the CSR 12-bit immediate operand as an unsigned integer. This is a special case of the I-instruction format, where it is same except that the 12-bit immediate is treated as unsigned rather than signed. | |||
| 2024-03-08 | Fix X86_64_RELOC_UNSIGNED not handling external symbols | Visual Ehrmanntraut | |
| Signed-off-by: Visual Ehrmanntraut <30368284+VisualEhrmanntraut@users.noreply.github.com> | |||
| 2024-03-05 | Move architecture modules into the API repo | Rusty Wagner | |
| 2024-02-01 | RISC-V: Fix disassembly of compressed JAL instruction | Pete Dietl | |
| Change integer register involved via compressed JAL instruction from 0 (x0 (zero)) to 1 (x1 (ra)) | |||
| 2024-01-04 | Add RISC-V relocations required by Linux kernel modules | Rusty Wagner | |
| 2024-01-04 | Add RISC-V architecture plugin | Rusty Wagner | |
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index : public/binaryninja-api.git | |
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