diff options
| author | Pete Dietl <petedietl@gmail.com> | 2024-01-31 22:41:21 -0800 |
|---|---|---|
| committer | Rusty Wagner <rusty.wagner@gmail.com> | 2024-02-01 12:41:28 -0500 |
| commit | d1cbe3f55e2b92b7acc0f9792ae6695153299f9c (patch) | |
| tree | 74e812c964b6decefe5af3b49ec9d0f1af90fee7 | |
| parent | 572344ae58da98d4fc8e2e210ccc61b258c765c0 (diff) | |
RISC-V: Fix disassembly of compressed JAL instruction
Change integer register involved via compressed JAL
instruction from 0 (x0 (zero)) to 1 (x1 (ra))
| -rw-r--r-- | arch/riscv/disasm/src/lib.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/disasm/src/lib.rs b/arch/riscv/disasm/src/lib.rs index 6762bb5d..b9505724 100644 --- a/arch/riscv/disasm/src/lib.rs +++ b/arch/riscv/disasm/src/lib.rs @@ -2395,7 +2395,7 @@ pub trait RiscVDisassembler: Sized + Copy + Clone { } 0b001_01 if int_width == 4 => { // JAL - Op::Jal(JTypeInst::new(IntReg::new(0), inst.cj_imm())?) + Op::Jal(JTypeInst::new(IntReg::new(1), inst.cj_imm())?) } 0b001_01 => { // ADDIW |