diff options
| author | Mark Rowe <mark@vector35.com> | 2025-09-18 11:46:39 -0700 |
|---|---|---|
| committer | Mark Rowe <mark@vector35.com> | 2025-09-25 08:41:48 -0700 |
| commit | 6e1306923c60b3d6c1cefb1fcc240f1a064d6f20 (patch) | |
| tree | 57fb65f74fecfa95dd394ecc5b664512d8f87609 /arch/arm64/disassembler/decode.c | |
| parent | 0deeb4a61749737b98f7946ec88b693068180e28 (diff) | |
[AArch64] Update disassembler based on 2025-06 ARM ISA data
Alongside this I also added support for decoding:
* LDR / STR (table)
* PMULLB / PMULLT
* ABS / CNT / CTZ
* SMIN / SMAX / UMIN / UMAX
* RPRFM
* PSEL
Note that while these instructions will now be disassembled, they are
not yet lifted to LLIL.
Additionally, I fixed a number of errors in the decoding of some less
commonly occurring instructions.
Diffstat (limited to 'arch/arm64/disassembler/decode.c')
| -rw-r--r-- | arch/arm64/disassembler/decode.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/disassembler/decode.c b/arch/arm64/disassembler/decode.c index b444bbcd..99d8bba0 100644 --- a/arch/arm64/disassembler/decode.c +++ b/arch/arm64/disassembler/decode.c @@ -10,8 +10,8 @@ int aarch64_decompose(uint32_t instructionValue, Instruction* instr, uint64_t ad ctx.halted = 1; // enable disassembly of exception instructions like DCPS1 ctx.insword = instructionValue; ctx.address = address; - ctx.features0 = ARCH_FEATURES_ALL; - ctx.features1 = ARCH_FEATURES_ALL; + ARCH_FEATURES_ENABLE_ALL(ctx.decode_features); + ARCH_FEATURES_ENABLE_ALL(ctx.pcode_features); ctx.EDSCR_HDE = 1; /* have the spec-generated code populate all the pcode variables */ |