diff options
| author | Mark Rowe <mark@vector35.com> | 2025-09-18 11:46:39 -0700 |
|---|---|---|
| committer | Mark Rowe <mark@vector35.com> | 2025-09-25 08:41:48 -0700 |
| commit | 6e1306923c60b3d6c1cefb1fcc240f1a064d6f20 (patch) | |
| tree | 57fb65f74fecfa95dd394ecc5b664512d8f87609 /arch/arm64/disassembler/sysregs_fmt_gen.c | |
| parent | 0deeb4a61749737b98f7946ec88b693068180e28 (diff) | |
[AArch64] Update disassembler based on 2025-06 ARM ISA data
Alongside this I also added support for decoding:
* LDR / STR (table)
* PMULLB / PMULLT
* ABS / CNT / CTZ
* SMIN / SMAX / UMIN / UMAX
* RPRFM
* PSEL
Note that while these instructions will now be disassembled, they are
not yet lifted to LLIL.
Additionally, I fixed a number of errors in the decoding of some less
commonly occurring instructions.
Diffstat (limited to 'arch/arm64/disassembler/sysregs_fmt_gen.c')
| -rw-r--r-- | arch/arm64/disassembler/sysregs_fmt_gen.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/disassembler/sysregs_fmt_gen.c b/arch/arm64/disassembler/sysregs_fmt_gen.c index 3a3a4767..4760d219 100644 --- a/arch/arm64/disassembler/sysregs_fmt_gen.c +++ b/arch/arm64/disassembler/sysregs_fmt_gen.c @@ -740,7 +740,7 @@ const char *get_system_register_name(enum SystemReg sr) case REG_CTR_EL0: return "ctr_el0"; case REG_DCZID_EL0: return "dczid_el0"; case REG_NZCV: return "nzcv"; - case REG_DAIF: return "daif"; + case REG_DAIF: return "daifset"; case REG_SVCR: return "svcr"; case REG_DIT: return "dit"; case REG_SSBS: return "ssbs"; @@ -1412,7 +1412,7 @@ const char *get_system_register_name(enum SystemReg sr) case REG_CNTPS_TVAL_EL1: return "cntps_tval_el1"; case REG_CNTPS_CTL_EL1: return "cntps_ctl_el1"; case REG_CNTPS_CVAL_EL1: return "cntps_cval_el1"; - case REG_PSTATE_SPSEL: return "pstate_spsel"; + case REG_PSTATE_SPSEL: return "spsel"; case REG_PWRDNSAVE0: return "pwrdnsave0"; case REG_NRG_ACC_CTL: return "nrg_acc_ctl"; case REG_AON_CNT0: return "aon_cnt0"; |