[aarch64] use static var to avoid recreation of sysregs vector

1 files changed, 209 insertions, 248 deletions

diff --git a/arch/arm64/disassembler/sysregs_gen.h b/arch/arm64/disassembler/sysregs_gen.h
index b7a16cd5..54978f45 100644
--- a/arch/arm64/disassembler/sysregs_gen.h
+++ b/arch/arm64/disassembler/sysregs_gen.h
@@ -1,11 +1,13 @@
+/* GENERATED FILE - DO NOT MODIFY - SUBMIT GITHUB ISSUE IF PROBLEM FOUND */
 #pragma once
 
 #include <stdbool.h>
 
-enum SystemReg {
+enum SystemReg 
+{
 	SYSREG_NONE=0,
 	REG_EDSCR                      =4 /* 4 */,  // S0_0_c0_c0_4 at min EL0: EDSCR
-	REG_EDPRSR                     =24 /* 24 */,  // S0_0_c0_c3_0 at min EL0: EDPRSR
+	REG_EDPRCR                     =24 /* 24 */,  // S0_0_c0_c3_0 at min EL0: EDPRCR
 	REG_UAOIMM                     =515 /* 515 */,  // S0_0_c4_c0_3 at min EL1: UAOIMM
 	REG_PANIMM                     =516 /* 516 */,  // S0_0_c4_c0_4 at min EL1: PANIMM
 	REG_SPSELIMM                   =517 /* 517 */,  // S0_0_c4_c0_5 at min EL1: SPSELIMM
@@ -141,11 +143,9 @@ enum SystemReg {
 	REG_OSLSR_EL1                  =32908 /* 32908 */,  // S2_0_c1_c1_4 at min EL1: OSLSR_EL1
 	REG_OSDLR_EL1                  =32924 /* 32924 */,  // S2_0_c1_c3_4 at min EL1: OSDLR_EL1
 	REG_DBGPRCR_EL1                =32932 /* 32932 */,  // S2_0_c1_c4_4 at min EL1: DBGPRCR_EL1
-	REG_CLAIMSET_EL1               =33734 /* 33734 */,  // S2_0_c7_c8_6 at min EL1: CLAIMSET_EL1
-	REG_DBGCLAIMSET_EL1            =33734 /* 33734 */,
-	REG_CLAIMCLR_EL1               =33742 /* 33742 */,  // S2_0_c7_c9_6 at min EL1: CLAIMCLR_EL1
-	REG_DBGCLAIMCLR_EL1            =33742 /* 33742 */,
-	REG_AUTHSTAT_EL1               =33782 /* 33782 */,  // S2_0_c7_c14_6 at min EL1: AUTHSTAT_EL1
+	REG_DBGCLAIMSET_EL1            =33734 /* 33734 */,  // S2_0_c7_c8_6 at min EL1: DBGCLAIMSET_EL1
+	REG_DBGCLAIMCLR_EL1            =33742 /* 33742 */,  // S2_0_c7_c9_6 at min EL1: DBGCLAIMCLR_EL1
+	REG_DBGAUTHSTAT_EL1            =33782 /* 33782 */,  // S2_0_c7_c14_6 at min EL1: DBGAUTHSTAT_EL1
 	REG_TRCTRACEIDR                =34817 /* 34817 */,
 	REG_TRCVICTLR                  =34818 /* 34818 */,
 	REG_TRCSEQEVR0                 =34820 /* 34820 */,
@@ -327,9 +327,8 @@ enum SystemReg {
 	REG_TEECR32_EL1                =36864 /* 36864 */,  // S2_2_c0_c0_0 at min EL1: TEECR32_EL1
 	REG_TEEHBR32_EL1               =36992 /* 36992 */,  // S2_2_c1_c0_0 at min EL1: TEEHBR32_EL1
 	REG_MDCCSR_EL0                 =38920 /* 38920 */,  // S2_3_c0_c1_0 at min EL1: MDCCSR_EL0
-	REG_MDDTR_EL0                  =38944 /* 38944 */,  // S2_3_c0_c4_0 at min EL1: MDDTR_EL0
-	REG_DBGDTR_EL0                 =38944 /* 38944 */,
-	REG_MDDTRTX_EL0                =38952 /* 38952 */,  // S2_3_c0_c5_0 at min EL1: MDDTRTX_EL0
+	REG_DBGDTR_EL0                 =38944 /* 38944 */,  // S2_3_c0_c4_0 at min EL0: DBGDTR_EL0
+	REG_DBGDTRRX_EL0               =38952 /* 38952 */,  // S2_3_c0_c5_0 at min EL0: DBGDTRRX_EL0
 	REG_DBGDTRTX_EL0               =38952 /* 38952 */,
 	REG_DBGVCR32_EL2               =41016 /* 41016 */,  // S2_4_c0_c7_0 at min EL2: DBGVCR32_EL2
 	REG_MIDR_EL1                   =49152 /* 49152 */,  // S3_0_c0_c0_0 at min EL1: MIDR_EL1
@@ -391,61 +390,39 @@ enum SystemReg {
 	REG_ID_AA64MMFR5_EL1           =49213 /* 49213 */,  // S3_0_c0_c7_5 at min EL1: ID_AA64MMFR5_EL1
 	REG_ID_AA64MMFR6_EL1           =49214 /* 49214 */,  // S3_0_c0_c7_6 at min EL1: ID_AA64MMFR6_EL1
 	REG_ID_AA64MMFR7_EL1           =49215 /* 49215 */,  // S3_0_c0_c7_7 at min EL1: ID_AA64MMFR7_EL1
-	REG_SCTLR_EL21                 =49280 /* 49280 */,  // S3_0_c1_c0_0 at min EL1: SCTLR_EL21
-	REG_SCTLR_EL1                  =49280 /* 49280 */,
-	REG_ACTLR_EL21                 =49281 /* 49281 */,  // S3_0_c1_c0_1 at min EL1: ACTLR_EL21
-	REG_ACTLR_EL1                  =49281 /* 49281 */,
-	REG_CPTR_EL21                  =49282 /* 49282 */,  // S3_0_c1_c0_2 at min EL1: CPTR_EL21
-	REG_CPACR_EL1                  =49282 /* 49282 */,
+	REG_SCTLR_EL1                  =49280 /* 49280 */,  // S3_0_c1_c0_0 at min EL1: SCTLR_EL1
+	REG_ACTLR_EL1                  =49281 /* 49281 */,  // S3_0_c1_c0_1 at min EL1: ACTLR_EL1
+	REG_CPACR_EL1                  =49282 /* 49282 */,  // S3_0_c1_c0_2 at min EL1: CPACR_EL1
 	REG_RGSR_EL1                   =49285 /* 49285 */,
 	REG_GCR_EL1                    =49286 /* 49286 */,
 	REG_TRFCR_EL1                  =49297 /* 49297 */,
 	REG_SMPRI_EL1                  =49300 /* 49300 */,  // S3_0_c1_c2_4 at min EL1: SMPRI_EL1
-	REG_SMCR_EL21                  =49302 /* 49302 */,  // S3_0_c1_c2_6 at min EL1: SMCR_EL21
-	REG_TTBR0_EL21                 =49408 /* 49408 */,  // S3_0_c2_c0_0 at min EL1: TTBR0_EL21
-	REG_TTBR0_EL1                  =49408 /* 49408 */,
-	REG_TTBR1_EL21                 =49409 /* 49409 */,  // S3_0_c2_c0_1 at min EL1: TTBR1_EL21
-	REG_TTBR1_EL1                  =49409 /* 49409 */,
-	REG_TCR_EL21                   =49410 /* 49410 */,  // S3_0_c2_c0_2 at min EL1: TCR_EL21
-	REG_TCR_EL1                    =49410 /* 49410 */,
-	REG_APIAKEYLO_EL21             =49416 /* 49416 */,  // S3_0_c2_c1_0 at min EL1: APIAKeyLo_EL21
-	REG_APIAKEYLO_EL1              =49416 /* 49416 */,
-	REG_APIAKEYHI_EL21             =49417 /* 49417 */,  // S3_0_c2_c1_1 at min EL1: APIAKeyHi_EL21
-	REG_APIAKEYHI_EL1              =49417 /* 49417 */,
-	REG_APIBKEYLO_EL21             =49418 /* 49418 */,  // S3_0_c2_c1_2 at min EL1: APIBKeyLo_EL21
-	REG_APIBKEYLO_EL1              =49418 /* 49418 */,
-	REG_APIBKEYHI_EL21             =49419 /* 49419 */,  // S3_0_c2_c1_3 at min EL1: APIBKeyHi_EL21
-	REG_APIBKEYHI_EL1              =49419 /* 49419 */,
-	REG_APDAKEYLO_EL21             =49424 /* 49424 */,  // S3_0_c2_c2_0 at min EL1: APDAKeyLo_EL21
-	REG_APDAKEYLO_EL1              =49424 /* 49424 */,
-	REG_APDAKEYHI_EL21             =49425 /* 49425 */,  // S3_0_c2_c2_1 at min EL1: APDAKeyHi_EL21
-	REG_APDAKEYHI_EL1              =49425 /* 49425 */,
-	REG_APDBKEYLO_EL21             =49426 /* 49426 */,  // S3_0_c2_c2_2 at min EL1: APDBKeyLo_EL21
-	REG_APDBKEYLO_EL1              =49426 /* 49426 */,
-	REG_APDBKEYHI_EL21             =49427 /* 49427 */,  // S3_0_c2_c2_3 at min EL1: APDBKeyHi_EL21
-	REG_APDBKEYHI_EL1              =49427 /* 49427 */,
-	REG_APGAKEYLO_EL21             =49432 /* 49432 */,  // S3_0_c2_c3_0 at min EL1: APGAKeyLo_EL21
-	REG_APGAKEYLO_EL1              =49432 /* 49432 */,
-	REG_APGAKEYHI_EL21             =49433 /* 49433 */,  // S3_0_c2_c3_1 at min EL1: APGAKeyHi_EL21
-	REG_APGAKEYHI_EL1              =49433 /* 49433 */,
-	REG_SPSR_EL21                  =49664 /* 49664 */,  // S3_0_c4_c0_0 at min EL1: SPSR_EL21
-	REG_SPSR_EL1                   =49664 /* 49664 */,
-	REG_ELR_EL21                   =49665 /* 49665 */,  // S3_0_c4_c0_1 at min EL1: ELR_EL21
-	REG_ELR_EL1                    =49665 /* 49665 */,
+	REG_SMCR_EL1                   =49302 /* 49302 */,  // S3_0_c1_c2_6 at min EL1: SMCR_EL1
+	REG_TTBR0_EL1                  =49408 /* 49408 */,  // S3_0_c2_c0_0 at min EL1: TTBR0_EL1
+	REG_TTBR1_EL1                  =49409 /* 49409 */,  // S3_0_c2_c0_1 at min EL1: TTBR1_EL1
+	REG_TCR_EL1                    =49410 /* 49410 */,  // S3_0_c2_c0_2 at min EL1: TCR_EL1
+	REG_APIAKEYLO_EL1              =49416 /* 49416 */,  // S3_0_c2_c1_0 at min EL1: APIAKeyLo_EL1
+	REG_APIAKEYHI_EL1              =49417 /* 49417 */,  // S3_0_c2_c1_1 at min EL1: APIAKeyHi_EL1
+	REG_APIBKEYLO_EL1              =49418 /* 49418 */,  // S3_0_c2_c1_2 at min EL1: APIBKeyLo_EL1
+	REG_APIBKEYHI_EL1              =49419 /* 49419 */,  // S3_0_c2_c1_3 at min EL1: APIBKeyHi_EL1
+	REG_APDAKEYLO_EL1              =49424 /* 49424 */,  // S3_0_c2_c2_0 at min EL1: APDAKeyLo_EL1
+	REG_APDAKEYHI_EL1              =49425 /* 49425 */,  // S3_0_c2_c2_1 at min EL1: APDAKeyHi_EL1
+	REG_APDBKEYLO_EL1              =49426 /* 49426 */,  // S3_0_c2_c2_2 at min EL1: APDBKeyLo_EL1
+	REG_APDBKEYHI_EL1              =49427 /* 49427 */,  // S3_0_c2_c2_3 at min EL1: APDBKeyHi_EL1
+	REG_APGAKEYLO_EL1              =49432 /* 49432 */,  // S3_0_c2_c3_0 at min EL1: APGAKeyLo_EL1
+	REG_APGAKEYHI_EL1              =49433 /* 49433 */,  // S3_0_c2_c3_1 at min EL1: APGAKeyHi_EL1
+	REG_SPSR_EL1                   =49664 /* 49664 */,  // S3_0_c4_c0_0 at min EL1: SPSR_EL1
+	REG_ELR_EL1                    =49665 /* 49665 */,  // S3_0_c4_c0_1 at min EL1: ELR_EL1
 	REG_SP_EL0                     =49672 /* 49672 */,  // S3_0_c4_c1_0 at min EL1: SP_EL0
 	REG_SPSEL                      =49680 /* 49680 */,  // S3_0_c4_c2_0 at min EL1: SPSEL
-	REG_NESTEDCURRENTEL            =49682 /* 49682 */,  // S3_0_c4_c2_2 at min EL1: NestedCurrentEL
-	REG_CURRENTEL                  =49682 /* 49682 */,
+	REG_CURRENTEL                  =49682 /* 49682 */,  // S3_0_c4_c2_2 at min EL1: CurrentEL
 	REG_PAN                        =49683 /* 49683 */,  // S3_0_c4_c2_3 at min EL1: PAN
 	REG_UAO                        =49684 /* 49684 */,  // S3_0_c4_c2_4 at min EL1: UAO
 	REG_ICV_PMR_EL1                =49712 /* 49712 */,  // S3_0_c4_c6_0 at min EL1: ICV_PMR_EL1
 	REG_ICC_PMR_EL1                =49712 /* 49712 */,
-	REG_AFSR0_EL21                 =49800 /* 49800 */,  // S3_0_c5_c1_0 at min EL1: AFSR0_EL21
-	REG_AFSR0_EL1                  =49800 /* 49800 */,
-	REG_AFSR1_EL21                 =49801 /* 49801 */,  // S3_0_c5_c1_1 at min EL1: AFSR1_EL21
-	REG_AFSR1_EL1                  =49801 /* 49801 */,
-	REG_ESR_EL21                   =49808 /* 49808 */,  // S3_0_c5_c2_0 at min EL1: ESR_EL21
-	REG_ESR_EL1                    =49808 /* 49808 */,
+	REG_AFSR0_EL1                  =49800 /* 49800 */,  // S3_0_c5_c1_0 at min EL1: AFSR0_EL1
+	REG_AFSR1_EL1                  =49801 /* 49801 */,  // S3_0_c5_c1_1 at min EL1: AFSR1_EL1
+	REG_ESR_EL1                    =49808 /* 49808 */,  // S3_0_c5_c2_0 at min EL1: ESR_EL1
 	REG_ERRIDR_EL1                 =49816 /* 49816 */,  // S3_0_c5_c3_0 at min EL1: ERRIDR_EL1
 	REG_ERRSELR_EL1                =49817 /* 49817 */,
 	REG_ERXCTLR_EL1                =49825 /* 49825 */,
@@ -460,8 +437,7 @@ enum SystemReg {
 	REG_ERXTS_EL1                  =49839 /* 49839 */,
 	REG_TFSR_EL1                   =49840 /* 49840 */,
 	REG_TFSRE0_EL1                 =49841 /* 49841 */,
-	REG_FAR_EL21                   =49920 /* 49920 */,  // S3_0_c6_c0_0 at min EL1: FAR_EL21
-	REG_FAR_EL1                    =49920 /* 49920 */,
+	REG_FAR_EL1                    =49920 /* 49920 */,  // S3_0_c6_c0_0 at min EL1: FAR_EL1
 	REG_PAR_EL1                    =50080 /* 50080 */,  // S3_0_c7_c4_0 at min EL1: PAR_EL1
 	REG_PMSCR_EL1                  =50376 /* 50376 */,
 	REG_PMSICR_EL1                 =50378 /* 50378 */,
@@ -483,10 +459,8 @@ enum SystemReg {
 	REG_PMINTENSET_EL1             =50417 /* 50417 */,
 	REG_PMINTENCLR_EL1             =50418 /* 50418 */,
 	REG_PMMIR_EL1                  =50422 /* 50422 */,
-	REG_MAIR_EL21                  =50448 /* 50448 */,  // S3_0_c10_c2_0 at min EL1: MAIR_EL21
-	REG_MAIR_EL1                   =50448 /* 50448 */,
-	REG_AMAIR_EL21                 =50456 /* 50456 */,  // S3_0_c10_c3_0 at min EL1: AMAIR_EL21
-	REG_AMAIR_EL1                  =50456 /* 50456 */,
+	REG_MAIR_EL1                   =50448 /* 50448 */,  // S3_0_c10_c2_0 at min EL1: MAIR_EL1
+	REG_AMAIR_EL1                  =50456 /* 50456 */,  // S3_0_c10_c3_0 at min EL1: AMAIR_EL1
 	REG_LORSA_EL1                  =50464 /* 50464 */,  // S3_0_c10_c4_0 at min EL1: LORSA_EL1
 	REG_LOREA_EL1                  =50465 /* 50465 */,  // S3_0_c10_c4_1 at min EL1: LOREA_EL1
 	REG_LORN_EL1                   =50466 /* 50466 */,  // S3_0_c10_c4_2 at min EL1: LORN_EL1
@@ -494,10 +468,10 @@ enum SystemReg {
 	REG_LORID_EL1                  =50471 /* 50471 */,  // S3_0_c10_c4_7 at min EL1: LORID_EL1
 	REG_MPAM1_EL1                  =50472 /* 50472 */,
 	REG_MPAM0_EL1                  =50473 /* 50473 */,
-	REG_CTRR_C_LWR_EL21            =50560 /* 50560 */,  // S3_0_c11_c0_0 at min EL1: CTRR_C_LWR_EL21
-	REG_CTRR_C_UPR_EL21            =50561 /* 50561 */,  // S3_0_c11_c0_1 at min EL1: CTRR_C_UPR_EL21
-	REG_CTRR_D_LWR_EL21            =50562 /* 50562 */,  // S3_0_c11_c0_2 at min EL1: CTRR_D_LWR_EL21
-	REG_CTRR_D_UPR_EL21            =50563 /* 50563 */,  // S3_0_c11_c0_3 at min EL1: CTRR_D_UPR_EL21
+	REG_CTRR_C_LWR_EL1             =50560 /* 50560 */,  // S3_0_c11_c0_0 at min EL1: CTRR_C_LWR_EL1
+	REG_CTRR_C_UPR_EL1             =50561 /* 50561 */,  // S3_0_c11_c0_1 at min EL1: CTRR_C_UPR_EL1
+	REG_CTRR_D_LWR_EL1             =50562 /* 50562 */,  // S3_0_c11_c0_2 at min EL1: CTRR_D_LWR_EL1
+	REG_CTRR_D_UPR_EL1             =50563 /* 50563 */,  // S3_0_c11_c0_3 at min EL1: CTRR_D_UPR_EL1
 	REG_CTRR_C_LWR_EL12            =50564 /* 50564 */,  // S3_0_c11_c0_4 at min EL2: CTRR_C_LWR_EL12
 	REG_CTRR_C_UPR_EL12            =50565 /* 50565 */,  // S3_0_c11_c0_5 at min EL2: CTRR_C_UPR_EL12
 	REG_CTRR_D_LWR_EL12            =50566 /* 50566 */,  // S3_0_c11_c0_6 at min EL2: CTRR_D_LWR_EL12
@@ -506,20 +480,20 @@ enum SystemReg {
 	REG_CTRR_C_UPR_EL2             =50569 /* 50569 */,  // S3_0_c11_c1_1 at min EL2: CTRR_C_UPR_EL2
 	REG_CTRR_D_LWR_EL2             =50570 /* 50570 */,  // S3_0_c11_c1_2 at min EL2: CTRR_D_LWR_EL2
 	REG_CTRR_D_UPR_EL2             =50571 /* 50571 */,  // S3_0_c11_c1_3 at min EL2: CTRR_D_UPR_EL2
-	REG_CTRR_C_CTL_EL21            =50572 /* 50572 */,  // S3_0_c11_c1_4 at min EL1: CTRR_C_CTL_EL21
-	REG_CTRR_D_CTL_EL21            =50573 /* 50573 */,  // S3_0_c11_c1_5 at min EL1: CTRR_D_CTL_EL21
+	REG_CTRR_C_CTL_EL1             =50572 /* 50572 */,  // S3_0_c11_c1_4 at min EL1: CTRR_C_CTL_EL1
+	REG_CTRR_D_CTL_EL1             =50573 /* 50573 */,  // S3_0_c11_c1_5 at min EL1: CTRR_D_CTL_EL1
 	REG_CTRR_C_CTL_EL12            =50574 /* 50574 */,  // S3_0_c11_c1_6 at min EL2: CTRR_C_CTL_EL12
 	REG_CTRR_D_CTL_EL12            =50575 /* 50575 */,  // S3_0_c11_c1_7 at min EL2: CTRR_D_CTL_EL12
 	REG_CTRR_C_CTL_EL2             =50576 /* 50576 */,  // S3_0_c11_c2_0 at min EL2: CTRR_C_CTL_EL2
 	REG_CTRR_D_CTL_EL2             =50577 /* 50577 */,  // S3_0_c11_c2_1 at min EL2: CTRR_D_CTL_EL2
-	REG_CTXR_A_LWR_EL21            =50578 /* 50578 */,  // S3_0_c11_c2_2 at min EL1: CTXR_A_LWR_EL21
-	REG_CTXR_A_UPR_EL21            =50579 /* 50579 */,  // S3_0_c11_c2_3 at min EL1: CTXR_A_UPR_EL21
-	REG_CTXR_B_LWR_EL21            =50580 /* 50580 */,  // S3_0_c11_c2_4 at min EL1: CTXR_B_LWR_EL21
-	REG_CTXR_B_UPR_EL21            =50581 /* 50581 */,  // S3_0_c11_c2_5 at min EL1: CTXR_B_UPR_EL21
-	REG_CTXR_C_LWR_EL21            =50582 /* 50582 */,  // S3_0_c11_c2_6 at min EL1: CTXR_C_LWR_EL21
-	REG_CTXR_C_UPR_EL21            =50583 /* 50583 */,  // S3_0_c11_c2_7 at min EL1: CTXR_C_UPR_EL21
-	REG_CTXR_D_LWR_EL21            =50584 /* 50584 */,  // S3_0_c11_c3_0 at min EL1: CTXR_D_LWR_EL21
-	REG_CTXR_D_UPR_EL21            =50585 /* 50585 */,  // S3_0_c11_c3_1 at min EL1: CTXR_D_UPR_EL21
+	REG_CTXR_A_LWR_EL1             =50578 /* 50578 */,  // S3_0_c11_c2_2 at min EL1: CTXR_A_LWR_EL1
+	REG_CTXR_A_UPR_EL1             =50579 /* 50579 */,  // S3_0_c11_c2_3 at min EL1: CTXR_A_UPR_EL1
+	REG_CTXR_B_LWR_EL1             =50580 /* 50580 */,  // S3_0_c11_c2_4 at min EL1: CTXR_B_LWR_EL1
+	REG_CTXR_B_UPR_EL1             =50581 /* 50581 */,  // S3_0_c11_c2_5 at min EL1: CTXR_B_UPR_EL1
+	REG_CTXR_C_LWR_EL1             =50582 /* 50582 */,  // S3_0_c11_c2_6 at min EL1: CTXR_C_LWR_EL1
+	REG_CTXR_C_UPR_EL1             =50583 /* 50583 */,  // S3_0_c11_c2_7 at min EL1: CTXR_C_UPR_EL1
+	REG_CTXR_D_LWR_EL1             =50584 /* 50584 */,  // S3_0_c11_c3_0 at min EL1: CTXR_D_LWR_EL1
+	REG_CTXR_D_UPR_EL1             =50585 /* 50585 */,  // S3_0_c11_c3_1 at min EL1: CTXR_D_UPR_EL1
 	REG_CTXR_A_LWR_EL12            =50586 /* 50586 */,  // S3_0_c11_c3_2 at min EL2: CTXR_A_LWR_EL12
 	REG_CTXR_A_UPR_EL12            =50587 /* 50587 */,  // S3_0_c11_c3_3 at min EL2: CTXR_A_UPR_EL12
 	REG_CTXR_B_LWR_EL12            =50588 /* 50588 */,  // S3_0_c11_c3_4 at min EL2: CTXR_B_LWR_EL12
@@ -536,10 +510,10 @@ enum SystemReg {
 	REG_CTXR_C_UPR_EL2             =50599 /* 50599 */,  // S3_0_c11_c4_7 at min EL2: CTXR_C_UPR_EL2
 	REG_CTXR_D_LWR_EL2             =50600 /* 50600 */,  // S3_0_c11_c5_0 at min EL2: CTXR_D_LWR_EL2
 	REG_CTXR_D_UPR_EL2             =50601 /* 50601 */,  // S3_0_c11_c5_1 at min EL2: CTXR_D_UPR_EL2
-	REG_CTXR_A_CTL_EL21            =50602 /* 50602 */,  // S3_0_c11_c5_2 at min EL1: CTXR_A_CTL_EL21
-	REG_CTXR_B_CTL_EL21            =50603 /* 50603 */,  // S3_0_c11_c5_3 at min EL1: CTXR_B_CTL_EL21
-	REG_CTXR_C_CTL_EL21            =50604 /* 50604 */,  // S3_0_c11_c5_4 at min EL1: CTXR_C_CTL_EL21
-	REG_CTXR_D_CTL_EL21            =50605 /* 50605 */,  // S3_0_c11_c5_5 at min EL1: CTXR_D_CTL_EL21
+	REG_CTXR_A_CTL_EL1             =50602 /* 50602 */,  // S3_0_c11_c5_2 at min EL1: CTXR_A_CTL_EL1
+	REG_CTXR_B_CTL_EL1             =50603 /* 50603 */,  // S3_0_c11_c5_3 at min EL1: CTXR_B_CTL_EL1
+	REG_CTXR_C_CTL_EL1             =50604 /* 50604 */,  // S3_0_c11_c5_4 at min EL1: CTXR_C_CTL_EL1
+	REG_CTXR_D_CTL_EL1             =50605 /* 50605 */,  // S3_0_c11_c5_5 at min EL1: CTXR_D_CTL_EL1
 	REG_CTXR_A_CTL_EL12            =50606 /* 50606 */,  // S3_0_c11_c5_6 at min EL2: CTXR_A_CTL_EL12
 	REG_CTXR_B_CTL_EL12            =50607 /* 50607 */,  // S3_0_c11_c5_7 at min EL2: CTXR_B_CTL_EL12
 	REG_CTXR_C_CTL_EL12            =50608 /* 50608 */,  // S3_0_c11_c6_0 at min EL2: CTXR_C_CTL_EL12
@@ -566,8 +540,7 @@ enum SystemReg {
 	REG_ACC_CTXR_B_CTL_EL2         =50629 /* 50629 */,  // S3_0_c11_c8_5 at min EL2: ACC_CTXR_B_CTL_EL2
 	REG_ACC_CTXR_C_CTL_EL2         =50630 /* 50630 */,  // S3_0_c11_c8_6 at min EL2: ACC_CTXR_C_CTL_EL2
 	REG_ACC_CTXR_D_CTL_EL2         =50631 /* 50631 */,  // S3_0_c11_c8_7 at min EL2: ACC_CTXR_D_CTL_EL2
-	REG_VBAR_EL21                  =50688 /* 50688 */,  // S3_0_c12_c0_0 at min EL1: VBAR_EL21
-	REG_VBAR_EL1                   =50688 /* 50688 */,
+	REG_VBAR_EL1                   =50688 /* 50688 */,  // S3_0_c12_c0_0 at min EL1: VBAR_EL1
 	REG_RVBAR_EL1                  =50689 /* 50689 */,  // S3_0_c12_c0_1 at min EL1: RVBAR_EL1
 	REG_RMR_EL1                    =50690 /* 50690 */,  // S3_0_c12_c0_2 at min EL1: RMR_EL1
 	REG_ISR_EL1                    =50696 /* 50696 */,  // S3_0_c12_c1_0 at min EL1: ISR_EL1
@@ -596,7 +569,7 @@ enum SystemReg {
 	REG_ICV_EOIR1_EL1              =50785 /* 50785 */,  // S3_0_c12_c12_1 at min EL1: ICV_EOIR1_EL1
 	REG_ICC_EOIR1_EL1              =50785 /* 50785 */,
 	REG_ICV_HPPIR1_EL1             =50786 /* 50786 */,  // S3_0_c12_c12_2 at min EL1: ICV_HPPIR1_EL1
-	REG_ICV_BPR1_EL1               =50787 /* 50787 */,  // S3_0_c12_c12_3 at min EL1: ICV_BPR1_EL1
+	REG_ICV_BPR1CBPR_EL1           =50787 /* 50787 */,  // S3_0_c12_c12_3 at min EL1: ICV_BPR1CBPR_EL1
 	REG_ICC_BPR1_EL1               =50787 /* 50787 */,
 	REG_ICV_CTLR_EL1               =50788 /* 50788 */,  // S3_0_c12_c12_4 at min EL1: ICV_CTLR_EL1
 	REG_ICC_CTLR_EL1               =50788 /* 50788 */,
@@ -606,12 +579,10 @@ enum SystemReg {
 	REG_ICV_IGRPEN1_EL1            =50791 /* 50791 */,  // S3_0_c12_c12_7 at min EL1: ICV_IGRPEN1_EL1
 	REG_ICC_IGRPEN1_EL1            =50791 /* 50791 */,
 	REG_ICC_SEIEN_EL1              =50792 /* 50792 */,
-	REG_CONTEXTIDR_EL21            =50817 /* 50817 */,  // S3_0_c13_c0_1 at min EL1: CONTEXTIDR_EL21
-	REG_CONTEXTIDR_EL1             =50817 /* 50817 */,
+	REG_CONTEXTIDR_EL1             =50817 /* 50817 */,  // S3_0_c13_c0_1 at min EL1: CONTEXTIDR_EL1
 	REG_TPIDR_EL1                  =50820 /* 50820 */,  // S3_0_c13_c0_4 at min EL1: TPIDR_EL1
-	REG_SCXTNUM_EL21               =50823 /* 50823 */,  // S3_0_c13_c0_7 at min EL1: SCXTNUM_EL21
-	REG_SCXTNUM_EL1                =50823 /* 50823 */,
-	REG_REDIR_CNTKCTL_EL1          =50952 /* 50952 */,  // S3_0_c14_c1_0 at min EL1: REDIR_CNTKCTL_EL1
+	REG_SCXTNUM_EL1                =50823 /* 50823 */,  // S3_0_c13_c0_7 at min EL1: SCXTNUM_EL1
+	REG_CNTHCTL_EL21               =50952 /* 50952 */,  // S3_0_c14_c1_0 at min EL1: CNTHCTL_EL21
 	REG_CNTKCTL_EL1                =50952 /* 50952 */,
 	REG_HID0                       =51072 /* 51072 */,  // S3_0_c15_c0_0 at min EL1: HID0
 	REG_HID25                      =51074 /* 51074 */,  // S3_0_c15_c0_2 at min EL1: HID25
@@ -658,79 +629,79 @@ enum SystemReg {
 	REG_HID17                      =51197 /* 51197 */,  // S3_0_c15_c15_5 at min EL1: HID17
 	REG_HID24                      =51198 /* 51198 */,  // S3_0_c15_c15_6 at min EL1: HID24
 	REG_HID35                      =51199 /* 51199 */,  // S3_0_c15_c15_7 at min EL1: HID35
-	REG_CCSIDRPL1_I_EL1            =51200 /* 51200 */,  // S3_1_c0_c0_0 at min EL1: CCSIDRPL1_I_EL1
+	REG_CCSIDR_EL1                 =51200 /* 51200 */,  // S3_1_c0_c0_0 at min EL1: CCSIDR_EL1
 	REG_CLIDR_EL1                  =51201 /* 51201 */,  // S3_1_c0_c0_1 at min EL1: CLIDR_EL1
 	REG_SMIDR_EL1                  =51206 /* 51206 */,  // S3_1_c0_c0_6 at min EL1: SMIDR_EL1
 	REG_AIDR_EL1                   =51207 /* 51207 */,  // S3_1_c0_c0_7 at min EL1: AIDR_EL1
 	REG_PMCR0_EL1                  =53120 /* 53120 */,  // S3_1_c15_c0_0 at min EL1: PMCR0_EL1
 	REG_APPL_CONTEXTPTR            =53121 /* 53121 */,  // S3_1_c15_c0_1 at min EL1: APPL_CONTEXTPTR
-	REG_LD_LATPROF_CTL_EL21        =53122 /* 53122 */,  // S3_1_c15_c0_2 at min EL1: LD_LATPROF_CTL_EL21
+	REG_LD_LATPROF_CTL_EL1         =53122 /* 53122 */,  // S3_1_c15_c0_2 at min EL1: LD_LATPROF_CTL_EL1
 	REG_AON_CPU_MSTALL_CTL01_EL1   =53123 /* 53123 */,  // S3_1_c15_c0_3 at min EL1: AON_CPU_MSTALL_CTL01_EL1
 	REG_PM_MEMFLT_CTL23_EL1        =53124 /* 53124 */,  // S3_1_c15_c0_4 at min EL1: PM_MEMFLT_CTL23_EL1
-	REG_REDIR_ACNTV_CTL_EL0        =53125 /* 53125 */,  // S3_1_c15_c0_5 at min EL1: REDIR_ACNTV_CTL_EL0
-	REG_LCL_ACNTVCTSS_NOREDIR_EL0  =53126 /* 53126 */,  // S3_1_c15_c0_6 at min EL1: LCL_ACNTVCTSS_NOREDIR_EL0
-	REG_PMCR1_EL21                 =53128 /* 53128 */,  // S3_1_c15_c1_0 at min EL1: PMCR1_EL21
+	REG_AGTCNTHV_CTL_EL21          =53125 /* 53125 */,  // S3_1_c15_c0_5 at min EL1: AGTCNTHV_CTL_EL21
+	REG_AGTCNTVCTSS_NOREDIR_EL0    =53126 /* 53126 */,  // S3_1_c15_c0_6 at min EL1: AGTCNTVCTSS_NOREDIR_EL0
+	REG_PMCR1_EL1                  =53128 /* 53128 */,  // S3_1_c15_c1_0 at min EL1: PMCR1_EL1
 	REG_LD_LATPROF_CTR_EL1         =53130 /* 53130 */,  // S3_1_c15_c1_2 at min EL1: LD_LATPROF_CTR_EL1
 	REG_AON_CPU_MSTALL_CTL23_EL1   =53131 /* 53131 */,  // S3_1_c15_c1_3 at min EL1: AON_CPU_MSTALL_CTL23_EL1
 	REG_PM_MEMFLT_CTL45_EL1        =53132 /* 53132 */,  // S3_1_c15_c1_4 at min EL1: PM_MEMFLT_CTL45_EL1
-	REG_AGTCNTRDIR_EL21            =53133 /* 53133 */,  // S3_1_c15_c1_5 at min EL1: AGTCNTRDIR_EL21
-	REG_AGTCNTKCTL_NOREDIR_EL1     =53134 /* 53134 */,  // S3_1_c15_c1_6 at min EL1: AGTCNTKCTL_NOREDIR_EL1
+	REG_AGTCNTRDIR_EL1             =53133 /* 53133 */,  // S3_1_c15_c1_5 at min EL1: AGTCNTRDIR_EL1
+	REG_AGTCNTHCTL_NOREDIR_EL21    =53134 /* 53134 */,  // S3_1_c15_c1_6 at min EL1: AGTCNTHCTL_NOREDIR_EL21
 	REG_PMCR2_EL1                  =53136 /* 53136 */,  // S3_1_c15_c2_0 at min EL1: PMCR2_EL1
 	REG_LD_LATPROF_STS_EL1         =53138 /* 53138 */,  // S3_1_c15_c2_2 at min EL1: LD_LATPROF_STS_EL1
 	REG_AON_CPU_MSTALL_CTL45_EL1   =53139 /* 53139 */,  // S3_1_c15_c2_3 at min EL1: AON_CPU_MSTALL_CTL45_EL1
-	REG_REDIR_ACNTHP_CVAL_EL2      =53140 /* 53140 */,  // S3_1_c15_c2_4 at min EL2: REDIR_ACNTHP_CVAL_EL2
-	REG_LCL_CNTVCT_NOREDIR_EL0     =53141 /* 53141 */,  // S3_1_c15_c2_5 at min EL1: LCL_CNTVCT_NOREDIR_EL0
-	REG_AGTCNTP_CVAL_NOREDIR_EL0   =53142 /* 53142 */,  // S3_1_c15_c2_6 at min EL1: AGTCNTP_CVAL_NOREDIR_EL0
+	REG_AGTCNTHP_CVAL_EL2          =53140 /* 53140 */,  // S3_1_c15_c2_4 at min EL2: AGTCNTHP_CVAL_EL2
+	REG_CNTVCT_NOREDIR_EL0         =53141 /* 53141 */,  // S3_1_c15_c2_5 at min EL1: CNTVCT_NOREDIR_EL0
+	REG_AGTCNTHP_CVAL_NOREDIR_EL21 =53142 /* 53142 */,  // S3_1_c15_c2_6 at min EL1: AGTCNTHP_CVAL_NOREDIR_EL21
 	REG_PMCR3_EL1                  =53144 /* 53144 */,  // S3_1_c15_c3_0 at min EL1: PMCR3_EL1
 	REG_LD_LATPROF_INF_EL1         =53146 /* 53146 */,  // S3_1_c15_c3_2 at min EL1: LD_LATPROF_INF_EL1
 	REG_AON_CPU_MSTALL_CTL67_EL1   =53147 /* 53147 */,  // S3_1_c15_c3_3 at min EL1: AON_CPU_MSTALL_CTL67_EL1
-	REG_REDIR_ACNTHP_TVAL_EL2      =53148 /* 53148 */,  // S3_1_c15_c3_4 at min EL2: REDIR_ACNTHP_TVAL_EL2
-	REG_LCL_CNTPCTSS_NOREDIR_EL0   =53149 /* 53149 */,  // S3_1_c15_c3_5 at min EL1: LCL_CNTPCTSS_NOREDIR_EL0
-	REG_AGTCNTP_TVAL_NOREDIR_EL0   =53150 /* 53150 */,  // S3_1_c15_c3_6 at min EL1: AGTCNTP_TVAL_NOREDIR_EL0
+	REG_AGTCNTHP_TVAL_EL2          =53148 /* 53148 */,  // S3_1_c15_c3_4 at min EL2: AGTCNTHP_TVAL_EL2
+	REG_CNTPCTSS_NOREDIR_EL0       =53149 /* 53149 */,  // S3_1_c15_c3_5 at min EL1: CNTPCTSS_NOREDIR_EL0
+	REG_AGTCNTHP_TVAL_NOREDIR_EL21 =53150 /* 53150 */,  // S3_1_c15_c3_6 at min EL1: AGTCNTHP_TVAL_NOREDIR_EL21
 	REG_PMCR4_EL1                  =53152 /* 53152 */,  // S3_1_c15_c4_0 at min EL1: PMCR4_EL1
 	REG_LD_LATPROF_CTL_EL2         =53154 /* 53154 */,  // S3_1_c15_c4_2 at min EL2: LD_LATPROF_CTL_EL2
 	REG_AON_CPU_MEMFLT_CTL01_EL1   =53155 /* 53155 */,  // S3_1_c15_c4_3 at min EL1: AON_CPU_MEMFLT_CTL01_EL1
-	REG_REDIR_ACNTHP_CTL_EL2       =53156 /* 53156 */,  // S3_1_c15_c4_4 at min EL2: REDIR_ACNTHP_CTL_EL2
-	REG_LCL_CNTVCTSS_NOREDIR_EL0   =53157 /* 53157 */,  // S3_1_c15_c4_5 at min EL1: LCL_CNTVCTSS_NOREDIR_EL0
-	REG_AGTCNTP_CTL_NOREDIR_EL0    =53158 /* 53158 */,  // S3_1_c15_c4_6 at min EL1: AGTCNTP_CTL_NOREDIR_EL0
+	REG_AGTCNTHP_CTL_EL2           =53156 /* 53156 */,  // S3_1_c15_c4_4 at min EL2: AGTCNTHP_CTL_EL2
+	REG_CNTVCTSS_NOREDIR_EL0       =53157 /* 53157 */,  // S3_1_c15_c4_5 at min EL1: CNTVCTSS_NOREDIR_EL0
+	REG_AGTCNTHP_CTL_NOREDIR_EL21  =53158 /* 53158 */,  // S3_1_c15_c4_6 at min EL1: AGTCNTHP_CTL_NOREDIR_EL21
 	REG_PMESR0_EL1                 =53160 /* 53160 */,  // S3_1_c15_c5_0 at min EL1: PMESR0_EL1
 	REG_LD_LATPROF_CMD_EL1         =53162 /* 53162 */,  // S3_1_c15_c5_2 at min EL1: LD_LATPROF_CMD_EL1
 	REG_AON_CPU_MEMFLT_CTL23_EL1   =53163 /* 53163 */,  // S3_1_c15_c5_3 at min EL1: AON_CPU_MEMFLT_CTL23_EL1
-	REG_REDIR_ACNTHV_CVAL_EL2      =53164 /* 53164 */,  // S3_1_c15_c5_4 at min EL2: REDIR_ACNTHV_CVAL_EL2
-	REG_AGTCNTV_CVAL_NOREDIR_EL0   =53166 /* 53166 */,  // S3_1_c15_c5_6 at min EL1: AGTCNTV_CVAL_NOREDIR_EL0
+	REG_AGTCNTHV_CVAL_EL2          =53164 /* 53164 */,  // S3_1_c15_c5_4 at min EL2: AGTCNTHV_CVAL_EL2
+	REG_AGTCNTHV_CVAL_NOREDIR_EL21 =53166 /* 53166 */,  // S3_1_c15_c5_6 at min EL1: AGTCNTHV_CVAL_NOREDIR_EL21
 	REG_PMESR1_EL1                 =53168 /* 53168 */,  // S3_1_c15_c6_0 at min EL1: PMESR1_EL1
 	REG_PMCR1_EL2                  =53170 /* 53170 */,  // S3_1_c15_c6_2 at min EL2: PMCR1_EL2
 	REG_AON_CPU_MEMFLT_CTL45_EL1   =53171 /* 53171 */,  // S3_1_c15_c6_3 at min EL1: AON_CPU_MEMFLT_CTL45_EL1
-	REG_REDIR_ACNTHV_TVAL_EL2      =53172 /* 53172 */,  // S3_1_c15_c6_4 at min EL2: REDIR_ACNTHV_TVAL_EL2
-	REG_CNTKCTL_NOREDIR_EL1        =53173 /* 53173 */,  // S3_1_c15_c6_5 at min EL1: CNTKCTL_NOREDIR_EL1
-	REG_AGTCNTV_TVAL_NOREDIR_EL0   =53174 /* 53174 */,  // S3_1_c15_c6_6 at min EL1: AGTCNTV_TVAL_NOREDIR_EL0
+	REG_AGTCNTHV_TVAL_EL2          =53172 /* 53172 */,  // S3_1_c15_c6_4 at min EL2: AGTCNTHV_TVAL_EL2
+	REG_CNTHCTL_NOREDIR_EL21       =53173 /* 53173 */,  // S3_1_c15_c6_5 at min EL1: CNTHCTL_NOREDIR_EL21
+	REG_AGTCNTHV_TVAL_NOREDIR_EL21 =53174 /* 53174 */,  // S3_1_c15_c6_6 at min EL1: AGTCNTHV_TVAL_NOREDIR_EL21
 	REG_OPMAT0_EL1                 =53176 /* 53176 */,  // S3_1_c15_c7_0 at min EL1: OPMAT0_EL1
 	REG_PMCR1_EL12                 =53178 /* 53178 */,  // S3_1_c15_c7_2 at min EL2: PMCR1_EL12
 	REG_AON_CPU_MEMFLT_CTL67_EL1   =53179 /* 53179 */,  // S3_1_c15_c7_3 at min EL1: AON_CPU_MEMFLT_CTL67_EL1
-	REG_REDIR_ACNTHV_CTL_EL2       =53180 /* 53180 */,  // S3_1_c15_c7_4 at min EL2: REDIR_ACNTHV_CTL_EL2
-	REG_CNTP_CVAL_NOREDIR_EL0      =53181 /* 53181 */,  // S3_1_c15_c7_5 at min EL1: CNTP_CVAL_NOREDIR_EL0
-	REG_AGTCNTV_CTL_NOREDIR_EL0    =53182 /* 53182 */,  // S3_1_c15_c7_6 at min EL1: AGTCNTV_CTL_NOREDIR_EL0
+	REG_AGTCNTHV_CTL_EL2           =53180 /* 53180 */,  // S3_1_c15_c7_4 at min EL2: AGTCNTHV_CTL_EL2
+	REG_CNTHP_CVAL_NOREDIR_EL21    =53181 /* 53181 */,  // S3_1_c15_c7_5 at min EL1: CNTHP_CVAL_NOREDIR_EL21
+	REG_AGTCNTHV_CTL_NOREDIR_EL21  =53182 /* 53182 */,  // S3_1_c15_c7_6 at min EL1: AGTCNTHV_CTL_NOREDIR_EL21
 	REG_OPMAT1_EL1                 =53184 /* 53184 */,  // S3_1_c15_c8_0 at min EL1: OPMAT1_EL1
 	REG_PMCR1_GL12                 =53186 /* 53186 */,  // S3_1_c15_c8_2 at min EL2: PMCR1_GL12
 	REG_AON_CPU_MSTALL_CTR0_EL1    =53187 /* 53187 */,  // S3_1_c15_c8_3 at min EL1: AON_CPU_MSTALL_CTR0_EL1
-	REG_REDIR_ACNTFRQ_EL0          =53188 /* 53188 */,  // S3_1_c15_c8_4 at min EL1: REDIR_ACNTFRQ_EL0
-	REG_CNTP_TVAL_NOREDIR_EL0      =53189 /* 53189 */,  // S3_1_c15_c8_5 at min EL1: CNTP_TVAL_NOREDIR_EL0
-	REG_LCL_CNTPCT_NOREDIR_EL0     =53190 /* 53190 */,  // S3_1_c15_c8_6 at min EL1: LCL_CNTPCT_NOREDIR_EL0
+	REG_AGTCNTFRQ_EL0              =53188 /* 53188 */,  // S3_1_c15_c8_4 at min EL1: AGTCNTFRQ_EL0
+	REG_CNTHP_TVAL_NOREDIR_EL21    =53189 /* 53189 */,  // S3_1_c15_c8_5 at min EL1: CNTHP_TVAL_NOREDIR_EL21
+	REG_CNTPCT_NOREDIR_EL0         =53190 /* 53190 */,  // S3_1_c15_c8_6 at min EL1: CNTPCT_NOREDIR_EL0
 	REG_OPMSK0_EL1                 =53192 /* 53192 */,  // S3_1_c15_c9_0 at min EL1: OPMSK0_EL1
 	REG_LD_LATPROF_CTL_EL12        =53194 /* 53194 */,  // S3_1_c15_c9_2 at min EL2: LD_LATPROF_CTL_EL12
 	REG_AON_CPU_MSTALL_CTR1_EL1    =53195 /* 53195 */,  // S3_1_c15_c9_3 at min EL1: AON_CPU_MSTALL_CTR1_EL1
 	REG_AGTCNTVOFF_EL2             =53196 /* 53196 */,  // S3_1_c15_c9_4 at min EL2: AGTCNTVOFF_EL2
-	REG_CNTP_CTL_NOREDIR_EL0       =53197 /* 53197 */,  // S3_1_c15_c9_5 at min EL1: CNTP_CTL_NOREDIR_EL0
-	REG_CNTV_CTL_NOREDIR_EL0       =53198 /* 53198 */,  // S3_1_c15_c9_6 at min EL1: CNTV_CTL_NOREDIR_EL0
+	REG_CNTHP_CTL_NOREDIR_EL21     =53197 /* 53197 */,  // S3_1_c15_c9_5 at min EL1: CNTHP_CTL_NOREDIR_EL21
+	REG_CNTHV_CTL_NOREDIR_EL21     =53198 /* 53198 */,  // S3_1_c15_c9_6 at min EL1: CNTHV_CTL_NOREDIR_EL21
 	REG_OPMSK1_EL1                 =53200 /* 53200 */,  // S3_1_c15_c10_0 at min EL1: OPMSK1_EL1
 	REG_LD_LATPROF_INF_EL2         =53202 /* 53202 */,  // S3_1_c15_c10_2 at min EL2: LD_LATPROF_INF_EL2
 	REG_AON_CPU_MSTALL_CTR2_EL1    =53203 /* 53203 */,  // S3_1_c15_c10_3 at min EL1: AON_CPU_MSTALL_CTR2_EL1
-	REG_REDIR_ACNTP_CVAL_EL0       =53204 /* 53204 */,  // S3_1_c15_c10_4 at min EL1: REDIR_ACNTP_CVAL_EL0
-	REG_CNTV_CVAL_NOREDIR_EL0      =53205 /* 53205 */,  // S3_1_c15_c10_5 at min EL1: CNTV_CVAL_NOREDIR_EL0
-	REG_LCL_ACNTPCT_NOREDIR_EL0    =53206 /* 53206 */,  // S3_1_c15_c10_6 at min EL1: LCL_ACNTPCT_NOREDIR_EL0
+	REG_AGTCNTHP_CVAL_EL21         =53204 /* 53204 */,  // S3_1_c15_c10_4 at min EL1: AGTCNTHP_CVAL_EL21
+	REG_CNTHV_CVAL_NOREDIR_EL21    =53205 /* 53205 */,  // S3_1_c15_c10_5 at min EL1: CNTHV_CVAL_NOREDIR_EL21
+	REG_AGTCNTPCT_NOREDIR_EL0      =53206 /* 53206 */,  // S3_1_c15_c10_6 at min EL1: AGTCNTPCT_NOREDIR_EL0
 	REG_AON_CPU_MSTALL_CTR3_EL1    =53211 /* 53211 */,  // S3_1_c15_c11_3 at min EL1: AON_CPU_MSTALL_CTR3_EL1
-	REG_REDIR_ACNTP_TVAL_EL0       =53212 /* 53212 */,  // S3_1_c15_c11_4 at min EL1: REDIR_ACNTP_TVAL_EL0
-	REG_CNTV_TVAL_NOREDIR_EL0      =53213 /* 53213 */,  // S3_1_c15_c11_5 at min EL1: CNTV_TVAL_NOREDIR_EL0
+	REG_AGTCNTHP_TVAL_EL21         =53212 /* 53212 */,  // S3_1_c15_c11_4 at min EL1: AGTCNTHP_TVAL_EL21
+	REG_CNTHV_TVAL_NOREDIR_EL21    =53213 /* 53213 */,  // S3_1_c15_c11_5 at min EL1: CNTHV_TVAL_NOREDIR_EL21
 	REG_VMSA_HV_LOCK_EL2           =53214 /* 53214 */,  // S3_1_c15_c11_6 at min EL2: VMSA_HV_LOCK_EL2
 	REG_PMSWCTRL_EL1               =53216 /* 53216 */,  // S3_1_c15_c12_0 at min EL1: PMSWCTRL_EL1
 	REG_PMCR5_EL0                  =53217 /* 53217 */,  // S3_1_c15_c12_1 at min EL1: PMCR5_EL0
@@ -740,19 +711,19 @@ enum SystemReg {
 	REG_VMSA_NV_LOCK_EL2           =53222 /* 53222 */,  // S3_1_c15_c12_6 at min EL2: VMSA_NV_LOCK_EL2
 	REG_PMSR_EL1                   =53224 /* 53224 */,  // S3_1_c15_c13_0 at min EL1: PMSR_EL1
 	REG_AON_CPU_MSTALL_CTR5_EL1    =53227 /* 53227 */,  // S3_1_c15_c13_3 at min EL1: AON_CPU_MSTALL_CTR5_EL1
-	REG_REDIR_ACNTP_CTL_EL0        =53228 /* 53228 */,  // S3_1_c15_c13_4 at min EL1: REDIR_ACNTP_CTL_EL0
+	REG_AGTCNTHP_CTL_EL21          =53228 /* 53228 */,  // S3_1_c15_c13_4 at min EL1: AGTCNTHP_CTL_EL21
 	REG_PMCOMPARE5_EL1             =53229 /* 53229 */,  // S3_1_c15_c13_5 at min EL1: PMCompare5_EL1
 	REG_PMCOMPARE6_EL1             =53230 /* 53230 */,  // S3_1_c15_c13_6 at min EL1: PMCompare6_EL1
 	REG_PMCOMPARE7_EL1             =53231 /* 53231 */,  // S3_1_c15_c13_7 at min EL1: PMCompare7_EL1
 	REG_PMCR_BVRNG4_EL1            =53232 /* 53232 */,  // S3_1_c15_c14_0 at min EL1: PMCR_BVRNG4_EL1
 	REG_PM_PMI_PC                  =53233 /* 53233 */,  // S3_1_c15_c14_1 at min EL1: PM_PMI_PC
 	REG_AON_CPU_MSTALL_CTR6_EL1    =53235 /* 53235 */,  // S3_1_c15_c14_3 at min EL1: AON_CPU_MSTALL_CTR6_EL1
-	REG_REDIR_ACNTV_CVAL_EL0       =53236 /* 53236 */,  // S3_1_c15_c14_4 at min EL1: REDIR_ACNTV_CVAL_EL0
-	REG_LCL_ACNTVCT_NOREDIR_EL0    =53237 /* 53237 */,  // S3_1_c15_c14_5 at min EL1: LCL_ACNTVCT_NOREDIR_EL0
+	REG_AGTCNTHV_CVAL_EL21         =53236 /* 53236 */,  // S3_1_c15_c14_4 at min EL1: AGTCNTHV_CVAL_EL21
+	REG_AGTCNTVCT_NOREDIR_EL0      =53237 /* 53237 */,  // S3_1_c15_c14_5 at min EL1: AGTCNTVCT_NOREDIR_EL0
 	REG_PMCR_BVRNG5_EL1            =53240 /* 53240 */,  // S3_1_c15_c15_0 at min EL1: PMCR_BVRNG5_EL1
 	REG_AON_CPU_MSTALL_CTR7_EL1    =53243 /* 53243 */,  // S3_1_c15_c15_3 at min EL1: AON_CPU_MSTALL_CTR7_EL1
-	REG_REDIR_ACNTV_TVAL_EL0       =53244 /* 53244 */,  // S3_1_c15_c15_4 at min EL1: REDIR_ACNTV_TVAL_EL0
-	REG_LCL_ACNTPCTSS_NOREDIR_EL0  =53245 /* 53245 */,  // S3_1_c15_c15_5 at min EL1: LCL_ACNTPCTSS_NOREDIR_EL0
+	REG_AGTCNTHV_TVAL_EL21         =53244 /* 53244 */,  // S3_1_c15_c15_4 at min EL1: AGTCNTHV_TVAL_EL21
+	REG_AGTCNTPCTSS_NOREDIR_EL0    =53245 /* 53245 */,  // S3_1_c15_c15_5 at min EL1: AGTCNTPCTSS_NOREDIR_EL0
 	REG_CSSELR_EL1                 =53248 /* 53248 */,  // S3_2_c0_c0_0 at min EL1: CSSELR_EL1
 	REG_PMC0                       =55168 /* 55168 */,  // S3_2_c15_c0_0 at min EL1: PMC0
 	REG_UPMCFILTER0                =55169 /* 55169 */,  // S3_2_c15_c0_1 at min EL1: UPMCFILTER0
@@ -787,8 +758,10 @@ enum SystemReg {
 	REG_TCO                        =55831 /* 55831 */,
 	REG_FPCR                       =55840 /* 55840 */,  // S3_3_c4_c4_0 at min EL1: FPCR
 	REG_FPSR                       =55841 /* 55841 */,  // S3_3_c4_c4_1 at min EL1: FPSR
-	REG_DSPSR_EL0                  =55848 /* 55848 */,  // S3_3_c4_c5_0 at min EL1: DSPSR_EL0
-	REG_DLR_EL0                    =55849 /* 55849 */,  // S3_3_c4_c5_1 at min EL1: DLR_EL0
+	REG_DSPSR                      =55848 /* 55848 */,  // S3_3_c4_c5_0 at min EL0: DSPSR
+	REG_DSPSR_EL0                  =55848 /* 55848 */,
+	REG_DLR                        =55849 /* 55849 */,  // S3_3_c4_c5_1 at min EL0: DLR
+	REG_DLR_EL0                    =55849 /* 55849 */,
 	REG_PMCR_EL0                   =56544 /* 56544 */,
 	REG_PMCNTENSET_EL0             =56545 /* 56545 */,
 	REG_PMCNTENCLR_EL0             =56546 /* 56546 */,
@@ -847,24 +820,22 @@ enum SystemReg {
 	REG_AMEVTYPER113_EL0           =57085 /* 57085 */,
 	REG_AMEVTYPER114_EL0           =57086 /* 57086 */,
 	REG_AMEVTYPER115_EL0           =57087 /* 57087 */,
-	REG_REDIR_CNTFRQ_EL0           =57088 /* 57088 */,  // S3_3_c14_c0_0 at min EL1: REDIR_CNTFRQ_EL0
-	REG_CNTFRQ_EL0                 =57088 /* 57088 */,
-	REG_REDIR_LCL_CNTPCT_EL0       =57089 /* 57089 */,  // S3_3_c14_c0_1 at min EL1: REDIR_LCL_CNTPCT_EL0
-	REG_CNTPCT_EL0                 =57089 /* 57089 */,
-	REG_REDIR_LCL_CNTVCT_EL0       =57090 /* 57090 */,  // S3_3_c14_c0_2 at min EL1: REDIR_LCL_CNTVCT_EL0
-	REG_REDIR_LCL_CNTPCTSS_EL0     =57093 /* 57093 */,  // S3_3_c14_c0_5 at min EL1: REDIR_LCL_CNTPCTSS_EL0
-	REG_REDIR_LCL_CNTVCTSS_EL0     =57094 /* 57094 */,  // S3_3_c14_c0_6 at min EL1: REDIR_LCL_CNTVCTSS_EL0
-	REG_REDIR_CNTP_TVAL_EL0        =57104 /* 57104 */,  // S3_3_c14_c2_0 at min EL1: REDIR_CNTP_TVAL_EL0
+	REG_CNTFRQ_EL0                 =57088 /* 57088 */,  // S3_3_c14_c0_0 at min EL1: CNTFRQ_EL0
+	REG_CNTPCT_EL0                 =57089 /* 57089 */,  // S3_3_c14_c0_1 at min EL1: CNTPCT_EL0
+	REG_CNTVCT_EL0                 =57090 /* 57090 */,  // S3_3_c14_c0_2 at min EL1: CNTVCT_EL0
+	REG_CNTPCTSS_EL0               =57093 /* 57093 */,  // S3_3_c14_c0_5 at min EL1: CNTPCTSS_EL0
+	REG_CNTVCTSS_EL0               =57094 /* 57094 */,  // S3_3_c14_c0_6 at min EL1: CNTVCTSS_EL0
+	REG_CNTHP_TVAL_EL21            =57104 /* 57104 */,  // S3_3_c14_c2_0 at min EL1: CNTHP_TVAL_EL21
 	REG_CNTP_TVAL_EL0              =57104 /* 57104 */,
-	REG_REDIR_CNTP_CTL_EL0         =57105 /* 57105 */,  // S3_3_c14_c2_1 at min EL1: REDIR_CNTP_CTL_EL0
+	REG_CNTHP_CTL_EL21             =57105 /* 57105 */,  // S3_3_c14_c2_1 at min EL1: CNTHP_CTL_EL21
 	REG_CNTP_CTL_EL0               =57105 /* 57105 */,
-	REG_REDIR_CNTP_CVAL_EL0        =57106 /* 57106 */,  // S3_3_c14_c2_2 at min EL1: REDIR_CNTP_CVAL_EL0
+	REG_CNTHP_CVAL_EL21            =57106 /* 57106 */,  // S3_3_c14_c2_2 at min EL1: CNTHP_CVAL_EL21
 	REG_CNTP_CVAL_EL0              =57106 /* 57106 */,
-	REG_REDIR_CNTV_TVAL_EL0        =57112 /* 57112 */,  // S3_3_c14_c3_0 at min EL1: REDIR_CNTV_TVAL_EL0
+	REG_CNTHV_TVAL_EL21            =57112 /* 57112 */,  // S3_3_c14_c3_0 at min EL1: CNTHV_TVAL_EL21
 	REG_CNTV_TVAL_EL0              =57112 /* 57112 */,
-	REG_REDIR_CNTV_CTL_EL0         =57113 /* 57113 */,  // S3_3_c14_c3_1 at min EL1: REDIR_CNTV_CTL_EL0
+	REG_CNTHV_CTL_EL21             =57113 /* 57113 */,  // S3_3_c14_c3_1 at min EL1: CNTHV_CTL_EL21
 	REG_CNTV_CTL_EL0               =57113 /* 57113 */,
-	REG_REDIR_CNTV_CVAL_EL0        =57114 /* 57114 */,  // S3_3_c14_c3_2 at min EL1: REDIR_CNTV_CVAL_EL0
+	REG_CNTHV_CVAL_EL21            =57114 /* 57114 */,  // S3_3_c14_c3_2 at min EL1: CNTHV_CVAL_EL21
 	REG_CNTV_CVAL_EL0              =57114 /* 57114 */,
 	REG_PMEVCNTR0_EL0              =57152 /* 57152 */,
 	REG_PMEVCNTR1_EL0              =57153 /* 57153 */,
@@ -1013,10 +984,8 @@ enum SystemReg {
 	REG_DACR32_EL2                 =57728 /* 57728 */,  // S3_4_c3_c0_0 at min EL2: DACR32_EL2
 	REG_HDFGRTR_EL2                =57740 /* 57740 */,  // S3_4_c3_c1_4 at min EL2: HDFGRTR_EL2
 	REG_HDFGWTR_EL2                =57741 /* 57741 */,  // S3_4_c3_c1_5 at min EL2: HDFGWTR_EL2
-	REG_SPSR_NV_EL21               =57856 /* 57856 */,  // S3_4_c4_c0_0 at min EL1: SPSR_NV_EL21
-	REG_SPSR_EL2                   =57856 /* 57856 */,
-	REG_ELR_NV_EL21                =57857 /* 57857 */,  // S3_4_c4_c0_1 at min EL1: ELR_NV_EL21
-	REG_ELR_EL2                    =57857 /* 57857 */,
+	REG_SPSR_EL2                   =57856 /* 57856 */,  // S3_4_c4_c0_0 at min EL2: SPSR_EL2
+	REG_ELR_EL2                    =57857 /* 57857 */,  // S3_4_c4_c0_1 at min EL2: ELR_EL2
 	REG_SP_EL1                     =57864 /* 57864 */,  // S3_4_c4_c1_0 at min EL1: SP_EL1
 	REG_SPSR_IRQ                   =57880 /* 57880 */,  // S3_4_c4_c3_0 at min EL1: SPSR_irq
 	REG_SPSR_ABT                   =57881 /* 57881 */,  // S3_4_c4_c3_1 at min EL1: SPSR_abt
@@ -1025,13 +994,11 @@ enum SystemReg {
 	REG_IFSR32_EL2                 =57985 /* 57985 */,  // S3_4_c5_c0_1 at min EL2: IFSR32_EL2
 	REG_AFSR0_EL2                  =57992 /* 57992 */,  // S3_4_c5_c1_0 at min EL2: AFSR0_EL2
 	REG_AFSR1_EL2                  =57993 /* 57993 */,  // S3_4_c5_c1_1 at min EL2: AFSR1_EL2
-	REG_ESR_NV_EL21                =58000 /* 58000 */,  // S3_4_c5_c2_0 at min EL1: ESR_NV_EL21
-	REG_ESR_EL2                    =58000 /* 58000 */,
+	REG_ESR_EL2                    =58000 /* 58000 */,  // S3_4_c5_c2_0 at min EL2: ESR_EL2
 	REG_VSESR_EL2                  =58003 /* 58003 */,  // S3_4_c5_c2_3 at min EL2: VSESR_EL2
 	REG_FPEXC32_EL2                =58008 /* 58008 */,  // S3_4_c5_c3_0 at min EL2: FPEXC32_EL2
 	REG_TFSR_EL2                   =58032 /* 58032 */,
-	REG_FAR_NV_EL21                =58112 /* 58112 */,  // S3_4_c6_c0_0 at min EL1: FAR_NV_EL21
-	REG_FAR_EL2                    =58112 /* 58112 */,
+	REG_FAR_EL2                    =58112 /* 58112 */,  // S3_4_c6_c0_0 at min EL2: FAR_EL2
 	REG_HPFAR_EL2                  =58116 /* 58116 */,  // S3_4_c6_c0_4 at min EL2: HPFAR_EL2
 	REG_PMSCR_EL2                  =58568 /* 58568 */,
 	REG_MAIR_EL2                   =58640 /* 58640 */,  // S3_4_c10_c2_0 at min EL2: MAIR_EL2
@@ -1087,20 +1054,13 @@ enum SystemReg {
 	REG_TPIDR_EL2                  =59010 /* 59010 */,  // S3_4_c13_c0_2 at min EL2: TPIDR_EL2
 	REG_SCXTNUM_EL2                =59015 /* 59015 */,  // S3_4_c13_c0_7 at min EL2: SCXTNUM_EL2
 	REG_CNTVOFF_EL2                =59139 /* 59139 */,  // S3_4_c14_c0_3 at min EL2: CNTVOFF_EL2
-	REG_REDIR_CNTHCTL_EL2          =59144 /* 59144 */,  // S3_4_c14_c1_0 at min EL2: REDIR_CNTHCTL_EL2
-	REG_CNTHCTL_EL2                =59144 /* 59144 */,
-	REG_REDIR_CNTHP_TVAL_EL2       =59152 /* 59152 */,  // S3_4_c14_c2_0 at min EL2: REDIR_CNTHP_TVAL_EL2
-	REG_CNTHP_TVAL_EL2             =59152 /* 59152 */,
-	REG_REDIR_CNTHP_CTL_EL2        =59153 /* 59153 */,  // S3_4_c14_c2_1 at min EL2: REDIR_CNTHP_CTL_EL2
-	REG_CNTHP_CTL_EL2              =59153 /* 59153 */,
-	REG_REDIR_CNTHP_CVAL_EL2       =59154 /* 59154 */,  // S3_4_c14_c2_2 at min EL2: REDIR_CNTHP_CVAL_EL2
-	REG_CNTHP_CVAL_EL2             =59154 /* 59154 */,
-	REG_REDIR_CNTHV_TVAL_EL2       =59160 /* 59160 */,  // S3_4_c14_c3_0 at min EL2: REDIR_CNTHV_TVAL_EL2
-	REG_CNTHV_TVAL_EL2             =59160 /* 59160 */,
-	REG_REDIR_CNTHV_CTL_EL2        =59161 /* 59161 */,  // S3_4_c14_c3_1 at min EL2: REDIR_CNTHV_CTL_EL2
-	REG_CNTHV_CTL_EL2              =59161 /* 59161 */,
-	REG_REDIR_CNTHV_CVAL_EL2       =59162 /* 59162 */,  // S3_4_c14_c3_2 at min EL2: REDIR_CNTHV_CVAL_EL2
-	REG_CNTHV_CVAL_EL2             =59162 /* 59162 */,
+	REG_CNTHCTL_EL2                =59144 /* 59144 */,  // S3_4_c14_c1_0 at min EL2: CNTHCTL_EL2
+	REG_CNTHP_TVAL_EL2             =59152 /* 59152 */,  // S3_4_c14_c2_0 at min EL2: CNTHP_TVAL_EL2
+	REG_CNTHP_CTL_EL2              =59153 /* 59153 */,  // S3_4_c14_c2_1 at min EL2: CNTHP_CTL_EL2
+	REG_CNTHP_CVAL_EL2             =59154 /* 59154 */,  // S3_4_c14_c2_2 at min EL2: CNTHP_CVAL_EL2
+	REG_CNTHV_TVAL_EL2             =59160 /* 59160 */,  // S3_4_c14_c3_0 at min EL2: CNTHV_TVAL_EL2
+	REG_CNTHV_CTL_EL2              =59161 /* 59161 */,  // S3_4_c14_c3_1 at min EL2: CNTHV_CTL_EL2
+	REG_CNTHV_CVAL_EL2             =59162 /* 59162 */,  // S3_4_c14_c3_2 at min EL2: CNTHV_CVAL_EL2
 	REG_CNTHVS_TVAL_EL2            =59168 /* 59168 */,
 	REG_CNTHVS_CTL_EL2             =59169 /* 59169 */,
 	REG_CNTHVS_CVAL_EL2            =59170 /* 59170 */,
@@ -1109,21 +1069,21 @@ enum SystemReg {
 	REG_CNTHPS_CVAL_EL2            =59178 /* 59178 */,
 	REG_FED_ERR_STS                =59264 /* 59264 */,  // S3_4_c15_c0_0 at min EL1: FED_ERR_STS
 	REG_FED_ERR_CTL                =59265 /* 59265 */,  // S3_4_c15_c0_1 at min EL1: FED_ERR_CTL
-	REG_APCTL_EL21                 =59268 /* 59268 */,  // S3_4_c15_c0_4 at min EL1: APCTL_EL21
-	REG_KERNKEYLO_EL21             =59272 /* 59272 */,  // S3_4_c15_c1_0 at min EL1: KERNKEYLo_EL21
-	REG_KERNKEYHI_EL21             =59273 /* 59273 */,  // S3_4_c15_c1_1 at min EL1: KERNKEYHi_EL21
-	REG_VMSA_LOCK_EL1              =59274 /* 59274 */,  // S3_4_c15_c1_2 at min EL1: VMSA_LOCK_EL1
+	REG_APCTL_EL1                  =59268 /* 59268 */,  // S3_4_c15_c0_4 at min EL1: APCTL_EL1
+	REG_KERNKEYLO_EL1              =59272 /* 59272 */,  // S3_4_c15_c1_0 at min EL1: KERNKEYLo_EL1
+	REG_KERNKEYHI_EL1              =59273 /* 59273 */,  // S3_4_c15_c1_1 at min EL1: KERNKEYHi_EL1
+	REG_VMSALOCK_EL21              =59274 /* 59274 */,  // S3_4_c15_c1_2 at min EL1: VMSALock_EL21
 	REG_AMX_STATE_T_EL1            =59275 /* 59275 */,  // S3_4_c15_c1_3 at min EL1: AMX_STATE_T_EL1
-	REG_AMX_CONFIG_EL21            =59276 /* 59276 */,  // S3_4_c15_c1_4 at min EL1: AMX_CONFIG_EL21
+	REG_AMX_CONFIG_EL1             =59276 /* 59276 */,  // S3_4_c15_c1_4 at min EL1: AMX_CONFIG_EL1
 	REG_VMSA_LOCK_EL2              =59277 /* 59277 */,  // S3_4_c15_c1_5 at min EL2: VMSA_LOCK_EL2
-	REG_CTRR_B_UPR_EL21            =59278 /* 59278 */,  // S3_4_c15_c1_6 at min EL1: CTRR_B_UPR_EL21
-	REG_CTRR_B_LWR_EL21            =59279 /* 59279 */,  // S3_4_c15_c1_7 at min EL1: CTRR_B_LWR_EL21
-	REG_SP_SETUP_GL21              =59280 /* 59280 */,  // S3_4_c15_c2_0 at min EL1: SP_SETUP_GL21
+	REG_CTRR_B_UPR_EL1             =59278 /* 59278 */,  // S3_4_c15_c1_6 at min EL1: CTRR_B_UPR_EL1
+	REG_CTRR_B_LWR_EL1             =59279 /* 59279 */,  // S3_4_c15_c1_7 at min EL1: CTRR_B_LWR_EL1
+	REG_SP_SETUP_GL1               =59280 /* 59280 */,  // S3_4_c15_c2_0 at min EL1: SP_SETUP_GL1
 	REG_SP_SETUP_GL2               =59281 /* 59281 */,  // S3_4_c15_c2_1 at min EL2: SP_SETUP_GL2
-	REG_CTRR_B_CTL_EL21            =59282 /* 59282 */,  // S3_4_c15_c2_2 at min EL1: CTRR_B_CTL_EL21
-	REG_CTRR_A_LWR_EL21            =59283 /* 59283 */,  // S3_4_c15_c2_3 at min EL1: CTRR_A_LWR_EL21
-	REG_CTRR_A_UPR_EL21            =59284 /* 59284 */,  // S3_4_c15_c2_4 at min EL1: CTRR_A_UPR_EL21
-	REG_CTRR_A_CTL_EL21            =59285 /* 59285 */,  // S3_4_c15_c2_5 at min EL1: CTRR_A_CTL_EL21
+	REG_CTRR_B_CTL_EL1             =59282 /* 59282 */,  // S3_4_c15_c2_2 at min EL1: CTRR_B_CTL_EL1
+	REG_CTRR_A_LWR_EL1             =59283 /* 59283 */,  // S3_4_c15_c2_3 at min EL1: CTRR_A_LWR_EL1
+	REG_CTRR_A_UPR_EL1             =59284 /* 59284 */,  // S3_4_c15_c2_4 at min EL1: CTRR_A_UPR_EL1
+	REG_CTRR_A_CTL_EL1             =59285 /* 59285 */,  // S3_4_c15_c2_5 at min EL1: CTRR_A_CTL_EL1
 	REG_VMSA_LOCK_EL12             =59286 /* 59286 */,  // S3_4_c15_c2_6 at min EL2: VMSA_LOCK_EL12
 	REG_AGTCNTV_CTL_EL02           =59287 /* 59287 */,  // S3_4_c15_c2_7 at min EL1: AGTCNTV_CTL_EL02
 	REG_AMX_STATE_EL1              =59288 /* 59288 */,  // S3_4_c15_c3_0 at min EL1: AMX_STATE_EL1
@@ -1165,15 +1125,15 @@ enum SystemReg {
 	REG_CTRR_B_UPR_EL12            =59339 /* 59339 */,  // S3_4_c15_c9_3 at min EL2: CTRR_B_UPR_EL12
 	REG_CTRR_A_CTL_EL12            =59340 /* 59340 */,  // S3_4_c15_c9_4 at min EL2: CTRR_A_CTL_EL12
 	REG_CTRR_B_CTL_EL12            =59341 /* 59341 */,  // S3_4_c15_c9_5 at min EL2: CTRR_B_CTL_EL12
-	REG_REDIR_ACNTKCTL_EL1         =59342 /* 59342 */,  // S3_4_c15_c9_6 at min EL1: REDIR_ACNTKCTL_EL1
+	REG_AGTCNTHCTL_EL21            =59342 /* 59342 */,  // S3_4_c15_c9_6 at min EL1: AGTCNTHCTL_EL21
 	REG_AGTCNTKCTL_EL12            =59343 /* 59343 */,  // S3_4_c15_c9_7 at min EL2: AGTCNTKCTL_EL12
 	REG_PREDAKEYLO_EL1             =59344 /* 59344 */,  // S3_4_c15_c10_0 at min EL1: PREDAKEYLo_EL1
 	REG_PREDAKEYHI_EL1             =59345 /* 59345 */,  // S3_4_c15_c10_1 at min EL1: PREDAKEYHi_EL1
 	REG_PREDBKEYLO_EL1             =59346 /* 59346 */,  // S3_4_c15_c10_2 at min EL1: PREDBKEYLo_EL1
 	REG_PREDBKEYHI_EL1             =59347 /* 59347 */,  // S3_4_c15_c10_3 at min EL1: PREDBKEYHi_EL1
 	REG_SIQ_CFG_EL1                =59348 /* 59348 */,  // S3_4_c15_c10_4 at min EL1: SIQ_CFG_EL1
-	REG_REDIR_LCL_ACNTPCTSS_EL0    =59349 /* 59349 */,  // S3_4_c15_c10_5 at min EL1: REDIR_LCL_ACNTPCTSS_EL0
-	REG_REDIR_LCL_ACNTVCTSS_EL0    =59350 /* 59350 */,  // S3_4_c15_c10_6 at min EL1: REDIR_LCL_ACNTVCTSS_EL0
+	REG_AGTCNTPCTSS_EL0            =59349 /* 59349 */,  // S3_4_c15_c10_5 at min EL1: AGTCNTPCTSS_EL0
+	REG_AGTCNTVCTSS_EL0            =59350 /* 59350 */,  // S3_4_c15_c10_6 at min EL1: AGTCNTVCTSS_EL0
 	REG_AVNCR_EL2                  =59351 /* 59351 */,  // S3_4_c15_c10_7 at min EL2: AVNCR_EL2
 	REG_ACC_CTRR_A_LWR_EL2         =59352 /* 59352 */,  // S3_4_c15_c11_0 at min EL2: ACC_CTRR_A_LWR_EL2
 	REG_ACC_CTRR_A_UPR_EL2         =59353 /* 59353 */,  // S3_4_c15_c11_1 at min EL2: ACC_CTRR_A_UPR_EL2
@@ -1181,21 +1141,21 @@ enum SystemReg {
 	REG_ACC_CTRR_B_UPR_EL2         =59355 /* 59355 */,  // S3_4_c15_c11_3 at min EL2: ACC_CTRR_B_UPR_EL2
 	REG_ACC_CTRR_A_CTL_EL2         =59356 /* 59356 */,  // S3_4_c15_c11_4 at min EL2: ACC_CTRR_A_CTL_EL2
 	REG_ACC_CTRR_B_CTL_EL2         =59357 /* 59357 */,  // S3_4_c15_c11_5 at min EL2: ACC_CTRR_B_CTL_EL2
-	REG_REDIR_LCL_ACNTPCT_EL0      =59358 /* 59358 */,  // S3_4_c15_c11_6 at min EL1: REDIR_LCL_ACNTPCT_EL0
-	REG_REDIR_LCL_ACNTVCT_EL0      =59359 /* 59359 */,  // S3_4_c15_c11_7 at min EL1: REDIR_LCL_ACNTVCT_EL0
+	REG_AGTCNTPCT_EL0              =59358 /* 59358 */,  // S3_4_c15_c11_6 at min EL1: AGTCNTPCT_EL0
+	REG_AGTCNTVCT_EL0              =59359 /* 59359 */,  // S3_4_c15_c11_7 at min EL1: AGTCNTVCT_EL0
 	REG_ACFG_EL1                   =59360 /* 59360 */,  // S3_4_c15_c12_0 at min EL1: ACFG_EL1
 	REG_AHCR_EL2                   =59361 /* 59361 */,  // S3_4_c15_c12_1 at min EL2: AHCR_EL2
-	REG_APL_INTSTATUS_EL21         =59362 /* 59362 */,  // S3_4_c15_c12_2 at min EL1: APL_INTSTATUS_EL21
+	REG_APL_INTSTATUS_EL1          =59362 /* 59362 */,  // S3_4_c15_c12_2 at min EL1: APL_INTSTATUS_EL1
 	REG_APL_INTSTATUS_EL2          =59363 /* 59363 */,  // S3_4_c15_c12_3 at min EL2: APL_INTSTATUS_EL2
-	REG_REDIR_ACNTHCTL_EL2         =59366 /* 59366 */,  // S3_4_c15_c12_6 at min EL2: REDIR_ACNTHCTL_EL2
-	REG_JAPIAKEYLO_NV_EL21         =59368 /* 59368 */,  // S3_4_c15_c13_0 at min EL1: JAPIAKeyLo_NV_EL21
-	REG_JAPIAKEYHI_NV_EL21         =59369 /* 59369 */,  // S3_4_c15_c13_1 at min EL1: JAPIAKeyHi_NV_EL21
-	REG_JAPIBKEYLO_NV_EL21         =59370 /* 59370 */,  // S3_4_c15_c13_2 at min EL1: JAPIBKeyLo_NV_EL21
-	REG_JAPIBKEYHI_NV_EL21         =59371 /* 59371 */,  // S3_4_c15_c13_3 at min EL1: JAPIBKeyHi_NV_EL21
-	REG_JAPIAKEYLO_EL21            =59372 /* 59372 */,  // S3_4_c15_c13_4 at min EL1: JAPIAKeyLo_EL21
-	REG_JAPIAKEYHI_EL21            =59373 /* 59373 */,  // S3_4_c15_c13_5 at min EL1: JAPIAKeyHi_EL21
-	REG_JAPIBKEYLO_EL21            =59374 /* 59374 */,  // S3_4_c15_c13_6 at min EL1: JAPIBKeyLo_EL21
-	REG_JAPIBKEYHI_EL21            =59375 /* 59375 */,  // S3_4_c15_c13_7 at min EL1: JAPIBKeyHi_EL21
+	REG_AGTCNTHCTL_EL2             =59366 /* 59366 */,  // S3_4_c15_c12_6 at min EL2: AGTCNTHCTL_EL2
+	REG_JAPIAKEYLO_EL2             =59368 /* 59368 */,  // S3_4_c15_c13_0 at min EL2: JAPIAKeyLo_EL2
+	REG_JAPIAKEYHI_EL2             =59369 /* 59369 */,  // S3_4_c15_c13_1 at min EL2: JAPIAKeyHi_EL2
+	REG_JAPIBKEYLO_EL2             =59370 /* 59370 */,  // S3_4_c15_c13_2 at min EL2: JAPIBKeyLo_EL2
+	REG_JAPIBKEYHI_EL2             =59371 /* 59371 */,  // S3_4_c15_c13_3 at min EL2: JAPIBKeyHi_EL2
+	REG_JAPIAKEYLO_EL1             =59372 /* 59372 */,  // S3_4_c15_c13_4 at min EL1: JAPIAKeyLo_EL1
+	REG_JAPIAKEYHI_EL1             =59373 /* 59373 */,  // S3_4_c15_c13_5 at min EL1: JAPIAKeyHi_EL1
+	REG_JAPIBKEYLO_EL1             =59374 /* 59374 */,  // S3_4_c15_c13_6 at min EL1: JAPIBKeyLo_EL1
+	REG_JAPIBKEYHI_EL1             =59375 /* 59375 */,  // S3_4_c15_c13_7 at min EL1: JAPIBKeyHi_EL1
 	REG_JAPIAKEYLO_EL12            =59376 /* 59376 */,  // S3_4_c15_c14_0 at min EL2: JAPIAKeyLo_EL12
 	REG_JAPIAKEYHI_EL12            =59377 /* 59377 */,  // S3_4_c15_c14_1 at min EL2: JAPIAKeyHi_EL12
 	REG_JAPIBKEYLO_EL12            =59378 /* 59378 */,  // S3_4_c15_c14_2 at min EL2: JAPIBKeyLo_EL12
@@ -1203,10 +1163,10 @@ enum SystemReg {
 	REG_AGTCNTRDIR_EL2             =59381 /* 59381 */,  // S3_4_c15_c14_5 at min EL2: AGTCNTRDIR_EL2
 	REG_AGTCNTRDIR_EL12            =59382 /* 59382 */,  // S3_4_c15_c14_6 at min EL2: AGTCNTRDIR_EL12
 	REG_JRANGE_EL2                 =59384 /* 59384 */,  // S3_4_c15_c15_0 at min EL2: JRANGE_EL2
-	REG_JRANGE_EL21                =59385 /* 59385 */,  // S3_4_c15_c15_1 at min EL1: JRANGE_EL21
+	REG_JRANGE_EL1                 =59385 /* 59385 */,  // S3_4_c15_c15_1 at min EL1: JRANGE_EL1
 	REG_JRANGE_EL12                =59386 /* 59386 */,  // S3_4_c15_c15_2 at min EL2: JRANGE_EL12
 	REG_JCTL_EL2                   =59387 /* 59387 */,  // S3_4_c15_c15_3 at min EL2: JCTL_EL2
-	REG_JCTL_EL21                  =59388 /* 59388 */,  // S3_4_c15_c15_4 at min EL1: JCTL_EL21
+	REG_JCTL_EL1                   =59388 /* 59388 */,  // S3_4_c15_c15_4 at min EL1: JCTL_EL1
 	REG_JCTL_EL12                  =59389 /* 59389 */,  // S3_4_c15_c15_5 at min EL2: JCTL_EL12
 	REG_JCTL_EL0                   =59390 /* 59390 */,  // S3_4_c15_c15_6 at min EL1: JCTL_EL0
 	REG_AMDSCR_EL1                 =59391 /* 59391 */,  // S3_4_c15_c15_7 at min EL1: AMDSCR_EL1
@@ -1246,7 +1206,7 @@ enum SystemReg {
 	REG_AF_ERR_SRC_IDS             =61316 /* 61316 */,  // S3_5_c15_c0_4 at min EL1: AF_ERR_SRC_IDS
 	REG_DPC_ERR_STS                =61317 /* 61317 */,  // S3_5_c15_c0_5 at min EL1: DPC_ERR_STS
 	REG_DPC_ERR_CTL                =61318 /* 61318 */,  // S3_5_c15_c0_6 at min EL1: DPC_ERR_CTL
-	REG_PROD_TRC_CORE_CFG_EL21     =61319 /* 61319 */,  // S3_5_c15_c0_7 at min EL1: PROD_TRC_CORE_CFG_EL21
+	REG_PROD_TRC_CORE_CFG_EL1      =61319 /* 61319 */,  // S3_5_c15_c0_7 at min EL1: PROD_TRC_CORE_CFG_EL1
 	REG_TRACE_CORE_CFG             =61320 /* 61320 */,  // S3_5_c15_c1_0 at min EL1: TRACE_CORE_CFG
 	REG_IPI_SR                     =61321 /* 61321 */,  // S3_5_c15_c1_1 at min EL1: IPI_SR
 	REG_APL_LRTMR_EL2              =61322 /* 61322 */,  // S3_5_c15_c1_2 at min EL2: APL_LRTMR_EL2
@@ -1273,20 +1233,20 @@ enum SystemReg {
 	REG_PROD_TRC_STRM_BASE1_GL2    =61343 /* 61343 */,  // S3_5_c15_c3_7 at min EL2: PROD_TRC_STRM_BASE1_GL2
 	REG_CPU_CFG                    =61344 /* 61344 */,  // S3_5_c15_c4_0 at min EL1: CPU_CFG
 	REG_PBLK_STS                   =61345 /* 61345 */,  // S3_5_c15_c4_1 at min EL1: PBLK_STS
-	REG_PROD_TRC_CTL_EL21          =61347 /* 61347 */,  // S3_5_c15_c4_3 at min EL1: PROD_TRC_CTL_EL21
-	REG_PROD_TRC_STRM_BASE0_GL21   =61348 /* 61348 */,  // S3_5_c15_c4_4 at min EL1: PROD_TRC_STRM_BASE0_GL21
-	REG_PROD_TRC_STRM_BASE1_GL21   =61349 /* 61349 */,  // S3_5_c15_c4_5 at min EL1: PROD_TRC_STRM_BASE1_GL21
-	REG_PROD_TRC_STRM_FIQ_EL21     =61350 /* 61350 */,  // S3_5_c15_c4_6 at min EL1: PROD_TRC_STRM_FIQ_EL21
+	REG_PROD_TRC_CTL_EL1           =61347 /* 61347 */,  // S3_5_c15_c4_3 at min EL1: PROD_TRC_CTL_EL1
+	REG_PROD_TRC_STRM_BASE0_GL1    =61348 /* 61348 */,  // S3_5_c15_c4_4 at min EL1: PROD_TRC_STRM_BASE0_GL1
+	REG_PROD_TRC_STRM_BASE1_GL1    =61349 /* 61349 */,  // S3_5_c15_c4_5 at min EL1: PROD_TRC_STRM_BASE1_GL1
+	REG_PROD_TRC_STRM_FIQ_EL1      =61350 /* 61350 */,  // S3_5_c15_c4_6 at min EL1: PROD_TRC_STRM_FIQ_EL1
 	REG_CPU_OVRD                   =61352 /* 61352 */,  // S3_5_c15_c5_0 at min EL1: CPU_OVRD
 	REG_PBLK_EXE_ST                =61354 /* 61354 */,  // S3_5_c15_c5_2 at min EL1: PBLK_EXE_ST
-	REG_PROD_TRC_CORE_GL_CTL_GL21  =61357 /* 61357 */,  // S3_5_c15_c5_5 at min EL1: PROD_TRC_CORE_GL_CTL_GL21
+	REG_PROD_TRC_CORE_GL_CTL_GL1   =61357 /* 61357 */,  // S3_5_c15_c5_5 at min EL1: PROD_TRC_CORE_GL_CTL_GL1
 	REG_PROD_TRC_CORE_GL_CTL_GL2   =61358 /* 61358 */,  // S3_5_c15_c5_6 at min EL2: PROD_TRC_CORE_GL_CTL_GL2
 	REG_ACC_OVRD                   =61360 /* 61360 */,  // S3_5_c15_c6_0 at min EL1: ACC_OVRD
 	REG_ACC_OVRD1                  =61361 /* 61361 */,  // S3_5_c15_c6_1 at min EL1: ACC_OVRD1
 	REG_CPM_PWRDN_CTL              =61362 /* 61362 */,  // S3_5_c15_c6_2 at min EL1: CPM_PWRDN_CTL
-	REG_PROD_TRC_BUF_RESTORE0_GL21 =61364 /* 61364 */,  // S3_5_c15_c6_4 at min EL1: PROD_TRC_BUF_RESTORE0_GL21
-	REG_PROD_TRC_BUF_RESTORE1_GL21 =61365 /* 61365 */,  // S3_5_c15_c6_5 at min EL1: PROD_TRC_BUF_RESTORE1_GL21
-	REG_PROD_TRC_EN_GL21           =61366 /* 61366 */,  // S3_5_c15_c6_6 at min EL1: PROD_TRC_EN_GL21
+	REG_PROD_TRC_BUF_RESTORE0_GL1  =61364 /* 61364 */,  // S3_5_c15_c6_4 at min EL1: PROD_TRC_BUF_RESTORE0_GL1
+	REG_PROD_TRC_BUF_RESTORE1_GL1  =61365 /* 61365 */,  // S3_5_c15_c6_5 at min EL1: PROD_TRC_BUF_RESTORE1_GL1
+	REG_PROD_TRC_EN_GL1            =61366 /* 61366 */,  // S3_5_c15_c6_6 at min EL1: PROD_TRC_EN_GL1
 	REG_PRE_LLCFLUSH_TMR           =61368 /* 61368 */,  // S3_5_c15_c7_0 at min EL1: PRE_LLCFLUSH_TMR
 	REG_BIUINTFCTL_CFG             =61372 /* 61372 */,  // S3_5_c15_c7_4 at min EL1: BIUINTFCTL_CFG
 	REG_BIUINTFWRR_CFG             =61373 /* 61373 */,  // S3_5_c15_c7_5 at min EL1: BIUINTFWRR_CFG
@@ -1344,20 +1304,20 @@ enum SystemReg {
 	REG_TPIDR_EL3                  =63106 /* 63106 */,  // S3_6_c13_c0_2 at min EL3: TPIDR_EL3
 	REG_SCXTNUM_EL3                =63111 /* 63111 */,
 	REG_MMU_ERR_STS                =63360 /* 63360 */,  // S3_6_c15_c0_0 at min EL1: MMU_ERR_STS
-	REG_AFSR1_GL21                 =63361 /* 63361 */,  // S3_6_c15_c0_1 at min EL1: AFSR1_GL21
+	REG_AFSR1_GL1                  =63361 /* 63361 */,  // S3_6_c15_c0_1 at min EL1: AFSR1_GL1
 	REG_AFSR1_GL2                  =63362 /* 63362 */,  // S3_6_c15_c0_2 at min EL2: AFSR1_GL2
 	REG_AFSR1_GL12                 =63363 /* 63363 */,  // S3_6_c15_c0_3 at min EL2: AFSR1_GL12
 	REG_BP_OBJC_ADR_EL1            =63364 /* 63364 */,  // S3_6_c15_c0_4 at min EL1: BP_OBJC_ADR_EL1
 	REG_BP_OBJC_CTL_EL1            =63365 /* 63365 */,  // S3_6_c15_c0_5 at min EL1: BP_OBJC_CTL_EL1
-	REG_SP_GL11_GL21               =63366 /* 63366 */,  // S3_6_c15_c0_6 at min EL1: SP_GL11_GL21
+	REG_SP_GL11                    =63366 /* 63366 */,  // S3_6_c15_c0_6 at min EL1: SP_GL11
 	REG_MMU_SESR_EL2               =63367 /* 63367 */,  // S3_6_c15_c0_7 at min EL2: MMU_SESR_EL2
-	REG_SPRR_CONFIG_EL21           =63368 /* 63368 */,  // S3_6_c15_c1_0 at min EL1: SPRR_CONFIG_EL21
+	REG_SPRR_CONFIG_EL1            =63368 /* 63368 */,  // S3_6_c15_c1_0 at min EL1: SPRR_CONFIG_EL1
 	REG_HPFAR_GL2                  =63369 /* 63369 */,  // S3_6_c15_c1_1 at min EL2: HPFAR_GL2
-	REG_GXF_CONFIG_EL21            =63370 /* 63370 */,  // S3_6_c15_c1_2 at min EL1: GXF_CONFIG_EL21
-	REG_SPRR_AMRANGE_EL1           =63371 /* 63371 */,  // S3_6_c15_c1_3 at min EL1: SPRR_AMRANGE_EL1
+	REG_GXF_CONFIG_EL1             =63370 /* 63370 */,  // S3_6_c15_c1_2 at min EL1: GXF_CONFIG_EL1
+	REG_AMRANGE_EL21               =63371 /* 63371 */,  // S3_6_c15_c1_3 at min EL1: AMRANGE_EL21
 	REG_GXF_CONFIG_EL2             =63372 /* 63372 */,  // S3_6_c15_c1_4 at min EL2: GXF_CONFIG_EL2
-	REG_SPRR_UPERM_EL02            =63373 /* 63373 */,  // S3_6_c15_c1_5 at min EL1: SPRR_UPERM_EL02
-	REG_SPRR_PPERM_EL21            =63374 /* 63374 */,  // S3_6_c15_c1_6 at min EL1: SPRR_PPERM_EL21
+	REG_SPRR_UPERM_EL0             =63373 /* 63373 */,  // S3_6_c15_c1_5 at min EL1: SPRR_UPERM_EL0
+	REG_SPRR_PPERM_EL1             =63374 /* 63374 */,  // S3_6_c15_c1_6 at min EL1: SPRR_PPERM_EL1
 	REG_SPRR_PPERM_EL2             =63375 /* 63375 */,  // S3_6_c15_c1_7 at min EL2: SPRR_PPERM_EL2
 	REG_APGAKEYLO_EL12             =63377 /* 63377 */,  // S3_6_c15_c2_1 at min EL2: APGAKeyLo_EL12
 	REG_APGAKEYHI_EL12             =63378 /* 63378 */,  // S3_6_c15_c2_2 at min EL2: APGAKeyHi_EL12
@@ -1366,23 +1326,23 @@ enum SystemReg {
 	REG_AFPCR_EL0                  =63381 /* 63381 */,  // S3_6_c15_c2_5 at min EL1: AFPCR_EL0
 	REG_SP_GL22                    =63382 /* 63382 */,  // S3_6_c15_c2_6 at min EL2: SP_GL22
 	REG_AMXIDR_EL1                 =63383 /* 63383 */,  // S3_6_c15_c2_7 at min EL1: AMXIDR_EL1
-	REG_SPRR_UMPRR_EL1             =63384 /* 63384 */,  // S3_6_c15_c3_0 at min EL1: SPRR_UMPRR_EL1
-	REG_SPRR_PMPRR_EL21            =63385 /* 63385 */,  // S3_6_c15_c3_1 at min EL1: SPRR_PMPRR_EL21
+	REG_SPRR_HUMPRR_EL21           =63384 /* 63384 */,  // S3_6_c15_c3_0 at min EL1: SPRR_HUMPRR_EL21
+	REG_SPRR_PMPRR_EL1             =63385 /* 63385 */,  // S3_6_c15_c3_1 at min EL1: SPRR_PMPRR_EL1
 	REG_SPRR_PMPRR_EL2             =63386 /* 63386 */,  // S3_6_c15_c3_2 at min EL2: SPRR_PMPRR_EL2
-	REG_SPRR_UPERM_SH01_EL1        =63387 /* 63387 */,  // S3_6_c15_c3_3 at min EL1: SPRR_UPERM_SH01_EL1
-	REG_SPRR_UPERM_SH02_EL1        =63388 /* 63388 */,  // S3_6_c15_c3_4 at min EL1: SPRR_UPERM_SH02_EL1
-	REG_SPRR_UPERM_SH03_EL1        =63389 /* 63389 */,  // S3_6_c15_c3_5 at min EL1: SPRR_UPERM_SH03_EL1
-	REG_SPRR_UPERM_SH04_EL1        =63390 /* 63390 */,  // S3_6_c15_c3_6 at min EL1: SPRR_UPERM_SH04_EL1
-	REG_SPRR_UPERM_SH05_EL1        =63391 /* 63391 */,  // S3_6_c15_c3_7 at min EL1: SPRR_UPERM_SH05_EL1
-	REG_SPRR_UPERM_SH06_EL1        =63392 /* 63392 */,  // S3_6_c15_c4_0 at min EL1: SPRR_UPERM_SH06_EL1
-	REG_SPRR_UPERM_SH07_EL1        =63393 /* 63393 */,  // S3_6_c15_c4_1 at min EL1: SPRR_UPERM_SH07_EL1
-	REG_SPRR_PPERM_SH01_EL21       =63394 /* 63394 */,  // S3_6_c15_c4_2 at min EL1: SPRR_PPERM_SH01_EL21
-	REG_SPRR_PPERM_SH02_EL21       =63395 /* 63395 */,  // S3_6_c15_c4_3 at min EL1: SPRR_PPERM_SH02_EL21
-	REG_SPRR_PPERM_SH03_EL21       =63396 /* 63396 */,  // S3_6_c15_c4_4 at min EL1: SPRR_PPERM_SH03_EL21
-	REG_SPRR_PPERM_SH04_EL21       =63397 /* 63397 */,  // S3_6_c15_c4_5 at min EL1: SPRR_PPERM_SH04_EL21
-	REG_SPRR_PPERM_SH05_EL21       =63398 /* 63398 */,  // S3_6_c15_c4_6 at min EL1: SPRR_PPERM_SH05_EL21
-	REG_SPRR_PPERM_SH06_EL21       =63399 /* 63399 */,  // S3_6_c15_c4_7 at min EL1: SPRR_PPERM_SH06_EL21
-	REG_SPRR_PPERM_SH07_EL21       =63400 /* 63400 */,  // S3_6_c15_c5_0 at min EL1: SPRR_PPERM_SH07_EL21
+	REG_SPRR_HUPERM_SH01_EL21      =63387 /* 63387 */,  // S3_6_c15_c3_3 at min EL1: SPRR_HUPERM_SH01_EL21
+	REG_SPRR_HUPERM_SH02_EL21      =63388 /* 63388 */,  // S3_6_c15_c3_4 at min EL1: SPRR_HUPERM_SH02_EL21
+	REG_SPRR_HUPERM_SH03_EL21      =63389 /* 63389 */,  // S3_6_c15_c3_5 at min EL1: SPRR_HUPERM_SH03_EL21
+	REG_SPRR_HUPERM_SH04_EL21      =63390 /* 63390 */,  // S3_6_c15_c3_6 at min EL1: SPRR_HUPERM_SH04_EL21
+	REG_SPRR_HUPERM_SH05_EL21      =63391 /* 63391 */,  // S3_6_c15_c3_7 at min EL1: SPRR_HUPERM_SH05_EL21
+	REG_SPRR_HUPERM_SH06_EL21      =63392 /* 63392 */,  // S3_6_c15_c4_0 at min EL1: SPRR_HUPERM_SH06_EL21
+	REG_SPRR_HUPERM_SH07_EL21      =63393 /* 63393 */,  // S3_6_c15_c4_1 at min EL1: SPRR_HUPERM_SH07_EL21
+	REG_SPRR_PPERM_SH01_EL1        =63394 /* 63394 */,  // S3_6_c15_c4_2 at min EL1: SPRR_PPERM_SH01_EL1
+	REG_SPRR_PPERM_SH02_EL1        =63395 /* 63395 */,  // S3_6_c15_c4_3 at min EL1: SPRR_PPERM_SH02_EL1
+	REG_SPRR_PPERM_SH03_EL1        =63396 /* 63396 */,  // S3_6_c15_c4_4 at min EL1: SPRR_PPERM_SH03_EL1
+	REG_SPRR_PPERM_SH04_EL1        =63397 /* 63397 */,  // S3_6_c15_c4_5 at min EL1: SPRR_PPERM_SH04_EL1
+	REG_SPRR_PPERM_SH05_EL1        =63398 /* 63398 */,  // S3_6_c15_c4_6 at min EL1: SPRR_PPERM_SH05_EL1
+	REG_SPRR_PPERM_SH06_EL1        =63399 /* 63399 */,  // S3_6_c15_c4_7 at min EL1: SPRR_PPERM_SH06_EL1
+	REG_SPRR_PPERM_SH07_EL1        =63400 /* 63400 */,  // S3_6_c15_c5_0 at min EL1: SPRR_PPERM_SH07_EL1
 	REG_SPRR_PPERM_SH01_EL2        =63401 /* 63401 */,  // S3_6_c15_c5_1 at min EL2: SPRR_PPERM_SH01_EL2
 	REG_SPRR_PPERM_SH02_EL2        =63402 /* 63402 */,  // S3_6_c15_c5_2 at min EL2: SPRR_PPERM_SH02_EL2
 	REG_SPRR_PPERM_SH03_EL2        =63403 /* 63403 */,  // S3_6_c15_c5_3 at min EL2: SPRR_PPERM_SH03_EL2
@@ -1407,13 +1367,13 @@ enum SystemReg {
 	REG_APDBKEYLO_EL12             =63422 /* 63422 */,  // S3_6_c15_c7_6 at min EL2: APDBKeyLo_EL12
 	REG_APDBKEYHI_EL12             =63423 /* 63423 */,  // S3_6_c15_c7_7 at min EL2: APDBKeyHi_EL12
 	REG_CURRENTG                   =63424 /* 63424 */,  // S3_6_c15_c8_0 at min EL1: CurrentG
-	REG_GXF_ENTRY_EL21             =63425 /* 63425 */,  // S3_6_c15_c8_1 at min EL1: GXF_ENTRY_EL21
-	REG_GXF_PABENTRY_EL21          =63426 /* 63426 */,  // S3_6_c15_c8_2 at min EL1: GXF_PABENTRY_EL21
-	REG_ASPSR_EL21                 =63427 /* 63427 */,  // S3_6_c15_c8_3 at min EL1: ASPSR_EL21
+	REG_GXF_ENTRY_EL1              =63425 /* 63425 */,  // S3_6_c15_c8_1 at min EL1: GXF_ENTRY_EL1
+	REG_GXF_PABENTRY_EL1           =63426 /* 63426 */,  // S3_6_c15_c8_2 at min EL1: GXF_PABENTRY_EL1
+	REG_ASPSR_EL1                  =63427 /* 63427 */,  // S3_6_c15_c8_3 at min EL1: ASPSR_EL1
 	REG_ADSPSR_EL0                 =63428 /* 63428 */,  // S3_6_c15_c8_4 at min EL1: ADSPSR_EL0
 	REG_PMCR1_GL2                  =63429 /* 63429 */,  // S3_6_c15_c8_5 at min EL2: PMCR1_GL2
-	REG_ASPSR_NV_EL21              =63430 /* 63430 */,  // S3_6_c15_c8_6 at min EL1: ASPSR_NV_EL21
-	REG_PMCR1_GL21                 =63431 /* 63431 */,  // S3_6_c15_c8_7 at min EL1: PMCR1_GL21
+	REG_ASPSR_EL2                  =63430 /* 63430 */,  // S3_6_c15_c8_6 at min EL2: ASPSR_EL2
+	REG_PMCR1_GL1                  =63431 /* 63431 */,  // S3_6_c15_c8_7 at min EL1: PMCR1_GL1
 	REG_VBAR_GL12                  =63434 /* 63434 */,  // S3_6_c15_c9_2 at min EL2: VBAR_GL12
 	REG_SPSR_GL12                  =63435 /* 63435 */,  // S3_6_c15_c9_3 at min EL2: SPSR_GL12
 	REG_ASPSR_GL12                 =63436 /* 63436 */,  // S3_6_c15_c9_4 at min EL2: ASPSR_GL12
@@ -1422,12 +1382,12 @@ enum SystemReg {
 	REG_FAR_GL12                   =63439 /* 63439 */,  // S3_6_c15_c9_7 at min EL2: FAR_GL12
 	REG_SP_GL1                     =63440 /* 63440 */,  // S3_6_c15_c10_0 at min EL1: SP_GL1
 	REG_TPIDR_GL1                  =63441 /* 63441 */,  // S3_6_c15_c10_1 at min EL1: TPIDR_GL1
-	REG_VBAR_GL21                  =63442 /* 63442 */,  // S3_6_c15_c10_2 at min EL1: VBAR_GL21
-	REG_SPSR_GL21                  =63443 /* 63443 */,  // S3_6_c15_c10_3 at min EL1: SPSR_GL21
-	REG_ASPSR_GL21                 =63444 /* 63444 */,  // S3_6_c15_c10_4 at min EL1: ASPSR_GL21
-	REG_ESR_GL21                   =63445 /* 63445 */,  // S3_6_c15_c10_5 at min EL1: ESR_GL21
-	REG_ELR_GL21                   =63446 /* 63446 */,  // S3_6_c15_c10_6 at min EL1: ELR_GL21
-	REG_FAR_GL21                   =63447 /* 63447 */,  // S3_6_c15_c10_7 at min EL1: FAR_GL21
+	REG_VBAR_GL1                   =63442 /* 63442 */,  // S3_6_c15_c10_2 at min EL1: VBAR_GL1
+	REG_SPSR_GL1                   =63443 /* 63443 */,  // S3_6_c15_c10_3 at min EL1: SPSR_GL1
+	REG_ASPSR_GL1                  =63444 /* 63444 */,  // S3_6_c15_c10_4 at min EL1: ASPSR_GL1
+	REG_ESR_GL1                    =63445 /* 63445 */,  // S3_6_c15_c10_5 at min EL1: ESR_GL1
+	REG_ELR_GL1                    =63446 /* 63446 */,  // S3_6_c15_c10_6 at min EL1: ELR_GL1
+	REG_FAR_GL1                    =63447 /* 63447 */,  // S3_6_c15_c10_7 at min EL1: FAR_GL1
 	REG_SP_GL2                     =63448 /* 63448 */,  // S3_6_c15_c11_0 at min EL2: SP_GL2
 	REG_TPIDR_GL2                  =63449 /* 63449 */,  // S3_6_c15_c11_1 at min EL2: TPIDR_GL2
 	REG_VBAR_GL2                   =63450 /* 63450 */,  // S3_6_c15_c11_2 at min EL2: VBAR_GL2
@@ -1440,20 +1400,20 @@ enum SystemReg {
 	REG_GXF_PABENTRY_EL2           =63457 /* 63457 */,  // S3_6_c15_c12_1 at min EL2: GXF_PABENTRY_EL2
 	REG_APCTL_EL2                  =63458 /* 63458 */,  // S3_6_c15_c12_2 at min EL2: APCTL_EL2
 	REG_APSTS_EL2                  =63459 /* 63459 */,  // S3_6_c15_c12_3 at min EL2: APSTS_EL2
-	REG_APSTS_NV1_EL1              =63460 /* 63460 */,  // S3_6_c15_c12_4 at min EL1: APSTS_NV1_EL1
-	REG_KERNKEYLO_NV_EL21          =63461 /* 63461 */,  // S3_6_c15_c12_5 at min EL1: KERNKEYLo_NV_EL21
-	REG_KERNKEYHI_NV_EL21          =63462 /* 63462 */,  // S3_6_c15_c12_6 at min EL1: KERNKEYHi_NV_EL21
+	REG_APSTS_EL1                  =63460 /* 63460 */,  // S3_6_c15_c12_4 at min EL1: APSTS_EL1
+	REG_KERNKEYLO_EL2              =63461 /* 63461 */,  // S3_6_c15_c12_5 at min EL2: KERNKEYLo_EL2
+	REG_KERNKEYHI_EL2              =63462 /* 63462 */,  // S3_6_c15_c12_6 at min EL2: KERNKEYHi_EL2
 	REG_ASPSR_EL12                 =63463 /* 63463 */,  // S3_6_c15_c12_7 at min EL2: ASPSR_EL12
-	REG_APIAKEYLO_NV_EL21          =63464 /* 63464 */,  // S3_6_c15_c13_0 at min EL1: APIAKeyLo_NV_EL21
-	REG_APIAKEYHI_NV_EL21          =63465 /* 63465 */,  // S3_6_c15_c13_1 at min EL1: APIAKeyHi_NV_EL21
-	REG_APIBKEYLO_NV_EL21          =63466 /* 63466 */,  // S3_6_c15_c13_2 at min EL1: APIBKeyLo_NV_EL21
-	REG_APIBKEYHI_NV_EL21          =63467 /* 63467 */,  // S3_6_c15_c13_3 at min EL1: APIBKeyHi_NV_EL21
-	REG_APDAKEYLO_NV_EL21          =63468 /* 63468 */,  // S3_6_c15_c13_4 at min EL1: APDAKeyLo_NV_EL21
-	REG_APDAKEYHI_NV_EL21          =63469 /* 63469 */,  // S3_6_c15_c13_5 at min EL1: APDAKeyHi_NV_EL21
-	REG_APDBKEYLO_NV_EL21          =63470 /* 63470 */,  // S3_6_c15_c13_6 at min EL1: APDBKeyLo_NV_EL21
-	REG_APDBKEYHI_NV_EL21          =63471 /* 63471 */,  // S3_6_c15_c13_7 at min EL1: APDBKeyHi_NV_EL21
-	REG_APGAKEYLO_NV_EL21          =63472 /* 63472 */,  // S3_6_c15_c14_0 at min EL1: APGAKeyLo_NV_EL21
-	REG_APGAKEYHI_NV_EL21          =63473 /* 63473 */,  // S3_6_c15_c14_1 at min EL1: APGAKeyHi_NV_EL21
+	REG_APIAKEYLO_EL2              =63464 /* 63464 */,  // S3_6_c15_c13_0 at min EL2: APIAKeyLo_EL2
+	REG_APIAKEYHI_EL2              =63465 /* 63465 */,  // S3_6_c15_c13_1 at min EL2: APIAKeyHi_EL2
+	REG_APIBKEYLO_EL2              =63466 /* 63466 */,  // S3_6_c15_c13_2 at min EL2: APIBKeyLo_EL2
+	REG_APIBKEYHI_EL2              =63467 /* 63467 */,  // S3_6_c15_c13_3 at min EL2: APIBKeyHi_EL2
+	REG_APDAKEYLO_EL2              =63468 /* 63468 */,  // S3_6_c15_c13_4 at min EL2: APDAKeyLo_EL2
+	REG_APDAKEYHI_EL2              =63469 /* 63469 */,  // S3_6_c15_c13_5 at min EL2: APDAKeyHi_EL2
+	REG_APDBKEYLO_EL2              =63470 /* 63470 */,  // S3_6_c15_c13_6 at min EL2: APDBKeyLo_EL2
+	REG_APDBKEYHI_EL2              =63471 /* 63471 */,  // S3_6_c15_c13_7 at min EL2: APDBKeyHi_EL2
+	REG_APGAKEYLO_EL2              =63472 /* 63472 */,  // S3_6_c15_c14_0 at min EL2: APGAKeyLo_EL2
+	REG_APGAKEYHI_EL2              =63473 /* 63473 */,  // S3_6_c15_c14_1 at min EL2: APGAKeyHi_EL2
 	REG_SPRR_CONFIG_EL2            =63474 /* 63474 */,  // S3_6_c15_c14_2 at min EL2: SPRR_CONFIG_EL2
 	REG_SPRR_AMRANGE_EL2           =63475 /* 63475 */,  // S3_6_c15_c14_3 at min EL2: SPRR_AMRANGE_EL2
 	REG_VMKEYLO_EL2                =63476 /* 63476 */,  // S3_6_c15_c14_4 at min EL2: VMKEYLo_EL2
@@ -1551,6 +1511,7 @@ enum SystemReg {
 	REG_CPU_CNT_CTL7               =65531 /* 65531 */,  // S3_7_c15_c15_3 at min EL1: CPU_CNT_CTL7
 	SYSREG_END=65532
 };
+
 #ifdef __cplusplus
 extern "C" {
 #endif