diff options
| author | Mark Rowe <mark@vector35.com> | 2025-09-18 11:46:39 -0700 |
|---|---|---|
| committer | Mark Rowe <mark@vector35.com> | 2025-09-25 08:41:48 -0700 |
| commit | 6e1306923c60b3d6c1cefb1fcc240f1a064d6f20 (patch) | |
| tree | 57fb65f74fecfa95dd394ecc5b664512d8f87609 /arch/arm64/disassembler/sysregs_gen.h | |
| parent | 0deeb4a61749737b98f7946ec88b693068180e28 (diff) | |
[AArch64] Update disassembler based on 2025-06 ARM ISA data
Alongside this I also added support for decoding:
* LDR / STR (table)
* PMULLB / PMULLT
* ABS / CNT / CTZ
* SMIN / SMAX / UMIN / UMAX
* RPRFM
* PSEL
Note that while these instructions will now be disassembled, they are
not yet lifted to LLIL.
Additionally, I fixed a number of errors in the decoding of some less
commonly occurring instructions.
Diffstat (limited to 'arch/arm64/disassembler/sysregs_gen.h')
| -rw-r--r-- | arch/arm64/disassembler/sysregs_gen.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/disassembler/sysregs_gen.h b/arch/arm64/disassembler/sysregs_gen.h index 54978f45..e971d317 100644 --- a/arch/arm64/disassembler/sysregs_gen.h +++ b/arch/arm64/disassembler/sysregs_gen.h @@ -3,7 +3,7 @@ #include <stdbool.h> -enum SystemReg +enum SystemReg { SYSREG_NONE=0, REG_EDSCR =4 /* 4 */, // S0_0_c0_c0_4 at min EL0: EDSCR |