Fix many of the warnings that show up when compiling with GCC 15.2

4 files changed, 51 insertions, 57 deletions

diff --git a/arch/arm64/disassembler/decode_scratchpad.c b/arch/arm64/disassembler/decode_scratchpad.c
index f869889f..d1160980 100644
--- a/arch/arm64/disassembler/decode_scratchpad.c
+++ b/arch/arm64/disassembler/decode_scratchpad.c
@@ -1086,9 +1086,12 @@ static const char* const reg_lookup_c[16] = {"c0", "c1", "c2", "c3", "c4", "c5",
 	i++;
 
 #define ADD_OPERAND_FLOAT32(VALUE) \
-	instr->operands[i].operandClass = FIMM32; \
-	*(float*)&(instr->operands[i].immediate) = VALUE; \
-	i++;
+	do { \
+		float value = VALUE; \
+		instr->operands[i].operandClass = FIMM32; \
+		memcpy(&instr->operands[i].immediate, &value, sizeof(float)); \
+		i++; \
+	} while (0)
 
 #define ADD_OPERAND_CONST  ADD_OPERAND_IMM64(const_, 0)
 #define ADD_OPERAND_FBITS  ADD_OPERAND_IMM32(fbits, 0)
diff --git a/arch/arm64/disassembler/format.c b/arch/arm64/disassembler/format.c
index 0db5ffbc..73f82a6f 100644
--- a/arch/arm64/disassembler/format.c
+++ b/arch/arm64/disassembler/format.c
@@ -383,7 +383,8 @@ uint32_t get_shifted_immediate(const InstructionOperand *instructionOperand, cha
 	}
 	if (type == FIMM32)
 	{
-		float f = *(const float*)&instructionOperand->immediate;
+		float f = 0.0f;
+		memcpy(&f, &instructionOperand->immediate, sizeof(float));
 		if (snprintf(outBuffer, outBufferSize, "#%.08f%s", f, shiftBuff) >= outBufferSize)
 			return FAILED_TO_DISASSEMBLE_OPERAND;
 	}
diff --git a/arch/arm64/disassembler/pcode.c b/arch/arm64/disassembler/pcode.c
index 7993e312..46ffdcec 100644
--- a/arch/arm64/disassembler/pcode.c
+++ b/arch/arm64/disassembler/pcode.c
@@ -584,37 +584,29 @@ uint64_t Replicate(uint64_t val, uint8_t times, uint64_t width)
   https://github.com/Siguza/iometa/blob/master/src/a64.c */
 uint64_t AdvSIMDExpandImm(uint8_t op, uint8_t cmode, uint64_t imm8)
 {
-	uint64_t imm64;
 	switch ((cmode >> 1) & 0b111)
 	{
 	case 0b000:
-		imm64 = Replicate(imm8, 2, 32);
-		break;
+		return Replicate(imm8, 2, 32);
 	case 0b001:
-		imm64 = Replicate(imm8 << 8, 2, 32);
-		break;
+		return Replicate(imm8 << 8, 2, 32);
 	case 0b010:
-		imm64 = Replicate(imm8 << 16, 2, 32);
-		break;
+		return Replicate(imm8 << 16, 2, 32);
 	case 0b011:
-		imm64 = Replicate(imm8 << 24, 2, 32);
-		break;
+		return Replicate(imm8 << 24, 2, 32);
 	case 0b100:
-		imm64 = Replicate(imm8, 4, 16);
-		break;
+		return Replicate(imm8, 4, 16);
 	case 0b101:
-		imm64 = Replicate(imm8 << 8, 4, 16);
-		break;
+		return Replicate(imm8 << 8, 4, 16);
 	case 0b110:
-		imm64 = Replicate(imm8 << (8 << (cmode & 0b1)), 2, 32);
-		break;
+		return Replicate(imm8 << (8 << (cmode & 0b1)), 2, 32);
 	case 0b111:
 		switch (((cmode & 0b1) << 1) | op)
 		{
 		case 0b00:
-			imm64 = Replicate(imm8, 8, 8);
-			break;
+			return Replicate(imm8, 8, 8);
 		case 0b01:
+		{
 #if 0
 					imm8a = Replicate((imm8 >> 7) & 0b1, 8, 1);
 					imm8b = Replicate((imm8 >> 6) & 0b1, 8, 1);
@@ -626,26 +618,24 @@ uint64_t AdvSIMDExpandImm(uint8_t op, uint8_t cmode, uint64_t imm8)
 					imm8h = Replicate((imm8	 ) & 0b1, 8, 1);
 					imm64 = (imm8a << 0x38) | (imm8b << 0x30) | (imm8c << 0x28) | (imm8d << 0x20) | (imm8e << 0x18) | (imm8f << 0x10) | (imm8g << 0x08) | imm8h;
 #else
-			imm64 = imm8 | (imm8 << (0x08 - 1)) | (imm8 << (0x10 - 2)) | (imm8 << (0x18 - 3)) |
+			uint64_t imm64 = imm8 | (imm8 << (0x08 - 1)) | (imm8 << (0x10 - 2)) | (imm8 << (0x18 - 3)) |
 			        (imm8 << (0x20 - 4)) | (imm8 << (0x28 - 5)) | (imm8 << (0x30 - 6)) |
 			        (imm8 << (0x38 - 7));
 			imm64 &= 0x0101010101010101;
-			imm64 = Replicate(imm64, 8, 1);
+			return Replicate(imm64, 8, 1);
 #endif
-			break;
+		}
 		case 0b10:
-			imm64 = Replicate((((imm8 & 0xc0) ^ 0x80) << 24) |
+			return Replicate((((imm8 & 0xc0) ^ 0x80) << 24) |
 			                      (Replicate((imm8 >> 6) & 0b1, 5, 1) << 25) | ((imm8 & 0x3f) << 19),
 			    2, 32);
-			break;
 		case 0b11:
-			imm64 = (((imm8 & 0xc0) ^ 0x80) << 56) | (Replicate((imm8 >> 6) & 0b1, 8, 1) << 54) |
+			return (((imm8 & 0xc0) ^ 0x80) << 56) | (Replicate((imm8 >> 6) & 0b1, 8, 1) << 54) |
 			        ((imm8 & 0x3f) << 48);
-			break;
 		}
 		break;
 	}
-	return imm64;
+	return 0;
 }
 
 bool BTypeCompatible_BTI(uint8_t hintcode, uint8_t pstate_btype)
diff --git a/arch/arm64/il.cpp b/arch/arm64/il.cpp
index bbec5959..f02cdd2d 100644
--- a/arch/arm64/il.cpp
+++ b/arch/arm64/il.cpp
@@ -174,9 +174,9 @@ static ExprId GetFloat(LowLevelILFunction& il, InstructionOperand& operand, int
 		case 2:
 			return il.FloatConstRaw(2, operand.immediate);
 		case 4:
-			return il.FloatConstSingle(*(float*)&(operand.immediate));
+			return il.FloatConstSingle(std::bit_cast<float>(static_cast<uint32_t>(operand.immediate)));
 		case 8:
-			return il.FloatConstDouble(*(float*)&(operand.immediate));
+			return il.FloatConstDouble(std::bit_cast<double>(operand.immediate));
 		default:
 			break;
 		}
@@ -851,7 +851,7 @@ static void LoadStoreVector(
 		for (int i = 0; i < regs_n; ++i)
 		{
 			int reg_spec_base = (oper0.reg[0] + i - REG_V0) * (16 / arrspec_size) + lane;
-			Register reg;
+			Register reg = REG_NONE;
 			switch (arrspec_size)
 			{
 			case 1:
@@ -1343,7 +1343,7 @@ bool GetLowLevelILForInstruction(
 		case ENC_ADD_Z_ZZ_:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-				return true;
+			return true;
 		default: break;
 		}
 	case ARM64_ADDS:
@@ -1372,7 +1372,7 @@ bool GetLowLevelILForInstruction(
 		case ENC_ANDS_P_P_PP_Z:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-				return true;
+			return true;
 		default: break;
 		}
 		il.AddInstruction(
@@ -1387,7 +1387,7 @@ bool GetLowLevelILForInstruction(
 		case ENC_ADR_Z_AZ_D_U32_SCALED:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-					return true;
+			return true;
 		default: break;
 		}
 	case ARM64_ADRP:
@@ -1403,7 +1403,7 @@ bool GetLowLevelILForInstruction(
 		case ENC_ASR_Z_ZW_:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-				return true;
+			return true;
 		default: break;
 		}
 		il.AddInstruction(ILSETREG_O(operand1, il.ArithShiftRight(REGSZ_O(operand2), ILREG_O(operand2),
@@ -1415,7 +1415,7 @@ bool GetLowLevelILForInstruction(
 		case ENC_AESD_Z_ZZ_:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-				return true;
+			return true;
 		default: break;
 		}
 		il.AddInstruction(il.Intrinsic({RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_AESD,
@@ -1427,8 +1427,8 @@ bool GetLowLevelILForInstruction(
 		case ENC_AESE_Z_ZZ_:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-					return true;
-			default: break;
+			return true;
+		default: break;
 		}
 		il.AddInstruction(il.Intrinsic({RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_AESE,
 		    {ILREG_O(operand1), ILREG_O(operand2)}));
@@ -1439,8 +1439,8 @@ bool GetLowLevelILForInstruction(
 		case ENC_AESIMC_Z_Z_:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-					return true;
-			default: break;
+			return true;
+		default: break;
 		}
 		il.AddInstruction(il.Intrinsic({RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_AESIMC,
 		    {ILREG_O(operand1), ILREG_O(operand2)}));
@@ -1451,8 +1451,8 @@ bool GetLowLevelILForInstruction(
 		case ENC_AESMC_Z_Z_:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-					return true;
-			default: break;
+			return true;
+		default: break;
 		}
 		il.AddInstruction(il.Intrinsic({RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_AESMC,
 		    {ILREG_O(operand1), ILREG_O(operand2)}));
@@ -1571,7 +1571,7 @@ bool GetLowLevelILForInstruction(
 		case ENC_BICS_P_P_PP_Z:
 			if (!preferIntrinsics())
 				il.AddInstruction(il.Unimplemented());
-				return true;
+			return true;
 		case ENC_BIC_ASIMDIMM_L_HL:
 		case ENC_BIC_ASIMDIMM_L_SL:
 			il.AddInstruction(ILSETREG_O(operand1,
@@ -2962,9 +2962,9 @@ bool GetLowLevelILForInstruction(
 		case ENC_NEG_ASIMDMISC_R:
 		case ENC_NEG_Z_P_Z_M:
 		case ENC_NEG_Z_P_Z_Z:
-		if (!preferIntrinsics())
-			il.AddInstruction(il.Unimplemented());
-				return true;
+			if (!preferIntrinsics())
+				il.AddInstruction(il.Unimplemented());
+			return true;
 		default: break;
 		}
 	case ARM64_NEGS:
@@ -3098,8 +3098,8 @@ bool GetLowLevelILForInstruction(
 		{
 		case ENC_ORN_Z_ZI__ORR_Z_ZI_:
 		case ENC_ORN_P_P_PP_Z:
-		if (!preferIntrinsics())
-				il.AddInstruction(il.Unimplemented());
+			if (!preferIntrinsics())
+					il.AddInstruction(il.Unimplemented());
 			return true;
 		default: break;
 		}
@@ -3588,11 +3588,11 @@ bool GetLowLevelILForInstruction(
 	case ARM64_STR:
 		switch (instr.encoding)
 		{
-	case ENC_STR_P_BI_:
-	case ENC_STR_Z_BI_:
-	case ENC_STR_ZA_RI_:
-		if (!preferIntrinsics())
-				il.AddInstruction(il.Unimplemented());
+		case ENC_STR_P_BI_:
+		case ENC_STR_Z_BI_:
+		case ENC_STR_ZA_RI_:
+			if (!preferIntrinsics())
+					il.AddInstruction(il.Unimplemented());
 			return true;
 		default: break;
 		}
@@ -3619,9 +3619,9 @@ bool GetLowLevelILForInstruction(
 		case ENC_SUB_Z_P_ZZ_:
 		case ENC_SUB_Z_ZI_:
 		case ENC_SUB_Z_ZZ_:
-		if (!preferIntrinsics())
-			il.AddInstruction(il.Unimplemented());
-				return true;
+			if (!preferIntrinsics())
+				il.AddInstruction(il.Unimplemented());
+			return true;
 		default: break;
 		}
 	case ARM64_SUBS: