diff options
| author | Josh Ferrell <josh@vector35.com> | 2025-03-06 11:01:48 -0500 |
|---|---|---|
| committer | Josh Ferrell <josh@vector35.com> | 2025-03-06 16:38:58 -0500 |
| commit | aaff6a6e366219c52a629729d741fff1711eeb7d (patch) | |
| tree | e5edf1fd76f470aead52851ba5a8c3ebb56eff3b /arch/armv7/test_lift.py | |
| parent | d59ee7f42ceb379dc107c6bca723b012b0c0e24a (diff) | |
ARMv7: update test_lift.py and test.py
Diffstat (limited to 'arch/armv7/test_lift.py')
| -rwxr-xr-x | arch/armv7/test_lift.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/armv7/test_lift.py b/arch/armv7/test_lift.py index 96a6f4d9..a3906fc6 100755 --- a/arch/armv7/test_lift.py +++ b/arch/armv7/test_lift.py @@ -124,7 +124,7 @@ test_cases = \ # just r0 = r1 >> 20, no left shift required ('T', b'\x41\xf3\x1d\x50', 'LLIL_SET_REG.d(r0,LLIL_ASR.d(LLIL_REG.d(r1),LLIL_CONST.b(0x14)))'), # rev r1, r1 - ('T', b'\x09\xba', 'LLIL_SET_REG.d(r1,LLIL_OR.d(LLIL_LSR.d(LLIL_REG.d(r1),LLIL_CONST.d(0x18)),LLIL_OR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_LSR.d(LLIL_REG.d(r1),LLIL_CONST.d(0x10)),LLIL_CONST.d(0xFF)),LLIL_CONST.d(0x8)),LLIL_OR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_LSR.d(LLIL_REG.d(r1),LLIL_CONST.d(0x8)),LLIL_CONST.d(0xFF)),LLIL_CONST.d(0x10)),LLIL_LSL.d(LLIL_AND.d(LLIL_REG.d(r1),LLIL_CONST.d(0xFF)),LLIL_CONST.d(0x18))))))'), + ('T', b'\x09\xba', 'LLIL_SET_REG.d(r1,LLIL_OR.d(LLIL_LSR.d(LLIL_REG.d(r1),LLIL_CONST.d(0x18)),LLIL_OR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_LSR.d(LLIL_REG.d(r1),LLIL_CONST.d(0x10)),LLIL_CONST.d(0xFF)),LLIL_CONST.b(0x8)),LLIL_OR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_LSR.d(LLIL_REG.d(r1),LLIL_CONST.d(0x8)),LLIL_CONST.d(0xFF)),LLIL_CONST.b(0x10)),LLIL_LSL.d(LLIL_AND.d(LLIL_REG.d(r1),LLIL_CONST.d(0xFF)),LLIL_CONST.b(0x18))))))'), ] import re |