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| author | noone <you@example.com> | 2024-07-31 22:48:31 -0500 |
|---|---|---|
| committer | Alexander Taylor <alex@vector35.com> | 2024-08-12 15:50:55 -0400 |
| commit | c6623fa5f2682f506d2d399d1b12547a195565f7 (patch) | |
| tree | 3b32dfdadc29fbd870d0f98f472e70e20b7c712a /arch/mips/il.cpp | |
| parent | 0b3adba96944076c8b1e4110f1698553bdfc265d (diff) | |
Add decode, disassembly, IL for TLBINV, TLBINVF
Diffstat (limited to 'arch/mips/il.cpp')
| -rw-r--r-- | arch/mips/il.cpp | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/mips/il.cpp b/arch/mips/il.cpp index d5bc1421..f14a8d3c 100644 --- a/arch/mips/il.cpp +++ b/arch/mips/il.cpp @@ -1876,6 +1876,18 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu })); break; + case MIPS_TLBINV: + il.AddInstruction(il.Intrinsic({}, MIPS_INTRIN_TLBINV, { + il.Register(registerSize, REG_INDEX), + il.Register(registerSize, REG_ENTRY_HI) + })); + break; + + case MIPS_TLBINVF: + il.AddInstruction(il.Intrinsic({}, MIPS_INTRIN_TLBINVF, { + il.Register(registerSize, REG_INDEX), + })); + break; case CNMIPS_BADDU: il.AddInstruction(SetRegisterOrNop(il, 8, registerSize, op1.reg, |