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authorMason Reed <mason@vector35.com>2025-04-30 17:38:40 -0400
committerMason Reed <35282038+emesare@users.noreply.github.com>2025-05-12 17:45:24 -0400
commitc3fdda9727f5507818e3f55576ad32215a22b0f9 (patch)
treed522025055eb7253c7f2cb94732402aacf2afbfc /arch/riscv/disasm/src
parentc3f344a38ca4b027b4e69b0f82d3184622d6da79 (diff)
[Rust] Remove Architecture trait bound on LLIL related structures
Diffstat (limited to 'arch/riscv/disasm/src')
-rw-r--r--arch/riscv/disasm/src/lib.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/disasm/src/lib.rs b/arch/riscv/disasm/src/lib.rs
index 959952ee..152817c6 100644
--- a/arch/riscv/disasm/src/lib.rs
+++ b/arch/riscv/disasm/src/lib.rs
@@ -2331,7 +2331,7 @@ impl StandardExtension for ExtensionSupported {
}
}
-pub trait RiscVDisassembler: 'static + Debug + Sized + Copy + Clone + Send + Sync {
+pub trait RiscVDisassembler: 'static + Debug + Sized + Copy + Clone + Send + Sync {
type RegFile: RegFile;
type MulDivExtension: StandardExtension;
type AtomicExtension: StandardExtension;