diff options
| author | Galen Williamson <galen@vector35.com> | 2025-08-06 19:22:13 -0400 |
|---|---|---|
| committer | Galen Williamson <galen@vector35.com> | 2025-08-14 14:06:49 -0400 |
| commit | 193450bcf90800753aec316322ee651c5520ea57 (patch) | |
| tree | fef4afd867ada17bb774db20c7d292df14c09df9 /arch | |
| parent | 408894062e4ff6b7271d7eaaf877d59be1712c74 (diff) | |
[armv7] Add lifting for VCVT floating-point scalar variants
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/armv7/il.cpp | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/arch/armv7/il.cpp b/arch/armv7/il.cpp index de53689b..73cf9a9a 100644 --- a/arch/armv7/il.cpp +++ b/arch/armv7/il.cpp @@ -4936,18 +4936,31 @@ bool GetLowLevelILForArmInstruction(Architecture* arch, uint64_t addr, LowLevelI case ARMV7_VCVT: switch (instr.dataType) { + // To integer cases case DT_S32: case DT_U32: switch (instr.dataType2) { case DT_F32: case DT_F64: - // ConditionExecute(il, instr.cond, - // il.SetRegister(get_register_size(op1.reg), op1.reg, - // il.FloatToInt(4, il.Register(get_register_size(op2.reg), op2.reg)))); - ConditionExecute(il, instr.cond, - il.SetRegister(get_register_size(op1.reg), op1.reg, - il.FloatToInt(get_register_size(op1.reg), il.Register(get_register_size(op2.reg), op2.reg)))); + ConditionExecute(il, instr.cond, il.SetRegister(get_register_size(op1.reg), op1.reg, + il.FloatToInt(get_register_size(op1.reg), il.RoundToInt(get_register_size(op2.reg), + il.Register(get_register_size(op2.reg), op2.reg))))); + break; + default: + break; + } + break; + // To float from integer cases + case DT_F32: + case DT_F64: + switch (instr.dataType2) + { + case DT_S32: + case DT_U32: + ConditionExecute(il, instr.cond, il.SetRegister(get_register_size(op1.reg), op1.reg, + il.IntToFloat(get_register_size(op1.reg), + il.Register(get_register_size(op2.reg), op2.reg)))); break; default: break; |