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authorRusty Wagner <rusty@vector35.com>2018-01-31 20:24:16 -0500
committerRusty Wagner <rusty@vector35.com>2018-01-31 20:24:16 -0500
commit2f3873928078e8c21911ffeb5476781b31886514 (patch)
tree41251ecf52ab82da3d9cf312850a4898df276a96 /lowlevelil.cpp
parent1228e32e300d62f5d76438e4500965d76edeca69 (diff)
Adding CPU intrinsics support
Diffstat (limited to 'lowlevelil.cpp')
-rw-r--r--lowlevelil.cpp25
1 files changed, 25 insertions, 0 deletions
diff --git a/lowlevelil.cpp b/lowlevelil.cpp
index c72d4b68..0f2b29be 100644
--- a/lowlevelil.cpp
+++ b/lowlevelil.cpp
@@ -216,6 +216,17 @@ ExprId LowLevelILFunction::AddIndexList(const vector<size_t> operands)
}
+ExprId LowLevelILFunction::AddRegisterOrFlagList(const vector<RegisterOrFlag>& regs)
+{
+ uint64_t* operandList = new uint64_t[regs.size()];
+ for (size_t i = 0; i < regs.size(); i++)
+ operandList[i] = regs[i].ToIdentifier();
+ ExprId result = (ExprId)BNLowLevelILAddOperandList(m_object, operandList, regs.size());
+ delete[] operandList;
+ return result;
+}
+
+
ExprId LowLevelILFunction::AddSSARegisterList(const vector<SSARegister>& regs)
{
uint64_t* operandList = new uint64_t[regs.size() * 2];
@@ -258,6 +269,20 @@ ExprId LowLevelILFunction::AddSSAFlagList(const vector<SSAFlag>& flags)
}
+ExprId LowLevelILFunction::AddSSARegisterOrFlagList(const vector<SSARegisterOrFlag>& regs)
+{
+ uint64_t* operandList = new uint64_t[regs.size() * 2];
+ for (size_t i = 0; i < regs.size(); i++)
+ {
+ operandList[i * 2] = regs[i].regOrFlag.ToIdentifier();
+ operandList[(i * 2) + 1] = regs[i].version;
+ }
+ ExprId result = (ExprId)BNLowLevelILAddOperandList(m_object, operandList, regs.size() * 2);
+ delete[] operandList;
+ return result;
+}
+
+
ExprId LowLevelILFunction::GetExprForRegisterOrConstant(const BNRegisterOrConstant& operand, size_t size)
{
if (operand.constant)