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| author | KyleMiles <krm504@nyu.edu> | 2023-06-01 17:36:20 -0400 |
|---|---|---|
| committer | Kyle Martin <krm504@nyu.edu> | 2023-06-02 10:03:01 -0400 |
| commit | 7b816fc2e285aa9cd77fba33bc55afa16947095f (patch) | |
| tree | a4783d7e1603c390d398a323342da97be6af47dd /python/commonil.py | |
| parent | b46e2e19c3a840e8e110f0b768efc73add56c33f (diff) | |
Add Var, SSAVar, and AliasedVar to commonil.py, and update the relavent MLIL/HLIL instrutctions
Diffstat (limited to 'python/commonil.py')
| -rw-r--r-- | python/commonil.py | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/python/commonil.py b/python/commonil.py index f84da073..288db8d9 100644 --- a/python/commonil.py +++ b/python/commonil.py @@ -189,3 +189,18 @@ class SetReg: @dataclass(frozen=True, repr=False, eq=False) class Intrinsic(BaseILInstruction): pass + + +@dataclass(frozen=True, repr=False, eq=False) +class VariableInstruction(BaseILInstruction): + pass + + +@dataclass(frozen=True, repr=False, eq=False) +class SSAVariableInstruction(SSA, VariableInstruction): + pass + + +@dataclass(frozen=True, repr=False, eq=False) +class AliasedVariableInstruction(VariableInstruction): + pass |