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-rw-r--r--arch/riscv/disasm/src/lib.rs5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/riscv/disasm/src/lib.rs b/arch/riscv/disasm/src/lib.rs
index a25516a6..959952ee 100644
--- a/arch/riscv/disasm/src/lib.rs
+++ b/arch/riscv/disasm/src/lib.rs
@@ -291,7 +291,7 @@ impl FloatRegType for () {}
impl FloatRegType for f32 {}
impl FloatRegType for f64 {}
-pub trait RegFile: Debug + Sized + Copy + Clone {
+pub trait RegFile: Debug + Sized + Copy + Clone + Send + Sync + 'static {
type Int: IntRegType;
type Float: FloatRegType;
@@ -2331,7 +2331,7 @@ impl StandardExtension for ExtensionSupported {
}
}
-pub trait RiscVDisassembler: Debug + Sized + Copy + Clone {
+pub trait RiscVDisassembler: 'static + Debug + Sized + Copy + Clone + Send + Sync {
type RegFile: RegFile;
type MulDivExtension: StandardExtension;
type AtomicExtension: StandardExtension;
@@ -3175,6 +3175,7 @@ pub trait RiscVDisassembler: Debug + Sized + Copy + Clone {
#[derive(Copy, Clone, Debug)]
pub struct RiscVIMACDisassembler<RF: RegFile>(PhantomData<RF>);
+
impl<RF: RegFile> RiscVDisassembler for RiscVIMACDisassembler<RF> {
type RegFile = RF;
type MulDivExtension = ExtensionSupported;