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2025-08-05[ARM64] Fix lifting of mrs xzr, ... to not reference the xzr registerMark Rowe
ARM64 lifting replaces references to the zero register with constant zeroes. The zero register is not intended to appear in any lifted IL. In the case of the `mrs` instruction, the destination being a zero register means the system register is accessed only for a side-effect, and is not stored anywhere. The lifting is updated to specify no output registers for the intrinsic in that case.
2025-07-30[CMake] Specify CONFIGURE_DEPENDS for all file(GLOB ..)Mark Rowe
This ensures that CMake detects when files that match the glob are added or removed.
2025-07-30[ARM64] Fix lifting of tbz / tbnz for bits >= 32Mark Rowe
2025-06-25Update CXX_STANDARD to 20.Alexander Taylor
Also update minimum CMake version.
2025-06-25Remove implicit conversions from Confidence to underlying type, these can ↵Rusty Wagner
cause bugs and also issues with C++20
2025-06-02ARM64 disassembler: fix MSVC compilationjustanotheranonymoususer
2025-05-28PR #6757: prefer fp, lr for x29, x30yrp
arm64: prefer fp, lr arm64: update tests to use new reg names, improve windows build
2025-05-28Revert "Fix compilation with MSVC: arm64/disassembler/decode_scratchpad.c"Galen Williamson
This reverts commit cb7c2d3bb716a2e96cf7f127bbf71992a4861907.
2025-05-27Update decode_scratchpad.cjustanotheranonymoususer
2025-05-27Fix compilation with MSVC: arm64/disassembler/decode_scratchpad.cjustanotheranonymoususer
MSVC shows several warnings, but this one is shown as an error, preventing compilation.
2025-05-13[CMake] Report compatibility with 3.15 to silence deprecation warningsGlenn Smith
2025-04-09[aarch64] add lifting for B.NV instruction, fix branch generation for B.AL ↵Galen Williamson
and B.NV, fix AlwaysBranch patching to generate a valid B instruction
2025-04-09[aarch64] add lifting for B.AL instructionGalen Williamson
2025-04-09Fix capitalization of AArch64.Alexander Taylor
2025-04-08[aarch64] remove "unknown hint" warningGalen Williamson
2025-04-08[aarch64] lift all LD[1-4]R? and ST[1-4] opcodes, lift ST/LDCLR, ST/LDEOR, ↵Galen Williamson
ST/LDSET, and their variants Also fixes all outstanding issues in arm64test.py, including intrinsics, dc, at, and tlbi
2025-04-01[aarch64] use static var to avoid recreation of sysregs vectorGalen Williamson
2025-03-31[aarch64] Updating Aarch64 system registers to 2024-12 spec, fix MSR/MRS ↵Galen Williamson
lifting to use ReadMSR/WriteMSR intrinsics that take enums, removing the sysregs from the register list of the architecture * sysregs are no longer registers, add enum for TLBI and AT operands * add erroneously missing cases for unsupported encodings, add enum for DC operands
2025-03-28belated copyright year updateJordan Wiens
2025-03-19Register relocation handlers for KCView typekat
2025-02-12bugfix: ARM64: missing break in il.cpp's switchMaxime Meignan
A `break` was missing in the switch, making the LDXRH instruction generate 2 IL instructions
2025-01-15[aarch64] fix size of immediate arguments in intrinsic callsGalen Williamson
2024-10-23Calling Conventions for register specific arc functionskat
2024-09-14Add mpidr_el1 aarch64 sysregJosh Ferrell
2024-09-13Fix many warningsJosh Ferrell
2024-09-13Ultimate.Alexander Taylor
2024-09-08Respect ELF view endianness when calculating AArch64 relocationsMichael Krasnitski
2024-08-06Add flag role for carry flag when subtraction is implemented with additionRusty Wagner
2024-07-09[arm64] cleaned up dangling else warnings and removed unneeded ENC_LDR_Q* ↵Galen Williamson
case from neon_intrinsics.cpp
2024-07-08[arm64] Full review of intrinsics; lifting of many instructions added, ↵Galen Williamson
improved, and/or fixed Merged https://github.com/Vector35/binaryninja-api/pull/5461: Author: yrp <yrp604@protonmail.com> Date: Sat May 25 21:00:26 2024 -0700 arm64: lift sxtl, sxtl2, sshll, sshll2 Partial list of detailed changes squashed into this commit (see https://github.com/Vector35/binaryninja-api/tree/arm64_improving_intrinsics for detailed commit history): * add lifting for sshll/sxtl * reverted neon_intrinsics.cpp to restore scvtf intrinsics * lifted sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and changed the lifting of uxtl/2 to be consistent with sxtl/2 * reformatted arm64test.py and added tests for sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and uxtl/2 fix scvtf (unroll because no intrinsic) and fsub (missing register assignment) half-precision vector cases * added preferIntrinsics setting to arm64 * added lifting for movn * fixed incorrect int/float conversions for FMOV, made half-precision immediates survive the lift to M/HLIL * fix missing break in SCVT; optimize MOVK * improved preferIntrinsics * fixed bad lifting introduced for movn * fixed bad settings definition for preferIntrinsics * added intrinsic definition for DUP from general register * added direct lifting of scalar version of FADDP, and fixed intrinsics for vector version * added direct lifting of scalar version of FABD, and fixed intrinsics for vector version * fixes to test_gen.py: gets the correct encoding instead of sometimes getting fooled by the mnemonic * fixed lifting of UCVTF; reviewed/fixed all intrinsics through SQXTUN * reviewed/fixed remaining intrinsics after SQXTUN * added lifting for FNMUL * WIP intrinsics improvements * WIP intrinsics improvements 2 * WIP intrinsics improvements: FCVT*_asisdmisc_R * added B.AL, B.NV, CASP* * direct lifting of scalar FSQRT instruction * SETREG now elides setting of targeting zero registers * fixed test_gen.py to correctly regenerate arm64test.py * unroll vector MOV operations, USHL no longer uses intrinsic for scalars * updated existing tests in arm64test.py for latest lifting changes * fixed CASH* and CASB* incorrectly accessing temp register in comparison (resulting in comparing to NOP) * lifting all variants of TBL as intrinsic * fixes/improvements to test_gen.py * lifting all variants of TBX as intrinsic * added tests for CAS*, UMUL*, UADD*, FABD, FABS, FADDP, FMAX, FMAXNM, FMIN, FMINNM, FNEG, FNMUL, FCMEQ, FCMGE, FCMGT, FMLA, FMLS * added tests for all aliases of SBFM
2024-06-13[arm64]: fix broken compilation on windowsGalen Williamson
no Elvis operator ?:( api\arch\arm64\il.cpp(894): error C2059: syntax error: ':' api\arch\arm64\il.cpp(1839): error C7555: use of designated initializers requires at least '/std:c++20'
2024-06-13[arm64] fixed lifting for LDADD*, filled in lifting for alias STADD*, fixed ↵Galen Williamson
tests for recently added system registers dczid_el0 and ctr_el0; fixes #5603
2024-06-13[arm64] fixes and improvements to test_gen.pyGalen Williamson
2024-06-11Add some missing arm64 system registersJosh Ferrell
2024-06-11Fix lifting of pair load operations when first and third operand are equal ↵Josh Ferrell
and reduce code duplication
2024-05-31improve efficiencyZichuan Li
2024-05-31Fixed type propagation issue in AARCH64 and MIPSZichuan Li
Previously, prtinf type library is not being appropriately applied. #3092
2024-05-30[arm64] lift scvtfGalen Williamson
* only scalar variants for integer and floating point * updated arm64test.py for scvtf * removed intrinsics for scvtf, scalar integer and floating point variants
2024-05-29improve lifting of arm64 CSET instruction per Vector35/binaryninja-api#5134Galen Williamson
2024-03-15Separate local variable tokens in higher level ILs from stack variable ↵Rusty Wagner
tokens in lower levels, and improve token usage in disassembly
2024-03-05Move architecture modules into the API repoRusty Wagner